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* Re: [PATCH v2 09/14] device core: Add ability to handle multiple dma offsets
From: Rob Herring @ 2020-05-29 17:34 UTC (permalink / raw)
  To: Jim Quinlan
  Cc: Nicolas Saenz Julienne,
	open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS,
	Christoph Hellwig, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
	Frank Rowand, Greg Kroah-Hartman, Marek Szyprowski, Robin Murphy,
	Alan Stern, Oliver Neukum, Rafael J. Wysocki, Andy Shevchenko,
	Wolfram Sang, Corey Minyard, Srinivas Kandagatla,
	Suzuki K Poulose, Saravana Kannan, Heikki Krogerus, Dan Williams,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE, open list,
	open list:USB SUBSYSTEM, open list:DMA MAPPING HELPERS
In-Reply-To: <CA+-6iNyOKvY-xNfXqDRa5_nJVJuqGKA-oe-ejNuJHUBt6ORu0A@mail.gmail.com>

On Wed, May 27, 2020 at 9:43 AM Jim Quinlan <james.quinlan@broadcom.com> wrote:
>
> Hi Nicolas,
>
> On Wed, May 27, 2020 at 11:00 AM Nicolas Saenz Julienne
> <nsaenzjulienne@suse.de> wrote:
> >
> > Hi Jim,
> > one thing comes to mind, there is a small test suite in drivers/of/unittest.c
> > (specifically of_unittest_pci_dma_ranges()) you could extend it to include your
> > use cases.
> Sure, will check out.
> >
> > On Tue, 2020-05-26 at 15:12 -0400, Jim Quinlan wrote:
> > > The new field in struct device 'dma_pfn_offset_map' is used to facilitate
> > > the use of multiple pfn offsets between cpu addrs and dma addrs.  It is
> > > similar to 'dma_pfn_offset' except that the offset chosen depends on the
> > > cpu or dma address involved.
> > >
> > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > > ---
> > >  drivers/of/address.c        | 65 +++++++++++++++++++++++++++++++++++--
> > >  drivers/usb/core/message.c  |  3 ++
> > >  drivers/usb/core/usb.c      |  3 ++
> > >  include/linux/device.h      | 10 +++++-
> > >  include/linux/dma-direct.h  | 10 ++++--
> > >  include/linux/dma-mapping.h | 46 ++++++++++++++++++++++++++
> > >  kernel/dma/Kconfig          | 13 ++++++++
> > >  7 files changed, 144 insertions(+), 6 deletions(-)
> > >
> >
> > [...]
> >
> > > @@ -977,10 +1020,19 @@ int of_dma_get_range(struct device *dev, struct
> > > device_node *np, u64 *dma_addr,
> > >               pr_debug("dma_addr(%llx) cpu_addr(%llx) size(%llx)\n",
> > >                        range.bus_addr, range.cpu_addr, range.size);
> > >
> > > +             num_ranges++;
> > >               if (dma_offset && range.cpu_addr - range.bus_addr != dma_offset)
> > > {
> > > -                     pr_warn("Can't handle multiple dma-ranges with different
> > > offsets on node(%pOF)\n", node);
> > > -                     /* Don't error out as we'd break some existing DTs */
> > > -                     continue;
> > > +                     if (!IS_ENABLED(CONFIG_DMA_PFN_OFFSET_MAP)) {
> > > +                             pr_warn("Can't handle multiple dma-ranges with
> > > different offsets on node(%pOF)\n", node);
> > > +                             pr_warn("Perhaps set DMA_PFN_OFFSET_MAP=y?\n");
> > > +                             /*
> > > +                              * Don't error out as we'd break some existing
> > > +                              * DTs that are using configs w/o
> > > +                              * CONFIG_DMA_PFN_OFFSET_MAP set.
> > > +                              */
> > > +                             continue;
> >
> > dev->bus_dma_limit is set in of_dma_configure(), this function's caller, based
> > on dma_start's value (set after this continue). So you'd be effectively setting
> > the dev->bus_dma_limit to whatever we get from the first dma-range.
> I'm not seeing that at all.  On the  evaluation of each dma-range,
> dma_start and dma_end are re-evaluated to be the lowest and highest
> bus values of the  dma-ranges seen so far.  After all dma-ranges are
> examined,  dev->bus_dma_limit being set to the highest.  In fact, the
> current code -- ie before my commits -- already does this for multiple
> dma-ranges as long as the cpu-bus offset is the same in the
> dma-ranges.
> >
> > This can be troublesome depending on how the dma-ranges are setup, for example
> > if the first dma-range doesn't include the CMA area, in arm64 generally set as
> > high as possible in ZONE_DMA32, that would render it useless for
> > dma/{direct/swiotlb}. Again depending on the bus_dma_limit value, if smaller
> > than ZONE_DMA you'd be unable to allocate any DMA memory.
> >
> > IMO, a solution to this calls for a revamp of dma-direct's dma_capable(): match
> > the target DMA memory area with each dma-range we have to see if it fits.
> >
> > > +                     }
> > > +                     dma_multi_pfn_offset = true;
> > >               }
> > >               dma_offset = range.cpu_addr - range.bus_addr;
> > >
> > > @@ -991,6 +1043,13 @@ int of_dma_get_range(struct device *dev, struct
> > > device_node *np, u64 *dma_addr,
> > >                       dma_end = range.bus_addr + range.size;
> > >       }
> > >
> > > +     if (dma_multi_pfn_offset) {
> > > +             dma_offset = 0;
> > > +             ret = attach_dma_pfn_offset_map(dev, node, num_ranges);
> > > +             if (ret)
> > > +                     return ret;
> > > +     }
> > > +
> > >       if (dma_start >= dma_end) {
> > >               ret = -EINVAL;
> > >               pr_debug("Invalid DMA ranges configuration on node(%pOF)\n",
> > > diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c
> > > index 6197938dcc2d..aaa3e58f5eb4 100644
> > > --- a/drivers/usb/core/message.c
> > > +++ b/drivers/usb/core/message.c
> > > @@ -1960,6 +1960,9 @@ int usb_set_configuration(struct usb_device *dev, int
> > > configuration)
> > >                */
> > >               intf->dev.dma_mask = dev->dev.dma_mask;
> > >               intf->dev.dma_pfn_offset = dev->dev.dma_pfn_offset;
> > > +#ifdef CONFIG_DMA_PFN_OFFSET_MAP
> > > +             intf->dev.dma_pfn_offset_map = dev->dev.dma_pfn_offset_map;
> > > +#endif
> >
> > Thanks for looking at this, that said, I see more instances of drivers changing
> > dma_pfn_offset outside of the core code. Why not doing this there too?
> >
> > Also, are we 100% sure that dev->dev.dma_pfn_offset isn't going to be freed
> > before we're done using intf->dev? Maybe it's safer to copy the ranges?
> >
> > >               INIT_WORK(&intf->reset_ws, __usb_queue_reset_device);
> > >               intf->minor = -1;
> > >               device_initialize(&intf->dev);
> > > diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c
> > > index f16c26dc079d..d2ed4d90e56e 100644
> > > --- a/drivers/usb/core/usb.c
> > > +++ b/drivers/usb/core/usb.c
> > > @@ -612,6 +612,9 @@ struct usb_device *usb_alloc_dev(struct usb_device
> > > *parent,
> > >        */
> > >       dev->dev.dma_mask = bus->sysdev->dma_mask;
> > >       dev->dev.dma_pfn_offset = bus->sysdev->dma_pfn_offset;
> > > +#ifdef CONFIG_DMA_PFN_OFFSET_MAP
> > > +     dev->dev.dma_pfn_offset_map = bus->sysdev->dma_pfn_offset_map;
> > > +#endif
> > >       set_dev_node(&dev->dev, dev_to_node(bus->sysdev));
> > >       dev->state = USB_STATE_ATTACHED;
> > >       dev->lpm_disable_count = 1;
> > > diff --git a/include/linux/device.h b/include/linux/device.h
> > > index ac8e37cd716a..67a240ad4fc5 100644
> > > --- a/include/linux/device.h
> > > +++ b/include/linux/device.h
> > > @@ -493,6 +493,8 @@ struct dev_links_info {
> > >   * @bus_dma_limit: Limit of an upstream bridge or bus which imposes a smaller
> > >   *           DMA limit than the device itself supports.
> > >   * @dma_pfn_offset: offset of DMA memory range relatively of RAM
> > > + * @dma_pfn_offset_map:      Like dma_pfn_offset but used when there are
> > > multiple
> > > + *           pfn offsets for multiple dma-ranges.
> > >   * @dma_parms:       A low level driver may set these to teach IOMMU code
> > > about
> > >   *           segment limitations.
> > >   * @dma_pools:       Dma pools (if dma'ble device).
> > > @@ -578,7 +580,13 @@ struct device {
> > >                                            allocations such descriptors. */
> > >       u64             bus_dma_limit;  /* upstream dma constraint */
> > >       unsigned long   dma_pfn_offset;
> > > -
> > > +#ifdef CONFIG_DMA_PFN_OFFSET_MAP
> > > +     const struct dma_pfn_offset_region *dma_pfn_offset_map;
> > > +                                     /* Like dma_pfn_offset, but for
> > > +                                      * the unlikely case of multiple
> > > +                                      * offsets. If non-null, dma_pfn_offset
> > > +                                      * will be set to 0. */
> > > +#endif
> >
> > I'm still sad this doesn't fully replace dma_pfn_offset & bus_dma_limit. I feel
> > the extra logic involved in incorporating this as default isn't going to be
> > noticeable as far as performance is concerned to single dma-range users, and
> > it'd make for a nicer DMA code. Also you'd force everyone to test their changes
> > on the multi dma-ranges code path, as opposed to having this disabled 99.9% of
> > the time (hence broken every so often).
> Good point.

+1

> > Note that I sympathize with the amount of work involved on improving that, so
> > better wait to hear what more knowledgeable people have to say about this :)
> Yes, I agree.  I want to avoid coding and testing one solution only to
> have a different reviewer NAK it.

It's a pretty safe bet that everyone will prefer one code path over 2.

Rob

^ permalink raw reply

* Re: [PATCH v2 3/3] dt-bindings: mmc: convert arasan sdhci bindings to yaml
From: Rob Herring @ 2020-05-29 17:25 UTC (permalink / raw)
  To: Wan Ahmad Zainie
  Cc: ulf.hansson, adrian.hunter, michal.simek, linux-mmc, devicetree
In-Reply-To: <20200526062758.17642-4-wan.ahmad.zainie.wan.mohamad@intel.com>

On Tue, May 26, 2020 at 02:27:58PM +0800, Wan Ahmad Zainie wrote:
> Convert arasan,sdhci.txt file to yaml. The new file arasan,sdhci.yaml
> will inherit properties from mmc-controller.yaml. 'sdhci' is no longer
> a valid name for node and should be changed to 'mmc'.
> 
> Suggested-by: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> ---
>  .../devicetree/bindings/mmc/arasan,sdhci.txt  | 192 ------------
>  .../devicetree/bindings/mmc/arasan,sdhci.yaml | 293 ++++++++++++++++++
>  2 files changed, 293 insertions(+), 192 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
>  create mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml


> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> new file mode 100644
> index 000000000000..927e2f13958b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> @@ -0,0 +1,293 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Device Tree Bindings for the Arasan SDHCI Controller
> +
> +allOf:
> +  - $ref: "mmc-controller.yaml#"
> +
> +maintainers:
> +  - Adrian Hunter <adrian.hunter@intel.com>
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: arasan,sdhci-8.9a                # generic Arasan SDHCI 8.9a PHY
> +      - const: arasan,sdhci-4.9a                # generic Arasan SDHCI 4.9a PHY
> +      - const: arasan,sdhci-5.1                 # generic Arasan SDHCI 5.1 PHY
> +      - items:
> +          - const: rockchip,rk3399-sdhci-5.1    # rk3399 eMMC PHY
> +          - const: arasan,sdhci-5.1
> +        description: |

Can drop '|' as formatting isn't important.

> +          For this device it is strongly suggested to include
> +          arasan,soc-ctl-syscon.
> +      - items:
> +          - const: xlnx,zynqmp-8.9a             # ZynqMP SDHCI 8.9a PHY
> +          - const: arasan,sdhci-8.9a
> +        description: |
> +          For this device it is strongly suggested to include
> +          clock-output-names and '#clock-cells'.

Sounds like a constraint. It's either optional or required though. There 
is no suggested.

> +      - items:
> +          - const: xlnx,versal-8.9a             # Versal SDHCI 8.9a PHY
> +          - const: arasan,sdhci-8.9a
> +        description: |
> +          For this device it is strongly suggested to include
> +          clock-output-names and '#clock-cells'.
> +      - items:
> +          - const: intel,lgm-sdhci-5.1-emmc     # Intel LGM eMMC PHY
> +          - const: arasan,sdhci-5.1
> +        description: |
> +          For this device it is strongly suggested to include
> +          arasan,soc-ctl-syscon.
> +      - items:
> +          - const: intel,lgm-sdhci-5.1-sdxc     # Intel LGM SDXC PHY
> +          - const: arasan,sdhci-5.1
> +        description: |
> +          For this device it is strongly suggested to include
> +          arasan,soc-ctl-syscon.
> +      - items:
> +          - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
> +          - const: arasan,sdhci-5.1
> +        description: |
> +          For this device it is strongly suggested to include
> +          arasan,soc-ctl-syscon.
> +      - const: intel,keembay-sdhci-5.1-sd       # Intel Keem Bay SD controller
> +        description: |
> +          For this device it is strongly suggested to include
> +          arasan,soc-ctl-syscon.
> +      - const: intel,keembay-sdhci-5.1-sdio     # Intel Keem Bay SDIO controller
> +        description: |
> +          For this device it is strongly suggested to include
> +          arasan,soc-ctl-syscon.
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 2
> +    maxItems: 3
> +
> +  clock-names:
> +    minItems: 2
> +    items:
> +      - const: clk_xin
> +      - const: clk_ahb
> +      - const: gate
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  phys:
> +    maxItems: 1
> +
> +  phy-names:
> +    const: phy_arasan
> +
> +  arasan,soc-ctl-syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: |
> +      A phandle to a syscon device (see ../mfd/syscon.txt) used to access
> +      core corecfg registers. Offsets of registers in this syscon are
> +      determined based on the main compatible string for the device.
> +
> +  clock-output-names:
> +    description: |
> +      If specified, this will be the name of the card clock which will
> +      be exposed by this device. Required if '#clock-cells' is specified.

The last sentence can be a 'dependencies' schema.

Are there defined names for this?

> +
> +  '#clock-cells':
> +    enum: [0, 1]
> +    description: |
> +      With this property in place we will export one or two clocks
> +      representing the Card Clock. These clocks are expected to be
> +      consumed by our PHY.
> +
> +  xlnx,fails-without-test-cd:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      When present, the controller doesn't work when the CD line is not
> +      connected properly, and the line is not connected properly.
> +      Test mode can be used to force the controller to function.
> +
> +  xlnx,int-clock-stable-broken:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: |
> +      When present, the controller always reports that the internal clock
> +      is stable even when it is not.
> +
> +  xlnx,mio-bank:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: |
> +      When specified, this will indicate the MIO bank number in which
> +      the command and data lines are configured. If not specified, driver
> +      will assume this as 0.

default: 0

Is there a range of valid values?

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        const: arasan,sdhci-5.1
> +then:
> +  required:
> +    - phys
> +    - phy-names

Add: unevaluatedProperties: false

> +
> +examples:
> +  - |
> +    mmc@e0100000 {
> +          compatible = "arasan,sdhci-8.9a";
> +          reg = <0xe0100000 0x1000>;
> +          clock-names = "clk_xin", "clk_ahb";
> +          clocks = <&clkc 21>, <&clkc 32>;
> +          interrupt-parent = <&gic>;
> +          interrupts = <0 24 4>;
> +    };
> +
> +  - |
> +    mmc@e2800000 {
> +          compatible = "arasan,sdhci-5.1";
> +          reg = <0xe2800000 0x1000>;
> +          clock-names = "clk_xin", "clk_ahb";
> +          clocks = <&cru 8>, <&cru 18>;
> +          interrupt-parent = <&gic>;
> +          interrupts = <0 24 4>;
> +          phys = <&emmc_phy>;
> +          phy-names = "phy_arasan";
> +    };
> +
> +  - |
> +    #include <dt-bindings/clock/rk3399-cru.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    mmc@fe330000 {
> +          compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
> +          reg = <0x0 0xfe330000 0x0 0x10000>;

Examples default to a single cell each for size and address.

> +          interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +          clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
> +          clock-names = "clk_xin", "clk_ahb";
> +          arasan,soc-ctl-syscon = <&grf>;
> +          assigned-clocks = <&cru SCLK_EMMC>;
> +          assigned-clock-rates = <200000000>;
> +          clock-output-names = "emmc_cardclock";
> +          phys = <&emmc_phy>;
> +          phy-names = "phy_arasan";
> +          #clock-cells = <0>;
> +    };
> +
> +  - |
> +    mmc@ff160000 {
> +          compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
> +          interrupt-parent = <&gic>;
> +          interrupts = <0 48 4>;
> +          reg = <0x0 0xff160000 0x0 0x1000>;

Same here.

> +          clocks = <&clk200>, <&clk200>;
> +          clock-names = "clk_xin", "clk_ahb";
> +          clock-output-names = "clk_out_sd0", "clk_in_sd0";
> +          #clock-cells = <1>;
> +          clk-phase-sd-hs = <63 72>;
> +    };
> +
> +  - |
> +    mmc@f1040000 {
> +          compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
> +          interrupt-parent = <&gic>;
> +          interrupts = <0 126 4>;
> +          reg = <0x0 0xf1040000 0x0 0x10000>;
> +          clocks = <&clk200>, <&clk200>;
> +          clock-names = "clk_xin", "clk_ahb";
> +          clock-output-names = "clk_out_sd0", "clk_in_sd0";
> +          #clock-cells = <1>;
> +          clk-phase-sd-hs = <132>, <60>;
> +    };
> +
> +  - |
> +    #define LGM_CLK_EMMC5
> +    #define LGM_CLK_NGI
> +    #define LGM_GCLK_EMMC
> +    mmc@ec700000 {
> +          compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> +          reg = <0xec700000 0x300>;
> +          interrupt-parent = <&ioapic1>;
> +          interrupts = <44 1>;
> +          clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
> +                   <&cgu0 LGM_GCLK_EMMC>;
> +          clock-names = "clk_xin", "clk_ahb", "gate";
> +          clock-output-names = "emmc_cardclock";
> +          #clock-cells = <0>;
> +          phys = <&emmc_phy>;
> +          phy-names = "phy_arasan";
> +          arasan,soc-ctl-syscon = <&sysconf>;
> +    };
> +
> +  - |
> +    #define LGM_CLK_SDIO
> +    #define LGM_GCLK_SDXC
> +    mmc@ec600000 {
> +          compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
> +          reg = <0xec600000 0x300>;
> +          interrupt-parent = <&ioapic1>;
> +          interrupts = <43 1>;
> +          clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
> +                   <&cgu0 LGM_GCLK_SDXC>;
> +          clock-names = "clk_xin", "clk_ahb", "gate";
> +          clock-output-names = "sdxc_cardclock";
> +          #clock-cells = <0>;
> +          phys = <&sdxc_phy>;
> +          phy-names = "phy_arasan";
> +          arasan,soc-ctl-syscon = <&sysconf>;
> +    };
> +
> +  - |
> +    #define KEEM_BAY_PSS_AUX_EMMC
> +    #define KEEM_BAY_PSS_EMMC
> +    mmc@33000000 {
> +          compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> +          interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +          reg = <0x0 0x33000000 0x0 0x300>;
> +          clock-names = "clk_xin", "clk_ahb";
> +          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
> +                   <&scmi_clk KEEM_BAY_PSS_EMMC>;
> +          phys = <&emmc_phy>;
> +          phy-names = "phy_arasan";
> +          assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
> +          assigned-clock-rates = <200000000>;
> +          clock-output-names = "emmc_cardclock";
> +          #clock-cells = <0>;
> +          arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
> +    };
> +
> +  - |
> +    #define KEEM_BAY_PSS_AUX_SD0
> +    #define KEEM_BAY_PSS_SD0
> +    mmc@31000000 {
> +          compatible = "intel,keembay-sdhci-5.1-sd";
> +          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +          reg = <0x0 0x31000000 0x0 0x300>;
> +          clock-names = "clk_xin", "clk_ahb";
> +          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
> +                   <&scmi_clk KEEM_BAY_PSS_SD0>;
> +          arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
> +    };
> +
> +  - |
> +    #define KEEM_BAY_PSS_AUX_SD1
> +    #define KEEM_BAY_PSS_SD1
> +    mmc@32000000 {
> +          compatible = "intel,keembay-sdhci-5.1-sdio";
> +          interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +          reg = <0x0 0x32000000 0x0 0x300>;
> +          clock-names = "clk_xin", "clk_ahb";
> +          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
> +                   <&scmi_clk KEEM_BAY_PSS_SD1>;
> +          arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
> +    };

Really need 3 Keem Bay examples?

> -- 
> 2.17.1
> 

^ permalink raw reply

* Re: [PATCH v6 00/16] spi: dw: Add generic DW DMA controller support
From: Mark Brown @ 2020-05-29 17:33 UTC (permalink / raw)
  To: Serge Semin
  Cc: Serge Semin, Ekaterina Skachko, Feng Tang, devicetree,
	Thomas Bogendoerfer, Georgy Vlasov, Pavel Parkhomenko,
	Alexey Kolotnikov, linux-spi, linux-kernel, Vadim Vlasov,
	Alexey Malahov, linux-mips, Andy Shevchenko, Rob Herring,
	Ramil Zaripov, Arnd Bergmann, Maxim Kaurkin
In-Reply-To: <20200529172642.hcnvyzv2ocizsvpy@mobilestation>

[-- Attachment #1: Type: text/plain, Size: 550 bytes --]

On Fri, May 29, 2020 at 08:26:42PM +0300, Serge Semin wrote:

> You must have missed the patch 16:
> 0e8332aaf059 dt-bindings: spi: Convert DW SPI binding to DT schema
> As you can see it has been acked by Rob. So you can also merge it into your
> repo. Though It has to be rebased first due to the Dinh Nguyen patches
> recently merged in. Do you want me to do the rebasing?

Please rebase.  TBH I'd not noticed Rob's review so I just left it
waiting for that, there's such a huge backlog there it didn't occur to
me that it might've been reviewed.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

^ permalink raw reply

* Re: [PATCH v2] arm: dts: am335x-boneblack: add gpio-line-names
From: Tony Lindgren @ 2020-05-29 17:21 UTC (permalink / raw)
  To: Drew Fustini
  Cc: Linus Walleij, Grygorii Strashko, Benoît Cousson,
	Rob Herring, Linux-OMAP, devicetree, linux-kernel, Jason Kridner,
	Robert Nelson
In-Reply-To: <20200528131620.GA3126290@x1>

* Drew Fustini <drew@beagleboard.org> [200528 13:17]:
> FYI - Linus W. provided an Acked-by in related thread [0].
> 
> Anyone else have any review comments?

Looks good to me thanks. But as the merge window is about
to open, let's do fixes only at this point and leave this
for v5.9.

Regards,

Tony


> 
> [0] https://lore.kernel.org/linux-devicetree/CACRpkdZLRjcE0FGwVR-Q7a50aEmpB=xO4q6H8_EaV199fGr0OA@mail.gmail.com/

^ permalink raw reply

* Re: [PATCHv3 1/2] spi: dw: add reset control
From: Mark Brown @ 2020-05-29 17:19 UTC (permalink / raw)
  To: linux-kernel, Dinh Nguyen
  Cc: devicetree, linux-spi, Sergey.Semin, Liang Jin J, lars.povlsen,
	andriy.shevchenko, fancer.lancer, robh+dt
In-Reply-To: <20200527204110.25676-1-dinguyen@kernel.org>

On Wed, 27 May 2020 15:41:09 -0500, Dinh Nguyen wrote:
> Add mechanism to get the reset control and deassert it in order to bring
> the IP out of reset.

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/2] spi: dw: add reset control
      commit: 7830c0ef26cb73b653c2db2f3ca7be08f44fa046
[2/2] dt-bindings: snps,dw-apb-ssi: add optional reset property
      commit: 2604d48702fe14fb3e97701269dd5e66b392b904

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

^ permalink raw reply

* Re: [PATCHv4 1/2] spi: dw: add reset control
From: Mark Brown @ 2020-05-29 17:18 UTC (permalink / raw)
  To: linux-kernel, Dinh Nguyen
  Cc: devicetree, linux-spi, liang.j.jin, Sergey.Semin, lars.povlsen,
	andriy.shevchenko, fancer.lancer, robh+dt
In-Reply-To: <20200529155806.16758-1-dinguyen@kernel.org>

On Fri, 29 May 2020 10:58:05 -0500, Dinh Nguyen wrote:
> Add mechanism to get the reset control and deassert it in order to bring
> the IP out of reset.

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/2] spi: dw: add reset control
      commit: 7830c0ef26cb73b653c2db2f3ca7be08f44fa046
[2/2] dt-bindings: snps,dw-apb-ssi: add optional reset property
      commit: 2604d48702fe14fb3e97701269dd5e66b392b904

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

^ permalink raw reply

* Re: [PATCH v6 00/16] spi: dw: Add generic DW DMA controller support
From: Mark Brown @ 2020-05-29 17:18 UTC (permalink / raw)
  To: Serge Semin
  Cc: Ekaterina Skachko, Feng Tang, devicetree, Thomas Bogendoerfer,
	Georgy Vlasov, Pavel Parkhomenko, Alexey Kolotnikov, Serge Semin,
	linux-spi, linux-kernel, Vadim Vlasov, Alexey Malahov, linux-mips,
	Andy Shevchenko, Rob Herring, Ramil Zaripov, Arnd Bergmann,
	Maxim Kaurkin
In-Reply-To: <20200529131205.31838-1-Sergey.Semin@baikalelectronics.ru>

On Fri, 29 May 2020 16:11:49 +0300, Serge Semin wrote:
> Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
> Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> APB SSI devices embedded into the SoC. Currently the DMA-based transfers
> are supported by the DW APB SPI driver only as a middle layer code for
> Intel MID/Elkhart PCI devices. Seeing the same code can be used for normal
> platform DMAC device we introduced a set of patches to fix it within this
> series.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[01/15] spi: dw: Set xfer effective_speed_hz
        commit: de4c2875a5ff2c886df60f2086c6affca83f890a
[02/15] spi: dw: Return any value retrieved from the dma_transfer callback
        commit: f0410bbf7d0fb80149e3b17d11d31f5b5197873e
[03/15] spi: dw: Locally wait for the DMA transfers completion
        commit: bdbdf0f06337d3661b64c0288c291cb06624065e
[04/15] spi: dw: Add SPI Tx-done wait method to DMA-based transfer
        commit: 1ade2d8a72f9240825f6be050f0d49c840f7daeb
[05/15] spi: dw: Add SPI Rx-done wait method to DMA-based transfer
        commit: 33726eff3d98e643f7d7a0940f4024844b430c82
[06/15] spi: dw: Parameterize the DMA Rx/Tx burst length
        commit: c534df9d6225314d1403e4330a22d68c35e0eb55
[07/15] spi: dw: Use DMA max burst to set the request thresholds
        commit: 0b2b66514fc9971b3a6002ba038d74f77705fd34
[08/15] spi: dw: Fix Rx-only DMA transfers
        commit: 46164fde6b7890e7a3982d54549947c8394c0192
[09/15] spi: dw: Add core suffix to the DW APB SSI core source file
        commit: 77ccff803d27279ccc100dc906c6f456c8fa515c
[10/15] spi: dw: Move Non-DMA code to the DW PCIe-SPI driver
        commit: 6c710c0cb6725bdbe647b958756685aed0295936
[11/15] spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI
        commit: 06cfadb8c51b05c6b91c2d43e0fe72b3d643dced
[12/15] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
        commit: ecb3a67edfd353837dc23b538fb250d1dfd88e7b
[13/15] spi: dw: Cleanup generic DW DMA code namings
        commit: 57784411728ff4d72ae051fdbba1e54fcb1f8d6f
[14/15] spi: dw: Add DMA support to the DW SPI MMIO driver
        commit: 0fdad596d46b28d5c3e39d1897c5e3878b64d9a2
[15/15] spi: dw: Use regset32 DebugFS method to create regdump file
        commit: 8378449d1f79add31be77e77fc7df9f639878e9c

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

^ permalink raw reply

* Re: [PATCH v2 1/2] dt-bindings: phy: intel: Add Keem Bay eMMC PHY bindings
From: Rob Herring @ 2020-05-29 17:14 UTC (permalink / raw)
  To: Wan Ahmad Zainie
  Cc: kishon, vkoul, linux-kernel, devicetree, andriy.shevchenko,
	adrian.hunter
In-Reply-To: <20200526050452.8837-2-wan.ahmad.zainie.wan.mohamad@intel.com>

On Tue, May 26, 2020 at 01:04:51PM +0800, Wan Ahmad Zainie wrote:
> Binding description for Intel Keem Bay eMMC PHY.
> 
> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> ---
>  .../bindings/phy/intel,keembay-emmc-phy.yaml  | 45 +++++++++++++++++++
>  1 file changed, 45 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/intel,keembay-emmc-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/intel,keembay-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,keembay-emmc-phy.yaml
> new file mode 100644
> index 000000000000..d3e0f169eb0a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/intel,keembay-emmc-phy.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2020 Intel Corporation
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/intel,keembay-emmc-phy.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Intel Keem Bay eMMC PHY bindings
> +
> +maintainers:
> +  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> +
> +properties:
> +  compatible:
> +    const: intel,keembay-emmc-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    items:
> +      - const: emmcclk
> +
> +  "#phy-cells":
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    phy@20290000 {
> +          compatible = "intel,keembay-emmc-phy";
> +          reg = <0x0 0x20290000 0x0 0x54>;

Examples expect a single cell for address and size.

> +          clocks = <&emmc>;
> +          clock-names = "emmcclk";
> +          #phy-cells = <0>;
> +    };
> -- 
> 2.17.1
> 

^ permalink raw reply

* Re: [PATCH 2/3] dt-bindings: rng: document Silex Insight BA431 hwrng
From: Rob Herring @ 2020-05-29 17:13 UTC (permalink / raw)
  To: Olivier Sobrie
  Cc: linux-crypto, linux-kernel, sebastien.rabou, Herbert Xu,
	devicetree, Waleed Ziad, Rob Herring, Matt Mackall, Arnd Bergmann,
	Greg Kroah-Hartman
In-Reply-To: <20200525195606.2941649-3-olivier.sobrie@silexinsight.com>

On Mon, 25 May 2020 21:56:05 +0200, Olivier Sobrie wrote:
> This patch documents the device tree bindings of the BA431 hardware
> random number generator.
> 
> This IP is for instance present in the Viper OEM boards sold by Silex
> Insight.
> 
> Signed-off-by: Olivier Sobrie <olivier.sobrie@silexinsight.com>
> ---
>  .../bindings/rng/silex-insight,ba431-rng.yaml | 36 +++++++++++++++++++
>  1 file changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/rng/silex-insight,ba431-rng.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply

* Re: [PATCH 1/3] dt-bindings: vendor-prefixes: Add Silex Insight vendor prefix
From: Rob Herring @ 2020-05-29 17:12 UTC (permalink / raw)
  To: Olivier Sobrie
  Cc: Greg Kroah-Hartman, linux-crypto, Waleed Ziad, Matt Mackall,
	sebastien.rabou, Rob Herring, Arnd Bergmann, Herbert Xu,
	linux-kernel, devicetree
In-Reply-To: <20200525195606.2941649-2-olivier.sobrie@silexinsight.com>

On Mon, 25 May 2020 21:56:04 +0200, Olivier Sobrie wrote:
> Silex Insight is a microelectronic company whose headquarter is located
> in Belgium.
> Web site of the company: https://www.silexinsight.com/
> 
> Signed-off-by: Olivier Sobrie <olivier.sobrie@silexinsight.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Applied, thanks!

^ permalink raw reply

* Re: [PATCH 3/3] hwrng: ba431-rng: add support for BA431 hwrng
From: Rob Herring @ 2020-05-29 17:12 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: Olivier Sobrie, Matt Mackall, Herbert Xu, Greg Kroah-Hartman,
	open list:HARDWARE RANDOM NUMBER GENERATOR CORE, DTML,
	linux-kernel@vger.kernel.org, Waleed Ziad, sebastien.rabou
In-Reply-To: <CAK8P3a3=HoQZuBoqyFgyde1X7BRfcH-GFQpu=8acOi_JhVU99g@mail.gmail.com>

On Mon, May 25, 2020 at 10:28:46PM +0200, Arnd Bergmann wrote:
> On Mon, May 25, 2020 at 10:07 PM Olivier Sobrie
> <olivier.sobrie@silexinsight.com> wrote:
> >
> > Silex insight BA431 is an IP designed to generate random numbers that
> > can be integrated in various FPGA.
> > This driver adds support for it through the hwrng interface.
> >
> > This driver is used in Silex Insight Viper OEM boards.
> >
> > Signed-off-by: Olivier Sobrie <olivier.sobrie@silexinsight.com>
> > Signed-off-by: Waleed Ziad <waleed94ziad@gmail.com>
> 
> The driver looks good to me.
> 
> Acked-by: Arnd Bergmann  <arnd@arndb.de>
> 
> >  drivers/char/hw_random/Kconfig     |  10 ++
> >  drivers/char/hw_random/Makefile    |   1 +
> >  drivers/char/hw_random/ba431-rng.c | 240 +++++++++++++++++++++++++++++
> 
> I wonder if we should move drivers/char/hw_random to its own top-level drivers
> subsystem outside of drivers/char. It seems to be growing steadily and is larger
> than a lot of other subsystems with currently 34 drivers in there.
> 
> Not your problem though.
> 
> > +       /* Wait until the state changed */
> > +       for (i = 0; i < BA431_RESET_READ_STATUS_RETRIES; ++i) {
> > +               state = ba431_trng_get_state(ba431);
> > +               if (state >= BA431_STATE_STARTUP)
> > +                       break;
> > +
> > +               udelay(BA431_RESET_READ_STATUS_INTERVAL);
> > +       }
> 
> Looking for something to improve, I noticed that this loop can take over
> a millisecond to time out, and it always runs in non-atomic context.
> It may be better to use usleep_range() than udelay().

Or better yet, use the register polling helpers.

Rob

^ permalink raw reply

* Re: [PATCH v4 2/5] dt-bindings: iio: imu: bmi160: add regulators and mount-matrix
From: Rob Herring @ 2020-05-29 17:09 UTC (permalink / raw)
  To: Jonathan Albrieux
  Cc: linux-kernel, ~postmarketos/upstreaming, daniel.baluta,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Hartmut Knaack, Lars-Peter Clausen,
	open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
	Jonathan Cameron
In-Reply-To: <20200525164615.14962-3-jonathan.albrieux@gmail.com>

On Mon, May 25, 2020 at 06:46:01PM +0200, Jonathan Albrieux wrote:
> Add vdd-supply and vddio-supply support.
> Add mount-matrix support.
> 
> Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
> ---
>  .../bindings/iio/imu/bosch,bmi160.yaml           | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml b/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
> index 0d0ef84e22b9..cfe40dbcd723 100644
> --- a/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
> +++ b/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
> @@ -37,6 +37,17 @@ properties:
>        set if the specified interrupt pin should be configured as
>        open drain. If not set, defaults to push-pull.
>  
> +  vdd-supply:
> +    maxItems: 1

Supplies are always a single item, so don't need this.

> +    description: provide VDD power to the sensor.
> +
> +  vddio-supply:
> +    maxItems: 1
> +    description: provide VDD IO power to the sensor.
> +
> +  mount-matrix:
> +    description: an optional 3x3 mounting rotation matrix
> +
>  required:
>    - compatible
>    - reg
> @@ -52,9 +63,14 @@ examples:
>          bmi160@68 {
>                  compatible = "bosch,bmi160";
>                  reg = <0x68>;
> +                vdd-supply = <&pm8916_l17>;
> +                vddio-supply = <&pm8916_l6>;
>                  interrupt-parent = <&gpio4>;
>                  interrupts = <12 IRQ_TYPE_EDGE_RISING>;
>                  interrupt-names = "INT1";
> +                mount-matrix = "0", "1", "0",
> +                               "-1", "0", "0",
> +                               "0", "0", "1";
>          };
>      };
>    - |
> -- 
> 2.17.1
> 

^ permalink raw reply

* Re: [PATCH v4 1/5] dt-bindings: iio: imu: bmi160: convert format to yaml, add maintainer
From: Rob Herring @ 2020-05-29 17:08 UTC (permalink / raw)
  To: Jonathan Albrieux
  Cc: Rob Herring, Hartmut Knaack, devicetree, linux-iio, daniel.baluta,
	Peter Meerwald-Stadler, ~postmarketos/upstreaming,
	Jonathan Cameron, linux-kernel, Lars-Peter Clausen
In-Reply-To: <20200525164615.14962-2-jonathan.albrieux@gmail.com>

On Mon, 25 May 2020 18:46:00 +0200, Jonathan Albrieux wrote:
> Converts documentation from txt format to yaml.
> 
> Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
> ---
>  .../devicetree/bindings/iio/imu/bmi160.txt    | 37 ---------
>  .../bindings/iio/imu/bosch,bmi160.yaml        | 75 +++++++++++++++++++
>  2 files changed, 75 insertions(+), 37 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/iio/imu/bmi160.txt
>  create mode 100644 Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply

* Re: [PATCH] dt-bindings: input: touchscreen: edt-ft5x06: change reg property
From: Rob Herring @ 2020-05-29 17:07 UTC (permalink / raw)
  To: Johan Jonker
  Cc: linux-rockchip, devicetree, linux-arm-kernel, linux-kernel, heiko,
	linux-input, dmitry.torokhov, robh+dt
In-Reply-To: <20200520073327.6016-1-jbx6244@gmail.com>

On Wed, 20 May 2020 09:33:27 +0200, Johan Jonker wrote:
> A test with the command below gives this error:
> 
> arch/arm/boot/dts/rk3188-bqedison2qc.dt.yaml:
> touchscreen@3e: reg:0:0: 56 was expected
> 
> The touchscreen chip on 'rk3188-bqedison2qc' and other BQ models
> was shipped with different addresses then the binding currently allows.
> Change the reg property that any address will pass.
> 
> make ARCH=arm dtbs_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/input/touchscreen/
> edt-ft5x06.yaml
> 
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
>  Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Applied, thanks!

^ permalink raw reply

* Re: [PATCH] dt-bindings: sound: tlv320adcx140: Fix dt-binding-check issue
From: Mark Brown @ 2020-05-29 16:51 UTC (permalink / raw)
  To: Dan Murphy, lgirdwood, perex, robh, tiwai
  Cc: devicetree, alsa-devel, linux-kernel
In-Reply-To: <20200528144711.18065-1-dmurphy@ti.com>

On Thu, 28 May 2020 09:47:11 -0500, Dan Murphy wrote:
> Fix dt-binding-check issue
> 
> ti,gpi-config:0:0: 4 is greater than the maximum of 1
> ti,gpi-config:0:1: 5 is greater than the maximum of 1
> ti,gpi-config:0:2: 6 is greater than the maximum of 1
> ti,gpi-config:0:3: 7 is greater than the maximum of 1

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/1] ASoC: tlv320adcx140: Fix dt-binding-check issue
      commit: c8b47d63ad8755780b6b70dbe57ab8333bcc4a0f

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

^ permalink raw reply

* Re: [Patch 1/2] dt-binbings: media: ti-vpe: Document the VIP driver
From: Benoit Parrot @ 2020-05-29 16:45 UTC (permalink / raw)
  To: Rob Herring; +Cc: Hans Verkuil, linux-media, devicetree, linux-kernel
In-Reply-To: <20200528233933.GA881467@bogus>

Hi Rob,

Thanks for the review.

Rob Herring <robh@kernel.org> wrote on Thu [2020-May-28 17:39:33 -0600]:
> On Fri, May 22, 2020 at 05:54:11PM -0500, Benoit Parrot wrote:
> > Device Tree bindings for the Video Input Port (VIP) driver.
> 
> Bindings document h/w, not drivers.

I'll fix that.

> 
> > 
> > Signed-off-by: Benoit Parrot <bparrot@ti.com>
> > ---
> >  .../devicetree/bindings/media/ti,vip.yaml     | 394 ++++++++++++++++++
> >  MAINTAINERS                                   |   1 +
> >  2 files changed, 395 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/media/ti,vip.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/media/ti,vip.yaml b/Documentation/devicetree/bindings/media/ti,vip.yaml
> > new file mode 100644
> > index 000000000000..8a9084e42329
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/ti,vip.yaml
> > @@ -0,0 +1,394 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/ti,vip.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Texas Instruments DRA7x VIDEO INPUT PORT (VIP) Device Tree Bindings
> > +
> > +maintainers:
> > +  - Benoit Parrot <bparrot@ti.com>
> > +
> > +description: |-
> > +  The Video Input Port (VIP) is a key component for image capture
> > +  applications. The capture module provides the system interface and the
> > +  processing capability to connect parallel image-sensor as well as
> > +  BT.656/1120 capable encoder chip to DRA7x device.
> > +
> > +  Each VIP instance supports 2 independently configurable external video
> > +  input capture slices (Slice 0 and Slice 1) each providing up to two video
> > +  input ports (Port A and Port B) where Port A can be configured as
> > +  24/16/8-bit port and Port B is fixed as 8-bit port.
> > +  Here these ports a represented as follows
> > +    port@0 -> Slice 0 Port A
> > +    port@1 -> Slice 0 Port B
> > +    port@2 -> Slice 1 Port A
> > +    port@3 -> Slice 1 Port B
> > +
> > +  Each camera port nodes should contain a 'port' child node with child
> > +  'endpoint' node. Please refer to the bindings defined in
> > +  Documentation/devicetree/bindings/media/video-interfaces.txt.
> > +
> > +properties:
> > +  compatible:
> > +    const: ti,dra7-vip
> > +
> > +  label:
> > +    description: Instance name
> 
> Kind of odd for this type of binding. Are there a define set or pattern 
> of values.

The label here are used to 'name' each H/W instance. And so far there can
be a up to 3 instances with the currently available devices, but that
doesn't mean there couldn't be more in the future. So I did not want to
limit it here.

> 
> > +
> > +  reg:
> > +    items:
> > +      - description: The VIP main register region
> > +      - description: Video Data Parser (PARSER) register region for Slice0
> > +      - description: Color Space Conversion (CSC) register region for Slice0
> > +      - description: Scaler (SC) register region for Slice0
> > +      - description: Video Data Parser (PARSER) register region for Slice1
> > +      - description: Color Space Conversion (CSC) register region for Slice1
> > +      - description: Scaler (SC) register region for Slice1
> > +      - description: Video Port Direct Memory Access (VPDMA) register region
> > +
> > +  reg-names:
> > +    items:
> > +      - const: vip
> > +      - const: parser0
> > +      - const: csc0
> > +      - const: sc0
> > +      - const: parser1
> > +      - const: csc1
> > +      - const: sc1
> > +      - const: vpdma
> > +
> > +  interrupts:
> > +    minItems: 2
> > +    description:
> > +      IRQ index 0 is used for Slice0 interrupts
> > +      IRQ index 1 is used for Slice1 interrupts
> > +
> > +  ti,vip-clk-polarity:
> > +    $ref: "/schemas/types.yaml#/definitions/phandle-array"
> > +    description:
> > +      phandle to the device control module. The 1st argument should
> > +      contain the register offset to the CTRL_CORE_SMA_SW_1 register.
> > +      2nd argument contains the bit field to slice 0 port A,
> > +      3rd argument contains the bit field to slice 0 port B,
> > +      4th argument contains the bit field to slice 1 port A,
> > +      5th argument contains the bit field to slice 1 port B.
> > +
> > +  # See ./video-interfaces.txt for details
> > +  ports:
> > +    type: object
> > +    additionalProperties: false
> > +
> > +    properties:
> > +      "#address-cells":
> > +        const: 1
> > +
> > +      "#size-cells":
> > +        const: 0
> > +
> > +      port@0:
> > +        type: object
> > +        additionalProperties: false
> > +
> > +        properties:
> > +          reg:
> > +            const: 0
> > +            description: Slice 0 Port A
> > +
> > +          label:
> > +            description: Port name. Usually the pin group name
> > +
> > +        patternProperties:
> > +          endpoint:
> > +            type: object
> > +            additionalProperties: false
> > +
> > +            properties:
> > +              hsync-active:
> > +                maxItems: 1
> 
> Not an array. Just:
> 
> hsync-active: true

OK I'll fix all of those.

> 
> > +
> > +              vsync-active:
> > +                maxItems: 1
> > +
> > +              pclk-sample:
> > +                maxItems: 1
> > +
> > +              bus-width:
> > +                maxItems: 1
> 
> Not an array. What subset of values are allowed?

So something like oneOf with a list then?

> 
> > +
> > +              ti,vip-pixel-mux:
> > +                type: boolean
> > +                description:
> > +                  In BT656/1120 mode, this enable pixel-muxing if
> > +                  the number of channels is either 1, 2 or 4. If this
> > +                  property is present then pixel-muxing is enabled
> > +                  otherwise it will use line-muxing.
> > +
> > +              ti,vip-channels:
> > +                $ref: "/schemas/types.yaml#definitions/uint8-array"
> > +                minItems: 1
> > +                maxItems: 16
> > +                description: |-
> > +                  In BT656/1120 mode, list of channel ids to be captured.
> > +                  If the property is not present then 1 channel is assumed.
> > +
> > +              remote-endpoint: true
> > +
> > +        required:
> > +          - reg
> > +          - label
> > +
> > +      port@1:
> > +        type: object
> > +        additionalProperties: false
> > +
> > +        properties:
> > +          reg:
> > +            const: 1
> > +            description: Slice 0 Port B
> > +
> > +          label:
> > +            description: Port name. Usually the pin group name
> > +
> > +        patternProperties:
> > +          endpoint:
> > +            type: object
> > +            additionalProperties: false
> > +
> > +            properties:
> > +              hsync-active:
> > +                maxItems: 1
> > +
> > +              vsync-active:
> > +                maxItems: 1
> > +
> > +              pclk-sample:
> > +                maxItems: 1
> > +
> > +              bus-width:
> > +                maxItems: 1
> > +
> > +              ti,vip-pixel-mux:
> > +                type: boolean
> > +                description:
> > +                  In BT656/1120 mode, this enable pixel-muxing if
> > +                  the number of channels is either 1, 2 or 4. If this
> > +                  property is present then pixel-muxing is enabled
> > +                  otherwise it will use line-muxing.
> > +
> > +              ti,vip-channels:
> > +                $ref: "/schemas/types.yaml#definitions/uint8-array"
> > +                minItems: 1
> > +                maxItems: 16
> > +                description:
> > +                  In BT656/1120 mode, list of channel ids to be captured.
> > +                  If the property is not present then 1 channel is assumed.
> > +
> > +              remote-endpoint: true
> > +
> > +        required:
> > +          - reg
> > +          - label
> > +
> > +      port@2:
> > +        type: object
> > +        additionalProperties: false
> > +
> > +        properties:
> > +          reg:
> > +            const: 2
> > +            description: Slice 1 Port A
> > +
> > +          label:
> > +            description: Port name. Usually the pin group name
> > +
> > +        patternProperties:
> > +          endpoint:
> > +            type: object
> > +            additionalProperties: false
> > +
> > +            properties:
> > +              hsync-active:
> > +                maxItems: 1
> > +
> > +              vsync-active:
> > +                maxItems: 1
> > +
> > +              pclk-sample:
> > +                maxItems: 1
> > +
> > +              bus-width:
> > +                maxItems: 1
> > +
> > +              ti,vip-pixel-mux:
> > +                type: boolean
> > +                description:
> > +                  In BT656/1120 mode, this enable pixel-muxing if
> > +                  the number of channels is either 1, 2 or 4. If this
> > +                  property is present then pixel-muxing is enabled
> > +                  otherwise it will use line-muxing.
> > +
> > +              ti,vip-channels:
> > +                $ref: "/schemas/types.yaml#definitions/uint8-array"
> > +                minItems: 1
> > +                maxItems: 16
> > +                description:
> > +                  In BT656/1120 mode, list of channel ids to be captured.
> > +                  If the property is not present then 1 channel is assumed.
> > +
> > +              remote-endpoint: true
> > +
> > +        required:
> > +          - reg
> > +          - label
> > +
> > +      port@3:
> > +        type: object
> > +        additionalProperties: false
> > +
> > +        properties:
> > +          reg:
> > +            const: 3
> > +            description: Slice 1 Port B
> > +
> > +          label:
> > +            description: Port name. Usually the pin group name
> > +
> > +        patternProperties:
> > +          endpoint:
> > +            type: object
> > +            additionalProperties: false
> > +
> > +            properties:
> > +              hsync-active:
> > +                maxItems: 1
> > +
> > +              vsync-active:
> > +                maxItems: 1
> > +
> > +              pclk-sample:
> > +                maxItems: 1
> > +
> > +              bus-width:
> > +                maxItems: 1
> > +
> > +              ti,vip-pixel-mux:
> > +                type: boolean
> > +                description:
> > +                  In BT656/1120 mode, this enable pixel-muxing if
> > +                  the number of channels is either 1, 2 or 4. If this
> > +                  property is present then pixel-muxing is enabled
> > +                  otherwise it will use line-muxing.
> > +
> > +              ti,vip-channels:
> > +                $ref: "/schemas/types.yaml#definitions/uint8-array"
> > +                minItems: 1
> > +                maxItems: 16
> > +                description:
> > +                  In BT656/1120 mode, list of channel ids to be captured.
> > +                  If the property is not present then 1 channel is assumed.
> > +
> > +              remote-endpoint: true
> 
> If all the properties are the same across ports, then do a 
> patternProperties with '^port@' and define them there. You'll still need 
> 'port@0', etc. to define what each port is.

Yeah I had tried to define something like that but I couldn't make pass
dt-binding-check wihtout any errors/warnings.

Can you point me to a recent example using this syntax?
Last time I check I couldn't find one.

Also I am not quite clear on the mechanism, you said to create a
patterProperties and then I wouols also have to define the individual port
themselves so I would have something like this:

      port@0:
        type: object
        additionalProperties: false

        properties:
          reg:
            const: 0
            description: Slice 0 Port A

          label:
            description: Port name. Usually the pin group name

      port@1:
        type: object
        additionalProperties: false

        properties:
          reg:
            const: 1
            description: Slice 0 Port B

          label:
            description: Port name. Usually the pin group name

      port@2:
        type: object
        additionalProperties: false

        properties:
          reg:
            const: 2
            description: Slice 1 Port A

          label:
            description: Port name. Usually the pin group name

      port@3:
        type: object
        additionalProperties: false

        properties:
          reg:
            const: 3
            description: Slice 1 Port B

          label:
            description: Port name. Usually the pin group name

And then in some way reference the patternProperties?
Or just put it before the individual ports?

> 
> > +
> > +        required:
> > +          - reg
> > +          - label
> > +
> > +    required:
> > +      - "#address-cells"
> > +      - "#size-cells"
> > +      - port@0
> > +
> > +required:
> > +  - compatible
> > +  - label
> > +  - reg
> > +  - reg-names
> > +  - interrupts
> > +  - ti,vip-clk-polarity
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +    vip1: vip@48970000 {
> > +        compatible = "ti,dra7-vip";
> > +        label = "vip1";
> > +        reg = <0x48970000 0x114>,
> > +              <0x48975500 0xD8>,
> > +              <0x48975700 0x18>,
> > +              <0x48975800 0x80>,
> > +              <0x48975a00 0xD8>,
> > +              <0x48975c00 0x18>,
> > +              <0x48975d00 0x80>,
> > +              <0x4897d000 0x400>;
> > +        reg-names = "vip",
> > +                    "parser0",
> > +                    "csc0",
> > +                    "sc0",
> > +                    "parser1",
> > +                    "csc1",
> > +                    "sc1",
> > +                    "vpdma";
> > +        interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
> > +        ti,vip-clk-polarity = <&scm_conf 0x534 0x1 0x4 0x2 0x8>;
> > +
> > +        ports {
> > +              #address-cells = <1>;
> > +              #size-cells = <0>;
> > +
> > +              vin1a: port@0 {
> > +                    reg = <0>;
> > +                    label = "vin1a";
> > +
> > +                    vin1a_ep: endpoint {
> > +                           remote-endpoint = <&camera1>;
> > +                           hsync-active = <1>;
> > +                           vsync-active = <1>;
> > +                           pclk-sample = <0>;
> > +                           bus-width = <8>;
> > +                    };
> > +              };
> > +              vin1b: port@1 {
> > +                    reg = <1>;
> > +                    label = "vin1b";
> > +              };
> > +              vin2a: port@2 {
> > +                    reg = <2>;
> > +                    label = "vin2a";
> > +              };
> > +              vin2b: port@3 {
> > +                    reg = <3>;
> > +                    label = "vin2b";
> > +              };
> > +         };
> > +    };
> > +
> > +    i2c {
> > +        clock-frequency = <400000>;
> > +        #address-cells = <1>;
> > +        #size-cells = <0>;
> > +
> > +         camera@37 {
> > +              compatible = "ovti,ov10633";
> > +              reg = <0x37>;
> > +
> > +              clocks = <&fixed_clock>;
> > +              clocks-names = "xvclk";
> > +
> > +              port {
> > +                   camera1: endpoint {
> > +                           remote-endpoint = <&vin1a_ep>;
> > +                           hsync-active = <1>;
> > +                           vsync-active = <1>;
> > +                           pclk-sample = <0>;
> > +                           bus-width = <8>;
> > +                   };
> > +              };
> > +         };
> > +    };
> > +
> > +...
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 2e9a5f6e4ff7..06856d05b53b 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -16947,6 +16947,7 @@ S:	Maintained
> >  W:	http://linuxtv.org/
> >  Q:	http://patchwork.linuxtv.org/project/linux-media/list/
> >  F:	Documentation/devicetree/bindings/media/ti,cal.yaml
> > +F:	Documentation/devicetree/bindings/media/ti,vip.yaml
> >  F:	Documentation/devicetree/bindings/media/ti,vpe.yaml
> >  F:	drivers/media/platform/ti-vpe/
> >  
> > -- 
> > 2.17.1
> > 

Regards,
Benoit

^ permalink raw reply

* Re: [RFC v3 1/3] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
From: Jack Pham @ 2020-05-29 16:28 UTC (permalink / raw)
  To: Wesley Cheng
  Cc: robh+dt, bjorn.andersson, balbi, gregkh, agross, linux-kernel,
	linux-arm-msm, devicetree, linux-usb
In-Reply-To: <1590630363-3934-2-git-send-email-wcheng@codeaurora.org>

Hi Wesley,

On Wed, May 27, 2020 at 06:46:01PM -0700, Wesley Cheng wrote:
> Some devices have USB compositions which may require multiple endpoints
> that support EP bursting.  HW defined TX FIFO sizes may not always be
> sufficient for these compositions.  By utilizing flexible TX FIFO
> allocation, this allows for endpoints to request the required FIFO depth to
> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
> a larger TX FIFO size results in better TX throughput.
> 
> Ensure that one TX FIFO is reserved for every IN endpoint.  This allows for
> the FIFO logic to prevent running out of FIFO space.
> 
> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
> ---

<snip>

> diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
> index 00746c2..9b09528 100644
> --- a/drivers/usb/dwc3/gadget.c
> +++ b/drivers/usb/dwc3/gadget.c
> @@ -540,6 +540,117 @@ static int dwc3_gadget_start_config(struct dwc3_ep *dep)
>  	return 0;
>  }
>  
> +/*
> + * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
> + * @dwc: pointer to our context structure
> + *
> + * This function will a best effort FIFO allocation in order
> + * to improve FIFO usage and throughput, while still allowing
> + * us to enable as many endpoints as possible.
> + *
> + * Keep in mind that this operation will be highly dependent
> + * on the configured size for RAM1 - which contains TxFifo -,
> + * the amount of endpoints enabled on coreConsultant tool, and
> + * the width of the Master Bus.
> + *
> + * In general, FIFO depths are represented with the following equation:
> + *
> + * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
> + *
> + * Conversions can be done to the equation to derive the number of packets that
> + * will fit to a particular FIFO size value.
> + */
> +static int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc, struct dwc3_ep *dep)

The 'dep' param should be sufficient; we can just get 'dwc' from
dep->dwc. That will make it more clear this function operates on each
endpoint that needs resizing.

> +{
> +	int ram1_depth, mdwidth, fifo_0_start, tmp, num_in_ep;
> +	int min_depth, remaining, fifo_size, mult = 1, fifo, max_packet = 1024;
> +
> +	if (!dwc->needs_fifo_resize)
> +		return 0;
> +
> +	/* resize IN endpoints except ep0 */
> +	if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
> +		return 0;
> +
> +	/* Don't resize already resized IN endpoint */
> +	if (dep->fifo_depth)
> +		return 0;
> +
> +	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
> +	mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
> +	/* MDWIDTH is represented in bits, we need it in bytes */
> +	mdwidth >>= 3;
> +
> +	if (((dep->endpoint.maxburst > 1) &&
> +			usb_endpoint_xfer_bulk(dep->endpoint.desc))
> +			|| usb_endpoint_xfer_isoc(dep->endpoint.desc))
> +		mult = 3;
> +
> +	if ((dep->endpoint.maxburst > 6) &&
> +			usb_endpoint_xfer_bulk(dep->endpoint.desc)
> +			&& dwc3_is_usb31(dwc))
> +		mult = 6;
> +
> +	/* FIFO size for a single buffer */
> +	fifo = (max_packet + mdwidth)/mdwidth;
> +	fifo++;
> +
> +	/* Calculate the number of remaining EPs w/o any FIFO */
> +	num_in_ep = dwc->num_eps/2;
> +	num_in_ep -= dwc->num_ep_resized;
> +	/* Ignore EP0 IN */
> +	num_in_ep--;
> +
> +	/* Reserve at least one FIFO for the number of IN EPs */
> +	min_depth = num_in_ep * (fifo+1);
> +	remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
> +
> +	/* We've already reserved 1 FIFO per EP, so check what we can fit in
> +	 * addition to it.  If there is not enough remaining space, allocate
> +	 * all the remaining space to the EP.
> +	 */
> +	fifo_size = (mult-1) * fifo;
> +	if (remaining < fifo_size) {
> +		if (remaining > 0)
> +			fifo_size = remaining;
> +		else
> +			fifo_size = 0;
> +	}
> +
> +	fifo_size += fifo;
> +	fifo_size++;
> +	dep->fifo_depth = fifo_size;
> +
> +	/* Check if TXFIFOs start at non-zero addr */
> +	tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
> +	fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
> +
> +	fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
> +	if (dwc3_is_usb31(dwc))
> +		dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
> +	else
> +		dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
> +
> +	/* Check fifo size allocation doesn't exceed available RAM size. */
> +	if (dwc->last_fifo_depth >= ram1_depth) {
> +		dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
> +				(dwc->last_fifo_depth * mdwidth), ram1_depth,
> +				dep->endpoint.name, fifo_size);

Use dev_WARN() here and eliminate the WARN_ON(1) below?

> +		if (dwc3_is_usb31(dwc))
> +			fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
> +		else
> +			fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
> +		dwc->last_fifo_depth -= fifo_size;
> +		dep->fifo_depth = 0;
> +		WARN_ON(1);
> +		return -ENOMEM;
> +	}
> +
> +	dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
> +	dwc->num_ep_resized++;
> +	return 0;
> +}
> +
>  static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
>  {
>  	const struct usb_ss_ep_comp_descriptor *comp_desc;
> @@ -620,6 +731,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
>  	int			ret;
>  
>  	if (!(dep->flags & DWC3_EP_ENABLED)) {
> +		ret = dwc3_gadget_resize_tx_fifos(dwc, dep);
> +		if (ret)
> +			return ret;
> +
>  		ret = dwc3_gadget_start_config(dep);
>  		if (ret)
>  			return ret;

Jack
-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply

* Re: [PATCH 1/2] arm64: dts: Add a device tree for the Librem5 phone
From: Pavel Machek @ 2020-05-29 16:28 UTC (permalink / raw)
  To: Martin Kepplinger
  Cc: robh, kernel, shawnguo, s.hauer, kernel, festevam, linux-imx,
	mchehab, Anson.Huang, agx, angus, linux-kernel, devicetree,
	linux-arm-kernel
In-Reply-To: <20200514155737.12160-1-martin.kepplinger@puri.sm>

[-- Attachment #1: Type: text/plain, Size: 1342 bytes --]

Hi!

> From: "Angus Ainslie (Purism)" <angus@akkea.ca>
> 
> Add a devicetree description for the Librem 5 phone. The early batches
> that have been sold are supported as well as the mass-produced device
> available later this year, see https://puri.sm/products/librem-5/
> 
> This boots to a working console with working WWAN modem, wifi usdhc,
> IMU sensor device, proximity sensor, haptic motor, gpio keys, GNSS and LEDs.
> 
> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
> Signed-off-by: Guido Günther <agx@sigxcpu.org>


> +		blue {
> +			label = "phone:blue:front";
> +			label = "phone:green:front";
> +			label = "phone:red:front";

Droid 4 uses "status-led:{red,green,blue}". Could this use same
naming?

> +			label = "lm3560:flash";
> +			label = "lm3560:torch";

This is one LED, right? I'm pretty sure we don't want lm3560 in the
name... "main-camera:flash" would be better. Even better would be
something that's already in use.

> +			label = "white:backlight_cluster";

Make this ":backlight", please. Again, we want something that's
already used.

Best regards,
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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^ permalink raw reply

* Re: [PATCH v3 4/5] arm64: dts: sun50i-a64-pinephone: Enable LCD support on PinePhone
From: Pavel Machek @ 2020-05-29 16:27 UTC (permalink / raw)
  To: Ondrej Jirman
  Cc: linux-sunxi, Thierry Reding, Sam Ravnborg, David Airlie,
	Daniel Vetter, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
	Linus Walleij, Icenowy Zheng, dri-devel, devicetree, linux-kernel,
	linux-arm-kernel, Samuel Holland, Martijn Braam, Luca Weiss,
	Bhushan Shah
In-Reply-To: <20200513212451.1919013-5-megous@megous.com>

[-- Attachment #1: Type: text/plain, Size: 1265 bytes --]

Hi!

> PinePhone uses PWM backlight and a XBD599 LCD panel over DSI for
> display.
> 
> Backlight levels curve was optimized by Martijn Braam using a
> lux meter.

If it was possible to preserve lux values for individual settings in
the comment somewhere... that would be nice :-).

One day, it would be nice to have brightness settings in lux, so I
could easily set matching levels on multiple devices, for example...

Best regards,

								Pavel

> +
> +&backlight {
> +	power-supply = <&reg_ldo_io0>;
> +	/*
> +	 * PWM backlight circuit on this PinePhone revision was changed since
> +	 * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight
> +	 * being off is around 20%. Duty cycle for the lowest brightness level
> +	 * also varries quite a bit between individual boards, so the lowest
> +	 * value here was chosen as a safe default.
> +	 */
> +	brightness-levels = <
> +		774  793  814  842
> +		882  935  1003 1088
> +		1192 1316 1462 1633
> +		1830 2054 2309 2596
> +		2916 3271 3664 4096>;
> +	num-interpolated-steps = <50>;
> +	default-brightness-level = <400>;

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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^ permalink raw reply

* Re: [PATCHv1 00/19] Improve SBS battery support
From: Pavel Machek @ 2020-05-29 16:27 UTC (permalink / raw)
  To: Sebastian Reichel
  Cc: Sebastian Reichel, Rob Herring, Greg Kroah-Hartman,
	Rafael J . Wysocki, linux-pm, devicetree, linux-kernel, kernel
In-Reply-To: <20200513185615.508236-1-sebastian.reichel@collabora.com>

[-- Attachment #1: Type: text/plain, Size: 887 bytes --]

Hi!

> This patchset improves support for SBS compliant batteries. Due to
> the changes, the battery now exposes 32 power supply properties and
> (un)plugging it generates a backtrace containing the following message
> without the first patch in this series:
> 
> ---------------------------
> WARNING: CPU: 0 PID: 20 at lib/kobject_uevent.c:659 add_uevent_var+0xd4/0x104
> add_uevent_var: too many keys
> ---------------------------
> 
> For references this is what an SBS battery status looks like after
> the patch series has been applied:
> 
> POWER_SUPPLY_VOLTAGE_MIN_DESIGN=10800000
> POWER_SUPPLY_VOLTAGE_MAX_DESIGN=10800000

Is that correct, BTW? sounds like these should not be equal...

Best regards,
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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^ permalink raw reply

* Re: [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC
From: Serge Semin @ 2020-05-29 16:21 UTC (permalink / raw)
  To: Lars Povlsen
  Cc: Serge Semin, Mark Brown, SoC Team, devicetree, linux-kernel,
	linux-spi, Microchip Linux Driver Support, linux-arm-kernel
In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com>

Hello Lars,

On Wed, May 13, 2020 at 04:00:21PM +0200, Lars Povlsen wrote:
> This is an add-on series to the main SoC Sparx5 series
> (Message-ID: <20200513125532.24585-1-lars.povlsen@microchip.com>).
> 
> The series add support for Sparx5 on top of the existing
> ocelot/jaguar2 spi driver.
> 
> It spins off the existing support for the MSCC platforms into a
> separate driver, as adding new platforms from the MSCC/Microchip
> product lines will further complicate (clutter) the original driver.
> 
> New YAML dt-bindings are provided for the resulting driver.
> 
> It is expected that the DT patches are to be taken directly by the arm-soc
> maintainers.

Regarding our cooperation. It can be implemented as follows. Since your patchset
is less cumbersome than mine and is more ready to be integrated into the generic DW
APB SSI code, it would be better to first make it through Mark', Andy' and my reviews
to be further merged into the kernel version of the driver. After that I'll have
my code altered so it could be applied on top of your patches. When everything
is done we'll have a more comprehensive DW APB SSI driver with poll-based
PIO operations support, new features like rx-delay, etc.

Thank you one more time for the series you've shared with us. Let's see what can
be done to improve it...

-Sergey

> 
> Lars Povlsen (10):
>   spi: dw: Add support for polled operation via no IRQ specified in DT
>   spi: dw: Add support for RX sample delay register
>   spi: dw: Add support for client driver memory operations
>   dt-bindings: spi: Add bindings for spi-dw-mchp
>   spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp
>   dt-bindings: spi: spi-dw-mchp: Add Sparx5 support
>   spi: spi-dw-mchp: Add Sparx5 support
>   arm64: dts: sparx5: Add SPI controller
>   arm64: dts: sparx5: Add spi-nor support
>   arm64: dts: sparx5: Add spi-nand devices
> 
>  .../bindings/spi/mscc,ocelot-spi.yaml         |  89 ++++
>  .../bindings/spi/snps,dw-apb-ssi.txt          |   7 +-
>  MAINTAINERS                                   |   2 +
>  arch/arm64/boot/dts/microchip/sparx5.dtsi     |  37 ++
>  .../boot/dts/microchip/sparx5_pcb125.dts      |  16 +
>  .../boot/dts/microchip/sparx5_pcb134.dts      |  22 +
>  .../dts/microchip/sparx5_pcb134_board.dtsi    |   9 +
>  .../boot/dts/microchip/sparx5_pcb135.dts      |  23 +
>  .../dts/microchip/sparx5_pcb135_board.dtsi    |   9 +
>  arch/mips/configs/generic/board-ocelot.config |   2 +-
>  drivers/spi/Kconfig                           |   7 +
>  drivers/spi/Makefile                          |   1 +
>  drivers/spi/spi-dw-mchp.c                     | 399 ++++++++++++++++++
>  drivers/spi/spi-dw-mmio.c                     |  93 ----
>  drivers/spi/spi-dw.c                          |  31 +-
>  drivers/spi/spi-dw.h                          |   4 +
>  16 files changed, 644 insertions(+), 107 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
>  create mode 100644 drivers/spi/spi-dw-mchp.c
> 
> --
> 2.26.2
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* [PATCH 1/3] dt-bindings: net: wireless: mt76: add power-limits node
From: Felix Fietkau @ 2020-05-29 16:19 UTC (permalink / raw)
  To: linux-wireless; +Cc: devicetree

This subnode can be used to set per-rate tx power limits either per
country code / regdomain or globally.
These limits are typically provided by the device manufacturers and are
used to limit sideband emissions and stay within regulatory limits

Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
 .../bindings/net/wireless/mediatek,mt76.txt   | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.txt b/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.txt
index ab7e7a00e534..9d9ace0cfbf9 100644
--- a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.txt
+++ b/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.txt
@@ -36,6 +36,7 @@ Optional nodes:
 - led: Properties for a connected LED
   Optional properties:
     - led-sources: See Documentation/devicetree/bindings/leds/common.txt
+- power-limits: contains per-regdomain/channel rate power limit subnodes
 
 &pcie {
 	pcie0 {
@@ -76,3 +77,49 @@ wmac: wmac@18000000 {
 
 	power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
 };
+
+
+Subnodes of power-limits:
+
+Properties:
+- country: One or more country codes, as used by the cfg80211 regdomain code
+- regdomain: "FCC", "ETSI" or "JP"
+
+If neither country, nor regdomain is specified, the power limits node is used
+as a fallback when no other subnode matches.
+
+Subnodes txpower-2g, txpower-5g:
+
+Properties:
+- channels: pairs of first and last channel number
+- cck: 4 half-dBm per-rate power limit values
+- ofdm: 8 half-dBm per-rate power limit values
+- mcs:
+	sets of per-rate power limit values for 802.11n/802.11ac rates for
+	multiple channel bandwidth settings.
+	Each set starts with the number of channel bandwidth settings for
+	which the rate set applies, followed by either 8 (MT7603/MT7628) or
+	10 (all other chips) power limit values.
+	The order of the channel bandwidth settings is: 20, 40, 80, 160 MHz.
+
+
+power-limit example:
+
+power-limits {
+	r0 {
+		regdomain = "FCC";
+		txpower-5g {
+			r1 {
+				channels = <36 48>;
+				ofdm = <23 23 23 23 23 23 23 23>;
+				mcs = <1 23 23 23 23 23 23 23 23 23 23>,
+					  <3 22 22 22 22 22 22 22 22 22 22>;
+			};
+			r2 {
+				channels = <100 181>;
+				ofdm = <14 14 14 14 14 14 14 14>;
+				mcs = <4 14 14 14 14 14 14 14 14 14 14>;
+			};
+		};
+	};
+};
-- 
2.24.0


^ permalink raw reply related

* Re: [PATCH v6 4/9] dt-bindings: display: panel: Add ilitek ili9341 panel bindings
From: Rob Herring @ 2020-05-29 16:17 UTC (permalink / raw)
  To: dillon.minfei
  Cc: robh+dt, alexandre.torgue, dillonhua, daniel, linux-spi,
	mturquette, linux-clk, sam, mcoquelin.stm32, devicetree,
	linus.walleij, linux-arm-kernel, thierry.reding, sboyd, broonie,
	noralf, airlied, dri-devel, linux-kernel, andy.shevchenko,
	p.zabel, linux-stm32
In-Reply-To: <1590564453-24499-5-git-send-email-dillon.minfei@gmail.com>

On Wed, 27 May 2020 15:27:28 +0800, dillon.minfei@gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> Add documentation for "ilitek,ili9341" panel.
> 
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>  .../bindings/display/panel/ilitek,ili9341.yaml     | 69 ++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply

* Re: [PATCH v2 1/3] media: dt-bindings: media: Document Rockchip CIF bindings
From: Rob Herring @ 2020-05-29 16:14 UTC (permalink / raw)
  To: Maxime Chevallier
  Cc: Robin Murphy, Hans Verkuil, devicetree, Heiko Stuebner,
	Paul Kocialkowski, Thomas Petazzoni, linux-rockchip,
	Mauro Carvalho Chehab, Miquel Raynal, Rob Herring, linux-media,
	linux-arm-kernel, Mark Rutland, linux-kernel
In-Reply-To: <20200529130405.929429-2-maxime.chevallier@bootlin.com>

On Fri, 29 May 2020 15:04:03 +0200, Maxime Chevallier wrote:
> Add a documentation for the Rockchip Camera Interface controller
> binding.
> 
> This controller can be found on platforms such as the PX30 or the
> RK3288, the PX30 being the only platform supported so far.
> 
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
> ---
> 
> Changes since V1
> 
>  - Updated the clock and reset names
>  - Added missing includes in the example, so that the make dt_binding_check passes
> 
>  .../bindings/media/rockchip-cif.yaml          | 100 ++++++++++++++++++
>  1 file changed, 100 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/rockchip-cif.yaml
> 


My bot found errors running 'make dt_binding_check' on your patch:

/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/rockchip-cif.example.dt.yaml: cif@ff490000: clock-names: Additional items are not allowed ('cif_out' was unexpected)
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/rockchip-cif.example.dt.yaml: cif@ff490000: clock-names:0: 'aclk' was expected
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/rockchip-cif.example.dt.yaml: cif@ff490000: clock-names:1: 'hclkf' was expected
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/rockchip-cif.example.dt.yaml: cif@ff490000: clock-names:2: 'pclkin' was expected
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/rockchip-cif.example.dt.yaml: cif@ff490000: clock-names: ['aclk_cif', 'hclk_cif', 'pclk_cif', 'cif_out'] is too long
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/rockchip-cif.example.dt.yaml: cif@ff490000: clocks: Additional items are not allowed ([4294967295, 52] was unexpected)
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/rockchip-cif.example.dt.yaml: cif@ff490000: clocks: [[4294967295, 179], [4294967295, 249], [4294967295, 352], [4294967295, 52]] is too long
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/rockchip-cif.example.dt.yaml: cif@ff490000: reset-names:0: 'axi' was expected
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/rockchip-cif.example.dt.yaml: cif@ff490000: reset-names:1: 'ahb' was expected
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/rockchip-cif.example.dt.yaml: cif@ff490000: reset-names:2: 'pclkin' was expected

See https://patchwork.ozlabs.org/patch/1300680

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:

pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade

Please check and re-submit.


^ permalink raw reply

* Re: [PATCH v8 5/5] dt-bindings: chosen: Document linux,low-memory-range for arm64 kdump
From: James Morse @ 2020-05-29 16:11 UTC (permalink / raw)
  To: Rob Herring, chenzhou
  Cc: Thomas Gleixner, Ingo Molnar, Catalin Marinas, Will Deacon,
	dyoung, Baoquan He, Arnd Bergmann, John.p.donnelly, pkushwaha,
	Simon Horman, Hanjun Guo,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	devicetree, Linux Doc Mailing List, linux-kernel@vger.kernel.org,
	kexec
In-Reply-To: <20200526211800.GA352001@bogus>

Hi guys,

On 26/05/2020 22:18, Rob Herring wrote:
> On Fri, May 22, 2020 at 11:24:11AM +0800, chenzhou wrote:
>> On 2020/5/21 21:29, Rob Herring wrote:
>>> On Thu, May 21, 2020 at 3:35 AM Chen Zhou <chenzhou10@huawei.com> wrote:
>>>> Add documentation for DT property used by arm64 kdump:
>>>> linux,low-memory-range.
>>>> "linux,low-memory-range" is an another memory region used for crash
>>>> dump kernel devices.

>>>> diff --git a/Documentation/devicetree/bindings/chosen.txt b/Documentation/devicetree/bindings/chosen.txt
>>>> index 45e79172a646..bfe6fb6976e6 100644
>>>> --- a/Documentation/devicetree/bindings/chosen.txt
>>>> +++ b/Documentation/devicetree/bindings/chosen.txt

>>>> +linux,low-memory-range
>>>> +----------------------
>>>> +This property (arm64 only) holds a base address and size, describing a
>>>> +limited region below 4G. Similar to "linux,usable-memory-range", it is
>>>> +an another memory range which may be considered available for use by the
>>>> +kernel.

>>> Why can't you just add a range to "linux,usable-memory-range"? It
>>> shouldn't be hard to figure out which part is below 4G.

>> The comments from James:
>> Won't this break if your kdump kernel doesn't know what the extra parameters are?
>> Or if it expects two ranges, but only gets one? These DT properties should be treated as
>> ABI between kernel versions, we can't really change it like this.
>>
>> I think the 'low' region is an optional-extra, that is never mapped by the first kernel. I
>> think the simplest thing to do is to add an 'linux,low-memory-range' that we
>> memblock_add() after memblock_cap_memory_range() has been called.
>> If its missing, or the new kernel doesn't know what its for, everything keeps working.
> 
> 
> I don't think there's a compatibility issue here though. The current 
> kernel doesn't care if the property is longer than 1 base+size. It only 
> checks if the size is less than 1 base+size.

Aha! I missed that.


> And yes, we can rely on 
> that implementation detail. It's only an ABI if an existing user 
> notices.
> 
> Now, if the low memory is listed first, then an older kdump kernel 
> would get a different memory range. If that's a problem, then define 
> that low memory goes last. 

This first entry would need to be the 'crashkernel' range where the kdump kernel is
placed, otherwise an older kernel won't boot. The rest can be optional extras, as long as
we are tolerant of it being missing...

I'll try and look at the rest of this series on Monday,


Thanks,

James

^ permalink raw reply


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