* Re: [PATCH 2/2] drm/panel: simple: Add support for KOE TX26D202VM0BWA panel
From: Emil Velikov @ 2020-06-02 12:46 UTC (permalink / raw)
To: Liu Ying
Cc: ML dri-devel, devicetree, Thierry Reding, Sam Ravnborg,
NXP Linux Team
In-Reply-To: <1590991880-24273-1-git-send-email-victor.liu@nxp.com>
On Tue, 2 Jun 2020 at 08:17, Liu Ying <victor.liu@nxp.com> wrote:
>
> This patch adds support for Kaohsiung Opto-Electronics Inc.
> 10.1" TX26D202VM0BWA WUXGA(1920x1200) TFT LCD panel with LVDS interface.
> The panel has dual LVDS channels.
>
> My panel is manufactured by US Micro Products(USMP). There is a tag at
> the back of the panel, which indicates the panel type is 'TX26D202VM0BWA'
> and it's made by KOE in Taiwan.
>
> The panel spec from USMP can be found at:
> https://www.usmicroproducts.com/sites/default/files/datasheets/USMP-T101-192120NDU-A0.pdf
>
> The below panel spec from KOE is basically the same to the one from USMP.
> However, the panel type 'TX26D202VM0BAA' is a little bit different.
> It looks that the two types of panel are compatible with each other.
> http://www.koe.j-display.com/upload/product/TX26D202VM0BAA.pdf
>
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Sam Ravnborg <sam@ravnborg.org>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> drivers/gpu/drm/panel/panel-simple.c | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index b6ecd15..7c222ec 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -2200,6 +2200,37 @@ static const struct panel_desc koe_tx14d24vm1bpa = {
> },
> };
>
> +static const struct display_timing koe_tx26d202vm0bwa_timing = {
> + .pixelclock = { 151820000, 156720000, 159780000 },
> + .hactive = { 1920, 1920, 1920 },
> + .hfront_porch = { 105, 130, 142 },
> + .hback_porch = { 45, 70, 82 },
> + .hsync_len = { 30, 30, 30 },
> + .vactive = { 1200, 1200, 1200},
> + .vfront_porch = { 3, 5, 10 },
> + .vback_porch = { 2, 5, 10 },
> + .vsync_len = { 5, 5, 5 },
> +};
> +
> +static const struct panel_desc koe_tx26d202vm0bwa = {
> + .timings = &koe_tx26d202vm0bwa_timing,
> + .num_timings = 1,
> + .bpc = 8,
> + .size = {
> + .width = 217,
> + .height = 136,
> + },
> + .delay = {
> + .prepare = 1000,
> + .enable = 1000,
> + .unprepare = 1000,
> + .disable = 1000,
Ouch 1s for each delay is huge. Nevertheless it matches the specs so,
the series is:
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Sam, Thierry I assume you'll merge the series. Let me know if I should
pick it up.
-Emil
^ permalink raw reply
* [PATCH] dt-bindings: usb: ti,keystone-dwc3.yaml: Improve schema
From: Roger Quadros @ 2020-06-02 12:40 UTC (permalink / raw)
To: balbi; +Cc: robh+dt, devicetree, linux-kernel, Roger Quadros
There were some review comments after the patch was integrated.
Address those.
Fixes: 1883a934e156 ("dt-bindings: usb: convert keystone-usb.txt to YAML")
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
.../bindings/usb/ti,keystone-dwc3.yaml | 47 ++++++++++++++-----
1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
index f127535feb0b..017c5883184b 100644
--- a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
@@ -11,30 +11,44 @@ maintainers:
properties:
compatible:
- oneOf:
- - const: "ti,keystone-dwc3"
- - const: "ti,am654-dwc3"
+ items:
+ - enum:
+ - "ti,keystone-dwc3"
+ - "ti,am654-dwc3"
reg:
maxItems: 1
- description: Address and length of the register set for the USB subsystem on
- the SOC.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ ranges: true
interrupts:
maxItems: 1
- description: The irq number of this device that is used to interrupt the MPU.
-
clocks:
+ $ref: /schemas/types.yaml#definitions/phandle-array
description: Clock ID for USB functional clock.
+ assigned-clocks:
+ $ref: /schemas/types.yaml#definitions/phandle-array
+
+ assigned-clock-parents:
+ $ref: /schemas/types.yaml#definitions/phandle-array
+
power-domains:
+ $ref: /schemas/types.yaml#definitions/phandle-array
description: Should contain a phandle to a PM domain provider node
and an args specifier containing the USB device id
value. This property is as per the binding,
Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
phys:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
description:
PHY specifier for the USB3.0 PHY. Some SoCs need the USB3.0 PHY
to be turned on before the controller.
@@ -44,31 +58,40 @@ properties:
items:
- const: "usb3-phy"
- dwc3:
+ dma-coherent: true
+
+ dma-ranges: true
+
+patternProperties:
+ "usb@[a-f0-9]+$":
+ type: object
description: This is the node representing the DWC3 controller instance
Documentation/devicetree/bindings/usb/dwc3.txt
required:
- compatible
- reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
- interrupts
- - clocks
+
+additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
- usb: usb@2680000 {
+ dwc3@2680000 {
compatible = "ti,keystone-dwc3";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2680000 0x10000>;
clocks = <&clkusb>;
- clock-names = "usb";
interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
ranges;
- dwc3@2690000 {
+ usb@2690000 {
compatible = "synopsys,dwc3";
reg = <0x2690000 0x70000>;
interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* Re: [PATCH 1/3] dt-bindings: usb: convert keystone-usb.txt to YAML
From: Roger Quadros @ 2020-06-02 12:36 UTC (permalink / raw)
To: Rob Herring; +Cc: balbi, vigneshr, linux-usb, devicetree, linux-kernel
In-Reply-To: <20200527013715.GA847644@bogus>
Rob,
Thanks for the review. Since this patch was already picked up I will
address the issues in a follow up patch.
cheers,
-roger
On 27/05/2020 04:37, Rob Herring wrote:
> On Wed, May 13, 2020 at 04:07:07PM +0300, Roger Quadros wrote:
>> Convert keystone-usb documentation to YAML format.
>>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>> .../devicetree/bindings/usb/keystone-usb.txt | 56 ----------------
>> .../bindings/usb/ti,keystone-dwc3.yaml | 67 +++++++++++++++++++
>> 2 files changed, 67 insertions(+), 56 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/usb/keystone-usb.txt
>> create mode 100644 Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/usb/keystone-usb.txt b/Documentation/devicetree/bindings/usb/keystone-usb.txt
>> deleted file mode 100644
>> index 77df82e36138..000000000000
>> --- a/Documentation/devicetree/bindings/usb/keystone-usb.txt
>> +++ /dev/null
>> @@ -1,56 +0,0 @@
>> -TI Keystone Soc USB Controller
>> -
>> -DWC3 GLUE
>> -
>> -Required properties:
>> - - compatible: should be
>> - "ti,keystone-dwc3" for Keystone 2 SoCs
>> - "ti,am654-dwc3" for AM654 SoC
>> - - #address-cells, #size-cells : should be '1' if the device has sub-nodes
>> - with 'reg' property.
>> - - reg : Address and length of the register set for the USB subsystem on
>> - the SOC.
>> - - interrupts : The irq number of this device that is used to interrupt the
>> - MPU.
>> - - ranges: allows valid 1:1 translation between child's address space and
>> - parent's address space.
>> -
>> -SoC-specific Required Properties:
>> -The following are mandatory properties for Keystone 2 66AK2HK, 66AK2L and 66AK2E
>> -SoCs only:
>> -
>> -- clocks: Clock ID for USB functional clock.
>> -- clock-names: Must be "usb".
>> -
>> -
>> -The following are mandatory properties for 66AK2G and AM654:
>> -
>> -- power-domains: Should contain a phandle to a PM domain provider node
>> - and an args specifier containing the USB device id
>> - value. This property is as per the binding,
>> - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
>> -
>> -Sub-nodes:
>> -The dwc3 core should be added as subnode to Keystone DWC3 glue.
>> -- dwc3 :
>> - The binding details of dwc3 can be found in:
>> - Documentation/devicetree/bindings/usb/dwc3.txt
>> -
>> -Example:
>> - usb: usb@2680000 {
>> - compatible = "ti,keystone-dwc3";
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> - reg = <0x2680000 0x10000>;
>> - clocks = <&clkusb>;
>> - clock-names = "usb";
>> - interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
>> - ranges;
>> -
>> - dwc3@2690000 {
>> - compatible = "synopsys,dwc3";
>> - reg = <0x2690000 0x70000>;
>> - interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
>> - usb-phy = <&usb_phy>, <&usb_phy>;
>> - };
>> - };
>> diff --git a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
>> new file mode 100644
>> index 000000000000..14d2fe329b93
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
>> @@ -0,0 +1,67 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: TI Keystone Soc USB Controller
>> +
>> +maintainers:
>> + - Roger Quadros <rogerq@ti.com>
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - const: "ti,keystone-dwc3"
>> + - const: "ti,am654-dwc3"
>
> Use enum rather than oneOf+const.
>
>> +
>> + reg:
>> + maxItems: 1
>> + description: Address and length of the register set for the USB subsystem on
>> + the SOC.
>> +
>> + interrupts:
>> + maxItems: 1
>> + description: The irq number of this device that is used to interrupt the MPU.
>
> No need for genericish descriptions when a single item.
>
>> +
>> +
>> + clocks:
>> + description: Clock ID for USB functional clock.
>
> How many?
>
>> +
>> + power-domains:
>> + description: Should contain a phandle to a PM domain provider node
>> + and an args specifier containing the USB device id
>> + value. This property is as per the binding,
>> + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
>
> How many?
>
>> +
>> + dwc3:
>
> This doesn't work because there's a unit address. You need a pattern.
>
>> + description: This is the node representing the DWC3 controller instance
>> + Documentation/devicetree/bindings/usb/dwc3.txt
>
> type: object
>
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - interrupts
>> + - clocks
>
> additionalProperties: false
>
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> + usb: usb@2680000 {
>> + compatible = "ti,keystone-dwc3";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>
> These have to be documented.
>
>> + reg = <0x2680000 0x10000>;
>> + clocks = <&clkusb>;
>> + clock-names = "usb";
>> + interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
>> + ranges;
>
> This too.
>
>> +
>> + dwc3@2690000 {
>> + compatible = "synopsys,dwc3";
>> + reg = <0x2690000 0x70000>;
>> + interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
>> + usb-phy = <&usb_phy>, <&usb_phy>;
>> + };
>> + };
>> --
>> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
>> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>>
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply
* Re: [PATCH v4 4/5] regulator: qcom: Add labibb driver
From: Mark Brown @ 2020-06-02 12:25 UTC (permalink / raw)
To: Sumit Semwal
Cc: agross, Bjorn Andersson, lgirdwood, robh+dt, Nisha Kumari,
linux-arm-msm, LKML, devicetree, kgunda, Rajendra Nayak
In-Reply-To: <CAO_48GGgNUGosN2PiL=U5JkR3Bh5wNK3N4xYYML1UwmdfDPRww@mail.gmail.com>
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On Tue, Jun 02, 2020 at 05:40:45PM +0530, Sumit Semwal wrote:
> On Tue, 2 Jun 2020 at 17:02, Mark Brown <broonie@kernel.org> wrote:
> > On Tue, Jun 02, 2020 at 03:39:23PM +0530, Sumit Semwal wrote:
> > This should be a get_status() callback...
> From my (limited) understanding of downstream code, it seemed like for
> this set of regulators, the 'enabled' check is done via the
> 'REG_LABIBB_STATUS1 reg; for some reason, not via the same enable_reg
> / enable_mask ones. That's why I used it as is_enabled() callback.
> I will try and check with the QC folks to clarify this point about
> their hardware.
The way this is functioning at the minute the downstream code is just
buggy.
> > ...is_enabled() should just be regulator_is_enabled_regmap() and these
> > functions should just be removed entirely, you can use the regmap
> > operations directly as the ops without the wrapper.
> The 2 wrappers are a precursor to the next patch, where we keep track
> of regulator's enable status to check during SC handling.
Add the functions when they're useful, not before. TBH if the register
is write only you're probably better off adding a register cache.
> > > + match = of_match_device(qcom_labibb_match, &pdev->dev);
> > > + if (!match)
> > > + return -ENODEV;
> > > +
> > > + for (reg_data = match->data; reg_data->name; reg_data++) {
> > > + child = of_get_child_by_name(pdev->dev.of_node, reg_data->name);
> > > +
> > > + if (WARN_ON(child == NULL))
> > > + return -EINVAL;
> >
> > This feels like the DT bindings are confused - why do we need to search
> > like this?
> The WARN_ON? This was suggested by Bjorn to catch the case where the
> DT binding for a PMIC instantiates only one of the regulators.
No, this whole loop - why this whole match and get child stuff?
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^ permalink raw reply
* Re: [PATCH v4 5/5] regulator: qcom: labibb: Add SC interrupt handling
From: Mark Brown @ 2020-06-02 12:22 UTC (permalink / raw)
To: Sumit Semwal
Cc: agross, bjorn.andersson, lgirdwood, robh+dt, nishakumari,
linux-arm-msm, linux-kernel, devicetree, kgunda, rnayak
In-Reply-To: <20200602100924.26256-6-sumit.semwal@linaro.org>
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On Tue, Jun 02, 2020 at 03:39:24PM +0530, Sumit Semwal wrote:
> static int qcom_labibb_regulator_enable(struct regulator_dev *rdev)
> {
> - return regulator_enable_regmap(rdev);
> + int ret;
> + struct labibb_regulator *reg = rdev_get_drvdata(rdev);
> +
> + ret = regulator_enable_regmap(rdev);
> + if (ret >= 0)
> + reg->enabled = true;
Can we not read the register we just wrote to here?
> + /*
> + * The SC(short circuit) fault would trigger PBS(Portable Batch
> + * System) to disable regulators for protection. This would
> + * cause the SC_DETECT status being cleared so that it's not
> + * able to get the SC fault status.
> + * Check if the regulator is enabled in the driver but
> + * disabled in hardware, this means a SC fault had happened
> + * and SCP handling is completed by PBS.
> + */
> + if (!in_sc_err) {
> +
> + reg = labibb_reg->base + REG_LABIBB_ENABLE_CTL;
> +
> + ret = regmap_read_poll_timeout(labibb_reg->regmap,
> + reg, val,
> + !(val & LABIBB_CONTROL_ENABLE),
> + POLLING_SCP_DONE_INTERVAL_US,
> + POLLING_SCP_TIMEOUT);
Why do we need a timeout here?
> + NULL);
> + regulator_unlock(labibb_reg->rdev);
> + }
> + return IRQ_HANDLED;
This returns IRQ_HANDLED even if we didn't detect an interrupt source...
Especially given the need to check to see if the regulator was turned
off by the hardware it seems like there must be some false positives.
> + } else {
> + ret = devm_request_threaded_irq(reg->dev,
> + sc_irq,
> + NULL, labibb_sc_err_handler,
> + IRQF_ONESHOT,
> + "sc-err", reg);
This looks like we're requesting the interrupt before we register the
regulator which means the interrupt might fire without the regulator
being there. The order of registration should be reversed.
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^ permalink raw reply
* Re: Security Random Number Generator support
From: Ard Biesheuvel @ 2020-06-02 12:14 UTC (permalink / raw)
To: Neal Liu
Cc: Matt Mackall, Herbert Xu, Rob Herring, Matthias Brugger,
Sean Wang, Arnd Bergmann, Greg Kroah-Hartman,
Linux Crypto Mailing List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-mediatek, lkml, wsd_upstream, Crystal Guo
In-Reply-To: <1591085678-22764-1-git-send-email-neal.liu@mediatek.com>
On Tue, 2 Jun 2020 at 10:15, Neal Liu <neal.liu@mediatek.com> wrote:
>
> These patch series introduce a security random number generator
> which provides a generic interface to get hardware rnd from Secure
> state. The Secure state can be Arm Trusted Firmware(ATF), Trusted
> Execution Environment(TEE), or even EL2 hypervisor.
>
> Patch #1..2 adds sec-rng kernel driver for Trustzone based SoCs.
> For security awareness SoCs on ARMv8 with TrustZone enabled,
> peripherals like entropy sources is not accessible from normal world
> (linux) and rather accessible from secure world (HYP/ATF/TEE) only.
> This driver aims to provide a generic interface to Arm Trusted
> Firmware or Hypervisor rng service.
>
>
> changes since v1:
> - rename mt67xx-rng to mtk-sec-rng since all MediaTek ARMv8 SoCs can reuse
> this driver.
> - refine coding style and unnecessary check.
>
> changes since v2:
> - remove unused comments.
> - remove redundant variable.
>
> changes since v3:
> - add dt-bindings for MediaTek rng with TrustZone enabled.
> - revise HWRNG SMC call fid.
>
> changes since v4:
> - move bindings to the arm/firmware directory.
> - revise driver init flow to check more property.
>
> changes since v5:
> - refactor to more generic security rng driver which
> is not platform specific.
>
> *** BLURB HERE ***
>
> Neal Liu (2):
> dt-bindings: rng: add bindings for sec-rng
> hwrng: add sec-rng driver
>
There is no reason to model a SMC call as a driver, and represent it
via a DT node like this.
It would be much better if this SMC interface is made truly generic,
and wired into the arch_get_random() interface, which can be used much
earlier.
> .../devicetree/bindings/rng/sec-rng.yaml | 53 ++++++
> drivers/char/hw_random/Kconfig | 13 ++
> drivers/char/hw_random/Makefile | 1 +
> drivers/char/hw_random/sec-rng.c | 155 ++++++++++++++++++
> 4 files changed, 222 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rng/sec-rng.yaml
> create mode 100644 drivers/char/hw_random/sec-rng.c
>
> --
> 2.18.0
^ permalink raw reply
* RE: [PATCH v7 21/24] iommu/arm-smmu-v3: Add stall support for platform devices
From: Shameerali Kolothum Thodi @ 2020-06-02 12:12 UTC (permalink / raw)
To: Jean-Philippe Brucker
Cc: devicetree@vger.kernel.org, kevin.tian@intel.com,
fenghua.yu@intel.com, linux-pci@vger.kernel.org,
felix.kuehling@amd.com, robin.murphy@arm.com,
christian.koenig@amd.com, hch@infradead.org, jgg@ziepe.ca,
iommu@lists.linux-foundation.org, catalin.marinas@arm.com,
zhangfei.gao@linaro.org, will@kernel.org, linux-mm@kvack.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20200602114611.GB1029680@myrica>
> -----Original Message-----
> From: linux-arm-kernel [mailto:linux-arm-kernel-bounces@lists.infradead.org]
> On Behalf Of Jean-Philippe Brucker
> Sent: 02 June 2020 12:46
> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
> Cc: devicetree@vger.kernel.org; kevin.tian@intel.com; fenghua.yu@intel.com;
> linux-pci@vger.kernel.org; felix.kuehling@amd.com; robin.murphy@arm.com;
> christian.koenig@amd.com; hch@infradead.org; jgg@ziepe.ca;
> iommu@lists.linux-foundation.org; catalin.marinas@arm.com;
> zhangfei.gao@linaro.org; will@kernel.org; linux-mm@kvack.org;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v7 21/24] iommu/arm-smmu-v3: Add stall support for
> platform devices
>
> On Tue, Jun 02, 2020 at 10:31:29AM +0000, Shameerali Kolothum Thodi wrote:
> > Hi Jean,
> >
> > > -----Original Message-----
> > > From: linux-arm-kernel
> > > [mailto:linux-arm-kernel-bounces@lists.infradead.org]
> > > On Behalf Of Jean-Philippe Brucker
> > > Sent: 02 June 2020 10:39
> > > To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
> > > Cc: devicetree@vger.kernel.org; kevin.tian@intel.com;
> > > will@kernel.org; fenghua.yu@intel.com; jgg@ziepe.ca;
> > > linux-pci@vger.kernel.org; felix.kuehling@amd.com;
> > > hch@infradead.org; linux-mm@kvack.org;
> > > iommu@lists.linux-foundation.org; catalin.marinas@arm.com;
> > > zhangfei.gao@linaro.org; robin.murphy@arm.com;
> > > christian.koenig@amd.com; linux-arm-kernel@lists.infradead.org
> > > Subject: Re: [PATCH v7 21/24] iommu/arm-smmu-v3: Add stall support
> > > for platform devices
> > >
> > > Hi Shameer,
> > >
> > > On Mon, Jun 01, 2020 at 12:42:15PM +0000, Shameerali Kolothum Thodi
> > > wrote:
> > > > > /* IRQ and event handlers */
> > > > > +static int arm_smmu_handle_evt(struct arm_smmu_device *smmu,
> > > > > +u64
> > > > > +*evt) {
> > > > > + int ret;
> > > > > + u32 perm = 0;
> > > > > + struct arm_smmu_master *master;
> > > > > + bool ssid_valid = evt[0] & EVTQ_0_SSV;
> > > > > + u8 type = FIELD_GET(EVTQ_0_ID, evt[0]);
> > > > > + u32 sid = FIELD_GET(EVTQ_0_SID, evt[0]);
> > > > > + struct iommu_fault_event fault_evt = { };
> > > > > + struct iommu_fault *flt = &fault_evt.fault;
> > > > > +
> > > > > + /* Stage-2 is always pinned at the moment */
> > > > > + if (evt[1] & EVTQ_1_S2)
> > > > > + return -EFAULT;
> > > > > +
> > > > > + master = arm_smmu_find_master(smmu, sid);
> > > > > + if (!master)
> > > > > + return -EINVAL;
> > > > > +
> > > > > + if (evt[1] & EVTQ_1_READ)
> > > > > + perm |= IOMMU_FAULT_PERM_READ;
> > > > > + else
> > > > > + perm |= IOMMU_FAULT_PERM_WRITE;
> > > > > +
> > > > > + if (evt[1] & EVTQ_1_EXEC)
> > > > > + perm |= IOMMU_FAULT_PERM_EXEC;
> > > > > +
> > > > > + if (evt[1] & EVTQ_1_PRIV)
> > > > > + perm |= IOMMU_FAULT_PERM_PRIV;
> > > > > +
> > > > > + if (evt[1] & EVTQ_1_STALL) {
> > > > > + flt->type = IOMMU_FAULT_PAGE_REQ;
> > > > > + flt->prm = (struct iommu_fault_page_request) {
> > > > > + .flags = IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE,
> > > > > + .pasid = FIELD_GET(EVTQ_0_SSID, evt[0]),
> > > > > + .grpid = FIELD_GET(EVTQ_1_STAG, evt[1]),
> > > > > + .perm = perm,
> > > > > + .addr = FIELD_GET(EVTQ_2_ADDR, evt[2]),
> > > > > + };
> > > > > +
> > > >
> > > > > + if (ssid_valid)
> > > > > + flt->prm.flags |=
> > > IOMMU_FAULT_PAGE_REQUEST_PASID_VALID;
> > > >
> > > > Do we need to set this for STALL mode only support? I had an issue
> > > > with this being set on a vSVA POC based on our D06 zip
> > > > device(which is a "fake " pci dev that supports STALL mode but no
> > > > PRI). The issue is, CMDQ_OP_RESUME doesn't have any ssid or SSV
> > > > params and works on sid
> > > and stag only.
> > >
> > > I don't understand the problem, arm_smmu_page_response() doesn't set
> > > SSID or SSV when sending a CMDQ_OP_RESUME. Could you detail the flow
> > > of a stall event and RESUME command in your prototype? Are you
> > > getting issues with the host driver or the guest driver?
> >
> > The issue is on the host side iommu_page_response(). The flow is
> > something like below.
> >
> > Stall: Host:-
> >
> > arm_smmu_handle_evt()
> > iommu_report_device_fault()
> > vfio_pci_iommu_dev_fault_handler()
> >
> > Stall: Qemu:-
> >
> > vfio_dma_fault_notifier_handler()
> > inject_faults()
> > smmuv3_inject_faults()
> >
> > Stall: Guest:-
> >
> > arm_smmu_handle_evt()
> > iommu_report_device_fault()
> > iommu_queue_iopf
> > ...
> > iopf_handle_group()
> > iopf_handle_single()
> > handle_mm_fault()
> > iopf_complete()
> > iommu_page_response()
> > arm_smmu_page_response()
> > arm_smmu_cmdq_issue_cmd(CMDQ_OP_RESUME)
> >
> > Resume: Qemu:-
> >
> > smmuv3_cmdq_consume(SMMU_CMD_RESUME)
> > smmuv3_notify_page_resp()
> > vfio:ioctl(page_response) --> struct iommu_page_response is filled
> > with only version, grpid and code.
> >
> > Resume: Host:-
> > ioctl(page_response)
> > iommu_page_response() --> fails as the pending req has PASID_VALID
> flag
> > set and it checks for a match.
>
> I believe the fix needs to be here. It's also wrong for PRI since not all PCIe
> endpoint require a PASID in the page response. Could you try the attached
> patch?
Going through the patch, yes, that will definitely fix the issue. But isn't it better if
the request itself indicate whether it expects a response msg with a valid pasid or
not? The response msg can come from userspace as well(vSVA) and if for some reason
doesn't set it for a req that expects pasid then it should be an error, right? In the temp
fix I had, I introduced another flag to indicate the endpoint has PRI support or not and
used that to verify the pasid requirement. But for the PRI case you mentioned
above, not sure it is easy to get that information or not. May be I am complicating things
here :)
Thanks,
Shameer
> Thanks,
> Jean
>
> > arm_smmu_page_response()
> >
> > Hope the above is clear.
> >
> > > We do need to forward the SSV flag all the way to the guest driver,
> > > so the guest can find the faulting address space using the SSID.
> > > Once the guest handled the fault, then we don't send the SSID back
> > > to the host as part of the RESUME command.
> >
> > True, the guest requires SSV flag to handle the page fault. But, as
> > shown in the flow above, the issue is on the host side
> > iommu_page_response() where it searches for a matching pending req
> > based on pasid. Not sure we can bypass that and call
> > arm_smmu_page_response() directly but then have to delete the pending req
> from the list as well.
> >
> > Please let me know if there is a better way to handle the host side
> > page response.
> >
> > Thanks,
> > Shameer
> >
> > > Thanks,
> > > Jean
> > >
> > > > Hence, it is difficult for
> > > > Qemu SMMUv3 to populate this fields while preparing a page
> > > > response. I can see that this flag is being checked in
> > > > iopf_handle_single() (patch
> > > > 04/24) as well. For POC, I used a temp fix[1] to work around this.
> > > > Please let
> > > me know your thoughts.
> > > >
> > > > Thanks,
> > > > Shameer
> > > >
> > > > 1.
> > > > https://github.com/hisilicon/kernel-dev/commit/99ff96146e924055f38
> > > > d97a
> > > > 5897e4becfa378d15
> > > >
> > >
> > > _______________________________________________
> > > linux-arm-kernel mailing list
> > > linux-arm-kernel@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v4 4/5] regulator: qcom: Add labibb driver
From: Sumit Semwal @ 2020-06-02 12:10 UTC (permalink / raw)
To: Mark Brown
Cc: agross, Bjorn Andersson, lgirdwood, robh+dt, Nisha Kumari,
linux-arm-msm, LKML, devicetree, kgunda, Rajendra Nayak
In-Reply-To: <20200602113241.GE5684@sirena.org.uk>
Hi Mark,
Thank you very much for reviewing.
On Tue, 2 Jun 2020 at 17:02, Mark Brown <broonie@kernel.org> wrote:
>
> On Tue, Jun 02, 2020 at 03:39:23PM +0530, Sumit Semwal wrote:
>
> > +static int qcom_labibb_regulator_is_enabled(struct regulator_dev *rdev)
> > +{
> > + int ret;
> > + unsigned int val;
> > + struct labibb_regulator *reg = rdev_get_drvdata(rdev);
> > +
> > + ret = regmap_read(reg->regmap, reg->base + REG_LABIBB_STATUS1, &val);
> > + if (ret < 0) {
> > + dev_err(reg->dev, "Read register failed ret = %d\n", ret);
> > + return ret;
> > + }
> > + return !!(val & LABIBB_STATUS1_VREG_OK_BIT);
> > +}
>
> This should be a get_status() callback...
>
From my (limited) understanding of downstream code, it seemed like for
this set of regulators, the 'enabled' check is done via the
'REG_LABIBB_STATUS1 reg; for some reason, not via the same enable_reg
/ enable_mask ones. That's why I used it as is_enabled() callback.
I will try and check with the QC folks to clarify this point about
their hardware.
> > +static int qcom_labibb_regulator_enable(struct regulator_dev *rdev)
> > +{
> > + return regulator_enable_regmap(rdev);
> > +}
> > +
> > +static int qcom_labibb_regulator_disable(struct regulator_dev *rdev)
> > +{
> > + return regulator_disable_regmap(rdev);
> > +}
>
> ...is_enabled() should just be regulator_is_enabled_regmap() and these
> functions should just be removed entirely, you can use the regmap
> operations directly as the ops without the wrapper.
The 2 wrappers are a precursor to the next patch, where we keep track
of regulator's enable status to check during SC handling.
>
> > + match = of_match_device(qcom_labibb_match, &pdev->dev);
> > + if (!match)
> > + return -ENODEV;
> > +
> > + for (reg_data = match->data; reg_data->name; reg_data++) {
> > + child = of_get_child_by_name(pdev->dev.of_node, reg_data->name);
> > +
> > + if (WARN_ON(child == NULL))
> > + return -EINVAL;
>
> This feels like the DT bindings are confused - why do we need to search
> like this?
The WARN_ON? This was suggested by Bjorn to catch the case where the
DT binding for a PMIC instantiates only one of the regulators.
>
> > + dev_info(dev, "Registering %s regulator\n", child->full_name);
>
> This is noise, remove it. The regulator framework will announce new
> regulators anyway.
Agreed. will remove in the next iteration.
Best,
Sumit.
^ permalink raw reply
* Re: [PATCH v4 1/5] regulator: Allow regulators to verify enabled during enable()
From: Sumit Semwal @ 2020-06-02 11:57 UTC (permalink / raw)
To: Mark Brown
Cc: agross, Bjorn Andersson, lgirdwood, robh+dt, Nisha Kumari,
linux-arm-msm, LKML, devicetree, kgunda, Rajendra Nayak
In-Reply-To: <20200602112415.GD5684@sirena.org.uk>
Hi Mark,
Thanks for the review!
On Tue, 2 Jun 2020 at 16:54, Mark Brown <broonie@kernel.org> wrote:
>
> On Tue, Jun 02, 2020 at 03:39:20PM +0530, Sumit Semwal wrote:
>
> > +
> > + if (time_remaining <= 0) {
> > + rdev_err(rdev, "Enabled check failed.\n");
> > + return -ETIMEDOUT;
>
> s/failed/timed out/
Ack
>
> > + * @poll_enabled_time: Maximum time (in uS) to poll if the regulator is
> > + * actually enabled, after enable() call
> > + *
>
> This comment needs updating to reflect the new implementation.
Yes, I will update.
Best,
Sumit.
^ permalink raw reply
* [PATCH v5 01/11] PCI: qcom: Add missing ipq806x clocks in PCIe driver
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, Sham Muthayyan, Rob Herring, Andy Gross,
Bjorn Andersson, Bjorn Helgaas, Mark Rutland, Stanimir Varbanov,
Lorenzo Pieralisi, Andrew Murray, Philipp Zabel, linux-arm-msm,
linux-pci, devicetree, linux-kernel
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>
Aux and Ref clk are missing in PCIe qcom driver. Add support for this
optional clks for ipq8064/apq8064 SoC.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++----
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 5ea527a6bd9f..4bf93ab8c7a7 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
struct clk *core_clk;
struct clk *phy_clk;
+ struct clk *aux_clk;
+ struct clk *ref_clk;
struct reset_control *pci_reset;
struct reset_control *axi_reset;
struct reset_control *ahb_reset;
@@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->phy_clk))
return PTR_ERR(res->phy_clk);
+ res->aux_clk = devm_clk_get_optional(dev, "aux");
+ if (IS_ERR(res->aux_clk))
+ return PTR_ERR(res->aux_clk);
+
+ res->ref_clk = devm_clk_get_optional(dev, "ref");
+ if (IS_ERR(res->ref_clk))
+ return PTR_ERR(res->ref_clk);
+
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
if (IS_ERR(res->pci_reset))
return PTR_ERR(res->pci_reset);
@@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
clk_disable_unprepare(res->phy_clk);
+ clk_disable_unprepare(res->aux_clk);
+ clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
}
@@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_assert_ahb;
}
+ ret = clk_prepare_enable(res->core_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable core clock\n");
+ goto err_clk_core;
+ }
+
ret = clk_prepare_enable(res->phy_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable phy clock\n");
goto err_clk_phy;
}
- ret = clk_prepare_enable(res->core_clk);
+ ret = clk_prepare_enable(res->aux_clk);
if (ret) {
- dev_err(dev, "cannot prepare/enable core clock\n");
- goto err_clk_core;
+ dev_err(dev, "cannot prepare/enable aux clock\n");
+ goto err_clk_aux;
+ }
+
+ ret = clk_prepare_enable(res->ref_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable ref clock\n");
+ goto err_clk_ref;
}
ret = reset_control_deassert(res->ahb_reset);
@@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return 0;
err_deassert_ahb:
- clk_disable_unprepare(res->core_clk);
-err_clk_core:
+ clk_disable_unprepare(res->ref_clk);
+err_clk_ref:
+ clk_disable_unprepare(res->aux_clk);
+err_clk_aux:
clk_disable_unprepare(res->phy_clk);
err_clk_phy:
+ clk_disable_unprepare(res->core_clk);
+err_clk_core:
clk_disable_unprepare(res->iface_clk);
err_assert_ahb:
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
--
2.25.1
^ permalink raw reply related
* [PATCH v5 04/11] PCI: qcom: Add missing reset for ipq806x
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, Sham Muthayyan, stable, Rob Herring, Philipp Zabel,
Andy Gross, Bjorn Andersson, Bjorn Helgaas, Mark Rutland,
Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>
Add missing ext reset used by ipq8064 SoC in PCIe qcom driver.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v4.5+
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
---
drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4512c2c5f61c..4dab5ef630cc 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 {
struct reset_control *ahb_reset;
struct reset_control *por_reset;
struct reset_control *phy_reset;
+ struct reset_control *ext_reset;
struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
};
@@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->por_reset))
return PTR_ERR(res->por_reset);
+ res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
+ if (IS_ERR(res->ext_reset))
+ return PTR_ERR(res->ext_reset);
+
res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
return PTR_ERR_OR_ZERO(res->phy_reset);
}
@@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
+ reset_control_assert(res->ext_reset);
reset_control_assert(res->phy_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
@@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_deassert_ahb;
}
+ ret = reset_control_deassert(res->ext_reset);
+ if (ret) {
+ dev_err(dev, "cannot deassert ext reset\n");
+ goto err_deassert_ahb;
+ }
+
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
val &= ~BIT(0);
--
2.25.1
^ permalink raw reply related
* [PATCH v5 02/11] dt-bindings: PCI: qcom: Add missing clks
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, Rob Herring, Andy Gross, Bjorn Andersson,
Bjorn Helgaas, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>
Document missing clks used in ipq8064 SoC.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 981b4de12807..becdbdc0fffa 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -90,6 +90,8 @@
Definition: Should contain the following entries
- "core" Clocks the pcie hw block
- "phy" Clocks the pcie PHY block
+ - "aux" Clocks the pcie AUX block
+ - "ref" Clocks the pcie ref block
- clock-names:
Usage: required for apq8084/ipq4019
Value type: <stringlist>
@@ -277,8 +279,10 @@
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc PCIE_A_CLK>,
<&gcc PCIE_H_CLK>,
- <&gcc PCIE_PHY_CLK>;
- clock-names = "core", "iface", "phy";
+ <&gcc PCIE_PHY_CLK>,
+ <&gcc PCIE_AUX_CLK>,
+ <&gcc PCIE_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
resets = <&gcc PCIE_ACLK_RESET>,
<&gcc PCIE_HCLK_RESET>,
<&gcc PCIE_POR_RESET>,
--
2.25.1
^ permalink raw reply related
* [PATCH v5 05/11] dt-bindings: PCI: qcom: Add ext reset
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, Rob Herring, Andy Gross, Bjorn Andersson,
Bjorn Helgaas, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>
Document ext reset used in ipq8064 SoC by qcom PCIe driver.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index becdbdc0fffa..6efcef040741 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -179,6 +179,7 @@
- "pwr" PWR reset
- "ahb" AHB reset
- "phy_ahb" PHY AHB reset
+ - "ext" EXT reset
- reset-names:
Usage: required for ipq8074
@@ -287,8 +288,9 @@
<&gcc PCIE_HCLK_RESET>,
<&gcc PCIE_POR_RESET>,
<&gcc PCIE_PCI_RESET>,
- <&gcc PCIE_PHY_RESET>;
- reset-names = "axi", "ahb", "por", "pci", "phy";
+ <&gcc PCIE_PHY_RESET>,
+ <&gcc PCIE_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
pinctrl-0 = <&pcie_pins_default>;
pinctrl-names = "default";
};
--
2.25.1
^ permalink raw reply related
* [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, stable, Rob Herring, Andy Gross, Bjorn Andersson,
Bjorn Helgaas, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>
Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
needed on some ipq8064 based device (Netgear R7800 for example). Without
this the system locks on kernel load.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v4.5+
Reviewed-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 27 ++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index f2ea1ab6f584..f5398b0d270c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -46,6 +46,9 @@
#define PCIE20_PARF_PHY_CTRL 0x40
#define PCIE20_PARF_PHY_REFCLK 0x4C
+#define PHY_REFCLK_SSP_EN BIT(16)
+#define PHY_REFCLK_USE_PAD BIT(12)
+
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
@@ -77,6 +80,18 @@
#define DBI_RO_WR_EN 1
#define PERST_DELAY_US 1000
+/* PARF registers */
+#define PCIE20_PARF_PCS_DEEMPH 0x34
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
+
+#define PCIE20_PARF_PCS_SWING 0x38
+#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
+#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
+
+#define PCIE20_PARF_CONFIG_BITS 0x50
+#define PHY_RX0_EQ(x) ((x) << 24)
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
@@ -293,6 +308,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
+ struct device_node *node = dev->of_node;
u32 val;
int ret;
@@ -347,6 +363,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
val &= ~BIT(0);
writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
+ writel(PCS_SWING_TX_SWING_FULL(120) |
+ PCS_SWING_TX_SWING_LOW(120),
+ pcie->parf + PCIE20_PARF_PCS_SWING);
+ writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
+ }
+
/* enable external reference clock */
val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
val |= BIT(16);
--
2.25.1
^ permalink raw reply related
* [PATCH v5 08/11] PCI: qcom: Add support for tx term offset for rev 2.1.0
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, Sham Muthayyan, stable, Andy Gross, Bjorn Andersson,
Bjorn Helgaas, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>
Add tx term offset support to pcie qcom driver need in some revision of
the ipq806x SoC. Ipq8064 needs tx term offset set to 7.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v4.5+
---
drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index f5398b0d270c..2cd6d1456210 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -45,6 +45,9 @@
#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
#define PCIE20_PARF_PHY_CTRL 0x40
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
+
#define PCIE20_PARF_PHY_REFCLK 0x4C
#define PHY_REFCLK_SSP_EN BIT(16)
#define PHY_REFCLK_USE_PAD BIT(12)
@@ -374,9 +377,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
}
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ /* set TX termination offset */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
+ val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+ }
+
/* enable external reference clock */
val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
- val |= BIT(16);
+ val &= ~PHY_REFCLK_USE_PAD;
+ val |= PHY_REFCLK_SSP_EN;
writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
/* wait for clock acquisition */
--
2.25.1
^ permalink raw reply related
* [PATCH v5 09/11] PCI: qcom: Add ipq8064 rev2 variant
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, Andy Gross, Bjorn Andersson, Bjorn Helgaas,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>
Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit
different offset based on the revision.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 2cd6d1456210..259b627bf890 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -366,7 +366,8 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
val &= ~BIT(0);
writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
- if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
+ of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
@@ -1464,6 +1465,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
{ .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
+ { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
--
2.25.1
^ permalink raw reply related
* [PATCH v5 10/11] dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, Rob Herring, Andy Gross, Bjorn Andersson,
Bjorn Helgaas, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>
Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset.
In ipq8064 phy_tx0_term_offset is 7. In ipq8064 v2 other SoC it's set to 0
by default.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 6efcef040741..02bc81bb8b2d 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -5,6 +5,7 @@
Value type: <stringlist>
Definition: Value should contain
- "qcom,pcie-ipq8064" for ipq8064
+ - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
- "qcom,pcie-apq8064" for apq8064
- "qcom,pcie-apq8084" for apq8084
- "qcom,pcie-msm8996" for msm8996 or apq8096
--
2.25.1
^ permalink raw reply related
* [PATCH v5 11/11] PCI: qcom: Add Force GEN1 support
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Sham Muthayyan, Ansuel Smith, Rob Herring, Andy Gross,
Bjorn Andersson, Bjorn Helgaas, Mark Rutland, Stanimir Varbanov,
Lorenzo Pieralisi, Andrew Murray, Philipp Zabel, linux-arm-msm,
linux-pci, devicetree, linux-kernel
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>
From: Sham Muthayyan <smuthayy@codeaurora.org>
Add Force GEN1 support needed in some ipq8064 board that needs to limit
some PCIe line to gen1 for some hardware limitation. This is set by the
max-link-speed binding and needed by some soc based on ipq8064. (for
example Netgear R7800 router)
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 259b627bf890..0ce15d53c46e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -27,6 +27,7 @@
#include <linux/slab.h>
#include <linux/types.h>
+#include "../../pci.h"
#include "pcie-designware.h"
#define PCIE20_PARF_SYS_CTRL 0x00
@@ -99,6 +100,8 @@
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
+
#define DEVICE_TYPE_RC 0x4
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
@@ -195,6 +198,7 @@ struct qcom_pcie {
struct phy *phy;
struct gpio_desc *reset;
const struct qcom_pcie_ops *ops;
+ int gen;
};
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
@@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
/* wait for clock acquisition */
usleep_range(1000, 1500);
+ if (pcie->gen == 1) {
+ val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
+ val |= 1;
+ writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
+ }
/* Set the Max TLP size to 2K, instead of using default of 4K */
writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
@@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct platform_device *pdev)
goto err_pm_runtime_put;
}
+ pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
+ if (pcie->gen < 0)
+ pcie->gen = 2;
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
pcie->parf = devm_ioremap_resource(dev, res);
if (IS_ERR(pcie->parf)) {
--
2.25.1
^ permalink raw reply related
* [PATCH v5 06/11] PCI: qcom: Use bulk clk api and assert on error
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, Rob Herring, Andy Gross, Bjorn Andersson,
Bjorn Helgaas, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>
Rework 2.1.0 revision to use bulk clk api and fix missing assert on
reset_control_deassert error.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 131 +++++++++----------------
1 file changed, 46 insertions(+), 85 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4dab5ef630cc..f2ea1ab6f584 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -84,12 +84,9 @@
#define DEVICE_TYPE_RC 0x4
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
+#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
struct qcom_pcie_resources_2_1_0 {
- struct clk *iface_clk;
- struct clk *core_clk;
- struct clk *phy_clk;
- struct clk *aux_clk;
- struct clk *ref_clk;
+ struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
struct reset_control *pci_reset;
struct reset_control *axi_reset;
struct reset_control *ahb_reset;
@@ -237,25 +234,21 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (ret)
return ret;
- res->iface_clk = devm_clk_get(dev, "iface");
- if (IS_ERR(res->iface_clk))
- return PTR_ERR(res->iface_clk);
-
- res->core_clk = devm_clk_get(dev, "core");
- if (IS_ERR(res->core_clk))
- return PTR_ERR(res->core_clk);
-
- res->phy_clk = devm_clk_get(dev, "phy");
- if (IS_ERR(res->phy_clk))
- return PTR_ERR(res->phy_clk);
+ res->clks[0].id = "iface";
+ res->clks[1].id = "core";
+ res->clks[2].id = "phy";
+ res->clks[3].id = "aux";
+ res->clks[4].id = "ref";
- res->aux_clk = devm_clk_get_optional(dev, "aux");
- if (IS_ERR(res->aux_clk))
- return PTR_ERR(res->aux_clk);
+ /* iface, core, phy are required */
+ ret = devm_clk_bulk_get(dev, 3, res->clks);
+ if (ret < 0)
+ return ret;
- res->ref_clk = devm_clk_get_optional(dev, "ref");
- if (IS_ERR(res->ref_clk))
- return PTR_ERR(res->ref_clk);
+ /* aux, ref are optional */
+ ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
+ if (ret < 0)
+ return ret;
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
if (IS_ERR(res->pci_reset))
@@ -285,17 +278,13 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
- clk_disable_unprepare(res->phy_clk);
+ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
reset_control_assert(res->pci_reset);
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
reset_control_assert(res->ext_reset);
reset_control_assert(res->phy_reset);
- clk_disable_unprepare(res->iface_clk);
- clk_disable_unprepare(res->core_clk);
- clk_disable_unprepare(res->aux_clk);
- clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
}
@@ -313,36 +302,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return ret;
}
- ret = reset_control_assert(res->ahb_reset);
- if (ret) {
- dev_err(dev, "cannot assert ahb reset\n");
- goto err_assert_ahb;
- }
-
- ret = clk_prepare_enable(res->iface_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable iface clock\n");
- goto err_assert_ahb;
- }
-
- ret = clk_prepare_enable(res->core_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable core clock\n");
- goto err_clk_core;
- }
-
- ret = clk_prepare_enable(res->aux_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable aux clock\n");
- goto err_clk_aux;
- }
-
- ret = clk_prepare_enable(res->ref_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable ref clock\n");
- goto err_clk_ref;
- }
-
ret = reset_control_deassert(res->ahb_reset);
if (ret) {
dev_err(dev, "cannot deassert ahb reset\n");
@@ -352,48 +311,46 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
ret = reset_control_deassert(res->ext_reset);
if (ret) {
dev_err(dev, "cannot deassert ext reset\n");
- goto err_deassert_ahb;
+ goto err_deassert_ext;
}
- /* enable PCIe clocks and resets */
- val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
- val &= ~BIT(0);
- writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
-
- /* enable external reference clock */
- val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
- val |= BIT(16);
- writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
-
ret = reset_control_deassert(res->phy_reset);
if (ret) {
dev_err(dev, "cannot deassert phy reset\n");
- return ret;
+ goto err_deassert_phy;
}
ret = reset_control_deassert(res->pci_reset);
if (ret) {
dev_err(dev, "cannot deassert pci reset\n");
- return ret;
+ goto err_deassert_pci;
}
ret = reset_control_deassert(res->por_reset);
if (ret) {
dev_err(dev, "cannot deassert por reset\n");
- return ret;
+ goto err_deassert_por;
}
ret = reset_control_deassert(res->axi_reset);
if (ret) {
dev_err(dev, "cannot deassert axi reset\n");
- return ret;
+ goto err_deassert_axi;
}
- ret = clk_prepare_enable(res->phy_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable phy clock\n");
- goto err_deassert_ahb;
- }
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
+ if (ret)
+ goto err_clks;
+
+ /* enable PCIe clocks and resets */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~BIT(0);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+ /* enable external reference clock */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
+ val |= BIT(16);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
/* wait for clock acquisition */
usleep_range(1000, 1500);
@@ -407,15 +364,19 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return 0;
+err_clks:
+ reset_control_assert(res->axi_reset);
+err_deassert_axi:
+ reset_control_assert(res->por_reset);
+err_deassert_por:
+ reset_control_assert(res->pci_reset);
+err_deassert_pci:
+ reset_control_assert(res->phy_reset);
+err_deassert_phy:
+ reset_control_assert(res->ext_reset);
+err_deassert_ext:
+ reset_control_assert(res->ahb_reset);
err_deassert_ahb:
- clk_disable_unprepare(res->ref_clk);
-err_clk_ref:
- clk_disable_unprepare(res->aux_clk);
-err_clk_aux:
- clk_disable_unprepare(res->core_clk);
-err_clk_core:
- clk_disable_unprepare(res->iface_clk);
-err_assert_ahb:
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
return ret;
--
2.25.1
^ permalink raw reply related
* [PATCH v5 03/11] PCI: qcom: Change duplicate PCI reset to phy reset
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Abhishek Sahu, Ansuel Smith, Rob Herring, Andy Gross,
Bjorn Andersson, Bjorn Helgaas, Mark Rutland, Stanimir Varbanov,
Lorenzo Pieralisi, Andrew Murray, Philipp Zabel, linux-arm-msm,
linux-pci, devicetree, linux-kernel
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>
From: Abhishek Sahu <absahu@codeaurora.org>
The deinit issues reset_control_assert for PCI twice and does not contain
phy reset.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4bf93ab8c7a7..4512c2c5f61c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -280,14 +280,14 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
+ clk_disable_unprepare(res->phy_clk);
reset_control_assert(res->pci_reset);
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
- reset_control_assert(res->pci_reset);
+ reset_control_assert(res->phy_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
- clk_disable_unprepare(res->phy_clk);
clk_disable_unprepare(res->aux_clk);
clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
@@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_clk_core;
}
- ret = clk_prepare_enable(res->phy_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable phy clock\n");
- goto err_clk_phy;
- }
-
ret = clk_prepare_enable(res->aux_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable aux clock\n");
@@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return ret;
}
+ ret = clk_prepare_enable(res->phy_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable phy clock\n");
+ goto err_deassert_ahb;
+ }
+
/* wait for clock acquisition */
usleep_range(1000, 1500);
@@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
err_clk_ref:
clk_disable_unprepare(res->aux_clk);
err_clk_aux:
- clk_disable_unprepare(res->phy_clk);
-err_clk_phy:
clk_disable_unprepare(res->core_clk);
err_clk_core:
clk_disable_unprepare(res->iface_clk);
--
2.25.1
^ permalink raw reply related
* [PATCH v5 00/11] Multiple fixes in PCIe qcom driver
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, Andy Gross, Bjorn Andersson, Bjorn Helgaas,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
This contains multiple fix for PCIe qcom driver.
Some optional reset and clocks were missing.
Fix a problem with no PARF programming that cause kernel lock on load.
Add support to force gen 1 speed if needed. (due to hardware limitation)
Add ipq8064 rev 2 support that use a different tx termination offset.
v5:
* Split PCI: qcom: Add ipq8064 rev2 variant and set tx term offset
v4:
* Fix grammar error across all patch subject
* Use bulk api for clks
* Program PARF only in ipq8064 SoC
* Program tx term only in ipq8064 SoC
* Drop configurable tx-dempth rx-eq
* Make added clk optional
v3:
* Fix check reported by checkpatch --strict
* Rename force_gen1 to gen
v2:
* Drop iATU programming (already done in pcie init)
* Use max-link-speed instead of force-gen1 custom definition
* Drop MRRS to 256B (Can't find a realy reason why this was suggested)
* Introduce a new variant for different revision of ipq8064
Abhishek Sahu (1):
PCI: qcom: Change duplicate PCI reset to phy reset
Ansuel Smith (9):
PCI: qcom: Add missing ipq806x clocks in PCIe driver
dt-bindings: PCI: qcom: Add missing clks
PCI: qcom: Add missing reset for ipq806x
dt-bindings: PCI: qcom: Add ext reset
PCI: qcom: Use bulk clk api and assert on error
PCI: qcom: Define some PARF params needed for ipq8064 SoC
PCI: qcom: Add support for tx term offset for rev 2.1.0
PCI: qcom: Add ipq8064 rev2 variant
dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant
Sham Muthayyan (1):
PCI: qcom: Add Force GEN1 support
.../devicetree/bindings/pci/qcom,pcie.txt | 15 +-
drivers/pci/controller/dwc/pcie-qcom.c | 171 ++++++++++++------
2 files changed, 123 insertions(+), 63 deletions(-)
--
2.25.1
^ permalink raw reply
* Re: [PATCH v7 21/24] iommu/arm-smmu-v3: Add stall support for platform devices
From: Jean-Philippe Brucker @ 2020-06-02 11:46 UTC (permalink / raw)
To: Shameerali Kolothum Thodi
Cc: devicetree@vger.kernel.org, kevin.tian@intel.com, will@kernel.org,
fenghua.yu@intel.com, jgg@ziepe.ca, linux-pci@vger.kernel.org,
felix.kuehling@amd.com, hch@infradead.org, linux-mm@kvack.org,
iommu@lists.linux-foundation.org, catalin.marinas@arm.com,
zhangfei.gao@linaro.org, robin.murphy@arm.com,
christian.koenig@amd.com, linux-arm-kernel@lists.infradead.org
In-Reply-To: <1517c4d97b5849e6b6d32e7d7ed35289@huawei.com>
[-- Attachment #1: Type: text/plain, Size: 5830 bytes --]
On Tue, Jun 02, 2020 at 10:31:29AM +0000, Shameerali Kolothum Thodi wrote:
> Hi Jean,
>
> > -----Original Message-----
> > From: linux-arm-kernel [mailto:linux-arm-kernel-bounces@lists.infradead.org]
> > On Behalf Of Jean-Philippe Brucker
> > Sent: 02 June 2020 10:39
> > To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
> > Cc: devicetree@vger.kernel.org; kevin.tian@intel.com; will@kernel.org;
> > fenghua.yu@intel.com; jgg@ziepe.ca; linux-pci@vger.kernel.org;
> > felix.kuehling@amd.com; hch@infradead.org; linux-mm@kvack.org;
> > iommu@lists.linux-foundation.org; catalin.marinas@arm.com;
> > zhangfei.gao@linaro.org; robin.murphy@arm.com;
> > christian.koenig@amd.com; linux-arm-kernel@lists.infradead.org
> > Subject: Re: [PATCH v7 21/24] iommu/arm-smmu-v3: Add stall support for
> > platform devices
> >
> > Hi Shameer,
> >
> > On Mon, Jun 01, 2020 at 12:42:15PM +0000, Shameerali Kolothum Thodi
> > wrote:
> > > > /* IRQ and event handlers */
> > > > +static int arm_smmu_handle_evt(struct arm_smmu_device *smmu, u64
> > > > +*evt) {
> > > > + int ret;
> > > > + u32 perm = 0;
> > > > + struct arm_smmu_master *master;
> > > > + bool ssid_valid = evt[0] & EVTQ_0_SSV;
> > > > + u8 type = FIELD_GET(EVTQ_0_ID, evt[0]);
> > > > + u32 sid = FIELD_GET(EVTQ_0_SID, evt[0]);
> > > > + struct iommu_fault_event fault_evt = { };
> > > > + struct iommu_fault *flt = &fault_evt.fault;
> > > > +
> > > > + /* Stage-2 is always pinned at the moment */
> > > > + if (evt[1] & EVTQ_1_S2)
> > > > + return -EFAULT;
> > > > +
> > > > + master = arm_smmu_find_master(smmu, sid);
> > > > + if (!master)
> > > > + return -EINVAL;
> > > > +
> > > > + if (evt[1] & EVTQ_1_READ)
> > > > + perm |= IOMMU_FAULT_PERM_READ;
> > > > + else
> > > > + perm |= IOMMU_FAULT_PERM_WRITE;
> > > > +
> > > > + if (evt[1] & EVTQ_1_EXEC)
> > > > + perm |= IOMMU_FAULT_PERM_EXEC;
> > > > +
> > > > + if (evt[1] & EVTQ_1_PRIV)
> > > > + perm |= IOMMU_FAULT_PERM_PRIV;
> > > > +
> > > > + if (evt[1] & EVTQ_1_STALL) {
> > > > + flt->type = IOMMU_FAULT_PAGE_REQ;
> > > > + flt->prm = (struct iommu_fault_page_request) {
> > > > + .flags = IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE,
> > > > + .pasid = FIELD_GET(EVTQ_0_SSID, evt[0]),
> > > > + .grpid = FIELD_GET(EVTQ_1_STAG, evt[1]),
> > > > + .perm = perm,
> > > > + .addr = FIELD_GET(EVTQ_2_ADDR, evt[2]),
> > > > + };
> > > > +
> > >
> > > > + if (ssid_valid)
> > > > + flt->prm.flags |=
> > IOMMU_FAULT_PAGE_REQUEST_PASID_VALID;
> > >
> > > Do we need to set this for STALL mode only support? I had an issue
> > > with this being set on a vSVA POC based on our D06 zip device(which is
> > > a "fake " pci dev that supports STALL mode but no PRI). The issue is,
> > > CMDQ_OP_RESUME doesn't have any ssid or SSV params and works on sid
> > and stag only.
> >
> > I don't understand the problem, arm_smmu_page_response() doesn't set SSID
> > or SSV when sending a CMDQ_OP_RESUME. Could you detail the flow of a stall
> > event and RESUME command in your prototype? Are you getting issues with
> > the host driver or the guest driver?
>
> The issue is on the host side iommu_page_response(). The flow is something like
> below.
>
> Stall: Host:-
>
> arm_smmu_handle_evt()
> iommu_report_device_fault()
> vfio_pci_iommu_dev_fault_handler()
>
> Stall: Qemu:-
>
> vfio_dma_fault_notifier_handler()
> inject_faults()
> smmuv3_inject_faults()
>
> Stall: Guest:-
>
> arm_smmu_handle_evt()
> iommu_report_device_fault()
> iommu_queue_iopf
> ...
> iopf_handle_group()
> iopf_handle_single()
> handle_mm_fault()
> iopf_complete()
> iommu_page_response()
> arm_smmu_page_response()
> arm_smmu_cmdq_issue_cmd(CMDQ_OP_RESUME)
>
> Resume: Qemu:-
>
> smmuv3_cmdq_consume(SMMU_CMD_RESUME)
> smmuv3_notify_page_resp()
> vfio:ioctl(page_response) --> struct iommu_page_response is filled
> with only version, grpid and code.
>
> Resume: Host:-
> ioctl(page_response)
> iommu_page_response() --> fails as the pending req has PASID_VALID flag
> set and it checks for a match.
I believe the fix needs to be here. It's also wrong for PRI since not all
PCIe endpoint require a PASID in the page response. Could you try the
attached patch?
Thanks,
Jean
> arm_smmu_page_response()
>
> Hope the above is clear.
>
> > We do need to forward the SSV flag all the way to the guest driver, so the guest
> > can find the faulting address space using the SSID. Once the guest handled the
> > fault, then we don't send the SSID back to the host as part of the RESUME
> > command.
>
> True, the guest requires SSV flag to handle the page fault. But, as shown in the
> flow above, the issue is on the host side iommu_page_response() where it
> searches for a matching pending req based on pasid. Not sure we can bypass
> that and call arm_smmu_page_response() directly but then have to delete the
> pending req from the list as well.
>
> Please let me know if there is a better way to handle the host side page
> response.
>
> Thanks,
> Shameer
>
> > Thanks,
> > Jean
> >
> > > Hence, it is difficult for
> > > Qemu SMMUv3 to populate this fields while preparing a page response. I
> > > can see that this flag is being checked in iopf_handle_single() (patch
> > > 04/24) as well. For POC, I used a temp fix[1] to work around this. Please let
> > me know your thoughts.
> > >
> > > Thanks,
> > > Shameer
> > >
> > > 1.
> > > https://github.com/hisilicon/kernel-dev/commit/99ff96146e924055f38d97a
> > > 5897e4becfa378d15
> > >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
[-- Attachment #2: 0001-iommu-Allow-page-responses-without-PASID.patch --]
[-- Type: text/plain, Size: 1682 bytes --]
From 9baf5b9894d4e4be05e665d80fd0ebac8b621aa4 Mon Sep 17 00:00:00 2001
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: Tue, 2 Jun 2020 13:13:27 +0200
Subject: [PATCH] iommu: Allow page responses without PASID
Some PCIe devices do not expect a PASID value in PRI Page Responses. If
the "PRG Response PASID Required" bit in the PRI capability is zero,
then the OS should not set the PASID field. Similarly on Arm SMMU,
responses to stall events do not have a PASID.
Currently iommu_page_response() checks that the PASID in the page
response corresponds to the one in the page request without first
checking the "PASID valid" bit. A page response coming from a guest OS
does not necessarily have a PASID, if the passed-through device does not
require one.
Allow page responses without PASID. The page request corresponding to a
page response is identified by device and by Page Response Group Index
(or stall tag).
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
---
drivers/iommu/iommu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index e61a9fc65b7e4..e481fdfafb77c 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -1296,7 +1296,8 @@ int iommu_page_response(struct device *dev,
*/
list_for_each_entry(evt, ¶m->fault_param->faults, list) {
prm = &evt->fault.prm;
- pasid_valid = prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID;
+ pasid_valid = prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID
+ && msg->flags & IOMMU_PAGE_RESP_PASID_VALID;
if ((pasid_valid && prm->pasid != msg->pasid) ||
prm->grpid != msg->grpid)
--
2.26.2
^ permalink raw reply related
* [PATCHv2 2/3] dt-binding: phy: ti,omap-usb2: Add quirk to disable charger detection
From: Roger Quadros @ 2020-06-02 11:46 UTC (permalink / raw)
To: kishon, robh+dt; +Cc: linux-kernel, devicetree, Roger Quadros
In-Reply-To: <20200602114606.32045-1-rogerq@ti.com>
Add "ti,dis-chg-det-quirk" property to disable the USB2_PHY Charger Detect
logic.
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml b/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml
index 2bbea8d2bcb1..5e8c7a98de1e 100644
--- a/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml
@@ -50,6 +50,11 @@ properties:
(deprecated) phandle of the control module used by PHY driver
to power on the PHY. Use syscon-phy-power instead.
+ ti,dis-chg-det-quirk:
+ description:
+ if present, driver will disable charger detection logic.
+ type: boolean
+
required:
- compatible
- reg
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCHv2 1/3] dt-binding: phy: convert ti,omap-usb2 to YAML
From: Roger Quadros @ 2020-06-02 11:46 UTC (permalink / raw)
To: kishon, robh+dt; +Cc: linux-kernel, devicetree, Roger Quadros
In-Reply-To: <20200602114606.32045-1-rogerq@ti.com>
Move ti,omap-usb2 to its own YAML schema.
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
.../devicetree/bindings/phy/ti,omap-usb2.yaml | 69 +++++++++++++++++++
.../devicetree/bindings/phy/ti-phy.txt | 37 ----------
2 files changed, 69 insertions(+), 37 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml
diff --git a/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml b/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml
new file mode 100644
index 000000000000..2bbea8d2bcb1
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/ti,omap-usb2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OMAP USB2 PHY
+
+maintainers:
+ - Kishon Vijay Abraham I <kishon@ti.com>
+ - Roger Quadros <rogerq@ti.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - "ti,dra7x-usb2"
+ - "ti,dra7x-usb2-phy2"
+ - "ti,am654-usb2"
+ - enum:
+ - "ti,omap-usb2"
+
+ reg:
+ maxItems: 1
+
+ '#phy-cells':
+ const: 0
+
+ clocks:
+ minItems: 1
+ items:
+ - description: wakeup clock
+ - description: reference clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: wkupclk
+ - const: refclk
+
+ syscon-phy-power:
+ $ref: /schemas/types.yaml#definitions/phandle-array
+ description:
+ phandle/offset pair. Phandle to the system control module and
+ register offset to power on/off the PHY.
+
+ ctrl-module:
+ $ref: /schemas/types.yaml#definitions/phandle
+ description:
+ (deprecated) phandle of the control module used by PHY driver
+ to power on the PHY. Use syscon-phy-power instead.
+
+required:
+ - compatible
+ - reg
+ - '#phy-cells'
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ usb0_phy: phy@4100000 {
+ compatible = "ti,am654-usb2", "ti,omap-usb2";
+ reg = <0x0 0x4100000 0x0 0x54>;
+ syscon-phy-power = <&scm_conf 0x4000>;
+ clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
+ clock-names = "wkupclk", "refclk";
+ #phy-cells = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 8f93c3b694a7..60c9d0ac75e6 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -27,43 +27,6 @@ omap_control_usb: omap-control-usb@4a002300 {
reg-names = "otghs_control";
};
-OMAP USB2 PHY
-
-Required properties:
- - compatible: Should be "ti,omap-usb2"
- Should be "ti,dra7x-usb2" for the 1st instance of USB2 PHY on
- DRA7x
- Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY
- in DRA7x
- Should be "ti,am654-usb2" for the USB2 PHYs on AM654.
- - reg : Address and length of the register set for the device.
- - #phy-cells: determine the number of cells that should be given in the
- phandle while referencing this phy.
- - clocks: a list of phandles and clock-specifier pairs, one for each entry in
- clock-names.
- - clock-names: should include:
- * "wkupclk" - wakeup clock.
- * "refclk" - reference clock (optional).
-
-Deprecated properties:
- - ctrl-module : phandle of the control module used by PHY driver to power on
- the PHY.
-
-Recommended properies:
-- syscon-phy-power : phandle/offset pair. Phandle to the system control
- module and the register offset to power on/off the PHY.
-
-This is usually a subnode of ocp2scp to which it is connected.
-
-usb2phy@4a0ad080 {
- compatible = "ti,omap-usb2";
- reg = <0x4a0ad080 0x58>;
- ctrl-module = <&omap_control_usb>;
- #phy-cells = <0>;
- clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
- clock-names = "wkupclk", "refclk";
-};
-
TI PIPE3 PHY
Required properties:
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCHv2 3/3] phy: omap-usb2-phy: disable PHY charger detect
From: Roger Quadros @ 2020-06-02 11:46 UTC (permalink / raw)
To: kishon, robh+dt
Cc: linux-kernel, devicetree, Roger Quadros, Bin Liu, Sekhar Nori
In-Reply-To: <20200602114606.32045-1-rogerq@ti.com>
AM654x PG1.0 has a silicon bug that D+ is pulled high after POR, which
could cause enumeration failure with some USB hubs. Disabling the
USB2_PHY Charger Detect function will put D+ into the normal state.
Using property "ti,dis-chg-det-quirk" in the DT usb2-phy node to
enable this workaround for AM654x PG1.0.
This addresses Silicon Errata:
i2075 - "USB2PHY: USB2PHY Charger Detect is Enabled by Default Without VBUS
Presence"
Signed-off-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
drivers/phy/ti/phy-omap-usb2.c | 35 +++++++++++++++++++++++++++-------
1 file changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/ti/phy-omap-usb2.c b/drivers/phy/ti/phy-omap-usb2.c
index cb2dd3230fa7..8ab8b94511d4 100644
--- a/drivers/phy/ti/phy-omap-usb2.c
+++ b/drivers/phy/ti/phy-omap-usb2.c
@@ -26,6 +26,10 @@
#define USB2PHY_ANA_CONFIG1 0x4c
#define USB2PHY_DISCON_BYP_LATCH BIT(31)
+#define USB2PHY_CHRG_DET 0x14
+#define USB2PHY_CHRG_DET_USE_CHG_DET_REG BIT(29)
+#define USB2PHY_CHRG_DET_DIS_CHG_DET BIT(28)
+
/* SoC Specific USB2_OTG register definitions */
#define AM654_USB2_OTG_PD BIT(8)
#define AM654_USB2_VBUS_DET_EN BIT(5)
@@ -43,6 +47,7 @@
#define OMAP_USB2_HAS_START_SRP BIT(0)
#define OMAP_USB2_HAS_SET_VBUS BIT(1)
#define OMAP_USB2_CALIBRATE_FALSE_DISCONNECT BIT(2)
+#define OMAP_USB2_DISABLE_CHRG_DET BIT(3)
struct omap_usb {
struct usb_phy phy;
@@ -236,6 +241,13 @@ static int omap_usb_init(struct phy *x)
omap_usb_writel(phy->phy_base, USB2PHY_ANA_CONFIG1, val);
}
+ if (phy->flags & OMAP_USB2_DISABLE_CHRG_DET) {
+ val = omap_usb_readl(phy->phy_base, USB2PHY_CHRG_DET);
+ val |= USB2PHY_CHRG_DET_USE_CHG_DET_REG |
+ USB2PHY_CHRG_DET_DIS_CHG_DET;
+ omap_usb_writel(phy->phy_base, USB2PHY_CHRG_DET, val);
+ }
+
return 0;
}
@@ -366,14 +378,12 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy->mask = phy_data->mask;
phy->power_on = phy_data->power_on;
phy->power_off = phy_data->power_off;
+ phy->flags = phy_data->flags;
- if (phy_data->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- phy->phy_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(phy->phy_base))
- return PTR_ERR(phy->phy_base);
- phy->flags |= OMAP_USB2_CALIBRATE_FALSE_DISCONNECT;
- }
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ phy->phy_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(phy->phy_base))
+ return PTR_ERR(phy->phy_base);
phy->syscon_phy_power = syscon_regmap_lookup_by_phandle(node,
"syscon-phy-power");
@@ -405,6 +415,17 @@ static int omap_usb2_probe(struct platform_device *pdev)
}
}
+ /*
+ * Errata i2075: USB2PHY: USB2PHY Charger Detect is Enabled by
+ * Default Without VBUS Presence.
+ *
+ * AM654x SR1.0 has a silicon bug due to which D+ is pulled high after
+ * POR, which could cause enumeration failure with some USB hubs.
+ * Disabling the USB2_PHY Charger Detect function will put D+
+ * into the normal state.
+ */
+ if (of_property_read_bool(node, "ti,dis-chg-det-quirk"))
+ phy->flags |= OMAP_USB2_DISABLE_CHRG_DET;
phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
if (IS_ERR(phy->wkupclk)) {
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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