* [PATCH v5 2/3] mmc: core: Add support for SDIO async interrupt
From: Axe Yang @ 2022-01-21 7:19 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Chaotian Jing, Matthias Brugger,
Adrian Hunter
Cc: Yoshihiro Shimoda, Satya Tangirala, Andy Shevchenko, Wolfram Sang,
Axe Yang, Lucas Stach, Eric Biggers, Andrew Jeffery, Stephen Boyd,
Kiwoong Kim, Yue Hu, Tian Tao, angelogioacchino.delregno,
linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek
In-Reply-To: <20220121071942.11601-1-axe.yang@mediatek.com>
If cap-sdio-async-irq flag is set in host dts node, parse EAI
information from SDIO CCCR interrupt externsion segment. If async
interrupt is supported by SDIO card then send command to card to
enable it and set enable_async_irq flag in sdio_cccr structure to 1.
The parse flow is implemented in sdio_read_cccr().
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Axe Yang <axe.yang@mediatek.com>
---
drivers/mmc/core/host.c | 2 ++
drivers/mmc/core/sdio.c | 17 +++++++++++++++++
include/linux/mmc/card.h | 3 ++-
include/linux/mmc/host.h | 1 +
include/linux/mmc/sdio.h | 5 +++++
5 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index cf140f4ec864..a972241548b4 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -410,6 +410,8 @@ int mmc_of_parse(struct mmc_host *host)
if (device_property_read_bool(dev, "no-mmc-hs400"))
host->caps2 &= ~(MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V |
MMC_CAP2_HS400_ES);
+ if (device_property_read_bool(dev, "cap-sdio-async-irq"))
+ host->caps2 |= MMC_CAP2_SDIO_ASYNC_IRQ;
/* Must be after "non-removable" check */
if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) {
diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
index 41164748723d..771fb5d18585 100644
--- a/drivers/mmc/core/sdio.c
+++ b/drivers/mmc/core/sdio.c
@@ -225,6 +225,23 @@ static int sdio_read_cccr(struct mmc_card *card, u32 ocr)
card->sw_caps.sd3_drv_type |= SD_DRIVER_TYPE_C;
if (data & SDIO_DRIVE_SDTD)
card->sw_caps.sd3_drv_type |= SD_DRIVER_TYPE_D;
+
+ if (card->host->caps2 & MMC_CAP2_SDIO_ASYNC_IRQ) {
+ ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_INTERRUPT_EXT, 0,
+ &data);
+ if (ret)
+ goto out;
+
+ if (data & SDIO_INTERRUPT_EXT_SAI) {
+ data |= SDIO_INTERRUPT_EXT_EAI;
+ ret = mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_INTERRUPT_EXT,
+ data, NULL);
+ if (ret)
+ goto out;
+
+ card->cccr.enable_async_irq = 1;
+ }
+ }
}
/* if no uhs mode ensure we check for high speed */
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index 37f975875102..4df9182bc0e6 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -219,7 +219,8 @@ struct sdio_cccr {
wide_bus:1,
high_power:1,
high_speed:1,
- disable_cd:1;
+ disable_cd:1,
+ enable_async_irq:1;
};
struct sdio_cis {
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 7afb57cab00b..502a5418264c 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -402,6 +402,7 @@ struct mmc_host {
#define MMC_CAP2_CRYPTO 0
#endif
#define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT entry at a non-standard location */
+#define MMC_CAP2_SDIO_ASYNC_IRQ (1 << 29) /* SDIO host supports asynchronous interrupt */
int fixed_drv_type; /* fixed driver type for non-removable media */
diff --git a/include/linux/mmc/sdio.h b/include/linux/mmc/sdio.h
index 2a05d1ac4f0e..1ef400f28642 100644
--- a/include/linux/mmc/sdio.h
+++ b/include/linux/mmc/sdio.h
@@ -159,6 +159,11 @@
#define SDIO_DTSx_SET_TYPE_A (1 << SDIO_DRIVE_DTSx_SHIFT)
#define SDIO_DTSx_SET_TYPE_C (2 << SDIO_DRIVE_DTSx_SHIFT)
#define SDIO_DTSx_SET_TYPE_D (3 << SDIO_DRIVE_DTSx_SHIFT)
+
+#define SDIO_CCCR_INTERRUPT_EXT 0x16
+#define SDIO_INTERRUPT_EXT_SAI (1 << 0)
+#define SDIO_INTERRUPT_EXT_EAI (1 << 1)
+
/*
* Function Basic Registers (FBR)
*/
--
2.25.1
^ permalink raw reply related
* [PATCH v5 3/3] mmc: mediatek: add support for SDIO eint IRQ
From: Axe Yang @ 2022-01-21 7:19 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Chaotian Jing, Matthias Brugger,
Adrian Hunter
Cc: Yoshihiro Shimoda, Satya Tangirala, Andy Shevchenko, Wolfram Sang,
Axe Yang, Lucas Stach, Eric Biggers, Andrew Jeffery, Stephen Boyd,
Kiwoong Kim, Yue Hu, Tian Tao, angelogioacchino.delregno,
linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Yong Mao
In-Reply-To: <20220121071942.11601-1-axe.yang@mediatek.com>
Add support for eint IRQ when MSDC is used as an SDIO host. This
feature requires SDIO device support async IRQ function. With this
feature, SDIO host can be awakened by SDIO card in suspend state,
without additional pin.
MSDC driver will time-share the SDIO DAT1 pin. During suspend, MSDC
turn off clock and switch SDIO DAT1 pin to GPIO mode. And during
resume, switch GPIO function back to DAT1 mode then turn on clock.
Some device tree property should be added or modified in MSDC node
to support SDIO eint IRQ. Pinctrls named state_dat1 and state_eint
are mandatory. And cap-sdio-async-irq flag is necessary since this
feature depends on asynchronous interrupt:
&mmcX {
...
pinctrl-names = "default", "state_uhs", "state_eint",
"state_dat1";
...
pinctrl-2 = <&mmc2_pins_eint>;
pinctrl-3 = <&mmc2_pins_dat1>;
...
cap-sdio-async-irq;
...
};
Co-developed-by: Yong Mao <yong.mao@mediatek.com>
Signed-off-by: Yong Mao <yong.mao@mediatek.com>
Signed-off-by: Axe Yang <axe.yang@mediatek.com>
---
drivers/mmc/host/mtk-sd.c | 123 +++++++++++++++++++++++++++++++++++---
1 file changed, 115 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 65037e1d7723..f8e38228d810 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2014-2015 MediaTek Inc.
+ * Copyright (c) 2014-2015, 2022 MediaTek Inc.
* Author: Chaotian.Jing <chaotian.jing@mediatek.com>
*/
@@ -9,6 +9,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
+#include <linux/gpio/consumer.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
#include <linux/irq.h>
@@ -440,8 +441,12 @@ struct msdc_host {
struct pinctrl *pinctrl;
struct pinctrl_state *pins_default;
struct pinctrl_state *pins_uhs;
+ struct pinctrl_state *pins_eint;
+ struct pinctrl_state *pins_dat1;
struct delayed_work req_timeout;
int irq; /* host interrupt */
+ int eint_irq; /* device interrupt */
+ int sdio_irq_cnt; /* irq enable cnt */
struct reset_control *reset;
struct clk *src_clk; /* msdc source clock */
@@ -465,6 +470,7 @@ struct msdc_host {
bool hs400_tuning; /* hs400 mode online tuning */
bool internal_cd; /* Use internal card-detect logic */
bool cqhci; /* support eMMC hw cmdq */
+ bool sdio_eint_ready; /* Ready to support SDIO eint interrupt */
struct msdc_save_para save_para; /* used when gate HCLK */
struct msdc_tune_para def_tune_para; /* default tune setting */
struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
@@ -1527,10 +1533,12 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
__msdc_enable_sdio_irq(host, enb);
spin_unlock_irqrestore(&host->lock, flags);
- if (enb)
- pm_runtime_get_noresume(host->dev);
- else
- pm_runtime_put_noidle(host->dev);
+ if (mmc->card && !mmc->card->cccr.enable_async_irq) {
+ if (enb)
+ pm_runtime_get_noresume(host->dev);
+ else
+ pm_runtime_put_noidle(host->dev);
+ }
}
static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
@@ -2461,6 +2469,48 @@ static const struct mmc_host_ops mt_msdc_ops = {
.hw_reset = msdc_hw_reset,
};
+static irqreturn_t msdc_sdio_eint_irq(int irq, void *dev_id)
+{
+ struct msdc_host *host = dev_id;
+ struct mmc_host *mmc = mmc_from_priv(host);
+
+ spin_lock(&host->lock);
+ if (likely(host->sdio_irq_cnt > 0)) {
+ disable_irq_nosync(host->eint_irq);
+ disable_irq_wake(host->eint_irq);
+ host->sdio_irq_cnt--;
+ }
+ spin_unlock(&host->lock);
+
+ sdio_signal_irq(mmc);
+
+ return IRQ_HANDLED;
+}
+
+static int msdc_request_dat1_eint_irq(struct msdc_host *host)
+{
+ struct gpio_desc *desc;
+ int irq, ret;
+
+ desc = devm_gpiod_get(host->dev, "eint", GPIOD_IN);
+ if (IS_ERR(desc))
+ return PTR_ERR(desc);
+
+ irq = gpiod_to_irq(desc);
+ if (irq < 0)
+ return irq;
+
+ ret = devm_request_threaded_irq(host->dev, irq, NULL, msdc_sdio_eint_irq,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT | IRQF_NO_AUTOEN,
+ "sdio-eint", host);
+ if (ret)
+ return ret;
+
+ host->eint_irq = irq;
+
+ return 0;
+}
+
static const struct cqhci_host_ops msdc_cmdq_ops = {
.enable = msdc_cqe_enable,
.disable = msdc_cqe_disable,
@@ -2631,6 +2681,23 @@ static int msdc_drv_probe(struct platform_device *pdev)
goto host_free;
}
+ if (!(mmc->caps2 & MMC_CAP2_NO_SDIO) && (mmc->caps2 & MMC_CAP2_SDIO_ASYNC_IRQ)) {
+ /* Support for SDIO eint irq */
+ host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
+ if (IS_ERR(host->pins_eint)) {
+ dev_dbg(&pdev->dev, "Cannot find pinctrl eint!\n");
+ } else {
+ host->pins_dat1 = pinctrl_lookup_state(host->pinctrl, "state_dat1");
+ if (IS_ERR(host->pins_dat1)) {
+ ret = dev_err_probe(&pdev->dev, PTR_ERR(host->pins_dat1),
+ "Cannot find pinctrl dat1!\n");
+ goto host_free;
+ }
+
+ host->sdio_eint_ready = true;
+ }
+ }
+
msdc_of_property_parse(pdev, host);
host->dev = &pdev->dev;
@@ -2722,6 +2789,16 @@ static int msdc_drv_probe(struct platform_device *pdev)
if (ret)
goto release;
+ if (host->sdio_eint_ready) {
+ ret = msdc_request_dat1_eint_irq(host);
+ if (ret) {
+ dev_err(host->dev, "Failed to register data1 eint irq!\n");
+ goto release;
+ }
+
+ pinctrl_select_state(host->pinctrl, host->pins_dat1);
+ }
+
pm_runtime_set_active(host->dev);
pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
pm_runtime_use_autosuspend(host->dev);
@@ -2843,8 +2920,22 @@ static int __maybe_unused msdc_runtime_suspend(struct device *dev)
{
struct mmc_host *mmc = dev_get_drvdata(dev);
struct msdc_host *host = mmc_priv(mmc);
+ unsigned long flags;
msdc_save_reg(host);
+
+ if (host->sdio_eint_ready) {
+ disable_irq(host->irq);
+ pinctrl_select_state(host->pinctrl, host->pins_eint);
+ spin_lock_irqsave(&host->lock, flags);
+ if (host->sdio_irq_cnt == 0) {
+ enable_irq(host->eint_irq);
+ enable_irq_wake(host->eint_irq);
+ host->sdio_irq_cnt++;
+ }
+ sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
+ spin_unlock_irqrestore(&host->lock, flags);
+ }
msdc_gate_clock(host);
return 0;
}
@@ -2853,6 +2944,7 @@ static int __maybe_unused msdc_runtime_resume(struct device *dev)
{
struct mmc_host *mmc = dev_get_drvdata(dev);
struct msdc_host *host = mmc_priv(mmc);
+ unsigned long flags;
int ret;
ret = msdc_ungate_clock(host);
@@ -2860,10 +2952,25 @@ static int __maybe_unused msdc_runtime_resume(struct device *dev)
return ret;
msdc_restore_reg(host);
+
+ if (host->sdio_eint_ready) {
+ spin_lock_irqsave(&host->lock, flags);
+ if (host->sdio_irq_cnt > 0) {
+ disable_irq_nosync(host->eint_irq);
+ disable_irq_wake(host->eint_irq);
+ host->sdio_irq_cnt--;
+ sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
+ } else {
+ sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
+ }
+ spin_unlock_irqrestore(&host->lock, flags);
+ pinctrl_select_state(host->pinctrl, host->pins_uhs);
+ enable_irq(host->irq);
+ }
return 0;
}
-static int __maybe_unused msdc_suspend(struct device *dev)
+static int __maybe_unused msdc_suspend_noirq(struct device *dev)
{
struct mmc_host *mmc = dev_get_drvdata(dev);
int ret;
@@ -2877,13 +2984,13 @@ static int __maybe_unused msdc_suspend(struct device *dev)
return pm_runtime_force_suspend(dev);
}
-static int __maybe_unused msdc_resume(struct device *dev)
+static int __maybe_unused msdc_resume_noirq(struct device *dev)
{
return pm_runtime_force_resume(dev);
}
static const struct dev_pm_ops msdc_dev_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(msdc_suspend_noirq, msdc_resume_noirq)
SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
};
--
2.25.1
^ permalink raw reply related
* [PATCH v5 1/3] dt-bindings: mmc: add cap-sdio-async-irq flag
From: Axe Yang @ 2022-01-21 7:19 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Chaotian Jing, Matthias Brugger,
Adrian Hunter
Cc: Yoshihiro Shimoda, Satya Tangirala, Andy Shevchenko, Wolfram Sang,
Axe Yang, Lucas Stach, Eric Biggers, Andrew Jeffery, Stephen Boyd,
Kiwoong Kim, Yue Hu, Tian Tao, angelogioacchino.delregno,
linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek
In-Reply-To: <20220121071942.11601-1-axe.yang@mediatek.com>
Asynchronous interrupt is a mechanism that allow SDIO devices alarm
interrupt when host stop providing clock to card. Add a DT flag to
enable this feature if it is supported by SDIO card.
Signed-off-by: Axe Yang <axe.yang@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mmc-controller.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
index 513f3c8758aa..16fb06f88471 100644
--- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
+++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
@@ -165,6 +165,11 @@ properties:
description:
eMMC hardware reset is supported
+ cap-sdio-async-irq:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ SDIO async interrupt is supported.
+
cap-sdio-irq:
$ref: /schemas/types.yaml#/definitions/flag
description:
--
2.25.1
^ permalink raw reply related
* [PATCH v5 0/3] mmc: mediatek: add support for SDIO async IRQ
From: Axe Yang @ 2022-01-21 7:19 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Chaotian Jing, Matthias Brugger,
Adrian Hunter
Cc: Yoshihiro Shimoda, Satya Tangirala, Andy Shevchenko, Wolfram Sang,
Axe Yang, Lucas Stach, Eric Biggers, Andrew Jeffery, Stephen Boyd,
Kiwoong Kim, Yue Hu, Tian Tao, angelogioacchino.delregno,
linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek
Change in v5:
- resort variables to reversed xmas tree order
- restore old copyright year range and add current year back
Change in v4:
- add MMC_CAP2_SDIO_ASYNC_IRQ judge before lookup eint pinctrl
- replace spin_lock_irqsave() variant with spin_lock() in eint irq handler
Changes in v3:
- correct abbreviations with capital letters in commit message
- replace copyright year with 2022 in mtk-sd.c
- remove unnessary pointer casting
- adjust variable order to reversed xmas tree
- remove a redundant blank line
- refine if statement, following standard pattern
Change in v2:
- change flag name from 'cap-sdio-async-int' to 'cap-sdio-async-irq'
- change corresponding macro names from xxx_INT to xxx_IRQ
- resort new member in msdc_host structure
- refine function msdc_request_dat1_eint_irq()
- rename msdc_{suspend,resume} function names, add suffix '_noirq'
- add MMC_CAP2_NO_SDIO judgement before parse eint related pin setting
Axe Yang (3):
dt-bindings: mmc: add cap-sdio-async-irq flag
mmc: core: Add support for SDIO async interrupt
mmc: mediatek: add support for SDIO eint IRQ
.../bindings/mmc/mmc-controller.yaml | 5 +
drivers/mmc/core/host.c | 2 +
drivers/mmc/core/sdio.c | 17 +++
drivers/mmc/host/mtk-sd.c | 123 ++++++++++++++++--
include/linux/mmc/card.h | 3 +-
include/linux/mmc/host.h | 1 +
include/linux/mmc/sdio.h | 5 +
7 files changed, 147 insertions(+), 9 deletions(-)
--
2.25.1
^ permalink raw reply
* RE: [PATCH v6 1/2] spi: Add spi driver for Sunplus SP7021
From: Lh Kuo 郭力豪 @ 2022-01-21 6:55 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Li-hao Kuo, Philipp Zabel, Mark Brown, Rob Herring, linux-spi,
devicetree, Linux Kernel Mailing List,
Wells Lu 呂芳騰
In-Reply-To: <CAHp75VcCpye1u3+PK=C3CT8fMHPSOsXTL5AhbLVy0YyGWfyfkQ@mail.gmail.com>
> > > > + if (xfer->tx_buf)
> > > > + dma_unmap_single(dev, xfer->tx_dma, xfer->len, DMA_TO_DEVICE);
> > > > + if (xfer->rx_buf)
> > > > + dma_unmap_single(dev, xfer->rx_dma, xfer->len,
> > > > + DMA_FROM_DEVICE);
> > >
> > > Why can't you use SPI core DMA mapping code?
> >
> > I didn't find the SPI core DMA mapping code for single maping.
> > The method currently used is the general DMA single-map code usage method.
>
> Why do you need single page mapping?
> What's wrong with SG mapping that SPI core provides?
SP7021 SPI slave dma only supports single dma in one trigger.
It is not suitable for using SG mapping.
If the length of the transfer is larger than the length of the SG-mapping,
Slave-mode will get error in the transfer.
^ permalink raw reply
* Re: [PATCH v3 1/3] dt-bindings: pwm: Fix node name pattern
From: Nikita Travkin @ 2022-01-21 6:20 UTC (permalink / raw)
To: Rob Herring
Cc: thierry.reding, lee.jones, u.kleine-koenig, sboyd, krzk,
linus.walleij, masneyb, linux-pwm, devicetree, linux-kernel,
~postmarketos/upstreaming
In-Reply-To: <Yem0wtltC/6FklZu@robh.at.kernel.org>
Rob Herring писал(а) 21.01.2022 00:15:
> On Thu, Jan 20, 2022 at 09:14:40PM +0500, Nikita Travkin wrote:
>> It looks like it was intended to allow two types of node names with the
>> binding:
>>
>> - With unit address, e.g. pwm@1f000000
>
> Yes, but the format of the unit-address is up to the parent bus which is
> outside the scope of this binding.
>
>> - With a suffix, e.g. pwm-clk
>
> No. pwm-0, pwm-1, etc. only to cover the few cases with no unit-address.
>
> Third is just 'pwm' as the '*' on the end means 0 or more. Though a '?'
> would have been more correct.
>
Oh, thanks for clarifying that. My assumption was that just numbering
the nodes is not informative enough, but if it's the agreed way to do
it, I will use this format instead.
I will drop this commit and correct the bindings to use 'pwm' with
no suffix as an example. (Though I still think that having a
meaningful suffix is nicer in the DT so one could see what the
node is used for)
Thanks
Nikita
>>
>> However the pattern regex only correctly matches the first variant,
>> as well as some incorrect ones.
>>
>> Fix the regex to match only two patterns shown above. (Either unit
>> address starting with @ and following with one or more hexademical
>> digit or arbitrary suffix stating with - and at least one symbol long)
>>
>> Fixes: 89650a1e3b6f ("dt-bindings: pwm: Convert PWM bindings to json-schema")
>> Signed-off-by: Nikita Travkin <nikita@trvn.ru>
>> ---
>> Documentation/devicetree/bindings/pwm/pwm.yaml | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pwm/pwm.yaml b/Documentation/devicetree/bindings/pwm/pwm.yaml
>> index 3c01f85029e5..4926fe65886f 100644
>> --- a/Documentation/devicetree/bindings/pwm/pwm.yaml
>> +++ b/Documentation/devicetree/bindings/pwm/pwm.yaml
>> @@ -13,7 +13,7 @@ select: false
>>
>> properties:
>> $nodename:
>> - pattern: "^pwm(@.*|-[0-9a-f])*$"
>> + pattern: "^pwm(@[0-9a-f]+|-.+)?$"
>>
>> "#pwm-cells":
>> description:
>> --
>> 2.30.2
>>
>>
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: usb: Add analogix anx7411 PD binding
From: Xin Ji @ 2022-01-21 6:18 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Xin Ji
Cc: bliang, qwen, jli, linux-usb, devicetree, linux-kernel
Add analogix PD chip anx7411 device binding
Signed-off-by: Xin Ji <xji@analogixsemi.com>
---
.../bindings/usb/analogix,anx7411.yaml | 76 +++++++++++++++++++
1 file changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/analogix,anx7411.yaml
diff --git a/Documentation/devicetree/bindings/usb/analogix,anx7411.yaml b/Documentation/devicetree/bindings/usb/analogix,anx7411.yaml
new file mode 100644
index 000000000000..c5c6d5a9dc17
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/analogix,anx7411.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/usb/analogix,anx7411.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Analogix ANX7411 Type-C controller bindings
+
+maintainers:
+ - Xin Ji <xji@analogixsemi.com>
+
+properties:
+ compatible:
+ enum:
+ - analogix,anx7411
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ connector:
+ type: object
+
+ allOf:
+ - $ref: ../connector/usb-connector.yaml
+
+ properties:
+ compatible:
+ const: usb-c-connector
+
+ power-role: true
+
+ data-role: true
+
+ try-power-role: true
+
+ required:
+ - compatible
+
+required:
+ - compatible
+ - reg
+ - connector
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ typec: anx7411@2C {
+ compatible = "analogix,anx7411";
+ reg = <0x2C>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpio0>;
+
+ typec_con: connector {
+ compatible = "usb-c-connector";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "source";
+
+ port {
+ typec_con_ep: endpoint {
+ remote-endpoint = <&usbotg_hs_ep>;
+ };
+ };
+ };
+ };
+ };
+...
--
2.25.1
^ permalink raw reply related
* [PATCH v2 2/2] pinctrl: add pinctrl driver on mt8186
From: Guodong Liu @ 2022-01-21 6:01 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Matthias Brugger, Sean Wang
Cc: Sean Wang, linux-gpio, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Guodong Liu
In-Reply-To: <20220121060120.10683-1-guodong.liu@mediatek.com>
This commit includes pinctrl driver for mt8186.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
---
drivers/pinctrl/mediatek/Kconfig | 7 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8186.c | 1313 ++++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h | 2186 +++++++++++++++++
4 files changed, 3507 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8186.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 66db4ac5d169..8dca1ef04965 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -147,6 +147,13 @@ config PINCTRL_MT8183
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
+config PINCTRL_MT8186
+ bool "Mediatek MT8186 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_PARIS
+
config PINCTRL_MT8192
bool "Mediatek MT8192 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 90f43bb9d9a7..31c3784c6089 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
+obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8186.c b/drivers/pinctrl/mediatek/pinctrl-mt8186.c
new file mode 100644
index 000000000000..1e550b15b9d4
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8186.c
@@ -0,0 +1,1313 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ *
+ * Author: Guodong Liu <guodong.liu@mediatek.com>
+ *
+ */
+
+#include "pinctrl-mtk-mt8186.h"
+#include "pinctrl-paris.h"
+
+/* MT8186 have multiple bases to program pin configuration listed as the below:
+ * iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200,
+ * iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800,
+ * iocfg[6]:0x10002C00.
+ * _i_based could be used to indicate what base the pin should be mapped into.
+ */
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 0)
+
+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 1)
+
+static const struct mtk_pin_field_calc mt8186_pin_mode_range[] = {
+ PIN_FIELD(0, 184, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_dir_range[] = {
+ PIN_FIELD(0, 184, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_di_range[] = {
+ PIN_FIELD(0, 184, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_do_range[] = {
+ PIN_FIELD(0, 184, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_ies_range[] = {
+ PIN_FIELD_BASE(0, 0, 6, 0x0030, 0x10, 13, 1),
+ PIN_FIELD_BASE(1, 1, 6, 0x0030, 0x10, 14, 1),
+ PIN_FIELD_BASE(2, 2, 6, 0x0030, 0x10, 17, 1),
+ PIN_FIELD_BASE(3, 3, 6, 0x0030, 0x10, 18, 1),
+ PIN_FIELD_BASE(4, 4, 6, 0x0030, 0x10, 19, 1),
+ PIN_FIELD_BASE(5, 5, 6, 0x0030, 0x10, 20, 1),
+ PIN_FIELD_BASE(6, 6, 4, 0x0020, 0x10, 19, 1),
+ PIN_FIELD_BASE(7, 7, 4, 0x0020, 0x10, 20, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0x0020, 0x10, 21, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0x0020, 0x10, 22, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0x0020, 0x10, 16, 1),
+ PIN_FIELD_BASE(11, 11, 4, 0x0020, 0x10, 17, 1),
+ PIN_FIELD_BASE(12, 12, 4, 0x0020, 0x10, 18, 1),
+ PIN_FIELD_BASE(13, 13, 3, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(14, 14, 3, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(15, 15, 6, 0x0030, 0x10, 15, 1),
+ PIN_FIELD_BASE(16, 16, 6, 0x0030, 0x10, 16, 1),
+ PIN_FIELD_BASE(17, 17, 5, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(18, 18, 5, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(19, 19, 5, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(20, 20, 5, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(21, 21, 5, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(22, 22, 5, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(23, 23, 5, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(24, 24, 5, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(25, 25, 5, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(26, 26, 5, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, 5, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(28, 28, 5, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(29, 29, 6, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(30, 30, 6, 0x0030, 0x10, 1, 1),
+ PIN_FIELD_BASE(31, 31, 6, 0x0030, 0x10, 2, 1),
+ PIN_FIELD_BASE(32, 32, 2, 0x0040, 0x10, 25, 1),
+ PIN_FIELD_BASE(33, 33, 2, 0x0040, 0x10, 27, 1),
+ PIN_FIELD_BASE(34, 34, 2, 0x0040, 0x10, 26, 1),
+ PIN_FIELD_BASE(35, 35, 2, 0x0040, 0x10, 28, 1),
+ PIN_FIELD_BASE(36, 36, 2, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(40, 40, 2, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(41, 41, 2, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(44, 44, 5, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(45, 45, 5, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(46, 46, 5, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(47, 47, 5, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(48, 48, 2, 0x0040, 0x10, 17, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x0040, 0x10, 18, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x0040, 0x10, 20, 1),
+ PIN_FIELD_BASE(51, 51, 2, 0x0040, 0x10, 19, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x0040, 0x10, 18, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x0040, 0x10, 19, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x0040, 0x10, 21, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0040, 0x10, 20, 1),
+ PIN_FIELD_BASE(56, 56, 5, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(57, 57, 5, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, 5, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(59, 59, 5, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x0040, 0x10, 27, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 22, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 28, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 23, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 24, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 25, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 26, 1),
+ PIN_FIELD_BASE(67, 67, 1, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(69, 69, 1, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(70, 70, 1, 0x0050, 0x10, 19, 1),
+ PIN_FIELD_BASE(71, 71, 1, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(72, 72, 1, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(73, 73, 1, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(74, 74, 1, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(75, 75, 1, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(76, 76, 1, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(77, 77, 1, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(78, 78, 1, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(79, 79, 5, 0x0050, 0x10, 24, 1),
+ PIN_FIELD_BASE(80, 80, 5, 0x0050, 0x10, 25, 1),
+ PIN_FIELD_BASE(81, 81, 5, 0x0050, 0x10, 26, 1),
+ PIN_FIELD_BASE(82, 82, 5, 0x0050, 0x10, 27, 1),
+ PIN_FIELD_BASE(83, 83, 6, 0x0030, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(85, 85, 3, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(86, 86, 3, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(87, 87, 3, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(88, 88, 3, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(89, 89, 3, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(90, 90, 3, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(91, 91, 3, 0x0040, 0x10, 29, 1),
+ PIN_FIELD_BASE(92, 92, 3, 0x0040, 0x10, 31, 1),
+ PIN_FIELD_BASE(93, 93, 3, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(94, 94, 3, 0x0040, 0x10, 30, 1),
+ PIN_FIELD_BASE(95, 95, 3, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(99, 99, 4, 0x0020, 0x10, 14, 1),
+ PIN_FIELD_BASE(100, 100, 4, 0x0020, 0x10, 15, 1),
+ PIN_FIELD_BASE(101, 101, 4, 0x0020, 0x10, 13, 1),
+ PIN_FIELD_BASE(102, 102, 4, 0x0020, 0x10, 12, 1),
+ PIN_FIELD_BASE(103, 103, 4, 0x0020, 0x10, 0, 1),
+ PIN_FIELD_BASE(104, 104, 4, 0x0020, 0x10, 1, 1),
+ PIN_FIELD_BASE(105, 105, 4, 0x0020, 0x10, 4, 1),
+ PIN_FIELD_BASE(106, 106, 4, 0x0020, 0x10, 5, 1),
+ PIN_FIELD_BASE(107, 107, 4, 0x0020, 0x10, 6, 1),
+ PIN_FIELD_BASE(108, 108, 4, 0x0020, 0x10, 7, 1),
+ PIN_FIELD_BASE(109, 109, 4, 0x0020, 0x10, 8, 1),
+ PIN_FIELD_BASE(110, 110, 4, 0x0020, 0x10, 9, 1),
+ PIN_FIELD_BASE(111, 111, 4, 0x0020, 0x10, 10, 1),
+ PIN_FIELD_BASE(112, 112, 4, 0x0020, 0x10, 11, 1),
+ PIN_FIELD_BASE(113, 113, 4, 0x0020, 0x10, 2, 1),
+ PIN_FIELD_BASE(114, 114, 4, 0x0020, 0x10, 3, 1),
+ PIN_FIELD_BASE(115, 115, 3, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(116, 116, 3, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(117, 117, 3, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(118, 118, 3, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(119, 119, 5, 0x0050, 0x10, 22, 1),
+ PIN_FIELD_BASE(120, 120, 5, 0x0050, 0x10, 19, 1),
+ PIN_FIELD_BASE(121, 121, 5, 0x0050, 0x10, 20, 1),
+ PIN_FIELD_BASE(122, 122, 5, 0x0050, 0x10, 21, 1),
+ PIN_FIELD_BASE(123, 123, 5, 0x0050, 0x10, 23, 1),
+ PIN_FIELD_BASE(124, 124, 5, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(125, 125, 5, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(126, 126, 5, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(127, 127, 3, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(128, 128, 3, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(129, 129, 5, 0x0050, 0x10, 28, 1),
+ PIN_FIELD_BASE(130, 130, 5, 0x0050, 0x10, 30, 1),
+ PIN_FIELD_BASE(131, 131, 5, 0x0050, 0x10, 29, 1),
+ PIN_FIELD_BASE(132, 132, 5, 0x0050, 0x10, 31, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x0050, 0x10, 21, 1),
+ PIN_FIELD_BASE(134, 134, 1, 0x0050, 0x10, 24, 1),
+ PIN_FIELD_BASE(135, 135, 6, 0x0030, 0x10, 21, 1),
+ PIN_FIELD_BASE(136, 136, 6, 0x0030, 0x10, 24, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x0050, 0x10, 22, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x0050, 0x10, 25, 1),
+ PIN_FIELD_BASE(139, 139, 2, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(140, 140, 2, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(141, 141, 3, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(142, 142, 3, 0x0040, 0x10, 17, 1),
+ PIN_FIELD_BASE(143, 143, 6, 0x0030, 0x10, 22, 1),
+ PIN_FIELD_BASE(144, 144, 6, 0x0030, 0x10, 25, 1),
+ PIN_FIELD_BASE(145, 145, 6, 0x0030, 0x10, 23, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x0030, 0x10, 26, 1),
+ PIN_FIELD_BASE(147, 147, 4, 0x0020, 0x10, 23, 1),
+ PIN_FIELD_BASE(148, 148, 4, 0x0020, 0x10, 24, 1),
+ PIN_FIELD_BASE(149, 149, 4, 0x0020, 0x10, 25, 1),
+ PIN_FIELD_BASE(150, 150, 4, 0x0020, 0x10, 26, 1),
+ PIN_FIELD_BASE(151, 151, 4, 0x0020, 0x10, 27, 1),
+ PIN_FIELD_BASE(152, 152, 4, 0x0020, 0x10, 28, 1),
+ PIN_FIELD_BASE(153, 153, 4, 0x0020, 0x10, 29, 1),
+ PIN_FIELD_BASE(154, 154, 4, 0x0020, 0x10, 30, 1),
+ PIN_FIELD_BASE(155, 155, 4, 0x0020, 0x10, 31, 1),
+ PIN_FIELD_BASE(156, 156, 4, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(157, 157, 2, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(158, 158, 2, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(159, 159, 2, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(160, 160, 2, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(161, 161, 2, 0x0040, 0x10, 23, 1),
+ PIN_FIELD_BASE(162, 162, 2, 0x0040, 0x10, 24, 1),
+ PIN_FIELD_BASE(163, 163, 1, 0x0050, 0x10, 23, 1),
+ PIN_FIELD_BASE(164, 164, 1, 0x0050, 0x10, 20, 1),
+ PIN_FIELD_BASE(165, 165, 1, 0x0050, 0x10, 26, 1),
+ PIN_FIELD_BASE(166, 166, 1, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(167, 167, 1, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(168, 168, 1, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(169, 169, 1, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(170, 170, 1, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(171, 171, 1, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(172, 172, 1, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(173, 173, 1, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(174, 174, 6, 0x0030, 0x10, 7, 1),
+ PIN_FIELD_BASE(175, 175, 6, 0x0030, 0x10, 8, 1),
+ PIN_FIELD_BASE(176, 176, 6, 0x0030, 0x10, 4, 1),
+ PIN_FIELD_BASE(177, 177, 6, 0x0030, 0x10, 5, 1),
+ PIN_FIELD_BASE(178, 178, 6, 0x0030, 0x10, 6, 1),
+ PIN_FIELD_BASE(179, 179, 6, 0x0030, 0x10, 9, 1),
+ PIN_FIELD_BASE(180, 180, 6, 0x0030, 0x10, 10, 1),
+ PIN_FIELD_BASE(181, 181, 6, 0x0030, 0x10, 11, 1),
+ PIN_FIELD_BASE(182, 182, 6, 0x0030, 0x10, 12, 1),
+ PIN_FIELD_BASE(183, 183, 2, 0x0040, 0x10, 21, 1),
+ PIN_FIELD_BASE(184, 184, 2, 0x0040, 0x10, 22, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_smt_range[] = {
+ PIN_FIELD_BASE(0, 0, 6, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(1, 1, 6, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(2, 2, 6, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(3, 3, 6, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, 6, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, 6, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(11, 11, 4, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, 4, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(13, 13, 3, 0x00e0, 0x10, 11, 1),
+ PIN_FIELD_BASE(14, 14, 3, 0x00e0, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, 6, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, 6, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(17, 17, 5, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(18, 18, 5, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(19, 19, 5, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, 5, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(21, 21, 5, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(22, 22, 5, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(23, 23, 5, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(24, 24, 5, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(25, 25, 5, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(26, 26, 5, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(27, 27, 5, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(28, 28, 5, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(32, 32, 2, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(33, 33, 2, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(34, 34, 2, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(35, 35, 2, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(36, 36, 2, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(40, 40, 2, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(41, 41, 2, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(44, 44, 5, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(45, 45, 5, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(46, 46, 5, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(47, 47, 5, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(48, 48, 2, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(51, 51, 2, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(56, 56, 5, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(57, 57, 5, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(58, 58, 5, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(59, 59, 5, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(67, 67, 1, 0x00f0, 0x10, 10, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x00f0, 0x10, 0, 1),
+ PIN_FIELD_BASE(69, 69, 1, 0x00f0, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 1, 0x00f0, 0x10, 11, 1),
+ PIN_FIELD_BASE(71, 71, 1, 0x00f0, 0x10, 2, 1),
+ PIN_FIELD_BASE(72, 72, 1, 0x00f0, 0x10, 3, 1),
+ PIN_FIELD_BASE(73, 73, 1, 0x00f0, 0x10, 4, 1),
+ PIN_FIELD_BASE(74, 74, 1, 0x00f0, 0x10, 5, 1),
+ PIN_FIELD_BASE(75, 75, 1, 0x00f0, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, 1, 0x00f0, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, 1, 0x00f0, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, 1, 0x00f0, 0x10, 9, 1),
+ PIN_FIELD_BASE(79, 79, 5, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(80, 80, 5, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(81, 81, 5, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(82, 82, 5, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(83, 83, 6, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(84, 84, 3, 0x00e0, 0x10, 0, 1),
+ PIN_FIELD_BASE(85, 85, 3, 0x00e0, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 3, 0x00e0, 0x10, 2, 1),
+ PIN_FIELD_BASE(87, 87, 3, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(88, 88, 3, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(89, 89, 3, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(90, 90, 3, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(91, 91, 3, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(92, 92, 3, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(93, 93, 3, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(94, 94, 3, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(95, 95, 3, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(98, 98, 2, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(99, 99, 4, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(100, 100, 4, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(101, 101, 4, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(102, 102, 4, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(103, 103, 4, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(104, 104, 4, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(105, 105, 4, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(106, 106, 4, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(107, 107, 4, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(108, 108, 4, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(109, 109, 4, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(110, 110, 4, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(111, 111, 4, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(112, 112, 4, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(113, 113, 4, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(114, 114, 4, 0x0090, 0x10, 8, 1),
+ PIN_FIELD_BASE(115, 115, 3, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(116, 116, 3, 0x00e0, 0x10, 11, 1),
+ PIN_FIELD_BASE(117, 117, 3, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(118, 118, 3, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(119, 119, 5, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(120, 120, 5, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(121, 121, 5, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(122, 122, 5, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(123, 123, 5, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(124, 124, 5, 0x00e0, 0x10, 0, 1),
+ PIN_FIELD_BASE(125, 125, 5, 0x00e0, 0x10, 1, 1),
+ PIN_FIELD_BASE(126, 126, 5, 0x00e0, 0x10, 2, 1),
+ PIN_FIELD_BASE(127, 127, 3, 0x00e0, 0x10, 12, 1),
+ PIN_FIELD_BASE(128, 128, 3, 0x00e0, 0x10, 14, 1),
+ PIN_FIELD_BASE(129, 129, 5, 0x00e0, 0x10, 11, 1),
+ PIN_FIELD_BASE(130, 130, 5, 0x00e0, 0x10, 13, 1),
+ PIN_FIELD_BASE(131, 131, 5, 0x00e0, 0x10, 12, 1),
+ PIN_FIELD_BASE(132, 132, 5, 0x00e0, 0x10, 14, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x00f0, 0x10, 15, 1),
+ PIN_FIELD_BASE(134, 134, 1, 0x00f0, 0x10, 17, 1),
+ PIN_FIELD_BASE(135, 135, 6, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(136, 136, 6, 0x0080, 0x10, 9, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x00f0, 0x10, 16, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x00f0, 0x10, 18, 1),
+ PIN_FIELD_BASE(139, 139, 2, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(140, 140, 2, 0x0090, 0x10, 8, 1),
+ PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 13, 1),
+ PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 15, 1),
+ PIN_FIELD_BASE(143, 143, 6, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(144, 144, 6, 0x0080, 0x10, 10, 1),
+ PIN_FIELD_BASE(145, 145, 6, 0x0080, 0x10, 8, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(147, 147, 4, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(148, 148, 4, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(149, 149, 4, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(150, 150, 4, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(151, 151, 4, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(152, 152, 4, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(153, 153, 4, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(154, 154, 4, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(155, 155, 4, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(156, 156, 4, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(157, 157, 2, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(158, 158, 2, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(159, 159, 2, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(160, 160, 2, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(161, 161, 2, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(162, 162, 2, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(163, 163, 1, 0x00f0, 0x10, 14, 1),
+ PIN_FIELD_BASE(164, 164, 1, 0x00f0, 0x10, 12, 1),
+ PIN_FIELD_BASE(165, 165, 1, 0x00f0, 0x10, 12, 1),
+ PIN_FIELD_BASE(166, 166, 1, 0x00f0, 0x10, 13, 1),
+ PIN_FIELD_BASE(167, 167, 1, 0x00f0, 0x10, 13, 1),
+ PIN_FIELD_BASE(168, 168, 1, 0x00f0, 0x10, 12, 1),
+ PIN_FIELD_BASE(169, 169, 1, 0x00f0, 0x10, 14, 1),
+ PIN_FIELD_BASE(170, 170, 1, 0x00f0, 0x10, 13, 1),
+ PIN_FIELD_BASE(171, 171, 1, 0x00f0, 0x10, 13, 1),
+ PIN_FIELD_BASE(172, 172, 1, 0x00f0, 0x10, 14, 1),
+ PIN_FIELD_BASE(173, 173, 1, 0x00f0, 0x10, 12, 1),
+ PIN_FIELD_BASE(174, 174, 6, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(175, 175, 6, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(176, 176, 6, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(177, 177, 6, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(178, 178, 6, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(179, 179, 6, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(180, 180, 6, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(181, 181, 6, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(182, 182, 6, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(183, 183, 2, 0x0090, 0x10, 9, 1),
+ PIN_FIELD_BASE(184, 184, 2, 0x0090, 0x10, 10, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_pu_range[] = {
+ PIN_FIELD_BASE(0, 0, 6, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(1, 1, 6, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(2, 2, 6, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(3, 3, 6, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(4, 4, 6, 0x0050, 0x10, 19, 1),
+ PIN_FIELD_BASE(5, 5, 6, 0x0050, 0x10, 20, 1),
+ PIN_FIELD_BASE(6, 6, 4, 0x0060, 0x10, 19, 1),
+ PIN_FIELD_BASE(7, 7, 4, 0x0060, 0x10, 20, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0x0060, 0x10, 21, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0x0060, 0x10, 22, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(11, 11, 4, 0x0060, 0x10, 17, 1),
+ PIN_FIELD_BASE(12, 12, 4, 0x0060, 0x10, 18, 1),
+ PIN_FIELD_BASE(13, 13, 3, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(14, 14, 3, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(15, 15, 6, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(16, 16, 6, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(17, 17, 5, 0x0090, 0x10, 9, 1),
+ PIN_FIELD_BASE(18, 18, 5, 0x0090, 0x10, 10, 1),
+ PIN_FIELD_BASE(19, 19, 5, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(20, 20, 5, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(21, 21, 5, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(22, 22, 5, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(23, 23, 5, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(24, 24, 5, 0x0090, 0x10, 8, 1),
+ PIN_FIELD_BASE(25, 25, 5, 0x0090, 0x10, 18, 1),
+ PIN_FIELD_BASE(26, 26, 5, 0x0090, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, 5, 0x0090, 0x10, 17, 1),
+ PIN_FIELD_BASE(28, 28, 5, 0x0090, 0x10, 16, 1),
+ PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(32, 32, 2, 0x0060, 0x10, 25, 1),
+ PIN_FIELD_BASE(33, 33, 2, 0x0060, 0x10, 27, 1),
+ PIN_FIELD_BASE(34, 34, 2, 0x0060, 0x10, 26, 1),
+ PIN_FIELD_BASE(35, 35, 2, 0x0060, 0x10, 28, 1),
+ PIN_FIELD_BASE(36, 36, 2, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(40, 40, 2, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(41, 41, 2, 0x0060, 0x10, 14, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x0060, 0x10, 15, 1),
+ PIN_FIELD_BASE(44, 44, 5, 0x0090, 0x10, 28, 1),
+ PIN_FIELD_BASE(45, 45, 5, 0x0090, 0x10, 29, 1),
+ PIN_FIELD_BASE(46, 46, 5, 0x0090, 0x10, 31, 1),
+ PIN_FIELD_BASE(47, 47, 5, 0x0090, 0x10, 30, 1),
+ PIN_FIELD_BASE(48, 48, 2, 0x0060, 0x10, 17, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x0060, 0x10, 18, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x0060, 0x10, 20, 1),
+ PIN_FIELD_BASE(51, 51, 2, 0x0060, 0x10, 19, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x0080, 0x10, 12, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x0080, 0x10, 13, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x0080, 0x10, 15, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0080, 0x10, 14, 1),
+ PIN_FIELD_BASE(56, 56, 5, 0x0090, 0x10, 12, 1),
+ PIN_FIELD_BASE(57, 57, 5, 0x0090, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, 5, 0x0090, 0x10, 13, 1),
+ PIN_FIELD_BASE(59, 59, 5, 0x0090, 0x10, 14, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x0080, 0x10, 21, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0080, 0x10, 16, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0080, 0x10, 22, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0080, 0x10, 17, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0080, 0x10, 18, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0080, 0x10, 19, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0080, 0x10, 20, 1),
+ PIN_FIELD_BASE(83, 83, 6, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(91, 91, 3, 0x0080, 0x10, 23, 1),
+ PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 25, 1),
+ PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 24, 1),
+ PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 26, 1),
+ PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(99, 99, 4, 0x0060, 0x10, 14, 1),
+ PIN_FIELD_BASE(100, 100, 4, 0x0060, 0x10, 15, 1),
+ PIN_FIELD_BASE(101, 101, 4, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(102, 102, 4, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(103, 103, 4, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(104, 104, 4, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(105, 105, 4, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(106, 106, 4, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(107, 107, 4, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(108, 108, 4, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(109, 109, 4, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(110, 110, 4, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(111, 111, 4, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(112, 112, 4, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(113, 113, 4, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(114, 114, 4, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(115, 115, 3, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(116, 116, 3, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(117, 117, 3, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(118, 118, 3, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(119, 119, 5, 0x0090, 0x10, 22, 1),
+ PIN_FIELD_BASE(120, 120, 5, 0x0090, 0x10, 19, 1),
+ PIN_FIELD_BASE(121, 121, 5, 0x0090, 0x10, 20, 1),
+ PIN_FIELD_BASE(122, 122, 5, 0x0090, 0x10, 21, 1),
+ PIN_FIELD_BASE(123, 123, 5, 0x0090, 0x10, 23, 1),
+ PIN_FIELD_BASE(124, 124, 5, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(125, 125, 5, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(126, 126, 5, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(127, 127, 3, 0x0080, 0x10, 8, 1),
+ PIN_FIELD_BASE(128, 128, 3, 0x0080, 0x10, 10, 1),
+ PIN_FIELD_BASE(129, 129, 5, 0x0090, 0x10, 24, 1),
+ PIN_FIELD_BASE(130, 130, 5, 0x0090, 0x10, 26, 1),
+ PIN_FIELD_BASE(131, 131, 5, 0x0090, 0x10, 25, 1),
+ PIN_FIELD_BASE(132, 132, 5, 0x0090, 0x10, 27, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 9, 1),
+ PIN_FIELD_BASE(134, 134, 1, 0x0080, 0x10, 12, 1),
+ PIN_FIELD_BASE(135, 135, 6, 0x0050, 0x10, 21, 1),
+ PIN_FIELD_BASE(136, 136, 6, 0x0050, 0x10, 24, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x0080, 0x10, 10, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x0080, 0x10, 13, 1),
+ PIN_FIELD_BASE(139, 139, 2, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(140, 140, 2, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(141, 141, 3, 0x0080, 0x10, 9, 1),
+ PIN_FIELD_BASE(142, 142, 3, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(143, 143, 6, 0x0050, 0x10, 22, 1),
+ PIN_FIELD_BASE(144, 144, 6, 0x0050, 0x10, 25, 1),
+ PIN_FIELD_BASE(145, 145, 6, 0x0050, 0x10, 23, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x0050, 0x10, 26, 1),
+ PIN_FIELD_BASE(147, 147, 4, 0x0060, 0x10, 23, 1),
+ PIN_FIELD_BASE(148, 148, 4, 0x0060, 0x10, 24, 1),
+ PIN_FIELD_BASE(149, 149, 4, 0x0060, 0x10, 25, 1),
+ PIN_FIELD_BASE(150, 150, 4, 0x0060, 0x10, 26, 1),
+ PIN_FIELD_BASE(151, 151, 4, 0x0060, 0x10, 27, 1),
+ PIN_FIELD_BASE(152, 152, 4, 0x0060, 0x10, 28, 1),
+ PIN_FIELD_BASE(153, 153, 4, 0x0060, 0x10, 29, 1),
+ PIN_FIELD_BASE(154, 154, 4, 0x0060, 0x10, 30, 1),
+ PIN_FIELD_BASE(155, 155, 4, 0x0060, 0x10, 31, 1),
+ PIN_FIELD_BASE(156, 156, 4, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(157, 157, 2, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(158, 158, 2, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(159, 159, 2, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(160, 160, 2, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(161, 161, 2, 0x0060, 0x10, 23, 1),
+ PIN_FIELD_BASE(162, 162, 2, 0x0060, 0x10, 24, 1),
+ PIN_FIELD_BASE(163, 163, 1, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(164, 164, 1, 0x0080, 0x10, 8, 1),
+ PIN_FIELD_BASE(165, 165, 1, 0x0080, 0x10, 16, 1),
+ PIN_FIELD_BASE(166, 166, 1, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(167, 167, 1, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(168, 168, 1, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(169, 169, 1, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(170, 170, 1, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(171, 171, 1, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(172, 172, 1, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(173, 173, 1, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(174, 174, 6, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(175, 175, 6, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(176, 176, 6, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(177, 177, 6, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(178, 178, 6, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(179, 179, 6, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(180, 180, 6, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(181, 181, 6, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(182, 182, 6, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(183, 183, 2, 0x0060, 0x10, 21, 1),
+ PIN_FIELD_BASE(184, 184, 2, 0x0060, 0x10, 22, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_pd_range[] = {
+ PIN_FIELD_BASE(0, 0, 6, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(1, 1, 6, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(2, 2, 6, 0x0040, 0x10, 17, 1),
+ PIN_FIELD_BASE(3, 3, 6, 0x0040, 0x10, 18, 1),
+ PIN_FIELD_BASE(4, 4, 6, 0x0040, 0x10, 19, 1),
+ PIN_FIELD_BASE(5, 5, 6, 0x0040, 0x10, 20, 1),
+ PIN_FIELD_BASE(6, 6, 4, 0x0040, 0x10, 19, 1),
+ PIN_FIELD_BASE(7, 7, 4, 0x0040, 0x10, 20, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0x0040, 0x10, 21, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0x0040, 0x10, 22, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(11, 11, 4, 0x0040, 0x10, 17, 1),
+ PIN_FIELD_BASE(12, 12, 4, 0x0040, 0x10, 18, 1),
+ PIN_FIELD_BASE(13, 13, 3, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(14, 14, 3, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(17, 17, 5, 0x0070, 0x10, 9, 1),
+ PIN_FIELD_BASE(18, 18, 5, 0x0070, 0x10, 10, 1),
+ PIN_FIELD_BASE(19, 19, 5, 0x0070, 0x10, 3, 1),
+ PIN_FIELD_BASE(20, 20, 5, 0x0070, 0x10, 6, 1),
+ PIN_FIELD_BASE(21, 21, 5, 0x0070, 0x10, 4, 1),
+ PIN_FIELD_BASE(22, 22, 5, 0x0070, 0x10, 7, 1),
+ PIN_FIELD_BASE(23, 23, 5, 0x0070, 0x10, 5, 1),
+ PIN_FIELD_BASE(24, 24, 5, 0x0070, 0x10, 8, 1),
+ PIN_FIELD_BASE(25, 25, 5, 0x0070, 0x10, 18, 1),
+ PIN_FIELD_BASE(26, 26, 5, 0x0070, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, 5, 0x0070, 0x10, 17, 1),
+ PIN_FIELD_BASE(28, 28, 5, 0x0070, 0x10, 16, 1),
+ PIN_FIELD_BASE(29, 29, 6, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(30, 30, 6, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(31, 31, 6, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(32, 32, 2, 0x0050, 0x10, 25, 1),
+ PIN_FIELD_BASE(33, 33, 2, 0x0050, 0x10, 27, 1),
+ PIN_FIELD_BASE(34, 34, 2, 0x0050, 0x10, 26, 1),
+ PIN_FIELD_BASE(35, 35, 2, 0x0050, 0x10, 28, 1),
+ PIN_FIELD_BASE(36, 36, 2, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(40, 40, 2, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(41, 41, 2, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(44, 44, 5, 0x0070, 0x10, 28, 1),
+ PIN_FIELD_BASE(45, 45, 5, 0x0070, 0x10, 29, 1),
+ PIN_FIELD_BASE(46, 46, 5, 0x0070, 0x10, 31, 1),
+ PIN_FIELD_BASE(47, 47, 5, 0x0070, 0x10, 30, 1),
+ PIN_FIELD_BASE(48, 48, 2, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x0050, 0x10, 20, 1),
+ PIN_FIELD_BASE(51, 51, 2, 0x0050, 0x10, 19, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x0060, 0x10, 15, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 14, 1),
+ PIN_FIELD_BASE(56, 56, 5, 0x0070, 0x10, 12, 1),
+ PIN_FIELD_BASE(57, 57, 5, 0x0070, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, 5, 0x0070, 0x10, 13, 1),
+ PIN_FIELD_BASE(59, 59, 5, 0x0070, 0x10, 14, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 21, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0060, 0x10, 22, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0060, 0x10, 17, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0060, 0x10, 18, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0060, 0x10, 19, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0060, 0x10, 20, 1),
+ PIN_FIELD_BASE(83, 83, 6, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(91, 91, 3, 0x0060, 0x10, 23, 1),
+ PIN_FIELD_BASE(92, 92, 3, 0x0060, 0x10, 25, 1),
+ PIN_FIELD_BASE(93, 93, 3, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(94, 94, 3, 0x0060, 0x10, 24, 1),
+ PIN_FIELD_BASE(95, 95, 3, 0x0060, 0x10, 26, 1),
+ PIN_FIELD_BASE(96, 96, 2, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(97, 97, 2, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(98, 98, 2, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(99, 99, 4, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(100, 100, 4, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(101, 101, 4, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(102, 102, 4, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(103, 103, 4, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(104, 104, 4, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(105, 105, 4, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(106, 106, 4, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(107, 107, 4, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(108, 108, 4, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(109, 109, 4, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(110, 110, 4, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(111, 111, 4, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(112, 112, 4, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(113, 113, 4, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(114, 114, 4, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(115, 115, 3, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(116, 116, 3, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(117, 117, 3, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(118, 118, 3, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(119, 119, 5, 0x0070, 0x10, 22, 1),
+ PIN_FIELD_BASE(120, 120, 5, 0x0070, 0x10, 19, 1),
+ PIN_FIELD_BASE(121, 121, 5, 0x0070, 0x10, 20, 1),
+ PIN_FIELD_BASE(122, 122, 5, 0x0070, 0x10, 21, 1),
+ PIN_FIELD_BASE(123, 123, 5, 0x0070, 0x10, 23, 1),
+ PIN_FIELD_BASE(124, 124, 5, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(125, 125, 5, 0x0070, 0x10, 1, 1),
+ PIN_FIELD_BASE(126, 126, 5, 0x0070, 0x10, 2, 1),
+ PIN_FIELD_BASE(127, 127, 3, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(128, 128, 3, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(129, 129, 5, 0x0070, 0x10, 24, 1),
+ PIN_FIELD_BASE(130, 130, 5, 0x0070, 0x10, 26, 1),
+ PIN_FIELD_BASE(131, 131, 5, 0x0070, 0x10, 25, 1),
+ PIN_FIELD_BASE(132, 132, 5, 0x0070, 0x10, 27, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(134, 134, 1, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(135, 135, 6, 0x0040, 0x10, 21, 1),
+ PIN_FIELD_BASE(136, 136, 6, 0x0040, 0x10, 24, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(139, 139, 2, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(140, 140, 2, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(141, 141, 3, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(142, 142, 3, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(143, 143, 6, 0x0040, 0x10, 22, 1),
+ PIN_FIELD_BASE(144, 144, 6, 0x0040, 0x10, 25, 1),
+ PIN_FIELD_BASE(145, 145, 6, 0x0040, 0x10, 23, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x0040, 0x10, 26, 1),
+ PIN_FIELD_BASE(147, 147, 4, 0x0040, 0x10, 23, 1),
+ PIN_FIELD_BASE(148, 148, 4, 0x0040, 0x10, 24, 1),
+ PIN_FIELD_BASE(149, 149, 4, 0x0040, 0x10, 25, 1),
+ PIN_FIELD_BASE(150, 150, 4, 0x0040, 0x10, 26, 1),
+ PIN_FIELD_BASE(151, 151, 4, 0x0040, 0x10, 27, 1),
+ PIN_FIELD_BASE(152, 152, 4, 0x0040, 0x10, 28, 1),
+ PIN_FIELD_BASE(153, 153, 4, 0x0040, 0x10, 29, 1),
+ PIN_FIELD_BASE(154, 154, 4, 0x0040, 0x10, 30, 1),
+ PIN_FIELD_BASE(155, 155, 4, 0x0040, 0x10, 31, 1),
+ PIN_FIELD_BASE(156, 156, 4, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(157, 157, 2, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(158, 158, 2, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(159, 159, 2, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(160, 160, 2, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(161, 161, 2, 0x0050, 0x10, 23, 1),
+ PIN_FIELD_BASE(162, 162, 2, 0x0050, 0x10, 24, 1),
+ PIN_FIELD_BASE(163, 163, 1, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(164, 164, 1, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(165, 165, 1, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(166, 166, 1, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(167, 167, 1, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(168, 168, 1, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(169, 169, 1, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(170, 170, 1, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(171, 171, 1, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(172, 172, 1, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(173, 173, 1, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(174, 174, 6, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(175, 175, 6, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(176, 176, 6, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(177, 177, 6, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(178, 178, 6, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(179, 179, 6, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(180, 180, 6, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(181, 181, 6, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(182, 182, 6, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(183, 183, 2, 0x0050, 0x10, 21, 1),
+ PIN_FIELD_BASE(184, 184, 2, 0x0050, 0x10, 22, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_pupd_range[] = {
+ PIN_FIELD_BASE(67, 67, 1, 0x0070, 0x10, 10, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(69, 69, 1, 0x0070, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 1, 0x0070, 0x10, 11, 1),
+ PIN_FIELD_BASE(71, 71, 1, 0x0070, 0x10, 2, 1),
+ PIN_FIELD_BASE(72, 72, 1, 0x0070, 0x10, 3, 1),
+ PIN_FIELD_BASE(73, 73, 1, 0x0070, 0x10, 4, 1),
+ PIN_FIELD_BASE(74, 74, 1, 0x0070, 0x10, 5, 1),
+ PIN_FIELD_BASE(75, 75, 1, 0x0070, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, 1, 0x0070, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, 1, 0x0070, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, 1, 0x0070, 0x10, 9, 1),
+ PIN_FIELD_BASE(79, 79, 5, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(80, 80, 5, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(81, 81, 5, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(82, 82, 5, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 3, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(85, 85, 3, 0x0070, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 3, 0x0070, 0x10, 2, 1),
+ PIN_FIELD_BASE(87, 87, 3, 0x0070, 0x10, 3, 1),
+ PIN_FIELD_BASE(88, 88, 3, 0x0070, 0x10, 4, 1),
+ PIN_FIELD_BASE(89, 89, 3, 0x0070, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_r0_range[] = {
+ PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 10, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(69, 69, 1, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 1, 0x0090, 0x10, 11, 1),
+ PIN_FIELD_BASE(71, 71, 1, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(72, 72, 1, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(73, 73, 1, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(74, 74, 1, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(75, 75, 1, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, 1, 0x0090, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, 1, 0x0090, 0x10, 9, 1),
+ PIN_FIELD_BASE(79, 79, 5, 0x00a0, 0x10, 0, 1),
+ PIN_FIELD_BASE(80, 80, 5, 0x00a0, 0x10, 1, 1),
+ PIN_FIELD_BASE(81, 81, 5, 0x00a0, 0x10, 2, 1),
+ PIN_FIELD_BASE(82, 82, 5, 0x00a0, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 3, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(85, 85, 3, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 3, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(87, 87, 3, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(88, 88, 3, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(89, 89, 3, 0x0090, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_r1_range[] = {
+ PIN_FIELD_BASE(67, 67, 1, 0x00a0, 0x10, 10, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x00a0, 0x10, 0, 1),
+ PIN_FIELD_BASE(69, 69, 1, 0x00a0, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 1, 0x00a0, 0x10, 11, 1),
+ PIN_FIELD_BASE(71, 71, 1, 0x00a0, 0x10, 2, 1),
+ PIN_FIELD_BASE(72, 72, 1, 0x00a0, 0x10, 3, 1),
+ PIN_FIELD_BASE(73, 73, 1, 0x00a0, 0x10, 4, 1),
+ PIN_FIELD_BASE(74, 74, 1, 0x00a0, 0x10, 5, 1),
+ PIN_FIELD_BASE(75, 75, 1, 0x00a0, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, 1, 0x00a0, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, 1, 0x00a0, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, 1, 0x00a0, 0x10, 9, 1),
+ PIN_FIELD_BASE(79, 79, 5, 0x00b0, 0x10, 0, 1),
+ PIN_FIELD_BASE(80, 80, 5, 0x00b0, 0x10, 1, 1),
+ PIN_FIELD_BASE(81, 81, 5, 0x00b0, 0x10, 2, 1),
+ PIN_FIELD_BASE(82, 82, 5, 0x00b0, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 0, 1),
+ PIN_FIELD_BASE(85, 85, 3, 0x00a0, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 3, 0x00a0, 0x10, 2, 1),
+ PIN_FIELD_BASE(87, 87, 3, 0x00a0, 0x10, 3, 1),
+ PIN_FIELD_BASE(88, 88, 3, 0x00a0, 0x10, 4, 1),
+ PIN_FIELD_BASE(89, 89, 3, 0x00a0, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_drv_range[] = {
+ PIN_FIELD_BASE(0, 0, 6, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(1, 1, 6, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(2, 2, 6, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(3, 3, 6, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(4, 4, 6, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(5, 5, 6, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(6, 6, 4, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(7, 7, 4, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(8, 8, 4, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(9, 9, 4, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(10, 10, 4, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(11, 11, 4, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(12, 12, 4, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(13, 13, 3, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(14, 14, 3, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(15, 15, 6, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(17, 17, 5, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(18, 18, 5, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(19, 19, 5, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(20, 20, 5, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(21, 21, 5, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(22, 22, 5, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(23, 23, 5, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(24, 24, 5, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(25, 25, 5, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(26, 26, 5, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(27, 27, 5, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(28, 28, 5, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(29, 29, 6, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(30, 30, 6, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(31, 31, 6, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(32, 32, 2, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(33, 33, 2, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(34, 34, 2, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(35, 35, 2, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(36, 36, 2, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(37, 37, 2, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(38, 38, 2, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(39, 39, 2, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(40, 40, 2, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(41, 41, 2, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(42, 42, 2, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(43, 43, 2, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(44, 44, 5, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(45, 45, 5, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(46, 46, 5, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(47, 47, 5, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(48, 48, 2, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(49, 49, 2, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(50, 50, 2, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(51, 51, 2, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(52, 52, 3, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(53, 53, 3, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(54, 54, 3, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(56, 56, 5, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(57, 57, 5, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(58, 58, 5, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(59, 59, 5, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(60, 60, 3, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(61, 61, 3, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(62, 62, 3, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(63, 63, 3, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(64, 64, 3, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(65, 65, 3, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(66, 66, 3, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(67, 67, 1, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(68, 68, 1, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(69, 69, 1, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(70, 70, 1, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(71, 71, 1, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(72, 72, 1, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(73, 73, 1, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(74, 74, 1, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(75, 75, 1, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(76, 76, 1, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(77, 77, 1, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(78, 78, 1, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(79, 79, 5, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(80, 80, 5, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(81, 81, 5, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(82, 82, 5, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(83, 83, 6, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(84, 84, 3, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(85, 85, 3, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(86, 86, 3, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(87, 87, 3, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(88, 88, 3, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(89, 89, 3, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(91, 91, 3, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(92, 92, 3, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(93, 93, 3, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(94, 94, 3, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(95, 95, 3, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(96, 96, 2, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(97, 97, 2, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(98, 98, 2, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(99, 99, 4, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(100, 100, 4, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(101, 101, 4, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(102, 102, 4, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(103, 103, 4, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(104, 104, 4, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(105, 105, 4, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(106, 106, 4, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(107, 107, 4, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(108, 108, 4, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(109, 109, 4, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(110, 110, 4, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(111, 111, 4, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(112, 112, 4, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(113, 113, 4, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(114, 114, 4, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(115, 115, 3, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(116, 116, 3, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(117, 117, 3, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(118, 118, 3, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(119, 119, 5, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(120, 120, 5, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(121, 121, 5, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(122, 122, 5, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(123, 123, 5, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(124, 124, 5, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(125, 125, 5, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(126, 126, 5, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(127, 127, 3, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(128, 128, 3, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(129, 129, 5, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(130, 130, 5, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(131, 131, 5, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(132, 132, 5, 0x0010, 0x10, 21, 3),
+ PIN_FIELD_BASE(133, 133, 1, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(134, 134, 1, 0x0010, 0x10, 21, 3),
+ PIN_FIELD_BASE(135, 135, 6, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(136, 136, 6, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(137, 137, 1, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(138, 138, 1, 0x0010, 0x10, 24, 3),
+ PIN_FIELD_BASE(139, 139, 2, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(140, 140, 2, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(141, 141, 3, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(142, 142, 3, 0x0010, 0x10, 21, 3),
+ PIN_FIELD_BASE(143, 143, 6, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(144, 144, 6, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(145, 145, 6, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(146, 146, 6, 0x0010, 0x10, 21, 3),
+ PIN_FIELD_BASE(147, 147, 4, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(148, 148, 4, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(149, 149, 4, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(150, 150, 4, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(151, 151, 4, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(152, 152, 4, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(153, 153, 4, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(154, 154, 4, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(155, 155, 4, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(156, 156, 4, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(157, 157, 2, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(158, 158, 2, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(159, 159, 2, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(160, 160, 2, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(161, 161, 2, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(162, 162, 2, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(163, 163, 1, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(165, 165, 1, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(166, 166, 1, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(167, 167, 1, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(168, 168, 1, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(169, 169, 1, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(170, 170, 1, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(171, 171, 1, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(172, 172, 1, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(173, 173, 1, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(174, 174, 6, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(175, 175, 6, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(176, 176, 6, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(177, 177, 6, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(178, 178, 6, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(179, 179, 6, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(180, 180, 6, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(181, 181, 6, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(182, 182, 6, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(183, 183, 2, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(184, 184, 2, 0x0010, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_drv_adv_range[] = {
+ PIN_FIELD_BASE(127, 127, 3, 0x0030, 0x10, 0, 3),
+ PIN_FIELD_BASE(128, 128, 3, 0x0030, 0x10, 6, 3),
+ PIN_FIELD_BASE(129, 129, 5, 0x0030, 0x10, 0, 3),
+ PIN_FIELD_BASE(130, 130, 5, 0x0030, 0x10, 6, 3),
+ PIN_FIELD_BASE(131, 131, 5, 0x0030, 0x10, 3, 3),
+ PIN_FIELD_BASE(132, 132, 5, 0x0030, 0x10, 9, 3),
+ PIN_FIELD_BASE(133, 133, 1, 0x0030, 0x10, 0, 3),
+ PIN_FIELD_BASE(134, 134, 1, 0x0030, 0x10, 6, 3),
+ PIN_FIELD_BASE(135, 135, 6, 0x0020, 0x10, 0, 3),
+ PIN_FIELD_BASE(136, 136, 6, 0x0020, 0x10, 9, 3),
+ PIN_FIELD_BASE(137, 137, 1, 0x0030, 0x10, 3, 3),
+ PIN_FIELD_BASE(138, 138, 1, 0x0030, 0x10, 9, 3),
+ PIN_FIELD_BASE(139, 139, 2, 0x0020, 0x10, 0, 3),
+ PIN_FIELD_BASE(140, 140, 2, 0x0020, 0x10, 3, 3),
+ PIN_FIELD_BASE(141, 141, 3, 0x0030, 0x10, 3, 3),
+ PIN_FIELD_BASE(142, 142, 3, 0x0030, 0x10, 9, 3),
+ PIN_FIELD_BASE(143, 143, 6, 0x0020, 0x10, 3, 3),
+ PIN_FIELD_BASE(144, 144, 6, 0x0020, 0x10, 12, 3),
+ PIN_FIELD_BASE(145, 145, 6, 0x0020, 0x10, 6, 3),
+ PIN_FIELD_BASE(146, 146, 6, 0x0020, 0x10, 15, 3),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_rsel_range[] = {
+ PIN_FIELD_BASE(127, 127, 3, 0x00d0, 0x10, 0, 2),
+ PIN_FIELD_BASE(128, 128, 3, 0x00d0, 0x10, 4, 2),
+ PIN_FIELD_BASE(129, 129, 5, 0x00d0, 0x10, 0, 2),
+ PIN_FIELD_BASE(130, 130, 5, 0x00d0, 0x10, 4, 2),
+ PIN_FIELD_BASE(131, 131, 5, 0x00d0, 0x10, 2, 2),
+ PIN_FIELD_BASE(132, 132, 5, 0x00d0, 0x10, 6, 2),
+ PIN_FIELD_BASE(133, 133, 1, 0x00e0, 0x10, 0, 2),
+ PIN_FIELD_BASE(134, 134, 1, 0x00e0, 0x10, 4, 2),
+ PIN_FIELD_BASE(135, 135, 6, 0x0070, 0x10, 0, 2),
+ PIN_FIELD_BASE(136, 136, 6, 0x0070, 0x10, 6, 2),
+ PIN_FIELD_BASE(137, 137, 1, 0x00e0, 0x10, 2, 2),
+ PIN_FIELD_BASE(138, 138, 1, 0x00e0, 0x10, 6, 2),
+ PIN_FIELD_BASE(139, 139, 2, 0x0080, 0x10, 0, 2),
+ PIN_FIELD_BASE(140, 140, 2, 0x0080, 0x10, 2, 2),
+ PIN_FIELD_BASE(141, 141, 3, 0x00d0, 0x10, 2, 2),
+ PIN_FIELD_BASE(142, 142, 3, 0x00d0, 0x10, 6, 2),
+ PIN_FIELD_BASE(143, 143, 6, 0x0070, 0x10, 2, 2),
+ PIN_FIELD_BASE(144, 144, 6, 0x0070, 0x10, 8, 2),
+ PIN_FIELD_BASE(145, 145, 6, 0x0070, 0x10, 4, 2),
+ PIN_FIELD_BASE(146, 146, 6, 0x0070, 0x10, 10, 2),
+};
+
+static const struct mtk_pin_rsel mt8186_pin_rsel_val_range[] = {
+ PIN_RSEL(127, 128, 0x0, 75000, 75000),
+ PIN_RSEL(127, 128, 0x1, 10000, 5000),
+ PIN_RSEL(127, 128, 0x2, 5000, 75000),
+ PIN_RSEL(127, 128, 0x3, 4000, 5000),
+ PIN_RSEL(127, 128, 0x4, 3000, 75000),
+ PIN_RSEL(127, 128, 0x5, 2000, 5000),
+ PIN_RSEL(127, 128, 0x6, 1500, 75000),
+ PIN_RSEL(127, 128, 0x7, 1000, 5000),
+ PIN_RSEL(129, 130, 0x0, 75000, 75000),
+ PIN_RSEL(129, 130, 0x1, 10000, 5000),
+ PIN_RSEL(129, 130, 0x2, 5000, 75000),
+ PIN_RSEL(129, 130, 0x3, 4000, 5000),
+ PIN_RSEL(129, 130, 0x4, 3000, 75000),
+ PIN_RSEL(129, 130, 0x5, 2000, 5000),
+ PIN_RSEL(129, 130, 0x6, 1500, 75000),
+ PIN_RSEL(129, 130, 0x7, 1000, 5000),
+ PIN_RSEL(131, 132, 0x0, 75000, 75000),
+ PIN_RSEL(131, 132, 0x1, 10000, 5000),
+ PIN_RSEL(131, 132, 0x2, 5000, 75000),
+ PIN_RSEL(131, 132, 0x3, 4000, 5000),
+ PIN_RSEL(131, 132, 0x4, 3000, 75000),
+ PIN_RSEL(131, 132, 0x5, 2000, 5000),
+ PIN_RSEL(131, 132, 0x6, 1500, 75000),
+ PIN_RSEL(131, 132, 0x7, 1000, 5000),
+ PIN_RSEL(133, 134, 0x0, 75000, 75000),
+ PIN_RSEL(133, 134, 0x1, 10000, 5000),
+ PIN_RSEL(133, 134, 0x2, 5000, 75000),
+ PIN_RSEL(133, 134, 0x3, 4000, 5000),
+ PIN_RSEL(133, 134, 0x4, 3000, 75000),
+ PIN_RSEL(133, 134, 0x5, 2000, 5000),
+ PIN_RSEL(133, 134, 0x6, 1500, 75000),
+ PIN_RSEL(133, 134, 0x7, 1000, 5000),
+ PIN_RSEL(135, 136, 0x0, 75000, 75000),
+ PIN_RSEL(135, 136, 0x1, 10000, 5000),
+ PIN_RSEL(135, 136, 0x2, 5000, 75000),
+ PIN_RSEL(135, 136, 0x3, 4000, 5000),
+ PIN_RSEL(135, 136, 0x4, 3000, 75000),
+ PIN_RSEL(135, 136, 0x5, 2000, 5000),
+ PIN_RSEL(135, 136, 0x6, 1500, 75000),
+ PIN_RSEL(135, 136, 0x7, 1000, 5000),
+ PIN_RSEL(137, 138, 0x0, 75000, 75000),
+ PIN_RSEL(137, 138, 0x1, 10000, 5000),
+ PIN_RSEL(137, 138, 0x2, 5000, 75000),
+ PIN_RSEL(137, 138, 0x3, 4000, 5000),
+ PIN_RSEL(137, 138, 0x4, 3000, 75000),
+ PIN_RSEL(137, 138, 0x5, 2000, 5000),
+ PIN_RSEL(137, 138, 0x6, 1500, 75000),
+ PIN_RSEL(137, 138, 0x7, 1000, 5000),
+ PIN_RSEL(139, 140, 0x0, 75000, 75000),
+ PIN_RSEL(139, 140, 0x1, 10000, 5000),
+ PIN_RSEL(139, 140, 0x2, 5000, 75000),
+ PIN_RSEL(139, 140, 0x3, 4000, 5000),
+ PIN_RSEL(139, 140, 0x4, 3000, 75000),
+ PIN_RSEL(139, 140, 0x5, 2000, 5000),
+ PIN_RSEL(139, 140, 0x6, 1500, 75000),
+ PIN_RSEL(139, 140, 0x7, 1000, 5000),
+ PIN_RSEL(141, 142, 0x0, 75000, 75000),
+ PIN_RSEL(141, 142, 0x1, 10000, 5000),
+ PIN_RSEL(141, 142, 0x2, 5000, 75000),
+ PIN_RSEL(141, 142, 0x3, 4000, 5000),
+ PIN_RSEL(141, 142, 0x4, 3000, 75000),
+ PIN_RSEL(141, 142, 0x5, 2000, 5000),
+ PIN_RSEL(141, 142, 0x6, 1500, 75000),
+ PIN_RSEL(141, 142, 0x7, 1000, 5000),
+ PIN_RSEL(143, 144, 0x0, 75000, 75000),
+ PIN_RSEL(143, 144, 0x1, 10000, 5000),
+ PIN_RSEL(143, 144, 0x2, 5000, 75000),
+ PIN_RSEL(143, 144, 0x3, 4000, 5000),
+ PIN_RSEL(143, 144, 0x4, 3000, 75000),
+ PIN_RSEL(143, 144, 0x5, 2000, 5000),
+ PIN_RSEL(143, 144, 0x6, 1500, 75000),
+ PIN_RSEL(143, 144, 0x7, 1000, 5000),
+ PIN_RSEL(145, 146, 0x0, 75000, 75000),
+ PIN_RSEL(145, 146, 0x1, 10000, 5000),
+ PIN_RSEL(145, 146, 0x2, 5000, 75000),
+ PIN_RSEL(145, 146, 0x3, 4000, 5000),
+ PIN_RSEL(145, 146, 0x4, 3000, 75000),
+ PIN_RSEL(145, 146, 0x5, 2000, 5000),
+ PIN_RSEL(145, 146, 0x6, 1500, 75000),
+ PIN_RSEL(145, 146, 0x7, 1000, 5000),
+};
+
+static const unsigned int mt8186_pull_type[] = {
+ MTK_PULL_PU_PD_TYPE,/*0*/ MTK_PULL_PU_PD_TYPE,/*1*/
+ MTK_PULL_PU_PD_TYPE,/*2*/ MTK_PULL_PU_PD_TYPE,/*3*/
+ MTK_PULL_PU_PD_TYPE,/*4*/ MTK_PULL_PU_PD_TYPE,/*5*/
+ MTK_PULL_PU_PD_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,/*7*/
+ MTK_PULL_PU_PD_TYPE,/*8*/ MTK_PULL_PU_PD_TYPE,/*9*/
+ MTK_PULL_PU_PD_TYPE,/*10*/ MTK_PULL_PU_PD_TYPE,/*11*/
+ MTK_PULL_PU_PD_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE,/*13*/
+ MTK_PULL_PU_PD_TYPE,/*14*/ MTK_PULL_PU_PD_TYPE,/*15*/
+ MTK_PULL_PU_PD_TYPE,/*16*/ MTK_PULL_PU_PD_TYPE,/*17*/
+ MTK_PULL_PU_PD_TYPE,/*18*/ MTK_PULL_PU_PD_TYPE,/*19*/
+ MTK_PULL_PU_PD_TYPE,/*20*/ MTK_PULL_PU_PD_TYPE,/*21*/
+ MTK_PULL_PU_PD_TYPE,/*22*/ MTK_PULL_PU_PD_TYPE,/*23*/
+ MTK_PULL_PU_PD_TYPE,/*24*/ MTK_PULL_PU_PD_TYPE,/*25*/
+ MTK_PULL_PU_PD_TYPE,/*26*/ MTK_PULL_PU_PD_TYPE,/*27*/
+ MTK_PULL_PU_PD_TYPE,/*28*/ MTK_PULL_PU_PD_TYPE,/*29*/
+ MTK_PULL_PU_PD_TYPE,/*30*/ MTK_PULL_PU_PD_TYPE,/*31*/
+ MTK_PULL_PU_PD_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/
+ MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/
+ MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/
+ MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PU_PD_TYPE,/*39*/
+ MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
+ MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
+ MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/
+ MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/
+ MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/
+ MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/
+ MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/
+ MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/
+ MTK_PULL_PU_PD_TYPE,/*56*/ MTK_PULL_PU_PD_TYPE,/*57*/
+ MTK_PULL_PU_PD_TYPE,/*58*/ MTK_PULL_PU_PD_TYPE,/*59*/
+ MTK_PULL_PU_PD_TYPE,/*60*/ MTK_PULL_PU_PD_TYPE,/*61*/
+ MTK_PULL_PU_PD_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,/*63*/
+ MTK_PULL_PU_PD_TYPE,/*64*/ MTK_PULL_PU_PD_TYPE,/*65*/
+ MTK_PULL_PU_PD_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PUPD_R1R0_TYPE,/*71*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PUPD_R1R0_TYPE,/*75*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*76*/ MTK_PULL_PUPD_R1R0_TYPE,/*77*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*78*/ MTK_PULL_PUPD_R1R0_TYPE,/*79*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*84*/ MTK_PULL_PUPD_R1R0_TYPE,/*85*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*86*/ MTK_PULL_PUPD_R1R0_TYPE,/*87*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*88*/ MTK_PULL_PUPD_R1R0_TYPE,/*89*/
+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
+ MTK_PULL_PU_PD_TYPE,/*100*/ MTK_PULL_PU_PD_TYPE,/*101*/
+ MTK_PULL_PU_PD_TYPE,/*102*/ MTK_PULL_PU_PD_TYPE,/*103*/
+ MTK_PULL_PU_PD_TYPE,/*104*/ MTK_PULL_PU_PD_TYPE,/*105*/
+ MTK_PULL_PU_PD_TYPE,/*106*/ MTK_PULL_PU_PD_TYPE,/*107*/
+ MTK_PULL_PU_PD_TYPE,/*108*/ MTK_PULL_PU_PD_TYPE,/*109*/
+ MTK_PULL_PU_PD_TYPE,/*110*/ MTK_PULL_PU_PD_TYPE,/*111*/
+ MTK_PULL_PU_PD_TYPE,/*112*/ MTK_PULL_PU_PD_TYPE,/*113*/
+ MTK_PULL_PU_PD_TYPE,/*114*/ MTK_PULL_PU_PD_TYPE,/*115*/
+ MTK_PULL_PU_PD_TYPE,/*116*/ MTK_PULL_PU_PD_TYPE,/*117*/
+ MTK_PULL_PU_PD_TYPE,/*118*/ MTK_PULL_PU_PD_TYPE,/*119*/
+ MTK_PULL_PU_PD_TYPE,/*120*/ MTK_PULL_PU_PD_TYPE,/*121*/
+ MTK_PULL_PU_PD_TYPE,/*122*/ MTK_PULL_PU_PD_TYPE,/*123*/
+ MTK_PULL_PU_PD_TYPE,/*124*/ MTK_PULL_PU_PD_TYPE,/*125*/
+ MTK_PULL_PU_PD_TYPE,/*126*/ MTK_PULL_PU_PD_RSEL_TYPE,/*127*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*128*/ MTK_PULL_PU_PD_RSEL_TYPE,/*129*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*130*/ MTK_PULL_PU_PD_RSEL_TYPE,/*131*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*132*/ MTK_PULL_PU_PD_RSEL_TYPE,/*133*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*134*/ MTK_PULL_PU_PD_RSEL_TYPE,/*135*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*136*/ MTK_PULL_PU_PD_RSEL_TYPE,/*137*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*138*/ MTK_PULL_PU_PD_RSEL_TYPE,/*139*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*140*/ MTK_PULL_PU_PD_RSEL_TYPE,/*141*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*142*/ MTK_PULL_PU_PD_RSEL_TYPE,/*143*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*144*/ MTK_PULL_PU_PD_RSEL_TYPE,/*145*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*146*/ MTK_PULL_PU_PD_TYPE,/*147*/
+ MTK_PULL_PU_PD_TYPE,/*148*/ MTK_PULL_PU_PD_TYPE,/*149*/
+ MTK_PULL_PU_PD_TYPE,/*150*/ MTK_PULL_PU_PD_TYPE,/*151*/
+ MTK_PULL_PU_PD_TYPE,/*152*/ MTK_PULL_PU_PD_TYPE,/*153*/
+ MTK_PULL_PU_PD_TYPE,/*154*/ MTK_PULL_PU_PD_TYPE,/*155*/
+ MTK_PULL_PU_PD_TYPE,/*156*/ MTK_PULL_PU_PD_TYPE,/*157*/
+ MTK_PULL_PU_PD_TYPE,/*158*/ MTK_PULL_PU_PD_TYPE,/*159*/
+ MTK_PULL_PU_PD_TYPE,/*160*/ MTK_PULL_PU_PD_TYPE,/*161*/
+ MTK_PULL_PU_PD_TYPE,/*162*/ MTK_PULL_PU_PD_TYPE,/*163*/
+ MTK_PULL_PU_PD_TYPE,/*164*/ MTK_PULL_PU_PD_TYPE,/*165*/
+ MTK_PULL_PU_PD_TYPE,/*166*/ MTK_PULL_PU_PD_TYPE,/*167*/
+ MTK_PULL_PU_PD_TYPE,/*168*/ MTK_PULL_PU_PD_TYPE,/*169*/
+ MTK_PULL_PU_PD_TYPE,/*170*/ MTK_PULL_PU_PD_TYPE,/*171*/
+ MTK_PULL_PU_PD_TYPE,/*172*/ MTK_PULL_PU_PD_TYPE,/*173*/
+ MTK_PULL_PU_PD_TYPE,/*174*/ MTK_PULL_PU_PD_TYPE,/*175*/
+ MTK_PULL_PU_PD_TYPE,/*176*/ MTK_PULL_PU_PD_TYPE,/*177*/
+ MTK_PULL_PU_PD_TYPE,/*178*/ MTK_PULL_PU_PD_TYPE,/*179*/
+ MTK_PULL_PU_PD_TYPE,/*180*/ MTK_PULL_PU_PD_TYPE,/*181*/
+ MTK_PULL_PU_PD_TYPE,/*182*/ MTK_PULL_PU_PD_TYPE,/*183*/
+ MTK_PULL_PU_PD_TYPE,/*184*/
+};
+
+static const struct mtk_pin_reg_calc mt8186_reg_cals[PINCTRL_PIN_REG_MAX] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8186_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8186_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8186_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8186_pin_do_range),
+ [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8186_pin_dir_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8186_pin_smt_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8186_pin_ies_range),
+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8186_pin_pu_range),
+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8186_pin_pd_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8186_pin_drv_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8186_pin_pupd_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8186_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8186_pin_r1_range),
+ [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8186_pin_drv_adv_range),
+ [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8186_pin_rsel_range),
+
+};
+
+static const char * const mt8186_pinctrl_register_base_names[] = {
+ "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", "iocfg_bl",
+ "iocfg_rb", "iocfg_rt",
+};
+
+static const struct mtk_eint_hw mt8186_eint_hw = {
+ .port_mask = 0xf,
+ .ports = 7,
+ .ap_num = 217,
+ .db_cnt = 32,
+};
+
+static const struct mtk_pin_soc mt8186_data = {
+ .reg_cal = mt8186_reg_cals,
+ .pins = mtk_pins_mt8186,
+ .npins = ARRAY_SIZE(mtk_pins_mt8186),
+ .ngrps = ARRAY_SIZE(mtk_pins_mt8186),
+ .nfuncs = 8,
+ .gpio_m = 0,
+ .eint_hw = &mt8186_eint_hw,
+ .base_names = mt8186_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt8186_pinctrl_register_base_names),
+ .pull_type = mt8186_pull_type,
+ .pin_rsel = mt8186_pin_rsel_val_range,
+ .npin_rsel = ARRAY_SIZE(mt8186_pin_rsel_val_range),
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_drive_get = mtk_pinconf_adv_drive_get_raw,
+ .adv_drive_set = mtk_pinconf_adv_drive_set_raw,
+};
+
+static const struct of_device_id mt8186_pinctrl_of_match[] = {
+ { .compatible = "mediatek,mt8186-pinctrl", },
+ { }
+};
+static int mt8186_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_paris_pinctrl_probe(pdev, &mt8186_data);
+}
+
+static struct platform_driver mt8186_pinctrl_driver = {
+ .driver = {
+ .name = "mt8186-pinctrl",
+ .of_match_table = mt8186_pinctrl_of_match,
+ .pm = &mtk_paris_pinctrl_pm_ops,
+ },
+ .probe = mt8186_pinctrl_probe,
+};
+
+static int __init mt8186_pinctrl_init(void)
+{
+ return platform_driver_register(&mt8186_pinctrl_driver);
+}
+
+arch_initcall(mt8186_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
new file mode 100644
index 000000000000..464651f7b44b
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
@@ -0,0 +1,2186 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ *
+ * Author: Guodong Liu <guodong.liu@mediatek.com>
+ *
+ */
+
+#ifndef __PINCTRL_MTK_MT8186_H
+#define __PINCTRL_MTK_MT8186_H
+
+#include "pinctrl-paris.h"
+
+static const struct mtk_pin_desc mtk_pins_mt8186[] = {
+ MTK_PIN(
+ 0, "GPIO0",
+ MTK_EINT_FUNCTION(0, 0),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "I2S0_MCK"),
+ MTK_FUNCTION(2, "SPI0_CLK_B"),
+ MTK_FUNCTION(3, "I2S2_MCK"),
+ MTK_FUNCTION(4, "CMFLASH0"),
+ MTK_FUNCTION(5, "SCP_SPI0_CK"),
+ MTK_FUNCTION(6, "TP_GPIO0_AO"),
+ MTK_FUNCTION(7, "dbg_mon_a0")
+ ),
+
+ MTK_PIN(
+ 1, "GPIO1",
+ MTK_EINT_FUNCTION(0, 1),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(2, "SPI0_CSB_B"),
+ MTK_FUNCTION(3, "I2S2_BCK"),
+ MTK_FUNCTION(4, "CMFLASH1"),
+ MTK_FUNCTION(5, "SCP_SPI0_CS"),
+ MTK_FUNCTION(6, "TP_GPIO1_AO")
+ ),
+
+ MTK_PIN(
+ 2, "GPIO2",
+ MTK_EINT_FUNCTION(0, 2),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(2, "SPI0_MO_B"),
+ MTK_FUNCTION(3, "I2S2_LRCK"),
+ MTK_FUNCTION(4, "CMFLASH2"),
+ MTK_FUNCTION(5, "SCP_SPI0_MO"),
+ MTK_FUNCTION(6, "TP_GPIO2_AO")
+ ),
+
+ MTK_PIN(
+ 3, "GPIO3",
+ MTK_EINT_FUNCTION(0, 3),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "I2S0_DI"),
+ MTK_FUNCTION(2, "SPI0_MI_B"),
+ MTK_FUNCTION(3, "I2S2_DI"),
+ MTK_FUNCTION(4, "SRCLKENAI1"),
+ MTK_FUNCTION(5, "SCP_SPI0_MI"),
+ MTK_FUNCTION(6, "TP_GPIO3_AO")
+ ),
+
+ MTK_PIN(
+ 4, "GPIO4",
+ MTK_EINT_FUNCTION(0, 4),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "I2S3_DO"),
+ MTK_FUNCTION(3, "I2S1_DO"),
+ MTK_FUNCTION(6, "TP_GPIO4_AO")
+ ),
+
+ MTK_PIN(
+ 5, "GPIO5",
+ MTK_EINT_FUNCTION(0, 5),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(6, "TP_GPIO5_AO")
+ ),
+
+ MTK_PIN(
+ 6, "GPIO6",
+ MTK_EINT_FUNCTION(0, 6),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "I2S3_MCK"),
+ MTK_FUNCTION(2, "SPI1_CLK_B"),
+ MTK_FUNCTION(3, "I2S1_MCK"),
+ MTK_FUNCTION(4, "DPI_DATA22"),
+ MTK_FUNCTION(6, "TP_GPIO6_AO")
+ ),
+
+ MTK_PIN(
+ 7, "GPIO7",
+ MTK_EINT_FUNCTION(0, 7),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "I2S3_BCK"),
+ MTK_FUNCTION(2, "SPI1_CSB_B"),
+ MTK_FUNCTION(3, "I2S1_BCK"),
+ MTK_FUNCTION(4, "DPI_DATA23"),
+ MTK_FUNCTION(6, "TP_GPIO7_AO")
+ ),
+
+ MTK_PIN(
+ 8, "GPIO8",
+ MTK_EINT_FUNCTION(0, 8),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "I2S3_LRCK"),
+ MTK_FUNCTION(2, "SPI1_MO_B"),
+ MTK_FUNCTION(3, "I2S1_LRCK"),
+ MTK_FUNCTION(4, "CONN_UART0_RXD"),
+ MTK_FUNCTION(5, "SSPM_URXD_AO"),
+ MTK_FUNCTION(6, "ADSP_UART_RX"),
+ MTK_FUNCTION(7, "CONN_MCU_DBGACK_N")
+ ),
+
+ MTK_PIN(
+ 9, "GPIO9",
+ MTK_EINT_FUNCTION(0, 9),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "I2S3_DO"),
+ MTK_FUNCTION(2, "SPI1_MI_B"),
+ MTK_FUNCTION(3, "I2S1_DO"),
+ MTK_FUNCTION(4, "CONN_UART0_TXD"),
+ MTK_FUNCTION(5, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(6, "ADSP_UART_TX"),
+ MTK_FUNCTION(7, "CONN_MCU_DBGI_N")
+ ),
+
+ MTK_PIN(
+ 10, "GPIO10",
+ MTK_EINT_FUNCTION(0, 10),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "I2S0_MCK"),
+ MTK_FUNCTION(2, "SPI4_CLK_A"),
+ MTK_FUNCTION(3, "I2S2_MCK"),
+ MTK_FUNCTION(4, "SPM_JTAG_TDI"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDI"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TDI"),
+ MTK_FUNCTION(7, "CONN_MCU_TDI")
+ ),
+
+ MTK_PIN(
+ 11, "GPIO11",
+ MTK_EINT_FUNCTION(0, 11),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(2, "SPI4_CSB_A"),
+ MTK_FUNCTION(3, "I2S2_BCK"),
+ MTK_FUNCTION(4, "SPM_JTAG_TRSTN"),
+ MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TRSTN"),
+ MTK_FUNCTION(7, "CONN_MCU_TRST_B")
+ ),
+
+ MTK_PIN(
+ 12, "GPIO12",
+ MTK_EINT_FUNCTION(0, 12),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(2, "SPI4_MO_A"),
+ MTK_FUNCTION(3, "I2S2_LRCK"),
+ MTK_FUNCTION(4, "SPM_JTAG_TCK"),
+ MTK_FUNCTION(5, "SCP_JTAG_TCK"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TCK"),
+ MTK_FUNCTION(7, "CONN_MCU_TCK")
+ ),
+
+ MTK_PIN(
+ 13, "GPIO13",
+ MTK_EINT_FUNCTION(0, 13),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "I2S0_DI"),
+ MTK_FUNCTION(2, "SPI4_MI_A"),
+ MTK_FUNCTION(3, "I2S2_DI"),
+ MTK_FUNCTION(4, "SPM_JTAG_TDO"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDO"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TDO"),
+ MTK_FUNCTION(7, "CONN_MCU_TDO")
+ ),
+
+ MTK_PIN(
+ 14, "GPIO14",
+ MTK_EINT_FUNCTION(0, 14),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "SPM_JTAG_TMS"),
+ MTK_FUNCTION(5, "SCP_JTAG_TMS"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TMS"),
+ MTK_FUNCTION(7, "CONN_MCU_TMS")
+ ),
+
+ MTK_PIN(
+ 15, "GPIO15",
+ MTK_EINT_FUNCTION(0, 15),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(2, "SRCLKENAI1"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "PWM0")
+ ),
+
+ MTK_PIN(
+ 16, "GPIO16",
+ MTK_EINT_FUNCTION(0, 16),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "CONN_WIFI_TXD"),
+ MTK_FUNCTION(2, "SRCLKENAI0"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "PWM1")
+ ),
+
+ MTK_PIN(
+ 17, "GPIO17",
+ MTK_EINT_FUNCTION(0, 17),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(7, "dbg_mon_a32")
+ ),
+
+ MTK_PIN(
+ 18, "GPIO18",
+ MTK_EINT_FUNCTION(0, 18),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(2, "CMVREF0"),
+ MTK_FUNCTION(6, "SPI2_CLK_B"),
+ MTK_FUNCTION(7, "dbg_mon_a26")
+ ),
+
+ MTK_PIN(
+ 19, "GPIO19",
+ MTK_EINT_FUNCTION(0, 19),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(2, "CMVREF1"),
+ MTK_FUNCTION(5, "ANT_SEL3"),
+ MTK_FUNCTION(6, "SPI2_CSB_B"),
+ MTK_FUNCTION(7, "dbg_mon_a2")
+ ),
+
+ MTK_PIN(
+ 20, "GPIO20",
+ MTK_EINT_FUNCTION(0, 20),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(2, "CMVREF2"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "SPI2_MO_B"),
+ MTK_FUNCTION(7, "dbg_mon_a3")
+ ),
+
+ MTK_PIN(
+ 21, "GPIO21",
+ MTK_EINT_FUNCTION(0, 21),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "I2S0_MCK"),
+ MTK_FUNCTION(2, "I2S1_MCK"),
+ MTK_FUNCTION(3, "I2S3_MCK"),
+ MTK_FUNCTION(5, "ANT_SEL5"),
+ MTK_FUNCTION(6, "SPI2_MI_B"),
+ MTK_FUNCTION(7, "dbg_mon_a4")
+ ),
+
+ MTK_PIN(
+ 22, "GPIO22",
+ MTK_EINT_FUNCTION(0, 22),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(2, "I2S1_BCK"),
+ MTK_FUNCTION(3, "I2S3_BCK"),
+ MTK_FUNCTION(4, "TDM_RX_LRCK"),
+ MTK_FUNCTION(5, "ANT_SEL6"),
+ MTK_FUNCTION(7, "dbg_mon_a5")
+ ),
+
+ MTK_PIN(
+ 23, "GPIO23",
+ MTK_EINT_FUNCTION(0, 23),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(2, "I2S1_LRCK"),
+ MTK_FUNCTION(3, "I2S3_LRCK"),
+ MTK_FUNCTION(4, "TDM_RX_BCK"),
+ MTK_FUNCTION(5, "ANT_SEL7"),
+ MTK_FUNCTION(7, "dbg_mon_a6")
+ ),
+
+ MTK_PIN(
+ 24, "GPIO24",
+ MTK_EINT_FUNCTION(0, 24),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "I2S0_DI"),
+ MTK_FUNCTION(2, "I2S1_DO"),
+ MTK_FUNCTION(3, "I2S3_DO"),
+ MTK_FUNCTION(4, "TDM_RX_MCK"),
+ MTK_FUNCTION(7, "dbg_mon_a7")
+ ),
+
+ MTK_PIN(
+ 25, "GPIO25",
+ MTK_EINT_FUNCTION(0, 25),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "I2S2_MCK"),
+ MTK_FUNCTION(2, "PCM_CLK"),
+ MTK_FUNCTION(3, "SPI4_CLK_B"),
+ MTK_FUNCTION(4, "TDM_RX_DATA0"),
+ MTK_FUNCTION(7, "dbg_mon_a8")
+ ),
+
+ MTK_PIN(
+ 26, "GPIO26",
+ MTK_EINT_FUNCTION(0, 26),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "I2S2_BCK"),
+ MTK_FUNCTION(2, "PCM_SYNC"),
+ MTK_FUNCTION(3, "SPI4_CSB_B"),
+ MTK_FUNCTION(4, "TDM_RX_DATA1"),
+ MTK_FUNCTION(7, "dbg_mon_a9")
+ ),
+
+ MTK_PIN(
+ 27, "GPIO27",
+ MTK_EINT_FUNCTION(0, 27),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "I2S2_LRCK"),
+ MTK_FUNCTION(2, "PCM_DI"),
+ MTK_FUNCTION(3, "SPI4_MO_B"),
+ MTK_FUNCTION(4, "TDM_RX_DATA2"),
+ MTK_FUNCTION(7, "dbg_mon_a10")
+ ),
+
+ MTK_PIN(
+ 28, "GPIO28",
+ MTK_EINT_FUNCTION(0, 28),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "I2S2_DI"),
+ MTK_FUNCTION(2, "PCM_DO"),
+ MTK_FUNCTION(3, "SPI4_MI_B"),
+ MTK_FUNCTION(4, "TDM_RX_DATA3")
+ ),
+
+ MTK_PIN(
+ 29, "GPIO29",
+ MTK_EINT_FUNCTION(0, 29),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "ANT_SEL0"),
+ MTK_FUNCTION(2, "GPS_L1_ELNA_EN")
+ ),
+
+ MTK_PIN(
+ 30, "GPIO30",
+ MTK_EINT_FUNCTION(0, 30),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "ANT_SEL1")
+ ),
+
+ MTK_PIN(
+ 31, "GPIO31",
+ MTK_EINT_FUNCTION(0, 31),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "ANT_SEL2"),
+ MTK_FUNCTION(2, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(3, "SRCLKENAI1")
+ ),
+
+ MTK_PIN(
+ 32, "GPIO32",
+ MTK_EINT_FUNCTION(0, 32),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0"),
+ MTK_FUNCTION(3, "ADSP_UART_RX"),
+ MTK_FUNCTION(4, "TP_URXD1_AO")
+ ),
+
+ MTK_PIN(
+ 33, "GPIO33",
+ MTK_EINT_FUNCTION(0, 33),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0"),
+ MTK_FUNCTION(3, "ADSP_UART_TX"),
+ MTK_FUNCTION(4, "TP_UTXD1_AO")
+ ),
+
+ MTK_PIN(
+ 34, "GPIO34",
+ MTK_EINT_FUNCTION(0, 34),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "TP_URXD2_AO"),
+ MTK_FUNCTION(3, "SSPM_URXD_AO"),
+ MTK_FUNCTION(4, "ADSP_UART_RX"),
+ MTK_FUNCTION(5, "CONN_UART0_RXD")
+ ),
+
+ MTK_PIN(
+ 35, "GPIO35",
+ MTK_EINT_FUNCTION(0, 35),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "TP_UTXD2_AO"),
+ MTK_FUNCTION(3, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(4, "ADSP_UART_TX"),
+ MTK_FUNCTION(5, "CONN_UART0_TXD"),
+ MTK_FUNCTION(6, "CONN_WIFI_TXD")
+ ),
+
+ MTK_PIN(
+ 36, "GPIO36",
+ MTK_EINT_FUNCTION(0, 36),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "SPI0_CLK_A"),
+ MTK_FUNCTION(2, "CLKM0"),
+ MTK_FUNCTION(4, "SCP_SPI0_CK"),
+ MTK_FUNCTION(5, "SPINOR_CK"),
+ MTK_FUNCTION(7, "dbg_mon_a11")
+ ),
+
+ MTK_PIN(
+ 37, "GPIO37",
+ MTK_EINT_FUNCTION(0, 37),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "SPI0_CSB_A"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(4, "SCP_SPI0_CS"),
+ MTK_FUNCTION(5, "SPINOR_CS"),
+ MTK_FUNCTION(7, "dbg_mon_a12")
+ ),
+
+ MTK_PIN(
+ 38, "GPIO38",
+ MTK_EINT_FUNCTION(0, 38),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "SPI0_MO_A"),
+ MTK_FUNCTION(2, "CLKM2"),
+ MTK_FUNCTION(3, "PWM1"),
+ MTK_FUNCTION(4, "SCP_SPI0_MO"),
+ MTK_FUNCTION(5, "SPINOR_IO0"),
+ MTK_FUNCTION(7, "dbg_mon_a13")
+ ),
+
+ MTK_PIN(
+ 39, "GPIO39",
+ MTK_EINT_FUNCTION(0, 39),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "SPI0_MI_A"),
+ MTK_FUNCTION(2, "CLKM3"),
+ MTK_FUNCTION(3, "PWM2"),
+ MTK_FUNCTION(4, "SCP_SPI0_MI"),
+ MTK_FUNCTION(5, "SPINOR_IO1"),
+ MTK_FUNCTION(7, "dbg_mon_a14")
+ ),
+
+ MTK_PIN(
+ 40, "GPIO40",
+ MTK_EINT_FUNCTION(0, 40),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "SPI1_CLK_A"),
+ MTK_FUNCTION(2, "SCP_SPI1_CK"),
+ MTK_FUNCTION(4, "UCTS0"),
+ MTK_FUNCTION(5, "SPINOR_IO2"),
+ MTK_FUNCTION(6, "TP_UCTS1_AO"),
+ MTK_FUNCTION(7, "dbg_mon_a15")
+ ),
+
+ MTK_PIN(
+ 41, "GPIO41",
+ MTK_EINT_FUNCTION(0, 41),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "SPI1_CSB_A"),
+ MTK_FUNCTION(2, "SCP_SPI1_CS"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(4, "URTS0"),
+ MTK_FUNCTION(5, "SPINOR_IO3"),
+ MTK_FUNCTION(6, "TP_URTS1_AO"),
+ MTK_FUNCTION(7, "dbg_mon_a16")
+ ),
+
+ MTK_PIN(
+ 42, "GPIO42",
+ MTK_EINT_FUNCTION(0, 42),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "SPI1_MO_A"),
+ MTK_FUNCTION(2, "SCP_SPI1_MO"),
+ MTK_FUNCTION(3, "PWM1"),
+ MTK_FUNCTION(4, "UCTS1"),
+ MTK_FUNCTION(6, "TP_UCTS2_AO"),
+ MTK_FUNCTION(7, "dbg_mon_a17")
+ ),
+
+ MTK_PIN(
+ 43, "GPIO43",
+ MTK_EINT_FUNCTION(0, 43),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "SPI1_MI_A"),
+ MTK_FUNCTION(2, "SCP_SPI1_MI"),
+ MTK_FUNCTION(3, "PWM2"),
+ MTK_FUNCTION(4, "URTS1"),
+ MTK_FUNCTION(6, "TP_URTS2_AO"),
+ MTK_FUNCTION(7, "dbg_mon_a18")
+ ),
+
+ MTK_PIN(
+ 44, "GPIO44",
+ MTK_EINT_FUNCTION(0, 44),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "SPI2_CLK_A"),
+ MTK_FUNCTION(2, "SCP_SPI0_CK"),
+ MTK_FUNCTION(7, "dbg_mon_a19")
+ ),
+
+ MTK_PIN(
+ 45, "GPIO45",
+ MTK_EINT_FUNCTION(0, 45),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "SPI2_CSB_A"),
+ MTK_FUNCTION(2, "SCP_SPI0_CS"),
+ MTK_FUNCTION(7, "dbg_mon_a20")
+ ),
+
+ MTK_PIN(
+ 46, "GPIO46",
+ MTK_EINT_FUNCTION(0, 46),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "SPI2_MO_A"),
+ MTK_FUNCTION(2, "SCP_SPI0_MO"),
+ MTK_FUNCTION(7, "dbg_mon_a21")
+ ),
+
+ MTK_PIN(
+ 47, "GPIO47",
+ MTK_EINT_FUNCTION(0, 47),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "SPI2_MI_A"),
+ MTK_FUNCTION(2, "SCP_SPI0_MI"),
+ MTK_FUNCTION(7, "dbg_mon_a22")
+ ),
+
+ MTK_PIN(
+ 48, "GPIO48",
+ MTK_EINT_FUNCTION(0, 48),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "SPI3_CLK"),
+ MTK_FUNCTION(2, "TP_URXD1_AO"),
+ MTK_FUNCTION(3, "TP_URXD2_AO"),
+ MTK_FUNCTION(4, "URXD1"),
+ MTK_FUNCTION(5, "I2S2_MCK"),
+ MTK_FUNCTION(6, "SCP_SPI0_CK")
+ ),
+
+ MTK_PIN(
+ 49, "GPIO49",
+ MTK_EINT_FUNCTION(0, 49),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "SPI3_CSB"),
+ MTK_FUNCTION(2, "TP_UTXD1_AO"),
+ MTK_FUNCTION(3, "TP_UTXD2_AO"),
+ MTK_FUNCTION(4, "UTXD1"),
+ MTK_FUNCTION(5, "I2S2_BCK"),
+ MTK_FUNCTION(6, "SCP_SPI0_CS")
+ ),
+
+ MTK_PIN(
+ 50, "GPIO50",
+ MTK_EINT_FUNCTION(0, 50),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "SPI3_MO"),
+ MTK_FUNCTION(5, "I2S2_LRCK"),
+ MTK_FUNCTION(6, "SCP_SPI0_MO")
+ ),
+
+ MTK_PIN(
+ 51, "GPIO51",
+ MTK_EINT_FUNCTION(0, 51),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "SPI3_MI"),
+ MTK_FUNCTION(5, "I2S2_DI"),
+ MTK_FUNCTION(6, "SCP_SPI0_MI")
+ ),
+
+ MTK_PIN(
+ 52, "GPIO52",
+ MTK_EINT_FUNCTION(0, 52),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "SPI5_CLK"),
+ MTK_FUNCTION(2, "I2S2_MCK"),
+ MTK_FUNCTION(3, "I2S1_MCK"),
+ MTK_FUNCTION(4, "SCP_SPI1_CK"),
+ MTK_FUNCTION(5, "LVTS_26M"),
+ MTK_FUNCTION(6, "DFD_TCK_XI"),
+ MTK_FUNCTION(7, "dbg_mon_b30")
+ ),
+
+ MTK_PIN(
+ 53, "GPIO53",
+ MTK_EINT_FUNCTION(0, 53),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "SPI5_CSB"),
+ MTK_FUNCTION(2, "I2S2_BCK"),
+ MTK_FUNCTION(3, "I2S1_BCK"),
+ MTK_FUNCTION(4, "SCP_SPI1_CS"),
+ MTK_FUNCTION(5, "LVTS_FOUT"),
+ MTK_FUNCTION(6, "DFD_TDI"),
+ MTK_FUNCTION(7, "dbg_mon_b31")
+ ),
+
+ MTK_PIN(
+ 54, "GPIO54",
+ MTK_EINT_FUNCTION(0, 54),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "SPI5_MO"),
+ MTK_FUNCTION(2, "I2S2_LRCK"),
+ MTK_FUNCTION(3, "I2S1_LRCK"),
+ MTK_FUNCTION(4, "SCP_SPI1_MO"),
+ MTK_FUNCTION(5, "LVTS_SCK"),
+ MTK_FUNCTION(6, "DFD_TDO"),
+ MTK_FUNCTION(7, "dbg_mon_a1")
+ ),
+
+ MTK_PIN(
+ 55, "GPIO55",
+ MTK_EINT_FUNCTION(0, 55),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "SPI5_MI"),
+ MTK_FUNCTION(2, "I2S2_DI"),
+ MTK_FUNCTION(3, "I2S1_DO"),
+ MTK_FUNCTION(4, "SCP_SPI1_MI"),
+ MTK_FUNCTION(5, "LVTS_SDO"),
+ MTK_FUNCTION(6, "DFD_TMS"),
+ MTK_FUNCTION(7, "dbg_mon_b32")
+ ),
+
+ MTK_PIN(
+ 56, "GPIO56",
+ MTK_EINT_FUNCTION(0, 56),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "I2S1_DO"),
+ MTK_FUNCTION(2, "I2S3_DO"),
+ MTK_FUNCTION(7, "dbg_mon_a23")
+ ),
+
+ MTK_PIN(
+ 57, "GPIO57",
+ MTK_EINT_FUNCTION(0, 57),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "I2S1_BCK"),
+ MTK_FUNCTION(2, "I2S3_BCK"),
+ MTK_FUNCTION(7, "dbg_mon_a24")
+ ),
+
+ MTK_PIN(
+ 58, "GPIO58",
+ MTK_EINT_FUNCTION(0, 58),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "I2S1_LRCK"),
+ MTK_FUNCTION(2, "I2S3_LRCK"),
+ MTK_FUNCTION(7, "dbg_mon_a25")
+ ),
+
+ MTK_PIN(
+ 59, "GPIO59",
+ MTK_EINT_FUNCTION(0, 59),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "I2S1_MCK"),
+ MTK_FUNCTION(2, "I2S3_MCK"),
+ MTK_FUNCTION(7, "dbg_mon_a27")
+ ),
+
+ MTK_PIN(
+ 60, "GPIO60",
+ MTK_EINT_FUNCTION(0, 60),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "TDM_RX_LRCK"),
+ MTK_FUNCTION(2, "ANT_SEL3"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N")
+ ),
+
+ MTK_PIN(
+ 61, "GPIO61",
+ MTK_EINT_FUNCTION(0, 61),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "TDM_RX_BCK"),
+ MTK_FUNCTION(2, "ANT_SEL4"),
+ MTK_FUNCTION(4, "SPINOR_CK"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGI_N")
+ ),
+
+ MTK_PIN(
+ 62, "GPIO62",
+ MTK_EINT_FUNCTION(0, 62),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "TDM_RX_MCK"),
+ MTK_FUNCTION(2, "ANT_SEL5"),
+ MTK_FUNCTION(4, "SPINOR_CS"),
+ MTK_FUNCTION(5, "CONN_MCU_TDI")
+ ),
+
+ MTK_PIN(
+ 63, "GPIO63",
+ MTK_EINT_FUNCTION(0, 63),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "TDM_RX_DATA0"),
+ MTK_FUNCTION(2, "ANT_SEL6"),
+ MTK_FUNCTION(4, "SPINOR_IO0"),
+ MTK_FUNCTION(5, "CONN_MCU_TRST_B")
+ ),
+
+ MTK_PIN(
+ 64, "GPIO64",
+ MTK_EINT_FUNCTION(0, 64),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "TDM_RX_DATA1"),
+ MTK_FUNCTION(2, "ANT_SEL7"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(4, "SPINOR_IO1"),
+ MTK_FUNCTION(5, "CONN_MCU_TCK")
+ ),
+
+ MTK_PIN(
+ 65, "GPIO65",
+ MTK_EINT_FUNCTION(0, 65),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "TDM_RX_DATA2"),
+ MTK_FUNCTION(2, "UCTS0"),
+ MTK_FUNCTION(3, "PWM1"),
+ MTK_FUNCTION(4, "SPINOR_IO2"),
+ MTK_FUNCTION(5, "CONN_MCU_TDO"),
+ MTK_FUNCTION(6, "TP_UCTS1_AO"),
+ MTK_FUNCTION(7, "TP_UCTS2_AO")
+ ),
+
+ MTK_PIN(
+ 66, "GPIO66",
+ MTK_EINT_FUNCTION(0, 66),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "TDM_RX_DATA3"),
+ MTK_FUNCTION(2, "URTS0"),
+ MTK_FUNCTION(3, "PWM2"),
+ MTK_FUNCTION(4, "SPINOR_IO3"),
+ MTK_FUNCTION(5, "CONN_MCU_TMS"),
+ MTK_FUNCTION(6, "TP_URTS1_AO"),
+ MTK_FUNCTION(7, "TP_URTS2_AO")
+ ),
+
+ MTK_PIN(
+ 67, "GPIO67",
+ MTK_EINT_FUNCTION(0, 67),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "MSDC0_DSL")
+ ),
+
+ MTK_PIN(
+ 68, "GPIO68",
+ MTK_EINT_FUNCTION(0, 68),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "MSDC0_CLK")
+ ),
+
+ MTK_PIN(
+ 69, "GPIO69",
+ MTK_EINT_FUNCTION(0, 69),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "MSDC0_CMD")
+ ),
+
+ MTK_PIN(
+ 70, "GPIO70",
+ MTK_EINT_FUNCTION(0, 70),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "MSDC0_RSTB")
+ ),
+
+ MTK_PIN(
+ 71, "GPIO71",
+ MTK_EINT_FUNCTION(0, 71),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "MSDC0_DAT0")
+ ),
+
+ MTK_PIN(
+ 72, "GPIO72",
+ MTK_EINT_FUNCTION(0, 72),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "MSDC0_DAT1")
+ ),
+
+ MTK_PIN(
+ 73, "GPIO73",
+ MTK_EINT_FUNCTION(0, 73),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "MSDC0_DAT2")
+ ),
+
+ MTK_PIN(
+ 74, "GPIO74",
+ MTK_EINT_FUNCTION(0, 74),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "MSDC0_DAT3")
+ ),
+
+ MTK_PIN(
+ 75, "GPIO75",
+ MTK_EINT_FUNCTION(0, 75),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "MSDC0_DAT4")
+ ),
+
+ MTK_PIN(
+ 76, "GPIO76",
+ MTK_EINT_FUNCTION(0, 76),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "MSDC0_DAT5")
+ ),
+
+ MTK_PIN(
+ 77, "GPIO77",
+ MTK_EINT_FUNCTION(0, 77),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "MSDC0_DAT6")
+ ),
+
+ MTK_PIN(
+ 78, "GPIO78",
+ MTK_EINT_FUNCTION(0, 78),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "MSDC0_DAT7")
+ ),
+
+ MTK_PIN(
+ 79, "GPIO79",
+ MTK_EINT_FUNCTION(0, 79),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "KPCOL0")
+ ),
+
+ MTK_PIN(
+ 80, "GPIO80",
+ MTK_EINT_FUNCTION(0, 80),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "KPCOL1"),
+ MTK_FUNCTION(2, "GPS_L1_ELNA_EN"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(4, "CLKM0")
+ ),
+
+ MTK_PIN(
+ 81, "GPIO81",
+ MTK_EINT_FUNCTION(0, 81),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "KPROW0"),
+ MTK_FUNCTION(3, "PWM1"),
+ MTK_FUNCTION(4, "CLKM1")
+ ),
+
+ MTK_PIN(
+ 82, "GPIO82",
+ MTK_EINT_FUNCTION(0, 82),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "KPROW1"),
+ MTK_FUNCTION(3, "PWM2"),
+ MTK_FUNCTION(4, "CLKM2")
+ ),
+
+ MTK_PIN(
+ 83, "GPIO83",
+ MTK_EINT_FUNCTION(0, 83),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "AP_GOOD"),
+ MTK_FUNCTION(2, "GPS_PPS"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(7, "dbg_mon_a28")
+ ),
+
+ MTK_PIN(
+ 84, "GPIO84",
+ MTK_EINT_FUNCTION(0, 84),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(2, "ADSP_JTAG_TCK"),
+ MTK_FUNCTION(4, "UDI_TCK"),
+ MTK_FUNCTION(5, "CONN_DSP_JCK"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TCK"),
+ MTK_FUNCTION(7, "DFD_TCK_XI")
+ ),
+
+ MTK_PIN(
+ 85, "GPIO85",
+ MTK_EINT_FUNCTION(0, 85),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(2, "ADSP_JTAG_TMS"),
+ MTK_FUNCTION(3, "CONN_MCU_AICE_TMSC"),
+ MTK_FUNCTION(4, "UDI_TMS"),
+ MTK_FUNCTION(5, "CONN_DSP_JMS"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TMS"),
+ MTK_FUNCTION(7, "DFD_TMS")
+ ),
+
+ MTK_PIN(
+ 86, "GPIO86",
+ MTK_EINT_FUNCTION(0, 86),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(2, "ADSP_JTAG_TDI"),
+ MTK_FUNCTION(4, "UDI_TDI"),
+ MTK_FUNCTION(5, "CONN_DSP_JDI"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TDI"),
+ MTK_FUNCTION(7, "DFD_TDI")
+ ),
+
+ MTK_PIN(
+ 87, "GPIO87",
+ MTK_EINT_FUNCTION(0, 87),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(2, "ADSP_JTAG_TDO"),
+ MTK_FUNCTION(4, "UDI_TDO"),
+ MTK_FUNCTION(5, "CONN_DSP_JDO"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TDO"),
+ MTK_FUNCTION(7, "DFD_TDO")
+ ),
+
+ MTK_PIN(
+ 88, "GPIO88",
+ MTK_EINT_FUNCTION(0, 88),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(2, "ADSP_JTAG_TRSTN"),
+ MTK_FUNCTION(3, "CONN_MCU_AICE_TCKC"),
+ MTK_FUNCTION(4, "UDI_NTRST"),
+ MTK_FUNCTION(5, "CONN_WIFI_TXD"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TRSTN")
+ ),
+
+ MTK_PIN(
+ 89, "GPIO89",
+ MTK_EINT_FUNCTION(0, 89),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(5, "CONN_DSP_JINTP")
+ ),
+
+ MTK_PIN(
+ 90, "GPIO90",
+ MTK_EINT_FUNCTION(0, 90),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "IDDIG_P0"),
+ MTK_FUNCTION(4, "PGD_HV_HSC_PWR4"),
+ MTK_FUNCTION(5, "GDU_SUM_TROOP2_2")
+ ),
+
+ MTK_PIN(
+ 91, "GPIO91",
+ MTK_EINT_FUNCTION(0, 91),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "USB_DRVVBUS_P0"),
+ MTK_FUNCTION(4, "PGD_HV_HSC_PWR5"),
+ MTK_FUNCTION(5, "GDU_TROOPS_DET0")
+ ),
+
+ MTK_PIN(
+ 92, "GPIO92",
+ MTK_EINT_FUNCTION(0, 92),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "VBUS_VALID_P0"),
+ MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY"),
+ MTK_FUNCTION(5, "GDU_TROOPS_DET1")
+ ),
+
+ MTK_PIN(
+ 93, "GPIO93",
+ MTK_EINT_FUNCTION(0, 93),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "IDDIG_P1"),
+ MTK_FUNCTION(2, "PWM0"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY_PRE"),
+ MTK_FUNCTION(5, "GDU_TROOPS_DET2")
+ ),
+
+ MTK_PIN(
+ 94, "GPIO94",
+ MTK_EINT_FUNCTION(0, 94),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "USB_DRVVBUS_P1"),
+ MTK_FUNCTION(2, "PWM1"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "PGD_DA_PWRGD_RESET")
+ ),
+
+ MTK_PIN(
+ 95, "GPIO95",
+ MTK_EINT_FUNCTION(0, 95),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "VBUS_VALID_P1"),
+ MTK_FUNCTION(2, "PWM2"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "PGD_DA_PWRGD_ENB")
+ ),
+
+ MTK_PIN(
+ 96, "GPIO96",
+ MTK_EINT_FUNCTION(0, 96),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "DSI_TE"),
+ MTK_FUNCTION(7, "dbg_mon_a29")
+ ),
+
+ MTK_PIN(
+ 97, "GPIO97",
+ MTK_EINT_FUNCTION(0, 97),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "DISP_PWM"),
+ MTK_FUNCTION(7, "dbg_mon_a30")
+ ),
+
+ MTK_PIN(
+ 98, "GPIO98",
+ MTK_EINT_FUNCTION(0, 98),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "LCM_RST")
+ ),
+
+ MTK_PIN(
+ 99, "GPIO99",
+ MTK_EINT_FUNCTION(0, 99),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "DPI_PCLK"),
+ MTK_FUNCTION(2, "GPS_L1_ELNA_EN"),
+ MTK_FUNCTION(3, "SSPM_JTAG_TCK"),
+ MTK_FUNCTION(5, "ANT_SEL0"),
+ MTK_FUNCTION(6, "TP_GPIO0_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR0")
+ ),
+
+ MTK_PIN(
+ 100, "GPIO100",
+ MTK_EINT_FUNCTION(0, 100),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "DPI_VSYNC"),
+ MTK_FUNCTION(2, "KPCOL2"),
+ MTK_FUNCTION(3, "SSPM_JTAG_TMS"),
+ MTK_FUNCTION(5, "ANT_SEL1"),
+ MTK_FUNCTION(6, "TP_GPIO1_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR1")
+ ),
+
+ MTK_PIN(
+ 101, "GPIO101",
+ MTK_EINT_FUNCTION(0, 101),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "DPI_HSYNC"),
+ MTK_FUNCTION(2, "KPROW2"),
+ MTK_FUNCTION(3, "SSPM_JTAG_TDI"),
+ MTK_FUNCTION(5, "ANT_SEL2"),
+ MTK_FUNCTION(6, "TP_GPIO2_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR2")
+ ),
+
+ MTK_PIN(
+ 102, "GPIO102",
+ MTK_EINT_FUNCTION(0, 102),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "DPI_DE"),
+ MTK_FUNCTION(3, "SSPM_JTAG_TDO"),
+ MTK_FUNCTION(5, "ANT_SEL3"),
+ MTK_FUNCTION(6, "TP_GPIO3_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR3")
+ ),
+
+ MTK_PIN(
+ 103, "GPIO103",
+ MTK_EINT_FUNCTION(0, 103),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "DPI_DATA0"),
+ MTK_FUNCTION(3, "SSPM_JTAG_TRSTN"),
+ MTK_FUNCTION(4, "CLKM0"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "TP_GPIO4_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR4")
+ ),
+
+ MTK_PIN(
+ 104, "GPIO104",
+ MTK_EINT_FUNCTION(0, 104),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "DPI_DATA1"),
+ MTK_FUNCTION(2, "GPS_PPS"),
+ MTK_FUNCTION(3, "UCTS2"),
+ MTK_FUNCTION(4, "CLKM1"),
+ MTK_FUNCTION(5, "ANT_SEL5"),
+ MTK_FUNCTION(6, "TP_GPIO5_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR5")
+ ),
+
+ MTK_PIN(
+ 105, "GPIO105",
+ MTK_EINT_FUNCTION(0, 105),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "DPI_DATA2"),
+ MTK_FUNCTION(2, "CONN_TCXOENA_REQ"),
+ MTK_FUNCTION(3, "URTS2"),
+ MTK_FUNCTION(4, "CLKM2"),
+ MTK_FUNCTION(5, "ANT_SEL6"),
+ MTK_FUNCTION(6, "TP_GPIO6_AO"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR0")
+ ),
+
+ MTK_PIN(
+ 106, "GPIO106",
+ MTK_EINT_FUNCTION(0, 106),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "DPI_DATA3"),
+ MTK_FUNCTION(2, "TP_UTXD1_AO"),
+ MTK_FUNCTION(3, "UTXD2"),
+ MTK_FUNCTION(4, "PWM0"),
+ MTK_FUNCTION(5, "ANT_SEL7"),
+ MTK_FUNCTION(6, "TP_GPIO7_AO"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR1")
+ ),
+
+ MTK_PIN(
+ 107, "GPIO107",
+ MTK_EINT_FUNCTION(0, 107),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "DPI_DATA4"),
+ MTK_FUNCTION(2, "TP_URXD1_AO"),
+ MTK_FUNCTION(3, "URXD2"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP0_0"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR2")
+ ),
+
+ MTK_PIN(
+ 108, "GPIO108",
+ MTK_EINT_FUNCTION(0, 108),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "DPI_DATA5"),
+ MTK_FUNCTION(2, "TP_UCTS1_AO"),
+ MTK_FUNCTION(3, "UCTS0"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP0_1"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR3")
+ ),
+
+ MTK_PIN(
+ 109, "GPIO109",
+ MTK_EINT_FUNCTION(0, 109),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "DPI_DATA6"),
+ MTK_FUNCTION(2, "TP_URTS1_AO"),
+ MTK_FUNCTION(3, "URTS0"),
+ MTK_FUNCTION(4, "I2S0_DI"),
+ MTK_FUNCTION(5, "I2S2_DI"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP0_2"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR4")
+ ),
+
+ MTK_PIN(
+ 110, "GPIO110",
+ MTK_EINT_FUNCTION(0, 110),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "DPI_DATA7"),
+ MTK_FUNCTION(2, "TP_UCTS2_AO"),
+ MTK_FUNCTION(3, "UCTS1"),
+ MTK_FUNCTION(4, "I2S3_BCK"),
+ MTK_FUNCTION(5, "I2S1_BCK"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP1_0"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR5")
+ ),
+
+ MTK_PIN(
+ 111, "GPIO111",
+ MTK_EINT_FUNCTION(0, 111),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "DPI_DATA8"),
+ MTK_FUNCTION(2, "TP_URTS2_AO"),
+ MTK_FUNCTION(3, "URTS1"),
+ MTK_FUNCTION(4, "I2S3_MCK"),
+ MTK_FUNCTION(5, "I2S1_MCK"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP1_1"),
+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR0")
+ ),
+
+ MTK_PIN(
+ 112, "GPIO112",
+ MTK_EINT_FUNCTION(0, 112),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "DPI_DATA9"),
+ MTK_FUNCTION(2, "TP_URXD2_AO"),
+ MTK_FUNCTION(3, "URXD1"),
+ MTK_FUNCTION(4, "I2S3_LRCK"),
+ MTK_FUNCTION(5, "I2S1_LRCK"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP1_2"),
+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR1")
+ ),
+
+ MTK_PIN(
+ 113, "GPIO113",
+ MTK_EINT_FUNCTION(0, 113),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "DPI_DATA10"),
+ MTK_FUNCTION(2, "TP_UTXD2_AO"),
+ MTK_FUNCTION(3, "UTXD1"),
+ MTK_FUNCTION(4, "I2S3_DO"),
+ MTK_FUNCTION(5, "I2S1_DO"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP2_0"),
+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR2")
+ ),
+
+ MTK_PIN(
+ 114, "GPIO114",
+ MTK_EINT_FUNCTION(0, 114),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "DPI_DATA11"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP2_1"),
+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR3")
+ ),
+
+ MTK_PIN(
+ 115, "GPIO115",
+ MTK_EINT_FUNCTION(0, 115),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "PCM_CLK"),
+ MTK_FUNCTION(2, "I2S0_BCK"),
+ MTK_FUNCTION(3, "I2S2_BCK")
+ ),
+
+ MTK_PIN(
+ 116, "GPIO116",
+ MTK_EINT_FUNCTION(0, 116),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "PCM_SYNC"),
+ MTK_FUNCTION(2, "I2S0_LRCK"),
+ MTK_FUNCTION(3, "I2S2_LRCK")
+ ),
+
+ MTK_PIN(
+ 117, "GPIO117",
+ MTK_EINT_FUNCTION(0, 117),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "PCM_DI"),
+ MTK_FUNCTION(2, "I2S0_DI"),
+ MTK_FUNCTION(3, "I2S2_DI")
+ ),
+
+ MTK_PIN(
+ 118, "GPIO118",
+ MTK_EINT_FUNCTION(0, 118),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "PCM_DO"),
+ MTK_FUNCTION(2, "I2S0_MCK"),
+ MTK_FUNCTION(3, "I2S2_MCK"),
+ MTK_FUNCTION(4, "I2S3_DO"),
+ MTK_FUNCTION(5, "I2S1_DO")
+ ),
+
+ MTK_PIN(
+ 119, "GPIO119",
+ MTK_EINT_FUNCTION(0, 119),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "JTMS_SEL1"),
+ MTK_FUNCTION(2, "UDI_TMS"),
+ MTK_FUNCTION(3, "DFD_TMS"),
+ MTK_FUNCTION(4, "SPM_JTAG_TMS"),
+ MTK_FUNCTION(5, "SCP_JTAG_TMS"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TMS")
+ ),
+
+ MTK_PIN(
+ 120, "GPIO120",
+ MTK_EINT_FUNCTION(0, 120),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "JTCK_SEL1"),
+ MTK_FUNCTION(2, "UDI_TCK"),
+ MTK_FUNCTION(3, "DFD_TCK_XI"),
+ MTK_FUNCTION(4, "SPM_JTAG_TCK"),
+ MTK_FUNCTION(5, "SCP_JTAG_TCK"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TCK")
+ ),
+
+ MTK_PIN(
+ 121, "GPIO121",
+ MTK_EINT_FUNCTION(0, 121),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "JTDI_SEL1"),
+ MTK_FUNCTION(2, "UDI_TDI"),
+ MTK_FUNCTION(3, "DFD_TDI"),
+ MTK_FUNCTION(4, "SPM_JTAG_TDI"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDI"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TDI")
+ ),
+
+ MTK_PIN(
+ 122, "GPIO122",
+ MTK_EINT_FUNCTION(0, 122),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "JTDO_SEL1"),
+ MTK_FUNCTION(2, "UDI_TDO"),
+ MTK_FUNCTION(3, "DFD_TDO"),
+ MTK_FUNCTION(4, "SPM_JTAG_TDO"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDO"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TDO")
+ ),
+
+ MTK_PIN(
+ 123, "GPIO123",
+ MTK_EINT_FUNCTION(0, 123),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "JTRSTN_SEL1"),
+ MTK_FUNCTION(2, "UDI_NTRST"),
+ MTK_FUNCTION(4, "SPM_JTAG_TRSTN"),
+ MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TRSTN")
+ ),
+
+ MTK_PIN(
+ 124, "GPIO124",
+ MTK_EINT_FUNCTION(0, 124),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "CMMCLK0"),
+ MTK_FUNCTION(2, "CLKM0"),
+ MTK_FUNCTION(3, "PWM0")
+ ),
+
+ MTK_PIN(
+ 125, "GPIO125",
+ MTK_EINT_FUNCTION(0, 125),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "CMMCLK1"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "PWM1"),
+ MTK_FUNCTION(7, "dbg_mon_b0")
+ ),
+
+ MTK_PIN(
+ 126, "GPIO126",
+ MTK_EINT_FUNCTION(0, 126),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "CMMCLK2"),
+ MTK_FUNCTION(2, "CLKM2"),
+ MTK_FUNCTION(3, "PWM2"),
+ MTK_FUNCTION(7, "dbg_mon_b1")
+ ),
+
+ MTK_PIN(
+ 127, "GPIO127",
+ MTK_EINT_FUNCTION(0, 127),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "SCL0"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1")
+ ),
+
+ MTK_PIN(
+ 128, "GPIO128",
+ MTK_EINT_FUNCTION(0, 128),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "SDA0"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1")
+ ),
+
+ MTK_PIN(
+ 129, "GPIO129",
+ MTK_EINT_FUNCTION(0, 129),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "SCL1"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b4")
+ ),
+
+ MTK_PIN(
+ 130, "GPIO130",
+ MTK_EINT_FUNCTION(0, 130),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "SDA1"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b5")
+ ),
+
+ MTK_PIN(
+ 131, "GPIO131",
+ MTK_EINT_FUNCTION(0, 131),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "SCL2"),
+ MTK_FUNCTION(2, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(3, "CONN_UART0_TXD"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b6")
+ ),
+
+ MTK_PIN(
+ 132, "GPIO132",
+ MTK_EINT_FUNCTION(0, 132),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "SDA2"),
+ MTK_FUNCTION(2, "SSPM_URXD_AO"),
+ MTK_FUNCTION(3, "CONN_UART0_RXD"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b7")
+ ),
+
+ MTK_PIN(
+ 133, "GPIO133",
+ MTK_EINT_FUNCTION(0, 133),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "SCL3"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b8")
+ ),
+
+ MTK_PIN(
+ 134, "GPIO134",
+ MTK_EINT_FUNCTION(0, 134),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "SDA3"),
+ MTK_FUNCTION(3, "GPS_PPS"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b9")
+ ),
+
+ MTK_PIN(
+ 135, "GPIO135",
+ MTK_EINT_FUNCTION(0, 135),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "SCL4"),
+ MTK_FUNCTION(2, "TP_UTXD1_AO"),
+ MTK_FUNCTION(3, "UTXD1"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b10")
+ ),
+
+ MTK_PIN(
+ 136, "GPIO136",
+ MTK_EINT_FUNCTION(0, 136),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "SDA4"),
+ MTK_FUNCTION(2, "TP_URXD1_AO"),
+ MTK_FUNCTION(3, "URXD1"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b11")
+ ),
+
+ MTK_PIN(
+ 137, "GPIO137",
+ MTK_EINT_FUNCTION(0, 137),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "SCL5"),
+ MTK_FUNCTION(2, "UTXD2"),
+ MTK_FUNCTION(3, "UCTS1"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1")
+ ),
+
+ MTK_PIN(
+ 138, "GPIO138",
+ MTK_EINT_FUNCTION(0, 138),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "SDA5"),
+ MTK_FUNCTION(2, "URXD2"),
+ MTK_FUNCTION(3, "URTS1"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1")
+ ),
+
+ MTK_PIN(
+ 139, "GPIO139",
+ MTK_EINT_FUNCTION(0, 139),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "SCL6"),
+ MTK_FUNCTION(2, "UTXD1"),
+ MTK_FUNCTION(3, "TP_UTXD1_AO"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b12")
+ ),
+
+ MTK_PIN(
+ 140, "GPIO140",
+ MTK_EINT_FUNCTION(0, 140),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "SDA6"),
+ MTK_FUNCTION(2, "URXD1"),
+ MTK_FUNCTION(3, "TP_URXD1_AO"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b13")
+ ),
+
+ MTK_PIN(
+ 141, "GPIO141",
+ MTK_EINT_FUNCTION(0, 141),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "SCL7"),
+ MTK_FUNCTION(2, "URTS0"),
+ MTK_FUNCTION(3, "TP_URTS1_AO"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(6, "UDI_TCK"),
+ MTK_FUNCTION(7, "dbg_mon_b14")
+ ),
+
+ MTK_PIN(
+ 142, "GPIO142",
+ MTK_EINT_FUNCTION(0, 142),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "SDA7"),
+ MTK_FUNCTION(2, "UCTS0"),
+ MTK_FUNCTION(3, "TP_UCTS1_AO"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1")
+ ),
+
+ MTK_PIN(
+ 143, "GPIO143",
+ MTK_EINT_FUNCTION(0, 143),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "SCL8"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b16")
+ ),
+
+ MTK_PIN(
+ 144, "GPIO144",
+ MTK_EINT_FUNCTION(0, 144),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "SDA8"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b17")
+ ),
+
+ MTK_PIN(
+ 145, "GPIO145",
+ MTK_EINT_FUNCTION(0, 145),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "SCL9"),
+ MTK_FUNCTION(2, "CMVREF1"),
+ MTK_FUNCTION(3, "GPS_PPS"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b18")
+ ),
+
+ MTK_PIN(
+ 146, "GPIO146",
+ MTK_EINT_FUNCTION(0, 146),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "SDA9"),
+ MTK_FUNCTION(2, "CMVREF0"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b19")
+ ),
+
+ MTK_PIN(
+ 147, "GPIO147",
+ MTK_EINT_FUNCTION(0, 147),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "CMFLASH0"),
+ MTK_FUNCTION(2, "LVTS_SDI"),
+ MTK_FUNCTION(3, "DPI_DATA12"),
+ MTK_FUNCTION(4, "TP_GPIO0_AO"),
+ MTK_FUNCTION(5, "ANT_SEL3"),
+ MTK_FUNCTION(6, "DFD_TCK_XI"),
+ MTK_FUNCTION(7, "dbg_mon_b20")
+ ),
+
+ MTK_PIN(
+ 148, "GPIO148",
+ MTK_EINT_FUNCTION(0, 148),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "CMFLASH1"),
+ MTK_FUNCTION(2, "LVTS_SCF"),
+ MTK_FUNCTION(3, "DPI_DATA13"),
+ MTK_FUNCTION(4, "TP_GPIO1_AO"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "DFD_TMS"),
+ MTK_FUNCTION(7, "dbg_mon_b21")
+ ),
+
+ MTK_PIN(
+ 149, "GPIO149",
+ MTK_EINT_FUNCTION(0, 149),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, "CMFLASH2"),
+ MTK_FUNCTION(2, "CLKM0"),
+ MTK_FUNCTION(3, "DPI_DATA14"),
+ MTK_FUNCTION(4, "TP_GPIO2_AO"),
+ MTK_FUNCTION(5, "ANT_SEL5"),
+ MTK_FUNCTION(6, "DFD_TDI"),
+ MTK_FUNCTION(7, "dbg_mon_b22")
+ ),
+
+ MTK_PIN(
+ 150, "GPIO150",
+ MTK_EINT_FUNCTION(0, 150),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "DPI_DATA15"),
+ MTK_FUNCTION(4, "TP_GPIO3_AO"),
+ MTK_FUNCTION(5, "ANT_SEL6"),
+ MTK_FUNCTION(6, "DFD_TDO"),
+ MTK_FUNCTION(7, "dbg_mon_b23")
+ ),
+
+ MTK_PIN(
+ 151, "GPIO151",
+ MTK_EINT_FUNCTION(0, 151),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, "GPS_L1_ELNA_EN"),
+ MTK_FUNCTION(2, "CLKM2"),
+ MTK_FUNCTION(3, "DPI_DATA16"),
+ MTK_FUNCTION(4, "TP_GPIO4_AO"),
+ MTK_FUNCTION(5, "ANT_SEL7"),
+ MTK_FUNCTION(6, "UDI_TMS"),
+ MTK_FUNCTION(7, "dbg_mon_b24")
+ ),
+
+ MTK_PIN(
+ 152, "GPIO152",
+ MTK_EINT_FUNCTION(0, 152),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(2, "CLKM3"),
+ MTK_FUNCTION(3, "DPI_DATA17"),
+ MTK_FUNCTION(4, "TP_GPIO5_AO")
+ ),
+
+ MTK_PIN(
+ 153, "GPIO153",
+ MTK_EINT_FUNCTION(0, 153),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, "CONN_TCXOENA_REQ"),
+ MTK_FUNCTION(3, "DPI_DATA18"),
+ MTK_FUNCTION(4, "TP_GPIO6_AO"),
+ MTK_FUNCTION(6, "UDI_TDI"),
+ MTK_FUNCTION(7, "dbg_mon_b26")
+ ),
+
+ MTK_PIN(
+ 154, "GPIO154",
+ MTK_EINT_FUNCTION(0, 154),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, "PWM0"),
+ MTK_FUNCTION(2, "CMVREF2"),
+ MTK_FUNCTION(3, "DPI_DATA19"),
+ MTK_FUNCTION(4, "TP_GPIO7_AO"),
+ MTK_FUNCTION(6, "UDI_TDO"),
+ MTK_FUNCTION(7, "dbg_mon_b27")
+ ),
+
+ MTK_PIN(
+ 155, "GPIO155",
+ MTK_EINT_FUNCTION(0, 155),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION(2, "CMVREF1"),
+ MTK_FUNCTION(3, "DPI_DATA20"),
+ MTK_FUNCTION(6, "UDI_NTRST"),
+ MTK_FUNCTION(7, "dbg_mon_b28")
+ ),
+
+ MTK_PIN(
+ 156, "GPIO156",
+ MTK_EINT_FUNCTION(0, 156),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION(2, "CMVREF0"),
+ MTK_FUNCTION(3, "DPI_DATA21")
+ ),
+
+ MTK_PIN(
+ 157, "GPIO157",
+ MTK_EINT_FUNCTION(0, 157),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
+ ),
+
+ MTK_PIN(
+ 158, "GPIO158",
+ MTK_EINT_FUNCTION(0, 158),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_CK")
+ ),
+
+ MTK_PIN(
+ 159, "GPIO159",
+ MTK_EINT_FUNCTION(0, 159),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
+ MTK_FUNCTION(2, "PWRAP_SPI0_MI")
+ ),
+
+ MTK_PIN(
+ 160, "GPIO160",
+ MTK_EINT_FUNCTION(0, 160),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
+ MTK_FUNCTION(2, "PWRAP_SPI0_MO")
+ ),
+
+ MTK_PIN(
+ 161, "GPIO161",
+ MTK_EINT_FUNCTION(0, 161),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, "SRCLKENA0")
+ ),
+
+ MTK_PIN(
+ 162, "GPIO162",
+ MTK_EINT_FUNCTION(0, 162),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, "SRCLKENA1"),
+ MTK_FUNCTION(7, "dbg_mon_a31")
+ ),
+
+ MTK_PIN(
+ 163, "GPIO163",
+ MTK_EINT_FUNCTION(0, 163),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, "SCP_VREQ_VAO"),
+ MTK_FUNCTION(2, "DVFSRC_EXT_REQ")
+ ),
+
+ MTK_PIN(
+ 164, "GPIO164",
+ MTK_EINT_FUNCTION(0, 164),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+
+ MTK_PIN(
+ 165, "GPIO165",
+ MTK_EINT_FUNCTION(0, 165),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+
+ MTK_PIN(
+ 166, "GPIO166",
+ MTK_EINT_FUNCTION(0, 166),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, "AUD_CLK_MOSI"),
+ MTK_FUNCTION(2, "AUD_CLK_MISO"),
+ MTK_FUNCTION(3, "I2S1_MCK")
+ ),
+
+ MTK_PIN(
+ 167, "GPIO167",
+ MTK_EINT_FUNCTION(0, 167),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, "AUD_SYNC_MOSI"),
+ MTK_FUNCTION(2, "AUD_SYNC_MISO"),
+ MTK_FUNCTION(3, "I2S1_BCK")
+ ),
+
+ MTK_PIN(
+ 168, "GPIO168",
+ MTK_EINT_FUNCTION(0, 168),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI0"),
+ MTK_FUNCTION(2, "AUD_DAT_MISO0"),
+ MTK_FUNCTION(3, "I2S1_LRCK")
+ ),
+
+ MTK_PIN(
+ 169, "GPIO169",
+ MTK_EINT_FUNCTION(0, 169),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI1"),
+ MTK_FUNCTION(2, "AUD_DAT_MISO1"),
+ MTK_FUNCTION(3, "I2S1_DO")
+ ),
+
+ MTK_PIN(
+ 170, "GPIO170",
+ MTK_EINT_FUNCTION(0, 170),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "AUD_CLK_MISO"),
+ MTK_FUNCTION(2, "AUD_CLK_MOSI"),
+ MTK_FUNCTION(3, "I2S2_MCK")
+ ),
+
+ MTK_PIN(
+ 171, "GPIO171",
+ MTK_EINT_FUNCTION(0, 171),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "AUD_SYNC_MISO"),
+ MTK_FUNCTION(2, "AUD_SYNC_MOSI"),
+ MTK_FUNCTION(3, "I2S2_BCK")
+ ),
+
+ MTK_PIN(
+ 172, "GPIO172",
+ MTK_EINT_FUNCTION(0, 172),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO0"),
+ MTK_FUNCTION(2, "AUD_DAT_MOSI0"),
+ MTK_FUNCTION(3, "I2S2_LRCK"),
+ MTK_FUNCTION(4, "VOW_DAT_MISO")
+ ),
+
+ MTK_PIN(
+ 173, "GPIO173",
+ MTK_EINT_FUNCTION(0, 173),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO1"),
+ MTK_FUNCTION(2, "AUD_DAT_MOSI1"),
+ MTK_FUNCTION(3, "I2S2_DI"),
+ MTK_FUNCTION(4, "VOW_CLK_MISO")
+ ),
+
+ MTK_PIN(
+ 174, "GPIO174",
+ MTK_EINT_FUNCTION(0, 174),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "CONN_TOP_CLK"),
+ MTK_FUNCTION(2, "AUXIF_CLK"),
+ MTK_FUNCTION(3, "DFD_TCK_XI"),
+ MTK_FUNCTION(7, "dbg_mon_b3")
+ ),
+
+ MTK_PIN(
+ 175, "GPIO175",
+ MTK_EINT_FUNCTION(0, 175),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "CONN_TOP_DATA"),
+ MTK_FUNCTION(2, "AUXIF_ST"),
+ MTK_FUNCTION(3, "DFD_TMS"),
+ MTK_FUNCTION(7, "dbg_mon_b15")
+ ),
+
+ MTK_PIN(
+ 176, "GPIO176",
+ MTK_EINT_FUNCTION(0, 176),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "CONN_BT_CLK"),
+ MTK_FUNCTION(3, "DFD_TDI"),
+ MTK_FUNCTION(7, "dbg_mon_b2")
+ ),
+
+ MTK_PIN(
+ 177, "GPIO177",
+ MTK_EINT_FUNCTION(0, 177),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "CONN_BT_DATA"),
+ MTK_FUNCTION(3, "DFD_TDO")
+ ),
+
+ MTK_PIN(
+ 178, "GPIO178",
+ MTK_EINT_FUNCTION(0, 178),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "CONN_HRST_B"),
+ MTK_FUNCTION(3, "UDI_TMS"),
+ MTK_FUNCTION(7, "dbg_mon_b25")
+ ),
+
+ MTK_PIN(
+ 179, "GPIO179",
+ MTK_EINT_FUNCTION(0, 179),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "CONN_WB_PTA"),
+ MTK_FUNCTION(3, "UDI_TCK"),
+ MTK_FUNCTION(7, "dbg_mon_b29")
+ ),
+
+ MTK_PIN(
+ 180, "GPIO180",
+ MTK_EINT_FUNCTION(0, 180),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "CONN_WF_CTRL0"),
+ MTK_FUNCTION(3, "UDI_TDI")
+ ),
+
+ MTK_PIN(
+ 181, "GPIO181",
+ MTK_EINT_FUNCTION(0, 181),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "CONN_WF_CTRL1"),
+ MTK_FUNCTION(3, "UDI_TDO")
+ ),
+
+ MTK_PIN(
+ 182, "GPIO182",
+ MTK_EINT_FUNCTION(0, 182),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "CONN_WF_CTRL2"),
+ MTK_FUNCTION(3, "UDI_NTRST")
+ ),
+
+ MTK_PIN(
+ 183, "GPIO183",
+ MTK_EINT_FUNCTION(0, 183),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "SPMI_SCL")
+ ),
+
+ MTK_PIN(
+ 184, "GPIO184",
+ MTK_EINT_FUNCTION(0, 184),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "SPMI_SDA")
+ ),
+
+ MTK_PIN(
+ 185, "GPIO185",
+ MTK_EINT_FUNCTION(0, 197),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 186, "GPIO186",
+ MTK_EINT_FUNCTION(0, 198),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 187, "GPIO187",
+ MTK_EINT_FUNCTION(0, 199),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 188, "GPIO188",
+ MTK_EINT_FUNCTION(0, 200),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 189, "GPIO189",
+ MTK_EINT_FUNCTION(0, 201),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 190, "GPIO190",
+ MTK_EINT_FUNCTION(0, 202),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 191, "GPIO191",
+ MTK_EINT_FUNCTION(0, 203),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 192, "GPIO192",
+ MTK_EINT_FUNCTION(0, 204),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 193, "GPIO193",
+ MTK_EINT_FUNCTION(0, 205),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 194, "GPIO194",
+ MTK_EINT_FUNCTION(0, 206),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 195, "GPIO195",
+ MTK_EINT_FUNCTION(0, 207),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 196, "GPIO196",
+ MTK_EINT_FUNCTION(0, 208),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ )
+};
+
+#endif /* __PINCTRL_MTK_MT8186_H */
--
2.25.5
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document
From: Guodong Liu @ 2022-01-21 6:01 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Matthias Brugger, Sean Wang
Cc: Sean Wang, linux-gpio, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Guodong Liu
In-Reply-To: <20220121060120.10683-1-guodong.liu@mediatek.com>
1. This patch adds pinctrl file for mt8186.
2. This patch adds mt8186 compatible node in binding document.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
---
.../bindings/pinctrl/pinctrl-mt8186.yaml | 303 +++++
include/dt-bindings/pinctrl/mt8186-pinfunc.h | 1174 +++++++++++++++++
2 files changed, 1477 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
create mode 100644 include/dt-bindings/pinctrl/mt8186-pinfunc.h
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
new file mode 100644
index 000000000000..0a1154faca29
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
@@ -0,0 +1,303 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT8186 Pin Controller
+
+maintainers:
+ - Sean Wang <sean.wang@mediatek.com>
+
+description: |
+ The Mediatek's Pin controller is used to control SoC pins.
+
+properties:
+ compatible:
+ const: mediatek,mt8186-pinctrl
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: |
+ Number of cells in GPIO specifier. Since the generic GPIO binding is used,
+ the amount of cells must be specified as 2. See the below
+ mentioned gpio binding representation for description of particular cells.
+ const: 2
+
+ gpio-ranges:
+ description: gpio valid number range.
+ maxItems: 1
+
+ reg:
+ description: |
+ Physical address base for gpio base registers. There are 8 GPIO
+ physical address base in mt8186.
+ maxItems: 8
+
+ reg-names:
+ description: |
+ Gpio base register names.
+ maxItems: 8
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupts:
+ description: The interrupt outputs to sysirq.
+ maxItems: 1
+
+ mediatek,rsel_resistance_in_si_unit:
+ type: boolean
+ description: |
+ Identifying i2c pins pull up/down type which is RSEL. It can support
+ RSEL define or si unit value(ohm) to set different resistance.
+
+# PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '^pins':
+ type: object
+ additionalProperties: false
+ description: |
+ A pinctrl node should contain at least one subnodes representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to muxer
+ configuration, pullups, drive strength, input enable/disable and
+ input schmitt.
+ An example of using macro:
+ pincontroller {
+ /* GPIO0 set as multifunction GPIO0 */
+ gpio-pins {
+ pins {
+ pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
+ }
+ };
+ /* GPIO128 set as multifunction SDA0 */
+ i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
+ }
+ };
+ };
+ $ref: "pinmux-node.yaml"
+
+ properties:
+ pinmux:
+ description: |
+ Integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are
+ defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
+ directly.
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
+ mediatek,drive-strength-adv:
+ description: |
+ Describe the specific driving setup property.
+ For I2C pins, the existing generic driving setup can only support
+ 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
+ can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
+ driving setup, the existing generic setup will be disabled.
+ The specific driving setup is controlled by E1E0EN.
+ When E1=0/E0=0, the strength is 0.125mA.
+ When E1=0/E0=1, the strength is 0.25mA.
+ When E1=1/E0=0, the strength is 0.5mA.
+ When E1=1/E0=1, the strength is 1mA.
+ EN is used to enable or disable the specific driving setup.
+ Valid arguments are described as below:
+ 0: (E1, E0, EN) = (0, 0, 0)
+ 1: (E1, E0, EN) = (0, 0, 1)
+ 2: (E1, E0, EN) = (0, 1, 0)
+ 3: (E1, E0, EN) = (0, 1, 1)
+ 4: (E1, E0, EN) = (1, 0, 0)
+ 5: (E1, E0, EN) = (1, 0, 1)
+ 6: (E1, E0, EN) = (1, 1, 0)
+ 7: (E1, E0, EN) = (1, 1, 1)
+ So the valid arguments are from 0 to 7.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+
+ bias-pull-down:
+ description: |
+ For pull down type is normal, it don't need add RSEL & R1R0 define
+ and resistance value.
+ For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
+ set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
+ "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
+ "MTK_PUPD_SET_R1R0_11" define in mt8186.
+ For pull down type is RSEL, it can add RSEL define & resistance
+ value(ohm) to set different resistance by identifying property
+ "mediatek,rsel_resistance_in_si_unit".
+ It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
+ & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
+ & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
+ & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
+ define in mt8186. It can also support resistance value(ohm)
+ "75000" & "5000" in mt8186.
+ oneOf:
+ - enum: [100, 101, 102, 103]
+ - description: mt8186 pull down PUPD/R0/R1 type define value.
+ - enum: [200, 201, 202, 203, 204, 205, 206, 207]
+ - description: mt8186 pull down RSEL type define value.
+ - enum: [75000, 5000]
+ - description: mt8186 pull down RSEL type si unit value(ohm).
+
+ An example of using RSEL define:
+ pincontroller {
+ i2c0_pin {
+ pins {
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
+ bias-pull-down = <MTK_PULL_SET_RSEL_001>;
+ }
+ };
+ };
+ An example of using si unit resistance value(ohm):
+ &pio {
+ mediatek,rsel_resistance_in_si_unit;
+ }
+ pincontroller {
+ i2c0_pin {
+ pins {
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
+ bias-pull-down = <75000>;
+ }
+ };
+ };
+
+ bias-pull-up:
+ description: |
+ For pull up type is normal, it don't need add RSEL & R1R0 define
+ and resistance value.
+ For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
+ set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
+ "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
+ "MTK_PUPD_SET_R1R0_11" define in mt8186.
+ For pull up type is RSEL, it can add RSEL define & resistance
+ value(ohm) to set different resistance by identifying property
+ "mediatek,rsel_resistance_in_si_unit".
+ It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
+ & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
+ & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
+ & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
+ define in mt8186. It can also support resistance value(ohm)
+ "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" &
+ "75000" in mt8186.
+ oneOf:
+ - enum: [100, 101, 102, 103]
+ - description: mt8186 pull up PUPD/R0/R1 type define value.
+ - enum: [200, 201, 202, 203, 204, 205, 206, 207]
+ - description: mt8186 pull up RSEL type define value.
+ - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
+ - description: mt8186 pull up RSEL type si unit value(ohm).
+ An example of using RSEL define:
+ pincontroller {
+ i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_001>;
+ }
+ };
+ };
+ An example of using si unit resistance value(ohm):
+ &pio {
+ mediatek,rsel_resistance_in_si_unit;
+ }
+ pincontroller {
+ i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
+ bias-pull-up = <1000>;
+ }
+ };
+ };
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ required:
+ - pinmux
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8186-pinctrl";
+ reg = <0x10005000 0x1000>,
+ <0x10002000 0x0200>,
+ <0x10002200 0x0200>,
+ <0x10002400 0x0200>,
+ <0x10002600 0x0200>,
+ <0x10002A00 0x0200>,
+ <0x10002c00 0x0200>,
+ <0x1000b000 0x1000>;
+ reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
+ "iocfg_br", "iocfg_lm", "iocfg_rb",
+ "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 185>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
+ #interrupt-cells = <2>;
+
+ pio-pins {
+ pins {
+ pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
+ output-low;
+ };
+ };
+
+ spi0-pins {
+ pins-spi {
+ pinmux = <PINMUX_GPIO0__FUNC_SPI0_CLK_B>,
+ <PINMUX_GPIO1__FUNC_SPI0_CSB_B>,
+ <PINMUX_GPIO2__FUNC_SPI0_MO_B>;
+ bias-disable;
+ };
+ pins-spi-mi {
+ pinmux = <PINMUX_GPIO3__FUNC_SPI0_MI_B>;
+ bias-pull-down;
+ };
+ };
+
+ i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO127__FUNC_SCL0>,
+ <PINMUX_GPIO128__FUNC_SDA0>;
+ bias-disable;
+ mediatek,drive-strength-adv = <7>;
+ };
+ };
+ };
diff --git a/include/dt-bindings/pinctrl/mt8186-pinfunc.h b/include/dt-bindings/pinctrl/mt8186-pinfunc.h
new file mode 100644
index 000000000000..f58983d11bca
--- /dev/null
+++ b/include/dt-bindings/pinctrl/mt8186-pinfunc.h
@@ -0,0 +1,1174 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Guodong Liu <Guodong.Liu@mediatek.com>
+ *
+ */
+
+#ifndef __MT8168_PINFUNC_H
+#define __MT8168_PINFUNC_H
+
+#include "mt65xx.h"
+
+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define PINMUX_GPIO0__FUNC_I2S0_MCK (MTK_PIN_NO(0) | 1)
+#define PINMUX_GPIO0__FUNC_SPI0_CLK_B (MTK_PIN_NO(0) | 2)
+#define PINMUX_GPIO0__FUNC_I2S2_MCK (MTK_PIN_NO(0) | 3)
+#define PINMUX_GPIO0__FUNC_CMFLASH0 (MTK_PIN_NO(0) | 4)
+#define PINMUX_GPIO0__FUNC_SCP_SPI0_CK (MTK_PIN_NO(0) | 5)
+#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6)
+#define PINMUX_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7)
+
+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define PINMUX_GPIO1__FUNC_I2S0_BCK (MTK_PIN_NO(1) | 1)
+#define PINMUX_GPIO1__FUNC_SPI0_CSB_B (MTK_PIN_NO(1) | 2)
+#define PINMUX_GPIO1__FUNC_I2S2_BCK (MTK_PIN_NO(1) | 3)
+#define PINMUX_GPIO1__FUNC_CMFLASH1 (MTK_PIN_NO(1) | 4)
+#define PINMUX_GPIO1__FUNC_SCP_SPI0_CS (MTK_PIN_NO(1) | 5)
+#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6)
+
+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define PINMUX_GPIO2__FUNC_I2S0_LRCK (MTK_PIN_NO(2) | 1)
+#define PINMUX_GPIO2__FUNC_SPI0_MO_B (MTK_PIN_NO(2) | 2)
+#define PINMUX_GPIO2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3)
+#define PINMUX_GPIO2__FUNC_CMFLASH2 (MTK_PIN_NO(2) | 4)
+#define PINMUX_GPIO2__FUNC_SCP_SPI0_MO (MTK_PIN_NO(2) | 5)
+#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6)
+
+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define PINMUX_GPIO3__FUNC_I2S0_DI (MTK_PIN_NO(3) | 1)
+#define PINMUX_GPIO3__FUNC_SPI0_MI_B (MTK_PIN_NO(3) | 2)
+#define PINMUX_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3)
+#define PINMUX_GPIO3__FUNC_SRCLKENAI1 (MTK_PIN_NO(3) | 4)
+#define PINMUX_GPIO3__FUNC_SCP_SPI0_MI (MTK_PIN_NO(3) | 5)
+#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6)
+
+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define PINMUX_GPIO4__FUNC_I2S3_DO (MTK_PIN_NO(4) | 1)
+#define PINMUX_GPIO4__FUNC_I2S1_DO (MTK_PIN_NO(4) | 3)
+#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6)
+
+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define PINMUX_GPIO5__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(5) | 1)
+#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6)
+
+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define PINMUX_GPIO6__FUNC_I2S3_MCK (MTK_PIN_NO(6) | 1)
+#define PINMUX_GPIO6__FUNC_SPI1_CLK_B (MTK_PIN_NO(6) | 2)
+#define PINMUX_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3)
+#define PINMUX_GPIO6__FUNC_DPI_DATA22 (MTK_PIN_NO(6) | 4)
+#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6)
+
+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define PINMUX_GPIO7__FUNC_I2S3_BCK (MTK_PIN_NO(7) | 1)
+#define PINMUX_GPIO7__FUNC_SPI1_CSB_B (MTK_PIN_NO(7) | 2)
+#define PINMUX_GPIO7__FUNC_I2S1_BCK (MTK_PIN_NO(7) | 3)
+#define PINMUX_GPIO7__FUNC_DPI_DATA23 (MTK_PIN_NO(7) | 4)
+#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6)
+
+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define PINMUX_GPIO8__FUNC_I2S3_LRCK (MTK_PIN_NO(8) | 1)
+#define PINMUX_GPIO8__FUNC_SPI1_MO_B (MTK_PIN_NO(8) | 2)
+#define PINMUX_GPIO8__FUNC_I2S1_LRCK (MTK_PIN_NO(8) | 3)
+#define PINMUX_GPIO8__FUNC_CONN_UART0_RXD (MTK_PIN_NO(8) | 4)
+#define PINMUX_GPIO8__FUNC_SSPM_URXD_AO (MTK_PIN_NO(8) | 5)
+#define PINMUX_GPIO8__FUNC_ADSP_UART_RX (MTK_PIN_NO(8) | 6)
+#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 7)
+
+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define PINMUX_GPIO9__FUNC_I2S3_DO (MTK_PIN_NO(9) | 1)
+#define PINMUX_GPIO9__FUNC_SPI1_MI_B (MTK_PIN_NO(9) | 2)
+#define PINMUX_GPIO9__FUNC_I2S1_DO (MTK_PIN_NO(9) | 3)
+#define PINMUX_GPIO9__FUNC_CONN_UART0_TXD (MTK_PIN_NO(9) | 4)
+#define PINMUX_GPIO9__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(9) | 5)
+#define PINMUX_GPIO9__FUNC_ADSP_UART_TX (MTK_PIN_NO(9) | 6)
+#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(9) | 7)
+
+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define PINMUX_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 1)
+#define PINMUX_GPIO10__FUNC_SPI4_CLK_A (MTK_PIN_NO(10) | 2)
+#define PINMUX_GPIO10__FUNC_I2S2_MCK (MTK_PIN_NO(10) | 3)
+#define PINMUX_GPIO10__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(10) | 4)
+#define PINMUX_GPIO10__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(10) | 5)
+#define PINMUX_GPIO10__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(10) | 6)
+#define PINMUX_GPIO10__FUNC_CONN_MCU_TDI (MTK_PIN_NO(10) | 7)
+
+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define PINMUX_GPIO11__FUNC_I2S0_BCK (MTK_PIN_NO(11) | 1)
+#define PINMUX_GPIO11__FUNC_SPI4_CSB_A (MTK_PIN_NO(11) | 2)
+#define PINMUX_GPIO11__FUNC_I2S2_BCK (MTK_PIN_NO(11) | 3)
+#define PINMUX_GPIO11__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(11) | 4)
+#define PINMUX_GPIO11__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(11) | 5)
+#define PINMUX_GPIO11__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(11) | 6)
+#define PINMUX_GPIO11__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(11) | 7)
+
+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define PINMUX_GPIO12__FUNC_I2S0_LRCK (MTK_PIN_NO(12) | 1)
+#define PINMUX_GPIO12__FUNC_SPI4_MO_A (MTK_PIN_NO(12) | 2)
+#define PINMUX_GPIO12__FUNC_I2S2_LRCK (MTK_PIN_NO(12) | 3)
+#define PINMUX_GPIO12__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(12) | 4)
+#define PINMUX_GPIO12__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(12) | 5)
+#define PINMUX_GPIO12__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(12) | 6)
+#define PINMUX_GPIO12__FUNC_CONN_MCU_TCK (MTK_PIN_NO(12) | 7)
+
+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define PINMUX_GPIO13__FUNC_I2S0_DI (MTK_PIN_NO(13) | 1)
+#define PINMUX_GPIO13__FUNC_SPI4_MI_A (MTK_PIN_NO(13) | 2)
+#define PINMUX_GPIO13__FUNC_I2S2_DI (MTK_PIN_NO(13) | 3)
+#define PINMUX_GPIO13__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(13) | 4)
+#define PINMUX_GPIO13__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(13) | 5)
+#define PINMUX_GPIO13__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(13) | 6)
+#define PINMUX_GPIO13__FUNC_CONN_MCU_TDO (MTK_PIN_NO(13) | 7)
+
+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define PINMUX_GPIO14__FUNC_CLKM0 (MTK_PIN_NO(14) | 3)
+#define PINMUX_GPIO14__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(14) | 4)
+#define PINMUX_GPIO14__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(14) | 5)
+#define PINMUX_GPIO14__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(14) | 6)
+#define PINMUX_GPIO14__FUNC_CONN_MCU_TMS (MTK_PIN_NO(14) | 7)
+
+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define PINMUX_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 1)
+#define PINMUX_GPIO15__FUNC_SRCLKENAI1 (MTK_PIN_NO(15) | 2)
+#define PINMUX_GPIO15__FUNC_CLKM1 (MTK_PIN_NO(15) | 3)
+#define PINMUX_GPIO15__FUNC_PWM0 (MTK_PIN_NO(15) | 4)
+
+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define PINMUX_GPIO16__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(16) | 1)
+#define PINMUX_GPIO16__FUNC_SRCLKENAI0 (MTK_PIN_NO(16) | 2)
+#define PINMUX_GPIO16__FUNC_CLKM2 (MTK_PIN_NO(16) | 3)
+#define PINMUX_GPIO16__FUNC_PWM1 (MTK_PIN_NO(16) | 4)
+
+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define PINMUX_GPIO17__FUNC_CLKM3 (MTK_PIN_NO(17) | 3)
+#define PINMUX_GPIO17__FUNC_PWM2 (MTK_PIN_NO(17) | 4)
+#define PINMUX_GPIO17__FUNC_DBG_MON_A32 (MTK_PIN_NO(17) | 7)
+
+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define PINMUX_GPIO18__FUNC_CMVREF0 (MTK_PIN_NO(18) | 2)
+#define PINMUX_GPIO18__FUNC_SPI2_CLK_B (MTK_PIN_NO(18) | 6)
+#define PINMUX_GPIO18__FUNC_DBG_MON_A26 (MTK_PIN_NO(18) | 7)
+
+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define PINMUX_GPIO19__FUNC_CMVREF1 (MTK_PIN_NO(19) | 2)
+#define PINMUX_GPIO19__FUNC_ANT_SEL3 (MTK_PIN_NO(19) | 5)
+#define PINMUX_GPIO19__FUNC_SPI2_CSB_B (MTK_PIN_NO(19) | 6)
+#define PINMUX_GPIO19__FUNC_DBG_MON_A2 (MTK_PIN_NO(19) | 7)
+
+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define PINMUX_GPIO20__FUNC_CMVREF2 (MTK_PIN_NO(20) | 2)
+#define PINMUX_GPIO20__FUNC_ANT_SEL4 (MTK_PIN_NO(20) | 5)
+#define PINMUX_GPIO20__FUNC_SPI2_MO_B (MTK_PIN_NO(20) | 6)
+#define PINMUX_GPIO20__FUNC_DBG_MON_A3 (MTK_PIN_NO(20) | 7)
+
+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define PINMUX_GPIO21__FUNC_I2S0_MCK (MTK_PIN_NO(21) | 1)
+#define PINMUX_GPIO21__FUNC_I2S1_MCK (MTK_PIN_NO(21) | 2)
+#define PINMUX_GPIO21__FUNC_I2S3_MCK (MTK_PIN_NO(21) | 3)
+#define PINMUX_GPIO21__FUNC_ANT_SEL5 (MTK_PIN_NO(21) | 5)
+#define PINMUX_GPIO21__FUNC_SPI2_MI_B (MTK_PIN_NO(21) | 6)
+#define PINMUX_GPIO21__FUNC_DBG_MON_A4 (MTK_PIN_NO(21) | 7)
+
+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define PINMUX_GPIO22__FUNC_I2S0_BCK (MTK_PIN_NO(22) | 1)
+#define PINMUX_GPIO22__FUNC_I2S1_BCK (MTK_PIN_NO(22) | 2)
+#define PINMUX_GPIO22__FUNC_I2S3_BCK (MTK_PIN_NO(22) | 3)
+#define PINMUX_GPIO22__FUNC_TDM_RX_LRCK (MTK_PIN_NO(22) | 4)
+#define PINMUX_GPIO22__FUNC_ANT_SEL6 (MTK_PIN_NO(22) | 5)
+#define PINMUX_GPIO22__FUNC_DBG_MON_A5 (MTK_PIN_NO(22) | 7)
+
+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define PINMUX_GPIO23__FUNC_I2S0_LRCK (MTK_PIN_NO(23) | 1)
+#define PINMUX_GPIO23__FUNC_I2S1_LRCK (MTK_PIN_NO(23) | 2)
+#define PINMUX_GPIO23__FUNC_I2S3_LRCK (MTK_PIN_NO(23) | 3)
+#define PINMUX_GPIO23__FUNC_TDM_RX_BCK (MTK_PIN_NO(23) | 4)
+#define PINMUX_GPIO23__FUNC_ANT_SEL7 (MTK_PIN_NO(23) | 5)
+#define PINMUX_GPIO23__FUNC_DBG_MON_A6 (MTK_PIN_NO(23) | 7)
+
+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define PINMUX_GPIO24__FUNC_I2S0_DI (MTK_PIN_NO(24) | 1)
+#define PINMUX_GPIO24__FUNC_I2S1_DO (MTK_PIN_NO(24) | 2)
+#define PINMUX_GPIO24__FUNC_I2S3_DO (MTK_PIN_NO(24) | 3)
+#define PINMUX_GPIO24__FUNC_TDM_RX_MCK (MTK_PIN_NO(24) | 4)
+#define PINMUX_GPIO24__FUNC_DBG_MON_A7 (MTK_PIN_NO(24) | 7)
+
+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define PINMUX_GPIO25__FUNC_I2S2_MCK (MTK_PIN_NO(25) | 1)
+#define PINMUX_GPIO25__FUNC_PCM_CLK (MTK_PIN_NO(25) | 2)
+#define PINMUX_GPIO25__FUNC_SPI4_CLK_B (MTK_PIN_NO(25) | 3)
+#define PINMUX_GPIO25__FUNC_TDM_RX_DATA0 (MTK_PIN_NO(25) | 4)
+#define PINMUX_GPIO25__FUNC_DBG_MON_A8 (MTK_PIN_NO(25) | 7)
+
+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define PINMUX_GPIO26__FUNC_I2S2_BCK (MTK_PIN_NO(26) | 1)
+#define PINMUX_GPIO26__FUNC_PCM_SYNC (MTK_PIN_NO(26) | 2)
+#define PINMUX_GPIO26__FUNC_SPI4_CSB_B (MTK_PIN_NO(26) | 3)
+#define PINMUX_GPIO26__FUNC_TDM_RX_DATA1 (MTK_PIN_NO(26) | 4)
+#define PINMUX_GPIO26__FUNC_DBG_MON_A9 (MTK_PIN_NO(26) | 7)
+
+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define PINMUX_GPIO27__FUNC_I2S2_LRCK (MTK_PIN_NO(27) | 1)
+#define PINMUX_GPIO27__FUNC_PCM_DI (MTK_PIN_NO(27) | 2)
+#define PINMUX_GPIO27__FUNC_SPI4_MO_B (MTK_PIN_NO(27) | 3)
+#define PINMUX_GPIO27__FUNC_TDM_RX_DATA2 (MTK_PIN_NO(27) | 4)
+#define PINMUX_GPIO27__FUNC_DBG_MON_A10 (MTK_PIN_NO(27) | 7)
+
+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define PINMUX_GPIO28__FUNC_I2S2_DI (MTK_PIN_NO(28) | 1)
+#define PINMUX_GPIO28__FUNC_PCM_DO (MTK_PIN_NO(28) | 2)
+#define PINMUX_GPIO28__FUNC_SPI4_MI_B (MTK_PIN_NO(28) | 3)
+#define PINMUX_GPIO28__FUNC_TDM_RX_DATA3 (MTK_PIN_NO(28) | 4)
+
+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define PINMUX_GPIO29__FUNC_ANT_SEL0 (MTK_PIN_NO(29) | 1)
+#define PINMUX_GPIO29__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(29) | 2)
+
+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define PINMUX_GPIO30__FUNC_ANT_SEL1 (MTK_PIN_NO(30) | 1)
+
+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define PINMUX_GPIO31__FUNC_ANT_SEL2 (MTK_PIN_NO(31) | 1)
+#define PINMUX_GPIO31__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(31) | 2)
+#define PINMUX_GPIO31__FUNC_SRCLKENAI1 (MTK_PIN_NO(31) | 3)
+
+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define PINMUX_GPIO32__FUNC_URXD0 (MTK_PIN_NO(32) | 1)
+#define PINMUX_GPIO32__FUNC_UTXD0 (MTK_PIN_NO(32) | 2)
+#define PINMUX_GPIO32__FUNC_ADSP_UART_RX (MTK_PIN_NO(32) | 3)
+#define PINMUX_GPIO32__FUNC_TP_URXD1_AO (MTK_PIN_NO(32) | 4)
+
+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define PINMUX_GPIO33__FUNC_UTXD0 (MTK_PIN_NO(33) | 1)
+#define PINMUX_GPIO33__FUNC_URXD0 (MTK_PIN_NO(33) | 2)
+#define PINMUX_GPIO33__FUNC_ADSP_UART_TX (MTK_PIN_NO(33) | 3)
+#define PINMUX_GPIO33__FUNC_TP_UTXD1_AO (MTK_PIN_NO(33) | 4)
+
+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define PINMUX_GPIO34__FUNC_URXD1 (MTK_PIN_NO(34) | 1)
+#define PINMUX_GPIO34__FUNC_TP_URXD2_AO (MTK_PIN_NO(34) | 2)
+#define PINMUX_GPIO34__FUNC_SSPM_URXD_AO (MTK_PIN_NO(34) | 3)
+#define PINMUX_GPIO34__FUNC_ADSP_UART_RX (MTK_PIN_NO(34) | 4)
+#define PINMUX_GPIO34__FUNC_CONN_UART0_RXD (MTK_PIN_NO(34) | 5)
+
+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define PINMUX_GPIO35__FUNC_UTXD1 (MTK_PIN_NO(35) | 1)
+#define PINMUX_GPIO35__FUNC_TP_UTXD2_AO (MTK_PIN_NO(35) | 2)
+#define PINMUX_GPIO35__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(35) | 3)
+#define PINMUX_GPIO35__FUNC_ADSP_UART_TX (MTK_PIN_NO(35) | 4)
+#define PINMUX_GPIO35__FUNC_CONN_UART0_TXD (MTK_PIN_NO(35) | 5)
+#define PINMUX_GPIO35__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(35) | 6)
+
+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define PINMUX_GPIO36__FUNC_SPI0_CLK_A (MTK_PIN_NO(36) | 1)
+#define PINMUX_GPIO36__FUNC_CLKM0 (MTK_PIN_NO(36) | 2)
+#define PINMUX_GPIO36__FUNC_SCP_SPI0_CK (MTK_PIN_NO(36) | 4)
+#define PINMUX_GPIO36__FUNC_SPINOR_CK (MTK_PIN_NO(36) | 5)
+#define PINMUX_GPIO36__FUNC_DBG_MON_A11 (MTK_PIN_NO(36) | 7)
+
+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define PINMUX_GPIO37__FUNC_SPI0_CSB_A (MTK_PIN_NO(37) | 1)
+#define PINMUX_GPIO37__FUNC_CLKM1 (MTK_PIN_NO(37) | 2)
+#define PINMUX_GPIO37__FUNC_PWM0 (MTK_PIN_NO(37) | 3)
+#define PINMUX_GPIO37__FUNC_SCP_SPI0_CS (MTK_PIN_NO(37) | 4)
+#define PINMUX_GPIO37__FUNC_SPINOR_CS (MTK_PIN_NO(37) | 5)
+#define PINMUX_GPIO37__FUNC_DBG_MON_A12 (MTK_PIN_NO(37) | 7)
+
+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define PINMUX_GPIO38__FUNC_SPI0_MO_A (MTK_PIN_NO(38) | 1)
+#define PINMUX_GPIO38__FUNC_CLKM2 (MTK_PIN_NO(38) | 2)
+#define PINMUX_GPIO38__FUNC_PWM1 (MTK_PIN_NO(38) | 3)
+#define PINMUX_GPIO38__FUNC_SCP_SPI0_MO (MTK_PIN_NO(38) | 4)
+#define PINMUX_GPIO38__FUNC_SPINOR_IO0 (MTK_PIN_NO(38) | 5)
+#define PINMUX_GPIO38__FUNC_DBG_MON_A13 (MTK_PIN_NO(38) | 7)
+
+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define PINMUX_GPIO39__FUNC_SPI0_MI_A (MTK_PIN_NO(39) | 1)
+#define PINMUX_GPIO39__FUNC_CLKM3 (MTK_PIN_NO(39) | 2)
+#define PINMUX_GPIO39__FUNC_PWM2 (MTK_PIN_NO(39) | 3)
+#define PINMUX_GPIO39__FUNC_SCP_SPI0_MI (MTK_PIN_NO(39) | 4)
+#define PINMUX_GPIO39__FUNC_SPINOR_IO1 (MTK_PIN_NO(39) | 5)
+#define PINMUX_GPIO39__FUNC_DBG_MON_A14 (MTK_PIN_NO(39) | 7)
+
+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define PINMUX_GPIO40__FUNC_SPI1_CLK_A (MTK_PIN_NO(40) | 1)
+#define PINMUX_GPIO40__FUNC_SCP_SPI1_CK (MTK_PIN_NO(40) | 2)
+#define PINMUX_GPIO40__FUNC_UCTS0 (MTK_PIN_NO(40) | 4)
+#define PINMUX_GPIO40__FUNC_SPINOR_IO2 (MTK_PIN_NO(40) | 5)
+#define PINMUX_GPIO40__FUNC_TP_UCTS1_AO (MTK_PIN_NO(40) | 6)
+#define PINMUX_GPIO40__FUNC_DBG_MON_A15 (MTK_PIN_NO(40) | 7)
+
+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define PINMUX_GPIO41__FUNC_SPI1_CSB_A (MTK_PIN_NO(41) | 1)
+#define PINMUX_GPIO41__FUNC_SCP_SPI1_CS (MTK_PIN_NO(41) | 2)
+#define PINMUX_GPIO41__FUNC_PWM0 (MTK_PIN_NO(41) | 3)
+#define PINMUX_GPIO41__FUNC_URTS0 (MTK_PIN_NO(41) | 4)
+#define PINMUX_GPIO41__FUNC_SPINOR_IO3 (MTK_PIN_NO(41) | 5)
+#define PINMUX_GPIO41__FUNC_TP_URTS1_AO (MTK_PIN_NO(41) | 6)
+#define PINMUX_GPIO41__FUNC_DBG_MON_A16 (MTK_PIN_NO(41) | 7)
+
+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define PINMUX_GPIO42__FUNC_SPI1_MO_A (MTK_PIN_NO(42) | 1)
+#define PINMUX_GPIO42__FUNC_SCP_SPI1_MO (MTK_PIN_NO(42) | 2)
+#define PINMUX_GPIO42__FUNC_PWM1 (MTK_PIN_NO(42) | 3)
+#define PINMUX_GPIO42__FUNC_UCTS1 (MTK_PIN_NO(42) | 4)
+#define PINMUX_GPIO42__FUNC_TP_UCTS2_AO (MTK_PIN_NO(42) | 6)
+#define PINMUX_GPIO42__FUNC_DBG_MON_A17 (MTK_PIN_NO(42) | 7)
+
+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define PINMUX_GPIO43__FUNC_SPI1_MI_A (MTK_PIN_NO(43) | 1)
+#define PINMUX_GPIO43__FUNC_SCP_SPI1_MI (MTK_PIN_NO(43) | 2)
+#define PINMUX_GPIO43__FUNC_PWM2 (MTK_PIN_NO(43) | 3)
+#define PINMUX_GPIO43__FUNC_URTS1 (MTK_PIN_NO(43) | 4)
+#define PINMUX_GPIO43__FUNC_TP_URTS2_AO (MTK_PIN_NO(43) | 6)
+#define PINMUX_GPIO43__FUNC_DBG_MON_A18 (MTK_PIN_NO(43) | 7)
+
+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define PINMUX_GPIO44__FUNC_SPI2_CLK_A (MTK_PIN_NO(44) | 1)
+#define PINMUX_GPIO44__FUNC_SCP_SPI0_CK (MTK_PIN_NO(44) | 2)
+#define PINMUX_GPIO44__FUNC_DBG_MON_A19 (MTK_PIN_NO(44) | 7)
+
+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define PINMUX_GPIO45__FUNC_SPI2_CSB_A (MTK_PIN_NO(45) | 1)
+#define PINMUX_GPIO45__FUNC_SCP_SPI0_CS (MTK_PIN_NO(45) | 2)
+#define PINMUX_GPIO45__FUNC_DBG_MON_A20 (MTK_PIN_NO(45) | 7)
+
+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define PINMUX_GPIO46__FUNC_SPI2_MO_A (MTK_PIN_NO(46) | 1)
+#define PINMUX_GPIO46__FUNC_SCP_SPI0_MO (MTK_PIN_NO(46) | 2)
+#define PINMUX_GPIO46__FUNC_DBG_MON_A21 (MTK_PIN_NO(46) | 7)
+
+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define PINMUX_GPIO47__FUNC_SPI2_MI_A (MTK_PIN_NO(47) | 1)
+#define PINMUX_GPIO47__FUNC_SCP_SPI0_MI (MTK_PIN_NO(47) | 2)
+#define PINMUX_GPIO47__FUNC_DBG_MON_A22 (MTK_PIN_NO(47) | 7)
+
+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define PINMUX_GPIO48__FUNC_SPI3_CLK (MTK_PIN_NO(48) | 1)
+#define PINMUX_GPIO48__FUNC_TP_URXD1_AO (MTK_PIN_NO(48) | 2)
+#define PINMUX_GPIO48__FUNC_TP_URXD2_AO (MTK_PIN_NO(48) | 3)
+#define PINMUX_GPIO48__FUNC_URXD1 (MTK_PIN_NO(48) | 4)
+#define PINMUX_GPIO48__FUNC_I2S2_MCK (MTK_PIN_NO(48) | 5)
+#define PINMUX_GPIO48__FUNC_SCP_SPI0_CK (MTK_PIN_NO(48) | 6)
+
+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define PINMUX_GPIO49__FUNC_SPI3_CSB (MTK_PIN_NO(49) | 1)
+#define PINMUX_GPIO49__FUNC_TP_UTXD1_AO (MTK_PIN_NO(49) | 2)
+#define PINMUX_GPIO49__FUNC_TP_UTXD2_AO (MTK_PIN_NO(49) | 3)
+#define PINMUX_GPIO49__FUNC_UTXD1 (MTK_PIN_NO(49) | 4)
+#define PINMUX_GPIO49__FUNC_I2S2_BCK (MTK_PIN_NO(49) | 5)
+#define PINMUX_GPIO49__FUNC_SCP_SPI0_CS (MTK_PIN_NO(49) | 6)
+
+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define PINMUX_GPIO50__FUNC_SPI3_MO (MTK_PIN_NO(50) | 1)
+#define PINMUX_GPIO50__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 5)
+#define PINMUX_GPIO50__FUNC_SCP_SPI0_MO (MTK_PIN_NO(50) | 6)
+
+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define PINMUX_GPIO51__FUNC_SPI3_MI (MTK_PIN_NO(51) | 1)
+#define PINMUX_GPIO51__FUNC_I2S2_DI (MTK_PIN_NO(51) | 5)
+#define PINMUX_GPIO51__FUNC_SCP_SPI0_MI (MTK_PIN_NO(51) | 6)
+
+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define PINMUX_GPIO52__FUNC_SPI5_CLK (MTK_PIN_NO(52) | 1)
+#define PINMUX_GPIO52__FUNC_I2S2_MCK (MTK_PIN_NO(52) | 2)
+#define PINMUX_GPIO52__FUNC_I2S1_MCK (MTK_PIN_NO(52) | 3)
+#define PINMUX_GPIO52__FUNC_SCP_SPI1_CK (MTK_PIN_NO(52) | 4)
+#define PINMUX_GPIO52__FUNC_LVTS_26M (MTK_PIN_NO(52) | 5)
+#define PINMUX_GPIO52__FUNC_DFD_TCK_XI (MTK_PIN_NO(52) | 6)
+#define PINMUX_GPIO52__FUNC_DBG_MON_B30 (MTK_PIN_NO(52) | 7)
+
+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define PINMUX_GPIO53__FUNC_SPI5_CSB (MTK_PIN_NO(53) | 1)
+#define PINMUX_GPIO53__FUNC_I2S2_BCK (MTK_PIN_NO(53) | 2)
+#define PINMUX_GPIO53__FUNC_I2S1_BCK (MTK_PIN_NO(53) | 3)
+#define PINMUX_GPIO53__FUNC_SCP_SPI1_CS (MTK_PIN_NO(53) | 4)
+#define PINMUX_GPIO53__FUNC_LVTS_FOUT (MTK_PIN_NO(53) | 5)
+#define PINMUX_GPIO53__FUNC_DFD_TDI (MTK_PIN_NO(53) | 6)
+#define PINMUX_GPIO53__FUNC_DBG_MON_B31 (MTK_PIN_NO(53) | 7)
+
+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define PINMUX_GPIO54__FUNC_SPI5_MO (MTK_PIN_NO(54) | 1)
+#define PINMUX_GPIO54__FUNC_I2S2_LRCK (MTK_PIN_NO(54) | 2)
+#define PINMUX_GPIO54__FUNC_I2S1_LRCK (MTK_PIN_NO(54) | 3)
+#define PINMUX_GPIO54__FUNC_SCP_SPI1_MO (MTK_PIN_NO(54) | 4)
+#define PINMUX_GPIO54__FUNC_LVTS_SCK (MTK_PIN_NO(54) | 5)
+#define PINMUX_GPIO54__FUNC_DFD_TDO (MTK_PIN_NO(54) | 6)
+#define PINMUX_GPIO54__FUNC_DBG_MON_A1 (MTK_PIN_NO(54) | 7)
+
+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define PINMUX_GPIO55__FUNC_SPI5_MI (MTK_PIN_NO(55) | 1)
+#define PINMUX_GPIO55__FUNC_I2S2_DI (MTK_PIN_NO(55) | 2)
+#define PINMUX_GPIO55__FUNC_I2S1_DO (MTK_PIN_NO(55) | 3)
+#define PINMUX_GPIO55__FUNC_SCP_SPI1_MI (MTK_PIN_NO(55) | 4)
+#define PINMUX_GPIO55__FUNC_LVTS_SDO (MTK_PIN_NO(55) | 5)
+#define PINMUX_GPIO55__FUNC_DFD_TMS (MTK_PIN_NO(55) | 6)
+#define PINMUX_GPIO55__FUNC_DBG_MON_B32 (MTK_PIN_NO(55) | 7)
+
+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define PINMUX_GPIO56__FUNC_I2S1_DO (MTK_PIN_NO(56) | 1)
+#define PINMUX_GPIO56__FUNC_I2S3_DO (MTK_PIN_NO(56) | 2)
+#define PINMUX_GPIO56__FUNC_DBG_MON_A23 (MTK_PIN_NO(56) | 7)
+
+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define PINMUX_GPIO57__FUNC_I2S1_BCK (MTK_PIN_NO(57) | 1)
+#define PINMUX_GPIO57__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 2)
+#define PINMUX_GPIO57__FUNC_DBG_MON_A24 (MTK_PIN_NO(57) | 7)
+
+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define PINMUX_GPIO58__FUNC_I2S1_LRCK (MTK_PIN_NO(58) | 1)
+#define PINMUX_GPIO58__FUNC_I2S3_LRCK (MTK_PIN_NO(58) | 2)
+#define PINMUX_GPIO58__FUNC_DBG_MON_A25 (MTK_PIN_NO(58) | 7)
+
+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define PINMUX_GPIO59__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 1)
+#define PINMUX_GPIO59__FUNC_I2S3_MCK (MTK_PIN_NO(59) | 2)
+#define PINMUX_GPIO59__FUNC_DBG_MON_A27 (MTK_PIN_NO(59) | 7)
+
+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define PINMUX_GPIO60__FUNC_TDM_RX_LRCK (MTK_PIN_NO(60) | 1)
+#define PINMUX_GPIO60__FUNC_ANT_SEL3 (MTK_PIN_NO(60) | 2)
+#define PINMUX_GPIO60__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(60) | 5)
+
+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define PINMUX_GPIO61__FUNC_TDM_RX_BCK (MTK_PIN_NO(61) | 1)
+#define PINMUX_GPIO61__FUNC_ANT_SEL4 (MTK_PIN_NO(61) | 2)
+#define PINMUX_GPIO61__FUNC_SPINOR_CK (MTK_PIN_NO(61) | 4)
+#define PINMUX_GPIO61__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(61) | 5)
+
+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define PINMUX_GPIO62__FUNC_TDM_RX_MCK (MTK_PIN_NO(62) | 1)
+#define PINMUX_GPIO62__FUNC_ANT_SEL5 (MTK_PIN_NO(62) | 2)
+#define PINMUX_GPIO62__FUNC_SPINOR_CS (MTK_PIN_NO(62) | 4)
+#define PINMUX_GPIO62__FUNC_CONN_MCU_TDI (MTK_PIN_NO(62) | 5)
+
+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define PINMUX_GPIO63__FUNC_TDM_RX_DATA0 (MTK_PIN_NO(63) | 1)
+#define PINMUX_GPIO63__FUNC_ANT_SEL6 (MTK_PIN_NO(63) | 2)
+#define PINMUX_GPIO63__FUNC_SPINOR_IO0 (MTK_PIN_NO(63) | 4)
+#define PINMUX_GPIO63__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(63) | 5)
+
+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define PINMUX_GPIO64__FUNC_TDM_RX_DATA1 (MTK_PIN_NO(64) | 1)
+#define PINMUX_GPIO64__FUNC_ANT_SEL7 (MTK_PIN_NO(64) | 2)
+#define PINMUX_GPIO64__FUNC_PWM0 (MTK_PIN_NO(64) | 3)
+#define PINMUX_GPIO64__FUNC_SPINOR_IO1 (MTK_PIN_NO(64) | 4)
+#define PINMUX_GPIO64__FUNC_CONN_MCU_TCK (MTK_PIN_NO(64) | 5)
+
+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define PINMUX_GPIO65__FUNC_TDM_RX_DATA2 (MTK_PIN_NO(65) | 1)
+#define PINMUX_GPIO65__FUNC_UCTS0 (MTK_PIN_NO(65) | 2)
+#define PINMUX_GPIO65__FUNC_PWM1 (MTK_PIN_NO(65) | 3)
+#define PINMUX_GPIO65__FUNC_SPINOR_IO2 (MTK_PIN_NO(65) | 4)
+#define PINMUX_GPIO65__FUNC_CONN_MCU_TDO (MTK_PIN_NO(65) | 5)
+#define PINMUX_GPIO65__FUNC_TP_UCTS1_AO (MTK_PIN_NO(65) | 6)
+#define PINMUX_GPIO65__FUNC_TP_UCTS2_AO (MTK_PIN_NO(65) | 7)
+
+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define PINMUX_GPIO66__FUNC_TDM_RX_DATA3 (MTK_PIN_NO(66) | 1)
+#define PINMUX_GPIO66__FUNC_URTS0 (MTK_PIN_NO(66) | 2)
+#define PINMUX_GPIO66__FUNC_PWM2 (MTK_PIN_NO(66) | 3)
+#define PINMUX_GPIO66__FUNC_SPINOR_IO3 (MTK_PIN_NO(66) | 4)
+#define PINMUX_GPIO66__FUNC_CONN_MCU_TMS (MTK_PIN_NO(66) | 5)
+#define PINMUX_GPIO66__FUNC_TP_URTS1_AO (MTK_PIN_NO(66) | 6)
+#define PINMUX_GPIO66__FUNC_TP_URTS2_AO (MTK_PIN_NO(66) | 7)
+
+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define PINMUX_GPIO67__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1)
+
+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define PINMUX_GPIO68__FUNC_MSDC0_CLK (MTK_PIN_NO(68) | 1)
+
+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define PINMUX_GPIO69__FUNC_MSDC0_CMD (MTK_PIN_NO(69) | 1)
+
+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define PINMUX_GPIO70__FUNC_MSDC0_RSTB (MTK_PIN_NO(70) | 1)
+
+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define PINMUX_GPIO71__FUNC_MSDC0_DAT0 (MTK_PIN_NO(71) | 1)
+
+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define PINMUX_GPIO72__FUNC_MSDC0_DAT1 (MTK_PIN_NO(72) | 1)
+
+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define PINMUX_GPIO73__FUNC_MSDC0_DAT2 (MTK_PIN_NO(73) | 1)
+
+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define PINMUX_GPIO74__FUNC_MSDC0_DAT3 (MTK_PIN_NO(74) | 1)
+
+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define PINMUX_GPIO75__FUNC_MSDC0_DAT4 (MTK_PIN_NO(75) | 1)
+
+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define PINMUX_GPIO76__FUNC_MSDC0_DAT5 (MTK_PIN_NO(76) | 1)
+
+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define PINMUX_GPIO77__FUNC_MSDC0_DAT6 (MTK_PIN_NO(77) | 1)
+
+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define PINMUX_GPIO78__FUNC_MSDC0_DAT7 (MTK_PIN_NO(78) | 1)
+
+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define PINMUX_GPIO79__FUNC_KPCOL0 (MTK_PIN_NO(79) | 1)
+
+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define PINMUX_GPIO80__FUNC_KPCOL1 (MTK_PIN_NO(80) | 1)
+#define PINMUX_GPIO80__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(80) | 2)
+#define PINMUX_GPIO80__FUNC_PWM0 (MTK_PIN_NO(80) | 3)
+#define PINMUX_GPIO80__FUNC_CLKM0 (MTK_PIN_NO(80) | 4)
+
+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define PINMUX_GPIO81__FUNC_KPROW0 (MTK_PIN_NO(81) | 1)
+#define PINMUX_GPIO81__FUNC_PWM1 (MTK_PIN_NO(81) | 3)
+#define PINMUX_GPIO81__FUNC_CLKM1 (MTK_PIN_NO(81) | 4)
+
+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define PINMUX_GPIO82__FUNC_KPROW1 (MTK_PIN_NO(82) | 1)
+#define PINMUX_GPIO82__FUNC_PWM2 (MTK_PIN_NO(82) | 3)
+#define PINMUX_GPIO82__FUNC_CLKM2 (MTK_PIN_NO(82) | 4)
+
+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define PINMUX_GPIO83__FUNC_AP_GOOD (MTK_PIN_NO(83) | 1)
+#define PINMUX_GPIO83__FUNC_GPS_PPS (MTK_PIN_NO(83) | 2)
+#define PINMUX_GPIO83__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(83) | 4)
+#define PINMUX_GPIO83__FUNC_DBG_MON_A28 (MTK_PIN_NO(83) | 7)
+
+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define PINMUX_GPIO84__FUNC_MSDC1_CLK (MTK_PIN_NO(84) | 1)
+#define PINMUX_GPIO84__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(84) | 2)
+#define PINMUX_GPIO84__FUNC_UDI_TCK (MTK_PIN_NO(84) | 4)
+#define PINMUX_GPIO84__FUNC_CONN_DSP_JCK (MTK_PIN_NO(84) | 5)
+#define PINMUX_GPIO84__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(84) | 6)
+#define PINMUX_GPIO84__FUNC_DFD_TCK_XI (MTK_PIN_NO(84) | 7)
+
+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define PINMUX_GPIO85__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1)
+#define PINMUX_GPIO85__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(85) | 2)
+#define PINMUX_GPIO85__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(85) | 3)
+#define PINMUX_GPIO85__FUNC_UDI_TMS (MTK_PIN_NO(85) | 4)
+#define PINMUX_GPIO85__FUNC_CONN_DSP_JMS (MTK_PIN_NO(85) | 5)
+#define PINMUX_GPIO85__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(85) | 6)
+#define PINMUX_GPIO85__FUNC_DFD_TMS (MTK_PIN_NO(85) | 7)
+
+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define PINMUX_GPIO86__FUNC_MSDC1_DAT0 (MTK_PIN_NO(86) | 1)
+#define PINMUX_GPIO86__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(86) | 2)
+#define PINMUX_GPIO86__FUNC_UDI_TDI (MTK_PIN_NO(86) | 4)
+#define PINMUX_GPIO86__FUNC_CONN_DSP_JDI (MTK_PIN_NO(86) | 5)
+#define PINMUX_GPIO86__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(86) | 6)
+#define PINMUX_GPIO86__FUNC_DFD_TDI (MTK_PIN_NO(86) | 7)
+
+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define PINMUX_GPIO87__FUNC_MSDC1_DAT1 (MTK_PIN_NO(87) | 1)
+#define PINMUX_GPIO87__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(87) | 2)
+#define PINMUX_GPIO87__FUNC_UDI_TDO (MTK_PIN_NO(87) | 4)
+#define PINMUX_GPIO87__FUNC_CONN_DSP_JDO (MTK_PIN_NO(87) | 5)
+#define PINMUX_GPIO87__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(87) | 6)
+#define PINMUX_GPIO87__FUNC_DFD_TDO (MTK_PIN_NO(87) | 7)
+
+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define PINMUX_GPIO88__FUNC_MSDC1_DAT2 (MTK_PIN_NO(88) | 1)
+#define PINMUX_GPIO88__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(88) | 2)
+#define PINMUX_GPIO88__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 3)
+#define PINMUX_GPIO88__FUNC_UDI_NTRST (MTK_PIN_NO(88) | 4)
+#define PINMUX_GPIO88__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(88) | 5)
+#define PINMUX_GPIO88__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(88) | 6)
+
+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define PINMUX_GPIO89__FUNC_MSDC1_DAT3 (MTK_PIN_NO(89) | 1)
+#define PINMUX_GPIO89__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(89) | 5)
+
+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define PINMUX_GPIO90__FUNC_IDDIG_P0 (MTK_PIN_NO(90) | 1)
+#define PINMUX_GPIO90__FUNC_PGD_HV_HSC_PWR4 (MTK_PIN_NO(90) | 4)
+#define PINMUX_GPIO90__FUNC_GDU_SUM_TROOP2_2 (MTK_PIN_NO(90) | 5)
+
+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define PINMUX_GPIO91__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(91) | 1)
+#define PINMUX_GPIO91__FUNC_PGD_HV_HSC_PWR5 (MTK_PIN_NO(91) | 4)
+#define PINMUX_GPIO91__FUNC_GDU_TROOPS_DET0 (MTK_PIN_NO(91) | 5)
+
+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define PINMUX_GPIO92__FUNC_VBUS_VALID_P0 (MTK_PIN_NO(92) | 1)
+#define PINMUX_GPIO92__FUNC_PGD_DA_EFUSE_RDY (MTK_PIN_NO(92) | 4)
+#define PINMUX_GPIO92__FUNC_GDU_TROOPS_DET1 (MTK_PIN_NO(92) | 5)
+
+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define PINMUX_GPIO93__FUNC_IDDIG_P1 (MTK_PIN_NO(93) | 1)
+#define PINMUX_GPIO93__FUNC_PWM0 (MTK_PIN_NO(93) | 2)
+#define PINMUX_GPIO93__FUNC_CLKM0 (MTK_PIN_NO(93) | 3)
+#define PINMUX_GPIO93__FUNC_PGD_DA_EFUSE_RDY_PRE (MTK_PIN_NO(93) | 4)
+#define PINMUX_GPIO93__FUNC_GDU_TROOPS_DET2 (MTK_PIN_NO(93) | 5)
+
+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define PINMUX_GPIO94__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(94) | 1)
+#define PINMUX_GPIO94__FUNC_PWM1 (MTK_PIN_NO(94) | 2)
+#define PINMUX_GPIO94__FUNC_CLKM1 (MTK_PIN_NO(94) | 3)
+#define PINMUX_GPIO94__FUNC_PGD_DA_PWRGD_RESET (MTK_PIN_NO(94) | 4)
+
+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define PINMUX_GPIO95__FUNC_VBUS_VALID_P1 (MTK_PIN_NO(95) | 1)
+#define PINMUX_GPIO95__FUNC_PWM2 (MTK_PIN_NO(95) | 2)
+#define PINMUX_GPIO95__FUNC_CLKM2 (MTK_PIN_NO(95) | 3)
+#define PINMUX_GPIO95__FUNC_PGD_DA_PWRGD_ENB (MTK_PIN_NO(95) | 4)
+
+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define PINMUX_GPIO96__FUNC_DSI_TE (MTK_PIN_NO(96) | 1)
+#define PINMUX_GPIO96__FUNC_DBG_MON_A29 (MTK_PIN_NO(96) | 7)
+
+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define PINMUX_GPIO97__FUNC_DISP_PWM (MTK_PIN_NO(97) | 1)
+#define PINMUX_GPIO97__FUNC_DBG_MON_A30 (MTK_PIN_NO(97) | 7)
+
+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define PINMUX_GPIO98__FUNC_LCM_RST (MTK_PIN_NO(98) | 1)
+
+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define PINMUX_GPIO99__FUNC_DPI_PCLK (MTK_PIN_NO(99) | 1)
+#define PINMUX_GPIO99__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(99) | 2)
+#define PINMUX_GPIO99__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(99) | 3)
+#define PINMUX_GPIO99__FUNC_ANT_SEL0 (MTK_PIN_NO(99) | 5)
+#define PINMUX_GPIO99__FUNC_TP_GPIO0_AO (MTK_PIN_NO(99) | 6)
+#define PINMUX_GPIO99__FUNC_PGD_LV_LSC_PWR0 (MTK_PIN_NO(99) | 7)
+
+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define PINMUX_GPIO100__FUNC_DPI_VSYNC (MTK_PIN_NO(100) | 1)
+#define PINMUX_GPIO100__FUNC_KPCOL2 (MTK_PIN_NO(100) | 2)
+#define PINMUX_GPIO100__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(100) | 3)
+#define PINMUX_GPIO100__FUNC_ANT_SEL1 (MTK_PIN_NO(100) | 5)
+#define PINMUX_GPIO100__FUNC_TP_GPIO1_AO (MTK_PIN_NO(100) | 6)
+#define PINMUX_GPIO100__FUNC_PGD_LV_LSC_PWR1 (MTK_PIN_NO(100) | 7)
+
+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define PINMUX_GPIO101__FUNC_DPI_HSYNC (MTK_PIN_NO(101) | 1)
+#define PINMUX_GPIO101__FUNC_KPROW2 (MTK_PIN_NO(101) | 2)
+#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(101) | 3)
+#define PINMUX_GPIO101__FUNC_ANT_SEL2 (MTK_PIN_NO(101) | 5)
+#define PINMUX_GPIO101__FUNC_TP_GPIO2_AO (MTK_PIN_NO(101) | 6)
+#define PINMUX_GPIO101__FUNC_PGD_LV_LSC_PWR2 (MTK_PIN_NO(101) | 7)
+
+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define PINMUX_GPIO102__FUNC_DPI_DE (MTK_PIN_NO(102) | 1)
+#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(102) | 3)
+#define PINMUX_GPIO102__FUNC_ANT_SEL3 (MTK_PIN_NO(102) | 5)
+#define PINMUX_GPIO102__FUNC_TP_GPIO3_AO (MTK_PIN_NO(102) | 6)
+#define PINMUX_GPIO102__FUNC_PGD_LV_LSC_PWR3 (MTK_PIN_NO(102) | 7)
+
+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define PINMUX_GPIO103__FUNC_DPI_DATA0 (MTK_PIN_NO(103) | 1)
+#define PINMUX_GPIO103__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(103) | 3)
+#define PINMUX_GPIO103__FUNC_CLKM0 (MTK_PIN_NO(103) | 4)
+#define PINMUX_GPIO103__FUNC_ANT_SEL4 (MTK_PIN_NO(103) | 5)
+#define PINMUX_GPIO103__FUNC_TP_GPIO4_AO (MTK_PIN_NO(103) | 6)
+#define PINMUX_GPIO103__FUNC_PGD_LV_LSC_PWR4 (MTK_PIN_NO(103) | 7)
+
+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define PINMUX_GPIO104__FUNC_DPI_DATA1 (MTK_PIN_NO(104) | 1)
+#define PINMUX_GPIO104__FUNC_GPS_PPS (MTK_PIN_NO(104) | 2)
+#define PINMUX_GPIO104__FUNC_UCTS2 (MTK_PIN_NO(104) | 3)
+#define PINMUX_GPIO104__FUNC_CLKM1 (MTK_PIN_NO(104) | 4)
+#define PINMUX_GPIO104__FUNC_ANT_SEL5 (MTK_PIN_NO(104) | 5)
+#define PINMUX_GPIO104__FUNC_TP_GPIO5_AO (MTK_PIN_NO(104) | 6)
+#define PINMUX_GPIO104__FUNC_PGD_LV_LSC_PWR5 (MTK_PIN_NO(104) | 7)
+
+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define PINMUX_GPIO105__FUNC_DPI_DATA2 (MTK_PIN_NO(105) | 1)
+#define PINMUX_GPIO105__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(105) | 2)
+#define PINMUX_GPIO105__FUNC_URTS2 (MTK_PIN_NO(105) | 3)
+#define PINMUX_GPIO105__FUNC_CLKM2 (MTK_PIN_NO(105) | 4)
+#define PINMUX_GPIO105__FUNC_ANT_SEL6 (MTK_PIN_NO(105) | 5)
+#define PINMUX_GPIO105__FUNC_TP_GPIO6_AO (MTK_PIN_NO(105) | 6)
+#define PINMUX_GPIO105__FUNC_PGD_LV_HSC_PWR0 (MTK_PIN_NO(105) | 7)
+
+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define PINMUX_GPIO106__FUNC_DPI_DATA3 (MTK_PIN_NO(106) | 1)
+#define PINMUX_GPIO106__FUNC_TP_UTXD1_AO (MTK_PIN_NO(106) | 2)
+#define PINMUX_GPIO106__FUNC_UTXD2 (MTK_PIN_NO(106) | 3)
+#define PINMUX_GPIO106__FUNC_PWM0 (MTK_PIN_NO(106) | 4)
+#define PINMUX_GPIO106__FUNC_ANT_SEL7 (MTK_PIN_NO(106) | 5)
+#define PINMUX_GPIO106__FUNC_TP_GPIO7_AO (MTK_PIN_NO(106) | 6)
+#define PINMUX_GPIO106__FUNC_PGD_LV_HSC_PWR1 (MTK_PIN_NO(106) | 7)
+
+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define PINMUX_GPIO107__FUNC_DPI_DATA4 (MTK_PIN_NO(107) | 1)
+#define PINMUX_GPIO107__FUNC_TP_URXD1_AO (MTK_PIN_NO(107) | 2)
+#define PINMUX_GPIO107__FUNC_URXD2 (MTK_PIN_NO(107) | 3)
+#define PINMUX_GPIO107__FUNC_PWM1 (MTK_PIN_NO(107) | 4)
+#define PINMUX_GPIO107__FUNC_GDU_SUM_TROOP0_0 (MTK_PIN_NO(107) | 6)
+#define PINMUX_GPIO107__FUNC_PGD_LV_HSC_PWR2 (MTK_PIN_NO(107) | 7)
+
+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define PINMUX_GPIO108__FUNC_DPI_DATA5 (MTK_PIN_NO(108) | 1)
+#define PINMUX_GPIO108__FUNC_TP_UCTS1_AO (MTK_PIN_NO(108) | 2)
+#define PINMUX_GPIO108__FUNC_UCTS0 (MTK_PIN_NO(108) | 3)
+#define PINMUX_GPIO108__FUNC_PWM2 (MTK_PIN_NO(108) | 4)
+#define PINMUX_GPIO108__FUNC_GDU_SUM_TROOP0_1 (MTK_PIN_NO(108) | 6)
+#define PINMUX_GPIO108__FUNC_PGD_LV_HSC_PWR3 (MTK_PIN_NO(108) | 7)
+
+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define PINMUX_GPIO109__FUNC_DPI_DATA6 (MTK_PIN_NO(109) | 1)
+#define PINMUX_GPIO109__FUNC_TP_URTS1_AO (MTK_PIN_NO(109) | 2)
+#define PINMUX_GPIO109__FUNC_URTS0 (MTK_PIN_NO(109) | 3)
+#define PINMUX_GPIO109__FUNC_I2S0_DI (MTK_PIN_NO(109) | 4)
+#define PINMUX_GPIO109__FUNC_I2S2_DI (MTK_PIN_NO(109) | 5)
+#define PINMUX_GPIO109__FUNC_GDU_SUM_TROOP0_2 (MTK_PIN_NO(109) | 6)
+#define PINMUX_GPIO109__FUNC_PGD_LV_HSC_PWR4 (MTK_PIN_NO(109) | 7)
+
+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define PINMUX_GPIO110__FUNC_DPI_DATA7 (MTK_PIN_NO(110) | 1)
+#define PINMUX_GPIO110__FUNC_TP_UCTS2_AO (MTK_PIN_NO(110) | 2)
+#define PINMUX_GPIO110__FUNC_UCTS1 (MTK_PIN_NO(110) | 3)
+#define PINMUX_GPIO110__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 4)
+#define PINMUX_GPIO110__FUNC_I2S1_BCK (MTK_PIN_NO(110) | 5)
+#define PINMUX_GPIO110__FUNC_GDU_SUM_TROOP1_0 (MTK_PIN_NO(110) | 6)
+#define PINMUX_GPIO110__FUNC_PGD_LV_HSC_PWR5 (MTK_PIN_NO(110) | 7)
+
+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define PINMUX_GPIO111__FUNC_DPI_DATA8 (MTK_PIN_NO(111) | 1)
+#define PINMUX_GPIO111__FUNC_TP_URTS2_AO (MTK_PIN_NO(111) | 2)
+#define PINMUX_GPIO111__FUNC_URTS1 (MTK_PIN_NO(111) | 3)
+#define PINMUX_GPIO111__FUNC_I2S3_MCK (MTK_PIN_NO(111) | 4)
+#define PINMUX_GPIO111__FUNC_I2S1_MCK (MTK_PIN_NO(111) | 5)
+#define PINMUX_GPIO111__FUNC_GDU_SUM_TROOP1_1 (MTK_PIN_NO(111) | 6)
+#define PINMUX_GPIO111__FUNC_PGD_HV_HSC_PWR0 (MTK_PIN_NO(111) | 7)
+
+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define PINMUX_GPIO112__FUNC_DPI_DATA9 (MTK_PIN_NO(112) | 1)
+#define PINMUX_GPIO112__FUNC_TP_URXD2_AO (MTK_PIN_NO(112) | 2)
+#define PINMUX_GPIO112__FUNC_URXD1 (MTK_PIN_NO(112) | 3)
+#define PINMUX_GPIO112__FUNC_I2S3_LRCK (MTK_PIN_NO(112) | 4)
+#define PINMUX_GPIO112__FUNC_I2S1_LRCK (MTK_PIN_NO(112) | 5)
+#define PINMUX_GPIO112__FUNC_GDU_SUM_TROOP1_2 (MTK_PIN_NO(112) | 6)
+#define PINMUX_GPIO112__FUNC_PGD_HV_HSC_PWR1 (MTK_PIN_NO(112) | 7)
+
+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define PINMUX_GPIO113__FUNC_DPI_DATA10 (MTK_PIN_NO(113) | 1)
+#define PINMUX_GPIO113__FUNC_TP_UTXD2_AO (MTK_PIN_NO(113) | 2)
+#define PINMUX_GPIO113__FUNC_UTXD1 (MTK_PIN_NO(113) | 3)
+#define PINMUX_GPIO113__FUNC_I2S3_DO (MTK_PIN_NO(113) | 4)
+#define PINMUX_GPIO113__FUNC_I2S1_DO (MTK_PIN_NO(113) | 5)
+#define PINMUX_GPIO113__FUNC_GDU_SUM_TROOP2_0 (MTK_PIN_NO(113) | 6)
+#define PINMUX_GPIO113__FUNC_PGD_HV_HSC_PWR2 (MTK_PIN_NO(113) | 7)
+
+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define PINMUX_GPIO114__FUNC_DPI_DATA11 (MTK_PIN_NO(114) | 1)
+#define PINMUX_GPIO114__FUNC_GDU_SUM_TROOP2_1 (MTK_PIN_NO(114) | 6)
+#define PINMUX_GPIO114__FUNC_PGD_HV_HSC_PWR3 (MTK_PIN_NO(114) | 7)
+
+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define PINMUX_GPIO115__FUNC_PCM_CLK (MTK_PIN_NO(115) | 1)
+#define PINMUX_GPIO115__FUNC_I2S0_BCK (MTK_PIN_NO(115) | 2)
+#define PINMUX_GPIO115__FUNC_I2S2_BCK (MTK_PIN_NO(115) | 3)
+
+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define PINMUX_GPIO116__FUNC_PCM_SYNC (MTK_PIN_NO(116) | 1)
+#define PINMUX_GPIO116__FUNC_I2S0_LRCK (MTK_PIN_NO(116) | 2)
+#define PINMUX_GPIO116__FUNC_I2S2_LRCK (MTK_PIN_NO(116) | 3)
+
+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define PINMUX_GPIO117__FUNC_PCM_DI (MTK_PIN_NO(117) | 1)
+#define PINMUX_GPIO117__FUNC_I2S0_DI (MTK_PIN_NO(117) | 2)
+#define PINMUX_GPIO117__FUNC_I2S2_DI (MTK_PIN_NO(117) | 3)
+
+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define PINMUX_GPIO118__FUNC_PCM_DO (MTK_PIN_NO(118) | 1)
+#define PINMUX_GPIO118__FUNC_I2S0_MCK (MTK_PIN_NO(118) | 2)
+#define PINMUX_GPIO118__FUNC_I2S2_MCK (MTK_PIN_NO(118) | 3)
+#define PINMUX_GPIO118__FUNC_I2S3_DO (MTK_PIN_NO(118) | 4)
+#define PINMUX_GPIO118__FUNC_I2S1_DO (MTK_PIN_NO(118) | 5)
+
+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define PINMUX_GPIO119__FUNC_JTMS_SEL1 (MTK_PIN_NO(119) | 1)
+#define PINMUX_GPIO119__FUNC_UDI_TMS (MTK_PIN_NO(119) | 2)
+#define PINMUX_GPIO119__FUNC_DFD_TMS (MTK_PIN_NO(119) | 3)
+#define PINMUX_GPIO119__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(119) | 4)
+#define PINMUX_GPIO119__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(119) | 5)
+#define PINMUX_GPIO119__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(119) | 6)
+
+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define PINMUX_GPIO120__FUNC_JTCK_SEL1 (MTK_PIN_NO(120) | 1)
+#define PINMUX_GPIO120__FUNC_UDI_TCK (MTK_PIN_NO(120) | 2)
+#define PINMUX_GPIO120__FUNC_DFD_TCK_XI (MTK_PIN_NO(120) | 3)
+#define PINMUX_GPIO120__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(120) | 4)
+#define PINMUX_GPIO120__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(120) | 5)
+#define PINMUX_GPIO120__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(120) | 6)
+
+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define PINMUX_GPIO121__FUNC_JTDI_SEL1 (MTK_PIN_NO(121) | 1)
+#define PINMUX_GPIO121__FUNC_UDI_TDI (MTK_PIN_NO(121) | 2)
+#define PINMUX_GPIO121__FUNC_DFD_TDI (MTK_PIN_NO(121) | 3)
+#define PINMUX_GPIO121__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(121) | 4)
+#define PINMUX_GPIO121__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(121) | 5)
+#define PINMUX_GPIO121__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(121) | 6)
+
+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define PINMUX_GPIO122__FUNC_JTDO_SEL1 (MTK_PIN_NO(122) | 1)
+#define PINMUX_GPIO122__FUNC_UDI_TDO (MTK_PIN_NO(122) | 2)
+#define PINMUX_GPIO122__FUNC_DFD_TDO (MTK_PIN_NO(122) | 3)
+#define PINMUX_GPIO122__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(122) | 4)
+#define PINMUX_GPIO122__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(122) | 5)
+#define PINMUX_GPIO122__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(122) | 6)
+
+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define PINMUX_GPIO123__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(123) | 1)
+#define PINMUX_GPIO123__FUNC_UDI_NTRST (MTK_PIN_NO(123) | 2)
+#define PINMUX_GPIO123__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(123) | 4)
+#define PINMUX_GPIO123__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(123) | 5)
+#define PINMUX_GPIO123__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(123) | 6)
+
+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define PINMUX_GPIO124__FUNC_CMMCLK0 (MTK_PIN_NO(124) | 1)
+#define PINMUX_GPIO124__FUNC_CLKM0 (MTK_PIN_NO(124) | 2)
+#define PINMUX_GPIO124__FUNC_PWM0 (MTK_PIN_NO(124) | 3)
+
+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define PINMUX_GPIO125__FUNC_CMMCLK1 (MTK_PIN_NO(125) | 1)
+#define PINMUX_GPIO125__FUNC_CLKM1 (MTK_PIN_NO(125) | 2)
+#define PINMUX_GPIO125__FUNC_PWM1 (MTK_PIN_NO(125) | 3)
+#define PINMUX_GPIO125__FUNC_DBG_MON_B0 (MTK_PIN_NO(125) | 7)
+
+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define PINMUX_GPIO126__FUNC_CMMCLK2 (MTK_PIN_NO(126) | 1)
+#define PINMUX_GPIO126__FUNC_CLKM2 (MTK_PIN_NO(126) | 2)
+#define PINMUX_GPIO126__FUNC_PWM2 (MTK_PIN_NO(126) | 3)
+#define PINMUX_GPIO126__FUNC_DBG_MON_B1 (MTK_PIN_NO(126) | 7)
+
+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define PINMUX_GPIO127__FUNC_SCL0 (MTK_PIN_NO(127) | 1)
+#define PINMUX_GPIO127__FUNC_SCP_SCL0 (MTK_PIN_NO(127) | 4)
+#define PINMUX_GPIO127__FUNC_SCP_SCL1 (MTK_PIN_NO(127) | 5)
+
+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define PINMUX_GPIO128__FUNC_SDA0 (MTK_PIN_NO(128) | 1)
+#define PINMUX_GPIO128__FUNC_SCP_SDA0 (MTK_PIN_NO(128) | 4)
+#define PINMUX_GPIO128__FUNC_SCP_SDA1 (MTK_PIN_NO(128) | 5)
+
+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define PINMUX_GPIO129__FUNC_SCL1 (MTK_PIN_NO(129) | 1)
+#define PINMUX_GPIO129__FUNC_SCP_SCL0 (MTK_PIN_NO(129) | 4)
+#define PINMUX_GPIO129__FUNC_SCP_SCL1 (MTK_PIN_NO(129) | 5)
+#define PINMUX_GPIO129__FUNC_DBG_MON_B4 (MTK_PIN_NO(129) | 7)
+
+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define PINMUX_GPIO130__FUNC_SDA1 (MTK_PIN_NO(130) | 1)
+#define PINMUX_GPIO130__FUNC_SCP_SDA0 (MTK_PIN_NO(130) | 4)
+#define PINMUX_GPIO130__FUNC_SCP_SDA1 (MTK_PIN_NO(130) | 5)
+#define PINMUX_GPIO130__FUNC_DBG_MON_B5 (MTK_PIN_NO(130) | 7)
+
+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define PINMUX_GPIO131__FUNC_SCL2 (MTK_PIN_NO(131) | 1)
+#define PINMUX_GPIO131__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(131) | 2)
+#define PINMUX_GPIO131__FUNC_CONN_UART0_TXD (MTK_PIN_NO(131) | 3)
+#define PINMUX_GPIO131__FUNC_SCP_SCL0 (MTK_PIN_NO(131) | 4)
+#define PINMUX_GPIO131__FUNC_SCP_SCL1 (MTK_PIN_NO(131) | 5)
+#define PINMUX_GPIO131__FUNC_DBG_MON_B6 (MTK_PIN_NO(131) | 7)
+
+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define PINMUX_GPIO132__FUNC_SDA2 (MTK_PIN_NO(132) | 1)
+#define PINMUX_GPIO132__FUNC_SSPM_URXD_AO (MTK_PIN_NO(132) | 2)
+#define PINMUX_GPIO132__FUNC_CONN_UART0_RXD (MTK_PIN_NO(132) | 3)
+#define PINMUX_GPIO132__FUNC_SCP_SDA0 (MTK_PIN_NO(132) | 4)
+#define PINMUX_GPIO132__FUNC_SCP_SDA1 (MTK_PIN_NO(132) | 5)
+#define PINMUX_GPIO132__FUNC_DBG_MON_B7 (MTK_PIN_NO(132) | 7)
+
+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define PINMUX_GPIO133__FUNC_SCL3 (MTK_PIN_NO(133) | 1)
+#define PINMUX_GPIO133__FUNC_SCP_SCL0 (MTK_PIN_NO(133) | 4)
+#define PINMUX_GPIO133__FUNC_SCP_SCL1 (MTK_PIN_NO(133) | 5)
+#define PINMUX_GPIO133__FUNC_DBG_MON_B8 (MTK_PIN_NO(133) | 7)
+
+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define PINMUX_GPIO134__FUNC_SDA3 (MTK_PIN_NO(134) | 1)
+#define PINMUX_GPIO134__FUNC_GPS_PPS (MTK_PIN_NO(134) | 3)
+#define PINMUX_GPIO134__FUNC_SCP_SDA0 (MTK_PIN_NO(134) | 4)
+#define PINMUX_GPIO134__FUNC_SCP_SDA1 (MTK_PIN_NO(134) | 5)
+#define PINMUX_GPIO134__FUNC_DBG_MON_B9 (MTK_PIN_NO(134) | 7)
+
+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define PINMUX_GPIO135__FUNC_SCL4 (MTK_PIN_NO(135) | 1)
+#define PINMUX_GPIO135__FUNC_TP_UTXD1_AO (MTK_PIN_NO(135) | 2)
+#define PINMUX_GPIO135__FUNC_UTXD1 (MTK_PIN_NO(135) | 3)
+#define PINMUX_GPIO135__FUNC_SCP_SCL0 (MTK_PIN_NO(135) | 4)
+#define PINMUX_GPIO135__FUNC_SCP_SCL1 (MTK_PIN_NO(135) | 5)
+#define PINMUX_GPIO135__FUNC_DBG_MON_B10 (MTK_PIN_NO(135) | 7)
+
+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define PINMUX_GPIO136__FUNC_SDA4 (MTK_PIN_NO(136) | 1)
+#define PINMUX_GPIO136__FUNC_TP_URXD1_AO (MTK_PIN_NO(136) | 2)
+#define PINMUX_GPIO136__FUNC_URXD1 (MTK_PIN_NO(136) | 3)
+#define PINMUX_GPIO136__FUNC_SCP_SDA0 (MTK_PIN_NO(136) | 4)
+#define PINMUX_GPIO136__FUNC_SCP_SDA1 (MTK_PIN_NO(136) | 5)
+#define PINMUX_GPIO136__FUNC_DBG_MON_B11 (MTK_PIN_NO(136) | 7)
+
+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define PINMUX_GPIO137__FUNC_SCL5 (MTK_PIN_NO(137) | 1)
+#define PINMUX_GPIO137__FUNC_UTXD2 (MTK_PIN_NO(137) | 2)
+#define PINMUX_GPIO137__FUNC_UCTS1 (MTK_PIN_NO(137) | 3)
+#define PINMUX_GPIO137__FUNC_SCP_SCL0 (MTK_PIN_NO(137) | 4)
+#define PINMUX_GPIO137__FUNC_SCP_SCL1 (MTK_PIN_NO(137) | 5)
+
+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define PINMUX_GPIO138__FUNC_SDA5 (MTK_PIN_NO(138) | 1)
+#define PINMUX_GPIO138__FUNC_URXD2 (MTK_PIN_NO(138) | 2)
+#define PINMUX_GPIO138__FUNC_URTS1 (MTK_PIN_NO(138) | 3)
+#define PINMUX_GPIO138__FUNC_SCP_SDA0 (MTK_PIN_NO(138) | 4)
+#define PINMUX_GPIO138__FUNC_SCP_SDA1 (MTK_PIN_NO(138) | 5)
+
+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define PINMUX_GPIO139__FUNC_SCL6 (MTK_PIN_NO(139) | 1)
+#define PINMUX_GPIO139__FUNC_UTXD1 (MTK_PIN_NO(139) | 2)
+#define PINMUX_GPIO139__FUNC_TP_UTXD1_AO (MTK_PIN_NO(139) | 3)
+#define PINMUX_GPIO139__FUNC_SCP_SCL0 (MTK_PIN_NO(139) | 4)
+#define PINMUX_GPIO139__FUNC_SCP_SCL1 (MTK_PIN_NO(139) | 5)
+#define PINMUX_GPIO139__FUNC_DBG_MON_B12 (MTK_PIN_NO(139) | 7)
+
+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define PINMUX_GPIO140__FUNC_SDA6 (MTK_PIN_NO(140) | 1)
+#define PINMUX_GPIO140__FUNC_URXD1 (MTK_PIN_NO(140) | 2)
+#define PINMUX_GPIO140__FUNC_TP_URXD1_AO (MTK_PIN_NO(140) | 3)
+#define PINMUX_GPIO140__FUNC_SCP_SDA0 (MTK_PIN_NO(140) | 4)
+#define PINMUX_GPIO140__FUNC_SCP_SDA1 (MTK_PIN_NO(140) | 5)
+#define PINMUX_GPIO140__FUNC_DBG_MON_B13 (MTK_PIN_NO(140) | 7)
+
+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define PINMUX_GPIO141__FUNC_SCL7 (MTK_PIN_NO(141) | 1)
+#define PINMUX_GPIO141__FUNC_URTS0 (MTK_PIN_NO(141) | 2)
+#define PINMUX_GPIO141__FUNC_TP_URTS1_AO (MTK_PIN_NO(141) | 3)
+#define PINMUX_GPIO141__FUNC_SCP_SCL0 (MTK_PIN_NO(141) | 4)
+#define PINMUX_GPIO141__FUNC_SCP_SCL1 (MTK_PIN_NO(141) | 5)
+#define PINMUX_GPIO141__FUNC_UDI_TCK (MTK_PIN_NO(141) | 6)
+#define PINMUX_GPIO141__FUNC_DBG_MON_B14 (MTK_PIN_NO(141) | 7)
+
+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define PINMUX_GPIO142__FUNC_SDA7 (MTK_PIN_NO(142) | 1)
+#define PINMUX_GPIO142__FUNC_UCTS0 (MTK_PIN_NO(142) | 2)
+#define PINMUX_GPIO142__FUNC_TP_UCTS1_AO (MTK_PIN_NO(142) | 3)
+#define PINMUX_GPIO142__FUNC_SCP_SDA0 (MTK_PIN_NO(142) | 4)
+#define PINMUX_GPIO142__FUNC_SCP_SDA1 (MTK_PIN_NO(142) | 5)
+
+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define PINMUX_GPIO143__FUNC_SCL8 (MTK_PIN_NO(143) | 1)
+#define PINMUX_GPIO143__FUNC_SCP_SCL0 (MTK_PIN_NO(143) | 4)
+#define PINMUX_GPIO143__FUNC_SCP_SCL1 (MTK_PIN_NO(143) | 5)
+#define PINMUX_GPIO143__FUNC_DBG_MON_B16 (MTK_PIN_NO(143) | 7)
+
+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define PINMUX_GPIO144__FUNC_SDA8 (MTK_PIN_NO(144) | 1)
+#define PINMUX_GPIO144__FUNC_SCP_SDA0 (MTK_PIN_NO(144) | 4)
+#define PINMUX_GPIO144__FUNC_SCP_SDA1 (MTK_PIN_NO(144) | 5)
+#define PINMUX_GPIO144__FUNC_DBG_MON_B17 (MTK_PIN_NO(144) | 7)
+
+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define PINMUX_GPIO145__FUNC_SCL9 (MTK_PIN_NO(145) | 1)
+#define PINMUX_GPIO145__FUNC_CMVREF1 (MTK_PIN_NO(145) | 2)
+#define PINMUX_GPIO145__FUNC_GPS_PPS (MTK_PIN_NO(145) | 3)
+#define PINMUX_GPIO145__FUNC_SCP_SCL0 (MTK_PIN_NO(145) | 4)
+#define PINMUX_GPIO145__FUNC_SCP_SCL1 (MTK_PIN_NO(145) | 5)
+#define PINMUX_GPIO145__FUNC_DBG_MON_B18 (MTK_PIN_NO(145) | 7)
+
+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define PINMUX_GPIO146__FUNC_SDA9 (MTK_PIN_NO(146) | 1)
+#define PINMUX_GPIO146__FUNC_CMVREF0 (MTK_PIN_NO(146) | 2)
+#define PINMUX_GPIO146__FUNC_SCP_SDA0 (MTK_PIN_NO(146) | 4)
+#define PINMUX_GPIO146__FUNC_SCP_SDA1 (MTK_PIN_NO(146) | 5)
+#define PINMUX_GPIO146__FUNC_DBG_MON_B19 (MTK_PIN_NO(146) | 7)
+
+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define PINMUX_GPIO147__FUNC_CMFLASH0 (MTK_PIN_NO(147) | 1)
+#define PINMUX_GPIO147__FUNC_LVTS_SDI (MTK_PIN_NO(147) | 2)
+#define PINMUX_GPIO147__FUNC_DPI_DATA12 (MTK_PIN_NO(147) | 3)
+#define PINMUX_GPIO147__FUNC_TP_GPIO0_AO (MTK_PIN_NO(147) | 4)
+#define PINMUX_GPIO147__FUNC_ANT_SEL3 (MTK_PIN_NO(147) | 5)
+#define PINMUX_GPIO147__FUNC_DFD_TCK_XI (MTK_PIN_NO(147) | 6)
+#define PINMUX_GPIO147__FUNC_DBG_MON_B20 (MTK_PIN_NO(147) | 7)
+
+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define PINMUX_GPIO148__FUNC_CMFLASH1 (MTK_PIN_NO(148) | 1)
+#define PINMUX_GPIO148__FUNC_LVTS_SCF (MTK_PIN_NO(148) | 2)
+#define PINMUX_GPIO148__FUNC_DPI_DATA13 (MTK_PIN_NO(148) | 3)
+#define PINMUX_GPIO148__FUNC_TP_GPIO1_AO (MTK_PIN_NO(148) | 4)
+#define PINMUX_GPIO148__FUNC_ANT_SEL4 (MTK_PIN_NO(148) | 5)
+#define PINMUX_GPIO148__FUNC_DFD_TMS (MTK_PIN_NO(148) | 6)
+#define PINMUX_GPIO148__FUNC_DBG_MON_B21 (MTK_PIN_NO(148) | 7)
+
+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define PINMUX_GPIO149__FUNC_CMFLASH2 (MTK_PIN_NO(149) | 1)
+#define PINMUX_GPIO149__FUNC_CLKM0 (MTK_PIN_NO(149) | 2)
+#define PINMUX_GPIO149__FUNC_DPI_DATA14 (MTK_PIN_NO(149) | 3)
+#define PINMUX_GPIO149__FUNC_TP_GPIO2_AO (MTK_PIN_NO(149) | 4)
+#define PINMUX_GPIO149__FUNC_ANT_SEL5 (MTK_PIN_NO(149) | 5)
+#define PINMUX_GPIO149__FUNC_DFD_TDI (MTK_PIN_NO(149) | 6)
+#define PINMUX_GPIO149__FUNC_DBG_MON_B22 (MTK_PIN_NO(149) | 7)
+
+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define PINMUX_GPIO150__FUNC_CLKM1 (MTK_PIN_NO(150) | 2)
+#define PINMUX_GPIO150__FUNC_DPI_DATA15 (MTK_PIN_NO(150) | 3)
+#define PINMUX_GPIO150__FUNC_TP_GPIO3_AO (MTK_PIN_NO(150) | 4)
+#define PINMUX_GPIO150__FUNC_ANT_SEL6 (MTK_PIN_NO(150) | 5)
+#define PINMUX_GPIO150__FUNC_DFD_TDO (MTK_PIN_NO(150) | 6)
+#define PINMUX_GPIO150__FUNC_DBG_MON_B23 (MTK_PIN_NO(150) | 7)
+
+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define PINMUX_GPIO151__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(151) | 1)
+#define PINMUX_GPIO151__FUNC_CLKM2 (MTK_PIN_NO(151) | 2)
+#define PINMUX_GPIO151__FUNC_DPI_DATA16 (MTK_PIN_NO(151) | 3)
+#define PINMUX_GPIO151__FUNC_TP_GPIO4_AO (MTK_PIN_NO(151) | 4)
+#define PINMUX_GPIO151__FUNC_ANT_SEL7 (MTK_PIN_NO(151) | 5)
+#define PINMUX_GPIO151__FUNC_UDI_TMS (MTK_PIN_NO(151) | 6)
+#define PINMUX_GPIO151__FUNC_DBG_MON_B24 (MTK_PIN_NO(151) | 7)
+
+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define PINMUX_GPIO152__FUNC_CLKM3 (MTK_PIN_NO(152) | 2)
+#define PINMUX_GPIO152__FUNC_DPI_DATA17 (MTK_PIN_NO(152) | 3)
+#define PINMUX_GPIO152__FUNC_TP_GPIO5_AO (MTK_PIN_NO(152) | 4)
+
+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define PINMUX_GPIO153__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(153) | 1)
+#define PINMUX_GPIO153__FUNC_DPI_DATA18 (MTK_PIN_NO(153) | 3)
+#define PINMUX_GPIO153__FUNC_TP_GPIO6_AO (MTK_PIN_NO(153) | 4)
+#define PINMUX_GPIO153__FUNC_UDI_TDI (MTK_PIN_NO(153) | 6)
+#define PINMUX_GPIO153__FUNC_DBG_MON_B26 (MTK_PIN_NO(153) | 7)
+
+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define PINMUX_GPIO154__FUNC_PWM0 (MTK_PIN_NO(154) | 1)
+#define PINMUX_GPIO154__FUNC_CMVREF2 (MTK_PIN_NO(154) | 2)
+#define PINMUX_GPIO154__FUNC_DPI_DATA19 (MTK_PIN_NO(154) | 3)
+#define PINMUX_GPIO154__FUNC_TP_GPIO7_AO (MTK_PIN_NO(154) | 4)
+#define PINMUX_GPIO154__FUNC_UDI_TDO (MTK_PIN_NO(154) | 6)
+#define PINMUX_GPIO154__FUNC_DBG_MON_B27 (MTK_PIN_NO(154) | 7)
+
+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define PINMUX_GPIO155__FUNC_PWM1 (MTK_PIN_NO(155) | 1)
+#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 2)
+#define PINMUX_GPIO155__FUNC_DPI_DATA20 (MTK_PIN_NO(155) | 3)
+#define PINMUX_GPIO155__FUNC_UDI_NTRST (MTK_PIN_NO(155) | 6)
+#define PINMUX_GPIO155__FUNC_DBG_MON_B28 (MTK_PIN_NO(155) | 7)
+
+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define PINMUX_GPIO156__FUNC_PWM2 (MTK_PIN_NO(156) | 1)
+#define PINMUX_GPIO156__FUNC_CMVREF0 (MTK_PIN_NO(156) | 2)
+#define PINMUX_GPIO156__FUNC_DPI_DATA21 (MTK_PIN_NO(156) | 3)
+
+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define PINMUX_GPIO157__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(157) | 1)
+
+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define PINMUX_GPIO158__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(158) | 1)
+
+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define PINMUX_GPIO159__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(159) | 1)
+#define PINMUX_GPIO159__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(159) | 2)
+
+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define PINMUX_GPIO160__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(160) | 1)
+#define PINMUX_GPIO160__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(160) | 2)
+
+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define PINMUX_GPIO161__FUNC_SRCLKENA0 (MTK_PIN_NO(161) | 1)
+
+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define PINMUX_GPIO162__FUNC_SRCLKENA1 (MTK_PIN_NO(162) | 1)
+#define PINMUX_GPIO162__FUNC_DBG_MON_A31 (MTK_PIN_NO(162) | 7)
+
+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define PINMUX_GPIO163__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(163) | 1)
+#define PINMUX_GPIO163__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(163) | 2)
+
+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define PINMUX_GPIO164__FUNC_RTC32K_CK (MTK_PIN_NO(164) | 1)
+
+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+#define PINMUX_GPIO165__FUNC_WATCHDOG (MTK_PIN_NO(165) | 1)
+
+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+#define PINMUX_GPIO166__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(166) | 1)
+#define PINMUX_GPIO166__FUNC_AUD_CLK_MISO (MTK_PIN_NO(166) | 2)
+#define PINMUX_GPIO166__FUNC_I2S1_MCK (MTK_PIN_NO(166) | 3)
+
+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+#define PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(167) | 1)
+#define PINMUX_GPIO167__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(167) | 2)
+#define PINMUX_GPIO167__FUNC_I2S1_BCK (MTK_PIN_NO(167) | 3)
+
+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+#define PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(168) | 1)
+#define PINMUX_GPIO168__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(168) | 2)
+#define PINMUX_GPIO168__FUNC_I2S1_LRCK (MTK_PIN_NO(168) | 3)
+
+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(169) | 1)
+#define PINMUX_GPIO169__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(169) | 2)
+#define PINMUX_GPIO169__FUNC_I2S1_DO (MTK_PIN_NO(169) | 3)
+
+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define PINMUX_GPIO170__FUNC_AUD_CLK_MISO (MTK_PIN_NO(170) | 1)
+#define PINMUX_GPIO170__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(170) | 2)
+#define PINMUX_GPIO170__FUNC_I2S2_MCK (MTK_PIN_NO(170) | 3)
+
+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define PINMUX_GPIO171__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(171) | 1)
+#define PINMUX_GPIO171__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(171) | 2)
+#define PINMUX_GPIO171__FUNC_I2S2_BCK (MTK_PIN_NO(171) | 3)
+
+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define PINMUX_GPIO172__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(172) | 1)
+#define PINMUX_GPIO172__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(172) | 2)
+#define PINMUX_GPIO172__FUNC_I2S2_LRCK (MTK_PIN_NO(172) | 3)
+#define PINMUX_GPIO172__FUNC_VOW_DAT_MISO (MTK_PIN_NO(172) | 4)
+
+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define PINMUX_GPIO173__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(173) | 1)
+#define PINMUX_GPIO173__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(173) | 2)
+#define PINMUX_GPIO173__FUNC_I2S2_DI (MTK_PIN_NO(173) | 3)
+#define PINMUX_GPIO173__FUNC_VOW_CLK_MISO (MTK_PIN_NO(173) | 4)
+
+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define PINMUX_GPIO174__FUNC_CONN_TOP_CLK (MTK_PIN_NO(174) | 1)
+#define PINMUX_GPIO174__FUNC_AUXIF_CLK (MTK_PIN_NO(174) | 2)
+#define PINMUX_GPIO174__FUNC_DFD_TCK_XI (MTK_PIN_NO(174) | 3)
+#define PINMUX_GPIO174__FUNC_DBG_MON_B3 (MTK_PIN_NO(174) | 7)
+
+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define PINMUX_GPIO175__FUNC_CONN_TOP_DATA (MTK_PIN_NO(175) | 1)
+#define PINMUX_GPIO175__FUNC_AUXIF_ST (MTK_PIN_NO(175) | 2)
+#define PINMUX_GPIO175__FUNC_DFD_TMS (MTK_PIN_NO(175) | 3)
+#define PINMUX_GPIO175__FUNC_DBG_MON_B15 (MTK_PIN_NO(175) | 7)
+
+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define PINMUX_GPIO176__FUNC_CONN_BT_CLK (MTK_PIN_NO(176) | 1)
+#define PINMUX_GPIO176__FUNC_DFD_TDI (MTK_PIN_NO(176) | 3)
+#define PINMUX_GPIO176__FUNC_DBG_MON_B2 (MTK_PIN_NO(176) | 7)
+
+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define PINMUX_GPIO177__FUNC_CONN_BT_DATA (MTK_PIN_NO(177) | 1)
+#define PINMUX_GPIO177__FUNC_DFD_TDO (MTK_PIN_NO(177) | 3)
+
+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define PINMUX_GPIO178__FUNC_CONN_HRST_B (MTK_PIN_NO(178) | 1)
+#define PINMUX_GPIO178__FUNC_UDI_TMS (MTK_PIN_NO(178) | 3)
+#define PINMUX_GPIO178__FUNC_DBG_MON_B25 (MTK_PIN_NO(178) | 7)
+
+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define PINMUX_GPIO179__FUNC_CONN_WB_PTA (MTK_PIN_NO(179) | 1)
+#define PINMUX_GPIO179__FUNC_UDI_TCK (MTK_PIN_NO(179) | 3)
+#define PINMUX_GPIO179__FUNC_DBG_MON_B29 (MTK_PIN_NO(179) | 7)
+
+#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(180) | 1)
+#define PINMUX_GPIO180__FUNC_UDI_TDI (MTK_PIN_NO(180) | 3)
+
+#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(181) | 1)
+#define PINMUX_GPIO181__FUNC_UDI_TDO (MTK_PIN_NO(181) | 3)
+
+#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(182) | 1)
+#define PINMUX_GPIO182__FUNC_UDI_NTRST (MTK_PIN_NO(182) | 3)
+
+#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)
+#define PINMUX_GPIO183__FUNC_SPMI_SCL (MTK_PIN_NO(183) | 1)
+
+#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)
+#define PINMUX_GPIO184__FUNC_SPMI_SDA (MTK_PIN_NO(184) | 1)
+
+#endif /* __MT8168-PINFUNC_H */
--
2.25.5
^ permalink raw reply related
* [PATCH v2 0/2] pinctrl: mediatek: Support pinctrl driver on mt8186
From: Guodong Liu @ 2022-01-21 6:01 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Matthias Brugger, Sean Wang
Cc: Sean Wang, linux-gpio, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Guodong Liu
changes since v1:
- add default pinctrl config to consistent with other MTK pinctrl drivers
Patch 1 add pinctrl file and binding document.
Patch 2 add pinctrl chip driver on mt8186.
Guodong Liu (2):
dt-bindings: pinctrl: mt8186: add pinctrl file and binding document
pinctrl: add pinctrl driver on mt8186
.../bindings/pinctrl/pinctrl-mt8186.yaml | 303 +++
drivers/pinctrl/mediatek/Kconfig | 7 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8186.c | 1313 ++++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h | 2186 +++++++++++++++++
include/dt-bindings/pinctrl/mt8186-pinfunc.h | 1174 +++++++++
6 files changed, 4984 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8186.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
create mode 100644 include/dt-bindings/pinctrl/mt8186-pinfunc.h
--
2.25.5
^ permalink raw reply
* Re: [PATCH] dt-bindings: i2c: imx: Make each example a separate entry
From: Oleksij Rempel @ 2022-01-21 5:43 UTC (permalink / raw)
To: Rob Herring
Cc: Oleksij Rempel, Pengutronix Kernel Team, Shawn Guo, Sascha Hauer,
Fabio Estevam, NXP Linux Team, linux-kernel, linux-i2c,
linux-arm-kernel, devicetree
In-Reply-To: <20220119015253.2437352-1-robh@kernel.org>
On Tue, Jan 18, 2022 at 07:52:53PM -0600, Rob Herring wrote:
> Each independent example should be a separate entry. This allows for
> 'interrupts' to have different cell sizes.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Thank you!
> ---
> Documentation/devicetree/bindings/i2c/i2c-imx.yaml | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx.yaml b/Documentation/devicetree/bindings/i2c/i2c-imx.yaml
> index c167958ae2a9..01720e338b4c 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-imx.yaml
> +++ b/Documentation/devicetree/bindings/i2c/i2c-imx.yaml
> @@ -88,9 +88,7 @@ unevaluatedProperties: false
> examples:
> - |
> #include <dt-bindings/clock/imx5-clock.h>
> - #include <dt-bindings/clock/vf610-clock.h>
> - #include <dt-bindings/gpio/gpio.h>
> - #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
>
> i2c@83fc4000 {
> compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
> @@ -99,6 +97,9 @@ examples:
> clocks = <&clks IMX5_CLK_I2C2_GATE>;
> };
>
> + - |
> + #include <dt-bindings/clock/vf610-clock.h>
> +
> i2c@40066000 {
> compatible = "fsl,vf610-i2c";
> reg = <0x40066000 0x1000>;
> --
> 2.32.0
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH v12, 2/2] net: Add dm9051 driver
From: Joseph CHAMG @ 2022-01-21 4:14 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Rob Herring, Joseph CHANG,
joseph_chang
Cc: netdev, devicetree, linux-kernel, andy.shevchenko, andrew,
Leon Romanovsky
In-Reply-To: <20220121041428.6437-1-josright123@gmail.com>
v1-v4
Add davicom dm9051 spi ethernet driver. The driver work for the
device platform with spi master
Test ok with raspberry pi 2 and pi 4, the spi configure used in
my raspberry pi 4 is spi0.1, spi speed 31200000, and INT by pin 26.
v5
Work to eliminate the wrappers to be clear for read, swapped to
phylib for phy connection tasks.
Tested with raspberry pi 4. Test for netwroking function, CAT5
cable unplug/plug and also ethtool detect for link state, and
all are ok.
v6
remove the redundant code that phylib has support,
adjust to be the reasonable sequence,
fine tune comments, add comments for pause function support
Tested with raspberry pi 4. Test for netwroking function, CAT5
cable unplug/plug and also ethtool detect for link state, and
all are ok.
v7
read/write registers must return error code to the callet,
add to enable pause processing
v8
not parmanently set MAC by .ndo_set_mac_address
correct rx function such as clear ISR,
inblk avoid stack buffer,
simple skb buffer process and
easy use netif_rx_ni.
simplely queue init and wake the queues,
limit the start_xmit function use netif_stop_queue.
descript that schedule delay is essential
for tx_work and rxctrl_work
eliminate ____cacheline_aligned and
add static int msg_enable.
v9
use phylib, no need 'select MII' in Kconfig,
make it clear in dm9051_xfer when using spi_sync,
improve the registers read/write so that error code
return as far as possible up the call stack.
v10
use regmap APIs for SPI and MDIO,
modify to correcting such as include header files
and program check styles
v11
eliminate the redundant code for struct regmap_config data
use regmap_read_poll_timeout
use corresponding regmap APIs, i.e. MDIO, SPI
all read/write registers by regmap
all read/write registers with mutex lock by regmap
problem: regmap MDIO and SPI has no .reg_update_bits, I write it
in the driver
problem: this chip can support bulk read/write to rx/tx data, but
can not support bulk read/write to continue registers, so need
read/write register one by one
v12
correctly use regmap bulk read/write/update_bits APIs
use mdiobus to work to phylib and to this driver
fine tune to arrange the source code to better usage
---
drivers/net/ethernet/davicom/Kconfig | 31 +
drivers/net/ethernet/davicom/Makefile | 1 +
drivers/net/ethernet/davicom/dm9051.c | 1180 +++++++++++++++++++++++++
drivers/net/ethernet/davicom/dm9051.h | 159 ++++
4 files changed, 1371 insertions(+)
create mode 100644 drivers/net/ethernet/davicom/dm9051.c
create mode 100644 drivers/net/ethernet/davicom/dm9051.h
diff --git a/drivers/net/ethernet/davicom/Kconfig b/drivers/net/ethernet/davicom/Kconfig
index 7af86b6d4150..02e0caff98e3 100644
--- a/drivers/net/ethernet/davicom/Kconfig
+++ b/drivers/net/ethernet/davicom/Kconfig
@@ -3,6 +3,19 @@
# Davicom device configuration
#
+config NET_VENDOR_DAVICOM
+ bool "Davicom devices"
+ default y
+ help
+ If you have a network (Ethernet) card belonging to this class, say Y.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Davicom devices. If you say Y, you will be asked
+ for your specific card in the following selections.
+
+if NET_VENDOR_DAVICOM
+
config DM9000
tristate "DM9000 support"
depends on ARM || MIPS || COLDFIRE || NIOS2 || COMPILE_TEST
@@ -22,3 +35,21 @@ config DM9000_FORCE_SIMPLE_PHY_POLL
bit to determine if the link is up or down instead of the more
costly MII PHY reads. Note, this will not work if the chip is
operating with an external PHY.
+
+config DM9051
+ tristate "DM9051 SPI support"
+ depends on SPI
+ select CRC32
+ select MDIO
+ select PHYLIB
+ select REGMAP_SPI
+ help
+ Support for DM9051 SPI chipset.
+
+ To compile this driver as a module, choose M here. The module
+ will be called dm9051.
+
+ The SPI mode for the host's SPI master to access DM9051 is mode
+ 0 on the SPI bus.
+
+endif # NET_VENDOR_DAVICOM
diff --git a/drivers/net/ethernet/davicom/Makefile b/drivers/net/ethernet/davicom/Makefile
index 173c87d21076..225f85bc1f53 100644
--- a/drivers/net/ethernet/davicom/Makefile
+++ b/drivers/net/ethernet/davicom/Makefile
@@ -4,3 +4,4 @@
#
obj-$(CONFIG_DM9000) += dm9000.o
+obj-$(CONFIG_DM9051) += dm9051.o
diff --git a/drivers/net/ethernet/davicom/dm9051.c b/drivers/net/ethernet/davicom/dm9051.c
new file mode 100644
index 000000000000..42d383fe84e7
--- /dev/null
+++ b/drivers/net/ethernet/davicom/dm9051.c
@@ -0,0 +1,1180 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022 Davicom Semiconductor,Inc.
+ * Davicom DM9051 SPI Fast Ethernet Linux driver
+ */
+
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/mii.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/spi/spi.h>
+
+#include "dm9051.h"
+
+/**
+ * struct rx_ctl_mach - rx activities record
+ *
+ * @status_err_counter: rx status error counter
+ * @large_err_counter: rx get large packet length error counter
+ * @fifo_rst_counter: reset operation counter
+ *
+ * To keep track for the driver operation statistics
+ */
+struct rx_ctl_mach {
+ u16 status_err_counter;
+ u16 large_err_counter;
+ u16 fifo_rst_counter;
+};
+
+/**
+ * struct dm9051_rxhdr - rx packet data header
+ *
+ * @rxpktready: lead byte is 0x01 tell a valid packet
+ * @rxstatus: status bits for the received packet
+ * @rxlen: packet length
+ *
+ * The rx packet enter into the fifo memory is start with these four
+ * bytes which is the rx header, follow this header is the ethernet
+ * packet data and end with a appended 4-byte CRC data.
+ * Both rx packet and CRC data are for check purpose and finally are
+ * dropped by this driver
+ */
+struct dm9051_rxhdr {
+ u8 rxpktready;
+ u8 rxstatus;
+ __le16 rxlen;
+};
+
+/**
+ * struct board_info - maintain the saved data
+ *
+ * @spidev: spi device structure
+ * @ndev: net device structure
+ * @mdiobus: mii bus structure
+ * @phydev: phy device structure
+ * @txq: tx queue structure
+ * @regmap_dm: regmap for register read/write
+ * @regmap_dmbulk: extra regmap for bulk read/write
+ * @kwr_task_kw: kwr task structure
+ * @kw: kernel thread worker structure
+ * @kw_rxctrl: kernel thread worke structure for rx control
+ * @kw_tx: kernel thread worke structure for transmit
+ * @eth_pause: ethtool pause parameter structure
+ * @spi_lockm: between threads lock structure
+ * @reg_mutex: regmap access lock structure
+ * @bc: rx control statistics structure
+ * @eth_rxhdr: rx header structure
+ * @msg_enable: message level value
+ * @hash_table: hash table
+ * @imr_all: to store operating imr value for register DM9051_IMR
+ * @rcr_all: to store operating rcr value for register DM9051_RCR
+ * @lcr_all: to store operating rcr value for register DM9051_LMCR
+ *
+ * The saved data variables, keep up to date for retrieval back to use
+ */
+struct board_info {
+ struct spi_device *spidev;
+ struct net_device *ndev;
+ struct mii_bus *mdiobus;
+ struct phy_device *phydev;
+ struct sk_buff_head txq;
+ struct regmap *regmap_dm;
+ struct regmap *regmap_dmbulk;
+ struct task_struct *kwr_task_kw;
+ struct kthread_worker kw;
+ struct kthread_work kw_rxctrl;
+ struct kthread_work kw_tx;
+ struct ethtool_pauseparam eth_pause;
+ struct mutex spi_lockm;
+ struct mutex reg_mutex;
+ struct rx_ctl_mach bc;
+ struct dm9051_rxhdr eth_rxhdr;
+ u32 msg_enable;
+ u16 hash_table[4];
+ u8 imr_all;
+ u8 rcr_all;
+ u8 lcr_all;
+};
+
+/* waiting tx-end rather than tx-req
+ * got faster
+ */
+static int dm9051_map_xmitpoll(struct board_info *db)
+{
+ unsigned int mval;
+ int ret = regmap_read_poll_timeout(db->regmap_dm, DM9051_NSR, mval,
+ mval & (NSR_TX2END | NSR_TX1END), 1, 20);
+
+ if (unlikely(ret))
+ netdev_err(db->ndev, "timeout in checking for tx ends\n");
+ return ret;
+}
+
+static int dm9051_map_ee_phypoll(struct board_info *db)
+{
+ unsigned int mval;
+ int ret = regmap_read_poll_timeout(db->regmap_dm, DM9051_EPCR, mval,
+ !(mval & EPCR_ERRE), 100, 10000);
+
+ if (unlikely(ret))
+ netdev_err(db->ndev, "eeprom/phy in processing get timeout\n");
+ return ret;
+}
+
+static int dm9051_map_eeread(struct board_info *db, int offset, u8 *to)
+{
+ int ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPAR, offset);
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_ERPRR);
+ if (unlikely(ret))
+ return ret;
+ ret = dm9051_map_ee_phypoll(db);
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, 0x0);
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_bulk_read(db->regmap_dmbulk, DM9051_EPDRL, to, 2);
+ if (unlikely(ret))
+ return ret;
+ return ret;
+}
+
+static int dm9051_map_eewrite(struct board_info *db, int offset, u8 *data)
+{
+ int ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPAR, offset);
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_bulk_write(db->regmap_dmbulk, DM9051_EPDRL, data, 2);
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_WEP | EPCR_ERPRW);
+ if (unlikely(ret))
+ return ret;
+ ret = dm9051_map_ee_phypoll(db);
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, 0);
+ if (unlikely(ret))
+ return ret;
+ return ret;
+}
+
+static int ctrl_dm9051_phyread(void *context, unsigned int reg, unsigned int *val)
+{
+ struct board_info *db = context;
+ int ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPAR, DM9051_PHY | reg);
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_ERPRR | EPCR_EPOS);
+ if (unlikely(ret))
+ return ret;
+ ret = dm9051_map_ee_phypoll(db);
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, 0x0);
+ if (unlikely(ret))
+ return ret;
+
+ /* this is a 4 bytes data, clear to zero since following regmap_bulk_read
+ * only fill lower 2 bytes
+ */
+ *val = 0;
+ ret = regmap_bulk_read(db->regmap_dmbulk, DM9051_EPDRL, val, 2);
+ if (unlikely(ret))
+ return ret;
+ return ret;
+}
+
+static int ctrl_dm9051_phywrite(void *context, unsigned int reg, unsigned int val)
+{
+ struct board_info *db = context;
+ int ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPAR, DM9051_PHY | reg);
+ if (unlikely(ret))
+ return ret;
+
+ /* this is a 2 bytes data written via regmap_bulk_write
+ */
+ ret = regmap_bulk_write(db->regmap_dmbulk, DM9051_EPDRL, &val, 2);
+ if (unlikely(ret))
+ return ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_EPOS | EPCR_ERPRW);
+ if (unlikely(ret))
+ return ret;
+ ret = dm9051_map_ee_phypoll(db);
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, 0x0);
+ if (unlikely(ret))
+ return ret;
+
+ /* chip internal operation need wait 1 ms for if power-up phy
+ */
+ if (reg == MII_BMCR && !(val & BMCR_PDOWN))
+ mdelay(1);
+ return ret;
+}
+
+static int dm9051_mdiobus_read(struct mii_bus *mdiobus, int phy_id, int reg)
+{
+ struct board_info *db = mdiobus->priv;
+ unsigned int val = 0;
+ int ret;
+
+ if (phy_id == DM9051_PHY_ID) {
+ ret = ctrl_dm9051_phyread(db, reg, &val);
+ if (unlikely(ret))
+ return ret;
+ return val;
+ }
+ return 0xffff;
+}
+
+static int dm9051_mdiobus_write(struct mii_bus *mdiobus, int phy_id, int reg, u16 val)
+{
+ struct board_info *db = mdiobus->priv;
+ int ret;
+
+ if (phy_id == DM9051_PHY_ID) {
+ ret = ctrl_dm9051_phywrite(db, reg, val);
+ if (unlikely(ret))
+ return ret;
+ return 0;
+ }
+ return -ENODEV;
+}
+
+/* skb buffer exhausted, just discard the received data
+ */
+static int dm9051_map_dumpblk(struct board_info *db, u8 reg, size_t count)
+{
+ struct net_device *ndev = db->ndev;
+ unsigned int rb;
+ int ret;
+
+ /* no skb buffer,
+ * both reg and &rb must be noinc,
+ * read once one byte via regmap_read
+ */
+ while (count--) {
+ ret = regmap_read(db->regmap_dm, reg, &rb);
+ if (unlikely(ret)) {
+ netif_err(db, drv, ndev, "%s: error %d dumping read reg %02x\n",
+ __func__, ret, reg);
+ break;
+ }
+ }
+ return ret;
+}
+
+static void dm9051_reg_lock_mutex(void *dbcontext)
+{
+ struct board_info *db = dbcontext;
+
+ mutex_lock(&db->reg_mutex);
+}
+
+static void dm9051_reg_unlock_mutex(void *dbcontext)
+{
+ struct board_info *db = dbcontext;
+
+ mutex_unlock(&db->reg_mutex);
+}
+
+static struct regmap_config regconfigdm = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0xff,
+ .reg_stride = 1,
+ .cache_type = REGCACHE_NONE,
+ .read_flag_mask = 0,
+ .write_flag_mask = DM_SPI_WR,
+ .val_format_endian = REGMAP_ENDIAN_LITTLE,
+ .lock = dm9051_reg_lock_mutex, /* essential, sure for no-conflict read/write */
+ .unlock = dm9051_reg_unlock_mutex, /* essential, sure for no-conflict read/write */
+};
+
+static struct regmap_config regconfigdmbulk = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0xff,
+ .reg_stride = 1,
+ .cache_type = REGCACHE_NONE,
+ .read_flag_mask = 0,
+ .write_flag_mask = DM_SPI_WR,
+ .val_format_endian = REGMAP_ENDIAN_LITTLE,
+ .lock = dm9051_reg_lock_mutex, /* essential, sure for no-conflict read/write */
+ .unlock = dm9051_reg_unlock_mutex, /* essential, sure for no-conflict read/write */
+ .use_single_read = true,
+ .use_single_write = true,
+};
+
+static int dm9051_map_chipid(struct board_info *db)
+{
+ struct device *dev = &db->spidev->dev;
+ unsigned int ret;
+ unsigned short wid;
+ u8 buff[6];
+
+ ret = regmap_bulk_read(db->regmap_dmbulk, DM9051_VIDL, buff, 6);
+ if (unlikely(ret)) {
+ netif_err(db, drv, db->ndev, "%s: error %d bulk_read reg %02x\n",
+ __func__, ret, DM9051_VIDL);
+ return ret;
+ }
+
+ wid = buff[3] << 8 | buff[2];
+ if (wid != DM9051_ID) {
+ dev_err(dev, "chipid error as %04x !\n", wid);
+ return -ENODEV;
+ }
+
+ dev_info(dev, "chip %04x found\n", wid);
+ return 0;
+}
+
+/* mac address is major from EEPROM
+ */
+static int dm9051_map_macaddr_init(struct net_device *ndev, struct board_info *db)
+{
+ u8 addr[ETH_ALEN];
+ int ret;
+
+ ret = regmap_bulk_read(db->regmap_dmbulk, DM9051_PAR, addr, ETH_ALEN);
+ if (unlikely(ret))
+ return ret;
+
+ if (!is_valid_ether_addr(addr)) {
+ eth_hw_addr_random(ndev);
+ dev_dbg(&db->spidev->dev, "Use random MAC address\n");
+ return 0;
+ }
+
+ eth_hw_addr_set(ndev, addr);
+ return 0;
+}
+
+static void dm9051_handle_link_change(struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ int lcl_adv, rmt_adv, ret;
+ u8 fcr = 0;
+
+ phy_print_status(ndev->phydev);
+
+ /* only write pause settings to mac. since mac and phy are integrated
+ * together, such as link state, speed and duplex are sync already
+ */
+ if (ndev->phydev->link) {
+ if (db->eth_pause.autoneg == AUTONEG_ENABLE) {
+ lcl_adv = linkmode_adv_to_mii_adv_t(db->phydev->advertising);
+ rmt_adv = linkmode_adv_to_mii_adv_t(db->phydev->lp_advertising);
+
+ if (lcl_adv & rmt_adv & ADVERTISE_PAUSE_CAP) {
+ db->eth_pause.rx_pause = true;
+ db->eth_pause.tx_pause = true;
+ }
+ }
+
+ /* while both rx_pause & tx_pause
+ * fcr will result idenical as FCR_RXTX_ENABLE
+ */
+ if (db->eth_pause.rx_pause)
+ fcr |= FCR_BKPM | FCR_FLCE;
+ if (db->eth_pause.tx_pause)
+ fcr |= FCR_TXPEN;
+
+ ret = regmap_update_bits(db->regmap_dm, DM9051_FCR, 0xff, fcr);
+ if (unlikely(ret))
+ netif_err(db, drv, ndev, "%s: error %d update bits reg %02x\n",
+ __func__, ret, DM9051_FCR);
+ }
+}
+
+/* phy connect as poll mode
+ */
+static int dm9051_phy_connect(struct board_info *db)
+{
+ char phy_id[MII_BUS_ID_SIZE + 3];
+
+ snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
+ db->mdiobus->id, DM9051_PHY_ID);
+
+ db->phydev = phy_connect(db->ndev, phy_id, dm9051_handle_link_change,
+ PHY_INTERFACE_MODE_MII);
+ if (IS_ERR(db->phydev))
+ return PTR_ERR_OR_ZERO(db->phydev);
+ return 0;
+}
+
+/* ethtool-ops
+ */
+static void dm9051_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
+{
+ strscpy(info->driver, DRVNAME_9051, sizeof(info->driver));
+}
+
+static void dm9051_set_msglevel(struct net_device *ndev, u32 value)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+
+ db->msg_enable = value;
+}
+
+static u32 dm9051_get_msglevel(struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+
+ return db->msg_enable;
+}
+
+static int dm9051_get_eeprom_len(struct net_device *dev)
+{
+ return 128;
+}
+
+static int dm9051_get_eeprom(struct net_device *ndev,
+ struct ethtool_eeprom *ee, u8 *data)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ int offset = ee->offset;
+ int len = ee->len;
+ int i, ret;
+
+ if ((len | offset) & 1)
+ return -EINVAL;
+
+ ee->magic = DM_EEPROM_MAGIC;
+
+ for (i = 0; i < len; i += 2) {
+ ret = dm9051_map_eeread(db, (offset + i) / 2, data + i);
+ if (unlikely(ret))
+ break;
+ }
+ return ret;
+}
+
+static int dm9051_set_eeprom(struct net_device *ndev,
+ struct ethtool_eeprom *ee, u8 *data)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ int offset = ee->offset;
+ int len = ee->len;
+ int i, ret;
+
+ if ((len | offset) & 1)
+ return -EINVAL;
+
+ if (ee->magic != DM_EEPROM_MAGIC)
+ return -EINVAL;
+
+ for (i = 0; i < len; i += 2) {
+ ret = dm9051_map_eewrite(db, (offset + i) / 2, data + i);
+ if (unlikely(ret))
+ break;
+ }
+ return ret;
+}
+
+static void dm9051_get_pauseparam(struct net_device *ndev,
+ struct ethtool_pauseparam *pause)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+
+ *pause = db->eth_pause;
+}
+
+static int dm9051_set_pauseparam(struct net_device *ndev,
+ struct ethtool_pauseparam *pause)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ u8 fcr = 0;
+ int ret;
+
+ db->eth_pause = *pause;
+
+ if (pause->autoneg)
+ db->phydev->autoneg = AUTONEG_ENABLE;
+ else
+ db->phydev->autoneg = AUTONEG_DISABLE;
+
+ if (pause->rx_pause)
+ fcr |= FCR_BKPM | FCR_FLCE;
+ if (pause->tx_pause)
+ fcr |= FCR_TXPEN;
+
+ ret = regmap_update_bits(db->regmap_dm, DM9051_FCR, 0xff, fcr);
+ if (unlikely(ret))
+ netif_err(db, drv, ndev, "%s: error %d update bits reg %02x\n",
+ __func__, ret, DM9051_FCR);
+ return ret;
+}
+
+static const struct ethtool_ops dm9051_ethtool_ops = {
+ .get_drvinfo = dm9051_get_drvinfo,
+ .get_link_ksettings = phy_ethtool_get_link_ksettings,
+ .set_link_ksettings = phy_ethtool_set_link_ksettings,
+ .get_msglevel = dm9051_get_msglevel,
+ .set_msglevel = dm9051_set_msglevel,
+ .nway_reset = phy_ethtool_nway_reset,
+ .get_link = ethtool_op_get_link,
+ .get_eeprom_len = dm9051_get_eeprom_len,
+ .get_eeprom = dm9051_get_eeprom,
+ .set_eeprom = dm9051_set_eeprom,
+ .get_pauseparam = dm9051_get_pauseparam,
+ .set_pauseparam = dm9051_set_pauseparam,
+};
+
+static int dm9051_direct_reset_code(struct board_info *db)
+{
+ int ret;
+
+ db->bc.fifo_rst_counter++;
+
+ ret = regmap_write(db->regmap_dm, DM9051_NCR, NCR_RST); /* NCR reset */
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_MBNDRY, MBNDRY_BYTE); /* MemBound */
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_PPCR, PPCR_PAUSE_COUNT); /* Pause Count */
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_LMCR, db->lcr_all); /* LEDMode1 */
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_INTCR, INTCR_POL_LOW); /* INTCR */
+ if (unlikely(ret))
+ return ret;
+ return ret;
+}
+
+/* reset while rx error found
+ */
+static int dm9051_direct_fifo_reset(struct board_info *db)
+{
+ struct net_device *ndev = db->ndev;
+ int rxlen = le16_to_cpu(db->eth_rxhdr.rxlen);
+ u8 fcr = 0;
+ int ret;
+
+ ret = dm9051_direct_reset_code(db);
+ if (unlikely(ret))
+ return ret;
+
+ if (db->eth_pause.rx_pause)
+ fcr |= FCR_BKPM | FCR_FLCE;
+ if (db->eth_pause.tx_pause)
+ fcr |= FCR_TXPEN;
+
+ ret = regmap_write(db->regmap_dm, DM9051_FCR, fcr);
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_IMR, db->imr_all); /* rxp to 0xc00 */
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_RCR, db->rcr_all); /* enable rx all */
+ if (unlikely(ret))
+ return ret;
+
+ netdev_dbg(ndev, "rxhdr-byte (%02x)\n",
+ db->eth_rxhdr.rxpktready);
+ netdev_dbg(ndev, "check rxstatus-eror (%02x)\n",
+ db->eth_rxhdr.rxstatus);
+ netdev_dbg(ndev, "check rxlen large-eror (%d > %d)\n",
+ rxlen, DM9051_PKT_MAX);
+
+ netdev_dbg(ndev, " rxstatus_Er & rxlen_Er %d, RST_c %d\n",
+ db->bc.status_err_counter + db->bc.large_err_counter,
+ db->bc.fifo_rst_counter);
+ return ret;
+}
+
+/* read packets from the fifo memory
+ * return value,
+ * > 0 - read packet number, caller can repeat the rx operation
+ * 0 - no error, caller need stop further rx operation
+ * -EBUSY - read data error, caller escape from rx operation
+ */
+static int dm9051_loop_rx(struct board_info *db)
+{
+ struct net_device *ndev = db->ndev;
+ unsigned int rxbyte;
+ int ret, rxlen;
+ struct sk_buff *skb;
+ u8 *rdptr;
+ int scanrr = 0;
+
+ do {
+ ret = regmap_noinc_read(db->regmap_dm, DM_SPI_MRCMDX, &rxbyte, 2);
+ if (unlikely(ret)) {
+ netif_err(db, drv, ndev, "%s: error %d noinc reading reg %02x, len %d\n",
+ __func__, ret, DM_SPI_MRCMDX, 2);
+ return ret;
+ }
+
+ if ((rxbyte & 0xff) != DM9051_PKT_RDY)
+ break; /* exhaust-empty */
+
+ ret = regmap_noinc_read(db->regmap_dm, DM_SPI_MRCMD, &db->eth_rxhdr, DM_RXHDR_SIZE);
+ if (unlikely(ret))
+ return ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_ISR, 0xff); /* to stop mrcmd */
+ if (unlikely(ret))
+ return ret;
+
+ rxlen = le16_to_cpu(db->eth_rxhdr.rxlen);
+ if (db->eth_rxhdr.rxstatus & RSR_ERR_BITS || rxlen > DM9051_PKT_MAX) {
+ if (db->eth_rxhdr.rxstatus & RSR_ERR_BITS)
+ db->bc.status_err_counter++;
+ else
+ db->bc.large_err_counter++;
+ ret = dm9051_direct_fifo_reset(db);
+ if (unlikely(ret))
+ return ret;
+ return 0;
+ }
+
+ skb = dev_alloc_skb(rxlen);
+ if (!skb) {
+ ret = dm9051_map_dumpblk(db, DM_SPI_MRCMD, rxlen);
+ if (unlikely(ret))
+ return ret;
+ return scanrr;
+ }
+
+ rdptr = skb_put(skb, rxlen - 4);
+ ret = regmap_noinc_read(db->regmap_dm, DM_SPI_MRCMD, rdptr, rxlen);
+ if (unlikely(ret)) {
+ dev_kfree_skb(skb);
+ return ret;
+ }
+
+ ret = regmap_write(db->regmap_dm, DM9051_ISR, 0xff); /* to stop mrcmd */
+ if (unlikely(ret))
+ return ret;
+
+ skb->protocol = eth_type_trans(skb, db->ndev);
+ if (db->ndev->features & NETIF_F_RXCSUM)
+ skb_checksum_none_assert(skb);
+ netif_rx_ni(skb);
+ db->ndev->stats.rx_bytes += rxlen;
+ db->ndev->stats.rx_packets++;
+ scanrr++;
+ } while (!ret);
+ return scanrr;
+}
+
+/* transmit a packet,
+ * return value,
+ * 0 - succeed
+ * -ETIMEDOUT - timeout error
+ */
+static int dm9051_single_tx(struct board_info *db, u8 *buff, unsigned int len)
+{
+ int ret;
+
+ ret = dm9051_map_xmitpoll(db);
+ if (ret)
+ return -ETIMEDOUT;
+
+ ret = regmap_noinc_write(db->regmap_dm, DM_SPI_MWCMD, buff, len);
+ if (unlikely(ret))
+ return ret;
+
+ ret = regmap_bulk_write(db->regmap_dmbulk, DM9051_TXPLL, &len, 2);
+ if (unlikely(ret))
+ return ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_TCR, TCR_TXREQ);
+ if (unlikely(ret))
+ return ret;
+ return 0;
+}
+
+static int dm9051_loop_tx(struct board_info *db)
+{
+ struct net_device *ndev = db->ndev;
+ int ntx = 0;
+ int ret;
+
+ while (!skb_queue_empty(&db->txq)) {
+ struct sk_buff *skb;
+
+ skb = skb_dequeue(&db->txq);
+ if (skb) {
+ ntx++;
+ ret = dm9051_single_tx(db, skb->data, skb->len);
+ dev_kfree_skb(skb);
+ if (ret < 0)
+ return 0;
+ ndev->stats.tx_bytes += skb->len;
+ ndev->stats.tx_packets++;
+ }
+
+ if (netif_queue_stopped(ndev) &&
+ (skb_queue_len(&db->txq) < DM9051_TX_QUE_LO_WATER))
+ netif_wake_queue(ndev);
+ }
+ return ntx;
+}
+
+static irqreturn_t dm9051_rx_threaded_irq(int irq, void *pw)
+{
+ struct board_info *db = pw;
+ int result, resul_tx;
+
+ mutex_lock(&db->spi_lockm); /* mutex essential */
+ if (netif_carrier_ok(db->ndev)) {
+ result = regmap_write(db->regmap_dm, DM9051_IMR, IMR_PAR); /* disable imr */
+ if (unlikely(result))
+ goto spi_err;
+
+ do {
+ result = dm9051_loop_rx(db); /* threaded irq rx */
+ if (result < 0)
+ goto spi_err;
+ resul_tx = dm9051_loop_tx(db); /* more tx better performance */
+ if (resul_tx < 0)
+ goto spi_err;
+ } while (result > 0);
+
+ result = regmap_write(db->regmap_dm, DM9051_IMR, db->imr_all); /* enable imr */
+ if (unlikely(result))
+ goto spi_err;
+ }
+spi_err:
+ mutex_unlock(&db->spi_lockm); /* mutex essential */
+ return IRQ_HANDLED;
+}
+
+static void dm9051_tx_delay(struct kthread_work *ws)
+{
+ struct board_info *db = container_of(ws, struct board_info, kw_tx);
+ int result;
+
+ mutex_lock(&db->spi_lockm); /* mutex essential */
+ result = dm9051_loop_tx(db);
+ if (result < 0)
+ netdev_err(db->ndev, "transmit packet error\n");
+ mutex_unlock(&db->spi_lockm); /* mutex essential */
+}
+
+static void dm9051_rxctl_delay(struct kthread_work *ws)
+{
+ struct board_info *db = container_of(ws, struct board_info, kw_rxctrl);
+ struct net_device *ndev = db->ndev;
+ int result;
+
+ mutex_lock(&db->spi_lockm); /* mutex essential */
+ result = regmap_bulk_write(db->regmap_dmbulk, DM9051_PAR, ndev->dev_addr, ETH_ALEN);
+ if (unlikely(result)) {
+ netif_err(db, drv, ndev, "%s: error %d bulk writing reg %02x, len %d\n",
+ __func__, result, DM9051_PAR, ETH_ALEN);
+ goto spi_err;
+ }
+
+ result = regmap_bulk_write(db->regmap_dmbulk, DM9051_MAR, db->hash_table, 8);
+ if (unlikely(result)) {
+ netif_err(db, drv, ndev, "%s: error %d bulk writing reg %02x, len %d\n",
+ __func__, result, DM9051_MAR, 8);
+ goto spi_err;
+ }
+ result = regmap_write(db->regmap_dm, DM9051_RCR, db->rcr_all); /* rx enable */
+ if (unlikely(result))
+ netif_err(db, drv, ndev, "%s: error %d write reg %02x\n",
+ __func__, result, DM9051_RCR);
+spi_err:
+ mutex_unlock(&db->spi_lockm); /* mutex essential */
+}
+
+static int dm9051_map_phyup(struct board_info *db)
+{
+ int ret;
+
+ /* ~BMCR_PDOWN to power-up phyxcer
+ */
+ ret = mdiobus_modify(db->mdiobus, DM9051_PHY_ID, MII_BMCR, BMCR_PDOWN, 0);
+ if (ret < 0)
+ return ret;
+
+ /* chip internal operation need wait 1 ms for if GPR power-up phy
+ */
+ ret = regmap_write(db->regmap_dm, DM9051_GPR, 0);
+ if (unlikely(ret))
+ return ret;
+ mdelay(1);
+
+ return 0;
+}
+
+static int dm9051_map_phydown(struct board_info *db)
+{
+ int ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_GPR, GPR_PHY_ON); /* Power-Down PHY */
+ if (unlikely(ret))
+ return ret;
+ return ret;
+}
+
+static int dm9051_all_start(struct board_info *db)
+{
+ int ret;
+
+ ret = dm9051_map_phyup(db);
+ if (unlikely(ret))
+ return ret;
+ ret = dm9051_direct_reset_code(db);
+ if (unlikely(ret))
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_IMR, db->imr_all); /* phyup, rxp to 0xc00 */
+ if (unlikely(ret))
+ return ret;
+ return ret;
+}
+
+static int dm9051_all_stop(struct board_info *db)
+{
+ int ret;
+
+ ret = dm9051_map_phydown(db);
+ if (unlikely(ret))
+ return ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_RCR, RCR_RX_DISABLE); /* rx disable */
+ if (unlikely(ret))
+ return ret;
+ return ret;
+}
+
+/* Open network device
+ * Called when the network device is marked active, such as a user executing
+ * 'ifconfig up' on the device
+ */
+static int dm9051_open(struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ struct spi_device *spi = db->spidev;
+ int ret;
+
+ netif_wake_queue(ndev);
+
+ ndev->irq = spi->irq; /* by dts */
+ ret = request_threaded_irq(spi->irq, NULL, dm9051_rx_threaded_irq,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+ ndev->name, db);
+ if (ret < 0) {
+ netdev_err(ndev, "failed to get irq\n");
+ return ret;
+ }
+
+ db->imr_all = IMR_PAR | IMR_PRM;
+ db->rcr_all = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
+ db->lcr_all = LMCR_MODE1;
+
+ /* init pause param FlowCtrl */
+ db->eth_pause.rx_pause = true;
+ db->eth_pause.tx_pause = true;
+ db->eth_pause.autoneg = AUTONEG_ENABLE;
+
+ /* We may have start with auto negotiation */
+ db->phydev->autoneg = AUTONEG_ENABLE;
+ db->phydev->speed = 0;
+ db->phydev->duplex = 0;
+
+ ret = dm9051_all_start(db);
+ if (unlikely(ret)) {
+ free_irq(spi->irq, db);
+ netif_stop_queue(ndev);
+ return ret;
+ }
+
+ phy_support_sym_pause(db->phydev); /* Enable support of sym pause */
+ phy_start(db->phydev); /* it enclose with mutex_lock/mutex_unlock */
+ return 0;
+}
+
+/* Close network device
+ * Called to close down a network device which has been active. Cancel any
+ * work, shutdown the RX and TX process and then place the chip into a low
+ * power state while it is not being used
+ */
+static int dm9051_stop(struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ int ret;
+
+ free_irq(db->spidev->irq, db);
+ netif_stop_queue(ndev);
+
+ phy_stop(db->phydev);
+ ret = dm9051_all_stop(db);
+ return ret;
+}
+
+/* event: play a schedule starter in condition
+ */
+static netdev_tx_t dm9051_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+
+ skb_queue_tail(&db->txq, skb); /* add to skb */
+ if (skb_queue_len(&db->txq) > DM9051_TX_QUE_HI_WATER)
+ netif_stop_queue(ndev); /* enforce limit queue size */
+ kthread_queue_work(&db->kw, &db->kw_tx);
+ return NETDEV_TX_OK;
+}
+
+/* event: play with a schedule starter
+ */
+static void dm9051_set_multicast_list_schedule(struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
+ struct netdev_hw_addr *ha;
+ u32 hash_val;
+
+ /* rx control */
+ if (ndev->flags & IFF_PROMISC) {
+ rcr |= RCR_PRMSC;
+ netdev_dbg(ndev, "set_multicast rcr |= RCR_PRMSC, rcr= %02x\n", rcr);
+ }
+
+ if (ndev->flags & IFF_ALLMULTI) {
+ rcr |= RCR_ALL;
+ netdev_dbg(ndev, "set_multicast rcr |= RCR_ALLMULTI, rcr= %02x\n", rcr);
+ }
+
+ db->rcr_all = rcr;
+
+ /* broadcast address */
+ db->hash_table[0] = 0;
+ db->hash_table[1] = 0;
+ db->hash_table[2] = 0;
+ db->hash_table[3] = 0x8000;
+
+ /* the multicast address in Hash Table : 64 bits */
+ netdev_for_each_mc_addr(ha, ndev) {
+ hash_val = ether_crc_le(ETH_ALEN, ha->addr) & 0x3f;
+ db->hash_table[hash_val / 16] |= 1U << (hash_val % 16);
+ }
+ kthread_queue_work(&db->kw, &db->kw_rxctrl);
+}
+
+/* event: write into the mac registers and eeprom directly
+ */
+static int dm9051_set_mac_address(struct net_device *ndev, void *p)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ int ret;
+
+ ret = eth_mac_addr(ndev, p);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_bulk_write(db->regmap_dmbulk, DM9051_PAR, ndev->dev_addr, ETH_ALEN);
+ if (unlikely(ret)) {
+ netif_err(db, drv, ndev, "%s: error %d bulk writing reg %02x, len %d\n",
+ __func__, ret, DM9051_PAR, ETH_ALEN);
+ return ret;
+ }
+ return ret;
+}
+
+/* netdev-ops
+ */
+static const struct of_device_id dm9051_match_table[] = {
+ { .compatible = "davicom,dm9051", },
+ {}
+};
+
+static const struct spi_device_id dm9051_id_table[] = {
+ { "dm9051", 0 },
+ {}
+};
+
+static
+const struct net_device_ops dm9051_netdev_ops = {
+ .ndo_open = dm9051_open,
+ .ndo_stop = dm9051_stop,
+ .ndo_start_xmit = dm9051_start_xmit,
+ .ndo_set_rx_mode = dm9051_set_multicast_list_schedule,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_set_mac_address = dm9051_set_mac_address,
+};
+
+/* probe subs
+ */
+static void dm9051_operation_clear(struct board_info *db)
+{
+ db->bc.status_err_counter = 0;
+ db->bc.large_err_counter = 0;
+ db->bc.fifo_rst_counter = 0;
+}
+
+static void dm9051_netdev(struct net_device *ndev)
+{
+ ndev->mtu = 1500;
+ ndev->if_port = IF_PORT_100BASET;
+ ndev->netdev_ops = &dm9051_netdev_ops;
+ ndev->ethtool_ops = &dm9051_ethtool_ops;
+}
+
+static int dm9051_map_init(struct spi_device *spi, struct board_info *db)
+{
+ /* create two regmap instances,
+ * run read/write and bulk_read/bulk_write individually,
+ * to resolve regmap execution confliction problem
+ */
+ regconfigdm.lock_arg = db;
+ db->regmap_dm = devm_regmap_init_spi(db->spidev, ®configdm);
+
+ if (IS_ERR(db->regmap_dm))
+ return PTR_ERR_OR_ZERO(db->regmap_dm);
+
+ regconfigdmbulk.lock_arg = db;
+ db->regmap_dmbulk = devm_regmap_init_spi(db->spidev, ®configdmbulk);
+
+ if (IS_ERR(db->regmap_dmbulk))
+ return PTR_ERR_OR_ZERO(db->regmap_dmbulk);
+ return 0;
+}
+
+static int dm9051_mdiobus_register(struct board_info *db)
+{
+ struct spi_device *spi = db->spidev;
+ int ret;
+
+ db->mdiobus = devm_mdiobus_alloc(&spi->dev);
+ if (!db->mdiobus)
+ return -ENOMEM;
+
+ db->mdiobus->priv = db;
+ db->mdiobus->read = dm9051_mdiobus_read;
+ db->mdiobus->write = dm9051_mdiobus_write;
+ db->mdiobus->name = "dm9051-mdiobus";
+ db->mdiobus->phy_mask = ~GENMASK(1, 1);
+ db->mdiobus->parent = &spi->dev;
+ snprintf(db->mdiobus->id, MII_BUS_ID_SIZE,
+ "dm9051-%s.%u", dev_name(&spi->dev), spi->chip_select);
+
+ ret = devm_mdiobus_register(&spi->dev, db->mdiobus);
+ if (ret) {
+ dev_err(&spi->dev, "Could not register MDIO bus\n");
+ return ret;
+ }
+ return 0;
+}
+
+static int dm9051_probe(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ struct net_device *ndev;
+ struct board_info *db;
+ int ret = 0;
+
+ ndev = devm_alloc_etherdev(dev, sizeof(struct board_info));
+ if (!ndev)
+ return -ENOMEM;
+
+ SET_NETDEV_DEV(ndev, dev);
+ dev_set_drvdata(dev, ndev);
+ db = netdev_priv(ndev);
+ db->msg_enable = 0;
+ db->spidev = spi;
+ db->ndev = ndev;
+ dm9051_netdev(ndev);
+
+ mutex_init(&db->spi_lockm);
+ mutex_init(&db->reg_mutex);
+
+ kthread_init_worker(&db->kw);
+ kthread_init_work(&db->kw_rxctrl, dm9051_rxctl_delay);
+ kthread_init_work(&db->kw_tx, dm9051_tx_delay);
+
+ db->kwr_task_kw = kthread_run(kthread_worker_fn, &db->kw, "dm9051");
+ if (IS_ERR(db->kwr_task_kw))
+ return PTR_ERR(db->kwr_task_kw);
+
+ ret = dm9051_map_init(spi, db);
+ if (ret)
+ goto err_stopthread;
+
+ ret = dm9051_map_chipid(db);
+ if (ret)
+ goto err_stopthread;
+
+ ret = dm9051_map_macaddr_init(ndev, db);
+ if (ret < 0)
+ goto err_stopthread;
+
+ ret = dm9051_mdiobus_register(db);
+ if (ret)
+ goto err_stopthread;
+
+ ret = dm9051_phy_connect(db);
+ if (ret)
+ goto err_stopthread;
+
+ dm9051_operation_clear(db);
+ ret = devm_register_netdev(dev, ndev);
+ if (ret) {
+ dev_err(dev, "failed to register network device\n");
+ kthread_stop(db->kwr_task_kw);
+ phy_disconnect(db->phydev);
+ return ret;
+ }
+
+ skb_queue_head_init(&db->txq);
+ return 0;
+
+err_stopthread:
+ kthread_stop(db->kwr_task_kw);
+ return ret;
+}
+
+static int dm9051_drv_remove(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ struct net_device *ndev = dev_get_drvdata(dev);
+ struct board_info *db = to_dm9051_board(ndev);
+
+ kthread_stop(db->kwr_task_kw);
+ phy_disconnect(db->phydev);
+ return 0;
+}
+
+static struct spi_driver dm9051_driver = {
+ .driver = {
+ .name = DRVNAME_9051,
+ .of_match_table = dm9051_match_table,
+ },
+ .probe = dm9051_probe,
+ .remove = dm9051_drv_remove,
+ .id_table = dm9051_id_table,
+};
+module_spi_driver(dm9051_driver);
+
+MODULE_AUTHOR("Joseph CHANG <joseph_chang@davicom.com.tw>");
+MODULE_DESCRIPTION("Davicom DM9051 network SPI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/davicom/dm9051.h b/drivers/net/ethernet/davicom/dm9051.h
new file mode 100644
index 000000000000..85eb90dc97e0
--- /dev/null
+++ b/drivers/net/ethernet/davicom/dm9051.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 Davicom Semiconductor,Inc.
+ * Davicom DM9051 SPI Fast Ethernet Linux driver
+ */
+
+#ifndef _DM9051_H_
+#define _DM9051_H_
+
+#include <linux/bitfield.h>
+
+#define DRVNAME_9051 "dm9051"
+
+#define DM9051_ID 0x9051
+
+#define DM9051_NCR 0x00
+#define DM9051_NSR 0x01
+#define DM9051_TCR 0x02
+#define DM9051_RCR 0x05
+#define DM9051_BPTR 0x08
+#define DM9051_FCR 0x0A
+#define DM9051_EPCR 0x0B
+#define DM9051_EPAR 0x0C
+#define DM9051_EPDRL 0x0D
+#define DM9051_EPDRH 0x0E
+#define DM9051_PAR 0x10
+#define DM9051_MAR 0x16
+#define DM9051_GPCR 0x1E
+#define DM9051_GPR 0x1F
+
+#define DM9051_VIDL 0x28
+#define DM9051_VIDH 0x29
+#define DM9051_PIDL 0x2A
+#define DM9051_PIDH 0x2B
+#define DM9051_SMCR 0x2F
+#define DM9051_ATCR 0x30
+#define DM9051_SPIBCR 0x38
+#define DM9051_INTCR 0x39
+#define DM9051_PPCR 0x3D
+
+#define DM9051_MPCR 0x55
+#define DM9051_LMCR 0x57
+#define DM9051_MBNDRY 0x5E
+
+#define DM9051_MRRL 0x74
+#define DM9051_MRRH 0x75
+#define DM9051_MWRL 0x7A
+#define DM9051_MWRH 0x7B
+#define DM9051_TXPLL 0x7C
+#define DM9051_TXPLH 0x7D
+#define DM9051_ISR 0x7E
+#define DM9051_IMR 0x7F
+
+#define DM_SPI_MRCMDX 0x70
+#define DM_SPI_MRCMD 0x72
+#define DM_SPI_MWCMD 0x78
+
+#define DM_SPI_WR 0x80
+
+/* dm9051 Ethernet
+ */
+/* 0x00 */
+#define NCR_WAKEEN BIT(6)
+#define NCR_FDX BIT(3)
+#define NCR_RST BIT(0)
+/* 0x01 */
+#define NSR_SPEED BIT(7)
+#define NSR_LINKST BIT(6)
+#define NSR_WAKEST BIT(5)
+#define NSR_TX2END BIT(3)
+#define NSR_TX1END BIT(2)
+/* 0x02 */
+#define TCR_DIS_JABBER_TIMER BIT(6) /* for Jabber Packet support */
+#define TCR_TXREQ BIT(0)
+/* 0x05 */
+#define RCR_DIS_WATCHDOG_TIMER BIT(6) /* for Jabber Packet support */
+#define RCR_DIS_LONG BIT(5)
+#define RCR_DIS_CRC BIT(4)
+#define RCR_ALL BIT(3)
+#define RCR_PRMSC BIT(1)
+#define RCR_RXEN BIT(0)
+#define RCR_RX_DISABLE (RCR_DIS_LONG | RCR_DIS_CRC)
+/* 0x06 */
+#define RSR_RF BIT(7)
+#define RSR_MF BIT(6)
+#define RSR_LCS BIT(5)
+#define RSR_RWTO BIT(4)
+#define RSR_PLE BIT(3)
+#define RSR_AE BIT(2)
+#define RSR_CE BIT(1)
+#define RSR_FOE BIT(0)
+#define RSR_ERR_BITS (RSR_RF | RSR_LCS | RSR_RWTO | RSR_PLE | \
+ RSR_AE | RSR_CE | RSR_FOE)
+/* 0x0A */
+#define FCR_TXPEN BIT(5)
+#define FCR_BKPM BIT(3)
+#define FCR_FLCE BIT(0)
+#define FCR_RXTX_ENABLE (FCR_TXPEN | FCR_BKPM | FCR_FLCE)
+/* 0x0B */
+#define EPCR_WEP BIT(4)
+#define EPCR_EPOS BIT(3)
+#define EPCR_ERPRR BIT(2)
+#define EPCR_ERPRW BIT(1)
+#define EPCR_ERRE BIT(0)
+/* 0x1E */
+#define GPCR_GEP_CNTL BIT(0)
+/* 0x1F */
+#define GPR_PHY_ON BIT(0)
+/* 0x30 */
+#define ATCR_AUTO_TX BIT(7)
+/* 0x39 */
+#define INTCR_POL_LOW BIT(0)
+#define INTCR_POL_HIGH (0 << 0)
+/* 0x3D */
+/* Pause Packet Control Register - default = 1 */
+#define PPCR_PAUSE_COUNT 0x08
+/* 0x55 */
+#define MPCR_RSTTX BIT(1)
+#define MPCR_RSTRX BIT(0)
+/* 0x57 */
+/* LEDMode Control Register - LEDMode1 */
+/* Value 0x81 : bit[7] = 1, bit[2] = 0, bit[1:0] = 01b */
+#define LMCR_NEWMOD BIT(7)
+#define LMCR_TYPED1 BIT(1)
+#define LMCR_TYPED0 BIT(0)
+#define LMCR_MODE1 (LMCR_NEWMOD | LMCR_TYPED0)
+/* 0x5E */
+#define MBNDRY_BYTE BIT(7)
+/* 0xFE */
+#define ISR_MBS BIT(7)
+#define ISR_ROOS BIT(3)
+#define ISR_ROS BIT(2)
+#define ISR_PTS BIT(1)
+#define ISR_PRS BIT(0)
+#define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
+/* 0xFF */
+#define IMR_PAR BIT(7)
+#define IMR_LNKCHGI BIT(5)
+#define IMR_PTM BIT(1)
+#define IMR_PRM BIT(0)
+
+/* Const
+ */
+#define DM9051_PHY_ID 1 /* PHY id */
+#define DM9051_PHY 0x40 /* PHY address 0x01 */
+#define DM9051_PKT_RDY 0x01 /* Packet ready to receive */
+#define DM9051_PKT_MAX 1536 /* Received packet max size */
+#define DM9051_TX_QUE_HI_WATER 50
+#define DM9051_TX_QUE_LO_WATER 25
+#define DM_EEPROM_MAGIC 0x9051
+
+#define DM_RXHDR_SIZE sizeof(struct dm9051_rxhdr)
+
+static inline struct board_info *to_dm9051_board(struct net_device *ndev)
+{
+ return netdev_priv(ndev);
+}
+
+#endif /* _DM9051_H_ */
--
2.20.1
^ permalink raw reply related
* [PATCH v12, 1/2] yaml: Add dm9051 SPI network yaml file
From: Joseph CHAMG @ 2022-01-21 4:14 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Rob Herring, Joseph CHANG,
joseph_chang
Cc: netdev, devicetree, linux-kernel, andy.shevchenko, andrew,
Rob Herring
In-Reply-To: <20220121041428.6437-1-josright123@gmail.com>
From: JosephCHANG <josright123@gmail.com>
This is a new yaml base data file for configure davicom dm9051 with
device tree
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: JosephCHANG <josright123@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/net/davicom,dm9051.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/davicom,dm9051.yaml
diff --git a/Documentation/devicetree/bindings/net/davicom,dm9051.yaml b/Documentation/devicetree/bindings/net/davicom,dm9051.yaml
new file mode 100644
index 000000000000..52e852fef753
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/davicom,dm9051.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/davicom,dm9051.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Davicom DM9051 SPI Ethernet Controller
+
+maintainers:
+ - Joseph CHANG <josright123@gmail.com>
+
+description: |
+ The DM9051 is a fully integrated and cost-effective low pin count single
+ chip Fast Ethernet controller with a Serial Peripheral Interface (SPI).
+
+allOf:
+ - $ref: ethernet-controller.yaml#
+
+properties:
+ compatible:
+ const: davicom,dm9051
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 45000000
+
+ interrupts:
+ maxItems: 1
+
+ local-mac-address: true
+
+ mac-address: true
+
+required:
+ - compatible
+ - reg
+ - spi-max-frequency
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ # Raspberry Pi platform
+ - |
+ /* for Raspberry Pi with pin control stuff for GPIO irq */
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@0 {
+ compatible = "davicom,dm9051";
+ reg = <0>; /* spi chip select */
+ local-mac-address = [00 00 00 00 00 00];
+ interrupt-parent = <&gpio>;
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <31200000>;
+ };
+ };
--
2.20.1
^ permalink raw reply related
* [PATCH v12, 0/2] ADD DM9051 ETHERNET DRIVER
From: Joseph CHAMG @ 2022-01-21 4:14 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Rob Herring, Joseph CHANG,
joseph_chang
Cc: netdev, devicetree, linux-kernel, andy.shevchenko, andrew
DM9051 is a spi interface chip,
need cs/mosi/miso/clock with an interrupt gpio pin
Joseph CHAMG (1):
net: Add dm9051 driver
JosephCHANG (1):
yaml: Add dm9051 SPI network yaml file
.../bindings/net/davicom,dm9051.yaml | 62 +
drivers/net/ethernet/davicom/Kconfig | 31 +
drivers/net/ethernet/davicom/Makefile | 1 +
drivers/net/ethernet/davicom/dm9051.c | 1180 +++++++++++++++++
drivers/net/ethernet/davicom/dm9051.h | 159 +++
5 files changed, 1433 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/davicom,dm9051.yaml
create mode 100644 drivers/net/ethernet/davicom/dm9051.c
create mode 100644 drivers/net/ethernet/davicom/dm9051.h
base-commit: 9d922f5df53844228b9f7c62f2593f4f06c0b69b
--
2.20.1
^ permalink raw reply
* Re: [PATCH v4 3/3] dmaengine: sf-pdma: Get number of channel by device tree
From: Zong Li @ 2022-01-21 2:21 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Rob Herring, Paul Walmsley, Albert Ou, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Bin Meng, Green Wan, Vinod,
dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org List, linux-riscv
In-Reply-To: <mhng-5b3e2596-3558-4534-9229-26885ee4cc5c@palmer-ri-x1c9>
On Fri, Jan 21, 2022 at 2:52 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Sun, 16 Jan 2022 17:35:28 PST (-0800), zong.li@sifive.com wrote:
> > It currently assumes that there are always four channels, it would
> > cause the error if there is actually less than four channels. Change
> > that by getting number of channel from device tree.
> >
> > For backwards-compatible, it uses the default value (i.e. 4) when there
> > is no 'dma-channels' information in dts.
>
> Some of the same wording issues here as those I pointed out in the DT
> bindings patch.
>
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> > drivers/dma/sf-pdma/sf-pdma.c | 20 +++++++++++++-------
> > drivers/dma/sf-pdma/sf-pdma.h | 8 ++------
> > 2 files changed, 15 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c
> > index f12606aeff87..1264add9897e 100644
> > --- a/drivers/dma/sf-pdma/sf-pdma.c
> > +++ b/drivers/dma/sf-pdma/sf-pdma.c
> > @@ -482,9 +482,7 @@ static void sf_pdma_setup_chans(struct sf_pdma *pdma)
> > static int sf_pdma_probe(struct platform_device *pdev)
> > {
> > struct sf_pdma *pdma;
> > - struct sf_pdma_chan *chan;
> > struct resource *res;
> > - int len, chans;
> > int ret;
> > const enum dma_slave_buswidth widths =
> > DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES |
> > @@ -492,13 +490,21 @@ static int sf_pdma_probe(struct platform_device *pdev)
> > DMA_SLAVE_BUSWIDTH_16_BYTES | DMA_SLAVE_BUSWIDTH_32_BYTES |
> > DMA_SLAVE_BUSWIDTH_64_BYTES;
> >
> > - chans = PDMA_NR_CH;
> > - len = sizeof(*pdma) + sizeof(*chan) * chans;
> > - pdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
> > + pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
> > if (!pdma)
> > return -ENOMEM;
> >
> > - pdma->n_chans = chans;
> > + ret = of_property_read_u32(pdev->dev.of_node, "dma-channels",
> > + &pdma->n_chans);
> > + if (ret) {
> > + dev_notice(&pdev->dev, "set number of channels to default value: 4\n");
> > + pdma->n_chans = PDMA_MAX_NR_CH;
> > + }
> > +
> > + if (pdma->n_chans > PDMA_MAX_NR_CH) {
> > + dev_err(&pdev->dev, "the number of channels exceeds the maximum\n");
> > + return -EINVAL;
>
> Can we get away with just using only the number of channels the driver
> actually supports? ie, just never sending an op to the channels above
> MAX_NR_CH? That should leave us with nothing to track.
It might be a bit like when pdma->n_chans is bigger than the maximum,
set the pdma->chans to PDMA_MAX_NR_CH, then we could ensure that we
don't access the channels above the maximum. If I understand
correctly, I gave the similar thought in the thread of v2 patch, and
there are some discussions on that, but this way seems to lead to
hard-to-track problems.
>
> > + }
> >
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > pdma->membase = devm_ioremap_resource(&pdev->dev, res);
> > @@ -556,7 +562,7 @@ static int sf_pdma_remove(struct platform_device *pdev)
> > struct sf_pdma_chan *ch;
> > int i;
> >
> > - for (i = 0; i < PDMA_NR_CH; i++) {
> > + for (i = 0; i < pdma->n_chans; i++) {
> > ch = &pdma->chans[i];
> >
> > devm_free_irq(&pdev->dev, ch->txirq, ch);
> > diff --git a/drivers/dma/sf-pdma/sf-pdma.h b/drivers/dma/sf-pdma/sf-pdma.h
> > index 0c20167b097d..8127d792f639 100644
> > --- a/drivers/dma/sf-pdma/sf-pdma.h
> > +++ b/drivers/dma/sf-pdma/sf-pdma.h
> > @@ -22,11 +22,7 @@
> > #include "../dmaengine.h"
> > #include "../virt-dma.h"
> >
> > -#define PDMA_NR_CH 4
> > -
> > -#if (PDMA_NR_CH != 4)
> > -#error "Please define PDMA_NR_CH to 4"
> > -#endif
> > +#define PDMA_MAX_NR_CH 4
> >
> > #define PDMA_BASE_ADDR 0x3000000
> > #define PDMA_CHAN_OFFSET 0x1000
> > @@ -118,7 +114,7 @@ struct sf_pdma {
> > void __iomem *membase;
> > void __iomem *mappedbase;
> > u32 n_chans;
> > - struct sf_pdma_chan chans[PDMA_NR_CH];
> > + struct sf_pdma_chan chans[PDMA_MAX_NR_CH];
> > };
> >
> > #endif /* _SF_PDMA_H */
^ permalink raw reply
* Re: [PATCH v1, 1/1] soc: mediatek: cmdq: add cmdq_pkt_poll_addr function
From: CK Hu @ 2022-01-21 2:08 UTC (permalink / raw)
To: Yongqiang Niu, Chun-Kuang Hu
Cc: devicetree, Project_Global_Chrome_Upstream_Group, David Airlie,
Jassi Brar, linux-kernel, dri-devel, Dennis YC Hsieh,
Fabien Parent, Rob Herring, linux-mediatek, Hsin-Yi Wang,
Matthias Brugger, mtk18742, linux-arm-kernel
In-Reply-To: <20220120074311.2243-2-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Thu, 2022-01-20 at 15:43 +0800, Yongqiang Niu wrote:
> From: mtk18742 <moudy.ho@mediatek.com>
>
> add cmdq_pkt_poll_addr function in cmdq helper functions
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 39
> ++++++++++++++++++++++++
> include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
> include/linux/soc/mediatek/mtk-cmdq.h | 2 ++
> 3 files changed, 42 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 3c8e4212d941..6c5cfb284140 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -344,6 +344,45 @@ int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16
> event)
> }
> EXPORT_SYMBOL(cmdq_pkt_set_event);
>
> +s32 cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, u32 value, u32 addr,
> u32 mask, u8 reg_gpr)
> +{
> + struct cmdq_instruction inst = { {0} };
> +
> + s32 err;
> +
> + if (mask != 0xffffffff) {
> + inst.op = CMDQ_CODE_MASK;
> + inst.mask = ~mask;
> + err = cmdq_pkt_append_command(pkt, inst);
> + if (err != 0)
> + return err;
> +
> + addr = addr | 0x1;
> + }
> +
> + /* Move extra handle APB address to GPR */
> + inst.op = CMDQ_CODE_MOVE;
> + inst.value = addr;
> + inst.sop = reg_gpr;
> + inst.dst_t = 1;
> + err = cmdq_pkt_append_command(pkt, inst);
> + if (err != 0)
> + pr_err("%s fail append command move addr to reg
> err:%d",
> + __func__, err);
cmdq_pkt_assign() could assign a value to GPR, so remove this part.
> +
> + inst.op = CMDQ_CODE_POLL;
> + inst.value = value;
> + inst.sop = reg_gpr;
> + inst.dst_t = 1;
> + err = cmdq_pkt_append_command(pkt, inst);
> + if (err != 0)
> + pr_err("%s fail append command poll err:%d",
> + __func__, err);
> +
> + return err;
> +}
> +EXPORT_SYMBOL(cmdq_pkt_poll_addr);
> +
> int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
> u16 offset, u32 value)
> {
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h
> b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index 44365aab043c..a27329fd7c7f 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -54,6 +54,7 @@
> */
> enum cmdq_code {
> CMDQ_CODE_MASK = 0x02,
> + CMDQ_CODE_MOVE = 0x02,
> CMDQ_CODE_WRITE = 0x04,
> CMDQ_CODE_POLL = 0x08,
> CMDQ_CODE_JUMP = 0x10,
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index ac6b5f3cba95..28dc5ce0ff03 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -280,4 +280,6 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt);
> int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb
> cb,
> void *data);
>
Add comment for this function, parameters, and return value like other
interface.
Regards,
CK
> +s32 cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, u32 value, u32 addr,
> u32 mask, u8 reg_gpr);
> +
> #endif /* __MTK_CMDQ_H__ */
^ permalink raw reply
* Re: [PATCH v2 net 2/4] dt-bindings: net: Document fsl,erratum-a009885
From: Rob Herring @ 2022-01-21 2:08 UTC (permalink / raw)
To: Tobias Waldekranz
Cc: davem, kuba, netdev, Andrew Lunn, Madalin Bucur, devicetree,
linux-kernel
In-Reply-To: <20220118215054.2629314-3-tobias@waldekranz.com>
On Tue, Jan 18, 2022 at 10:50:51PM +0100, Tobias Waldekranz wrote:
> Update FMan binding documentation with the newly added workaround for
> erratum A-009885.
>
> Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> ---
> Documentation/devicetree/bindings/net/fsl-fman.txt | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/fsl-fman.txt b/Documentation/devicetree/bindings/net/fsl-fman.txt
> index c00fb0d22c7b..020337f3c05f 100644
> --- a/Documentation/devicetree/bindings/net/fsl-fman.txt
> +++ b/Documentation/devicetree/bindings/net/fsl-fman.txt
> @@ -410,6 +410,15 @@ PROPERTIES
> The settings and programming routines for internal/external
> MDIO are different. Must be included for internal MDIO.
>
> +- fsl,erratum-a009885
Adding errata properties doesn't work because then you have to update
your dtb to fix the issue where as if you use the compatible property
(specific to the SoC) you can fix the issue with just a (stable) kernel
update.
Yes, I see we already have some, but doesn't mean we need more of them.
> + Usage: optional
> + Value type: <boolean>
> + Definition: Indicates the presence of the A009885
> + erratum describing that the contents of MDIO_DATA may
> + become corrupt unless it is read within 16 MDC cycles
> + of MDIO_CFG[BSY] being cleared, when performing an
> + MDIO read operation.
> +
> - fsl,erratum-a011043
> Usage: optional
> Value type: <boolean>
> --
> 2.25.1
>
>
^ permalink raw reply
* Re: [PATCH v2 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding
From: Rob Herring @ 2022-01-21 2:04 UTC (permalink / raw)
To: Ansuel Smith
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Philipp Zabel, Taniya Das, linux-arm-msm, linux-clk, devicetree,
linux-kernel
In-Reply-To: <20220120232028.6738-4-ansuelsmth@gmail.com>
On Fri, Jan 21, 2022 at 12:20:16AM +0100, Ansuel Smith wrote:
> Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
> clocks. The gcc node is also used by the tsens driver, already documented,
> to get the calib nvmem cells and the base reg from gcc.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++
> 1 file changed, 70 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> new file mode 100644
> index 000000000000..abc76a46b2ca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
> +
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +maintainers:
> + - Ansuel Smith <ansuelsmth@gmail.com>
> +
> +description: |
> + Qualcomm global clock control module which supports the clocks, resets and
> + power domains on IPQ8064.
> +
> + See also:
> + - dt-bindings/clock/qcom,gcc-ipq806x.h
> + - dt-bindings/reset/qcom,gcc-ipq806x.h
> +
> +properties:
This schema will never be applied because there is not a compatible
property to use for matching. The base/common schema is the one that
shouldn't have a compatible and then the specific schemas like this
one do.
> + clocks:
> + items:
> + - description: PXO source
> + - description: CXO source
> +
> + clock-names:
> + items:
> + - const: pxo
> + - const: cxo
> +
> + thermal-sensor:
> + type: object
> +
> + allOf:
> + - $ref: /schemas/thermal/qcom-tsens.yaml#
> +
> +required:
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + gcc: clock-controller@900000 {
> + compatible = "qcom,gcc-ipq8064", "syscon";
> + reg = <0x00900000 0x4000>;
> + clocks = <&pxo_board>, <&cxo_board>;
> + clock-names = "pxo", "cxo";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> +
> + tsens: thermal-sensor {
> + compatible = "qcom,ipq8064-tsens";
> +
> + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
> + nvmem-cell-names = "calib", "calib_backup";
> + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "uplow";
> +
> + #qcom,sensors = <11>;
> + #thermal-sensor-cells = <1>;
> + };
> + };
> --
> 2.33.1
>
>
^ permalink raw reply
* Re: [PATCH v2 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
From: Rob Herring @ 2022-01-21 2:01 UTC (permalink / raw)
To: Ansuel Smith
Cc: devicetree, Taniya Das, linux-kernel, Bjorn Andersson,
Stephen Boyd, Michael Turquette, linux-arm-msm, Andy Gross,
linux-clk, Philipp Zabel
In-Reply-To: <61ea0f73.1c69fb81.44cb7.5093@mx.google.com>
On Fri, Jan 21, 2022 at 02:41:59AM +0100, Ansuel Smith wrote:
> On Thu, Jan 20, 2022 at 07:37:38PM -0600, Rob Herring wrote:
> > On Fri, 21 Jan 2022 00:20:15 +0100, Ansuel Smith wrote:
> > > Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a
> > > template.
> > >
> > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > > ---
> > > .../bindings/clock/qcom,gcc-apq8064.yaml | 27 +++----------------
> > > 1 file changed, 3 insertions(+), 24 deletions(-)
> > >
> >
> > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> >
> > yamllint warnings/errors:
> >
> > dtschema/dtc warnings/errors:
> > Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.example.dt.yaml:0:0: /example-0/clock-controller@900000: failed to match any schema with compatible: ['qcom,gcc-apq8064']
> >
> > doc reference errors (make refcheckdocs):
> >
> > See https://patchwork.ozlabs.org/patch/1582347
> >
> > This check can fail if there are any dependencies. The base for a patch
> > series is generally the most recent rc1.
> >
> > If you already ran 'make dt_binding_check' and didn't see the above
> > error(s), then make sure 'yamllint' is installed and dt-schema is up to
> > date:
> >
> > pip3 install dtschema --upgrade
> >
> > Please check and re-submit.
> >
>
> Mhh, think these error comes from running the bot with the single change.
> Or the bot runs the test with the previous commits merged?
It should apply the whole series one by one. However, if patch 1 didn't
apply it will still try the rest. It's only smart enough to apply to the
last rc1. Given it's the merge window, I suspect you have dependency in the
next rc1.
Rob
^ permalink raw reply
* Re: [PATCH v4 2/3] dt-bindings: Add dma-channels for pdma device node
From: Zong Li @ 2022-01-21 1:57 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Rob Herring, Paul Walmsley, Albert Ou, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Bin Meng, Green Wan, Vinod,
dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org List, linux-riscv
In-Reply-To: <mhng-e5e649a2-96bf-4244-a29a-a75c913111a2@palmer-ri-x1c9>
On Fri, Jan 21, 2022 at 2:51 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Sun, 16 Jan 2022 17:35:27 PST (-0800), zong.li@sifive.com wrote:
> > Add dma-channels property, then we can determine how many channels there
> > by device tree, rather than statically defines it in PDMA driver
>
> Maybe "statically defining it" is better here?
>
Thanks for the correction, I would modify it in the next version.
> >
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> > .../devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
> > index d32a71b975fe..3dbb8caefc17 100644
> > --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
> > +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
> > @@ -34,6 +34,12 @@ properties:
> > minItems: 1
> > maxItems: 8
> >
> > + dma-channels:
> > + description: For backwards-compatible, the default value is 4
>
> Maybe "backwards-compatibility" is better here?
Thanks, let me change it in the next version together.
>
> > + minimum: 1
> > + maximum: 4
> > + default: 4
> > +
> > '#dma-cells':
> > const: 1
> >
> > @@ -50,6 +56,7 @@ examples:
> > dma@3000000 {
> > compatible = "sifive,fu540-c000-pdma";
>
> IMO we should have a "sifive,pdma-1.0.0" (or whatever the versioning
> scheme ended up being) here, in addition to the SOC-specific DT entry.
> It's kind of odd to start extending the SOC-specific DT entry, as the
> whole idea there is to let us have an out in case we find future
> compatibility issues.
yes, I notice that we usually have a entry with the version in other
device nodes, such as "sifive,xxx0", I guess we should have a
"sifive,pdma0" there, thanks for your advice, let me add it and use it
in match table of pdma driver in the next version.
>
> > reg = <0x3000000 0x8000>;
> > + dma-channels = <4>;
> > interrupts = <23 24 25 26 27 28 29 30>;
> > #dma-cells = <1>;
> > };
^ permalink raw reply
* Re: [PATCH v2 01/15] dt-bindings: clock: permit additionalProprieties to qcom,gcc
From: Rob Herring @ 2022-01-21 1:53 UTC (permalink / raw)
To: Ansuel Smith
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Philipp Zabel, Taniya Das, linux-arm-msm, linux-clk, devicetree,
linux-kernel
In-Reply-To: <20220120232028.6738-2-ansuelsmth@gmail.com>
On Fri, Jan 21, 2022 at 12:20:14AM +0100, Ansuel Smith wrote:
> To permit the use of qcom,gcc as a template for other Documentation, set
> additionalProprieties to true.
> While at it add the missing syscon for qcom,ipq8064 that is mandatory
> for the correct function of the tsens driver.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> .../devicetree/bindings/clock/qcom,gcc.yaml | 41 ++++++++++---------
> 1 file changed, 22 insertions(+), 19 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> index f66d703bd913..3fd03687a6f7 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> @@ -36,24 +36,27 @@ description: |
>
> properties:
> compatible:
> - enum:
> - - qcom,gcc-apq8084
> - - qcom,gcc-ipq4019
> - - qcom,gcc-ipq6018
> - - qcom,gcc-ipq8064
> - - qcom,gcc-mdm9607
> - - qcom,gcc-msm8226
> - - qcom,gcc-msm8660
> - - qcom,gcc-msm8916
> - - qcom,gcc-msm8939
> - - qcom,gcc-msm8953
> - - qcom,gcc-msm8960
> - - qcom,gcc-msm8974
> - - qcom,gcc-msm8974pro
> - - qcom,gcc-msm8974pro-ac
> - - qcom,gcc-mdm9615
> - - qcom,gcc-sdm630
> - - qcom,gcc-sdm660
> + oneOf:
> + - enum:
> + - qcom,gcc-apq8084
> + - qcom,gcc-ipq4019
> + - qcom,gcc-ipq6018
> + - qcom,gcc-mdm9607
> + - qcom,gcc-msm8226
> + - qcom,gcc-msm8660
> + - qcom,gcc-msm8916
> + - qcom,gcc-msm8939
> + - qcom,gcc-msm8953
> + - qcom,gcc-msm8960
> + - qcom,gcc-msm8974
> + - qcom,gcc-msm8974pro
> + - qcom,gcc-msm8974pro-ac
> + - qcom,gcc-mdm9615
> + - qcom,gcc-sdm630
> + - qcom,gcc-sdm660
> + - items:
> + - const: qcom,gcc-ipq8064
> + - const: syscon
>
> '#clock-cells':
> const: 1
> @@ -78,7 +81,7 @@ required:
> - '#reset-cells'
> - '#power-domain-cells'
>
> -additionalProperties: false
> +additionalProperties: true
This doesn't work. You just allowed any other property to be allowed for
all these devices. If you need something shared, you have to create a
common base schema that's referenced by other schemas. Minimally, those
would look like this:
$ref: /to/base/schema.yaml
unevaluatedProperties: false
properties:
compatible:
...
Rob
^ permalink raw reply
* Re: [PATCH V4 XRT Alveo Infrastructure 3/5] of: create empty of root
From: Xu Yilun @ 2022-01-21 1:42 UTC (permalink / raw)
To: Lizhi Hou
Cc: robh, linux-kernel, linux-fpga, maxz, sonal.santan, yliu,
michal.simek, stefanos, devicetree, trix, mdf, dwmw2, Max Zhen
In-Reply-To: <72a8ee48-b38b-b72c-bcd4-78908af5d829@xilinx.com>
On Wed, Jan 19, 2022 at 10:59:48AM -0800, Lizhi Hou wrote:
> Hi Yilun,
>
> Thanks for your comments. Overall, we made the code change based on Rob's
> comments on previous patch set. Please see my inline comments for detail.
>
> Rob, please provide your guidance here.
>
> On 1/10/22 8:29 PM, Xu Yilun wrote:
> > On Wed, Jan 05, 2022 at 02:50:11PM -0800, Lizhi Hou wrote:
> > > When OF_FLATTREE is selected and there is not a device tree, create an
> > > empty device tree root node. of/unittest.c code is referenced.
> > >
> > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com>
> > > Signed-off-by: Max Zhen <max.zhen@xilinx.com>
> > > Signed-off-by: Lizhi Hou <lizhi.hou@xilinx.com>
> > > ---
> > > drivers/of/Makefile | 5 +++
> > > drivers/of/fdt.c | 90 ++++++++++++++++++++++++++++++++++++++
> > > drivers/of/fdt_default.dts | 5 +++
> > > drivers/of/of_private.h | 17 +++++++
> > > drivers/of/unittest.c | 72 ++----------------------------
> > > 5 files changed, 120 insertions(+), 69 deletions(-)
> > > create mode 100644 drivers/of/fdt_default.dts
> > >
> > > diff --git a/drivers/of/Makefile b/drivers/of/Makefile
> > > index c13b982084a3..a2989055c578 100644
> > > --- a/drivers/of/Makefile
> > > +++ b/drivers/of/Makefile
> > > @@ -1,5 +1,6 @@
> > > # SPDX-License-Identifier: GPL-2.0
> > > obj-y = base.o device.o platform.o property.o
> > > +
> > remove the blank line.
> Will remove.
> >
> > > obj-$(CONFIG_OF_KOBJ) += kobj.o
> > > obj-$(CONFIG_OF_DYNAMIC) += dynamic.o
> > > obj-$(CONFIG_OF_FLATTREE) += fdt.o
> > > @@ -20,4 +21,8 @@ obj-y += kexec.o
> > > endif
> > > endif
> > >
> > > +ifndef CONFIG_OF_UNITTEST
> > > +obj-$(CONFIG_OF_FLATTREE) += fdt_default.dtb.o
> > > +endif
> > > +
> > Same question as Tom, the unittest should work well with or without
> > of_root, is it? So creating an empty root will not affect unittest, so
> > why so many ifdefs for CONFIG_OF_UNITTEST?
>
> Based on Rob's comment in
> https://lore.kernel.org/lkml/YaWFksVvfQQWqKcG@robh.at.kernel.org/, it needs
> to have a unified code to set of_root with or without CONFIG_OF_UNITTEST
> defined. So the unified code works as this during boot
>
> 1. With CONFIG_OF_UNITEST define, of_root is set to base tree
> defined/compiled in testcases.dtb.o
>
> 2. Without CONFIG_OF_UNITEST, of_root is set to base tree defined/compiled
> in fdt_default.dtb.o
>
> >
> > > obj-$(CONFIG_OF_UNITTEST) += unittest-data/
> > > diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> > > index 4546572af24b..66ef9ac97829 100644
> > > --- a/drivers/of/fdt.c
> > > +++ b/drivers/of/fdt.c
> > > @@ -466,6 +466,96 @@ void *of_fdt_unflatten_tree(const unsigned long *blob,
> > > }
> > > EXPORT_SYMBOL_GPL(of_fdt_unflatten_tree);
> > >
> > > +static int __init of_fdt_root_init(void)
> > > +{
> > > + struct device_node *dt = NULL, *np;
> > > + void *fdt = NULL, *fdt_aligned;
> > > + struct property *prop = NULL;
> > > + __be32 *val = NULL;
> > > + int size, rc = 0;
> > > +
> > > +#if !defined(CONFIG_OF_UNITTEST)
> > > + if (of_root)
> > > + return 0;
> > > +#endif
> > > + size = __dtb_fdt_default_end - __dtb_fdt_default_begin;
> > > +
> > > + fdt = kmalloc(size + FDT_ALIGN_SIZE, GFP_KERNEL);
> > > + if (!fdt)
> > > + return -ENOMEM;
> > > +
> > > + fdt_aligned = PTR_ALIGN(fdt, FDT_ALIGN_SIZE);
> > > + memcpy(fdt_aligned, __dtb_fdt_default_begin, size);
> > > +
> > > + if (!of_fdt_unflatten_tree((const unsigned long *)fdt_aligned,
> > > + NULL, &dt)) {
> > > + pr_warn("%s: unflatten default tree failed\n", __func__);
> > > + kfree(fdt);
> > > + return -ENODATA;
> > > + }
> > > + if (!dt) {
> > > + pr_warn("%s: empty default tree\n", __func__);
> > > + kfree(fdt);
> > > + return -ENODATA;
> > > + }
> > > +
> > > + /*
> > > + * This lock normally encloses of_resolve_phandles()
> > > + */
> > > + of_overlay_mutex_lock();
> > > +
> > > + rc = of_resolve_phandles(dt);
> > > + if (rc) {
> > > + pr_err("%s: Failed to resolve phandles (rc=%i)\n", __func__, rc);
> > > + goto failed;
> > > + }
> > > +
> > > + if (!of_root) {
> > > + prop = kcalloc(2, sizeof(*prop), GFP_KERNEL);
> > > + if (!prop) {
> > > + rc = -ENOMEM;
> > > + goto failed;
> > > + }
> > > + val = kzalloc(sizeof(*val), GFP_KERNEL);
> > > + if (!val) {
> > > + rc = -ENOMEM;
> > > + goto failed;
> > > + }
> > > + *val = cpu_to_be32(sizeof(void *) / sizeof(u32));
> > > +
> > > + prop->name = "#address-cells";
> > > + prop->value = val;
> > > + prop->length = sizeof(u32);
> > > + of_add_property(dt, prop);
> > > + prop++;
> > > + prop->name = "#size-cells";
> > > + prop->value = val;
> > > + prop->length = sizeof(u32);
> > > + of_add_property(dt, prop);
> > > + of_root = dt;
> > > + for_each_of_allnodes(np)
> > > + __of_attach_node_sysfs(np);
> > > + of_aliases = of_find_node_by_path("/aliases");
> > > + of_chosen = of_find_node_by_path("/chosen");
> > > + of_overlay_mutex_unlock();
> > > +pr_info("OF ROOT FLAG %lx\n", of_root->_flags);
> > > + return 0;
> > > + }
> > > +
> > > + unittest_data_add(dt);
> > It's confusing to me. If we need to share some functions with unittest,
> > make a new clearly defined (and named) function.
>
> unittest_data_add() is not shared function. If CONFIG_OF_UNITTEST is not
> defined, this is a null function (please see of_private.h). I just followed
> the existing code style. e.g. of_property_notify() in of_private.h.
>
> Would adding some comments to describe this be good enough?
>
> >
> > > +
> > > + of_overlay_mutex_unlock();
> > > +
> > > + return 0;
> > > +
> > > +failed:
> > > + of_overlay_mutex_unlock();
> > > + kfree(val);
> > > + kfree(prop);
> > > + return rc;
> > > +}
> > > +pure_initcall(of_fdt_root_init);
> > Is it better we have a new Kconfig option for the empty tree creation.
> Sure, if needed.
> >
> > > +
> > > /* Everything below here references initial_boot_params directly. */
> > > int __initdata dt_root_addr_cells;
> > > int __initdata dt_root_size_cells;
> > > diff --git a/drivers/of/fdt_default.dts b/drivers/of/fdt_default.dts
> > > new file mode 100644
> > > index 000000000000..d1f12a76dfc6
> > > --- /dev/null
> > > +++ b/drivers/of/fdt_default.dts
> > > @@ -0,0 +1,5 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/dts-v1/;
> > > +
> > > +/ {
> > > +};
> > > diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h
> > > index 631489f7f8c0..1ef93bccfdba 100644
> > > --- a/drivers/of/of_private.h
> > > +++ b/drivers/of/of_private.h
> > > @@ -41,6 +41,18 @@ extern struct mutex of_mutex;
> > > extern struct list_head aliases_lookup;
> > > extern struct kset *of_kset;
> > >
> > > +#if defined(CONFIG_OF_UNITTEST)
> > > +extern u8 __dtb_testcases_begin[];
> > > +extern u8 __dtb_testcases_end[];
> > > +#define __dtb_fdt_default_begin __dtb_testcases_begin
> > > +#define __dtb_fdt_default_end __dtb_testcases_end
> > Maybe we don't have to use the test dt data, stick to the default empty
> > fdt is fine?
>
> I am not sure I understand the point. test dt data contains a lot test nodes
> and we should not create those nodes if CONFIG_OF_UNITTEST is not defined.
>
> Are you asking that we create empty of_root here and test nodes are created
> in unittest.c? I believe that was we tried to do with previous patch. Is
> this the same ask within your second comment?
Yes, generally this is what I mean. I think you may have some
misunderstanding for Rob's comments. My understanding is, to move the code
from unittest to the of core, refactor them and make clearly defined
functions, and let unittest call these functions.
It is generally not reasonable the core uses help functions or test data
from unittest.
>
> We are open to change it back as previous patch does if needed.
>
> Rob, do you have any comment here?
>
> >
> > > +void __init unittest_data_add(struct device_node *dt);
> > > +#else
> > > +extern u8 __dtb_fdt_default_begin[];
> > > +extern u8 __dtb_fdt_default_end[];
> > > +static inline void unittest_data_add(struct device_node *dt) {}
> > > +#endif
> > > +
> > > #if defined(CONFIG_OF_DYNAMIC)
> > > extern int of_property_notify(int action, struct device_node *np,
> > > struct property *prop, struct property *old_prop);
> > > @@ -84,6 +96,11 @@ static inline void __of_detach_node_sysfs(struct device_node *np) {}
> > >
> > > #if defined(CONFIG_OF_RESOLVE)
> > > int of_resolve_phandles(struct device_node *tree);
> > > +#else
> > > +static inline int of_resolve_phandles(struct device_node *tree)
> > > +{
> > > + return 0;
> > > +}
> > If we have an empty of_resolve_phandles, does the empty tree creation
> > still works? Or if we don't need this func, just delete in the code.
>
> test nodes creation requires of_resolve_phandles() and creating empty
> of_root does not. This define is added for unifying the code.
If you don't need the of_resolve_phandles in core code, don't call it.
Thanks,
Yilun
>
>
> Thanks,
>
> Lizhi
>
> >
> > Thanks,
> > Yilun
> >
> > > #endif
> > >
> > > void __of_phandle_cache_inv_entry(phandle handle);
> > > diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
> > > index 8c056972a6dd..745f455235cc 100644
> > > --- a/drivers/of/unittest.c
> > > +++ b/drivers/of/unittest.c
> > > @@ -1402,73 +1402,15 @@ static void attach_node_and_children(struct device_node *np)
> > > * unittest_data_add - Reads, copies data from
> > > * linked tree and attaches it to the live tree
> > > */
> > > -static int __init unittest_data_add(void)
> > > +void __init unittest_data_add(struct device_node *dt)
> > > {
> > > - void *unittest_data;
> > > - void *unittest_data_align;
> > > - struct device_node *unittest_data_node = NULL, *np;
> > > - /*
> > > - * __dtb_testcases_begin[] and __dtb_testcases_end[] are magically
> > > - * created by cmd_dt_S_dtb in scripts/Makefile.lib
> > > - */
> > > - extern uint8_t __dtb_testcases_begin[];
> > > - extern uint8_t __dtb_testcases_end[];
> > > - const int size = __dtb_testcases_end - __dtb_testcases_begin;
> > > - int rc;
> > > - void *ret;
> > > -
> > > - if (!size) {
> > > - pr_warn("%s: testcases is empty\n", __func__);
> > > - return -ENODATA;
> > > - }
> > > -
> > > - /* creating copy */
> > > - unittest_data = kmalloc(size + FDT_ALIGN_SIZE, GFP_KERNEL);
> > > - if (!unittest_data)
> > > - return -ENOMEM;
> > > -
> > > - unittest_data_align = PTR_ALIGN(unittest_data, FDT_ALIGN_SIZE);
> > > - memcpy(unittest_data_align, __dtb_testcases_begin, size);
> > > -
> > > - ret = of_fdt_unflatten_tree(unittest_data_align, NULL, &unittest_data_node);
> > > - if (!ret) {
> > > - pr_warn("%s: unflatten testcases tree failed\n", __func__);
> > > - kfree(unittest_data);
> > > - return -ENODATA;
> > > - }
> > > - if (!unittest_data_node) {
> > > - pr_warn("%s: testcases tree is empty\n", __func__);
> > > - kfree(unittest_data);
> > > - return -ENODATA;
> > > - }
> > > -
> > > - /*
> > > - * This lock normally encloses of_resolve_phandles()
> > > - */
> > > - of_overlay_mutex_lock();
> > > -
> > > - rc = of_resolve_phandles(unittest_data_node);
> > > - if (rc) {
> > > - pr_err("%s: Failed to resolve phandles (rc=%i)\n", __func__, rc);
> > > - of_overlay_mutex_unlock();
> > > - return -EINVAL;
> > > - }
> > > -
> > > - if (!of_root) {
> > > - of_root = unittest_data_node;
> > > - for_each_of_allnodes(np)
> > > - __of_attach_node_sysfs(np);
> > > - of_aliases = of_find_node_by_path("/aliases");
> > > - of_chosen = of_find_node_by_path("/chosen");
> > > - of_overlay_mutex_unlock();
> > > - return 0;
> > > - }
> > > + struct device_node *np;
> > >
> > > EXPECT_BEGIN(KERN_INFO,
> > > "Duplicate name in testcase-data, renamed to \"duplicate-name#1\"");
> > >
> > > /* attach the sub-tree to live tree */
> > > - np = unittest_data_node->child;
> > > + np = dt->child;
> > > while (np) {
> > > struct device_node *next = np->sibling;
> > >
> > > @@ -1479,10 +1421,6 @@ static int __init unittest_data_add(void)
> > >
> > > EXPECT_END(KERN_INFO,
> > > "Duplicate name in testcase-data, renamed to \"duplicate-name#1\"");
> > > -
> > > - of_overlay_mutex_unlock();
> > > -
> > > - return 0;
> > > }
> > >
> > > #ifdef CONFIG_OF_OVERLAY
> > > @@ -3258,7 +3196,6 @@ static inline __init void of_unittest_overlay_high_level(void) {}
> > > static int __init of_unittest(void)
> > > {
> > > struct device_node *np;
> > > - int res;
> > >
> > > pr_info("start of unittest - you will see error messages\n");
> > >
> > > @@ -3267,9 +3204,6 @@ static int __init of_unittest(void)
> > > if (IS_ENABLED(CONFIG_UML))
> > > unittest_unflatten_overlay_base();
> > >
> > > - res = unittest_data_add();
> > > - if (res)
> > > - return res;
> > > if (!of_aliases)
> > > of_aliases = of_find_node_by_path("/aliases");
> > >
> > > --
> > > 2.27.0
^ permalink raw reply
* Re: [RFC PATCH 1/2] dt-bindings: mtd: partitions: Document new dynamic-partitions node
From: Rob Herring @ 2022-01-21 1:49 UTC (permalink / raw)
To: Ansuel Smith
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra, linux-mtd,
devicetree, linux-kernel
In-Reply-To: <20220120202615.28076-2-ansuelsmth@gmail.com>
On Thu, Jan 20, 2022 at 09:26:14PM +0100, Ansuel Smith wrote:
> Document new dynamic-partitions node used to provide an of node for
> partition registred at runtime by parsers. This is required for nvmem
> system to declare and detect nvmem-cells.
So you have some discoverable way to find all the partitions and the
nvmem cells are at an unknown (to the DT) location, but still need to be
described in DT?
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> .../mtd/partitions/dynamic-partitions.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
>
> diff --git a/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml b/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
> new file mode 100644
> index 000000000000..7528e49f2d7e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/partitions/dynamic-partitions.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Dynamic partitions
> +
> +description: |
> + This binding can be used on platforms which have partitions registered at
> + runtime by parsers or partition table present on the flash. Example are
> + partitions declared from smem parser or cmdlinepart. This will create an
Some information in DT and some on the cmdline seems broken to me. Pick
one or the other.
> + of node for these dynamic partition where systems like Nvmem can get a
> + reference to register nvmem-cells.
> +
> + The partition table should be a node named "dynamic-partitions".
> + Partitions are then defined as subnodes. Only the label is required
> + as any other data will be taken from the parser.
> +
> +maintainers:
> + - Ansuel Smith <ansuelsmth@gmail.com>
> +
> +properties:
> + compatible:
> + const: dynamic-partitions
This is useless. This tells me nothing about the what's in the
partitions.
> +
> +patternProperties:
> + "@[0-9a-f]+$":
> + $ref: "partition.yaml#"
> +
> +additionalProperties: true
> +
> +examples:
> + - |
> + partitions {
> + compatible = "qcom,smem";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +
> + dynamic-partitions {
> + compatible = "dynamic-partitions";
> +
> + art: art {
> + label = "0:art";
> + read-only;
> + compatible = "nvmem-cells";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + macaddr_art_0: macaddr@0 {
> + reg = <0x0 0x6>;
> + };
> +
> + macaddr_art_6: macaddr@6 {
> + reg = <0x6 0x6>;
> + };
> + };
> + };
> --
> 2.33.1
>
>
^ permalink raw reply
* RE: [EXT] Re: [PATCH v14 00/13] amphion video decoder/encoder driver
From: Ming Qian @ 2022-01-21 1:48 UTC (permalink / raw)
To: Hans Verkuil, mchehab@kernel.org, shawnguo@kernel.org,
robh+dt@kernel.org, s.hauer@pengutronix.de
Cc: kernel@pengutronix.de, festevam@gmail.com, dl-linux-imx,
Aisheng Dong, linux-media@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <d0540f65-ccc8-cfc8-d5c6-8dc40603b18d@xs4all.nl>
> -----Original Message-----
> From: Hans Verkuil [mailto:hverkuil-cisco@xs4all.nl]
> Sent: Thursday, January 20, 2022 10:44 PM
> To: Ming Qian <ming.qian@nxp.com>; mchehab@kernel.org;
> shawnguo@kernel.org; robh+dt@kernel.org; s.hauer@pengutronix.de
> Cc: kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx
> <linux-imx@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>;
> linux-media@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: [EXT] Re: [PATCH v14 00/13] amphion video decoder/encoder driver
>
> Caution: EXT Email
>
> Hi Ming,
>
> Running 'scripts/checkpatch.pl --strict' over the patches gives me lots of issues,
> most of them easily fixed.
>
> As always with checkpatch, use common sense since not everything can be
> fixed.
>
> You probably ran checkpatch.pl without the --strict option, but in the media
> subsystem we use that option.
>
> Note that sparse and smatch are happy, so it is just the checkpatch issues that
> need to be improved.
Yes, I just run checkpatch.pl without the --strict option,
I'll fix the issues in v15.
>
> On 12/7/21 09:24, Ming Qian wrote:
> > Hi all,
> >
> > This patch series adds support for
> > the amphion video encoder and decoder
> > via the VPU block present in imx8q platforms.
> > Currently, support for IMX8QXP and IMX8QM is included.
> >
> > It features decoding for the following formats:
> > - H.264
> > - HEVC
> > - MPEG4
> > - MPEG2
> > - VC1
> > - VP8
> >
> > It features encoding for the following formats:
> > - H.264
> >
> > The driver creates a separate device node for the encoder and decoder.
> >
> > This driver is dependent on vpu firmwares.
> > The firmwares have been submitted to linux-firmware.
> > The firmware patch is since commit
> > b563148fd28623f6b6ce68bb06c3dd3bd138b058:
> > linux-firmware: Update firmware file for Intel Bluetooth 9462 (Fri Oct
> > 8 16:30:14 2021 +0530)
> >
> > and it's available in the git repository at:
> >
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> >
> ub.com%2Fmingqian-0%2Flinux-firmware.git&data=04%7C01%7Cming.qi
> an%
> >
> 40nxp.com%7Ce806f02c9c204fab735408d9dc235f55%7C686ea1d3bc2b4c6fa
> 92cd99
> >
> c5c301635%7C0%7C1%7C637782866747675249%7CUnknown%7CTWFpbGZ
> sb3d8eyJWIjo
> >
> iMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C300
> 0&
> > ;sdata=tGdn4wXog4281rkjx%2FkS5Yu995uf1dKk%2B%2Fw7g%2B4hiCc%3D
> &rese
> > rved=0
> >
> > for you to fetch changes up to
> bb3eee4f99589d4910dee4c053a3a685546b5dbb:
> > amphion: add VPU firmwares for NXP i.MX8Q SoCs (Tue Oct 12 15:09:57
> > 2021 +0800)
> >
> > encoder is tested with gstreamer
> > decoder is tested with gstreamer, but the following patches are required:
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitl
> >
> ab.freedesktop.org%2Fgstreamer%2Fgstreamer%2F-%2Fmerge_requests%2F1
> 379
> >
> &data=04%7C01%7Cming.qian%40nxp.com%7Ce806f02c9c204fab73540
> 8d9dc23
> >
> 5f55%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C63778286674
> 7675249%7
> >
> CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT
> iI6Ik1
> >
> haWwiLCJXVCI6Mn0%3D%7C3000&sdata=Z%2B28N2DXrRHm1PFwWrpk
> 0koOSTVdqrm
> > qqY6fKbJuh34%3D&reserved=0
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitl
> >
> ab.freedesktop.org%2Fgstreamer%2Fgstreamer%2F-%2Fmerge_requests%2F1
> 381
> >
> &data=04%7C01%7Cming.qian%40nxp.com%7Ce806f02c9c204fab73540
> 8d9dc23
> >
> 5f55%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C63778286674
> 7675249%7
> >
> CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT
> iI6Ik1
> >
> haWwiLCJXVCI6Mn0%3D%7C3000&sdata=jitq4XO15%2BMux3jyVYGs0fp
> Lwxr7hbv
> > WAZad9TEGyso%3D&reserved=0
> >
> >
> > Tested-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
>
> For v15 please add this tag from Nicolas to the patch(es) that it applies to.
> Tags in the cover letter are ignored.cd
>
> Regarding patch 12/13 (firmware patch): who will take that? I think it should
> go through Shawn Guo, or if he can Ack it, then I can take it with the rest of
> the series as well.
>
> Regards,
>
> Hans
>
> >
> >
> > Changelog:
> >
> > v14
> > - fix some errors according to Hans's comments
> >
> > v13
> > - make a workaround that avoid firmware entering wfi wrongly
> >
> > v12
> > - support reset decoder when starting a new stream
> > - don't append an empty last buffer, set last_buffer_dequeued
> > - improve the resolution change flow
> > - return all buffers if start_streaming fail
> > - fill encoder capture buffer's filed to none
> > - fix a bug in calculating bytesperline
> >
> > v11
> > - fix dt_binding_check error after upgrade dtschema
> > - remove "default y"
> > - add media device
> >
> > v10
> > - refine vpu log, remove custom logging infrastructure
> > - support non contiguous planes format nv12m instead of nv12
> > - rename V4L2_PIX_FMT_NV12_8L128 to V4L2_PIX_FMT_NV12MT_8L128
> > - rename V4L2_PIX_FMT_NV12_10BE_8L128 to
> > V4L2_PIX_FMT_NV12MT_10BE_8L128
> > - merge two module into one
> > - fix kernel panic in rmmod
> >
> > v9
> > - drop V4L2_BUF_FLAG_CODECCONFIG
> > - drop V4L2_EVENT_CODEC_ERROR
> > - drop V4L2_EVENT_SKIP - use the v4l2_buffer.sequence counter
> > - fix some build warnings with W=1 reported by kernel test robot
> >
> > v8
> > - move driver from driver/media/platform/imx/vpu-8q to
> > driver/media/platform/amphion
> > - rename driver name to amphion
> > - remove imx_vpu.h
> > - move the definition of V4L2_EVENT_CODEC_ERROR to videodev2.h
> > - move the definition of V4L2_EVENT_SKIP to videodev2.h
> >
> > v7
> > - fix build warnings with W=1 reported by kernel test robot
> >
> > v6:
> > - rename V4L2_PIX_FMT_NT8 to V4L2_PIX_FMT_NV12_8L128
> > - rename V4L2_PIX_FMT_NT10 to V4L2_PIX_FMT_NV12_10BE_8L128
> >
> > v5:
> > - move some definition from imx_vph.h to videodev2.h
> > - remove some unnecessary content
> > - add some documentation descriptions
> > - pass the lateset v4l2-compliance test
> >
> > v4:
> > - redefine the memory-region in devicetree bindings documentation
> > - use v4l2's mechanism to implement synchronize queuing ioctl
> > - remove the unnecessary mutex ioctl_sync
> > - don't notify source change event if the parameters are same as
> > previously established
> > - add flag V4L2_FMT_FLAG_DYN_RESOLUTION to decoder's capture format
> >
> > v3:
> > - don't make vpu device node a simple-bus
> > - trigger probing vpu core in the driver
> > - remove unnecessary vpu core index property
> >
> > v2:
> > - fix dt bindings build error
> > - split driver patch into several parts to avoid exceeding bytes limit
> >
> > Compliance
> > ==========
> > # v4l2-compliance -d /dev/video0
> > v4l2-compliance 1.21.0-4859, 64 bits, 64-bit time_t v4l2-compliance
> > SHA: 493af03f3c57 2021-10-08 17:23:11
> >
> > Compliance test for amphion-vpu device /dev/video0:
> >
> > Driver Info:
> > Driver name : amphion-vpu
> > Card type : amphion vpu decoder
> > Bus info : platform: amphion-vpu
> > Driver version : 5.15.0
> > Capabilities : 0x84204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
> > Device Capabilities
> > Device Caps : 0x04204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
> > Detected Stateful Decoder
> > Media Driver Info:
> > Driver name : amphion-vpu
> > Model : amphion-vpu
> > Serial :
> > Bus info : platform: amphion-vpu
> > Media version : 5.15.0
> > Hardware revision: 0x00000000 (0)
> > Driver version : 5.15.0
> > Interface Info:
> > ID : 0x0300000c
> > Type : V4L Video
> > Entity Info:
> > ID : 0x00000001 (1)
> > Name : amphion-vpu-decoder-source
> > Function : V4L2 I/O
> > Pad 0x01000002 : 0: Source
> > Link 0x02000008: to remote pad 0x1000004 of entity
> > 'amphion-vpu-decoder-proc' (Video Decoder): Data, Enabled, Immutable
> >
> > Required ioctls:
> > test MC information (see 'Media Driver Info' above): OK
> > test VIDIOC_QUERYCAP: OK
> > test invalid ioctls: OK
> >
> > Allow for multiple opens:
> > test second /dev/video0 open: OK
> > test VIDIOC_QUERYCAP: OK
> > test VIDIOC_G/S_PRIORITY: OK
> > test for unlimited opens: OK
> >
> > Debug ioctls:
> > test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> > test VIDIOC_LOG_STATUS: OK (Not Supported)
> >
> > Input ioctls:
> > test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> > test VIDIOC_ENUMAUDIO: OK (Not Supported)
> > test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDIO: OK (Not Supported)
> > Inputs: 0 Audio Inputs: 0 Tuners: 0
> >
> > Output ioctls:
> > test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> > test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> > Outputs: 0 Audio Outputs: 0 Modulators: 0
> >
> > Input/Output configuration ioctls:
> > test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> > test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> > test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> > test VIDIOC_G/S_EDID: OK (Not Supported)
> >
> > Control ioctls:
> > test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> > test VIDIOC_QUERYCTRL: OK
> > test VIDIOC_G/S_CTRL: OK
> > test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> > test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> > test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> > Standard Controls: 3 Private Controls: 0
> >
> > Format ioctls:
> > test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> > test VIDIOC_G/S_PARM: OK (Not Supported)
> > test VIDIOC_G_FBUF: OK (Not Supported)
> > test VIDIOC_G_FMT: OK
> > test VIDIOC_TRY_FMT: OK
> > test VIDIOC_S_FMT: OK
> > test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> > test Cropping: OK (Not Supported)
> > test Composing: OK
> > test Scaling: OK (Not Supported)
> >
> > Codec ioctls:
> > test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> > test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> > test VIDIOC_(TRY_)DECODER_CMD: OK
> >
> > Buffer ioctls:
> > test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> > test VIDIOC_EXPBUF: OK
> > test Requests: OK (Not Supported)
> >
> > Total for amphion-vpu device /dev/video0: 46, Succeeded: 46, Failed:
> > 0, Warnings: 0
> >
> > # v4l2-compliance -d /dev/video1
> > v4l2-compliance 1.21.0-4859, 64 bits, 64-bit time_t v4l2-compliance
> > SHA: 493af03f3c57 2021-10-08 17:23:11
> >
> > Compliance test for amphion-vpu device /dev/video1:
> >
> > Driver Info:
> > Driver name : amphion-vpu
> > Card type : amphion vpu encoder
> > Bus info : platform: amphion-vpu
> > Driver version : 5.15.0
> > Capabilities : 0x84204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
> > Device Capabilities
> > Device Caps : 0x04204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
> > Detected Stateful Encoder
> > Media Driver Info:
> > Driver name : amphion-vpu
> > Model : amphion-vpu
> > Serial :
> > Bus info : platform: amphion-vpu
> > Media version : 5.15.0
> > Hardware revision: 0x00000000 (0)
> > Driver version : 5.15.0
> > Interface Info:
> > ID : 0x0300001a
> > Type : V4L Video
> > Entity Info:
> > ID : 0x0000000f (15)
> > Name : amphion-vpu-encoder-source
> > Function : V4L2 I/O
> > Pad 0x01000010 : 0: Source
> > Link 0x02000016: to remote pad 0x1000012 of entity
> > 'amphion-vpu-encoder-proc' (Video Encoder): Data, Enabled, Immutable
> >
> > Required ioctls:
> > test MC information (see 'Media Driver Info' above): OK
> > test VIDIOC_QUERYCAP: OK
> > test invalid ioctls: OK
> >
> > Allow for multiple opens:
> > test second /dev/video1 open: OK
> > test VIDIOC_QUERYCAP: OK
> > test VIDIOC_G/S_PRIORITY: OK
> > test for unlimited opens: OK
> >
> > Debug ioctls:
> > test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> > test VIDIOC_LOG_STATUS: OK (Not Supported)
> >
> > Input ioctls:
> > test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> > test VIDIOC_ENUMAUDIO: OK (Not Supported)
> > test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDIO: OK (Not Supported)
> > Inputs: 0 Audio Inputs: 0 Tuners: 0
> >
> > Output ioctls:
> > test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> > test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> > Outputs: 0 Audio Outputs: 0 Modulators: 0
> >
> > Input/Output configuration ioctls:
> > test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> > test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> > test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> > test VIDIOC_G/S_EDID: OK (Not Supported)
> >
> > Control ioctls:
> > test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> > test VIDIOC_QUERYCTRL: OK
> > test VIDIOC_G/S_CTRL: OK
> > test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> > test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> > test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> > Standard Controls: 20 Private Controls: 0
> >
> > Format ioctls:
> > test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> > test VIDIOC_G/S_PARM: OK
> > test VIDIOC_G_FBUF: OK (Not Supported)
> > test VIDIOC_G_FMT: OK
> > test VIDIOC_TRY_FMT: OK
> > test VIDIOC_S_FMT: OK
> > test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> > test Cropping: OK
> > test Composing: OK (Not Supported)
> > test Scaling: OK (Not Supported)
> >
> > Codec ioctls:
> > test VIDIOC_(TRY_)ENCODER_CMD: OK
> > test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> > test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
> >
> > Buffer ioctls:
> > test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> > test VIDIOC_EXPBUF: OK
> > test Requests: OK (Not Supported)
> >
> > Total for amphion-vpu device /dev/video1: 46, Succeeded: 46, Failed:
> > 0, Warnings: 0
> >
> > # v4l2-compliance -d /dev/media0
> > v4l2-compliance 1.21.0-4859, 64 bits, 64-bit time_t v4l2-compliance
> > SHA: 493af03f3c57 2021-10-08 17:23:11
> >
> > Compliance test for amphion-vpu device /dev/media0:
> >
> > Media Driver Info:
> > Driver name : amphion-vpu
> > Model : amphion-vpu
> > Serial :
> > Bus info : platform: amphion-vpu
> > Media version : 5.15.0
> > Hardware revision: 0x00000000 (0)
> > Driver version : 5.15.0
> >
> > Required ioctls:
> > test MEDIA_IOC_DEVICE_INFO: OK
> > test invalid ioctls: OK
> >
> > Allow for multiple opens:
> > test second /dev/media0 open: OK
> > test MEDIA_IOC_DEVICE_INFO: OK
> > test for unlimited opens: OK
> >
> > Media Controller ioctls:
> > test MEDIA_IOC_G_TOPOLOGY: OK
> > Entities: 6 Interfaces: 2 Pads: 8 Links: 8
> > test MEDIA_IOC_ENUM_ENTITIES/LINKS: OK
> > test MEDIA_IOC_SETUP_LINK: OK
> >
> > Total for amphion-vpu device /dev/media0: 8, Succeeded: 8, Failed: 0,
> > Warnings: 0
> >
> > Ming Qian (13):
> > dt-bindings: media: amphion: add amphion video codec bindings
> > media: add nv12m_8l128 and nv12m_10be_8l128 video format.
> > media: amphion: add amphion vpu device driver
> > media: amphion: add vpu core driver
> > media: amphion: implement vpu core communication based on mailbox
> > media: amphion: add vpu v4l2 m2m support
> > media: amphion: add v4l2 m2m vpu encoder stateful driver
> > media: amphion: add v4l2 m2m vpu decoder stateful driver
> > media: amphion: implement windsor encoder rpc interface
> > media: amphion: implement malone decoder rpc interface
> > ARM64: dts: freescale: imx8q: add imx vpu codec entries
> > firmware: imx: scu-pd: imx8q: add vpu mu resources
> > MAINTAINERS: add AMPHION VPU CODEC V4L2 driver entry
> >
> > .../bindings/media/amphion,vpu.yaml | 180 ++
> > .../media/v4l/pixfmt-yuv-planar.rst | 28 +-
> > MAINTAINERS | 9 +
> > .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 72 +
> > arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 17 +
> > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 24 +
> > arch/arm64/configs/defconfig | 1 +
> > drivers/firmware/imx/scu-pd.c | 4 +
> > drivers/media/platform/Kconfig | 19 +
> > drivers/media/platform/Makefile | 2 +
> > drivers/media/platform/amphion/Makefile | 20 +
> > drivers/media/platform/amphion/vdec.c | 1692
> +++++++++++++++++
> > drivers/media/platform/amphion/venc.c | 1354 +++++++++++++
> > drivers/media/platform/amphion/vpu.h | 356 ++++
> > drivers/media/platform/amphion/vpu_cmds.c | 437 +++++
> > drivers/media/platform/amphion/vpu_cmds.h | 25 +
> > drivers/media/platform/amphion/vpu_codec.h | 67 +
> > drivers/media/platform/amphion/vpu_color.c | 186 ++
> > drivers/media/platform/amphion/vpu_core.c | 872 +++++++++
> > drivers/media/platform/amphion/vpu_core.h | 15 +
> > drivers/media/platform/amphion/vpu_dbg.c | 497 +++++
> > drivers/media/platform/amphion/vpu_defs.h | 186 ++
> > drivers/media/platform/amphion/vpu_drv.c | 260 +++
> > drivers/media/platform/amphion/vpu_helpers.c | 416 ++++
> > drivers/media/platform/amphion/vpu_helpers.h | 70 +
> > drivers/media/platform/amphion/vpu_imx8q.c | 271 +++
> > drivers/media/platform/amphion/vpu_imx8q.h | 116 ++
> > drivers/media/platform/amphion/vpu_malone.c | 1630
> ++++++++++++++++
> > drivers/media/platform/amphion/vpu_malone.h | 42 +
> > drivers/media/platform/amphion/vpu_mbox.c | 118 ++
> > drivers/media/platform/amphion/vpu_mbox.h | 16 +
> > drivers/media/platform/amphion/vpu_msgs.c | 388 ++++
> > drivers/media/platform/amphion/vpu_msgs.h | 14 +
> > drivers/media/platform/amphion/vpu_rpc.c | 265 +++
> > drivers/media/platform/amphion/vpu_rpc.h | 453 +++++
> > drivers/media/platform/amphion/vpu_v4l2.c | 733 +++++++
> > drivers/media/platform/amphion/vpu_v4l2.h | 56 +
> > drivers/media/platform/amphion/vpu_windsor.c | 1207 ++++++++++++
> > drivers/media/platform/amphion/vpu_windsor.h | 39 +
> > drivers/media/v4l2-core/v4l2-ioctl.c | 2 +
> > include/uapi/linux/videodev2.h | 2 +
> > 41 files changed, 12158 insertions(+), 3 deletions(-) create mode
> > 100644 Documentation/devicetree/bindings/media/amphion,vpu.yaml
> > create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
> > create mode 100644 drivers/media/platform/amphion/Makefile
> > create mode 100644 drivers/media/platform/amphion/vdec.c
> > create mode 100644 drivers/media/platform/amphion/venc.c
> > create mode 100644 drivers/media/platform/amphion/vpu.h
> > create mode 100644 drivers/media/platform/amphion/vpu_cmds.c
> > create mode 100644 drivers/media/platform/amphion/vpu_cmds.h
> > create mode 100644 drivers/media/platform/amphion/vpu_codec.h
> > create mode 100644 drivers/media/platform/amphion/vpu_color.c
> > create mode 100644 drivers/media/platform/amphion/vpu_core.c
> > create mode 100644 drivers/media/platform/amphion/vpu_core.h
> > create mode 100644 drivers/media/platform/amphion/vpu_dbg.c
> > create mode 100644 drivers/media/platform/amphion/vpu_defs.h
> > create mode 100644 drivers/media/platform/amphion/vpu_drv.c
> > create mode 100644 drivers/media/platform/amphion/vpu_helpers.c
> > create mode 100644 drivers/media/platform/amphion/vpu_helpers.h
> > create mode 100644 drivers/media/platform/amphion/vpu_imx8q.c
> > create mode 100644 drivers/media/platform/amphion/vpu_imx8q.h
> > create mode 100644 drivers/media/platform/amphion/vpu_malone.c
> > create mode 100644 drivers/media/platform/amphion/vpu_malone.h
> > create mode 100644 drivers/media/platform/amphion/vpu_mbox.c
> > create mode 100644 drivers/media/platform/amphion/vpu_mbox.h
> > create mode 100644 drivers/media/platform/amphion/vpu_msgs.c
> > create mode 100644 drivers/media/platform/amphion/vpu_msgs.h
> > create mode 100644 drivers/media/platform/amphion/vpu_rpc.c
> > create mode 100644 drivers/media/platform/amphion/vpu_rpc.h
> > create mode 100644 drivers/media/platform/amphion/vpu_v4l2.c
> > create mode 100644 drivers/media/platform/amphion/vpu_v4l2.h
> > create mode 100644 drivers/media/platform/amphion/vpu_windsor.c
> > create mode 100644 drivers/media/platform/amphion/vpu_windsor.h
> >
> >
> > base-commit: 1f1517fafda598839a02e39968c5063ddcfa51fc
^ permalink raw reply
* Re: [PATCH v2 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
From: Ansuel Smith @ 2022-01-21 1:41 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Taniya Das, linux-kernel, Bjorn Andersson,
Stephen Boyd, Rob Herring, Michael Turquette, linux-arm-msm,
Andy Gross, linux-clk, Philipp Zabel
In-Reply-To: <1642729058.530862.2314864.nullmailer@robh.at.kernel.org>
On Thu, Jan 20, 2022 at 07:37:38PM -0600, Rob Herring wrote:
> On Fri, 21 Jan 2022 00:20:15 +0100, Ansuel Smith wrote:
> > Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a
> > template.
> >
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> > .../bindings/clock/qcom,gcc-apq8064.yaml | 27 +++----------------
> > 1 file changed, 3 insertions(+), 24 deletions(-)
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.example.dt.yaml:0:0: /example-0/clock-controller@900000: failed to match any schema with compatible: ['qcom,gcc-apq8064']
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/patch/1582347
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
>
Mhh, think these error comes from running the bot with the single change.
Or the bot runs the test with the previous commits merged?
I don't have these errors on my system with make dt_binding_check.
--
Ansuel
^ permalink raw reply
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