* [PATCH v8 2/4] phy: dt-bindings: Convert Cadence DPHY binding to YAML
From: Pratyush Yadav @ 2022-01-21 9:38 UTC (permalink / raw)
To: Vinod Koul
Cc: Pratyush Yadav, Laurent Pinchart, Paul Kocialkowski,
Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I,
Rob Herring, Swapnil Jakhade, devicetree, linux-kernel, linux-phy
In-Reply-To: <20220121093849.3218092-1-p.yadav@ti.com>
Convert Cadence DPHY binding to YAML.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
(no changes since v3)
Changes in v3:
- Add Rob's R-by.
Changes in v2:
- Drop reg description.
- Add a description for each DPHY clock.
- Rename dphy@... to phy@... in example.
- Add Laurent's R-by.
- Re-order subject prefixes.
.../devicetree/bindings/phy/cdns,dphy.txt | 20 --------
.../devicetree/bindings/phy/cdns,dphy.yaml | 51 +++++++++++++++++++
2 files changed, 51 insertions(+), 20 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt
create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml
diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.txt b/Documentation/devicetree/bindings/phy/cdns,dphy.txt
deleted file mode 100644
index 1095bc4e72d9..000000000000
--- a/Documentation/devicetree/bindings/phy/cdns,dphy.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Cadence DPHY
-============
-
-Cadence DPHY block.
-
-Required properties:
-- compatible: should be set to "cdns,dphy".
-- reg: physical base address and length of the DPHY registers.
-- clocks: DPHY reference clocks.
-- clock-names: must contain "psm" and "pll_ref".
-- #phy-cells: must be set to 0.
-
-Example:
- dphy0: dphy@fd0e0000{
- compatible = "cdns,dphy";
- reg = <0x0 0xfd0e0000 0x0 0x1000>;
- clocks = <&psm_clk>, <&pll_ref_clk>;
- clock-names = "psm", "pll_ref";
- #phy-cells = <0>;
- };
diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
new file mode 100644
index 000000000000..b90a58773bf2
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence DPHY Device Tree Bindings
+
+maintainers:
+ - Pratyush Yadav <p.yadav@ti.com>
+
+properties:
+ compatible:
+ items:
+ - const: cdns,dphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PMA state machine clock
+ - description: PLL reference clock
+
+ clock-names:
+ items:
+ - const: psm
+ - const: pll_ref
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+
+ dphy0: phy@fd0e0000{
+ compatible = "cdns,dphy";
+ reg = <0xfd0e0000 0x1000>;
+ clocks = <&psm_clk>, <&pll_ref_clk>;
+ clock-names = "psm", "pll_ref";
+ #phy-cells = <0>;
+ };
--
2.25.1
^ permalink raw reply related
* [PATCH v8 3/4] phy: dt-bindings: cdns,dphy: add power-domains property
From: Pratyush Yadav @ 2022-01-21 9:38 UTC (permalink / raw)
To: Vinod Koul
Cc: Pratyush Yadav, Laurent Pinchart, Paul Kocialkowski,
Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I,
Rob Herring, Swapnil Jakhade, devicetree, linux-kernel, linux-phy
In-Reply-To: <20220121093849.3218092-1-p.yadav@ti.com>
This property is needed on TI platforms to enable the PD of the DPHY
before it can be used.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Rob Herring <robh@kernel.org>
---
(no changes since v3)
Changes in v3:
- Add Rob's Ack.
Changes in v2:
- Add power-domain to the example.
- Add Laurent's R-by.
- Re-order subject prefixes.
Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
index b90a58773bf2..c50629bd1b51 100644
--- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
@@ -30,6 +30,9 @@ properties:
"#phy-cells":
const: 0
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -41,11 +44,13 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
dphy0: phy@fd0e0000{
compatible = "cdns,dphy";
reg = <0xfd0e0000 0x1000>;
clocks = <&psm_clk>, <&pll_ref_clk>;
clock-names = "psm", "pll_ref";
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
#phy-cells = <0>;
};
--
2.25.1
^ permalink raw reply related
* [PATCH v8 0/4] Rx mode support for Cadence DPHY
From: Pratyush Yadav @ 2022-01-21 9:38 UTC (permalink / raw)
To: Vinod Koul
Cc: Pratyush Yadav, Laurent Pinchart, Paul Kocialkowski,
Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I,
Rob Herring, Swapnil Jakhade, devicetree, linux-kernel, linux-phy
Hi,
This series adds support for Cadence DPHY Rx driver. It has been split
off from [0] to facilitate easier merging. I have still kept the version
number to maintain continuity with the previous patches. The earlier
version used the same binding for Tx and Rx DPHY. With the separate
driver, I have added a separate binding. But I am still keeping the old
conversion patch in this series since I have already done the work in
converting the binding to yaml, might as well get it merged.
Tested on TI's J721E with OV5640 sensor.
[0] https://patchwork.linuxtv.org/project/linux-media/list/?series=5526&state=%2A&archive=both
Changes in v8:
- Move lanes check to start of configure sequence.
- Change MODULE_LICENSE() to "GPL".
Changes in v7:
- Add spaces after { and before } in the bands table.
- Drop the wrapping around the for loop on cdns_dphy_rx_get_band_ctrl().
- Make cdns_dphy_rx_wait_for_bit() inline.
- Print an error message if registering PHY provider fails.
Changes in v6:
- Add a new binding for DPHY Rx.
- Move the DPHY Rx part to a separate driver.
- Drop Rx specific changes from the cdns,dphy.yaml binding. Keep those
in cdns,dphy-rx.yaml
Changes in v5:
- Use the new cdns_dphy_info to specify PHY ops.
- Re-order include in alphabetical order.
- Make bands const.
- Drop num_bands.
- Make i, lanes unsigned.
- Drop the maximum check in cdns_dphy_rx_get_band_ctrl(). Let the loop
complete and return -EOPNOTSUPP when we reach the end.
- Drop the "rate < bands[i].min_rate" check since the bands are in
ascending order.
- Move data_lane_ctrl to start of function and make it static const.
Changes in v4:
- Drop the submode parts. Use a different compatible for the Rx ops.
- Make bands and num_bands static.
- Drop the submode patches. Use a different compatible for Rx mode DPHY
instead.
Changes in v3:
- Use a table to select the band.
- Use a table to poll the data lane ready bits.
- Multiply the DPHY HS clock rate by 2 to get the bit rate since the
clock is DDR.
- Add Rob's R-by.
Changes in v2:
- Drop reg description.
- Add a description for each DPHY clock.
- Rename dphy@... to phy@... in example.
- Add Laurent's R-by.
- Re-order subject prefixes.
- Add power-domain to the example.
- Add Laurent's R-by.
- Re-order subject prefixes.
Pratyush Yadav (4):
phy: cadence: Add Cadence D-PHY Rx driver
phy: dt-bindings: Convert Cadence DPHY binding to YAML
phy: dt-bindings: cdns,dphy: add power-domains property
phy: dt-bindings: Add Cadence D-PHY Rx bindings
.../devicetree/bindings/phy/cdns,dphy-rx.yaml | 42 +++
.../devicetree/bindings/phy/cdns,dphy.txt | 20 --
.../devicetree/bindings/phy/cdns,dphy.yaml | 56 ++++
drivers/phy/cadence/Kconfig | 8 +
drivers/phy/cadence/Makefile | 1 +
drivers/phy/cadence/cdns-dphy-rx.c | 255 ++++++++++++++++++
6 files changed, 362 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt
create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml
create mode 100644 drivers/phy/cadence/cdns-dphy-rx.c
--
2.25.1
^ permalink raw reply
* [PATCH v1 2/2] arm64: dts: imx8mq-librem5: fix mipi_csi1 port number to sensor
From: Martin Kepplinger @ 2022-01-21 9:33 UTC (permalink / raw)
To: robh, shawnguo
Cc: kernel, linux-imx, devicetree, linux-arm-kernel, phone-devel,
linux-kernel, Martin Kepplinger
In-Reply-To: <20220121093326.2388251-1-martin.kepplinger@puri.sm>
Since the previous commit fixed a hardware description bug for imx8mq,
we need to fix up all DT users like this. The mipi_csi port@0
is connected to the sensor, not port@1.
Fixes: fed7603597fa ("arm64: dts: imx8mq-librem5: describe the selfie cam")
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
---
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
index f3e3418f7edc..2d4a472af6a9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
@@ -1115,8 +1115,8 @@ &mipi_csi1 {
status = "okay";
ports {
- port@1 {
- reg = <1>;
+ port@0 {
+ reg = <0>;
mipi1_sensor_ep: endpoint {
remote-endpoint = <&camera1_ep>;
--
2.30.2
^ permalink raw reply related
* [PATCH v1 1/2] arm64: dts: imx8mq: fix mipi_csi bidirectional port numbers
From: Martin Kepplinger @ 2022-01-21 9:33 UTC (permalink / raw)
To: robh, shawnguo
Cc: kernel, linux-imx, devicetree, linux-arm-kernel, phone-devel,
linux-kernel, Martin Kepplinger
In-Reply-To: <20220121093326.2388251-1-martin.kepplinger@puri.sm>
The port numbers for the imx8mq mipi csi controller are wrong and
the mipi driver can't find any media devices as port@1 is connected
to the CSI bridge, not port@0. And port@0 is connected to the
source - the sensor. Fix this.
Fixes: bcadd5f66c2a ("arm64: dts: imx8mq: add mipi csi phy and csi bridge descriptions")
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 2df2510d0118..bb68c94c2fc9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1151,8 +1151,8 @@ ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
- reg = <0>;
+ port@1 {
+ reg = <1>;
csi1_mipi_ep: endpoint {
remote-endpoint = <&csi1_ep>;
@@ -1203,8 +1203,8 @@ ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
- reg = <0>;
+ port@1 {
+ reg = <1>;
csi2_mipi_ep: endpoint {
remote-endpoint = <&csi2_ep>;
--
2.30.2
^ permalink raw reply related
* [PATCH v1 0/2] arm64: dts: imx8mq: fix mipi_csi port numbering
From: Martin Kepplinger @ 2022-01-21 9:33 UTC (permalink / raw)
To: robh, shawnguo
Cc: kernel, linux-imx, devicetree, linux-arm-kernel, phone-devel,
linux-kernel, Martin Kepplinger
hi Shawn and all interested,
This is a fix for an embarrassing bug that slipped into commit
bcadd5f66c2a ("arm64: dts: imx8mq: add mipi csi phy and csi bridge descriptions")
and commit fed7603597fa ("arm64: dts: imx8mq-librem5: describe the selfie cam").
When preparing the imx8mq.dtsi description I only tested with port@1
being connected to the csi bridge, but what I sent said port@0.
I have this on my list for a while and want to sort this out now. I'm
sorry for the inconvenience. Until now imx8mq-librem5 is the only user
(maybe because of this :).
thank you,
martin
Martin Kepplinger (2):
arm64: dts: imx8mq: fix mipi_csi bidirectional port numbers
arm64: dts: imx8mq-librem5: fix mipi_csi1 port number to sensor
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 4 ++--
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
--
2.30.2
^ permalink raw reply
* Re: [RFC PATCH v2 1/4] media: dt-bindings: media: Document RZ/G2L CSI-2 block
From: Geert Uytterhoeven @ 2022-01-21 9:26 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Niklas Söderlund, Jacopo Mondi, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Laurent Pinchart,
Sakari Ailus, Hans Verkuil, Linux Media Mailing List,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
In-Reply-To: <20220121010543.31385-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Fri, Jan 21, 2022 at 2:06 AM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Document the CSI-2 block which is part of CRU found in Renesas
> RZ/G2L SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> ---
> Hi Geert/All,
>
> vclk and pclk clocks are shared with CRU both CSI and CRU driver are using
> pm_runtime. pclk clock is necessary for register access where as vclk clock
> is only used for calculations. So would you suggest passing vclk as part of
What do you mean by "calculations"?
The bindings say this is the main clock?
> clocks (as currently implemented) or pass the vclk clock rate as a dt property.
Please do not specify clock rates in DT, but always pass clock
specifiers instead.
The clock subsystem handles sharing of clocks just fine.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 6/9] soc: imx: add i.MX8MP HSIO blk-ctrl
From: Lucas Stach @ 2022-01-21 9:19 UTC (permalink / raw)
To: Abel Vesa
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Fabio Estevam, devicetree, linux-arm-kernel, patchwork-lst
In-Reply-To: <Yep3EF6VPc5LhMAE@abelvesa>
Hi Abel,
Am Freitag, dem 21.01.2022 um 11:04 +0200 schrieb Abel Vesa:
> On 22-01-19 14:40:24, Lucas Stach wrote:
> > The i.MX8MP added some blk-ctrl peripherals that don't follow the regular
> > structure of the blk-ctrls in the previous SoCs. Add a new file for those
> > with currently only the HSIO blk-ctrl being supported. Others will be added
> > later on.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> > drivers/soc/imx/Makefile | 1 +
> > drivers/soc/imx/imx8mp-blk-ctrl.c | 444 ++++++++++++++++++++++++++++++
> > 2 files changed, 445 insertions(+)
> > create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
> >
> > diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
> > index 8a707077914c..63cd29f6d4d2 100644
> > --- a/drivers/soc/imx/Makefile
> > +++ b/drivers/soc/imx/Makefile
> > @@ -6,3 +6,4 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
> > obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
> > obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
> > obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
> > +obj-$(CONFIG_SOC_IMX8M) += imx8mp-blk-ctrl.o
> > diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
>
> So far the imx8m-blk-ctrl is used only by i.MX8MM, while this new one is
> used by i.MX8MP. Do you think we can have the generic stuff we should
> probably put the generic stuff in something new called imx-blk-ctrl
> (which could be used for future non-i.MX8) ? Then maybe we can have one
> file per SoC that only adds the SoC specific stuff. For example, you
> define those structs that look quite the same in each file. Same goes
> for the probe function.
>
The i.MX8MP VPU and MEDIA blk-ctrls also match the structure laid out
in imx8m-blk-ctrl and should use this driver. HSIO, AUDIO and HDMI
however don't have that regular clk/reset register structure and need
special handling, that's why I added the new file for those.
> I can prepare a patch and send it, if you want.
For now I didn't consider the overlap big enough to warrant that. While
many things look similar they are different in little details, so I
didn't want to start with adding abstractions there. Usually it's
easier to first (mostly) duplicate some code and then refactor to
abstract some things and move them into common code when you have the
full picture where the real overlap is. Trying to move too much stuff
into common code before having the full picture is usually a recipe for
unreadable code.
However, I won't stop you from giving it a shot. I just think it would
be better to first get all the blk-ctrls on the 8MP working, even with
some duplication, and then clean things up when we have a more complete
picture.
Regards,
Lucas
>
> > new file mode 100644
> > index 000000000000..7f4e1a151d2b
> > --- /dev/null
> > +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
> > @@ -0,0 +1,444 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +
> > +/*
> > + * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
> > + */
> > +
> > +#include <linux/device.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_domain.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/regmap.h>
> > +#include <linux/clk.h>
> > +
> > +#include <dt-bindings/power/imx8mp-power.h>
> > +
> > +#define GPR_REG0 0x0
> > +#define PCIE_CLOCK_MODULE_EN BIT(0)
> > +#define USB_CLOCK_MODULE_EN BIT(1)
> > +
> > +struct imx8mp_hsio_blk_ctrl_domain;
> > +
> > +struct imx8mp_hsio_blk_ctrl {
> > + struct device *dev;
> > + struct notifier_block power_nb;
> > + struct device *bus_power_dev;
> > + struct regmap *regmap;
> > + struct imx8mp_hsio_blk_ctrl_domain *domains;
> > + struct genpd_onecell_data onecell_data;
> > +};
> > +
> > +struct imx8mp_hsio_blk_ctrl_domain_data {
> > + const char *name;
> > + const char *clk_name;
> > + const char *gpc_name;
> > +};
> > +
> > +struct imx8mp_hsio_blk_ctrl_domain {
> > + struct generic_pm_domain genpd;
> > + struct clk *clk;
> > + struct device *power_dev;
> > + struct imx8mp_hsio_blk_ctrl *bc;
> > + int id;
> > +};
> > +
> > +static inline struct imx8mp_hsio_blk_ctrl_domain *
> > +to_imx8mp_hsio_blk_ctrl_domain(struct generic_pm_domain *genpd)
> > +{
> > + return container_of(genpd, struct imx8mp_hsio_blk_ctrl_domain, genpd);
> > +}
> > +
> > +static int imx8mp_hsio_blk_ctrl_power_on(struct generic_pm_domain *genpd)
> > +{
> > + struct imx8mp_hsio_blk_ctrl_domain *domain =
> > + to_imx8mp_hsio_blk_ctrl_domain(genpd);
> > + struct imx8mp_hsio_blk_ctrl *bc = domain->bc;
> > + int ret;
> > +
> > + /* make sure bus domain is awake */
> > + ret = pm_runtime_get_sync(bc->bus_power_dev);
> > + if (ret < 0) {
> > + pm_runtime_put_noidle(bc->bus_power_dev);
> > + dev_err(bc->dev, "failed to power up bus domain\n");
> > + return ret;
> > + }
> > +
> > + /* enable upstream and blk-ctrl clocks */
> > + ret = clk_prepare_enable(domain->clk);
> > + if (ret) {
> > + dev_err(bc->dev, "failed to enable clocks\n");
> > + goto bus_put;
> > + }
> > +
> > + switch (domain->id) {
> > + case IMX8MP_HSIOBLK_PD_USB:
> > + regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
> > + break;
> > + case IMX8MP_HSIOBLK_PD_PCIE:
> > + regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + /* power up upstream GPC domain */
> > + ret = pm_runtime_get_sync(domain->power_dev);
> > + if (ret < 0) {
> > + dev_err(bc->dev, "failed to power up peripheral domain\n");
> > + goto clk_disable;
> > + }
> > +
> > + return 0;
> > +
> > +clk_disable:
> > + clk_disable_unprepare(domain->clk);
> > +bus_put:
> > + pm_runtime_put(bc->bus_power_dev);
> > +
> > + return ret;
> > +}
> > +
> > +static int imx8mp_hsio_blk_ctrl_power_off(struct generic_pm_domain *genpd)
> > +{
> > + struct imx8mp_hsio_blk_ctrl_domain *domain =
> > + to_imx8mp_hsio_blk_ctrl_domain(genpd);
> > + struct imx8mp_hsio_blk_ctrl *bc = domain->bc;
> > +
> > + /* disable clocks */
> > + switch (domain->id) {
> > + case IMX8MP_HSIOBLK_PD_USB:
> > + regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
> > + break;
> > + case IMX8MP_HSIOBLK_PD_PCIE:
> > + regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + clk_disable_unprepare(domain->clk);
> > +
> > + /* power down upstream GPC domain */
> > + pm_runtime_put(domain->power_dev);
> > +
> > + /* allow bus domain to suspend */
> > + pm_runtime_put(bc->bus_power_dev);
> > +
> > + return 0;
> > +}
> > +
> > +static struct generic_pm_domain *
> > +imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data)
> > +{
> > + struct genpd_onecell_data *onecell_data = data;
> > + unsigned int index = args->args[0];
> > +
> > + if (args->args_count != 1 ||
> > + index >= onecell_data->num_domains)
> > + return ERR_PTR(-EINVAL);
> > +
> > + return onecell_data->domains[index];
> > +}
> > +
> > +static struct lock_class_key blk_ctrl_genpd_lock_class;
> > +
> > +static const struct imx8mp_hsio_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = {
> > + [IMX8MP_HSIOBLK_PD_USB] = {
> > + .name = "hsioblk-usb",
> > + .clk_name = "usb",
> > + .gpc_name = "usb",
> > + },
> > + [IMX8MP_HSIOBLK_PD_USB_PHY1] = {
> > + .name = "hsioblk-ubs-phy1",
> > + .gpc_name = "usb-phy1",
> > + },
> > + [IMX8MP_HSIOBLK_PD_USB_PHY2] = {
> > + .name = "hsioblk-ubs-phy2",
> > + .gpc_name = "usb-phy2",
> > + },
> > + [IMX8MP_HSIOBLK_PD_PCIE] = {
> > + .name = "hsioblk-pcie",
> > + .clk_name = "pcie",
> > + .gpc_name = "pcie",
> > + },
> > + [IMX8MP_HSIOBLK_PD_PCIE_PHY] = {
> > + .name = "hsioblk-pcie-phy",
> > + .gpc_name = "pcie-phy",
> > + },
> > +};
> > +
> > +static int imx8mp_hsio_power_notifier(struct notifier_block *nb,
> > + unsigned long action, void *data)
> > +{
> > + struct imx8mp_hsio_blk_ctrl *bc = container_of(nb, struct imx8mp_hsio_blk_ctrl,
> > + power_nb);
> > + struct clk *usb_clk = bc->domains[IMX8MP_HSIOBLK_PD_USB].clk;
> > + int ret;
> > +
> > + switch (action) {
> > + case GENPD_NOTIFY_ON:
> > + /*
> > + * enable USB clock for a moment for the power-on ADB handshake
> > + * to proceed
> > + */
> > + ret = clk_prepare_enable(usb_clk);
> > + if (ret)
> > + return NOTIFY_BAD;
> > + regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
> > +
> > + udelay(5);
> > +
> > + regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
> > + clk_disable_unprepare(usb_clk);
> > + break;
> > + case GENPD_NOTIFY_PRE_OFF:
> > + /* enable USB clock for the power-down ADB handshake to work */
> > + ret = clk_prepare_enable(usb_clk);
> > + if (ret)
> > + return NOTIFY_BAD;
> > +
> > + regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
> > + break;
> > + case GENPD_NOTIFY_OFF:
> > + clk_disable_unprepare(usb_clk);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + return NOTIFY_OK;
> > +}
> > +
> > +static int imx8mp_hsio_blk_ctrl_probe(struct platform_device *pdev)
> > +{
> > + int num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data);
> > + struct device *dev = &pdev->dev;
> > + struct imx8mp_hsio_blk_ctrl *bc;
> > + void __iomem *base;
> > + int i, ret;
> > +
> > + struct regmap_config regmap_config = {
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
> > + .max_register = 0x24,
> > + };
> > +
> > + bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
> > + if (!bc)
> > + return -ENOMEM;
> > +
> > + bc->dev = dev;
> > +
> > + base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(base))
> > + return PTR_ERR(base);
> > +
> > + bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
> > + if (IS_ERR(bc->regmap))
> > + return dev_err_probe(dev, PTR_ERR(bc->regmap),
> > + "failed to init regmap\n");
> > +
> > + bc->domains = devm_kcalloc(dev, num_domains,
> > + sizeof(struct imx8mp_hsio_blk_ctrl_domain),
> > + GFP_KERNEL);
> > + if (!bc->domains)
> > + return -ENOMEM;
> > +
> > + bc->onecell_data.num_domains = num_domains;
> > + bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
> > + bc->onecell_data.domains =
> > + devm_kcalloc(dev, num_domains,
> > + sizeof(struct generic_pm_domain *), GFP_KERNEL);
> > + if (!bc->onecell_data.domains)
> > + return -ENOMEM;
> > +
> > + bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
> > + if (IS_ERR(bc->bus_power_dev))
> > + return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
> > + "failed to attach power domain\n");
> > +
> > + for (i = 0; i < num_domains; i++) {
> > + const struct imx8mp_hsio_blk_ctrl_domain_data *data =
> > + &imx8mp_hsio_domain_data[i];
> > + struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
> > +
> > + if (data->clk_name) {
> > + domain->clk = devm_clk_get(dev, data->clk_name);
> > + if (IS_ERR(domain->clk)) {
> > + ret = PTR_ERR(domain->clk);
> > + dev_err_probe(dev, ret, "failed to get clock\n");
> > + goto cleanup_pds;
> > + }
> > + }
> > +
> > + domain->power_dev =
> > + dev_pm_domain_attach_by_name(dev, data->gpc_name);
> > + if (IS_ERR(domain->power_dev)) {
> > + dev_err_probe(dev, PTR_ERR(domain->power_dev),
> > + "failed to attach power domain\n");
> > + ret = PTR_ERR(domain->power_dev);
> > + goto cleanup_pds;
> > + }
> > +
> > + domain->genpd.name = data->name;
> > + domain->genpd.power_on = imx8mp_hsio_blk_ctrl_power_on;
> > + domain->genpd.power_off = imx8mp_hsio_blk_ctrl_power_off;
> > + domain->bc = bc;
> > + domain->id = i;
> > +
> > + ret = pm_genpd_init(&domain->genpd, NULL, true);
> > + if (ret) {
> > + dev_err_probe(dev, ret, "failed to init power domain\n");
> > + dev_pm_domain_detach(domain->power_dev, true);
> > + goto cleanup_pds;
> > + }
> > +
> > + /*
> > + * We use runtime PM to trigger power on/off of the upstream GPC
> > + * domain, as a strict hierarchical parent/child power domain
> > + * setup doesn't allow us to meet the sequencing requirements.
> > + * This means we have nested locking of genpd locks, without the
> > + * nesting being visible at the genpd level, so we need a
> > + * separate lock class to make lockdep aware of the fact that
> > + * this are separate domain locks that can be nested without a
> > + * self-deadlock.
> > + */
> > + lockdep_set_class(&domain->genpd.mlock,
> > + &blk_ctrl_genpd_lock_class);
> > +
> > + bc->onecell_data.domains[i] = &domain->genpd;
> > + }
> > +
> > + ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
> > + if (ret) {
> > + dev_err_probe(dev, ret, "failed to add power domain provider\n");
> > + goto cleanup_pds;
> > + }
> > +
> > + bc->power_nb.notifier_call = imx8mp_hsio_power_notifier;
> > + ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
> > + if (ret) {
> > + dev_err_probe(dev, ret, "failed to add power notifier\n");
> > + goto cleanup_provider;
> > + }
> > +
> > + dev_set_drvdata(dev, bc);
> > +
> > + return 0;
> > +
> > +cleanup_provider:
> > + of_genpd_del_provider(dev->of_node);
> > +cleanup_pds:
> > + for (i--; i >= 0; i--) {
> > + pm_genpd_remove(&bc->domains[i].genpd);
> > + dev_pm_domain_detach(bc->domains[i].power_dev, true);
> > + }
> > +
> > + dev_pm_domain_detach(bc->bus_power_dev, true);
> > +
> > + return ret;
> > +}
> > +
> > +static int imx8mp_hsio_blk_ctrl_remove(struct platform_device *pdev)
> > +{
> > + struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
> > + int i;
> > +
> > + of_genpd_del_provider(pdev->dev.of_node);
> > +
> > + for (i = 0; bc->onecell_data.num_domains; i++) {
> > + struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
> > +
> > + pm_genpd_remove(&domain->genpd);
> > + dev_pm_domain_detach(domain->power_dev, true);
> > + }
> > +
> > + dev_pm_genpd_remove_notifier(bc->bus_power_dev);
> > +
> > + dev_pm_domain_detach(bc->bus_power_dev, true);
> > +
> > + return 0;
> > +}
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int imx8mp_hsio_blk_ctrl_suspend(struct device *dev)
> > +{
> > + struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(dev);
> > + int ret, i;
> > +
> > + /*
> > + * This may look strange, but is done so the generic PM_SLEEP code
> > + * can power down our domains and more importantly power them up again
> > + * after resume, without tripping over our usage of runtime PM to
> > + * control the upstream GPC domains. Things happen in the right order
> > + * in the system suspend/resume paths due to the device parent/child
> > + * hierarchy.
> > + */
> > + ret = pm_runtime_get_sync(bc->bus_power_dev);
> > + if (ret < 0) {
> > + pm_runtime_put_noidle(bc->bus_power_dev);
> > + return ret;
> > + }
> > +
> > + for (i = 0; i < bc->onecell_data.num_domains; i++) {
> > + struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
> > +
> > + ret = pm_runtime_get_sync(domain->power_dev);
> > + if (ret < 0) {
> > + pm_runtime_put_noidle(domain->power_dev);
> > + goto out_fail;
> > + }
> > + }
> > +
> > + return 0;
> > +
> > +out_fail:
> > + for (i--; i >= 0; i--)
> > + pm_runtime_put(bc->domains[i].power_dev);
> > +
> > + pm_runtime_put(bc->bus_power_dev);
> > +
> > + return ret;
> > +}
> > +
> > +static int imx8mp_hsio_blk_ctrl_resume(struct device *dev)
> > +{
> > + struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(dev);
> > + int i;
> > +
> > + for (i = 0; i < bc->onecell_data.num_domains; i++)
> > + pm_runtime_put(bc->domains[i].power_dev);
> > +
> > + pm_runtime_put(bc->bus_power_dev);
> > +
> > + return 0;
> > +}
> > +#endif
> > +
> > +static const struct dev_pm_ops imx8mp_hsio_blk_ctrl_pm_ops = {
> > + SET_SYSTEM_SLEEP_PM_OPS(imx8mp_hsio_blk_ctrl_suspend,
> > + imx8mp_hsio_blk_ctrl_resume)
> > +};
> > +
> > +static const struct of_device_id imx8mp_hsio_blk_ctrl_of_match[] = {
> > + {
> > + .compatible = "fsl,imx8mp-hsio-blk-ctrl",
> > + }, {
> > + /* Sentinel */
> > + }
> > +};
> > +MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
> > +
> > +static struct platform_driver imx8mp_hsio_blk_ctrl_driver = {
> > + .probe = imx8mp_hsio_blk_ctrl_probe,
> > + .remove = imx8mp_hsio_blk_ctrl_remove,
> > + .driver = {
> > + .name = "imx8mp-hsio-blk-ctrl",
> > + .pm = &imx8mp_hsio_blk_ctrl_pm_ops,
> > + .of_match_table = imx8mp_hsio_blk_ctrl_of_match,
> > + },
> > +};
> > +module_platform_driver(imx8mp_hsio_blk_ctrl_driver);
> > --
> > 2.30.2
> >
^ permalink raw reply
* [PATCH v3] powerpc: dts: t1040rdb: fix ports names for Seville Ethernet switch
From: Maxim Kiselev @ 2022-01-21 9:14 UTC (permalink / raw)
To: mpe
Cc: andrew, benh, bigunclemax, davem, devicetree, fido_max,
linux-kernel, linuxppc-dev, paulus, robh+dt, vladimir.oltean
In-Reply-To: <87czkmudh0.fsf@mpe.ellerman.id.au>
On board rev A, the network interface labels for the switch ports
written on the front panel are different than on rev B and later.
This patch fixes network interface names for the switch ports according
to labels that are written on the front panel of the board rev B.
They start from ETH3 and end at ETH10.
This patch also introduces a separate device tree for rev A.
The main device tree is supposed to cover rev B and later.
Fixes: e69eb0824d8c ("powerpc: dts: t1040rdb: add ports for Seville Ethernet switch")
Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
Reviewed-by: Maxim Kochetkov <fido_max@inbox.ru>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Here is the fix for the error in t1040rdb-rev-a.dts caused by containing '#include' directive inside '/include/'
---
arch/powerpc/boot/dts/fsl/t1040rdb-rev-a.dts | 30 ++++++++++++++++++++
arch/powerpc/boot/dts/fsl/t1040rdb.dts | 8 +++---
2 files changed, 34 insertions(+), 4 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/t1040rdb-rev-a.dts
diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb-rev-a.dts b/arch/powerpc/boot/dts/fsl/t1040rdb-rev-a.dts
new file mode 100644
index 0000000000000..73f8c998c64df
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040rdb-rev-a.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * T1040RDB-REV-A Device Tree Source
+ *
+ * Copyright 2014 - 2015 Freescale Semiconductor Inc.
+ *
+ */
+
+#include "t1040rdb.dts"
+
+/ {
+ model = "fsl,T1040RDB-REV-A";
+ compatible = "fsl,T1040RDB-REV-A";
+};
+
+&seville_port0 {
+ label = "ETH5";
+};
+
+&seville_port2 {
+ label = "ETH7";
+};
+
+&seville_port4 {
+ label = "ETH9";
+};
+
+&seville_port6 {
+ label = "ETH11";
+};
diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
index af0c8a6f56138..b6733e7e65805 100644
--- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
@@ -119,7 +119,7 @@ &seville_port0 {
managed = "in-band-status";
phy-handle = <&phy_qsgmii_0>;
phy-mode = "qsgmii";
- label = "ETH5";
+ label = "ETH3";
status = "okay";
};
@@ -135,7 +135,7 @@ &seville_port2 {
managed = "in-band-status";
phy-handle = <&phy_qsgmii_2>;
phy-mode = "qsgmii";
- label = "ETH7";
+ label = "ETH5";
status = "okay";
};
@@ -151,7 +151,7 @@ &seville_port4 {
managed = "in-band-status";
phy-handle = <&phy_qsgmii_4>;
phy-mode = "qsgmii";
- label = "ETH9";
+ label = "ETH7";
status = "okay";
};
@@ -167,7 +167,7 @@ &seville_port6 {
managed = "in-band-status";
phy-handle = <&phy_qsgmii_6>;
phy-mode = "qsgmii";
- label = "ETH11";
+ label = "ETH9";
status = "okay";
};
--
2.32.0
^ permalink raw reply related
* Re: [PATCH v3 2/6] ASoC: xilinx: xlnx_i2s: create drvdata structure
From: Amadeusz Sławiński @ 2022-01-21 9:06 UTC (permalink / raw)
To: Robert Hancock, alsa-devel
Cc: devicetree, kuninori.morimoto.gx, lgirdwood, tiwai, robh+dt,
michal.simek, broonie, maruthi.srinivas.bayyavarapu
In-Reply-To: <20220120195832.1742271-3-robert.hancock@calian.com>
On 1/20/2022 8:58 PM, Robert Hancock wrote:
> An upcoming change will require storing additional driver data other
> than the memory base address. Create a drvdata structure and use that
> rather than storing the raw base address pointer.
>
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> ---
> sound/soc/xilinx/xlnx_i2s.c | 66 ++++++++++++++++++++-----------------
> 1 file changed, 35 insertions(+), 31 deletions(-)
>
> diff --git a/sound/soc/xilinx/xlnx_i2s.c b/sound/soc/xilinx/xlnx_i2s.c
> index cc641e582c82..3bafa34b789a 100644
> --- a/sound/soc/xilinx/xlnx_i2s.c
> +++ b/sound/soc/xilinx/xlnx_i2s.c
> @@ -22,15 +22,20 @@
> #define I2S_CH0_OFFSET 0x30
> #define I2S_I2STIM_VALID_MASK GENMASK(7, 0)
>
> +struct xlnx_i2s_drv_data {
> + struct snd_soc_dai_driver dai_drv;
> + void __iomem *base;
> +};
> +
> static int xlnx_i2s_set_sclkout_div(struct snd_soc_dai *cpu_dai,
> int div_id, int div)
> {
> - void __iomem *base = snd_soc_dai_get_drvdata(cpu_dai);
> + struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(cpu_dai);
>
> if (!div || (div & ~I2S_I2STIM_VALID_MASK))
> return -EINVAL;
>
> - writel(div, base + I2S_I2STIM_OFFSET);
> + writel(div, drv_data->base + I2S_I2STIM_OFFSET);
>
> return 0;
> }
> @@ -40,13 +45,13 @@ static int xlnx_i2s_hw_params(struct snd_pcm_substream *substream,
> struct snd_soc_dai *i2s_dai)
> {
> u32 reg_off, chan_id;
> - void __iomem *base = snd_soc_dai_get_drvdata(i2s_dai);
> + struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(i2s_dai);
>
> chan_id = params_channels(params) / 2;
>
> while (chan_id > 0) {
> reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4);
> - writel(chan_id, base + reg_off);
> + writel(chan_id, drv_data->base + reg_off);
> chan_id--;
> }
>
> @@ -56,18 +61,18 @@ static int xlnx_i2s_hw_params(struct snd_pcm_substream *substream,
> static int xlnx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
> struct snd_soc_dai *i2s_dai)
> {
> - void __iomem *base = snd_soc_dai_get_drvdata(i2s_dai);
> + struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(i2s_dai);
>
> switch (cmd) {
> case SNDRV_PCM_TRIGGER_START:
> case SNDRV_PCM_TRIGGER_RESUME:
> case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
> - writel(1, base + I2S_CORE_CTRL_OFFSET);
> + writel(1, drv_data->base + I2S_CORE_CTRL_OFFSET);
> break;
> case SNDRV_PCM_TRIGGER_STOP:
> case SNDRV_PCM_TRIGGER_SUSPEND:
> case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
> - writel(0, base + I2S_CORE_CTRL_OFFSET);
> + writel(0, drv_data->base + I2S_CORE_CTRL_OFFSET);
> break;
> default:
> return -EINVAL;
> @@ -95,20 +100,19 @@ MODULE_DEVICE_TABLE(of, xlnx_i2s_of_match);
>
> static int xlnx_i2s_probe(struct platform_device *pdev)
> {
> - void __iomem *base;
> - struct snd_soc_dai_driver *dai_drv;
> + struct xlnx_i2s_drv_data *drv_data;
> int ret;
> u32 ch, format, data_width;
> struct device *dev = &pdev->dev;
> struct device_node *node = dev->of_node;
>
> - dai_drv = devm_kzalloc(&pdev->dev, sizeof(*dai_drv), GFP_KERNEL);
> - if (!dai_drv)
> + drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
> + if (!drv_data)
> return -ENOMEM;
>
> - base = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(base))
> - return PTR_ERR(base);
> + drv_data->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(drv_data->base))
> + return PTR_ERR(drv_data->base);
>
> ret = of_property_read_u32(node, "xlnx,num-channels", &ch);
> if (ret < 0) {
> @@ -134,35 +138,35 @@ static int xlnx_i2s_probe(struct platform_device *pdev)
> }
>
> if (of_device_is_compatible(node, "xlnx,i2s-transmitter-1.0")) {
> - dai_drv->name = "xlnx_i2s_playback";
> - dai_drv->playback.stream_name = "Playback";
> - dai_drv->playback.formats = format;
> - dai_drv->playback.channels_min = ch;
> - dai_drv->playback.channels_max = ch;
> - dai_drv->playback.rates = SNDRV_PCM_RATE_8000_192000;
> - dai_drv->ops = &xlnx_i2s_dai_ops;
> + drv_data->dai_drv.name = "xlnx_i2s_playback";
> + drv_data->dai_drv.playback.stream_name = "Playback";
> + drv_data->dai_drv.playback.formats = format;
> + drv_data->dai_drv.playback.channels_min = ch;
> + drv_data->dai_drv.playback.channels_max = ch;
> + drv_data->dai_drv.playback.rates = SNDRV_PCM_RATE_8000_192000;
> + drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
> } else if (of_device_is_compatible(node, "xlnx,i2s-receiver-1.0")) {
> - dai_drv->name = "xlnx_i2s_capture";
> - dai_drv->capture.stream_name = "Capture";
> - dai_drv->capture.formats = format;
> - dai_drv->capture.channels_min = ch;
> - dai_drv->capture.channels_max = ch;
> - dai_drv->capture.rates = SNDRV_PCM_RATE_8000_192000;
> - dai_drv->ops = &xlnx_i2s_dai_ops;
> + drv_data->dai_drv.name = "xlnx_i2s_capture";
> + drv_data->dai_drv.capture.stream_name = "Capture";
> + drv_data->dai_drv.capture.formats = format;
> + drv_data->dai_drv.capture.channels_min = ch;
> + drv_data->dai_drv.capture.channels_max = ch;
> + drv_data->dai_drv.capture.rates = SNDRV_PCM_RATE_8000_192000;
> + drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
> } else {
> return -ENODEV;
> }
>
> - dev_set_drvdata(&pdev->dev, base);
> + dev_set_drvdata(&pdev->dev, drv_data);
>
> ret = devm_snd_soc_register_component(&pdev->dev, &xlnx_i2s_component,
> - dai_drv, 1);
> + &drv_data->dai_drv, 1);
> if (ret) {
> dev_err(&pdev->dev, "i2s component registration failed\n");
> return ret;
> }
>
> - dev_info(&pdev->dev, "%s DAI registered\n", dai_drv->name);
> + dev_info(&pdev->dev, "%s DAI registered\n", drv_data->dai_drv.name);
>
> return ret;
> }
I don't think this patch is needed, snd_soc_dai, already has pointer to
its snd_soc_dai_driver, so there is no need to keep it additionally in
drvdata?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/sound/soc-dai.h?h=v5.16#n431
^ permalink raw reply
* Re: [PATCH 6/9] soc: imx: add i.MX8MP HSIO blk-ctrl
From: Abel Vesa @ 2022-01-21 9:04 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Fabio Estevam, devicetree, linux-arm-kernel, patchwork-lst
In-Reply-To: <20220119134027.2931945-7-l.stach@pengutronix.de>
On 22-01-19 14:40:24, Lucas Stach wrote:
> The i.MX8MP added some blk-ctrl peripherals that don't follow the regular
> structure of the blk-ctrls in the previous SoCs. Add a new file for those
> with currently only the HSIO blk-ctrl being supported. Others will be added
> later on.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> drivers/soc/imx/Makefile | 1 +
> drivers/soc/imx/imx8mp-blk-ctrl.c | 444 ++++++++++++++++++++++++++++++
> 2 files changed, 445 insertions(+)
> create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
>
> diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
> index 8a707077914c..63cd29f6d4d2 100644
> --- a/drivers/soc/imx/Makefile
> +++ b/drivers/soc/imx/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
> obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
> obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
> obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
> +obj-$(CONFIG_SOC_IMX8M) += imx8mp-blk-ctrl.o
> diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
So far the imx8m-blk-ctrl is used only by i.MX8MM, while this new one is
used by i.MX8MP. Do you think we can have the generic stuff we should
probably put the generic stuff in something new called imx-blk-ctrl
(which could be used for future non-i.MX8) ? Then maybe we can have one
file per SoC that only adds the SoC specific stuff. For example, you
define those structs that look quite the same in each file. Same goes
for the probe function.
I can prepare a patch and send it, if you want.
> new file mode 100644
> index 000000000000..7f4e1a151d2b
> --- /dev/null
> +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
> @@ -0,0 +1,444 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/*
> + * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
> + */
> +
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/clk.h>
> +
> +#include <dt-bindings/power/imx8mp-power.h>
> +
> +#define GPR_REG0 0x0
> +#define PCIE_CLOCK_MODULE_EN BIT(0)
> +#define USB_CLOCK_MODULE_EN BIT(1)
> +
> +struct imx8mp_hsio_blk_ctrl_domain;
> +
> +struct imx8mp_hsio_blk_ctrl {
> + struct device *dev;
> + struct notifier_block power_nb;
> + struct device *bus_power_dev;
> + struct regmap *regmap;
> + struct imx8mp_hsio_blk_ctrl_domain *domains;
> + struct genpd_onecell_data onecell_data;
> +};
> +
> +struct imx8mp_hsio_blk_ctrl_domain_data {
> + const char *name;
> + const char *clk_name;
> + const char *gpc_name;
> +};
> +
> +struct imx8mp_hsio_blk_ctrl_domain {
> + struct generic_pm_domain genpd;
> + struct clk *clk;
> + struct device *power_dev;
> + struct imx8mp_hsio_blk_ctrl *bc;
> + int id;
> +};
> +
> +static inline struct imx8mp_hsio_blk_ctrl_domain *
> +to_imx8mp_hsio_blk_ctrl_domain(struct generic_pm_domain *genpd)
> +{
> + return container_of(genpd, struct imx8mp_hsio_blk_ctrl_domain, genpd);
> +}
> +
> +static int imx8mp_hsio_blk_ctrl_power_on(struct generic_pm_domain *genpd)
> +{
> + struct imx8mp_hsio_blk_ctrl_domain *domain =
> + to_imx8mp_hsio_blk_ctrl_domain(genpd);
> + struct imx8mp_hsio_blk_ctrl *bc = domain->bc;
> + int ret;
> +
> + /* make sure bus domain is awake */
> + ret = pm_runtime_get_sync(bc->bus_power_dev);
> + if (ret < 0) {
> + pm_runtime_put_noidle(bc->bus_power_dev);
> + dev_err(bc->dev, "failed to power up bus domain\n");
> + return ret;
> + }
> +
> + /* enable upstream and blk-ctrl clocks */
> + ret = clk_prepare_enable(domain->clk);
> + if (ret) {
> + dev_err(bc->dev, "failed to enable clocks\n");
> + goto bus_put;
> + }
> +
> + switch (domain->id) {
> + case IMX8MP_HSIOBLK_PD_USB:
> + regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
> + break;
> + case IMX8MP_HSIOBLK_PD_PCIE:
> + regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
> + break;
> + default:
> + break;
> + }
> +
> + /* power up upstream GPC domain */
> + ret = pm_runtime_get_sync(domain->power_dev);
> + if (ret < 0) {
> + dev_err(bc->dev, "failed to power up peripheral domain\n");
> + goto clk_disable;
> + }
> +
> + return 0;
> +
> +clk_disable:
> + clk_disable_unprepare(domain->clk);
> +bus_put:
> + pm_runtime_put(bc->bus_power_dev);
> +
> + return ret;
> +}
> +
> +static int imx8mp_hsio_blk_ctrl_power_off(struct generic_pm_domain *genpd)
> +{
> + struct imx8mp_hsio_blk_ctrl_domain *domain =
> + to_imx8mp_hsio_blk_ctrl_domain(genpd);
> + struct imx8mp_hsio_blk_ctrl *bc = domain->bc;
> +
> + /* disable clocks */
> + switch (domain->id) {
> + case IMX8MP_HSIOBLK_PD_USB:
> + regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
> + break;
> + case IMX8MP_HSIOBLK_PD_PCIE:
> + regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
> + break;
> + default:
> + break;
> + }
> +
> + clk_disable_unprepare(domain->clk);
> +
> + /* power down upstream GPC domain */
> + pm_runtime_put(domain->power_dev);
> +
> + /* allow bus domain to suspend */
> + pm_runtime_put(bc->bus_power_dev);
> +
> + return 0;
> +}
> +
> +static struct generic_pm_domain *
> +imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data)
> +{
> + struct genpd_onecell_data *onecell_data = data;
> + unsigned int index = args->args[0];
> +
> + if (args->args_count != 1 ||
> + index >= onecell_data->num_domains)
> + return ERR_PTR(-EINVAL);
> +
> + return onecell_data->domains[index];
> +}
> +
> +static struct lock_class_key blk_ctrl_genpd_lock_class;
> +
> +static const struct imx8mp_hsio_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = {
> + [IMX8MP_HSIOBLK_PD_USB] = {
> + .name = "hsioblk-usb",
> + .clk_name = "usb",
> + .gpc_name = "usb",
> + },
> + [IMX8MP_HSIOBLK_PD_USB_PHY1] = {
> + .name = "hsioblk-ubs-phy1",
> + .gpc_name = "usb-phy1",
> + },
> + [IMX8MP_HSIOBLK_PD_USB_PHY2] = {
> + .name = "hsioblk-ubs-phy2",
> + .gpc_name = "usb-phy2",
> + },
> + [IMX8MP_HSIOBLK_PD_PCIE] = {
> + .name = "hsioblk-pcie",
> + .clk_name = "pcie",
> + .gpc_name = "pcie",
> + },
> + [IMX8MP_HSIOBLK_PD_PCIE_PHY] = {
> + .name = "hsioblk-pcie-phy",
> + .gpc_name = "pcie-phy",
> + },
> +};
> +
> +static int imx8mp_hsio_power_notifier(struct notifier_block *nb,
> + unsigned long action, void *data)
> +{
> + struct imx8mp_hsio_blk_ctrl *bc = container_of(nb, struct imx8mp_hsio_blk_ctrl,
> + power_nb);
> + struct clk *usb_clk = bc->domains[IMX8MP_HSIOBLK_PD_USB].clk;
> + int ret;
> +
> + switch (action) {
> + case GENPD_NOTIFY_ON:
> + /*
> + * enable USB clock for a moment for the power-on ADB handshake
> + * to proceed
> + */
> + ret = clk_prepare_enable(usb_clk);
> + if (ret)
> + return NOTIFY_BAD;
> + regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
> +
> + udelay(5);
> +
> + regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
> + clk_disable_unprepare(usb_clk);
> + break;
> + case GENPD_NOTIFY_PRE_OFF:
> + /* enable USB clock for the power-down ADB handshake to work */
> + ret = clk_prepare_enable(usb_clk);
> + if (ret)
> + return NOTIFY_BAD;
> +
> + regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
> + break;
> + case GENPD_NOTIFY_OFF:
> + clk_disable_unprepare(usb_clk);
> + break;
> + default:
> + break;
> + }
> +
> + return NOTIFY_OK;
> +}
> +
> +static int imx8mp_hsio_blk_ctrl_probe(struct platform_device *pdev)
> +{
> + int num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data);
> + struct device *dev = &pdev->dev;
> + struct imx8mp_hsio_blk_ctrl *bc;
> + void __iomem *base;
> + int i, ret;
> +
> + struct regmap_config regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = 0x24,
> + };
> +
> + bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
> + if (!bc)
> + return -ENOMEM;
> +
> + bc->dev = dev;
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
> + if (IS_ERR(bc->regmap))
> + return dev_err_probe(dev, PTR_ERR(bc->regmap),
> + "failed to init regmap\n");
> +
> + bc->domains = devm_kcalloc(dev, num_domains,
> + sizeof(struct imx8mp_hsio_blk_ctrl_domain),
> + GFP_KERNEL);
> + if (!bc->domains)
> + return -ENOMEM;
> +
> + bc->onecell_data.num_domains = num_domains;
> + bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
> + bc->onecell_data.domains =
> + devm_kcalloc(dev, num_domains,
> + sizeof(struct generic_pm_domain *), GFP_KERNEL);
> + if (!bc->onecell_data.domains)
> + return -ENOMEM;
> +
> + bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
> + if (IS_ERR(bc->bus_power_dev))
> + return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
> + "failed to attach power domain\n");
> +
> + for (i = 0; i < num_domains; i++) {
> + const struct imx8mp_hsio_blk_ctrl_domain_data *data =
> + &imx8mp_hsio_domain_data[i];
> + struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
> +
> + if (data->clk_name) {
> + domain->clk = devm_clk_get(dev, data->clk_name);
> + if (IS_ERR(domain->clk)) {
> + ret = PTR_ERR(domain->clk);
> + dev_err_probe(dev, ret, "failed to get clock\n");
> + goto cleanup_pds;
> + }
> + }
> +
> + domain->power_dev =
> + dev_pm_domain_attach_by_name(dev, data->gpc_name);
> + if (IS_ERR(domain->power_dev)) {
> + dev_err_probe(dev, PTR_ERR(domain->power_dev),
> + "failed to attach power domain\n");
> + ret = PTR_ERR(domain->power_dev);
> + goto cleanup_pds;
> + }
> +
> + domain->genpd.name = data->name;
> + domain->genpd.power_on = imx8mp_hsio_blk_ctrl_power_on;
> + domain->genpd.power_off = imx8mp_hsio_blk_ctrl_power_off;
> + domain->bc = bc;
> + domain->id = i;
> +
> + ret = pm_genpd_init(&domain->genpd, NULL, true);
> + if (ret) {
> + dev_err_probe(dev, ret, "failed to init power domain\n");
> + dev_pm_domain_detach(domain->power_dev, true);
> + goto cleanup_pds;
> + }
> +
> + /*
> + * We use runtime PM to trigger power on/off of the upstream GPC
> + * domain, as a strict hierarchical parent/child power domain
> + * setup doesn't allow us to meet the sequencing requirements.
> + * This means we have nested locking of genpd locks, without the
> + * nesting being visible at the genpd level, so we need a
> + * separate lock class to make lockdep aware of the fact that
> + * this are separate domain locks that can be nested without a
> + * self-deadlock.
> + */
> + lockdep_set_class(&domain->genpd.mlock,
> + &blk_ctrl_genpd_lock_class);
> +
> + bc->onecell_data.domains[i] = &domain->genpd;
> + }
> +
> + ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
> + if (ret) {
> + dev_err_probe(dev, ret, "failed to add power domain provider\n");
> + goto cleanup_pds;
> + }
> +
> + bc->power_nb.notifier_call = imx8mp_hsio_power_notifier;
> + ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
> + if (ret) {
> + dev_err_probe(dev, ret, "failed to add power notifier\n");
> + goto cleanup_provider;
> + }
> +
> + dev_set_drvdata(dev, bc);
> +
> + return 0;
> +
> +cleanup_provider:
> + of_genpd_del_provider(dev->of_node);
> +cleanup_pds:
> + for (i--; i >= 0; i--) {
> + pm_genpd_remove(&bc->domains[i].genpd);
> + dev_pm_domain_detach(bc->domains[i].power_dev, true);
> + }
> +
> + dev_pm_domain_detach(bc->bus_power_dev, true);
> +
> + return ret;
> +}
> +
> +static int imx8mp_hsio_blk_ctrl_remove(struct platform_device *pdev)
> +{
> + struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
> + int i;
> +
> + of_genpd_del_provider(pdev->dev.of_node);
> +
> + for (i = 0; bc->onecell_data.num_domains; i++) {
> + struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
> +
> + pm_genpd_remove(&domain->genpd);
> + dev_pm_domain_detach(domain->power_dev, true);
> + }
> +
> + dev_pm_genpd_remove_notifier(bc->bus_power_dev);
> +
> + dev_pm_domain_detach(bc->bus_power_dev, true);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int imx8mp_hsio_blk_ctrl_suspend(struct device *dev)
> +{
> + struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(dev);
> + int ret, i;
> +
> + /*
> + * This may look strange, but is done so the generic PM_SLEEP code
> + * can power down our domains and more importantly power them up again
> + * after resume, without tripping over our usage of runtime PM to
> + * control the upstream GPC domains. Things happen in the right order
> + * in the system suspend/resume paths due to the device parent/child
> + * hierarchy.
> + */
> + ret = pm_runtime_get_sync(bc->bus_power_dev);
> + if (ret < 0) {
> + pm_runtime_put_noidle(bc->bus_power_dev);
> + return ret;
> + }
> +
> + for (i = 0; i < bc->onecell_data.num_domains; i++) {
> + struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
> +
> + ret = pm_runtime_get_sync(domain->power_dev);
> + if (ret < 0) {
> + pm_runtime_put_noidle(domain->power_dev);
> + goto out_fail;
> + }
> + }
> +
> + return 0;
> +
> +out_fail:
> + for (i--; i >= 0; i--)
> + pm_runtime_put(bc->domains[i].power_dev);
> +
> + pm_runtime_put(bc->bus_power_dev);
> +
> + return ret;
> +}
> +
> +static int imx8mp_hsio_blk_ctrl_resume(struct device *dev)
> +{
> + struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(dev);
> + int i;
> +
> + for (i = 0; i < bc->onecell_data.num_domains; i++)
> + pm_runtime_put(bc->domains[i].power_dev);
> +
> + pm_runtime_put(bc->bus_power_dev);
> +
> + return 0;
> +}
> +#endif
> +
> +static const struct dev_pm_ops imx8mp_hsio_blk_ctrl_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(imx8mp_hsio_blk_ctrl_suspend,
> + imx8mp_hsio_blk_ctrl_resume)
> +};
> +
> +static const struct of_device_id imx8mp_hsio_blk_ctrl_of_match[] = {
> + {
> + .compatible = "fsl,imx8mp-hsio-blk-ctrl",
> + }, {
> + /* Sentinel */
> + }
> +};
> +MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
> +
> +static struct platform_driver imx8mp_hsio_blk_ctrl_driver = {
> + .probe = imx8mp_hsio_blk_ctrl_probe,
> + .remove = imx8mp_hsio_blk_ctrl_remove,
> + .driver = {
> + .name = "imx8mp-hsio-blk-ctrl",
> + .pm = &imx8mp_hsio_blk_ctrl_pm_ops,
> + .of_match_table = imx8mp_hsio_blk_ctrl_of_match,
> + },
> +};
> +module_platform_driver(imx8mp_hsio_blk_ctrl_driver);
> --
> 2.30.2
>
^ permalink raw reply
* Re: [PATCH] arm64: dts: marvell: armada-37xx: Increase PCIe IO size from 64 KiB to 1 MiB
From: Gregory CLEMENT @ 2022-01-21 9:02 UTC (permalink / raw)
To: Pali Rohár
Cc: Andrew Lunn, Sebastian Hesselbarth, Rob Herring, Marek Behún,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20220113170755.11856-1-pali@kernel.org>
Pali Rohár <pali@kernel.org> writes:
> Commit 514ef1e62d65 ("arm64: dts: marvell: armada-37xx: Extend PCIe MEM
> space") increased size of PCIe MEM to 127 MiB, which is the maximal
> possible size for allocated 128 MiB PCIe window. PCIe IO size in that
> commit was unchanged.
>
> Armada 3720 PCIe controller supports 32-bit IO space mapping so it is
> possible to assign more than 64 KiB if address space for IO.
>
> Currently controller has assigned 127 MiB + 64 KiB memory and therefore
> there is 960 KiB of unused memory. So assign it to IO space by increasing
> IO window from 64 KiB to 1 MiB.
>
> DTS file armada-3720-turris-mox.dts already uses whole 128 MiB space, so
> only update comment about 32-bit IO space mapping.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Fixes: 514ef1e62d65 ("arm64: dts: marvell: armada-37xx: Extend PCIe
> MEM space")
Applied on mvebu/fixes
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 2 +-
> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
> index dd01409d4bb7..23e1b07c060a 100644
> --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
> @@ -153,7 +153,7 @@
> * 2 size cells and also expects that the second range starts at 16 MB offset. If these
> * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
> * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
> - * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
> + * for IO and the rest 112 MB (64+32+16) for MEM. Controller supports 32-bit IO mapping.
> * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
> * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
> * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
> diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> index 1c74f02535c6..8d59eabadce6 100644
> --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> @@ -508,12 +508,12 @@
> /*
> * The 128 MiB address range [0xe8000000-0xf0000000] is
> * dedicated for PCIe and can be assigned to 8 windows
> - * with size a power of two. Use one 64 KiB window for
> + * with size a power of two. Use one 1 MiB window for
> * IO at the end and the remaining seven windows
> * (totaling 127 MiB) for MEM.
> */
> ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
> - 0x81000000 0 0xefff0000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
> + 0x81000000 0 0xeff00000 0 0xeff00000 0 0x00100000>; /* Port 0 IO*/
> interrupt-map-mask = <0 0 0 7>;
> interrupt-map = <0 0 0 1 &pcie_intc 0>,
> <0 0 0 2 &pcie_intc 1>,
> --
> 2.20.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply
* Re: [PATCH] dt-bindings: mfd: cirrus,madera: Fix 'interrupts' in example
From: Lee Jones @ 2022-01-21 8:39 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel, alsa-devel, Charles Keepax, -, Richard Fitzgerald,
devicetree
In-Reply-To: <Yem5rQ7RFG3bUUxV@robh.at.kernel.org>
On Thu, 20 Jan 2022, Rob Herring wrote:
> On Tue, 18 Jan 2022 19:56:11 -0600, Rob Herring wrote:
> > The 'interrupts' properties takes an irq number, not a phandle, and
> > 'interrupt-parent' isn't needed in examples.
> > ---
> > Documentation/devicetree/bindings/mfd/cirrus,madera.yaml | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
>
> Applied (with my Sob added), thanks!
Was going to say ... :)
Please add my Ack too:
Acked-by: Lee Jones <lee.jones@linaro.org>
--
Lee Jones [李琼斯]
Principal Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v4 3/3] dmaengine: sf-pdma: Get number of channel by device tree
From: Geert Uytterhoeven @ 2022-01-21 8:33 UTC (permalink / raw)
To: Zong Li
Cc: Palmer Dabbelt, Rob Herring, Paul Walmsley, Albert Ou,
Krzysztof Kozlowski, Conor Dooley, Bin Meng, Green Wan, Vinod,
dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org List, linux-riscv
In-Reply-To: <CANXhq0ruGxjO0WPUipzZ7QQM1oEapyHAvb_aVQ_CMqVxbjc_BQ@mail.gmail.com>
Hi Zong, Palmer,
On Fri, Jan 21, 2022 at 3:21 AM Zong Li <zong.li@sifive.com> wrote:
> On Fri, Jan 21, 2022 at 2:52 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> > On Sun, 16 Jan 2022 17:35:28 PST (-0800), zong.li@sifive.com wrote:
> > > It currently assumes that there are always four channels, it would
> > > cause the error if there is actually less than four channels. Change
> > > that by getting number of channel from device tree.
> > >
> > > For backwards-compatible, it uses the default value (i.e. 4) when there
> > > is no 'dma-channels' information in dts.
> >
> > Some of the same wording issues here as those I pointed out in the DT
> > bindings patch.
> >
> > > Signed-off-by: Zong Li <zong.li@sifive.com>
> > > --- a/drivers/dma/sf-pdma/sf-pdma.c
> > > +++ b/drivers/dma/sf-pdma/sf-pdma.c
> > > @@ -482,9 +482,7 @@ static void sf_pdma_setup_chans(struct sf_pdma *pdma)
> > > static int sf_pdma_probe(struct platform_device *pdev)
> > > {
> > > struct sf_pdma *pdma;
> > > - struct sf_pdma_chan *chan;
> > > struct resource *res;
> > > - int len, chans;
> > > int ret;
> > > const enum dma_slave_buswidth widths =
> > > DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES |
> > > @@ -492,13 +490,21 @@ static int sf_pdma_probe(struct platform_device *pdev)
> > > DMA_SLAVE_BUSWIDTH_16_BYTES | DMA_SLAVE_BUSWIDTH_32_BYTES |
> > > DMA_SLAVE_BUSWIDTH_64_BYTES;
> > >
> > > - chans = PDMA_NR_CH;
> > > - len = sizeof(*pdma) + sizeof(*chan) * chans;
> > > - pdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
> > > + pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
> > > if (!pdma)
> > > return -ENOMEM;
> > >
> > > - pdma->n_chans = chans;
> > > + ret = of_property_read_u32(pdev->dev.of_node, "dma-channels",
> > > + &pdma->n_chans);
> > > + if (ret) {
> > > + dev_notice(&pdev->dev, "set number of channels to default value: 4\n");
> > > + pdma->n_chans = PDMA_MAX_NR_CH;
> > > + }
> > > +
> > > + if (pdma->n_chans > PDMA_MAX_NR_CH) {
> > > + dev_err(&pdev->dev, "the number of channels exceeds the maximum\n");
> > > + return -EINVAL;
> >
> > Can we get away with just using only the number of channels the driver
> > actually supports? ie, just never sending an op to the channels above
> > MAX_NR_CH? That should leave us with nothing to track.
In theory we can...
> It might be a bit like when pdma->n_chans is bigger than the maximum,
> set the pdma->chans to PDMA_MAX_NR_CH, then we could ensure that we
> don't access the channels above the maximum. If I understand
> correctly, I gave the similar thought in the thread of v2 patch, and
> there are some discussions on that, but this way seems to lead to
> hard-to-track problems.
... but that would mean that when a new variant appears that supports
more channels, no error is printed, and people might not notice
immediately that the higher channels are never used.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [RFC PATCH v2 5/7] ARM: dts: bcm2711: Add unicam CSI nodes
From: Jean-Michel Hautbois @ 2022-01-21 8:18 UTC (permalink / raw)
To: jeanmichel.hautbois
Cc: dave.stevenson, devicetree, kernel-list, laurent.pinchart,
linux-arm-kernel, linux-kernel, linux-media, linux-rpi-kernel,
lukasz, mchehab, naush, robh, tomi.valkeinen
In-Reply-To: <20220121081810.155500-1-jeanmichel.hautbois@ideasonboard.com>
Add both MIPI CSI-2 nodes in the core bcm2711 tree. Use the 3-cells
interrupt declaration, corresponding clocks and default as disabled.
Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
---
arch/arm/boot/dts/bcm2711.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index dff18fc9a906..077141df7024 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/bcm2835-pm.h>
+#include <dt-bindings/power/raspberrypi-power.h>
/ {
compatible = "brcm,bcm2711";
@@ -293,6 +294,36 @@ hvs: hvs@7e400000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
};
+ csi0: csi1@7e800000 {
+ compatible = "brcm,bcm2835-unicam";
+ reg = <0x7e800000 0x800>,
+ <0x7e802000 0x4>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_CAM0>,
+ <&firmware_clocks 4>;
+ clock-names = "lp", "vpu";
+ power-domains = <&power RPI_POWER_DOMAIN_UNICAM0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ status="disabled";
+ };
+
+ csi1: csi1@7e801000 {
+ compatible = "brcm,bcm2835-unicam";
+ reg = <0x7e801000 0x800>,
+ <0x7e802004 0x4>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_CAM1>,
+ <&firmware_clocks 4>;
+ clock-names = "lp", "vpu";
+ power-domains = <&power RPI_POWER_DOMAIN_UNICAM1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ status="disabled";
+ };
+
pixelvalve3: pixelvalve@7ec12000 {
compatible = "brcm,bcm2711-pixelvalve3";
reg = <0x7ec12000 0x100>;
--
2.32.0
^ permalink raw reply related
* [RFC PATCH v2 7/7] media: bcm283x: Include the imx219 node
From: Jean-Michel Hautbois @ 2022-01-21 8:18 UTC (permalink / raw)
To: jeanmichel.hautbois
Cc: dave.stevenson, devicetree, kernel-list, laurent.pinchart,
linux-arm-kernel, linux-kernel, linux-media, linux-rpi-kernel,
lukasz, mchehab, naush, robh, tomi.valkeinen
In-Reply-To: <20220121081810.155500-1-jeanmichel.hautbois@ideasonboard.com>
Configure the csi1 endpoint, add the imx219 node and connect it through
the i2c mux.
Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
---
MAINTAINERS | 1 +
arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 1 +
arch/arm/boot/dts/bcm283x-rpi-imx219.dtsi | 102 ++++++++++++++++++++++
3 files changed, 104 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm283x-rpi-imx219.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index b17bb533e007..56544ac98d69 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3684,6 +3684,7 @@ M: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
L: linux-media@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
+F: arch/arm/boot/dts/bcm283x*
F: drivers/media/platform/bcm2835/
BROADCOM BCM47XX MIPS ARCHITECTURE
diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
index 4432412044de..f7625b70fe57 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
@@ -4,6 +4,7 @@
#include "bcm2711-rpi.dtsi"
#include "bcm283x-rpi-usb-peripheral.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
+#include "bcm283x-rpi-imx219.dtsi"
/ {
compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
diff --git a/arch/arm/boot/dts/bcm283x-rpi-imx219.dtsi b/arch/arm/boot/dts/bcm283x-rpi-imx219.dtsi
new file mode 100644
index 000000000000..f2c6a85fd731
--- /dev/null
+++ b/arch/arm/boot/dts/bcm283x-rpi-imx219.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/bcm2835.h>
+
+/ {
+ compatible = "brcm,bcm2835";
+
+ imx219_vdig: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "imx219_vdig";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ imx219_vddl: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "imx219_vddl";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ imx219_clk: imx219_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "24MHz-clock";
+ };
+
+ cam1_reg: cam1_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "imx219_vana";
+ enable-active-high;
+ status = "okay";
+ gpio = <&expgpio 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ i2c0mux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-parent = <&i2c0>;
+
+ pinctrl-names = "i2c0", "i2c_csi_dsi";
+ pinctrl-0 = <&i2c0_gpio0>;
+ pinctrl-1 = <&i2c0_gpio44>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ imx219: sensor@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+ status = "okay";
+
+ clocks = <&imx219_clk>;
+ clock-names = "xclk";
+
+ VANA-supply = <&cam1_reg>; /* 2.8v */
+ VDIG-supply = <&imx219_vdig>; /* 1.8v */
+ VDDL-supply = <&imx219_vddl>; /* 1.2v */
+
+ rotation = <0>;
+ orientation = <0>;
+
+ port {
+ imx219_0: endpoint {
+ remote-endpoint = <&csi1_ep>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ clock-noncontinuous;
+ link-frequencies = /bits/ 64 <456000000>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&csi1 {
+ status="okay";
+ num-data-lanes = <2>;
+ port {
+ csi1_ep: endpoint {
+ remote-endpoint = <&imx219_0>;
+ data-lanes = <1 2>;
+ clock-lanes = <0>;
+ };
+ };
+};
+
+&i2c0 {
+ /delete-property/ pinctrl-names;
+ /delete-property/ pinctrl-0;
+};
+
--
2.32.0
^ permalink raw reply related
* [RFC PATCH v2 6/7] media: imx219: Add support for multiplexed streams
From: Jean-Michel Hautbois @ 2022-01-21 8:18 UTC (permalink / raw)
To: jeanmichel.hautbois
Cc: dave.stevenson, devicetree, kernel-list, laurent.pinchart,
linux-arm-kernel, linux-kernel, linux-media, linux-rpi-kernel,
lukasz, mchehab, naush, robh, tomi.valkeinen
In-Reply-To: <20220121081810.155500-1-jeanmichel.hautbois@ideasonboard.com>
As of now, imx219 was not supporting anything more than one stream. Add
support for embedded data, based on linux-rpi kernel, and make it work
with multiplexed streams. We have only one source pad with two streams:
stream 0 is the image, and stream 1 is the embedded data.
Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
---
in v2: modified the get_format_pad function as it was not correctly
propagating the format in case of sensor flips.
---
drivers/media/i2c/imx219.c | 452 ++++++++++++++++++++-----------------
1 file changed, 241 insertions(+), 211 deletions(-)
diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
index e10af3f74b38..d73fe6b8b2fb 100644
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
@@ -118,6 +118,16 @@
#define IMX219_PIXEL_ARRAY_WIDTH 3280U
#define IMX219_PIXEL_ARRAY_HEIGHT 2464U
+/* Embedded metadata stream structure */
+#define IMX219_EMBEDDED_LINE_WIDTH 16384
+#define IMX219_NUM_EMBEDDED_LINES 1
+
+enum pad_types {
+ IMAGE_PAD,
+ METADATA_PAD,
+ NUM_PADS
+};
+
struct imx219_reg {
u16 address;
u8 val;
@@ -429,7 +439,7 @@ static const char * const imx219_supply_name[] = {
* - v flip
* - h&v flips
*/
-static const u32 codes[] = {
+static const u32 imx219_mbus_formats[] = {
MEDIA_BUS_FMT_SRGGB10_1X10,
MEDIA_BUS_FMT_SGRBG10_1X10,
MEDIA_BUS_FMT_SGBRG10_1X10,
@@ -655,62 +665,17 @@ static u32 imx219_get_format_code(struct imx219 *imx219, u32 code)
lockdep_assert_held(&imx219->mutex);
- for (i = 0; i < ARRAY_SIZE(codes); i++)
- if (codes[i] == code)
+ for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); i++)
+ if (imx219_mbus_formats[i] == code)
break;
- if (i >= ARRAY_SIZE(codes))
+ if (i >= ARRAY_SIZE(imx219_mbus_formats))
i = 0;
i = (i & ~3) | (imx219->vflip->val ? 2 : 0) |
(imx219->hflip->val ? 1 : 0);
- return codes[i];
-}
-
-static void imx219_set_default_format(struct imx219 *imx219)
-{
- struct v4l2_mbus_framefmt *fmt;
-
- fmt = &imx219->fmt;
- fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
- fmt->colorspace = V4L2_COLORSPACE_SRGB;
- fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
- fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
- fmt->colorspace,
- fmt->ycbcr_enc);
- fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
- fmt->width = supported_modes[0].width;
- fmt->height = supported_modes[0].height;
- fmt->field = V4L2_FIELD_NONE;
-}
-
-static int imx219_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
-{
- struct imx219 *imx219 = to_imx219(sd);
- struct v4l2_mbus_framefmt *try_fmt =
- v4l2_subdev_get_try_format(sd, fh->state, 0);
- struct v4l2_rect *try_crop;
-
- mutex_lock(&imx219->mutex);
-
- /* Initialize try_fmt */
- try_fmt->width = supported_modes[0].width;
- try_fmt->height = supported_modes[0].height;
- try_fmt->code = imx219_get_format_code(imx219,
- MEDIA_BUS_FMT_SRGGB10_1X10);
- try_fmt->field = V4L2_FIELD_NONE;
-
- /* Initialize try_crop rectangle. */
- try_crop = v4l2_subdev_get_try_crop(sd, fh->state, 0);
- try_crop->top = IMX219_PIXEL_ARRAY_TOP;
- try_crop->left = IMX219_PIXEL_ARRAY_LEFT;
- try_crop->width = IMX219_PIXEL_ARRAY_WIDTH;
- try_crop->height = IMX219_PIXEL_ARRAY_HEIGHT;
-
- mutex_unlock(&imx219->mutex);
-
- return 0;
+ return imx219_mbus_formats[i];
}
static int imx219_set_ctrl(struct v4l2_ctrl *ctrl)
@@ -802,98 +767,148 @@ static const struct v4l2_ctrl_ops imx219_ctrl_ops = {
.s_ctrl = imx219_set_ctrl,
};
-static int imx219_enum_mbus_code(struct v4l2_subdev *sd,
- struct v4l2_subdev_state *sd_state,
- struct v4l2_subdev_mbus_code_enum *code)
+static void imx219_init_formats(struct v4l2_subdev_state *state)
{
- struct imx219 *imx219 = to_imx219(sd);
+ struct v4l2_mbus_framefmt *format;
+
+ format = v4l2_state_get_stream_format(state, 0, 0);
+ format->code = imx219_mbus_formats[0];
+ format->width = supported_modes[0].width;
+ format->height = supported_modes[0].height;
+ format->field = V4L2_FIELD_NONE;
+ format->colorspace = V4L2_COLORSPACE_RAW;
+
+ if (state->routing.routes[1].flags & V4L2_SUBDEV_ROUTE_FL_ACTIVE) {
+ format = v4l2_state_get_stream_format(state, 0, 1);
+ format->code = MEDIA_BUS_FMT_METADATA_8;
+ format->width = IMX219_EMBEDDED_LINE_WIDTH;
+ format->height = 1;
+ format->field = V4L2_FIELD_NONE;
+ format->colorspace = V4L2_COLORSPACE_DEFAULT;
+ }
+}
- if (code->index >= (ARRAY_SIZE(codes) / 4))
- return -EINVAL;
+static int _imx219_set_routing(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state)
+{
+ struct v4l2_subdev_route routes[] = {
+ {
+ .source_pad = 0,
+ .source_stream = 0,
+ .flags = V4L2_SUBDEV_ROUTE_FL_IMMUTABLE |
+ V4L2_SUBDEV_ROUTE_FL_SOURCE |
+ V4L2_SUBDEV_ROUTE_FL_ACTIVE,
+ },
+ {
+ .source_pad = 0,
+ .source_stream = 1,
+ .flags = V4L2_SUBDEV_ROUTE_FL_SOURCE |
+ V4L2_SUBDEV_ROUTE_FL_ACTIVE,
+ }
+ };
- mutex_lock(&imx219->mutex);
- code->code = imx219_get_format_code(imx219, codes[code->index * 4]);
- mutex_unlock(&imx219->mutex);
+ struct v4l2_subdev_krouting routing = {
+ .num_routes = ARRAY_SIZE(routes),
+ .routes = routes,
+ };
+
+ int ret;
+
+ ret = v4l2_subdev_set_routing(sd, state, &routing);
+ if (ret)
+ return ret;
+
+ imx219_init_formats(state);
return 0;
}
-static int imx219_enum_frame_size(struct v4l2_subdev *sd,
- struct v4l2_subdev_state *sd_state,
- struct v4l2_subdev_frame_size_enum *fse)
+static int imx219_set_routing(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ enum v4l2_subdev_format_whence which,
+ struct v4l2_subdev_krouting *routing)
{
- struct imx219 *imx219 = to_imx219(sd);
- u32 code;
+ int ret;
- if (fse->index >= ARRAY_SIZE(supported_modes))
+ if (routing->num_routes == 0 || routing->num_routes > 2)
return -EINVAL;
- mutex_lock(&imx219->mutex);
- code = imx219_get_format_code(imx219, fse->code);
- mutex_unlock(&imx219->mutex);
- if (fse->code != code)
- return -EINVAL;
+ v4l2_subdev_lock_state(state);
- fse->min_width = supported_modes[fse->index].width;
- fse->max_width = fse->min_width;
- fse->min_height = supported_modes[fse->index].height;
- fse->max_height = fse->min_height;
+ ret = _imx219_set_routing(sd, state);
- return 0;
+ v4l2_subdev_unlock_state(state);
+
+ return ret;
}
-static void imx219_reset_colorspace(struct v4l2_mbus_framefmt *fmt)
+static int imx219_init_cfg(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state)
{
- fmt->colorspace = V4L2_COLORSPACE_SRGB;
- fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
- fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
- fmt->colorspace,
- fmt->ycbcr_enc);
- fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
+ int ret;
+
+ v4l2_subdev_lock_state(state);
+
+ ret = _imx219_set_routing(sd, state);
+
+ v4l2_subdev_unlock_state(state);
+
+ return ret;
}
-static void imx219_update_pad_format(struct imx219 *imx219,
- const struct imx219_mode *mode,
- struct v4l2_subdev_format *fmt)
+static int imx219_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_mbus_code_enum *code)
{
- fmt->format.width = mode->width;
- fmt->format.height = mode->height;
- fmt->format.field = V4L2_FIELD_NONE;
- imx219_reset_colorspace(&fmt->format);
+ if (code->index >= ARRAY_SIZE(imx219_mbus_formats))
+ return -EINVAL;
+
+ code->code = imx219_mbus_formats[code->index];
+
+ return 0;
}
-static int __imx219_get_pad_format(struct imx219 *imx219,
- struct v4l2_subdev_state *sd_state,
- struct v4l2_subdev_format *fmt)
+static int imx219_enum_frame_size(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_frame_size_enum *fse)
{
- if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
- struct v4l2_mbus_framefmt *try_fmt =
- v4l2_subdev_get_try_format(&imx219->sd, sd_state,
- fmt->pad);
- /* update the code which could change due to vflip or hflip: */
- try_fmt->code = imx219_get_format_code(imx219, try_fmt->code);
- fmt->format = *try_fmt;
+ unsigned int i;
+
+ if (fse->stream == 0) {
+ for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); ++i) {
+ if (imx219_mbus_formats[i] == fse->code)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(imx219_mbus_formats))
+ return -EINVAL;
+
+ if (fse->index >= ARRAY_SIZE(supported_modes))
+ return -EINVAL;
+
+ fse->min_width = supported_modes[fse->index].width;
+ fse->max_width = fse->min_width;
+ fse->max_height = supported_modes[fse->index].height;
+ fse->min_height = fse->max_height;
} else {
- imx219_update_pad_format(imx219, imx219->mode, fmt);
- fmt->format.code = imx219_get_format_code(imx219,
- imx219->fmt.code);
+ if (fse->code != MEDIA_BUS_FMT_METADATA_8)
+ return -EINVAL;
+
+ fse->min_width = IMX219_EMBEDDED_LINE_WIDTH;
+ fse->max_width = fse->min_width;
+ fse->min_height = IMX219_NUM_EMBEDDED_LINES;
+ fse->max_height = fse->min_height;
}
return 0;
}
-static int imx219_get_pad_format(struct v4l2_subdev *sd,
- struct v4l2_subdev_state *sd_state,
- struct v4l2_subdev_format *fmt)
+static void imx219_update_metadata_pad_format(struct v4l2_subdev_format *fmt)
{
- struct imx219 *imx219 = to_imx219(sd);
- int ret;
-
- mutex_lock(&imx219->mutex);
- ret = __imx219_get_pad_format(imx219, sd_state, fmt);
- mutex_unlock(&imx219->mutex);
-
- return ret;
+ fmt->format.width = IMX219_EMBEDDED_LINE_WIDTH;
+ fmt->format.height = IMX219_NUM_EMBEDDED_LINES;
+ fmt->format.code = MEDIA_BUS_FMT_METADATA_8;
+ fmt->format.field = V4L2_FIELD_NONE;
}
static int imx219_set_pad_format(struct v4l2_subdev *sd,
@@ -901,82 +916,91 @@ static int imx219_set_pad_format(struct v4l2_subdev *sd,
struct v4l2_subdev_format *fmt)
{
struct imx219 *imx219 = to_imx219(sd);
+ struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
const struct imx219_mode *mode;
- struct v4l2_mbus_framefmt *framefmt;
- int exposure_max, exposure_def, hblank;
+ struct v4l2_mbus_framefmt *format;
unsigned int i;
+ int ret = 0;
+ int exposure_max, exposure_def, hblank;
- mutex_lock(&imx219->mutex);
+ if (fmt->pad != 0) {
+ dev_err(&client->dev, "%s Could not get pad %d\n", __func__,
+ fmt->pad);
+ return -EINVAL;
+ }
- for (i = 0; i < ARRAY_SIZE(codes); i++)
- if (codes[i] == fmt->format.code)
+ if (fmt->stream == 1) {
+ /* Only one embedded data mode is supported */
+ imx219_update_metadata_pad_format(fmt);
+ return 0;
+ }
+
+ if (fmt->stream != 0)
+ return -EINVAL;
+
+ /*
+ * Validate the media bus code, defaulting to the first one if the
+ * requested code isn't supported.
+ */
+ for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); ++i) {
+ if (imx219_mbus_formats[i] == fmt->format.code)
break;
- if (i >= ARRAY_SIZE(codes))
- i = 0;
+ }
- /* Bayer order varies with flips */
- fmt->format.code = imx219_get_format_code(imx219, codes[i]);
+ if (i >= ARRAY_SIZE(imx219_mbus_formats))
+ i = 0;
mode = v4l2_find_nearest_size(supported_modes,
ARRAY_SIZE(supported_modes),
width, height,
- fmt->format.width, fmt->format.height);
- imx219_update_pad_format(imx219, mode, fmt);
- if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
- framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
- *framefmt = fmt->format;
- } else if (imx219->mode != mode ||
- imx219->fmt.code != fmt->format.code) {
- imx219->fmt = fmt->format;
- imx219->mode = mode;
- /* Update limits and set FPS to default */
- __v4l2_ctrl_modify_range(imx219->vblank, IMX219_VBLANK_MIN,
- IMX219_VTS_MAX - mode->height, 1,
- mode->vts_def - mode->height);
- __v4l2_ctrl_s_ctrl(imx219->vblank,
- mode->vts_def - mode->height);
- /* Update max exposure while meeting expected vblanking */
- exposure_max = mode->vts_def - 4;
- exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
- exposure_max : IMX219_EXPOSURE_DEFAULT;
- __v4l2_ctrl_modify_range(imx219->exposure,
- imx219->exposure->minimum,
- exposure_max, imx219->exposure->step,
- exposure_def);
- /*
- * Currently PPL is fixed to IMX219_PPL_DEFAULT, so hblank
- * depends on mode->width only, and is not changeble in any
- * way other than changing the mode.
- */
- hblank = IMX219_PPL_DEFAULT - mode->width;
- __v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank, 1,
- hblank);
- }
+ fmt->format.width,
+ fmt->format.height);
- mutex_unlock(&imx219->mutex);
+ v4l2_subdev_lock_state(sd_state);
- return 0;
-}
+ /* Update the stored format and return it. */
+ format = v4l2_state_get_stream_format(sd_state, fmt->pad, fmt->stream);
-static int imx219_set_framefmt(struct imx219 *imx219)
-{
- switch (imx219->fmt.code) {
- case MEDIA_BUS_FMT_SRGGB8_1X8:
- case MEDIA_BUS_FMT_SGRBG8_1X8:
- case MEDIA_BUS_FMT_SGBRG8_1X8:
- case MEDIA_BUS_FMT_SBGGR8_1X8:
- return imx219_write_regs(imx219, raw8_framefmt_regs,
- ARRAY_SIZE(raw8_framefmt_regs));
-
- case MEDIA_BUS_FMT_SRGGB10_1X10:
- case MEDIA_BUS_FMT_SGRBG10_1X10:
- case MEDIA_BUS_FMT_SGBRG10_1X10:
- case MEDIA_BUS_FMT_SBGGR10_1X10:
- return imx219_write_regs(imx219, raw10_framefmt_regs,
- ARRAY_SIZE(raw10_framefmt_regs));
+ if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE && imx219->streaming) {
+ ret = -EBUSY;
+ goto done;
}
- return -EINVAL;
+ /* Bayer order varies with flips */
+ fmt->format.code = imx219_get_format_code(imx219, imx219_mbus_formats[i]);
+ fmt->format = *format;
+
+ /* Update limits and set FPS to default */
+ __v4l2_ctrl_modify_range(imx219->vblank,
+ IMX219_VBLANK_MIN,
+ IMX219_VTS_MAX - mode->height,
+ 1,
+ mode->vts_def - mode->height);
+ __v4l2_ctrl_s_ctrl(imx219->vblank, mode->vts_def - mode->height);
+ /*
+ * Update max exposure while meeting
+ * expected vblanking
+ */
+ exposure_max = mode->vts_def - 4;
+ exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
+ exposure_max : IMX219_EXPOSURE_DEFAULT;
+ __v4l2_ctrl_modify_range(imx219->exposure,
+ imx219->exposure->minimum,
+ exposure_max,
+ imx219->exposure->step,
+ exposure_def);
+ /*
+ * Currently PPL is fixed to IMX219_PPL_DEFAULT, so
+ * hblank depends on mode->width only, and is not
+ * changeble in any way other than changing the mode.
+ */
+ hblank = IMX219_PPL_DEFAULT - mode->width;
+ __v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank, 1, hblank);
+
+done:
+ v4l2_subdev_unlock_state(sd_state);
+
+ return ret;
}
static const struct v4l2_rect *
@@ -1037,9 +1061,11 @@ static int imx219_start_streaming(struct imx219 *imx219)
const struct imx219_reg_list *reg_list;
int ret;
- ret = pm_runtime_resume_and_get(&client->dev);
- if (ret < 0)
+ ret = pm_runtime_get_sync(&client->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(&client->dev);
return ret;
+ }
/* Apply default values of current mode */
reg_list = &imx219->mode->reg_list;
@@ -1049,13 +1075,6 @@ static int imx219_start_streaming(struct imx219 *imx219)
goto err_rpm_put;
}
- ret = imx219_set_framefmt(imx219);
- if (ret) {
- dev_err(&client->dev, "%s failed to set frame format: %d\n",
- __func__, ret);
- goto err_rpm_put;
- }
-
/* Apply customized values from user */
ret = __v4l2_ctrl_handler_setup(imx219->sd.ctrl_handler);
if (ret)
@@ -1133,21 +1152,22 @@ static int imx219_set_stream(struct v4l2_subdev *sd, int enable)
/* Power/clock management functions */
static int imx219_power_on(struct device *dev)
{
- struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct imx219 *imx219 = to_imx219(sd);
int ret;
ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES,
imx219->supplies);
if (ret) {
- dev_err(dev, "%s: failed to enable regulators\n",
+ dev_err(&client->dev, "%s: failed to enable regulators\n",
__func__);
return ret;
}
ret = clk_prepare_enable(imx219->xclk);
if (ret) {
- dev_err(dev, "%s: failed to enable clock\n",
+ dev_err(&client->dev, "%s: failed to enable clock\n",
__func__);
goto reg_off;
}
@@ -1166,7 +1186,8 @@ static int imx219_power_on(struct device *dev)
static int imx219_power_off(struct device *dev)
{
- struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct imx219 *imx219 = to_imx219(sd);
gpiod_set_value_cansleep(imx219->reset_gpio, 0);
@@ -1178,7 +1199,8 @@ static int imx219_power_off(struct device *dev)
static int __maybe_unused imx219_suspend(struct device *dev)
{
- struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct imx219 *imx219 = to_imx219(sd);
if (imx219->streaming)
@@ -1189,7 +1211,8 @@ static int __maybe_unused imx219_suspend(struct device *dev)
static int __maybe_unused imx219_resume(struct device *dev)
{
- struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct imx219 *imx219 = to_imx219(sd);
int ret;
@@ -1255,11 +1278,13 @@ static const struct v4l2_subdev_video_ops imx219_video_ops = {
};
static const struct v4l2_subdev_pad_ops imx219_pad_ops = {
- .enum_mbus_code = imx219_enum_mbus_code,
- .get_fmt = imx219_get_pad_format,
- .set_fmt = imx219_set_pad_format,
- .get_selection = imx219_get_selection,
- .enum_frame_size = imx219_enum_frame_size,
+ .init_cfg = imx219_init_cfg,
+ .enum_mbus_code = imx219_enum_mbus_code,
+ .get_fmt = v4l2_subdev_get_fmt,
+ .set_fmt = imx219_set_pad_format,
+ .get_selection = imx219_get_selection,
+ .set_routing = imx219_set_routing,
+ .enum_frame_size = imx219_enum_frame_size,
};
static const struct v4l2_subdev_ops imx219_subdev_ops = {
@@ -1268,10 +1293,6 @@ static const struct v4l2_subdev_ops imx219_subdev_ops = {
.pad = &imx219_pad_ops,
};
-static const struct v4l2_subdev_internal_ops imx219_internal_ops = {
- .open = imx219_open,
-};
-
/* Initialize control handlers */
static int imx219_init_controls(struct imx219 *imx219)
{
@@ -1446,6 +1467,7 @@ static int imx219_check_hwcfg(struct device *dev)
static int imx219_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
+ struct v4l2_subdev *sd;
struct imx219 *imx219;
int ret;
@@ -1453,7 +1475,8 @@ static int imx219_probe(struct i2c_client *client)
if (!imx219)
return -ENOMEM;
- v4l2_i2c_subdev_init(&imx219->sd, client, &imx219_subdev_ops);
+ sd = &imx219->sd;
+ v4l2_i2c_subdev_init(sd, client, &imx219_subdev_ops);
/* Check the hardware configuration in device tree */
if (imx219_check_hwcfg(dev))
@@ -1520,27 +1543,29 @@ static int imx219_probe(struct i2c_client *client)
goto error_power_off;
/* Initialize subdev */
- imx219->sd.internal_ops = &imx219_internal_ops;
- imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
- V4L2_SUBDEV_FL_HAS_EVENTS;
- imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
+ V4L2_SUBDEV_FL_HAS_EVENTS |
+ V4L2_SUBDEV_FL_MULTIPLEXED;
- /* Initialize source pad */
+ /* Initialize the media entity. */
imx219->pad.flags = MEDIA_PAD_FL_SOURCE;
-
- /* Initialize default format */
- imx219_set_default_format(imx219);
-
- ret = media_entity_pads_init(&imx219->sd.entity, 1, &imx219->pad);
+ sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ ret = media_entity_pads_init(&sd->entity, 1, &imx219->pad);
if (ret) {
dev_err(dev, "failed to init entity pads: %d\n", ret);
goto error_handler_free;
}
- ret = v4l2_async_register_subdev_sensor(&imx219->sd);
+ ret = v4l2_subdev_init_finalize(sd);
+ if (ret) {
+ dev_err(dev, "failed to finalize sensor init: %d\n", ret);
+ goto error_media_entity;
+ }
+
+ ret = v4l2_async_register_subdev_sensor(sd);
if (ret < 0) {
dev_err(dev, "failed to register sensor sub-device: %d\n", ret);
- goto error_media_entity;
+ goto error_free_state;
}
/* Enable runtime PM and turn off the device */
@@ -1550,6 +1575,8 @@ static int imx219_probe(struct i2c_client *client)
return 0;
+error_free_state:
+ v4l2_subdev_cleanup(sd);
error_media_entity:
media_entity_cleanup(&imx219->sd.entity);
@@ -1568,6 +1595,9 @@ static int imx219_remove(struct i2c_client *client)
struct imx219 *imx219 = to_imx219(sd);
v4l2_async_unregister_subdev(sd);
+
+ v4l2_subdev_cleanup(sd);
+
media_entity_cleanup(&sd->entity);
imx219_free_controls(imx219);
--
2.32.0
^ permalink raw reply related
* [RFC PATCH v2 4/7] media: bcm2835-unicam: Add support for for CCP2/CSI2 camera interface
From: Jean-Michel Hautbois @ 2022-01-21 8:18 UTC (permalink / raw)
To: jeanmichel.hautbois
Cc: dave.stevenson, devicetree, kernel-list, laurent.pinchart,
linux-arm-kernel, linux-kernel, linux-media, linux-rpi-kernel,
lukasz, mchehab, naush, robh, tomi.valkeinen
In-Reply-To: <20220121081810.155500-1-jeanmichel.hautbois@ideasonboard.com>
Add driver for the Unicam camera receiver block on BCM283x processors.
It is represented as two video device nodes: unicam-image and
unicam-embedded which are connected to an internal subdev (named
unicam-subdev) in order to manage streams routing.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
---
in v2: Remove the unicam_{info,debug,error} macros and use
dev_dbg/dev_err instead.
---
MAINTAINERS | 1 +
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/bcm2835/Kconfig | 21 +
drivers/media/platform/bcm2835/Makefile | 3 +
.../media/platform/bcm2835/bcm2835-unicam.c | 2678 +++++++++++++++++
.../media/platform/bcm2835/vc4-regs-unicam.h | 253 ++
7 files changed, 2959 insertions(+)
create mode 100644 drivers/media/platform/bcm2835/Kconfig
create mode 100644 drivers/media/platform/bcm2835/Makefile
create mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c
create mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 07f238fd5ff9..b17bb533e007 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3684,6 +3684,7 @@ M: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
L: linux-media@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
+F: drivers/media/platform/bcm2835/
BROADCOM BCM47XX MIPS ARCHITECTURE
M: Hauke Mehrtens <hauke@hauke-m.de>
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 9fbdba0fd1e7..033b0358fbb8 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -170,6 +170,7 @@ source "drivers/media/platform/am437x/Kconfig"
source "drivers/media/platform/xilinx/Kconfig"
source "drivers/media/platform/rcar-vin/Kconfig"
source "drivers/media/platform/atmel/Kconfig"
+source "drivers/media/platform/bcm2835/Kconfig"
source "drivers/media/platform/sunxi/Kconfig"
config VIDEO_TI_CAL
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 19bcbced7382..689e64857db1 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -85,6 +85,8 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom/camss/
obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/
+obj-y += bcm2835/
+
obj-y += sunxi/
obj-$(CONFIG_VIDEO_MESON_GE2D) += meson/ge2d/
diff --git a/drivers/media/platform/bcm2835/Kconfig b/drivers/media/platform/bcm2835/Kconfig
new file mode 100644
index 000000000000..bd1370199650
--- /dev/null
+++ b/drivers/media/platform/bcm2835/Kconfig
@@ -0,0 +1,21 @@
+# Broadcom VideoCore4 V4L2 camera support
+
+config VIDEO_BCM2835_UNICAM
+ tristate "Broadcom BCM283x/BCM271x Unicam video capture driver"
+ depends on VIDEO_V4L2
+ depends on ARCH_BCM2835 || COMPILE_TEST
+ select VIDEO_V4L2_SUBDEV_API
+ select MEDIA_CONTROLLER
+ select VIDEOBUF2_DMA_CONTIG
+ select V4L2_FWNODE
+ help
+ Say Y here to enable support for the BCM283x/BCM271x CSI-2 receiver.
+ This is a V4L2 driver that controls the CSI-2 receiver directly,
+ independently from the VC4 firmware.
+ This driver is mutually exclusive with the use of bcm2835-camera. The
+ firmware will disable all access to the peripheral from within the
+ firmware if it finds a DT node using it, and bcm2835-camera will
+ therefore fail to probe.
+
+ To compile this driver as a module, choose M here. The module will be
+ called bcm2835-unicam.
diff --git a/drivers/media/platform/bcm2835/Makefile b/drivers/media/platform/bcm2835/Makefile
new file mode 100644
index 000000000000..a98aba03598a
--- /dev/null
+++ b/drivers/media/platform/bcm2835/Makefile
@@ -0,0 +1,3 @@
+# Makefile for BCM2835 Unicam driver
+
+obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o
diff --git a/drivers/media/platform/bcm2835/bcm2835-unicam.c b/drivers/media/platform/bcm2835/bcm2835-unicam.c
new file mode 100644
index 000000000000..7636496be00a
--- /dev/null
+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c
@@ -0,0 +1,2678 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * BCM283x / BCM271x Unicam Capture Driver
+ *
+ * Copyright (C) 2017-2020 - Raspberry Pi (Trading) Ltd.
+ *
+ * Dave Stevenson <dave.stevenson@raspberrypi.com>
+ *
+ * Based on TI am437x driver by
+ * Benoit Parrot <bparrot@ti.com>
+ * Lad, Prabhakar <prabhakar.csengg@gmail.com>
+ *
+ * and TI CAL camera interface driver by
+ * Benoit Parrot <bparrot@ti.com>
+ *
+ *
+ * There are two camera drivers in the kernel for BCM283x - this one
+ * and bcm2835-camera (currently in staging).
+ *
+ * This driver directly controls the Unicam peripheral - there is no
+ * involvement with the VideoCore firmware. Unicam receives CSI-2 or
+ * CCP2 data and writes it into SDRAM.
+ * The only potential processing options are to repack Bayer data into an
+ * alternate format, and applying windowing.
+ * The repacking does not shift the data, so can repack V4L2_PIX_FMT_Sxxxx10P
+ * to V4L2_PIX_FMT_Sxxxx10, or V4L2_PIX_FMT_Sxxxx12P to V4L2_PIX_FMT_Sxxxx12,
+ * but not generically up to V4L2_PIX_FMT_Sxxxx16. The driver will add both
+ * formats where the relevant formats are defined, and will automatically
+ * configure the repacking as required.
+ * Support for windowing may be added later.
+ *
+ * It should be possible to connect this driver to any sensor with a
+ * suitable output interface and V4L2 subdevice driver.
+ *
+ * bcm2835-camera uses the VideoCore firmware to control the sensor,
+ * Unicam, ISP, and all tuner control loops. Fully processed frames are
+ * delivered to the driver by the firmware. It only has sensor drivers
+ * for Omnivision OV5647, and Sony IMX219 sensors.
+ *
+ * The two drivers are mutually exclusive for the same Unicam instance.
+ * The VideoCore firmware checks the device tree configuration during boot.
+ * If it finds device tree nodes called csi0 or csi1 it will block the
+ * firmware from accessing the peripheral, and bcm2835-camera will
+ * not be able to stream data.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/videodev2.h>
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-dv-timings.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-fwnode.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include <media/v4l2-async.h>
+#define v4l2_async_nf_add_subdev __v4l2_async_nf_add_subdev
+
+#include "vc4-regs-unicam.h"
+
+#define UNICAM_MODULE_NAME "unicam"
+#define UNICAM_VERSION "0.1.0"
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Debug level 0-3");
+
+/*
+ * Unicam must request a minimum of 250Mhz from the VPU clock.
+ * Otherwise the input FIFOs overrun and cause image corruption.
+ */
+#define MIN_VPU_CLOCK_RATE (250 * 1000 * 1000)
+/*
+ * To protect against a dodgy sensor driver never returning an error from
+ * enum_mbus_code, set a maximum index value to be used.
+ */
+#define MAX_ENUM_MBUS_CODE 128
+
+/*
+ * Stride is a 16 bit register, but also has to be a multiple of 32.
+ */
+#define BPL_ALIGNMENT 32
+#define MAX_BYTESPERLINE ((1 << 16) - BPL_ALIGNMENT)
+/*
+ * Max width is therefore determined by the max stride divided by
+ * the number of bits per pixel. Take 32bpp as a
+ * worst case.
+ * No imposed limit on the height, so adopt a square image for want
+ * of anything better.
+ */
+#define MAX_WIDTH (MAX_BYTESPERLINE / 4)
+#define MAX_HEIGHT MAX_WIDTH
+/* Define a nominal minimum image size */
+#define MIN_WIDTH 16
+#define MIN_HEIGHT 16
+/* Default size of the embedded buffer */
+#define UNICAM_EMBEDDED_SIZE 16384
+
+/*
+ * Size of the dummy buffer. Can be any size really, but the DMA
+ * allocation works in units of page sizes.
+ */
+#define DUMMY_BUF_SIZE (PAGE_SIZE)
+
+#define UNICAM_SD_PAD_SINK 0
+#define UNICAM_SD_PAD_FIRST_SOURCE 1
+#define UNICAM_SD_NUM_SOURCE_PADS 2
+#define UNICAM_SD_NUM_PADS (1 + UNICAM_SD_NUM_SOURCE_PADS)
+
+static inline bool unicam_sd_pad_is_sink(u32 pad)
+{
+ /* Camera RX has 1 sink pad, and N source pads */
+ return pad == 0;
+}
+
+static inline bool unicam_sd_pad_is_source(u32 pad)
+{
+ /* Camera RX has 1 sink pad, and N source pads */
+ return pad >= UNICAM_SD_PAD_FIRST_SOURCE &&
+ pad <= UNICAM_SD_NUM_SOURCE_PADS;
+}
+
+enum node_types {
+ IMAGE_NODE,
+ METADATA_NODE,
+ MAX_NODES
+};
+
+#define MASK_CS_DEFAULT BIT(V4L2_COLORSPACE_DEFAULT)
+#define MASK_CS_SMPTE170M BIT(V4L2_COLORSPACE_SMPTE170M)
+#define MASK_CS_SMPTE240M BIT(V4L2_COLORSPACE_SMPTE240M)
+#define MASK_CS_REC709 BIT(V4L2_COLORSPACE_REC709)
+#define MASK_CS_BT878 BIT(V4L2_COLORSPACE_BT878)
+#define MASK_CS_470_M BIT(V4L2_COLORSPACE_470_SYSTEM_M)
+#define MASK_CS_470_BG BIT(V4L2_COLORSPACE_470_SYSTEM_BG)
+#define MASK_CS_JPEG BIT(V4L2_COLORSPACE_JPEG)
+#define MASK_CS_SRGB BIT(V4L2_COLORSPACE_SRGB)
+#define MASK_CS_OPRGB BIT(V4L2_COLORSPACE_OPRGB)
+#define MASK_CS_BT2020 BIT(V4L2_COLORSPACE_BT2020)
+#define MASK_CS_RAW BIT(V4L2_COLORSPACE_RAW)
+#define MASK_CS_DCI_P3 BIT(V4L2_COLORSPACE_DCI_P3)
+
+#define MAX_COLORSPACE 32
+
+/*
+ * struct unicam_fmt - Unicam media bus format information
+ * @pixelformat: V4L2 pixel format FCC identifier. 0 if n/a.
+ * @repacked_fourcc: V4L2 pixel format FCC identifier if the data is expanded
+ * out to 16bpp. 0 if n/a.
+ * @code: V4L2 media bus format code.
+ * @depth: Bits per pixel as delivered from the source.
+ * @csi_dt: CSI data type.
+ * @valid_colorspaces: Bitmask of valid colorspaces so that the Media Controller
+ * centric try_fmt can validate the colorspace and pass
+ * v4l2-compliance.
+ * @check_variants: Flag to denote that there are multiple mediabus formats
+ * still in the list that could match this V4L2 format.
+ * @mc_skip: Media Controller shouldn't list this format via ENUM_FMT as it is
+ * a duplicate of an earlier format.
+ * @metadata_fmt: This format only applies to the metadata pad.
+ */
+struct unicam_fmt {
+ u32 fourcc;
+ u32 repacked_fourcc;
+ u32 code;
+ u8 depth;
+ u8 csi_dt;
+ u32 valid_colorspaces;
+ u8 check_variants:1;
+ u8 mc_skip:1;
+ u8 metadata_fmt:1;
+};
+
+static const struct unicam_fmt formats[] = {
+ /* YUV Formats */
+ {
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .code = MEDIA_BUS_FMT_YUYV8_2X8,
+ .depth = 16,
+ .csi_dt = 0x1e,
+ .check_variants = 1,
+ .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
+ MASK_CS_JPEG,
+ }, {
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .depth = 16,
+ .csi_dt = 0x1e,
+ .check_variants = 1,
+ .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
+ MASK_CS_JPEG,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YVYU,
+ .code = MEDIA_BUS_FMT_YVYU8_2X8,
+ .depth = 16,
+ .csi_dt = 0x1e,
+ .check_variants = 1,
+ .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
+ MASK_CS_JPEG,
+ }, {
+ .fourcc = V4L2_PIX_FMT_VYUY,
+ .code = MEDIA_BUS_FMT_VYUY8_2X8,
+ .depth = 16,
+ .csi_dt = 0x1e,
+ .check_variants = 1,
+ .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
+ MASK_CS_JPEG,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .code = MEDIA_BUS_FMT_YUYV8_1X16,
+ .depth = 16,
+ .csi_dt = 0x1e,
+ .mc_skip = 1,
+ .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
+ MASK_CS_JPEG,
+ }, {
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .code = MEDIA_BUS_FMT_UYVY8_1X16,
+ .depth = 16,
+ .csi_dt = 0x1e,
+ .mc_skip = 1,
+ .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
+ MASK_CS_JPEG,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YVYU,
+ .code = MEDIA_BUS_FMT_YVYU8_1X16,
+ .depth = 16,
+ .csi_dt = 0x1e,
+ .mc_skip = 1,
+ .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
+ MASK_CS_JPEG,
+ }, {
+ .fourcc = V4L2_PIX_FMT_VYUY,
+ .code = MEDIA_BUS_FMT_VYUY8_1X16,
+ .depth = 16,
+ .csi_dt = 0x1e,
+ .mc_skip = 1,
+ .valid_colorspaces = MASK_CS_SMPTE170M | MASK_CS_REC709 |
+ MASK_CS_JPEG,
+ }, {
+ /* RGB Formats */
+ .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */
+ .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
+ .depth = 16,
+ .csi_dt = 0x22,
+ .valid_colorspaces = MASK_CS_SRGB,
+ }, {
+ .fourcc = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */
+ .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
+ .depth = 16,
+ .csi_dt = 0x22,
+ .valid_colorspaces = MASK_CS_SRGB,
+ }, {
+ .fourcc = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */
+ .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
+ .depth = 16,
+ .csi_dt = 0x21,
+ .valid_colorspaces = MASK_CS_SRGB,
+ }, {
+ .fourcc = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */
+ .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
+ .depth = 16,
+ .csi_dt = 0x21,
+ .valid_colorspaces = MASK_CS_SRGB,
+ }, {
+ .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */
+ .code = MEDIA_BUS_FMT_RGB888_1X24,
+ .depth = 24,
+ .csi_dt = 0x24,
+ .valid_colorspaces = MASK_CS_SRGB,
+ }, {
+ .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */
+ .code = MEDIA_BUS_FMT_BGR888_1X24,
+ .depth = 24,
+ .csi_dt = 0x24,
+ .valid_colorspaces = MASK_CS_SRGB,
+ }, {
+ .fourcc = V4L2_PIX_FMT_RGB32, /* argb */
+ .code = MEDIA_BUS_FMT_ARGB8888_1X32,
+ .depth = 32,
+ .csi_dt = 0x0,
+ .valid_colorspaces = MASK_CS_SRGB,
+ }, {
+ /* Bayer Formats */
+ .fourcc = V4L2_PIX_FMT_SBGGR8,
+ .code = MEDIA_BUS_FMT_SBGGR8_1X8,
+ .depth = 8,
+ .csi_dt = 0x2a,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGBRG8,
+ .code = MEDIA_BUS_FMT_SGBRG8_1X8,
+ .depth = 8,
+ .csi_dt = 0x2a,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGRBG8,
+ .code = MEDIA_BUS_FMT_SGRBG8_1X8,
+ .depth = 8,
+ .csi_dt = 0x2a,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SRGGB8,
+ .code = MEDIA_BUS_FMT_SRGGB8_1X8,
+ .depth = 8,
+ .csi_dt = 0x2a,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SBGGR10P,
+ .repacked_fourcc = V4L2_PIX_FMT_SBGGR10,
+ .code = MEDIA_BUS_FMT_SBGGR10_1X10,
+ .depth = 10,
+ .csi_dt = 0x2b,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGBRG10P,
+ .repacked_fourcc = V4L2_PIX_FMT_SGBRG10,
+ .code = MEDIA_BUS_FMT_SGBRG10_1X10,
+ .depth = 10,
+ .csi_dt = 0x2b,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGRBG10P,
+ .repacked_fourcc = V4L2_PIX_FMT_SGRBG10,
+ .code = MEDIA_BUS_FMT_SGRBG10_1X10,
+ .depth = 10,
+ .csi_dt = 0x2b,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SRGGB10P,
+ .repacked_fourcc = V4L2_PIX_FMT_SRGGB10,
+ .code = MEDIA_BUS_FMT_SRGGB10_1X10,
+ .depth = 10,
+ .csi_dt = 0x2b,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SBGGR12P,
+ .repacked_fourcc = V4L2_PIX_FMT_SBGGR12,
+ .code = MEDIA_BUS_FMT_SBGGR12_1X12,
+ .depth = 12,
+ .csi_dt = 0x2c,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGBRG12P,
+ .repacked_fourcc = V4L2_PIX_FMT_SGBRG12,
+ .code = MEDIA_BUS_FMT_SGBRG12_1X12,
+ .depth = 12,
+ .csi_dt = 0x2c,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGRBG12P,
+ .repacked_fourcc = V4L2_PIX_FMT_SGRBG12,
+ .code = MEDIA_BUS_FMT_SGRBG12_1X12,
+ .depth = 12,
+ .csi_dt = 0x2c,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SRGGB12P,
+ .repacked_fourcc = V4L2_PIX_FMT_SRGGB12,
+ .code = MEDIA_BUS_FMT_SRGGB12_1X12,
+ .depth = 12,
+ .csi_dt = 0x2c,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SBGGR14P,
+ .repacked_fourcc = V4L2_PIX_FMT_SBGGR14,
+ .code = MEDIA_BUS_FMT_SBGGR14_1X14,
+ .depth = 14,
+ .csi_dt = 0x2d,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGBRG14P,
+ .repacked_fourcc = V4L2_PIX_FMT_SGBRG14,
+ .code = MEDIA_BUS_FMT_SGBRG14_1X14,
+ .depth = 14,
+ .csi_dt = 0x2d,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGRBG14P,
+ .repacked_fourcc = V4L2_PIX_FMT_SGRBG14,
+ .code = MEDIA_BUS_FMT_SGRBG14_1X14,
+ .depth = 14,
+ .csi_dt = 0x2d,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SRGGB14P,
+ .repacked_fourcc = V4L2_PIX_FMT_SRGGB14,
+ .code = MEDIA_BUS_FMT_SRGGB14_1X14,
+ .depth = 14,
+ .csi_dt = 0x2d,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ /*
+ * 16 bit Bayer formats could be supported, but there is no CSI2
+ * data_type defined for raw 16, and no sensors that produce it at
+ * present.
+ */
+
+ /* Greyscale formats */
+ .fourcc = V4L2_PIX_FMT_GREY,
+ .code = MEDIA_BUS_FMT_Y8_1X8,
+ .depth = 8,
+ .csi_dt = 0x2a,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_Y10P,
+ .repacked_fourcc = V4L2_PIX_FMT_Y10,
+ .code = MEDIA_BUS_FMT_Y10_1X10,
+ .depth = 10,
+ .csi_dt = 0x2b,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_Y12P,
+ .repacked_fourcc = V4L2_PIX_FMT_Y12,
+ .code = MEDIA_BUS_FMT_Y12_1X12,
+ .depth = 12,
+ .csi_dt = 0x2c,
+ .valid_colorspaces = MASK_CS_RAW,
+ }, {
+ .fourcc = V4L2_PIX_FMT_Y14P,
+ .repacked_fourcc = V4L2_PIX_FMT_Y14,
+ .code = MEDIA_BUS_FMT_Y14_1X14,
+ .depth = 14,
+ .csi_dt = 0x2d,
+ .valid_colorspaces = MASK_CS_RAW,
+ },
+ /* Embedded data format */
+ {
+ .fourcc = V4L2_META_FMT_8,
+ .code = MEDIA_BUS_FMT_METADATA_8,
+ .depth = 8,
+ .metadata_fmt = 1,
+ }
+};
+
+struct unicam_buffer {
+ struct vb2_v4l2_buffer vb;
+ struct list_head list;
+};
+
+static inline struct unicam_buffer *to_unicam_buffer(struct vb2_buffer *vb)
+{
+ return container_of(vb, struct unicam_buffer, vb.vb2_buf);
+}
+
+struct unicam_node {
+ bool registered;
+ int open;
+ bool streaming;
+ unsigned int node_id;
+ /* Source pad id on the sensor for this node */
+ unsigned int src_pad_id;
+ /* Pointer pointing to current v4l2_buffer */
+ struct unicam_buffer *cur_frm;
+ /* Pointer pointing to next v4l2_buffer */
+ struct unicam_buffer *next_frm;
+ /* video capture */
+ const struct unicam_fmt *fmt;
+ /* Used to store current pixel format */
+ struct v4l2_format v_fmt;
+ /* Used to store current mbus frame format */
+ struct v4l2_mbus_framefmt m_fmt;
+ /* Buffer queue used in video-buf */
+ struct vb2_queue buffer_queue;
+ /* Queue of filled frames */
+ struct list_head dma_queue;
+ /* IRQ lock for DMA queue */
+ spinlock_t dma_queue_lock;
+ /* lock used to access this structure */
+ struct mutex lock;
+ /* Identifies video device for this channel */
+ struct video_device video_dev;
+ /* Pointer to the parent handle */
+ struct unicam_device *dev;
+ struct media_pad pad;
+ unsigned int embedded_lines;
+ struct media_pipeline pipe;
+ /*
+ * Dummy buffer intended to be used by unicam
+ * if we have no other queued buffers to swap to.
+ */
+ void *dummy_buf_cpu_addr;
+ dma_addr_t dummy_buf_dma_addr;
+};
+
+struct unicam_device {
+ struct kref kref;
+
+ /* V4l2 specific parameters */
+ struct v4l2_async_subdev asd;
+
+ /* peripheral base address */
+ void __iomem *base;
+ /* clock gating base address */
+ void __iomem *clk_gate_base;
+ /* lp clock handle */
+ struct clk *clock;
+ /* vpu clock handle */
+ struct clk *vpu_clock;
+ /* vpu clock request */
+ struct clk_request *vpu_req;
+ /* clock status for error handling */
+ bool clocks_enabled;
+ /* V4l2 device */
+ struct v4l2_device v4l2_dev;
+ struct media_device mdev;
+
+ /* parent device */
+ struct platform_device *pdev;
+ /* subdevice async Notifier */
+ struct v4l2_async_notifier notifier;
+ unsigned int sequence;
+
+ /* ptr to sub device */
+ struct v4l2_subdev *sensor;
+ /* Pad config for the sensor */
+ struct v4l2_subdev_state *sensor_state;
+
+ /* Internal subdev */
+ struct v4l2_subdev sd;
+ struct media_pad pads[UNICAM_SD_NUM_PADS];
+
+ bool streaming;
+
+ enum v4l2_mbus_type bus_type;
+ /*
+ * Stores bus.mipi_csi2.flags for CSI2 sensors, or
+ * bus.mipi_csi1.strobe for CCP2.
+ */
+ unsigned int bus_flags;
+ unsigned int max_data_lanes;
+ unsigned int active_data_lanes;
+ bool sensor_embedded_data;
+
+ struct unicam_node node[MAX_NODES];
+ struct v4l2_ctrl_handler ctrl_handler;
+
+ bool mc_api;
+};
+
+static inline struct unicam_device *
+to_unicam_device(struct v4l2_device *v4l2_dev)
+{
+ return container_of(v4l2_dev, struct unicam_device, v4l2_dev);
+}
+
+static inline struct unicam_device *
+sd_to_unicam_device(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct unicam_device, sd);
+}
+
+static inline bool is_metadata_node(struct unicam_node *node)
+{
+ return node->video_dev.device_caps & V4L2_CAP_META_CAPTURE;
+}
+
+static inline bool is_image_node(struct unicam_node *node)
+{
+ return node->video_dev.device_caps & V4L2_CAP_VIDEO_CAPTURE;
+}
+
+/* Hardware access */
+static inline void clk_write(struct unicam_device *dev, u32 val)
+{
+ writel(val | 0x5a000000, dev->clk_gate_base);
+}
+
+static inline u32 reg_read(struct unicam_device *dev, u32 offset)
+{
+ return readl(dev->base + offset);
+}
+
+static inline void reg_write(struct unicam_device *dev, u32 offset, u32 val)
+{
+ writel(val, dev->base + offset);
+}
+
+static inline int get_field(u32 value, u32 mask)
+{
+ return (value & mask) >> __ffs(mask);
+}
+
+static inline void set_field(u32 *valp, u32 field, u32 mask)
+{
+ u32 val = *valp;
+
+ val &= ~mask;
+ val |= (field << __ffs(mask)) & mask;
+ *valp = val;
+}
+
+static inline u32 reg_read_field(struct unicam_device *dev, u32 offset,
+ u32 mask)
+{
+ return get_field(reg_read(dev, offset), mask);
+}
+
+static inline void reg_write_field(struct unicam_device *dev, u32 offset,
+ u32 field, u32 mask)
+{
+ u32 val = reg_read(dev, offset);
+
+ set_field(&val, field, mask);
+ reg_write(dev, offset, val);
+}
+
+/* Power management functions */
+static inline int unicam_runtime_get(struct unicam_device *dev)
+{
+ return pm_runtime_get_sync(&dev->pdev->dev);
+}
+
+static inline void unicam_runtime_put(struct unicam_device *dev)
+{
+ pm_runtime_put_sync(&dev->pdev->dev);
+}
+
+/* Format setup functions */
+static const struct unicam_fmt *find_format_by_code(u32 code)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(formats); i++) {
+ if (formats[i].code == code)
+ return &formats[i];
+ }
+
+ return NULL;
+}
+
+static const struct unicam_fmt *find_format_by_fourcc(u32 fourcc)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(formats); ++i) {
+ if (formats[i].fourcc == fourcc)
+ return &formats[i];
+ }
+
+ return NULL;
+}
+
+static unsigned int bytes_per_line(u32 width, const struct unicam_fmt *fmt,
+ u32 v4l2_fourcc)
+{
+ if (v4l2_fourcc == fmt->repacked_fourcc)
+ /* Repacking always goes to 16bpp */
+ return ALIGN(width << 1, BPL_ALIGNMENT);
+ else
+ return ALIGN((width * fmt->depth) >> 3, BPL_ALIGNMENT);
+}
+
+static int unicam_calc_format_size_bpl(struct unicam_device *dev,
+ const struct unicam_fmt *fmt,
+ struct v4l2_format *f)
+{
+ unsigned int min_bytesperline;
+
+ v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 2,
+ &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 0,
+ 0);
+
+ min_bytesperline = bytes_per_line(f->fmt.pix.width, fmt,
+ f->fmt.pix.pixelformat);
+
+ if (f->fmt.pix.bytesperline > min_bytesperline &&
+ f->fmt.pix.bytesperline <= MAX_BYTESPERLINE)
+ f->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,
+ BPL_ALIGNMENT);
+ else
+ f->fmt.pix.bytesperline = min_bytesperline;
+
+ f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
+
+ dev_dbg(dev->v4l2_dev.dev, "%s: fourcc: %08X size: %dx%d bpl:%d img_size:%d\n",
+ __func__,
+ f->fmt.pix.pixelformat,
+ f->fmt.pix.width, f->fmt.pix.height,
+ f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
+
+ return 0;
+}
+
+static void unicam_wr_dma_addr(struct unicam_device *dev, dma_addr_t dmaaddr,
+ unsigned int buffer_size, int node_id)
+{
+ dma_addr_t endaddr = dmaaddr + buffer_size;
+
+ if (node_id == IMAGE_NODE) {
+ reg_write(dev, UNICAM_IBSA0, dmaaddr);
+ reg_write(dev, UNICAM_IBEA0, endaddr);
+ } else {
+ reg_write(dev, UNICAM_DBSA0, dmaaddr);
+ reg_write(dev, UNICAM_DBEA0, endaddr);
+ }
+}
+
+static unsigned int unicam_get_lines_done(struct unicam_device *dev)
+{
+ dma_addr_t start_addr, cur_addr;
+ unsigned int stride = dev->node[IMAGE_NODE].v_fmt.fmt.pix.bytesperline;
+ struct unicam_buffer *frm = dev->node[IMAGE_NODE].cur_frm;
+
+ if (!frm)
+ return 0;
+
+ start_addr = vb2_dma_contig_plane_dma_addr(&frm->vb.vb2_buf, 0);
+ cur_addr = reg_read(dev, UNICAM_IBWP);
+ return (unsigned int)(cur_addr - start_addr) / stride;
+}
+
+static void unicam_schedule_next_buffer(struct unicam_node *node)
+{
+ struct unicam_device *dev = node->dev;
+ struct unicam_buffer *buf;
+ unsigned int size;
+ dma_addr_t addr;
+
+ buf = list_first_entry(&node->dma_queue, struct unicam_buffer, list);
+ node->next_frm = buf;
+ list_del(&buf->list);
+
+ addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
+ if (is_image_node(node)) {
+ size = node->v_fmt.fmt.pix.sizeimage;
+ unicam_wr_dma_addr(dev, addr, size, IMAGE_NODE);
+ } else {
+ size = node->v_fmt.fmt.meta.buffersize;
+ unicam_wr_dma_addr(dev, addr, size, METADATA_NODE);
+ }
+}
+
+static void unicam_schedule_dummy_buffer(struct unicam_node *node)
+{
+ struct unicam_device *dev = node->dev;
+ int node_id = is_image_node(node) ? IMAGE_NODE : METADATA_NODE;
+
+ dev_dbg(dev->v4l2_dev.dev, "Scheduling dummy buffer for node %d\n", node_id);
+
+ unicam_wr_dma_addr(dev, node->dummy_buf_dma_addr, DUMMY_BUF_SIZE,
+ node_id);
+ node->next_frm = NULL;
+}
+
+static void unicam_process_buffer_complete(struct unicam_node *node,
+ unsigned int sequence)
+{
+ node->cur_frm->vb.field = node->m_fmt.field;
+ node->cur_frm->vb.sequence = sequence;
+
+ vb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
+}
+
+static void unicam_queue_event_sof(struct unicam_device *unicam)
+{
+ struct v4l2_event event = {
+ .type = V4L2_EVENT_FRAME_SYNC,
+ .u.frame_sync.frame_sequence = unicam->sequence,
+ };
+
+ v4l2_event_queue(&unicam->node[IMAGE_NODE].video_dev, &event);
+}
+
+/*
+ * unicam_isr : ISR handler for unicam capture
+ * @irq: irq number
+ * @dev_id: dev_id ptr
+ *
+ * It changes status of the captured buffer, takes next buffer from the queue
+ * and sets its address in unicam registers
+ */
+static irqreturn_t unicam_isr(int irq, void *dev)
+{
+ struct unicam_device *unicam = dev;
+ unsigned int lines_done = unicam_get_lines_done(dev);
+ unsigned int sequence = unicam->sequence;
+ unsigned int i;
+ u32 ista, sta;
+ bool fe;
+ u64 ts;
+
+ sta = reg_read(unicam, UNICAM_STA);
+ /* Write value back to clear the interrupts */
+ reg_write(unicam, UNICAM_STA, sta);
+
+ ista = reg_read(unicam, UNICAM_ISTA);
+ /* Write value back to clear the interrupts */
+ reg_write(unicam, UNICAM_ISTA, ista);
+
+ dev_dbg(unicam->v4l2_dev.dev, "ISR: ISTA: 0x%X, STA: 0x%X, sequence %d, lines done %d",
+ ista, sta, sequence, lines_done);
+
+ if (!(sta & (UNICAM_IS | UNICAM_PI0)))
+ return IRQ_HANDLED;
+
+ /*
+ * Look for either the Frame End interrupt or the Packet Capture status
+ * to signal a frame end.
+ */
+ fe = (ista & UNICAM_FEI || sta & UNICAM_PI0);
+
+ /*
+ * We must run the frame end handler first. If we have a valid next_frm
+ * and we get a simultaneout FE + FS interrupt, running the FS handler
+ * first would null out the next_frm ptr and we would have lost the
+ * buffer forever.
+ */
+ if (fe) {
+ /*
+ * Ensure we have swapped buffers already as we can't
+ * stop the peripheral. If no buffer is available, use a
+ * dummy buffer to dump out frames until we get a new buffer
+ * to use.
+ */
+ for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
+ if (!unicam->node[i].streaming)
+ continue;
+
+ /*
+ * If cur_frm == next_frm, it means we have not had
+ * a chance to swap buffers, likely due to having
+ * multiple interrupts occurring simultaneously (like FE
+ * + FS + LS). In this case, we cannot signal the buffer
+ * as complete, as the HW will reuse that buffer.
+ */
+ if (unicam->node[i].cur_frm &&
+ unicam->node[i].cur_frm != unicam->node[i].next_frm)
+ unicam_process_buffer_complete(&unicam->node[i],
+ sequence);
+ unicam->node[i].cur_frm = unicam->node[i].next_frm;
+ }
+ unicam->sequence++;
+ }
+
+ if (ista & UNICAM_FSI) {
+ /*
+ * Timestamp is to be when the first data byte was captured,
+ * aka frame start.
+ */
+ ts = ktime_get_ns();
+ for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
+ if (!unicam->node[i].streaming)
+ continue;
+
+ if (unicam->node[i].cur_frm)
+ unicam->node[i].cur_frm->vb.vb2_buf.timestamp =
+ ts;
+ else
+ dev_dbg(unicam->v4l2_dev.dev, "ISR: [%d] Dropping frame, buffer not available at FS\n",
+ i);
+ /*
+ * Set the next frame output to go to a dummy frame
+ * if we have not managed to obtain another frame
+ * from the queue.
+ */
+ unicam_schedule_dummy_buffer(&unicam->node[i]);
+ }
+
+ unicam_queue_event_sof(unicam);
+ }
+
+ /*
+ * Cannot swap buffer at frame end, there may be a race condition
+ * where the HW does not actually swap it if the new frame has
+ * already started.
+ */
+ if (ista & (UNICAM_FSI | UNICAM_LCI) && !fe) {
+ for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
+ if (!unicam->node[i].streaming)
+ continue;
+
+ spin_lock(&unicam->node[i].dma_queue_lock);
+ if (!list_empty(&unicam->node[i].dma_queue) &&
+ !unicam->node[i].next_frm)
+ unicam_schedule_next_buffer(&unicam->node[i]);
+ spin_unlock(&unicam->node[i].dma_queue_lock);
+ }
+ }
+
+ if (reg_read(unicam, UNICAM_ICTL) & UNICAM_FCM) {
+ /* Switch out of trigger mode if selected */
+ reg_write_field(unicam, UNICAM_ICTL, 1, UNICAM_TFC);
+ reg_write_field(unicam, UNICAM_ICTL, 0, UNICAM_FCM);
+ }
+ return IRQ_HANDLED;
+}
+
+/* V4L2 Common IOCTLs */
+static int unicam_querycap(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ struct unicam_node *node = video_drvdata(file);
+ struct unicam_device *dev = node->dev;
+
+ strscpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));
+ strscpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));
+
+ snprintf(cap->bus_info, sizeof(cap->bus_info),
+ "platform:%s", dev_name(&dev->pdev->dev));
+
+ cap->capabilities |= V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_META_CAPTURE;
+
+ return 0;
+}
+
+static int unicam_log_status(struct file *file, void *fh)
+{
+ struct unicam_node *node = video_drvdata(file);
+ struct unicam_device *dev = node->dev;
+ u32 reg;
+
+ /* status for sub devices */
+ v4l2_device_call_all(&dev->v4l2_dev, 0, core, log_status);
+
+ dev_info(dev->v4l2_dev.dev, "-----Receiver status-----\n");
+ dev_info(dev->v4l2_dev.dev, "V4L2 width/height: %ux%u\n",
+ node->v_fmt.fmt.pix.width, node->v_fmt.fmt.pix.height);
+ dev_info(dev->v4l2_dev.dev, "Mediabus format: %08x\n", node->fmt->code);
+ dev_info(dev->v4l2_dev.dev, "V4L2 format: %08x\n",
+ node->v_fmt.fmt.pix.pixelformat);
+ reg = reg_read(dev, UNICAM_IPIPE);
+ dev_info(dev->v4l2_dev.dev, "Unpacking/packing: %u / %u\n",
+ get_field(reg, UNICAM_PUM_MASK),
+ get_field(reg, UNICAM_PPM_MASK));
+ dev_info(dev->v4l2_dev.dev, "----Live data----\n");
+ dev_info(dev->v4l2_dev.dev, "Programmed stride: %4u\n",
+ reg_read(dev, UNICAM_IBLS));
+ dev_info(dev->v4l2_dev.dev, "Detected resolution: %ux%u\n",
+ reg_read(dev, UNICAM_IHSTA),
+ reg_read(dev, UNICAM_IVSTA));
+ dev_info(dev->v4l2_dev.dev, "Write pointer: %08x\n",
+ reg_read(dev, UNICAM_IBWP));
+
+ return 0;
+}
+
+static int unicam_subscribe_event(struct v4l2_fh *fh,
+ const struct v4l2_event_subscription *sub)
+{
+ switch (sub->type) {
+ case V4L2_EVENT_FRAME_SYNC:
+ return v4l2_event_subscribe(fh, sub, 2, NULL);
+ case V4L2_EVENT_SOURCE_CHANGE:
+ return v4l2_event_subscribe(fh, sub, 4, NULL);
+ }
+
+ return v4l2_ctrl_subscribe_event(fh, sub);
+}
+
+static void unicam_notify(struct v4l2_subdev *sd,
+ unsigned int notification, void *arg)
+{
+ struct unicam_device *dev = to_unicam_device(sd->v4l2_dev);
+
+ switch (notification) {
+ case V4L2_DEVICE_NOTIFY_EVENT:
+ v4l2_event_queue(&dev->node[IMAGE_NODE].video_dev, arg);
+ break;
+ default:
+ break;
+ }
+}
+
+/* V4L2 Media Controller Centric IOCTLs */
+
+static int unicam_mc_enum_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ int i, j;
+
+ for (i = 0, j = 0; i < ARRAY_SIZE(formats); i++) {
+ if (f->mbus_code && formats[i].code != f->mbus_code)
+ continue;
+ if (formats[i].mc_skip || formats[i].metadata_fmt)
+ continue;
+
+ if (formats[i].fourcc) {
+ if (j == f->index) {
+ f->pixelformat = formats[i].fourcc;
+ f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ return 0;
+ }
+ j++;
+ }
+ if (formats[i].repacked_fourcc) {
+ if (j == f->index) {
+ f->pixelformat = formats[i].repacked_fourcc;
+ f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ return 0;
+ }
+ j++;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int unicam_mc_g_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct unicam_node *node = video_drvdata(file);
+
+ if (!is_image_node(node))
+ return -EINVAL;
+
+ *f = node->v_fmt;
+
+ return 0;
+}
+
+static void unicam_mc_try_fmt(struct unicam_node *node, struct v4l2_format *f,
+ const struct unicam_fmt **ret_fmt)
+{
+ struct v4l2_pix_format *v4l2_format = &f->fmt.pix;
+ struct unicam_device *dev = node->dev;
+ const struct unicam_fmt *fmt;
+ int is_rgb;
+
+ /*
+ * Default to the first format if the requested pixel format code isn't
+ * supported.
+ */
+ fmt = find_format_by_fourcc(v4l2_format->pixelformat);
+ if (!fmt) {
+ fmt = &formats[0];
+ v4l2_format->pixelformat = fmt->fourcc;
+ }
+
+ unicam_calc_format_size_bpl(dev, fmt, f);
+
+ if (v4l2_format->field == V4L2_FIELD_ANY)
+ v4l2_format->field = V4L2_FIELD_NONE;
+
+ if (v4l2_format->colorspace >= MAX_COLORSPACE ||
+ !(fmt->valid_colorspaces & (1 << v4l2_format->colorspace))) {
+ v4l2_format->colorspace = __ffs(fmt->valid_colorspaces);
+
+ v4l2_format->xfer_func =
+ V4L2_MAP_XFER_FUNC_DEFAULT(v4l2_format->colorspace);
+ v4l2_format->ycbcr_enc =
+ V4L2_MAP_YCBCR_ENC_DEFAULT(v4l2_format->colorspace);
+ is_rgb = v4l2_format->colorspace == V4L2_COLORSPACE_SRGB;
+ v4l2_format->quantization =
+ V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb,
+ v4l2_format->colorspace,
+ v4l2_format->ycbcr_enc);
+ }
+
+ if (ret_fmt)
+ *ret_fmt = fmt;
+
+ dev_dbg(dev->v4l2_dev.dev, "%s: %08x %ux%u (bytesperline %u sizeimage %u)\n",
+ __func__, v4l2_format->pixelformat,
+ v4l2_format->width, v4l2_format->height,
+ v4l2_format->bytesperline, v4l2_format->sizeimage);
+}
+
+static int unicam_mc_try_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct unicam_node *node = video_drvdata(file);
+
+ unicam_mc_try_fmt(node, f, NULL);
+ return 0;
+}
+
+static int unicam_mc_s_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct unicam_node *node = video_drvdata(file);
+ struct unicam_device *dev = node->dev;
+ const struct unicam_fmt *fmt;
+
+ if (vb2_is_busy(&node->buffer_queue)) {
+ dev_dbg(dev->v4l2_dev.dev, "%s device busy\n", __func__);
+ return -EBUSY;
+ }
+
+ unicam_mc_try_fmt(node, f, &fmt);
+
+ node->v_fmt = *f;
+ node->fmt = fmt;
+
+ return 0;
+}
+
+static int unicam_mc_enum_framesizes(struct file *file, void *fh,
+ struct v4l2_frmsizeenum *fsize)
+{
+ struct unicam_node *node = video_drvdata(file);
+ struct unicam_device *dev = node->dev;
+
+ if (fsize->index > 0)
+ return -EINVAL;
+
+ if (!find_format_by_fourcc(fsize->pixel_format)) {
+ dev_dbg(dev->v4l2_dev.dev, "Invalid pixel format 0x%08x\n",
+ fsize->pixel_format);
+ return -EINVAL;
+ }
+
+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
+ fsize->stepwise.min_width = MIN_WIDTH;
+ fsize->stepwise.max_width = MAX_WIDTH;
+ fsize->stepwise.step_width = 1;
+ fsize->stepwise.min_height = MIN_HEIGHT;
+ fsize->stepwise.max_height = MAX_HEIGHT;
+ fsize->stepwise.step_height = 1;
+
+ return 0;
+}
+
+static int unicam_mc_enum_fmt_meta_cap(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ struct unicam_node *node = video_drvdata(file);
+ int i, j;
+
+ if (!is_metadata_node(node))
+ return -EINVAL;
+
+ for (i = 0, j = 0; i < ARRAY_SIZE(formats); i++) {
+ if (f->mbus_code && formats[i].code != f->mbus_code)
+ continue;
+ if (!formats[i].metadata_fmt)
+ continue;
+
+ if (formats[i].fourcc) {
+ if (j == f->index) {
+ f->pixelformat = formats[i].fourcc;
+ f->type = V4L2_BUF_TYPE_META_CAPTURE;
+ return 0;
+ }
+ j++;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int unicam_mc_g_fmt_meta_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct unicam_node *node = video_drvdata(file);
+
+ if (!is_metadata_node(node))
+ return -EINVAL;
+
+ *f = node->v_fmt;
+
+ return 0;
+}
+
+static int unicam_mc_try_fmt_meta_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct unicam_node *node = video_drvdata(file);
+
+ if (!is_metadata_node(node))
+ return -EINVAL;
+
+ f->fmt.meta.dataformat = V4L2_META_FMT_8;
+
+ return 0;
+}
+
+static int unicam_mc_s_fmt_meta_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct unicam_node *node = video_drvdata(file);
+
+ if (!is_metadata_node(node))
+ return -EINVAL;
+
+ unicam_mc_try_fmt_meta_cap(file, priv, f);
+
+ node->v_fmt = *f;
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops unicam_mc_ioctl_ops = {
+ .vidioc_querycap = unicam_querycap,
+ .vidioc_enum_fmt_vid_cap = unicam_mc_enum_fmt_vid_cap,
+ .vidioc_g_fmt_vid_cap = unicam_mc_g_fmt_vid_cap,
+ .vidioc_try_fmt_vid_cap = unicam_mc_try_fmt_vid_cap,
+ .vidioc_s_fmt_vid_cap = unicam_mc_s_fmt_vid_cap,
+
+ .vidioc_enum_fmt_meta_cap = unicam_mc_enum_fmt_meta_cap,
+ .vidioc_g_fmt_meta_cap = unicam_mc_g_fmt_meta_cap,
+ .vidioc_try_fmt_meta_cap = unicam_mc_try_fmt_meta_cap,
+ .vidioc_s_fmt_meta_cap = unicam_mc_s_fmt_meta_cap,
+
+ .vidioc_enum_framesizes = unicam_mc_enum_framesizes,
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+
+ .vidioc_log_status = unicam_log_status,
+ .vidioc_subscribe_event = unicam_subscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static const struct media_entity_operations unicam_mc_entity_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+ .has_route = v4l2_subdev_has_route,
+};
+
+/* videobuf2 Operations */
+
+static int unicam_queue_setup(struct vb2_queue *vq,
+ unsigned int *nbuffers,
+ unsigned int *nplanes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ struct unicam_node *node = vb2_get_drv_priv(vq);
+ struct unicam_device *dev = node->dev;
+ unsigned int size = is_image_node(node) ?
+ node->v_fmt.fmt.pix.sizeimage :
+ node->v_fmt.fmt.meta.buffersize;
+
+ if (vq->num_buffers + *nbuffers < 3)
+ *nbuffers = 3 - vq->num_buffers;
+
+ if (*nplanes) {
+ if (sizes[0] < size) {
+ dev_err(dev->v4l2_dev.dev, "sizes[0] %i < size %u\n", sizes[0],
+ size);
+ return -EINVAL;
+ }
+ size = sizes[0];
+ }
+
+ *nplanes = 1;
+ sizes[0] = size;
+
+ return 0;
+}
+
+static int unicam_buffer_prepare(struct vb2_buffer *vb)
+{
+ struct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);
+ struct unicam_device *dev = node->dev;
+ struct unicam_buffer *buf = to_unicam_buffer(vb);
+ unsigned long size;
+
+ if (WARN_ON(!node->fmt))
+ return -EINVAL;
+
+ size = is_image_node(node) ? node->v_fmt.fmt.pix.sizeimage :
+ node->v_fmt.fmt.meta.buffersize;
+ if (vb2_plane_size(vb, 0) < size) {
+ dev_err(dev->v4l2_dev.dev, "data will not fit into plane (%lu < %lu)\n",
+ vb2_plane_size(vb, 0), size);
+ return -EINVAL;
+ }
+
+ vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
+ return 0;
+}
+
+static void unicam_buffer_queue(struct vb2_buffer *vb)
+{
+ struct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);
+ struct unicam_buffer *buf = to_unicam_buffer(vb);
+ unsigned long flags;
+
+ spin_lock_irqsave(&node->dma_queue_lock, flags);
+ list_add_tail(&buf->list, &node->dma_queue);
+ spin_unlock_irqrestore(&node->dma_queue_lock, flags);
+}
+
+static void unicam_set_packing_config(struct unicam_device *dev)
+{
+ u32 pack, unpack;
+ u32 val;
+
+ if (dev->node[IMAGE_NODE].v_fmt.fmt.pix.pixelformat ==
+ dev->node[IMAGE_NODE].fmt->fourcc) {
+ unpack = UNICAM_PUM_NONE;
+ pack = UNICAM_PPM_NONE;
+ } else {
+ switch (dev->node[IMAGE_NODE].fmt->depth) {
+ case 8:
+ unpack = UNICAM_PUM_UNPACK8;
+ break;
+ case 10:
+ unpack = UNICAM_PUM_UNPACK10;
+ break;
+ case 12:
+ unpack = UNICAM_PUM_UNPACK12;
+ break;
+ case 14:
+ unpack = UNICAM_PUM_UNPACK14;
+ break;
+ case 16:
+ unpack = UNICAM_PUM_UNPACK16;
+ break;
+ default:
+ unpack = UNICAM_PUM_NONE;
+ break;
+ }
+
+ /* Repacking is always to 16bpp */
+ pack = UNICAM_PPM_PACK16;
+ }
+
+ val = 0;
+ set_field(&val, unpack, UNICAM_PUM_MASK);
+ set_field(&val, pack, UNICAM_PPM_MASK);
+ reg_write(dev, UNICAM_IPIPE, val);
+}
+
+static void unicam_cfg_image_id(struct unicam_device *dev)
+{
+ if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
+ /* CSI2 mode, hardcode VC 0 for now. */
+ reg_write(dev, UNICAM_IDI0,
+ (0 << 6) | dev->node[IMAGE_NODE].fmt->csi_dt);
+ } else {
+ /* CCP2 mode */
+ reg_write(dev, UNICAM_IDI0,
+ 0x80 | dev->node[IMAGE_NODE].fmt->csi_dt);
+ }
+}
+
+static void unicam_enable_ed(struct unicam_device *dev)
+{
+ u32 val = reg_read(dev, UNICAM_DCS);
+
+ set_field(&val, 2, UNICAM_EDL_MASK);
+ /* Do not wrap at the end of the embedded data buffer */
+ set_field(&val, 0, UNICAM_DBOB);
+
+ reg_write(dev, UNICAM_DCS, val);
+}
+
+static void unicam_start_rx(struct unicam_device *dev, dma_addr_t *addr)
+{
+ int line_int_freq = dev->node[IMAGE_NODE].v_fmt.fmt.pix.height >> 2;
+ unsigned int size, i;
+ u32 val;
+
+ if (line_int_freq < 128)
+ line_int_freq = 128;
+
+ /* Enable lane clocks */
+ val = 1;
+ for (i = 0; i < dev->active_data_lanes; i++)
+ val = val << 2 | 1;
+ clk_write(dev, val);
+
+ /* Basic init */
+ reg_write(dev, UNICAM_CTRL, UNICAM_MEM);
+
+ /* Enable analogue control, and leave in reset. */
+ val = UNICAM_AR;
+ set_field(&val, 7, UNICAM_CTATADJ_MASK);
+ set_field(&val, 7, UNICAM_PTATADJ_MASK);
+ reg_write(dev, UNICAM_ANA, val);
+ usleep_range(1000, 2000);
+
+ /* Come out of reset */
+ reg_write_field(dev, UNICAM_ANA, 0, UNICAM_AR);
+
+ /* Peripheral reset */
+ reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPR);
+ reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPR);
+
+ reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPE);
+
+ /* Enable Rx control. */
+ val = reg_read(dev, UNICAM_CTRL);
+ if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
+ set_field(&val, UNICAM_CPM_CSI2, UNICAM_CPM_MASK);
+ set_field(&val, UNICAM_DCM_STROBE, UNICAM_DCM_MASK);
+ } else {
+ set_field(&val, UNICAM_CPM_CCP2, UNICAM_CPM_MASK);
+ set_field(&val, dev->bus_flags, UNICAM_DCM_MASK);
+ }
+ /* Packet framer timeout */
+ set_field(&val, 0xf, UNICAM_PFT_MASK);
+ set_field(&val, 128, UNICAM_OET_MASK);
+ reg_write(dev, UNICAM_CTRL, val);
+
+ reg_write(dev, UNICAM_IHWIN, 0);
+ reg_write(dev, UNICAM_IVWIN, 0);
+
+ /* AXI bus access QoS setup */
+ val = reg_read(dev, UNICAM_PRI);
+ set_field(&val, 0, UNICAM_BL_MASK);
+ set_field(&val, 0, UNICAM_BS_MASK);
+ set_field(&val, 0xe, UNICAM_PP_MASK);
+ set_field(&val, 8, UNICAM_NP_MASK);
+ set_field(&val, 2, UNICAM_PT_MASK);
+ set_field(&val, 1, UNICAM_PE);
+ reg_write(dev, UNICAM_PRI, val);
+
+ reg_write_field(dev, UNICAM_ANA, 0, UNICAM_DDL);
+
+ /* Always start in trigger frame capture mode (UNICAM_FCM set) */
+ val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM | UNICAM_IBOB;
+ set_field(&val, line_int_freq, UNICAM_LCIE_MASK);
+ reg_write(dev, UNICAM_ICTL, val);
+ reg_write(dev, UNICAM_STA, UNICAM_STA_MASK_ALL);
+ reg_write(dev, UNICAM_ISTA, UNICAM_ISTA_MASK_ALL);
+
+ /* tclk_term_en */
+ reg_write_field(dev, UNICAM_CLT, 2, UNICAM_CLT1_MASK);
+ /* tclk_settle */
+ reg_write_field(dev, UNICAM_CLT, 6, UNICAM_CLT2_MASK);
+ /* td_term_en */
+ reg_write_field(dev, UNICAM_DLT, 2, UNICAM_DLT1_MASK);
+ /* ths_settle */
+ reg_write_field(dev, UNICAM_DLT, 6, UNICAM_DLT2_MASK);
+ /* trx_enable */
+ reg_write_field(dev, UNICAM_DLT, 0, UNICAM_DLT3_MASK);
+
+ reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_SOE);
+
+ /* Packet compare setup - required to avoid missing frame ends */
+ val = 0;
+ set_field(&val, 1, UNICAM_PCE);
+ set_field(&val, 1, UNICAM_GI);
+ set_field(&val, 1, UNICAM_CPH);
+ set_field(&val, 0, UNICAM_PCVC_MASK);
+ set_field(&val, 1, UNICAM_PCDT_MASK);
+ reg_write(dev, UNICAM_CMP0, val);
+
+ /* Enable clock lane and set up terminations */
+ val = 0;
+ if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
+ /* CSI2 */
+ set_field(&val, 1, UNICAM_CLE);
+ set_field(&val, 1, UNICAM_CLLPE);
+ if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
+ set_field(&val, 1, UNICAM_CLTRE);
+ set_field(&val, 1, UNICAM_CLHSE);
+ }
+ } else {
+ /* CCP2 */
+ set_field(&val, 1, UNICAM_CLE);
+ set_field(&val, 1, UNICAM_CLHSE);
+ set_field(&val, 1, UNICAM_CLTRE);
+ }
+ reg_write(dev, UNICAM_CLK, val);
+
+ /*
+ * Enable required data lanes with appropriate terminations.
+ * The same value needs to be written to UNICAM_DATn registers for
+ * the active lanes, and 0 for inactive ones.
+ */
+ val = 0;
+ if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
+ /* CSI2 */
+ set_field(&val, 1, UNICAM_DLE);
+ set_field(&val, 1, UNICAM_DLLPE);
+ if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
+ set_field(&val, 1, UNICAM_DLTRE);
+ set_field(&val, 1, UNICAM_DLHSE);
+ }
+ } else {
+ /* CCP2 */
+ set_field(&val, 1, UNICAM_DLE);
+ set_field(&val, 1, UNICAM_DLHSE);
+ set_field(&val, 1, UNICAM_DLTRE);
+ }
+ reg_write(dev, UNICAM_DAT0, val);
+
+ if (dev->active_data_lanes == 1)
+ val = 0;
+ reg_write(dev, UNICAM_DAT1, val);
+
+ if (dev->max_data_lanes > 2) {
+ /*
+ * Registers UNICAM_DAT2 and UNICAM_DAT3 only valid if the
+ * instance supports more than 2 data lanes.
+ */
+ if (dev->active_data_lanes == 2)
+ val = 0;
+ reg_write(dev, UNICAM_DAT2, val);
+
+ if (dev->active_data_lanes == 3)
+ val = 0;
+ reg_write(dev, UNICAM_DAT3, val);
+ }
+
+ reg_write(dev, UNICAM_IBLS,
+ dev->node[IMAGE_NODE].v_fmt.fmt.pix.bytesperline);
+ size = dev->node[IMAGE_NODE].v_fmt.fmt.pix.sizeimage;
+ unicam_wr_dma_addr(dev, addr[IMAGE_NODE], size, IMAGE_NODE);
+ unicam_set_packing_config(dev);
+ unicam_cfg_image_id(dev);
+
+ val = reg_read(dev, UNICAM_MISC);
+ set_field(&val, 1, UNICAM_FL0);
+ set_field(&val, 1, UNICAM_FL1);
+ reg_write(dev, UNICAM_MISC, val);
+
+ if (dev->node[METADATA_NODE].streaming && dev->sensor_embedded_data) {
+ dev_dbg(dev->v4l2_dev.dev, "enable metadata dma\n");
+ size = dev->node[METADATA_NODE].v_fmt.fmt.meta.buffersize;
+ unicam_enable_ed(dev);
+ unicam_wr_dma_addr(dev, addr[METADATA_NODE], size, METADATA_NODE);
+ }
+
+ /* Enable peripheral */
+ reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPE);
+
+ /* Load image pointers */
+ reg_write_field(dev, UNICAM_ICTL, 1, UNICAM_LIP_MASK);
+
+ /* Load embedded data buffer pointers if needed */
+ if (dev->node[METADATA_NODE].streaming && dev->sensor_embedded_data)
+ reg_write_field(dev, UNICAM_DCS, 1, UNICAM_LDP);
+
+ /*
+ * Enable trigger only for the first frame to
+ * sync correctly to the FS from the source.
+ */
+ reg_write_field(dev, UNICAM_ICTL, 1, UNICAM_TFC);
+}
+
+static void unicam_disable(struct unicam_device *dev)
+{
+ /* Analogue lane control disable */
+ reg_write_field(dev, UNICAM_ANA, 1, UNICAM_DDL);
+
+ /* Stop the output engine */
+ reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_SOE);
+
+ /* Disable the data lanes. */
+ reg_write(dev, UNICAM_DAT0, 0);
+ reg_write(dev, UNICAM_DAT1, 0);
+
+ if (dev->max_data_lanes > 2) {
+ reg_write(dev, UNICAM_DAT2, 0);
+ reg_write(dev, UNICAM_DAT3, 0);
+ }
+
+ /* Peripheral reset */
+ reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPR);
+ usleep_range(50, 100);
+ reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPR);
+
+ /* Disable peripheral */
+ reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPE);
+
+ /* Clear ED setup */
+ reg_write(dev, UNICAM_DCS, 0);
+
+ /* Disable all lane clocks */
+ clk_write(dev, 0);
+}
+
+static void unicam_return_buffers(struct unicam_node *node,
+ enum vb2_buffer_state state)
+{
+ struct unicam_buffer *buf, *tmp;
+ unsigned long flags;
+
+ spin_lock_irqsave(&node->dma_queue_lock, flags);
+ list_for_each_entry_safe(buf, tmp, &node->dma_queue, list) {
+ list_del(&buf->list);
+ vb2_buffer_done(&buf->vb.vb2_buf, state);
+ }
+
+ if (node->cur_frm)
+ vb2_buffer_done(&node->cur_frm->vb.vb2_buf,
+ state);
+ if (node->next_frm && node->cur_frm != node->next_frm)
+ vb2_buffer_done(&node->next_frm->vb.vb2_buf,
+ state);
+
+ node->cur_frm = NULL;
+ node->next_frm = NULL;
+ spin_unlock_irqrestore(&node->dma_queue_lock, flags);
+}
+
+static int unicam_video_check_format(struct unicam_node *node)
+{
+ const struct v4l2_mbus_framefmt *format;
+ struct media_pad *remote_pad;
+ struct v4l2_subdev_state *state;
+ int ret = 0;
+
+ remote_pad = media_entity_remote_pad(&node->pad);
+ if (!remote_pad)
+ return -ENODEV;
+
+ state = v4l2_subdev_lock_active_state(node->dev->sensor);
+
+ format = v4l2_state_get_stream_format(state,
+ remote_pad->index, 0);
+ if (!format) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (node->fmt->code != format->code ||
+ node->v_fmt.fmt.pix.height != format->height ||
+ node->v_fmt.fmt.pix.width != format->width ||
+ node->v_fmt.fmt.pix.field != format->field) {
+ ret = -EPIPE;
+ goto out;
+ }
+
+out:
+ v4l2_subdev_unlock_state(state);
+
+ return ret;
+}
+
+static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)
+{
+ struct unicam_node *node = vb2_get_drv_priv(vq);
+ struct unicam_device *dev = node->dev;
+ dma_addr_t buffer_addr[MAX_NODES] = { 0 };
+ struct unicam_buffer *buf;
+ unsigned long flags;
+ unsigned int i;
+ int ret;
+
+ node->streaming = true;
+
+ dev->sequence = 0;
+ ret = unicam_runtime_get(dev);
+ if (ret < 0) {
+ dev_dbg(dev->v4l2_dev.dev, "unicam_runtime_get failed\n");
+ goto err_streaming;
+ }
+
+ ret = media_pipeline_start(node->video_dev.entity.pads, &node->pipe);
+ if (ret < 0) {
+ dev_err(dev->v4l2_dev.dev, "Failed to start media pipeline: %d\n", ret);
+ goto err_pm_put;
+ }
+
+ dev->active_data_lanes = dev->max_data_lanes;
+
+ unicam_video_check_format(node);
+
+ dev_dbg(dev->v4l2_dev.dev, "Running with %u data lanes\n",
+ dev->active_data_lanes);
+
+ ret = clk_set_min_rate(dev->vpu_clock, MIN_VPU_CLOCK_RATE);
+ if (ret) {
+ dev_err(dev->v4l2_dev.dev, "failed to set up VPU clock\n");
+ goto error_pipeline;
+ }
+
+ ret = clk_prepare_enable(dev->vpu_clock);
+ if (ret) {
+ dev_err(dev->v4l2_dev.dev, "Failed to enable VPU clock: %d\n", ret);
+ goto error_pipeline;
+ }
+
+ ret = clk_set_rate(dev->clock, 100 * 1000 * 1000);
+ if (ret) {
+ dev_err(dev->v4l2_dev.dev, "failed to set up CSI clock\n");
+ goto err_vpu_clock;
+ }
+
+ ret = clk_prepare_enable(dev->clock);
+ if (ret) {
+ dev_err(dev->v4l2_dev.dev, "Failed to enable CSI clock: %d\n", ret);
+ goto err_vpu_clock;
+ }
+
+ dev_dbg(dev->v4l2_dev.dev, "node %s\n", node->video_dev.name);
+
+ spin_lock_irqsave(&node->dma_queue_lock, flags);
+ buf = list_first_entry(&node->dma_queue,
+ struct unicam_buffer, list);
+ node->cur_frm = buf;
+ node->next_frm = buf;
+ list_del(&buf->list);
+ spin_unlock_irqrestore(&node->dma_queue_lock, flags);
+
+ buffer_addr[i] =
+ vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
+
+ unicam_start_rx(dev, buffer_addr);
+
+ ret = v4l2_subdev_call(&dev->sd, video, s_stream, 1);
+ if (ret < 0) {
+ dev_err(dev->v4l2_dev.dev, "stream on failed in subdev\n");
+ goto err_disable_unicam;
+ }
+
+ dev->clocks_enabled = true;
+ return 0;
+
+err_disable_unicam:
+ unicam_disable(dev);
+ clk_disable_unprepare(dev->clock);
+err_vpu_clock:
+ if (clk_set_min_rate(dev->vpu_clock, 0))
+ dev_err(dev->v4l2_dev.dev, "failed to reset the VPU clock\n");
+ clk_disable_unprepare(dev->vpu_clock);
+error_pipeline:
+ media_pipeline_stop(node->video_dev.entity.pads);
+err_pm_put:
+ unicam_runtime_put(dev);
+err_streaming:
+ unicam_return_buffers(node, VB2_BUF_STATE_QUEUED);
+ node->streaming = false;
+
+ return ret;
+}
+
+static void unicam_stop_streaming(struct vb2_queue *vq)
+{
+ struct unicam_node *node = vb2_get_drv_priv(vq);
+ struct unicam_device *dev = node->dev;
+
+ node->streaming = false;
+ /*
+ * Stop streaming the sensor and disable the peripheral.
+ * We cannot continue streaming embedded data with the
+ * image pad disabled.
+ */
+ if (v4l2_subdev_call(&dev->sd, video, s_stream, 0) < 0)
+ dev_err(dev->v4l2_dev.dev, "stream off failed in subdev\n");
+
+ unicam_disable(dev);
+
+ media_pipeline_stop(node->video_dev.entity.pads);
+
+ if (dev->clocks_enabled) {
+ if (clk_set_min_rate(dev->vpu_clock, 0))
+ dev_err(dev->v4l2_dev.dev, "failed to reset the VPU clock\n");
+ clk_disable_unprepare(dev->vpu_clock);
+ clk_disable_unprepare(dev->clock);
+ dev->clocks_enabled = false;
+ }
+ unicam_runtime_put(dev);
+
+ if (is_metadata_node(node)) {
+ /*
+ * Allow the hardware to spin in the dummy buffer.
+ * This is only really needed if the embedded data pad is
+ * disabled before the image pad.
+ */
+ unicam_wr_dma_addr(dev, node->dummy_buf_dma_addr,
+ DUMMY_BUF_SIZE, METADATA_NODE);
+ }
+
+ /* Clear all queued buffers for the node */
+ unicam_return_buffers(node, VB2_BUF_STATE_ERROR);
+}
+
+static const struct vb2_ops unicam_video_qops = {
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+ .queue_setup = unicam_queue_setup,
+ .buf_prepare = unicam_buffer_prepare,
+ .buf_queue = unicam_buffer_queue,
+ .start_streaming = unicam_start_streaming,
+ .stop_streaming = unicam_stop_streaming,
+};
+
+/* unicam capture driver file operations */
+static const struct v4l2_file_operations unicam_fops = {
+ .owner = THIS_MODULE,
+ .open = v4l2_fh_open,
+ .release = vb2_fop_release,
+ .poll = vb2_fop_poll,
+ .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
+ .mmap = vb2_fop_mmap,
+};
+
+static int
+unicam_async_bound(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *subdev,
+ struct v4l2_async_subdev *asd)
+{
+ struct unicam_device *unicam = to_unicam_device(notifier->v4l2_dev);
+
+ if (unicam->sensor) {
+ dev_info(unicam->v4l2_dev.dev, "subdev %s (Already set!!)",
+ subdev->name);
+ return 0;
+ }
+
+ unicam->sensor = subdev;
+ dev_dbg(unicam->v4l2_dev.dev, "Using sensor %s for capture\n", subdev->name);
+
+ return 0;
+}
+
+static void unicam_release(struct kref *kref)
+{
+ struct unicam_device *unicam =
+ container_of(kref, struct unicam_device, kref);
+
+ v4l2_ctrl_handler_free(&unicam->ctrl_handler);
+ media_device_cleanup(&unicam->mdev);
+
+ if (unicam->sensor_state)
+ __v4l2_subdev_state_free(unicam->sensor_state);
+
+ kfree(unicam);
+}
+
+static void unicam_put(struct unicam_device *unicam)
+{
+ kref_put(&unicam->kref, unicam_release);
+}
+
+static void unicam_get(struct unicam_device *unicam)
+{
+ kref_get(&unicam->kref);
+}
+
+static void unicam_node_release(struct video_device *vdev)
+{
+ struct unicam_node *node = video_get_drvdata(vdev);
+
+ unicam_put(node->dev);
+}
+
+static void unicam_mc_set_default_format(struct unicam_node *node)
+{
+ dev_dbg(node->dev->v4l2_dev.dev, "Set default format for %s node\n",
+ node->node_id == IMAGE_NODE ? "image" : "metadata");
+
+ if (is_image_node(node)) {
+ struct v4l2_pix_format *pix_fmt = &node->v_fmt.fmt.pix;
+
+ pix_fmt->width = 640;
+ pix_fmt->height = 480;
+ pix_fmt->field = V4L2_FIELD_NONE;
+ pix_fmt->colorspace = V4L2_COLORSPACE_SRGB;
+ pix_fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
+ pix_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE;
+ pix_fmt->xfer_func = V4L2_XFER_FUNC_SRGB;
+ pix_fmt->pixelformat = formats[0].fourcc;
+ unicam_calc_format_size_bpl(node->dev, &formats[0],
+ &node->v_fmt);
+ node->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+
+ node->fmt = &formats[0];
+ } else {
+ const struct unicam_fmt *fmt;
+
+ /* Fix this node format as embedded data. */
+ fmt = find_format_by_code(MEDIA_BUS_FMT_METADATA_8);
+ node->v_fmt.fmt.meta.dataformat = fmt->fourcc;
+ node->fmt = fmt;
+ node->v_fmt.fmt.meta.buffersize = UNICAM_EMBEDDED_SIZE;
+ node->embedded_lines = 1;
+ node->v_fmt.type = V4L2_BUF_TYPE_META_CAPTURE;
+ }
+}
+
+static int register_node(struct unicam_device *unicam, struct unicam_node *node,
+ enum v4l2_buf_type type)
+{
+ struct video_device *vdev;
+ struct vb2_queue *q;
+ int ret;
+
+ node->dev = unicam;
+ node->node_id = type == V4L2_BUF_TYPE_VIDEO_CAPTURE ?
+ IMAGE_NODE :
+ METADATA_NODE;
+
+ spin_lock_init(&node->dma_queue_lock);
+ mutex_init(&node->lock);
+
+ vdev = &node->video_dev;
+ /*
+ * If the sensor subdevice has any controls, associate the node
+ * with the ctrl handler to allow access from userland.
+ */
+ if (!list_empty(&unicam->ctrl_handler.ctrls))
+ vdev->ctrl_handler = &unicam->ctrl_handler;
+
+ q = &node->buffer_queue;
+ q->type = type;
+ q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
+ q->drv_priv = node;
+ q->ops = &unicam_video_qops;
+ q->mem_ops = &vb2_dma_contig_memops;
+ q->buf_struct_size = sizeof(struct unicam_buffer);
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ q->lock = &node->lock;
+ q->min_buffers_needed = 1;
+ q->dev = &unicam->pdev->dev;
+
+ ret = vb2_queue_init(q);
+ if (ret) {
+ dev_err(unicam->v4l2_dev.dev, "vb2_queue_init() failed\n");
+ return ret;
+ }
+
+ INIT_LIST_HEAD(&node->dma_queue);
+
+ vdev->release = unicam_node_release;
+ vdev->fops = &unicam_fops;
+ vdev->ioctl_ops = &unicam_mc_ioctl_ops;
+ vdev->v4l2_dev = &unicam->v4l2_dev;
+ vdev->vfl_dir = VFL_DIR_RX;
+ vdev->queue = q;
+ vdev->lock = &node->lock;
+ vdev->device_caps = (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) ?
+ V4L2_CAP_VIDEO_CAPTURE : V4L2_CAP_META_CAPTURE;
+ vdev->device_caps |= V4L2_CAP_READWRITE | V4L2_CAP_STREAMING | V4L2_CAP_IO_MC;
+ vdev->entity.ops = &unicam_mc_entity_ops;
+
+ /* Define the device names */
+ snprintf(vdev->name, sizeof(vdev->name), "%s-%s", UNICAM_MODULE_NAME,
+ type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? "image" : "embedded");
+
+ video_set_drvdata(vdev, node);
+ if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ vdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;
+ node->pad.flags = MEDIA_PAD_FL_SINK;
+ media_entity_pads_init(&vdev->entity, 1, &node->pad);
+
+ node->dummy_buf_cpu_addr = dma_alloc_coherent(&unicam->pdev->dev,
+ DUMMY_BUF_SIZE,
+ &node->dummy_buf_dma_addr,
+ GFP_KERNEL);
+ if (!node->dummy_buf_cpu_addr) {
+ dev_err(unicam->v4l2_dev.dev, "Unable to allocate dummy buffer.\n");
+ return -ENOMEM;
+ }
+
+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+ if (ret) {
+ dev_err(unicam->v4l2_dev.dev, "Unable to register video device %s\n",
+ vdev->name);
+ return ret;
+ }
+
+ /*
+ * Acquire a reference to unicam, which will be released when the video
+ * device will be unregistered and userspace will have closed all open
+ * file handles.
+ */
+ unicam_get(unicam);
+ node->registered = true;
+
+ ret = media_create_pad_link(&unicam->sd.entity,
+ node->src_pad_id,
+ &node->video_dev.entity,
+ 0,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
+ if (ret)
+ dev_err(unicam->v4l2_dev.dev, "Unable to create pad link for %s",
+ unicam->sensor->name);
+
+ unicam_mc_set_default_format(node);
+
+ return ret;
+}
+
+static void unregister_nodes(struct unicam_device *unicam)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
+ struct unicam_node *node = &unicam->node[i];
+
+ if (node->dummy_buf_cpu_addr) {
+ dma_free_coherent(&unicam->pdev->dev, DUMMY_BUF_SIZE,
+ node->dummy_buf_cpu_addr,
+ node->dummy_buf_dma_addr);
+ }
+
+ if (node->registered) {
+ node->registered = false;
+ video_unregister_device(&node->video_dev);
+ }
+ }
+}
+
+static int unicam_async_complete(struct v4l2_async_notifier *notifier)
+{
+ struct unicam_device *unicam = to_unicam_device(notifier->v4l2_dev);
+ unsigned int i, source_pads = 0;
+ int ret;
+ static struct lock_class_key key;
+
+ unicam->v4l2_dev.notify = unicam_notify;
+
+ unicam->sensor_state = __v4l2_subdev_state_alloc(unicam->sensor,
+ "unicam:state->lock",
+ &key);
+ if (!unicam->sensor_state)
+ return -ENOMEM;
+
+ for (i = 0; i < unicam->sd.entity.num_pads; i++) {
+ if (unicam->sd.entity.pads[i].flags & MEDIA_PAD_FL_SOURCE) {
+ if (source_pads < MAX_NODES) {
+ unicam->node[source_pads].src_pad_id = i;
+ dev_dbg(unicam->v4l2_dev.dev, "source pad %u is index %u\n",
+ source_pads, i);
+ }
+ source_pads++;
+ }
+ }
+ if (!source_pads) {
+ dev_err(unicam->v4l2_dev.dev, "No source pads on sensor.\n");
+ goto unregister;
+ }
+
+ ret = register_node(unicam, &unicam->node[IMAGE_NODE],
+ V4L2_BUF_TYPE_VIDEO_CAPTURE);
+ if (ret) {
+ dev_err(unicam->v4l2_dev.dev, "Unable to register image video device.\n");
+ goto unregister;
+ }
+
+ /* \todo: check before :-) */
+ unicam->sensor_embedded_data = true;
+
+ ret = register_node(unicam, &unicam->node[METADATA_NODE],
+ V4L2_BUF_TYPE_META_CAPTURE);
+ if (ret) {
+ dev_err(unicam->v4l2_dev.dev, "Unable to register metadata video device.\n");
+ goto unregister;
+ }
+
+ ret = media_create_pad_link(&unicam->sensor->entity,
+ 0,
+ &unicam->sd.entity,
+ UNICAM_SD_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
+ if (ret)
+ dev_err(unicam->v4l2_dev.dev, "Unable to create pad link for %s",
+ unicam->sensor->name);
+
+ ret = v4l2_device_register_subdev_nodes(&unicam->v4l2_dev);
+ if (ret) {
+ dev_err(unicam->v4l2_dev.dev, "Unable to register subdev nodes.\n");
+ goto unregister;
+ }
+
+ /*
+ * Release the initial reference, all references are now owned by the
+ * video devices.
+ */
+ unicam_put(unicam);
+ return 0;
+
+unregister:
+ unregister_nodes(unicam);
+ unicam_put(unicam);
+
+ return ret;
+}
+
+static const struct v4l2_async_notifier_operations unicam_async_ops = {
+ .bound = unicam_async_bound,
+ .complete = unicam_async_complete,
+};
+
+static int of_unicam_connect_subdevs(struct unicam_device *dev)
+{
+ struct platform_device *pdev = dev->pdev;
+ struct v4l2_fwnode_endpoint ep = { };
+ struct device_node *ep_node;
+ struct device_node *sensor_node;
+ unsigned int lane;
+ int ret = -EINVAL;
+
+ if (of_property_read_u32(pdev->dev.of_node, "num-data-lanes",
+ &dev->max_data_lanes) < 0) {
+ dev_err(dev->v4l2_dev.dev, "number of data lanes not set\n");
+ return -EINVAL;
+ }
+
+ /* Get the local endpoint and remote device. */
+ ep_node = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
+ if (!ep_node) {
+ dev_dbg(dev->v4l2_dev.dev, "can't get next endpoint\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev->v4l2_dev.dev, "ep_node is %pOF\n", ep_node);
+
+ sensor_node = of_graph_get_remote_port_parent(ep_node);
+ if (!sensor_node) {
+ dev_dbg(dev->v4l2_dev.dev, "can't get remote parent\n");
+ goto cleanup_exit;
+ }
+
+ dev_dbg(dev->v4l2_dev.dev, "found subdevice %pOF\n", sensor_node);
+
+ /* Parse the local endpoint and validate its configuration. */
+ v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
+
+ dev_dbg(dev->v4l2_dev.dev, "parsed local endpoint, bus_type %u\n",
+ ep.bus_type);
+
+ dev->bus_type = ep.bus_type;
+
+ switch (ep.bus_type) {
+ case V4L2_MBUS_CSI2_DPHY:
+ switch (ep.bus.mipi_csi2.num_data_lanes) {
+ case 1:
+ case 2:
+ case 4:
+ break;
+
+ default:
+ dev_err(dev->v4l2_dev.dev, "subdevice %pOF: %u data lanes not supported\n",
+ sensor_node,
+ ep.bus.mipi_csi2.num_data_lanes);
+ goto cleanup_exit;
+ }
+
+ for (lane = 0; lane < ep.bus.mipi_csi2.num_data_lanes; lane++) {
+ if (ep.bus.mipi_csi2.data_lanes[lane] != lane + 1) {
+ dev_err(dev->v4l2_dev.dev, "subdevice %pOF: data lanes reordering not supported\n",
+ sensor_node);
+ goto cleanup_exit;
+ }
+ }
+
+ if (ep.bus.mipi_csi2.num_data_lanes > dev->max_data_lanes) {
+ dev_err(dev->v4l2_dev.dev, "subdevice requires %u data lanes when %u are supported\n",
+ ep.bus.mipi_csi2.num_data_lanes,
+ dev->max_data_lanes);
+ }
+
+ dev->max_data_lanes = ep.bus.mipi_csi2.num_data_lanes;
+ dev->bus_flags = ep.bus.mipi_csi2.flags;
+
+ break;
+
+ case V4L2_MBUS_CCP2:
+ if (ep.bus.mipi_csi1.clock_lane != 0 ||
+ ep.bus.mipi_csi1.data_lane != 1) {
+ dev_err(dev->v4l2_dev.dev, "subdevice %pOF: unsupported lanes configuration\n",
+ sensor_node);
+ goto cleanup_exit;
+ }
+
+ dev->max_data_lanes = 1;
+ dev->bus_flags = ep.bus.mipi_csi1.strobe;
+ break;
+
+ default:
+ /* Unsupported bus type */
+ dev_err(dev->v4l2_dev.dev, "subdevice %pOF: unsupported bus type %u\n",
+ sensor_node, ep.bus_type);
+ goto cleanup_exit;
+ }
+
+ dev_dbg(dev->v4l2_dev.dev, "subdevice %pOF: %s bus, %u data lanes, flags=0x%08x\n",
+ sensor_node,
+ dev->bus_type == V4L2_MBUS_CSI2_DPHY ? "CSI-2" : "CCP2",
+ dev->max_data_lanes, dev->bus_flags);
+
+ /* Initialize and register the async notifier. */
+ v4l2_async_nf_init(&dev->notifier);
+ dev->notifier.ops = &unicam_async_ops;
+
+ dev->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
+ dev->asd.match.fwnode = fwnode_graph_get_remote_endpoint(of_fwnode_handle(ep_node));
+ ret = v4l2_async_nf_add_subdev(&dev->notifier, &dev->asd);
+ if (ret) {
+ dev_err(dev->v4l2_dev.dev, "Error adding subdevice: %d\n", ret);
+ goto cleanup_exit;
+ }
+
+ ret = v4l2_async_nf_register(&dev->v4l2_dev, &dev->notifier);
+ if (ret) {
+ dev_err(dev->v4l2_dev.dev, "Error registering async notifier: %d\n", ret);
+ ret = -EINVAL;
+ }
+
+cleanup_exit:
+ of_node_put(sensor_node);
+ of_node_put(ep_node);
+
+ return ret;
+}
+
+static int bcm2835_media_dev_init(struct unicam_device *unicam,
+ struct platform_device *pdev)
+{
+ int ret = 0;
+
+ unicam->mdev.dev = &pdev->dev;
+ strscpy(unicam->mdev.model, UNICAM_MODULE_NAME,
+ sizeof(unicam->mdev.model));
+ strscpy(unicam->mdev.serial, "", sizeof(unicam->mdev.serial));
+ snprintf(unicam->mdev.bus_info, sizeof(unicam->mdev.bus_info),
+ "platform:%s", dev_name(&pdev->dev));
+ unicam->mdev.hw_revision = 0;
+
+ media_device_init(&unicam->mdev);
+
+ unicam->v4l2_dev.mdev = &unicam->mdev;
+
+ ret = v4l2_device_register(&pdev->dev, &unicam->v4l2_dev);
+
+ return ret;
+}
+
+/* Internal subdev */
+
+static int _unicam_subdev_set_routing(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ struct v4l2_subdev_krouting *routing)
+{
+ static const struct v4l2_mbus_framefmt format = {
+ .width = 640,
+ .height = 480,
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .field = V4L2_FIELD_NONE,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .ycbcr_enc = V4L2_YCBCR_ENC_601,
+ .quantization = V4L2_QUANTIZATION_LIM_RANGE,
+ .xfer_func = V4L2_XFER_FUNC_SRGB,
+ .flags = 0,
+ };
+ int ret;
+
+ ret = v4l2_subdev_routing_validate_1_to_1(routing);
+ if (ret)
+ return ret;
+
+ v4l2_subdev_lock_state(state);
+
+ ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format);
+
+ v4l2_subdev_unlock_state(state);
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int unicam_subdev_set_routing(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ enum v4l2_subdev_format_whence which,
+ struct v4l2_subdev_krouting *routing)
+{
+ struct unicam_device *unicam = sd_to_unicam_device(sd);
+
+ if (which == V4L2_SUBDEV_FORMAT_ACTIVE && unicam->streaming)
+ return -EBUSY;
+
+ return _unicam_subdev_set_routing(sd, state, routing);
+}
+
+static int unicam_subdev_init_cfg(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state)
+{
+ struct v4l2_subdev_route routes[] = {
+ {
+ .sink_pad = 0,
+ .sink_stream = 0,
+ .source_pad = 1,
+ .source_stream = 0,
+ .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
+ },
+ };
+
+ struct v4l2_subdev_krouting routing = {
+ .num_routes = ARRAY_SIZE(routes),
+ .routes = routes,
+ };
+
+ /* Initialize routing to single route to the fist source pad */
+ return _unicam_subdev_set_routing(sd, state, &routing);
+}
+
+static int unicam_subdev_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ int ret = 0;
+
+ v4l2_subdev_lock_state(state);
+
+ /* No transcoding, source and sink codes must match. */
+ if (unicam_sd_pad_is_source(code->pad)) {
+ struct v4l2_mbus_framefmt *fmt;
+
+ if (code->index > 0) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ fmt = v4l2_subdev_state_get_opposite_stream_format(state,
+ code->pad,
+ code->stream);
+ if (!fmt) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ code->code = fmt->code;
+ } else {
+ if (code->index >= ARRAY_SIZE(formats)) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ code->code = formats[code->index].code;
+ }
+
+out:
+ v4l2_subdev_unlock_state(state);
+
+ return ret;
+}
+
+static int unicam_subdev_start_streaming(struct unicam_device *unicam)
+{
+ const struct v4l2_subdev_krouting *routing;
+ struct v4l2_subdev_state *state;
+ int ret = 0;
+
+ state = v4l2_subdev_lock_active_state(&unicam->sd);
+
+ routing = &state->routing;
+
+ v4l2_subdev_unlock_state(state);
+
+ unicam->streaming = true;
+
+ ret = v4l2_subdev_call(unicam->sensor, video, s_stream, 1);
+ if (ret) {
+ v4l2_subdev_call(unicam->sensor, video, s_stream, 0);
+ unicam->streaming = false;
+ return ret;
+ }
+
+ return 0;
+}
+
+static int unicam_subdev_stop_streaming(struct unicam_device *unicam)
+{
+ v4l2_subdev_call(unicam->sensor, video, s_stream, 0);
+
+ unicam->streaming = false;
+
+ return 0;
+}
+
+static int unicam_subdev_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct unicam_device *unicam = sd_to_unicam_device(sd);
+
+ if (enable)
+ return unicam_subdev_start_streaming(unicam);
+ else
+ return unicam_subdev_stop_streaming(unicam);
+ return 0;
+}
+
+static int unicam_subdev_set_pad_format(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ struct v4l2_subdev_format *format)
+{
+ struct unicam_device *unicam = sd_to_unicam_device(sd);
+ struct v4l2_mbus_framefmt *fmt;
+ int ret = 0;
+
+ if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && unicam->streaming)
+ return -EBUSY;
+
+ /* No transcoding, source and sink formats must match. */
+ if (unicam_sd_pad_is_source(format->pad))
+ return v4l2_subdev_get_fmt(sd, state, format);
+
+ // TODO: implement fmt validation
+
+ v4l2_subdev_lock_state(state);
+
+ fmt = v4l2_state_get_stream_format(state, format->pad, format->stream);
+ if (!fmt) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ *fmt = format->format;
+
+ fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,
+ format->stream);
+ if (!fmt) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ *fmt = format->format;
+
+out:
+ v4l2_subdev_unlock_state(state);
+
+ return ret;
+}
+
+static int unicam_subdev_enum_frame_size(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ const struct unicam_fmt *fmtinfo;
+ int ret = 0;
+
+ if (fse->index > 0)
+ return -EINVAL;
+
+ v4l2_subdev_lock_state(state);
+
+ /* No transcoding, source and sink formats must match. */
+ if (unicam_sd_pad_is_source(fse->pad)) {
+ struct v4l2_mbus_framefmt *fmt;
+
+ fmt = v4l2_subdev_state_get_opposite_stream_format(state,
+ fse->pad,
+ fse->stream);
+
+ if (!fmt) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (fse->code != fmt->code) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ fse->min_width = fmt->width;
+ fse->max_width = fmt->width;
+ fse->min_height = fmt->height;
+ fse->max_height = fmt->height;
+ } else {
+ fmtinfo = find_format_by_code(fse->code);
+ if (!fmtinfo) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ fse->min_width = MIN_WIDTH * 8 / ALIGN(fmtinfo->depth, 8);
+ fse->max_width = MAX_WIDTH * 8 / ALIGN(fmtinfo->depth, 8);
+ fse->min_height = MIN_HEIGHT;
+ fse->max_height = MAX_HEIGHT;
+ }
+
+out:
+ v4l2_subdev_unlock_state(state);
+
+ return ret;
+}
+
+static const struct v4l2_subdev_video_ops unicam_subdev_video_ops = {
+ .s_stream = unicam_subdev_s_stream,
+};
+
+static const struct v4l2_subdev_pad_ops unicam_subdev_pad_ops = {
+ .init_cfg = unicam_subdev_init_cfg,
+ .enum_mbus_code = unicam_subdev_enum_mbus_code,
+ .get_fmt = v4l2_subdev_get_fmt,
+ .set_fmt = unicam_subdev_set_pad_format,
+ .set_routing = unicam_subdev_set_routing,
+ .enum_frame_size = unicam_subdev_enum_frame_size,
+};
+
+static const struct v4l2_subdev_ops unicam_subdev_ops = {
+ .video = &unicam_subdev_video_ops,
+ .pad = &unicam_subdev_pad_ops,
+};
+
+static struct media_entity_operations unicam_subdev_media_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+ .has_route = v4l2_subdev_has_route,
+};
+
+static int unicam_probe(struct platform_device *pdev)
+{
+ struct unicam_device *unicam;
+ int ret = 0;
+ int i;
+
+ unicam = kzalloc(sizeof(*unicam), GFP_KERNEL);
+ if (!unicam)
+ return -ENOMEM;
+
+ kref_init(&unicam->kref);
+ unicam->pdev = pdev;
+
+ unicam->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(unicam->base)) {
+ dev_err(unicam->v4l2_dev.dev, "Failed to get main io block\n");
+ ret = PTR_ERR(unicam->base);
+ goto err_unicam_put;
+ }
+
+ unicam->clk_gate_base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(unicam->clk_gate_base)) {
+ dev_err(unicam->v4l2_dev.dev, "Failed to get 2nd io block\n");
+ ret = PTR_ERR(unicam->clk_gate_base);
+ goto err_unicam_put;
+ }
+
+ unicam->clock = devm_clk_get(&pdev->dev, "lp");
+ if (IS_ERR(unicam->clock)) {
+ dev_err(unicam->v4l2_dev.dev, "Failed to get lp clock\n");
+ ret = PTR_ERR(unicam->clock);
+ goto err_unicam_put;
+ }
+
+ unicam->vpu_clock = devm_clk_get(&pdev->dev, "vpu");
+ if (IS_ERR(unicam->vpu_clock)) {
+ dev_err(unicam->v4l2_dev.dev, "Failed to get vpu clock\n");
+ ret = PTR_ERR(unicam->vpu_clock);
+ goto err_unicam_put;
+ }
+
+ ret = platform_get_irq(pdev, 0);
+ if (ret <= 0) {
+ dev_err(&pdev->dev, "No IRQ resource\n");
+ ret = -EINVAL;
+ goto err_unicam_put;
+ }
+
+ ret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,
+ "unicam_capture0", unicam);
+ if (ret) {
+ dev_err(&pdev->dev, "Unable to request interrupt\n");
+ ret = -EINVAL;
+ goto err_unicam_put;
+ }
+
+ ret = bcm2835_media_dev_init(unicam, pdev);
+ if (ret) {
+ dev_err(unicam->v4l2_dev.dev,
+ "Unable to register v4l2 device.\n");
+ goto err_unicam_put;
+ }
+
+ ret = media_device_register(&unicam->mdev);
+ if (ret < 0) {
+ dev_err(unicam->v4l2_dev.dev,
+ "Unable to register media-controller device.\n");
+ goto err_v4l2_unregister;
+ }
+
+ /* Reserve space for the controls */
+ ret = v4l2_ctrl_handler_init(&unicam->ctrl_handler, 16);
+ if (ret < 0)
+ goto err_media_unregister;
+
+ /* set the driver data in platform device */
+ platform_set_drvdata(pdev, unicam);
+
+ dev_dbg(unicam->v4l2_dev.dev, "Initialize internal subdev");
+ v4l2_subdev_init(&unicam->sd, &unicam_subdev_ops);
+ v4l2_set_subdevdata(&unicam->sd, unicam);
+ unicam->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
+ unicam->sd.dev = &pdev->dev;
+ unicam->sd.owner = THIS_MODULE;
+ unicam->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_MULTIPLEXED;
+ snprintf(unicam->sd.name, sizeof(unicam->sd.name), "unicam-subdev");
+
+ unicam->pads[UNICAM_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+
+ for (i = UNICAM_SD_PAD_FIRST_SOURCE; i < UNICAM_SD_NUM_PADS; ++i)
+ unicam->pads[i].flags = MEDIA_PAD_FL_SOURCE;
+ unicam->sd.entity.ops = &unicam_subdev_media_ops;
+ ret = media_entity_pads_init(&unicam->sd.entity,
+ ARRAY_SIZE(unicam->pads), unicam->pads);
+ if (ret) {
+ dev_err(unicam->v4l2_dev.dev, "Could not init media controller for subdev");
+ goto err_subdev_unregister;
+ }
+
+ ret = v4l2_subdev_init_finalize(&unicam->sd);
+ if (ret) {
+ dev_err(unicam->v4l2_dev.dev, "Could not finalize init for subdev");
+ goto err_entity_cleanup;
+ }
+
+ ret = v4l2_device_register_subdev(&unicam->v4l2_dev, &unicam->sd);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register internal subdev\n");
+ goto err_subdev_unregister;
+ }
+
+ ret = of_unicam_connect_subdevs(unicam);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to connect subdevs\n");
+ goto err_subdev_unregister;
+ }
+
+ /* Enable the block power domain */
+ pm_runtime_enable(&pdev->dev);
+
+ return 0;
+
+err_subdev_unregister:
+ v4l2_subdev_cleanup(&unicam->sd);
+err_entity_cleanup:
+ media_entity_cleanup(&unicam->sd.entity);
+err_media_unregister:
+ media_device_unregister(&unicam->mdev);
+err_v4l2_unregister:
+ v4l2_device_unregister(&unicam->v4l2_dev);
+err_unicam_put:
+ unicam_put(unicam);
+
+ return ret;
+}
+
+static int unicam_remove(struct platform_device *pdev)
+{
+ struct unicam_device *unicam = platform_get_drvdata(pdev);
+
+ v4l2_async_nf_unregister(&unicam->notifier);
+ v4l2_device_unregister(&unicam->v4l2_dev);
+ media_device_unregister(&unicam->mdev);
+ unregister_nodes(unicam);
+
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id unicam_of_match[] = {
+ { .compatible = "brcm,bcm2835-unicam", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, unicam_of_match);
+
+static struct platform_driver unicam_driver = {
+ .probe = unicam_probe,
+ .remove = unicam_remove,
+ .driver = {
+ .name = UNICAM_MODULE_NAME,
+ .of_match_table = of_match_ptr(unicam_of_match),
+ },
+};
+
+module_platform_driver(unicam_driver);
+
+MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com>");
+MODULE_DESCRIPTION("BCM2835 Unicam driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(UNICAM_VERSION);
diff --git a/drivers/media/platform/bcm2835/vc4-regs-unicam.h b/drivers/media/platform/bcm2835/vc4-regs-unicam.h
new file mode 100644
index 000000000000..ae059a171d0f
--- /dev/null
+++ b/drivers/media/platform/bcm2835/vc4-regs-unicam.h
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Copyright (C) 2017-2020 Raspberry Pi Trading.
+ * Dave Stevenson <dave.stevenson@raspberrypi.com>
+ */
+
+#ifndef VC4_REGS_UNICAM_H
+#define VC4_REGS_UNICAM_H
+
+/*
+ * The following values are taken from files found within the code drop
+ * made by Broadcom for the BCM21553 Graphics Driver, predominantly in
+ * brcm_usrlib/dag/vmcsx/vcinclude/hardware_vc4.h.
+ * They have been modified to be only the register offset.
+ */
+#define UNICAM_CTRL 0x000
+#define UNICAM_STA 0x004
+#define UNICAM_ANA 0x008
+#define UNICAM_PRI 0x00c
+#define UNICAM_CLK 0x010
+#define UNICAM_CLT 0x014
+#define UNICAM_DAT0 0x018
+#define UNICAM_DAT1 0x01c
+#define UNICAM_DAT2 0x020
+#define UNICAM_DAT3 0x024
+#define UNICAM_DLT 0x028
+#define UNICAM_CMP0 0x02c
+#define UNICAM_CMP1 0x030
+#define UNICAM_CAP0 0x034
+#define UNICAM_CAP1 0x038
+#define UNICAM_ICTL 0x100
+#define UNICAM_ISTA 0x104
+#define UNICAM_IDI0 0x108
+#define UNICAM_IPIPE 0x10c
+#define UNICAM_IBSA0 0x110
+#define UNICAM_IBEA0 0x114
+#define UNICAM_IBLS 0x118
+#define UNICAM_IBWP 0x11c
+#define UNICAM_IHWIN 0x120
+#define UNICAM_IHSTA 0x124
+#define UNICAM_IVWIN 0x128
+#define UNICAM_IVSTA 0x12c
+#define UNICAM_ICC 0x130
+#define UNICAM_ICS 0x134
+#define UNICAM_IDC 0x138
+#define UNICAM_IDPO 0x13c
+#define UNICAM_IDCA 0x140
+#define UNICAM_IDCD 0x144
+#define UNICAM_IDS 0x148
+#define UNICAM_DCS 0x200
+#define UNICAM_DBSA0 0x204
+#define UNICAM_DBEA0 0x208
+#define UNICAM_DBWP 0x20c
+#define UNICAM_DBCTL 0x300
+#define UNICAM_IBSA1 0x304
+#define UNICAM_IBEA1 0x308
+#define UNICAM_IDI1 0x30c
+#define UNICAM_DBSA1 0x310
+#define UNICAM_DBEA1 0x314
+#define UNICAM_MISC 0x400
+
+/*
+ * The following bitmasks are from the kernel released by Broadcom
+ * for Android - https://android.googlesource.com/kernel/bcm/
+ * The Rhea, Hawaii, and Java chips all contain the same VideoCore4
+ * Unicam block as BCM2835, as defined in eg
+ * arch/arm/mach-rhea/include/mach/rdb_A0/brcm_rdb_cam.h and similar.
+ * Values reworked to use the kernel BIT and GENMASK macros.
+ *
+ * Some of the bit mnenomics have been amended to match the datasheet.
+ */
+/* UNICAM_CTRL Register */
+#define UNICAM_CPE BIT(0)
+#define UNICAM_MEM BIT(1)
+#define UNICAM_CPR BIT(2)
+#define UNICAM_CPM_MASK GENMASK(3, 3)
+#define UNICAM_CPM_CSI2 0
+#define UNICAM_CPM_CCP2 1
+#define UNICAM_SOE BIT(4)
+#define UNICAM_DCM_MASK GENMASK(5, 5)
+#define UNICAM_DCM_STROBE 0
+#define UNICAM_DCM_DATA 1
+#define UNICAM_SLS BIT(6)
+#define UNICAM_PFT_MASK GENMASK(11, 8)
+#define UNICAM_OET_MASK GENMASK(20, 12)
+
+/* UNICAM_STA Register */
+#define UNICAM_SYN BIT(0)
+#define UNICAM_CS BIT(1)
+#define UNICAM_SBE BIT(2)
+#define UNICAM_PBE BIT(3)
+#define UNICAM_HOE BIT(4)
+#define UNICAM_PLE BIT(5)
+#define UNICAM_SSC BIT(6)
+#define UNICAM_CRCE BIT(7)
+#define UNICAM_OES BIT(8)
+#define UNICAM_IFO BIT(9)
+#define UNICAM_OFO BIT(10)
+#define UNICAM_BFO BIT(11)
+#define UNICAM_DL BIT(12)
+#define UNICAM_PS BIT(13)
+#define UNICAM_IS BIT(14)
+#define UNICAM_PI0 BIT(15)
+#define UNICAM_PI1 BIT(16)
+#define UNICAM_FSI_S BIT(17)
+#define UNICAM_FEI_S BIT(18)
+#define UNICAM_LCI_S BIT(19)
+#define UNICAM_BUF0_RDY BIT(20)
+#define UNICAM_BUF0_NO BIT(21)
+#define UNICAM_BUF1_RDY BIT(22)
+#define UNICAM_BUF1_NO BIT(23)
+#define UNICAM_DI BIT(24)
+
+#define UNICAM_STA_MASK_ALL \
+ (UNICAM_DL + \
+ UNICAM_SBE + \
+ UNICAM_PBE + \
+ UNICAM_HOE + \
+ UNICAM_PLE + \
+ UNICAM_SSC + \
+ UNICAM_CRCE + \
+ UNICAM_IFO + \
+ UNICAM_OFO + \
+ UNICAM_PS + \
+ UNICAM_PI0 + \
+ UNICAM_PI1)
+
+/* UNICAM_ANA Register */
+#define UNICAM_APD BIT(0)
+#define UNICAM_BPD BIT(1)
+#define UNICAM_AR BIT(2)
+#define UNICAM_DDL BIT(3)
+#define UNICAM_CTATADJ_MASK GENMASK(7, 4)
+#define UNICAM_PTATADJ_MASK GENMASK(11, 8)
+
+/* UNICAM_PRI Register */
+#define UNICAM_PE BIT(0)
+#define UNICAM_PT_MASK GENMASK(2, 1)
+#define UNICAM_NP_MASK GENMASK(7, 4)
+#define UNICAM_PP_MASK GENMASK(11, 8)
+#define UNICAM_BS_MASK GENMASK(15, 12)
+#define UNICAM_BL_MASK GENMASK(17, 16)
+
+/* UNICAM_CLK Register */
+#define UNICAM_CLE BIT(0)
+#define UNICAM_CLPD BIT(1)
+#define UNICAM_CLLPE BIT(2)
+#define UNICAM_CLHSE BIT(3)
+#define UNICAM_CLTRE BIT(4)
+#define UNICAM_CLAC_MASK GENMASK(8, 5)
+#define UNICAM_CLSTE BIT(29)
+
+/* UNICAM_CLT Register */
+#define UNICAM_CLT1_MASK GENMASK(7, 0)
+#define UNICAM_CLT2_MASK GENMASK(15, 8)
+
+/* UNICAM_DATn Registers */
+#define UNICAM_DLE BIT(0)
+#define UNICAM_DLPD BIT(1)
+#define UNICAM_DLLPE BIT(2)
+#define UNICAM_DLHSE BIT(3)
+#define UNICAM_DLTRE BIT(4)
+#define UNICAM_DLSM BIT(5)
+#define UNICAM_DLFO BIT(28)
+#define UNICAM_DLSTE BIT(29)
+
+#define UNICAM_DAT_MASK_ALL (UNICAM_DLSTE + UNICAM_DLFO)
+
+/* UNICAM_DLT Register */
+#define UNICAM_DLT1_MASK GENMASK(7, 0)
+#define UNICAM_DLT2_MASK GENMASK(15, 8)
+#define UNICAM_DLT3_MASK GENMASK(23, 16)
+
+/* UNICAM_ICTL Register */
+#define UNICAM_FSIE BIT(0)
+#define UNICAM_FEIE BIT(1)
+#define UNICAM_IBOB BIT(2)
+#define UNICAM_FCM BIT(3)
+#define UNICAM_TFC BIT(4)
+#define UNICAM_LIP_MASK GENMASK(6, 5)
+#define UNICAM_LCIE_MASK GENMASK(28, 16)
+
+/* UNICAM_IDI0/1 Register */
+#define UNICAM_ID0_MASK GENMASK(7, 0)
+#define UNICAM_ID1_MASK GENMASK(15, 8)
+#define UNICAM_ID2_MASK GENMASK(23, 16)
+#define UNICAM_ID3_MASK GENMASK(31, 24)
+
+/* UNICAM_ISTA Register */
+#define UNICAM_FSI BIT(0)
+#define UNICAM_FEI BIT(1)
+#define UNICAM_LCI BIT(2)
+
+#define UNICAM_ISTA_MASK_ALL (UNICAM_FSI + UNICAM_FEI + UNICAM_LCI)
+
+/* UNICAM_IPIPE Register */
+#define UNICAM_PUM_MASK GENMASK(2, 0)
+ /* Unpacking modes */
+ #define UNICAM_PUM_NONE 0
+ #define UNICAM_PUM_UNPACK6 1
+ #define UNICAM_PUM_UNPACK7 2
+ #define UNICAM_PUM_UNPACK8 3
+ #define UNICAM_PUM_UNPACK10 4
+ #define UNICAM_PUM_UNPACK12 5
+ #define UNICAM_PUM_UNPACK14 6
+ #define UNICAM_PUM_UNPACK16 7
+#define UNICAM_DDM_MASK GENMASK(6, 3)
+#define UNICAM_PPM_MASK GENMASK(9, 7)
+ /* Packing modes */
+ #define UNICAM_PPM_NONE 0
+ #define UNICAM_PPM_PACK8 1
+ #define UNICAM_PPM_PACK10 2
+ #define UNICAM_PPM_PACK12 3
+ #define UNICAM_PPM_PACK14 4
+ #define UNICAM_PPM_PACK16 5
+#define UNICAM_DEM_MASK GENMASK(11, 10)
+#define UNICAM_DEBL_MASK GENMASK(14, 12)
+#define UNICAM_ICM_MASK GENMASK(16, 15)
+#define UNICAM_IDM_MASK GENMASK(17, 17)
+
+/* UNICAM_ICC Register */
+#define UNICAM_ICFL_MASK GENMASK(4, 0)
+#define UNICAM_ICFH_MASK GENMASK(9, 5)
+#define UNICAM_ICST_MASK GENMASK(12, 10)
+#define UNICAM_ICLT_MASK GENMASK(15, 13)
+#define UNICAM_ICLL_MASK GENMASK(31, 16)
+
+/* UNICAM_DCS Register */
+#define UNICAM_DIE BIT(0)
+#define UNICAM_DIM BIT(1)
+#define UNICAM_DBOB BIT(3)
+#define UNICAM_FDE BIT(4)
+#define UNICAM_LDP BIT(5)
+#define UNICAM_EDL_MASK GENMASK(15, 8)
+
+/* UNICAM_DBCTL Register */
+#define UNICAM_DBEN BIT(0)
+#define UNICAM_BUF0_IE BIT(1)
+#define UNICAM_BUF1_IE BIT(2)
+
+/* UNICAM_CMP[0,1] register */
+#define UNICAM_PCE BIT(31)
+#define UNICAM_GI BIT(9)
+#define UNICAM_CPH BIT(8)
+#define UNICAM_PCVC_MASK GENMASK(7, 6)
+#define UNICAM_PCDT_MASK GENMASK(5, 0)
+
+/* UNICAM_MISC register */
+#define UNICAM_FL0 BIT(6)
+#define UNICAM_FL1 BIT(9)
+
+#endif
--
2.32.0
^ permalink raw reply related
* [RFC PATCH v2 3/7] media: dt-bindings: media: Add bindings for bcm2835-unicam
From: Jean-Michel Hautbois @ 2022-01-21 8:18 UTC (permalink / raw)
To: jeanmichel.hautbois
Cc: dave.stevenson, devicetree, kernel-list, laurent.pinchart,
linux-arm-kernel, linux-kernel, linux-media, linux-rpi-kernel,
lukasz, mchehab, naush, robh, tomi.valkeinen
In-Reply-To: <20220121081810.155500-1-jeanmichel.hautbois@ideasonboard.com>
Introduce the dt-bindinds documentation for bcm2835 CCP2/CSI2 camera
interface. Also add a MAINTAINERS entry for it.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
---
Dave: I assumed you were the maintainer for this file, as I based it on the
bcm2835-unicam.txt file. Are you happy to be added directly as the
maintainer, or should this be specified as "Raspberry Pi Kernel
Maintenance <kernel-list@raspberrypi.com>"
- in v2: multiple corrections to pass the bot checking as Rob kindly
told me.
---
.../bindings/media/brcm,bcm2835-unicam.yaml | 103 ++++++++++++++++++
MAINTAINERS | 6 +
2 files changed, 109 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
diff --git a/Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml b/Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
new file mode 100644
index 000000000000..1427514142cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/brcm,bcm2835-unicam.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM283x Camera Interface (Unicam)
+
+maintainers:
+ - Dave Stevenson <dave.stevenson@raspberrypi.com>
+
+description: |-
+ The Unicam block on BCM283x SoCs is the receiver for either
+ CSI-2 or CCP2 data from image sensors or similar devices.
+
+ The main platform using this SoC is the Raspberry Pi family of boards.
+ On the Pi the VideoCore firmware can also control this hardware block,
+ and driving it from two different processors will cause issues.
+ To avoid this, the firmware checks the device tree configuration
+ during boot. If it finds device tree nodes called csi0 or csi1 then
+ it will stop the firmware accessing the block, and it can then
+ safely be used via the device tree binding.
+
+properties:
+ compatible:
+ const: brcm,bcm2835-unicam
+
+ reg:
+ description:
+ physical base address and length of the register sets for the device.
+ maxItems: 1
+
+ interrupts:
+ description: the IRQ line for this Unicam instance.
+ maxItems: 1
+
+ clocks:
+ description: |-
+ list of clock specifiers, corresponding to entries in clock-names
+ property.
+
+ clock-names:
+ items:
+ - const: lp
+ - const: vpu
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - port
+
+additionalProperties: False
+
+examples:
+ - |
+ csi1: csi1@7e801000 {
+ compatible = "brcm,bcm2835-unicam";
+ reg = <0x7e801000 0x800>,
+ <0x7e802004 0x4>;
+ interrupts = <2 7>;
+ clocks = <&clocks BCM2835_CLOCK_CAM1>,
+ <&firmware_clocks 4>;
+ clock-names = "lp", "vpu";
+ port {
+ csi1_ep: endpoint {
+ remote-endpoint = <&tc358743_0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ i2c0: i2c@7e205000 {
+ tc358743: csi-hdmi-bridge@0f {
+ compatible = "toshiba,tc358743";
+ reg = <0x0f>;
+ clocks = <&tc358743_clk>;
+ clock-names = "refclk";
+
+ tc358743_clk: bridge-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ port {
+ tc358743_0: endpoint {
+ remote-endpoint = <&csi1_ep>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ clock-noncontinuous;
+ link-frequencies =
+ /bits/ 64 <297000000>;
+ };
+ };
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 33f75892f98e..07f238fd5ff9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3679,6 +3679,12 @@ F: Documentation/media/v4l-drivers/bcm2835-isp.rst
F: drivers/staging/vc04_services/bcm2835-isp
F: include/uapi/linux/bcm2835-isp.h
+BROADCOM BCM2835 CAMERA DRIVER
+M: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
+L: linux-media@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
+
BROADCOM BCM47XX MIPS ARCHITECTURE
M: Hauke Mehrtens <hauke@hauke-m.de>
M: Rafał Miłecki <zajec5@gmail.com>
--
2.32.0
^ permalink raw reply related
* [RFC PATCH v2 1/7] media: v4l: Add V4L2-PIX-FMT-Y12P format
From: Jean-Michel Hautbois @ 2022-01-21 8:18 UTC (permalink / raw)
To: jeanmichel.hautbois
Cc: dave.stevenson, devicetree, kernel-list, laurent.pinchart,
linux-arm-kernel, linux-kernel, linux-media, linux-rpi-kernel,
lukasz, mchehab, naush, robh, tomi.valkeinen
In-Reply-To: <20220121081810.155500-1-jeanmichel.hautbois@ideasonboard.com>
This is a packed grey-scale image format with a depth of 12 bits per
pixel. Two consecutive pixels are packed into 3 bytes. The first 2 bytes
contain the 8 high order bits of the pixels, and the 3rd byte contains
the 4 least significants bits of each pixel, in the same order.
Add the entry in userspace API, and document it.
Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
.../userspace-api/media/v4l/pixfmt-yuv-luma.rst | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst
index 8ebd58c3588f..d37ce6027095 100644
--- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst
+++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst
@@ -92,6 +92,17 @@ are often referred to as greyscale formats.
- ...
- ...
+ * .. _V4L2-PIX-FMT-Y12P:
+
+ - ``V4L2_PIX_FMT_Y12P``
+ - 'Y12P'
+
+ - Y'\ :sub:`0`\ [11:4]
+ - Y'\ :sub:`1`\ [11:4]
+ - Y'\ :sub:`1`\ [3:0] Y'\ :sub:`0`\ [3:0]
+ - ...
+ - ...
+
* .. _V4L2-PIX-FMT-Y14:
- ``V4L2_PIX_FMT_Y14``
--
2.32.0
^ permalink raw reply related
* [RFC PATCH v2 2/7] media: v4l: Add V4L2-PIX-FMT-Y14P format
From: Jean-Michel Hautbois @ 2022-01-21 8:18 UTC (permalink / raw)
To: jeanmichel.hautbois
Cc: dave.stevenson, devicetree, kernel-list, laurent.pinchart,
linux-arm-kernel, linux-kernel, linux-media, linux-rpi-kernel,
lukasz, mchehab, naush, robh, tomi.valkeinen
In-Reply-To: <20220121081810.155500-1-jeanmichel.hautbois@ideasonboard.com>
This is a packed grey-scale image format with a depth of 14 bits per
pixel. Every four consecutive samples are packed into seven bytes. Each
of the first four bytes contain the eight high order bits of the pixels,
and the three following bytes contains the six least significants bits
of each pixel, in the same order.
As the other formats only needed 5 bytes before, append two bytes in the
documentation array.
Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
.../media/v4l/pixfmt-yuv-luma.rst | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst
index d37ce6027095..c64485b03d27 100644
--- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst
+++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst
@@ -36,6 +36,8 @@ are often referred to as greyscale formats.
- Byte 2
- Byte 3
- Byte 4
+ - Byte 5
+ - Byte 6
* .. _V4L2-PIX-FMT-GREY:
@@ -47,6 +49,8 @@ are often referred to as greyscale formats.
- ...
- ...
- ...
+ - ...
+ - ...
* .. _V4L2-PIX-FMT-Y10:
@@ -58,6 +62,8 @@ are often referred to as greyscale formats.
- ...
- ...
- ...
+ - ...
+ - ...
* .. _V4L2-PIX-FMT-Y10BPACK:
@@ -69,6 +75,8 @@ are often referred to as greyscale formats.
- Y'\ :sub:`1`\ [3:0] Y'\ :sub:`2`\ [9:6]
- Y'\ :sub:`2`\ [5:0] Y'\ :sub:`3`\ [9:8]
- Y'\ :sub:`3`\ [7:0]
+ - ...
+ - ...
* .. _V4L2-PIX-FMT-Y10P:
@@ -80,6 +88,8 @@ are often referred to as greyscale formats.
- Y'\ :sub:`2`\ [9:2]
- Y'\ :sub:`3`\ [9:2]
- Y'\ :sub:`3`\ [1:0] Y'\ :sub:`2`\ [1:0] Y'\ :sub:`1`\ [1:0] Y'\ :sub:`0`\ [1:0]
+ - ...
+ - ...
* .. _V4L2-PIX-FMT-Y12:
@@ -91,6 +101,8 @@ are often referred to as greyscale formats.
- ...
- ...
- ...
+ - ...
+ - ...
* .. _V4L2-PIX-FMT-Y12P:
@@ -102,6 +114,8 @@ are often referred to as greyscale formats.
- Y'\ :sub:`1`\ [3:0] Y'\ :sub:`0`\ [3:0]
- ...
- ...
+ - ...
+ - ...
* .. _V4L2-PIX-FMT-Y14:
@@ -113,6 +127,21 @@ are often referred to as greyscale formats.
- ...
- ...
- ...
+ - ...
+ - ...
+
+ * .. _V4L2-PIX-FMT-Y14P:
+
+ - ``V4L2_PIX_FMT_Y14P``
+ - 'Y14P'
+
+ - Y'\ :sub:`0`\ [13:6]
+ - Y'\ :sub:`1`\ [13:6]
+ - Y'\ :sub:`2`\ [13:6]
+ - Y'\ :sub:`3`\ [13:6]
+ - Y'\ :sub:`1`\ [1:0] Y'\ :sub:`0`\ [5:0]
+ - Y'\ :sub:`2`\ [3:0] Y'\ :sub:`1`\ [5:2]
+ - Y'\ :sub:`3`\ [5:0] Y'\ :sub:`2`\ [5:4]
* .. _V4L2-PIX-FMT-Y16:
@@ -124,6 +153,8 @@ are often referred to as greyscale formats.
- ...
- ...
- ...
+ - ...
+ - ...
* .. _V4L2-PIX-FMT-Y16-BE:
@@ -135,6 +166,8 @@ are often referred to as greyscale formats.
- ...
- ...
- ...
+ - ...
+ - ...
.. raw:: latex
--
2.32.0
^ permalink raw reply related
* [RFC PATCH v2 0/7] Add support for BCM2835 camera interface (unicam)
From: Jean-Michel Hautbois @ 2022-01-21 8:18 UTC (permalink / raw)
To: jeanmichel.hautbois
Cc: dave.stevenson, devicetree, kernel-list, laurent.pinchart,
linux-arm-kernel, linux-kernel, linux-media, linux-rpi-kernel,
lukasz, mchehab, naush, robh, tomi.valkeinen
Hello !
This patch series adds the BCM2835 CCP2/CSI2 camera interface named
unicam. This driver is already used in the out-of-tree linux-rpi
repository [1], and this work aims to support it in mainline.
The series is based on top of:
- Rebased on top of 5.16 Tomi Valkeinen's multiplexed stream work, on
his multistream/work branch [2] which has been submitted as v10 at the
time of this writing. The objective is to demonstrate the use of
multiplexed streams on a real world widely used example as well as
supporting unicam mainline.
- The "Add 12bit and 14bit luma-only formats" series [3] is partly
applied (the Y10P format bug) the new formats are now part of this
series.
The series is made of 7 patches:
- 1/7 and 2/7 introduce the new formats needed for the unicam driver
- 3/7 introduces dt-bindings documentation and MAINTAINERS entry
I have tentatively assigned maintainership, is this fine ?
- 4/7 adds the driver support in media/platform
- 5/7 introduces the csi nodes in the bcm2711 file, in a disabled state
- 6/7 modifies imx219 driver to make it use the multiplexed streams API
- 7/7 is the imx219 dtsi file tested on my RPi 4b with the mainline dtb
and not the downstream dtb anymore.
All those patches are in my tree [4].
Patch 4/7 comes from the linux-rpi work [1] with substantial
modifications:
- Removed the non-mc API which is deprecated, and not needed upstream
- Moved from one video node with two source pads (image and embedded) to
two video nodes
- Added a subdev between the sensor and the video nodes to properly
route the streams
- Added support for multiplexed streams API
In order to test it, one will need a RPi board and the camv2 (imx219)
sensor. An updated v4l-utils is also needed [5] to have support for
multiplexed streams.
v4l2-compliance passes on both video devices, without streaming testing
though.
This series in its v2 does integrate the device tree nodes into the
upstream BCM2835 or BCM2711 device tree support.
The media-ctl topology is:
```
pi@raspberrypi:~ $ media-ctl -d0 -p
Media controller API version 5.16.0
Media device information
------------------------
driver unicam
model unicam
serial
bus info platform:fe801000.csi
hw revision 0x0
driver version 5.16.0
Device topology
- entity 1: unicam-subdev (3 pads, 3 links, 1 route)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev0
routes:
0/0 -> 1/0 [ACTIVE]
pad0: Sink
[stream:0 fmt:UYVY8_2X8/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
<- "imx219 10-0010":0 [ENABLED,IMMUTABLE]
pad1: Source
[stream:0 fmt:UYVY8_2X8/640x480 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:lim-range]
-> "unicam-image":0 [ENABLED,IMMUTABLE]
pad2: Source
-> "unicam-embedded":0 [ENABLED,IMMUTABLE]
- entity 5: imx219 10-0010 (1 pad, 1 link, 2 routes)
type V4L2 subdev subtype Sensor flags 0
device node name /dev/v4l-subdev1
routes:
0/0 -> 0/0 [ACTIVE, IMMUTABLE, SOURCE]
0/0 -> 0/1 [ACTIVE, SOURCE]
pad0: Source
[stream:0 fmt:SRGGB10_1X10/3280x2464 field:none colorspace:raw
crop.bounds:(8,8)/3280x2464
crop:(8,8)/3280x2464]
[stream:1 fmt:METADATA_8/16384x1 field:none
crop.bounds:(8,8)/3280x2464
crop:(8,8)/3280x2464]
-> "unicam-subdev":0 [ENABLED,IMMUTABLE]
- entity 7: unicam-image (1 pad, 1 link, 0 route)
type Node subtype V4L flags 1
device node name /dev/video0
pad0: Sink
<- "unicam-subdev":1 [ENABLED,IMMUTABLE]
- entity 13: unicam-embedded (1 pad, 1 link, 0 route)
type Node subtype V4L flags 0
device node name /dev/video1
pad0: Sink
<- "unicam-subdev":2 [ENABLED,IMMUTABLE]
```
In order to properly configure the media pipeline, it is needed to call
the usual ioctls, and configure routing in order to send the embedded
data from the sensor to the "unicam-embedded" device node :
``` media=0
media-ctl -d${media} -l "'imx219 10-0010':0->'unicam-subdev':0 [1]"
media-ctl -d${media} -l "'unicam-subdev':1->'unicam-image':0 [1]"
media-ctl -d${media} -v -R "'unicam-subdev' [0/0->1/0[1],0/1->2/0[1]]"
media-ctl -d${media} -V "'imx219 10-0010':0/0
[fmt:SRGGB10_1X10/3280x2464 field:none]" v4l2-ctl -d0 --set-fmt-video
width=3280,height=2464,pixelformat='pRAA',field=none media-ctl
-d${media} -v -V "'imx219 10-0010':0/1 [fmt:METADATA_8/16384x1
field:none]" media-ctl -d${media} -p ```
Be sure to configure the routes before setting the format, as s_routing
resets the default format.
Then a frame can be capture with yavta:
`yavta --capture=1 /dev/video0 -F/tmp/test-#.bin`
Side note:
My tree [4] also includes a backport for the unicam-isp drivers, it is
then possible, and it has been successfully tested, to use libcamera and
qcam to display the camera output.
[1]: https://github.com/raspberrypi/linux/tree/rpi-5.15.y
[2]: https://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux.git/log/?h=multistream/work
[3]: https://patchwork.linuxtv.org/project/linux-media/list/?series=7099
[4]: https://github.com/jhautbois/linux/tree/jmh/tomba/multistream/next/work-v10-with-laurent-isp
[5]: https://github.com/tomba/v4l-utils
Jean-Michel Hautbois (7):
media: v4l: Add V4L2-PIX-FMT-Y12P format
media: v4l: Add V4L2-PIX-FMT-Y14P format
media: dt-bindings: media: Add bindings for bcm2835-unicam
media: bcm2835-unicam: Add support for for CCP2/CSI2 camera interface
ARM: dts: bcm2711: Add unicam CSI nodes
media: imx219: Add support for multiplexed streams
media: bcm283x: Include the imx219 node
.../bindings/media/brcm,bcm2835-unicam.yaml | 103 +
.../media/v4l/pixfmt-yuv-luma.rst | 44 +
MAINTAINERS | 7 +
arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 1 +
arch/arm/boot/dts/bcm2711.dtsi | 31 +
arch/arm/boot/dts/bcm283x-rpi-imx219.dtsi | 103 +
drivers/media/i2c/imx219.c | 452 +--
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/bcm2835/Kconfig | 21 +
drivers/media/platform/bcm2835/Makefile | 3 +
.../media/platform/bcm2835/bcm2835-unicam.c | 2678 +++++++++++++++++
.../media/platform/bcm2835/vc4-regs-unicam.h | 253 ++
13 files changed, 3488 insertions(+), 211 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
create mode 100644 arch/arm/boot/dts/bcm283x-rpi-imx219.dtsi
create mode 100644 drivers/media/platform/bcm2835/Kconfig
create mode 100644 drivers/media/platform/bcm2835/Makefile
create mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c
create mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h
--
2.32.0
^ permalink raw reply
* RE: [PATCH v8 05/10] dt-bindings: clock: Add bindings for SP7021 clock driver
From: qinjian[覃健] @ 2022-01-21 8:12 UTC (permalink / raw)
To: qinjian[覃健], robh+dt@kernel.org
Cc: mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de,
maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk,
broonie@kernel.org, arnd@arndb.de, stefan.wahren@i2se.com,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
Wells Lu 呂芳騰
In-Reply-To: <504303c7cf92af8368dcda0cdde3b9c15a833418.1642751015.git.qinjian@cqplus1.com>
> Add documentation to describe Sunplus SP7021 clock driver bindings.
>
> Signed-off-by: Qin Jian <qinjian@cqplus1.com>
> ---
> Add clocks & clock-names.
> ---
Sorry, forgot update the status of this patch
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v8] arm64: dts: qcom: sc7280: Add WPSS remoteproc node
From: Rakesh Pillai @ 2022-01-21 8:00 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, swboyd
Cc: linux-arm-msm, devicetree, linux-kernel, quic_sibis,
quic_mpubbise, kuabhs, Rakesh Pillai
Add the WPSS remoteproc node in dts for
PIL loading.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Rakesh Pillai <quic_pillair@quicinc.com>
---
Changes from v7:
- Remove wpss_mem from reserved memory. Its part of board dtsi.
Changes from v6:
- Swap the oder of two properties in wpss_mem reserved memory
Changes from v5:
- Update the clock names
---
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 +++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 51 +++++++++++++++++++++++++++++++++
2 files changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index 9b991ba..ddab150 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -80,3 +80,7 @@
qcom,pre-scaling = <1 1>;
};
};
+
+&remoteproc_wpss {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 937c2e0..e7c0745 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2603,6 +2603,57 @@
status = "disabled";
};
+ remoteproc_wpss: remoteproc@8a00000 {
+ compatible = "qcom,sc7280-wpss-pil";
+ reg = <0 0x08a00000 0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
+ <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
+ <&gcc GCC_WPSS_AHB_CLK>,
+ <&gcc GCC_WPSS_RSCP_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ahb_bdg", "ahb",
+ "rscp", "xo";
+
+ power-domains = <&rpmhpd SC7280_CX>,
+ <&rpmhpd SC7280_MX>;
+ power-domain-names = "cx", "mx";
+
+ memory-region = <&wpss_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&wpss_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
+ <&pdc_reset PDC_WPSS_SYNC_RESET>;
+ reset-names = "restart", "pdc_sync";
+
+ qcom,halt-regs = <&tcsr_mutex 0x37000>;
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "wpss";
+ qcom,remote-pid = <13>;
+ };
+ };
+
dc_noc: interconnect@90e0000 {
reg = <0 0x090e0000 0 0x5080>;
compatible = "qcom,sc7280-dc-noc";
--
2.7.4
^ permalink raw reply related
* [PATCH v8 08/10] irqchip: Add Sunplus SP7021 interrupt controller driver
From: Qin Jian @ 2022-01-21 7:53 UTC (permalink / raw)
To: robh+dt
Cc: mturquette, sboyd, tglx, maz, p.zabel, linux, broonie, arnd,
stefan.wahren, linux-arm-kernel, devicetree, linux-kernel,
linux-clk, wells.lu, Qin Jian
In-Reply-To: <cover.1642751015.git.qinjian@cqplus1.com>
Add interrupt controller driver for Sunplus SP7021 SoC.
This is the interrupt controller in P-chip which collects all interrupt
sources in P-chip and routes them to parent interrupt controller in C-chip.
Signed-off-by: Qin Jian <qinjian@cqplus1.com>
---
Fix the comments from Marc.
---
MAINTAINERS | 1 +
drivers/irqchip/Kconfig | 9 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-sp7021-intc.c | 288 ++++++++++++++++++++++++++++++
4 files changed, 299 insertions(+)
create mode 100644 drivers/irqchip/irq-sp7021-intc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 6b3bbe021..febbd97bf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2665,6 +2665,7 @@ F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml
F: drivers/clk/clk-sp7021.c
+F: drivers/irqchip/irq-sp7021-intc.c
F: drivers/reset/reset-sunplus.c
F: include/dt-bindings/clock/sp-sp7021.h
F: include/dt-bindings/reset/sp-sp7021.h
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index aca7b595c..32d7a8e0c 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -602,4 +602,13 @@ config APPLE_AIC
Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
such as the M1.
+config SUNPLUS_SP7021_INTC
+ bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
+ default SOC_SP7021
+ help
+ Support for the Sunplus SP7021 Interrupt Controller IP core.
+ SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
+ chained controller, routing all interrupt source in P-Chip to
+ the primary controller on C-Chip.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index f88cbf36a..75411f654 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -116,3 +116,4 @@ obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o
obj-$(CONFIG_WPCM450_AIC) += irq-wpcm450-aic.o
obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o
obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o
+obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
diff --git a/drivers/irqchip/irq-sp7021-intc.c b/drivers/irqchip/irq-sp7021-intc.c
new file mode 100644
index 000000000..d1821a955
--- /dev/null
+++ b/drivers/irqchip/irq-sp7021-intc.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (C) Sunplus Technology Co., Ltd.
+ * All rights reserved.
+ */
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define SP_INTC_HWIRQ_MIN 0
+#define SP_INTC_HWIRQ_MAX 223
+
+#define SP_INTC_NR_IRQS (SP_INTC_HWIRQ_MAX - SP_INTC_HWIRQ_MIN + 1)
+#define SP_INTC_NR_GROUPS DIV_ROUND_UP(SP_INTC_NR_IRQS, 32)
+#define SP_INTC_REG_SIZE (SP_INTC_NR_GROUPS * 4)
+
+/* REG_GROUP_0 regs */
+#define REG_INTR_TYPE (sp_intc.g0)
+#define REG_INTR_POLARITY (REG_INTR_TYPE + SP_INTC_REG_SIZE)
+#define REG_INTR_PRIORITY (REG_INTR_POLARITY + SP_INTC_REG_SIZE)
+#define REG_INTR_MASK (REG_INTR_PRIORITY + SP_INTC_REG_SIZE)
+
+/* REG_GROUP_1 regs */
+#define REG_INTR_CLEAR (sp_intc.g1)
+#define REG_MASKED_EXT1 (REG_INTR_CLEAR + SP_INTC_REG_SIZE)
+#define REG_MASKED_EXT0 (REG_MASKED_EXT1 + SP_INTC_REG_SIZE)
+#define REG_INTR_GROUP (REG_INTR_CLEAR + 31 * 4)
+
+#define GROUP_MASK (BIT(SP_INTC_NR_GROUPS) - 1)
+#define GROUP_SHIFT_EXT1 (0)
+#define GROUP_SHIFT_EXT0 (8)
+
+/*
+ * When GPIO_INT0~7 set to edge trigger, doesn't work properly.
+ * WORKAROUND: change it to level trigger, and toggle the polarity
+ * at ACK/Handler to make the HW work.
+ */
+#define GPIO_INT0_HWIRQ 120
+#define GPIO_INT7_HWIRQ 127
+#define IS_GPIO_INT(irq) \
+({ \
+ u32 i = irq; \
+ (i >= GPIO_INT0_HWIRQ) && (i <= GPIO_INT7_HWIRQ); \
+})
+
+/* index of states */
+enum {
+ _IS_EDGE = 0,
+ _IS_LOW,
+ _IS_ACTIVE
+};
+
+#define STATE_BIT(irq, idx) (((irq) - GPIO_INT0_HWIRQ) * 3 + (idx))
+#define ASSIGN_STATE(irq, idx, v) assign_bit(STATE_BIT(irq, idx), sp_intc.states, v)
+#define TEST_STATE(irq, idx) test_bit(STATE_BIT(irq, idx), sp_intc.states)
+
+static struct sp_intctl {
+ /*
+ * REG_GROUP_0: include type/polarity/priority/mask regs.
+ * REG_GROUP_1: include clear/masked_ext0/masked_ext1/group regs.
+ */
+ void __iomem *g0; // REG_GROUP_0 base
+ void __iomem *g1; // REG_GROUP_1 base
+
+ struct irq_domain *domain;
+ raw_spinlock_t lock;
+
+ /*
+ * store GPIO_INT states
+ * each interrupt has 3 states: is_edge, is_low, is_active
+ */
+ DECLARE_BITMAP(states, (GPIO_INT7_HWIRQ - GPIO_INT0_HWIRQ + 1) * 3);
+} sp_intc;
+
+static struct irq_chip sp_intc_chip;
+
+static void sp_intc_assign_bit(u32 hwirq, void __iomem *base, bool value)
+{
+ u32 offset, mask;
+ unsigned long flags;
+ void __iomem *reg;
+
+ offset = (hwirq / 32) * 4;
+ reg = base + offset;
+
+ raw_spin_lock_irqsave(&sp_intc.lock, flags);
+ mask = readl_relaxed(reg);
+ if (value)
+ mask |= BIT(hwirq % 32);
+ else
+ mask &= ~BIT(hwirq % 32);
+ writel_relaxed(mask, reg);
+ raw_spin_unlock_irqrestore(&sp_intc.lock, flags);
+}
+
+static void sp_intc_ack_irq(struct irq_data *d)
+{
+ u32 hwirq = d->hwirq;
+
+ if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_EDGE))) { // WORKAROUND
+ sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, !TEST_STATE(hwirq, _IS_LOW));
+ ASSIGN_STATE(hwirq, _IS_ACTIVE, true);
+ }
+
+ sp_intc_assign_bit(hwirq, REG_INTR_CLEAR, 1);
+}
+
+static void sp_intc_mask_irq(struct irq_data *d)
+{
+ sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 0);
+}
+
+static void sp_intc_unmask_irq(struct irq_data *d)
+{
+ sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 1);
+}
+
+static int sp_intc_set_type(struct irq_data *d, unsigned int type)
+{
+ u32 hwirq = d->hwirq;
+ bool is_edge = !(type & IRQ_TYPE_LEVEL_MASK);
+ bool is_low = (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING);
+
+ irq_set_handler_locked(d, is_edge ? handle_edge_irq : handle_level_irq);
+
+ if (unlikely(IS_GPIO_INT(hwirq) && is_edge)) { // WORKAROUND
+ /* store states */
+ ASSIGN_STATE(hwirq, _IS_EDGE, is_edge);
+ ASSIGN_STATE(hwirq, _IS_LOW, is_low);
+ ASSIGN_STATE(hwirq, _IS_ACTIVE, false);
+ /* change to level */
+ is_edge = false;
+ }
+
+ sp_intc_assign_bit(hwirq, REG_INTR_TYPE, is_edge);
+ sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, is_low);
+
+ return 0;
+}
+
+static int sp_intc_get_ext_irq(int ext_num)
+{
+ void __iomem *base = ext_num ? REG_MASKED_EXT1 : REG_MASKED_EXT0;
+ u32 shift = ext_num ? GROUP_SHIFT_EXT1 : GROUP_SHIFT_EXT0;
+ u32 groups;
+ u32 pending_group;
+ u32 group;
+ u32 pending_irq;
+
+ groups = readl_relaxed(REG_INTR_GROUP);
+ pending_group = (groups >> shift) & GROUP_MASK;
+ if (!pending_group)
+ return -1;
+
+ group = fls(pending_group) - 1;
+ pending_irq = readl_relaxed(base + group * 4);
+ if (!pending_irq)
+ return -1;
+
+ return (group * 32) + fls(pending_irq) - 1;
+}
+
+static void sp_intc_handle_ext_cascaded(struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ int ext_num = (int)irq_desc_get_handler_data(desc);
+ int hwirq;
+
+ chained_irq_enter(chip, desc);
+
+ while ((hwirq = sp_intc_get_ext_irq(ext_num)) >= 0) {
+ if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_ACTIVE))) { // WORKAROUND
+ ASSIGN_STATE(hwirq, _IS_ACTIVE, false);
+ sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, TEST_STATE(hwirq, _IS_LOW));
+ } else {
+ generic_handle_domain_irq(sp_intc.domain, hwirq);
+ }
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+#ifdef CONFIG_SMP
+static int sp_intc_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
+{
+ return -EINVAL;
+}
+#endif
+
+static struct irq_chip sp_intc_chip = {
+ .name = "sp_intc",
+ .irq_ack = sp_intc_ack_irq,
+ .irq_mask = sp_intc_mask_irq,
+ .irq_unmask = sp_intc_unmask_irq,
+ .irq_set_type = sp_intc_set_type,
+#ifdef CONFIG_SMP
+ .irq_set_affinity = sp_intc_set_affinity,
+#endif
+};
+
+static int sp_intc_irq_domain_map(struct irq_domain *domain,
+ unsigned int irq, irq_hw_number_t hwirq)
+{
+ irq_set_chip_and_handler(irq, &sp_intc_chip, handle_level_irq);
+ irq_set_chip_data(irq, &sp_intc_chip);
+ irq_set_noprobe(irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops sp_intc_dm_ops = {
+ .xlate = irq_domain_xlate_twocell,
+ .map = sp_intc_irq_domain_map,
+};
+
+static int sp_intc_irq_map(struct device_node *node, int i)
+{
+ unsigned int irq;
+
+ irq = irq_of_parse_and_map(node, i);
+ if (!irq)
+ return -ENOENT;
+
+ irq_set_chained_handler_and_data(irq, sp_intc_handle_ext_cascaded, (void *)i);
+
+ return 0;
+}
+
+static int __init sp_intc_init_dt(struct device_node *node, struct device_node *parent)
+{
+ int i, ret;
+
+ sp_intc.g0 = of_iomap(node, 0);
+ if (!sp_intc.g0)
+ return -ENXIO;
+
+ sp_intc.g1 = of_iomap(node, 1);
+ if (!sp_intc.g1) {
+ ret = -ENXIO;
+ goto out_unmap0;
+ }
+
+ ret = sp_intc_irq_map(node, 0); // EXT_INT0
+ if (ret)
+ goto out_unmap1;
+
+ ret = sp_intc_irq_map(node, 1); // EXT_INT1
+ if (ret)
+ goto out_unmap1;
+
+ /* initial regs */
+ for (i = 0; i < SP_INTC_NR_GROUPS; i++) {
+ /* all mask */
+ writel_relaxed(0, REG_INTR_MASK + i * 4);
+ /* all edge */
+ writel_relaxed(~0, REG_INTR_TYPE + i * 4);
+ /* all high-active */
+ writel_relaxed(0, REG_INTR_POLARITY + i * 4);
+ /* all EXT_INT0 */
+ writel_relaxed(~0, REG_INTR_PRIORITY + i * 4);
+ /* all clear */
+ writel_relaxed(~0, REG_INTR_CLEAR + i * 4);
+ }
+
+ sp_intc.domain = irq_domain_add_linear(node, SP_INTC_NR_IRQS,
+ &sp_intc_dm_ops, &sp_intc);
+ if (!sp_intc.domain) {
+ ret = -ENOMEM;
+ goto out_unmap1;
+ }
+
+ raw_spin_lock_init(&sp_intc.lock);
+
+ return 0;
+
+out_unmap1:
+ iounmap(sp_intc.g1);
+out_unmap0:
+ iounmap(sp_intc.g0);
+
+ return ret;
+}
+
+IRQCHIP_DECLARE(sp_intc, "sunplus,sp7021-intc", sp_intc_init_dt);
--
2.33.1
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