* Re: [RFC PATCH v2 6/7] media: imx219: Add support for multiplexed streams
From: Laurent Pinchart @ 2022-01-21 23:34 UTC (permalink / raw)
To: Jean-Michel Hautbois
Cc: dave.stevenson, devicetree, kernel-list, linux-arm-kernel,
linux-kernel, linux-media, linux-rpi-kernel, lukasz, mchehab,
naush, robh, tomi.valkeinen
In-Reply-To: <20220121081810.155500-7-jeanmichel.hautbois@ideasonboard.com>
Hi Jean-Michel,
Thank you for the patch.
On Fri, Jan 21, 2022 at 09:18:09AM +0100, Jean-Michel Hautbois wrote:
> As of now, imx219 was not supporting anything more than one stream. Add
> support for embedded data, based on linux-rpi kernel, and make it work
> with multiplexed streams. We have only one source pad with two streams:
> stream 0 is the image, and stream 1 is the embedded data.
>
> Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
>
> ---
> in v2: modified the get_format_pad function as it was not correctly
> propagating the format in case of sensor flips.
> ---
> drivers/media/i2c/imx219.c | 452 ++++++++++++++++++++-----------------
This is too big, it bundles multiple changes together. It should be
split in multiple patches.
> 1 file changed, 241 insertions(+), 211 deletions(-)
>
> diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
> index e10af3f74b38..d73fe6b8b2fb 100644
> --- a/drivers/media/i2c/imx219.c
> +++ b/drivers/media/i2c/imx219.c
> @@ -118,6 +118,16 @@
> #define IMX219_PIXEL_ARRAY_WIDTH 3280U
> #define IMX219_PIXEL_ARRAY_HEIGHT 2464U
>
> +/* Embedded metadata stream structure */
> +#define IMX219_EMBEDDED_LINE_WIDTH 16384
> +#define IMX219_NUM_EMBEDDED_LINES 1
> +
> +enum pad_types {
> + IMAGE_PAD,
> + METADATA_PAD,
> + NUM_PADS
> +};
No used.
> +
> struct imx219_reg {
> u16 address;
> u8 val;
> @@ -429,7 +439,7 @@ static const char * const imx219_supply_name[] = {
> * - v flip
> * - h&v flips
> */
> -static const u32 codes[] = {
> +static const u32 imx219_mbus_formats[] = {
For instance renaming this array should go in a patch of its own.
> MEDIA_BUS_FMT_SRGGB10_1X10,
> MEDIA_BUS_FMT_SGRBG10_1X10,
> MEDIA_BUS_FMT_SGBRG10_1X10,
> @@ -655,62 +665,17 @@ static u32 imx219_get_format_code(struct imx219 *imx219, u32 code)
>
> lockdep_assert_held(&imx219->mutex);
>
> - for (i = 0; i < ARRAY_SIZE(codes); i++)
> - if (codes[i] == code)
> + for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); i++)
> + if (imx219_mbus_formats[i] == code)
> break;
>
> - if (i >= ARRAY_SIZE(codes))
> + if (i >= ARRAY_SIZE(imx219_mbus_formats))
> i = 0;
>
> i = (i & ~3) | (imx219->vflip->val ? 2 : 0) |
> (imx219->hflip->val ? 1 : 0);
>
> - return codes[i];
> -}
> -
> -static void imx219_set_default_format(struct imx219 *imx219)
> -{
> - struct v4l2_mbus_framefmt *fmt;
> -
> - fmt = &imx219->fmt;
> - fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
> - fmt->colorspace = V4L2_COLORSPACE_SRGB;
> - fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
> - fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
> - fmt->colorspace,
> - fmt->ycbcr_enc);
> - fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
> - fmt->width = supported_modes[0].width;
> - fmt->height = supported_modes[0].height;
> - fmt->field = V4L2_FIELD_NONE;
> -}
> -
> -static int imx219_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
So should switching from open to init_cfg. Same thing for adding support
for the V4L2 subdev active state (v4l2_subdev_init_finalize() and the
corresponding changes in the get/set format handlers). This is mainline,
not a BSP, patches must be reviewable.
> -{
> - struct imx219 *imx219 = to_imx219(sd);
> - struct v4l2_mbus_framefmt *try_fmt =
> - v4l2_subdev_get_try_format(sd, fh->state, 0);
> - struct v4l2_rect *try_crop;
> -
> - mutex_lock(&imx219->mutex);
> -
> - /* Initialize try_fmt */
> - try_fmt->width = supported_modes[0].width;
> - try_fmt->height = supported_modes[0].height;
> - try_fmt->code = imx219_get_format_code(imx219,
> - MEDIA_BUS_FMT_SRGGB10_1X10);
> - try_fmt->field = V4L2_FIELD_NONE;
> -
> - /* Initialize try_crop rectangle. */
> - try_crop = v4l2_subdev_get_try_crop(sd, fh->state, 0);
> - try_crop->top = IMX219_PIXEL_ARRAY_TOP;
> - try_crop->left = IMX219_PIXEL_ARRAY_LEFT;
> - try_crop->width = IMX219_PIXEL_ARRAY_WIDTH;
> - try_crop->height = IMX219_PIXEL_ARRAY_HEIGHT;
> -
> - mutex_unlock(&imx219->mutex);
> -
> - return 0;
> + return imx219_mbus_formats[i];
> }
>
> static int imx219_set_ctrl(struct v4l2_ctrl *ctrl)
> @@ -802,98 +767,148 @@ static const struct v4l2_ctrl_ops imx219_ctrl_ops = {
> .s_ctrl = imx219_set_ctrl,
> };
>
> -static int imx219_enum_mbus_code(struct v4l2_subdev *sd,
> - struct v4l2_subdev_state *sd_state,
> - struct v4l2_subdev_mbus_code_enum *code)
> +static void imx219_init_formats(struct v4l2_subdev_state *state)
> {
> - struct imx219 *imx219 = to_imx219(sd);
> + struct v4l2_mbus_framefmt *format;
> +
> + format = v4l2_state_get_stream_format(state, 0, 0);
> + format->code = imx219_mbus_formats[0];
> + format->width = supported_modes[0].width;
> + format->height = supported_modes[0].height;
> + format->field = V4L2_FIELD_NONE;
> + format->colorspace = V4L2_COLORSPACE_RAW;
> +
> + if (state->routing.routes[1].flags & V4L2_SUBDEV_ROUTE_FL_ACTIVE) {
> + format = v4l2_state_get_stream_format(state, 0, 1);
> + format->code = MEDIA_BUS_FMT_METADATA_8;
> + format->width = IMX219_EMBEDDED_LINE_WIDTH;
> + format->height = 1;
> + format->field = V4L2_FIELD_NONE;
> + format->colorspace = V4L2_COLORSPACE_DEFAULT;
> + }
> +}
>
> - if (code->index >= (ARRAY_SIZE(codes) / 4))
> - return -EINVAL;
> +static int _imx219_set_routing(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state)
> +{
> + struct v4l2_subdev_route routes[] = {
> + {
> + .source_pad = 0,
> + .source_stream = 0,
> + .flags = V4L2_SUBDEV_ROUTE_FL_IMMUTABLE |
> + V4L2_SUBDEV_ROUTE_FL_SOURCE |
> + V4L2_SUBDEV_ROUTE_FL_ACTIVE,
> + },
> + {
> + .source_pad = 0,
> + .source_stream = 1,
> + .flags = V4L2_SUBDEV_ROUTE_FL_SOURCE |
> + V4L2_SUBDEV_ROUTE_FL_ACTIVE,
> + }
> + };
>
> - mutex_lock(&imx219->mutex);
> - code->code = imx219_get_format_code(imx219, codes[code->index * 4]);
> - mutex_unlock(&imx219->mutex);
> + struct v4l2_subdev_krouting routing = {
> + .num_routes = ARRAY_SIZE(routes),
> + .routes = routes,
> + };
> +
> + int ret;
> +
> + ret = v4l2_subdev_set_routing(sd, state, &routing);
> + if (ret)
> + return ret;
> +
> + imx219_init_formats(state);
>
> return 0;
> }
>
> -static int imx219_enum_frame_size(struct v4l2_subdev *sd,
> - struct v4l2_subdev_state *sd_state,
> - struct v4l2_subdev_frame_size_enum *fse)
> +static int imx219_set_routing(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state,
> + enum v4l2_subdev_format_whence which,
> + struct v4l2_subdev_krouting *routing)
> {
> - struct imx219 *imx219 = to_imx219(sd);
> - u32 code;
> + int ret;
>
> - if (fse->index >= ARRAY_SIZE(supported_modes))
> + if (routing->num_routes == 0 || routing->num_routes > 2)
> return -EINVAL;
>
> - mutex_lock(&imx219->mutex);
> - code = imx219_get_format_code(imx219, fse->code);
> - mutex_unlock(&imx219->mutex);
> - if (fse->code != code)
> - return -EINVAL;
> + v4l2_subdev_lock_state(state);
>
> - fse->min_width = supported_modes[fse->index].width;
> - fse->max_width = fse->min_width;
> - fse->min_height = supported_modes[fse->index].height;
> - fse->max_height = fse->min_height;
> + ret = _imx219_set_routing(sd, state);
>
> - return 0;
> + v4l2_subdev_unlock_state(state);
> +
> + return ret;
> }
>
> -static void imx219_reset_colorspace(struct v4l2_mbus_framefmt *fmt)
> +static int imx219_init_cfg(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state)
> {
> - fmt->colorspace = V4L2_COLORSPACE_SRGB;
> - fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
> - fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
> - fmt->colorspace,
> - fmt->ycbcr_enc);
> - fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
> + int ret;
> +
> + v4l2_subdev_lock_state(state);
> +
> + ret = _imx219_set_routing(sd, state);
> +
> + v4l2_subdev_unlock_state(state);
> +
> + return ret;
> }
>
> -static void imx219_update_pad_format(struct imx219 *imx219,
> - const struct imx219_mode *mode,
> - struct v4l2_subdev_format *fmt)
> +static int imx219_enum_mbus_code(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_subdev_mbus_code_enum *code)
> {
> - fmt->format.width = mode->width;
> - fmt->format.height = mode->height;
> - fmt->format.field = V4L2_FIELD_NONE;
> - imx219_reset_colorspace(&fmt->format);
> + if (code->index >= ARRAY_SIZE(imx219_mbus_formats))
> + return -EINVAL;
> +
> + code->code = imx219_mbus_formats[code->index];
> +
> + return 0;
> }
>
> -static int __imx219_get_pad_format(struct imx219 *imx219,
> - struct v4l2_subdev_state *sd_state,
> - struct v4l2_subdev_format *fmt)
> +static int imx219_enum_frame_size(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_subdev_frame_size_enum *fse)
> {
> - if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
> - struct v4l2_mbus_framefmt *try_fmt =
> - v4l2_subdev_get_try_format(&imx219->sd, sd_state,
> - fmt->pad);
> - /* update the code which could change due to vflip or hflip: */
> - try_fmt->code = imx219_get_format_code(imx219, try_fmt->code);
> - fmt->format = *try_fmt;
> + unsigned int i;
> +
> + if (fse->stream == 0) {
> + for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); ++i) {
> + if (imx219_mbus_formats[i] == fse->code)
> + break;
> + }
> +
> + if (i == ARRAY_SIZE(imx219_mbus_formats))
> + return -EINVAL;
> +
> + if (fse->index >= ARRAY_SIZE(supported_modes))
> + return -EINVAL;
> +
> + fse->min_width = supported_modes[fse->index].width;
> + fse->max_width = fse->min_width;
> + fse->max_height = supported_modes[fse->index].height;
> + fse->min_height = fse->max_height;
> } else {
> - imx219_update_pad_format(imx219, imx219->mode, fmt);
> - fmt->format.code = imx219_get_format_code(imx219,
> - imx219->fmt.code);
> + if (fse->code != MEDIA_BUS_FMT_METADATA_8)
> + return -EINVAL;
> +
> + fse->min_width = IMX219_EMBEDDED_LINE_WIDTH;
> + fse->max_width = fse->min_width;
> + fse->min_height = IMX219_NUM_EMBEDDED_LINES;
> + fse->max_height = fse->min_height;
> }
>
> return 0;
> }
>
> -static int imx219_get_pad_format(struct v4l2_subdev *sd,
> - struct v4l2_subdev_state *sd_state,
> - struct v4l2_subdev_format *fmt)
> +static void imx219_update_metadata_pad_format(struct v4l2_subdev_format *fmt)
> {
> - struct imx219 *imx219 = to_imx219(sd);
> - int ret;
> -
> - mutex_lock(&imx219->mutex);
> - ret = __imx219_get_pad_format(imx219, sd_state, fmt);
> - mutex_unlock(&imx219->mutex);
> -
> - return ret;
> + fmt->format.width = IMX219_EMBEDDED_LINE_WIDTH;
> + fmt->format.height = IMX219_NUM_EMBEDDED_LINES;
> + fmt->format.code = MEDIA_BUS_FMT_METADATA_8;
> + fmt->format.field = V4L2_FIELD_NONE;
> }
>
> static int imx219_set_pad_format(struct v4l2_subdev *sd,
> @@ -901,82 +916,91 @@ static int imx219_set_pad_format(struct v4l2_subdev *sd,
> struct v4l2_subdev_format *fmt)
> {
> struct imx219 *imx219 = to_imx219(sd);
> + struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
> const struct imx219_mode *mode;
> - struct v4l2_mbus_framefmt *framefmt;
> - int exposure_max, exposure_def, hblank;
> + struct v4l2_mbus_framefmt *format;
> unsigned int i;
> + int ret = 0;
> + int exposure_max, exposure_def, hblank;
>
> - mutex_lock(&imx219->mutex);
> + if (fmt->pad != 0) {
> + dev_err(&client->dev, "%s Could not get pad %d\n", __func__,
> + fmt->pad);
> + return -EINVAL;
> + }
>
> - for (i = 0; i < ARRAY_SIZE(codes); i++)
> - if (codes[i] == fmt->format.code)
> + if (fmt->stream == 1) {
> + /* Only one embedded data mode is supported */
> + imx219_update_metadata_pad_format(fmt);
> + return 0;
> + }
> +
> + if (fmt->stream != 0)
> + return -EINVAL;
> +
> + /*
> + * Validate the media bus code, defaulting to the first one if the
> + * requested code isn't supported.
> + */
> + for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); ++i) {
> + if (imx219_mbus_formats[i] == fmt->format.code)
> break;
> - if (i >= ARRAY_SIZE(codes))
> - i = 0;
> + }
>
> - /* Bayer order varies with flips */
> - fmt->format.code = imx219_get_format_code(imx219, codes[i]);
> + if (i >= ARRAY_SIZE(imx219_mbus_formats))
> + i = 0;
>
> mode = v4l2_find_nearest_size(supported_modes,
> ARRAY_SIZE(supported_modes),
> width, height,
> - fmt->format.width, fmt->format.height);
> - imx219_update_pad_format(imx219, mode, fmt);
> - if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
> - framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
> - *framefmt = fmt->format;
> - } else if (imx219->mode != mode ||
> - imx219->fmt.code != fmt->format.code) {
> - imx219->fmt = fmt->format;
> - imx219->mode = mode;
> - /* Update limits and set FPS to default */
> - __v4l2_ctrl_modify_range(imx219->vblank, IMX219_VBLANK_MIN,
> - IMX219_VTS_MAX - mode->height, 1,
> - mode->vts_def - mode->height);
> - __v4l2_ctrl_s_ctrl(imx219->vblank,
> - mode->vts_def - mode->height);
> - /* Update max exposure while meeting expected vblanking */
> - exposure_max = mode->vts_def - 4;
> - exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
> - exposure_max : IMX219_EXPOSURE_DEFAULT;
> - __v4l2_ctrl_modify_range(imx219->exposure,
> - imx219->exposure->minimum,
> - exposure_max, imx219->exposure->step,
> - exposure_def);
> - /*
> - * Currently PPL is fixed to IMX219_PPL_DEFAULT, so hblank
> - * depends on mode->width only, and is not changeble in any
> - * way other than changing the mode.
> - */
> - hblank = IMX219_PPL_DEFAULT - mode->width;
> - __v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank, 1,
> - hblank);
> - }
> + fmt->format.width,
> + fmt->format.height);
>
> - mutex_unlock(&imx219->mutex);
> + v4l2_subdev_lock_state(sd_state);
>
> - return 0;
> -}
> + /* Update the stored format and return it. */
> + format = v4l2_state_get_stream_format(sd_state, fmt->pad, fmt->stream);
>
> -static int imx219_set_framefmt(struct imx219 *imx219)
> -{
> - switch (imx219->fmt.code) {
> - case MEDIA_BUS_FMT_SRGGB8_1X8:
> - case MEDIA_BUS_FMT_SGRBG8_1X8:
> - case MEDIA_BUS_FMT_SGBRG8_1X8:
> - case MEDIA_BUS_FMT_SBGGR8_1X8:
> - return imx219_write_regs(imx219, raw8_framefmt_regs,
> - ARRAY_SIZE(raw8_framefmt_regs));
> -
> - case MEDIA_BUS_FMT_SRGGB10_1X10:
> - case MEDIA_BUS_FMT_SGRBG10_1X10:
> - case MEDIA_BUS_FMT_SGBRG10_1X10:
> - case MEDIA_BUS_FMT_SBGGR10_1X10:
> - return imx219_write_regs(imx219, raw10_framefmt_regs,
> - ARRAY_SIZE(raw10_framefmt_regs));
> + if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE && imx219->streaming) {
> + ret = -EBUSY;
> + goto done;
> }
>
> - return -EINVAL;
> + /* Bayer order varies with flips */
> + fmt->format.code = imx219_get_format_code(imx219, imx219_mbus_formats[i]);
> + fmt->format = *format;
> +
> + /* Update limits and set FPS to default */
> + __v4l2_ctrl_modify_range(imx219->vblank,
> + IMX219_VBLANK_MIN,
> + IMX219_VTS_MAX - mode->height,
> + 1,
> + mode->vts_def - mode->height);
> + __v4l2_ctrl_s_ctrl(imx219->vblank, mode->vts_def - mode->height);
> + /*
> + * Update max exposure while meeting
> + * expected vblanking
> + */
> + exposure_max = mode->vts_def - 4;
> + exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
> + exposure_max : IMX219_EXPOSURE_DEFAULT;
> + __v4l2_ctrl_modify_range(imx219->exposure,
> + imx219->exposure->minimum,
> + exposure_max,
> + imx219->exposure->step,
> + exposure_def);
> + /*
> + * Currently PPL is fixed to IMX219_PPL_DEFAULT, so
> + * hblank depends on mode->width only, and is not
> + * changeble in any way other than changing the mode.
> + */
> + hblank = IMX219_PPL_DEFAULT - mode->width;
> + __v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank, 1, hblank);
> +
> +done:
> + v4l2_subdev_unlock_state(sd_state);
> +
> + return ret;
> }
>
> static const struct v4l2_rect *
> @@ -1037,9 +1061,11 @@ static int imx219_start_streaming(struct imx219 *imx219)
> const struct imx219_reg_list *reg_list;
> int ret;
>
> - ret = pm_runtime_resume_and_get(&client->dev);
> - if (ret < 0)
> + ret = pm_runtime_get_sync(&client->dev);
> + if (ret < 0) {
> + pm_runtime_put_noidle(&client->dev);
> return ret;
> + }
>
> /* Apply default values of current mode */
> reg_list = &imx219->mode->reg_list;
> @@ -1049,13 +1075,6 @@ static int imx219_start_streaming(struct imx219 *imx219)
> goto err_rpm_put;
> }
>
> - ret = imx219_set_framefmt(imx219);
> - if (ret) {
> - dev_err(&client->dev, "%s failed to set frame format: %d\n",
> - __func__, ret);
> - goto err_rpm_put;
> - }
> -
> /* Apply customized values from user */
> ret = __v4l2_ctrl_handler_setup(imx219->sd.ctrl_handler);
> if (ret)
> @@ -1133,21 +1152,22 @@ static int imx219_set_stream(struct v4l2_subdev *sd, int enable)
> /* Power/clock management functions */
> static int imx219_power_on(struct device *dev)
> {
> - struct v4l2_subdev *sd = dev_get_drvdata(dev);
> + struct i2c_client *client = to_i2c_client(dev);
> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> struct imx219 *imx219 = to_imx219(sd);
> int ret;
>
> ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES,
> imx219->supplies);
> if (ret) {
> - dev_err(dev, "%s: failed to enable regulators\n",
> + dev_err(&client->dev, "%s: failed to enable regulators\n",
> __func__);
> return ret;
> }
>
> ret = clk_prepare_enable(imx219->xclk);
> if (ret) {
> - dev_err(dev, "%s: failed to enable clock\n",
> + dev_err(&client->dev, "%s: failed to enable clock\n",
> __func__);
> goto reg_off;
> }
> @@ -1166,7 +1186,8 @@ static int imx219_power_on(struct device *dev)
>
> static int imx219_power_off(struct device *dev)
> {
> - struct v4l2_subdev *sd = dev_get_drvdata(dev);
> + struct i2c_client *client = to_i2c_client(dev);
> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> struct imx219 *imx219 = to_imx219(sd);
>
> gpiod_set_value_cansleep(imx219->reset_gpio, 0);
> @@ -1178,7 +1199,8 @@ static int imx219_power_off(struct device *dev)
>
> static int __maybe_unused imx219_suspend(struct device *dev)
> {
> - struct v4l2_subdev *sd = dev_get_drvdata(dev);
> + struct i2c_client *client = to_i2c_client(dev);
> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> struct imx219 *imx219 = to_imx219(sd);
>
> if (imx219->streaming)
> @@ -1189,7 +1211,8 @@ static int __maybe_unused imx219_suspend(struct device *dev)
>
> static int __maybe_unused imx219_resume(struct device *dev)
> {
> - struct v4l2_subdev *sd = dev_get_drvdata(dev);
> + struct i2c_client *client = to_i2c_client(dev);
> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> struct imx219 *imx219 = to_imx219(sd);
> int ret;
>
> @@ -1255,11 +1278,13 @@ static const struct v4l2_subdev_video_ops imx219_video_ops = {
> };
>
> static const struct v4l2_subdev_pad_ops imx219_pad_ops = {
> - .enum_mbus_code = imx219_enum_mbus_code,
> - .get_fmt = imx219_get_pad_format,
> - .set_fmt = imx219_set_pad_format,
> - .get_selection = imx219_get_selection,
> - .enum_frame_size = imx219_enum_frame_size,
> + .init_cfg = imx219_init_cfg,
> + .enum_mbus_code = imx219_enum_mbus_code,
> + .get_fmt = v4l2_subdev_get_fmt,
> + .set_fmt = imx219_set_pad_format,
> + .get_selection = imx219_get_selection,
> + .set_routing = imx219_set_routing,
> + .enum_frame_size = imx219_enum_frame_size,
> };
>
> static const struct v4l2_subdev_ops imx219_subdev_ops = {
> @@ -1268,10 +1293,6 @@ static const struct v4l2_subdev_ops imx219_subdev_ops = {
> .pad = &imx219_pad_ops,
> };
>
> -static const struct v4l2_subdev_internal_ops imx219_internal_ops = {
> - .open = imx219_open,
> -};
> -
> /* Initialize control handlers */
> static int imx219_init_controls(struct imx219 *imx219)
> {
> @@ -1446,6 +1467,7 @@ static int imx219_check_hwcfg(struct device *dev)
> static int imx219_probe(struct i2c_client *client)
> {
> struct device *dev = &client->dev;
> + struct v4l2_subdev *sd;
> struct imx219 *imx219;
> int ret;
>
> @@ -1453,7 +1475,8 @@ static int imx219_probe(struct i2c_client *client)
> if (!imx219)
> return -ENOMEM;
>
> - v4l2_i2c_subdev_init(&imx219->sd, client, &imx219_subdev_ops);
> + sd = &imx219->sd;
> + v4l2_i2c_subdev_init(sd, client, &imx219_subdev_ops);
>
> /* Check the hardware configuration in device tree */
> if (imx219_check_hwcfg(dev))
> @@ -1520,27 +1543,29 @@ static int imx219_probe(struct i2c_client *client)
> goto error_power_off;
>
> /* Initialize subdev */
> - imx219->sd.internal_ops = &imx219_internal_ops;
> - imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
> - V4L2_SUBDEV_FL_HAS_EVENTS;
> - imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
> + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
> + V4L2_SUBDEV_FL_HAS_EVENTS |
> + V4L2_SUBDEV_FL_MULTIPLEXED;
>
> - /* Initialize source pad */
> + /* Initialize the media entity. */
> imx219->pad.flags = MEDIA_PAD_FL_SOURCE;
> -
> - /* Initialize default format */
> - imx219_set_default_format(imx219);
> -
> - ret = media_entity_pads_init(&imx219->sd.entity, 1, &imx219->pad);
> + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
> + ret = media_entity_pads_init(&sd->entity, 1, &imx219->pad);
> if (ret) {
> dev_err(dev, "failed to init entity pads: %d\n", ret);
> goto error_handler_free;
> }
>
> - ret = v4l2_async_register_subdev_sensor(&imx219->sd);
> + ret = v4l2_subdev_init_finalize(sd);
> + if (ret) {
> + dev_err(dev, "failed to finalize sensor init: %d\n", ret);
> + goto error_media_entity;
> + }
> +
> + ret = v4l2_async_register_subdev_sensor(sd);
> if (ret < 0) {
> dev_err(dev, "failed to register sensor sub-device: %d\n", ret);
> - goto error_media_entity;
> + goto error_free_state;
> }
>
> /* Enable runtime PM and turn off the device */
> @@ -1550,6 +1575,8 @@ static int imx219_probe(struct i2c_client *client)
>
> return 0;
>
> +error_free_state:
> + v4l2_subdev_cleanup(sd);
> error_media_entity:
> media_entity_cleanup(&imx219->sd.entity);
>
> @@ -1568,6 +1595,9 @@ static int imx219_remove(struct i2c_client *client)
> struct imx219 *imx219 = to_imx219(sd);
>
> v4l2_async_unregister_subdev(sd);
> +
> + v4l2_subdev_cleanup(sd);
> +
> media_entity_cleanup(&sd->entity);
> imx219_free_controls(imx219);
>
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [v2 2/3] dt-bindings: ARM: Mediatek: Remove vppsys in MT8195 clock document
From: Rob Herring @ 2022-01-21 23:35 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, linux-arm-kernel,
linux-kernel, linux-mediatek, linux-clk, devicetree,
srv_heupstream, Project_Global_Chrome_Upstream_Group
In-Reply-To: <20220110005902.27148-3-chun-jie.chen@mediatek.com>
On Mon, Jan 10, 2022 at 08:59:01AM +0800, Chun-Jie Chen wrote:
> vppsys0 and vppsys1 sub-system are both integrated with mmsys driver,
> should be describe in mediatek,mmsys.yaml
Driver partitioning is not a reason to change the DT. This needs a
better description answering why you are doing this and what are the
implications (is this breaking the ABI?).
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> .../arm/mediatek/mediatek,mt8195-clock.yaml | 16 ----------------
> 1 file changed, 16 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> index 17fcbb45d121..d62d60181147 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> @@ -28,11 +28,9 @@ properties:
> - mediatek,mt8195-imp_iic_wrap_s
> - mediatek,mt8195-imp_iic_wrap_w
> - mediatek,mt8195-mfgcfg
> - - mediatek,mt8195-vppsys0
> - mediatek,mt8195-wpesys
> - mediatek,mt8195-wpesys_vpp0
> - mediatek,mt8195-wpesys_vpp1
> - - mediatek,mt8195-vppsys1
> - mediatek,mt8195-imgsys
> - mediatek,mt8195-imgsys1_dip_top
> - mediatek,mt8195-imgsys1_dip_nr
> @@ -92,13 +90,6 @@ examples:
> #clock-cells = <1>;
> };
>
> - - |
> - vppsys0: clock-controller@14000000 {
> - compatible = "mediatek,mt8195-vppsys0";
> - reg = <0x14000000 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - |
> wpesys: clock-controller@14e00000 {
> compatible = "mediatek,mt8195-wpesys";
> @@ -120,13 +111,6 @@ examples:
> #clock-cells = <1>;
> };
>
> - - |
> - vppsys1: clock-controller@14f00000 {
> - compatible = "mediatek,mt8195-vppsys1";
> - reg = <0x14f00000 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - |
> imgsys: clock-controller@15000000 {
> compatible = "mediatek,mt8195-imgsys";
> --
> 2.18.0
>
>
^ permalink raw reply
* Re: [PATCH v1 1/2] dt-bindings: iio: adc: Add compatible for Mediatek MT8186
From: Rob Herring @ 2022-01-21 23:38 UTC (permalink / raw)
To: Guodong Liu
Cc: linux-kernel, Project_Global_Chrome_Upstream_Group, Rob Herring,
linux-arm-kernel, Zhiyong Tao, linux-iio, Jonathan Cameron,
linux-mediatek, Lars-Peter Clausen, Matthias Brugger, devicetree
In-Reply-To: <20220110084841.575-1-guodong.liu@mediatek.com>
On Mon, 10 Jan 2022 16:48:40 +0800, Guodong Liu wrote:
> This commit adds dt-binding documentation of auxadc for Mediatek MT8186 SoC
> Platform.
>
> Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
> ---
> .../devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH 0/2] Add QCOM TCSR driver
From: Ansuel Smith @ 2022-01-22 0:16 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Ansuel Smith,
linux-arm-msm, devicetree, linux-kernel
This is another try of the long gone TCSR driver needed for ipq8064 and
now also ipq4019. The first (and unique) proposal for this is back in
the 2015. After that only part of this got merged, to be specific a
variant of this got merged to support gsbi driver on ipq8064.
All the "configuration" part was never merged and without this ipq8064
SoC and ipq4019 SoC require custom patches to be configured correctly.
The driver itself is really simple. A syscon driver that configure the
system based on the passed bindings. All this stuff can't be moved and
handled by another driver (for example dwc3) as it's global and has to
be set only one (we have 2 dwc3 port for example)
This is necessary for some devices (especially ipq4019 based) that
require some special configuration for the internal WiFi chip memory
configuration.
Ansuel Smith (2):
dt-bindings: soc: qcom: add qcom,tcsr bindings
drivers: soc: qcom: add TCSR driver
.../bindings/soc/qcom/qcom,tcsr-ipq4019.yaml | 93 ++++++++
.../bindings/soc/qcom/qcom,tcsr-ipq8064.yaml | 47 +++++
drivers/soc/qcom/Kconfig | 8 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/qcom_tcsr.c | 198 ++++++++++++++++++
5 files changed, 347 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,tcsr-ipq4019.yaml
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,tcsr-ipq8064.yaml
create mode 100644 drivers/soc/qcom/qcom_tcsr.c
--
2.33.1
^ permalink raw reply
* [PATCH 1/2] dt-bindings: soc: qcom: add qcom,tcsr bindings
From: Ansuel Smith @ 2022-01-22 0:16 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Ansuel Smith,
linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20220122001609.15904-1-ansuelsmth@gmail.com>
Add qcom,tcsr-ipq8064 and qcom,tcsr-ipq4019 Documentation for the
tcsr present in ipq8064 and ipa4019 required to configure and
set various peripherals present in the SoC.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
.../bindings/soc/qcom/qcom,tcsr-ipq4019.yaml | 93 +++++++++++++++++++
.../bindings/soc/qcom/qcom,tcsr-ipq8064.yaml | 47 ++++++++++
2 files changed, 140 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,tcsr-ipq4019.yaml
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,tcsr-ipq8064.yaml
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,tcsr-ipq4019.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,tcsr-ipq4019.yaml
new file mode 100644
index 000000000000..3a82ccbb6588
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,tcsr-ipq4019.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/qcom/qcom,tcsr-ipq4019.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Top Control and Status Registers binding for IPQ4019
+
+maintainers:
+ - Ansuel Smith <ansuelsmth@gmail.com>
+
+description: |
+ This binding describes the Qualcomm Top Control and Status Registers, used
+ for accessing configuration and mux settings for a variety of peripherals
+ for ipq4019.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,tcsr-ipq4019
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ qcom,usb-hsphy-mode-select:
+ description: Select usb hsphy mode for ipq4019
+ enum:
+ - 'host'
+ - 'device'
+
+ qcom,ess-interface-select:
+ description: Select ess interface mode for ipq4019
+ enum:
+ - 'psgmii'
+ - 'rgmii5'
+ - 'rmii0'
+ - 'rmii1'
+ - 'rmii0_rmii1'
+ - 'rgmii4'
+
+ qcom,wifi-glb-cfg-enable-axid:
+ description: Enable AXI master bus Axid translating
+ to confirm all txn submitted by order for ipq4019
+ type: boolean
+
+ qcom,wifi-glb-cfg-socslv-mode:
+ description: Select wifi socslv mode for ipq4019
+ snoc use SNOC socslv_wxi_bvalid.
+ local use locally generate socslv_wxi_bvalid for performance.
+ enum:
+ - 'snoc'
+ - 'local'
+
+ qcom,wifi_noc_memtype_m0_m2:
+ description: Configure special wifi memory type needed for
+ some IPQ40xx devicesfor ipq4019
+ type: boolean
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ tcsr@194b000 {
+ compatible = "qcom,tcsr-ipq4019", "syscon";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = "host";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr-ipq4019", "syscon";
+ reg = <0x1949000 0x100>;
+ qcom,wifi-glb-cfg-enable-axid;
+ qcom,wifi-glb-cfg-socslv-mode = "local";
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr-ipq4019", "syscon";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = "psgmii";
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr-ipq4019", "syscon";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,tcsr-ipq8064.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,tcsr-ipq8064.yaml
new file mode 100644
index 000000000000..4ccc0bfccec5
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,tcsr-ipq8064.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/qcom/qcom,tcsr-ipq8064.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Top Control and Status Registers binding for IPQ8064
+
+maintainers:
+ - Ansuel Smith <ansuelsmth@gmail.com>
+
+description: |
+ This binding describes the Qualcomm Top Control and Status Registers, used
+ for accessing configuration and mux settings for a variety of peripherals
+ for ipq8064.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,tcsr-ipq8064
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ qcom,usb-ctrl-select:
+ description: Select usb3 ctrl type for ipq8064
+ enum:
+ - 'p0'
+ - 'p1'
+ - 'dual'
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ tcsr: syscon@1a400000 {
+ compatible = "qcom,tcsr-ipq8064", "syscon";
+ reg = <0x1a400000 0x100>;
+ qcom,usb-ctrl-select = "dual";
+ };
+
+...
--
2.33.1
^ permalink raw reply related
* [PATCH 2/2] drivers: soc: qcom: add TCSR driver
From: Ansuel Smith @ 2022-01-22 0:16 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Ansuel Smith,
linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20220122001609.15904-1-ansuelsmth@gmail.com>
Add QCOM Top Control and Status Registers driver required to control and
configure various peripherals for ipq8064 and ipq4019. This is required
to configure usb3 mode, gsbi configuration for ipq8064 and various
devices (WiFi, USB mode, WiFi memtype, ESS interface mode) for ipq4019.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/soc/qcom/Kconfig | 8 ++
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/qcom_tcsr.c | 198 +++++++++++++++++++++++++++++++++++
3 files changed, 207 insertions(+)
create mode 100644 drivers/soc/qcom/qcom_tcsr.c
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index e718b8735444..20dd341ae369 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -209,6 +209,14 @@ config QCOM_STATS
various SoC level low power modes statistics and export to debugfs
interface.
+config QCOM_TCSR
+ tristate "QCOM Top Control and Status Registers"
+ depends on ARCH_QCOM || COMPILE_TEST
+ select MFD_SYSCON
+ help
+ Say y here to enable TCSR support. The TCSR provides control
+ functions for various peripherals (USB, WiFi, ESS).
+
config QCOM_WCNSS_CTRL
tristate "Qualcomm WCNSS control driver"
depends on ARCH_QCOM || COMPILE_TEST
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 70d5de69fd7b..b17dd46ed1fa 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o
+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
diff --git a/drivers/soc/qcom/qcom_tcsr.c b/drivers/soc/qcom/qcom_tcsr.c
new file mode 100644
index 000000000000..dc80768d57c2
--- /dev/null
+++ b/drivers/soc/qcom/qcom_tcsr.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/bitfield.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+#define TCSR_USB_PORT_SEL_REG 0xb0
+#define TCSR_USB_PORT_SEL_MASK GENMASK(1, 0)
+
+#define TCSR_USB_SELECT_USB3_P0 FIELD_PREP(TCSR_USB_PORT_SEL_MASK, 0x1)
+#define TCSR_USB_SELECT_USB3_P1 FIELD_PREP(TCSR_USB_PORT_SEL_MASK, 0x2)
+#define TCSR_USB_SELECT_USB3_DUAL FIELD_PREP(TCSR_USB_PORT_SEL_MASK, 0x3)
+
+/* IPQ40xx HS PHY Mode Select */
+#define TCSR_USB_HSPHY_CONFIG_REG 0xc
+#define TCSR_USB_HSPHY_MODE_MASK BIT(21)
+#define TCSR_USB_HSPHY_MODE_HOST_MODE FIELD_PREP(TCSR_USB_HSPHY_MODE_MASK, 0x0)
+#define TCSR_USB_HSPHY_MODE_DEVICE_MODE FIELD_PREP(TCSR_USB_HSPHY_MODE_MASK, 0x1)
+
+/* IPQ40xx ess interface mode select */
+#define TCSR_ESS_INTERFACE_SEL_REG 0x0
+#define TCSR_ESS_INTERFACE_SEL_MASK GENMASK(3, 0)
+#define TCSR_ESS_PSGMII FIELD_PREP(TCSR_ESS_INTERFACE_SEL_MASK, 0x0)
+#define TCSR_ESS_PSGMII_RGMII5 FIELD_PREP(TCSR_ESS_INTERFACE_SEL_MASK, 0x1)
+#define TCSR_ESS_PSGMII_RMII0 FIELD_PREP(TCSR_ESS_INTERFACE_SEL_MASK, 0x2)
+#define TCSR_ESS_PSGMII_RMII1 FIELD_PREP(TCSR_ESS_INTERFACE_SEL_MASK, 0x4)
+#define TCSR_ESS_PSGMII_RMII0_RMII1 FIELD_PREP(TCSR_ESS_INTERFACE_SEL_MASK, 0x6)
+#define TCSR_ESS_PSGMII_RGMII4 FIELD_PREP(TCSR_ESS_INTERFACE_SEL_MASK, 0x9)
+
+/* IPQ40xx WiFi Global Config */
+#define TCSR_WIFI0_GLB_CFG_OFFSET_REG 0x0
+#define TCSR_WIFI1_GLB_CFG_OFFSET_REG 0x4
+/* Enable AXI master bus Axid translating to confirm all txn submitted by order */
+#define TCSR_WIFI_GLB_CFG_AXID_EN BIT(30)
+/* 1: use locally generate socslv_wxi_bvalid for performance.
+ * 0: use SNOC socslv_wxi_bvalid.
+ */
+#define TCSR_WIFI_GLB_CFG_SOCSLV_WXI_BVALID BIT(24)
+#define TCSR_WIFI_GLB_CFG_SOCSLV_SNOC FIELD_PREP(TCSR_WIFI_GLB_CFG_SOCSLV_WXI_BVALID, 0x0)
+#define TCSR_WIFI_GLB_CFG_SOCSLV_LOCAL FIELD_PREP(TCSR_WIFI_GLB_CFG_SOCSLV_WXI_BVALID, 0x1)
+
+/* Configure special wifi memory type needed for some IPQ40xx devices */
+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2_REG 0x4
+#define TCSR_WIFI_NOC_MEMTYPE_MASK GENMASK(26, 24)
+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 FIELD_PREP(TCSR_WIFI_NOC_MEMTYPE_MASK, 0x2)
+
+static int qcom_tcsr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node;
+ struct regmap *tcsr;
+ int ret, val;
+
+ node = dev->of_node;
+ tcsr = syscon_node_to_regmap(node);
+ if (IS_ERR(tcsr))
+ return PTR_ERR(tcsr);
+
+ if (of_find_property(node, "qcom,usb-ctrl-select", NULL) &&
+ of_device_is_compatible(node, "qcom,tcsr-ipq8064")) {
+ if (of_property_match_string(node, "qcom,usb-ctrl-select",
+ "p0")) {
+ val = TCSR_USB_SELECT_USB3_P0;
+ } else if (of_property_match_string(node, "qcom,usb-ctrl-select",
+ "p1")) {
+ val = TCSR_USB_SELECT_USB3_P1;
+ } else if (of_property_match_string(node, "qcom,usb-ctrl-select",
+ "dual")) {
+ val = TCSR_USB_SELECT_USB3_DUAL;
+ } else {
+ dev_err(dev, "invalid value for qcom,usb-ctrl-select");
+ return -EINVAL;
+ }
+
+ ret = regmap_update_bits(tcsr, TCSR_USB_PORT_SEL_REG,
+ TCSR_USB_PORT_SEL_MASK, val);
+ if (ret)
+ return ret;
+ }
+
+ if (of_find_property(node, "qcom,usb-hsphy-mode-select", NULL) &&
+ of_device_is_compatible(node, "qcom,tcsr-ipq4019")) {
+ if (of_property_match_string(node, "qcom,usb-hsphy-mode-select",
+ "host")) {
+ val = TCSR_USB_HSPHY_MODE_HOST_MODE;
+ } else if (of_property_match_string(node, "qcom,usb-hsphy-mode-select",
+ "device")) {
+ val = TCSR_USB_HSPHY_MODE_DEVICE_MODE;
+ } else {
+ dev_err(dev, "invalid value for qcom,usb-hsphy-mode-select");
+ return -EINVAL;
+ }
+
+ ret = regmap_update_bits(tcsr, TCSR_USB_HSPHY_CONFIG_REG,
+ TCSR_USB_HSPHY_MODE_MASK, val);
+ if (ret)
+ return ret;
+ }
+
+ if (of_find_property(node, "qcom,ess-interface-select", NULL) &&
+ of_device_is_compatible(node, "qcom,tcsr-ipq4019")) {
+ if (of_property_match_string(node, "qcom,ess-interface-select",
+ "psgmii")) {
+ val = TCSR_ESS_PSGMII;
+ } else if (of_property_match_string(node, "qcom,ess-interface-select",
+ "rgmii5")) {
+ val = TCSR_ESS_PSGMII_RGMII5;
+ } else if (of_property_match_string(node, "qcom,ess-interface-select",
+ "rmii0")) {
+ val = TCSR_ESS_PSGMII_RMII0;
+ } else if (of_property_match_string(node, "qcom,ess-interface-select",
+ "rmii1")) {
+ val = TCSR_ESS_PSGMII_RMII1;
+ } else if (of_property_match_string(node, "qcom,ess-interface-select",
+ "rmii0_rmii1")) {
+ val = TCSR_ESS_PSGMII_RMII0_RMII1;
+ } else if (of_property_match_string(node, "qcom,ess-interface-select",
+ "rgmii4")) {
+ val = TCSR_ESS_PSGMII_RGMII4;
+ } else {
+ dev_err(dev, "invalid value for qcom,ess-interface-select");
+ return -EINVAL;
+ }
+
+ ret = regmap_update_bits(tcsr, TCSR_ESS_INTERFACE_SEL_REG,
+ TCSR_ESS_INTERFACE_SEL_MASK, val);
+ if (ret)
+ return ret;
+ }
+
+ if (of_find_property(node, "qcom,wifi-glb-cfg-enable-axid", NULL) &&
+ of_device_is_compatible(node, "qcom,tcsr-ipq4019")) {
+ ret = regmap_set_bits(tcsr, TCSR_WIFI0_GLB_CFG_OFFSET_REG,
+ TCSR_WIFI_GLB_CFG_AXID_EN);
+ ret = regmap_set_bits(tcsr, TCSR_WIFI1_GLB_CFG_OFFSET_REG,
+ TCSR_WIFI_GLB_CFG_AXID_EN);
+ if (ret)
+ return ret;
+ }
+
+ if (of_find_property(node, "qcom,wifi-glb-cfg-socslv-mode", NULL) &&
+ of_device_is_compatible(node, "qcom,tcsr-ipq4019")) {
+ if (of_property_match_string(node, "qcom,wifi-glb-cfg-socslv-mode",
+ "snoc")) {
+ val = TCSR_WIFI_GLB_CFG_SOCSLV_SNOC;
+ } else if (of_property_match_string(node, "qcom,wifi-glb-cfg-socslv-mode",
+ "local")) {
+ val = TCSR_WIFI_GLB_CFG_SOCSLV_SNOC;
+ } else {
+ dev_err(dev, "invalid value for qcom,wifi-glb-cfg-socslv-mode");
+ return -EINVAL;
+ }
+
+ ret = regmap_update_bits(tcsr, TCSR_WIFI0_GLB_CFG_OFFSET_REG,
+ TCSR_WIFI_GLB_CFG_SOCSLV_WXI_BVALID, val);
+ ret = regmap_update_bits(tcsr, TCSR_WIFI1_GLB_CFG_OFFSET_REG,
+ TCSR_WIFI_GLB_CFG_SOCSLV_WXI_BVALID, val);
+ }
+
+ if (of_find_property(node, "qcom,wifi_noc_memtype_m0_m2", NULL) &&
+ of_device_is_compatible(node, "qcom,tcsr-ipq4019")) {
+ ret = regmap_update_bits(tcsr, TCSR_PNOC_SNOC_MEMTYPE_M0_M2_REG,
+ TCSR_WIFI_NOC_MEMTYPE_MASK,
+ TCSR_WIFI_NOC_MEMTYPE_M0_M2);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id qcom_tcsr_dt_match[] = {
+ { .compatible = "qcom,tcsr-ipq8064", },
+ { .compatible = "qcom,tcsr-ipq4019", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, qcom_tcsr_dt_match);
+
+static struct platform_driver qcom_tcsr_driver = {
+ .probe = qcom_tcsr_probe,
+ .driver = {
+ .name = "qcom-tcsr",
+ .of_match_table = qcom_tcsr_dt_match,
+ },
+};
+
+module_platform_driver(qcom_tcsr_driver);
+
+MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("QCOM TCSR driver");
+MODULE_LICENSE("GPL v2");
--
2.33.1
^ permalink raw reply related
* Re: [v1 01/16] dt-bindings: ARM: Mediatek: Add new document bindings of MT8186 clock
From: Rob Herring @ 2022-01-22 0:25 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, linux-arm-kernel,
linux-kernel, linux-mediatek, linux-clk, devicetree,
srv_heupstream, Project_Global_Chrome_Upstream_Group
In-Reply-To: <20220110134416.5191-2-chun-jie.chen@mediatek.com>
On Mon, Jan 10, 2022 at 09:44:01PM +0800, Chun-Jie Chen wrote:
> This patch adds the new binding documentation for system clock
> and functional clock on Mediatek MT8186.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> .../arm/mediatek/mediatek,mt8186-clock.yaml | 133 ++++++++++++++++++
> .../mediatek/mediatek,mt8186-sys-clock.yaml | 74 ++++++++++
> 2 files changed, 207 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
> new file mode 100644
> index 000000000000..fc39101bc9b0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
> @@ -0,0 +1,133 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Mediatek Functional Clock Controller for MT8186
> +
> +maintainers:
> + - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +description:
> + The clock architecture in Mediatek like below
> + PLLs -->
> + dividers -->
> + muxes
> + -->
> + clock gate
> +
> + The devices provide clock gate control in different IP blocks.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8186-imp_iic_wrap
> + - mediatek,mt8186-mfgsys
> + - mediatek,mt8186-wpesys
> + - mediatek,mt8186-imgsys1
> + - mediatek,mt8186-imgsys2
> + - mediatek,mt8186-vdecsys
> + - mediatek,mt8186-vencsys
> + - mediatek,mt8186-camsys
> + - mediatek,mt8186-camsys_rawa
> + - mediatek,mt8186-camsys_rawb
> + - mediatek,mt8186-mdpsys
> + - mediatek,mt8186-ipesys
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + imp_iic_wrap: clock-controller@11017000 {
> + compatible = "mediatek,mt8186-imp_iic_wrap";
> + reg = <0x11017000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + mfgsys: clock-controller@13000000 {
> + compatible = "mediatek,mt8186-mfgsys";
> + reg = <0x13000000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + wpesys: clock-controller@14020000 {
> + compatible = "mediatek,mt8186-wpesys";
> + reg = <0x14020000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + imgsys1: clock-controller@15020000 {
> + compatible = "mediatek,mt8186-imgsys1";
> + reg = <0x15020000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + imgsys2: clock-controller@15820000 {
> + compatible = "mediatek,mt8186-imgsys2";
> + reg = <0x15820000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + vdecsys: clock-controller@1602f000 {
> + compatible = "mediatek,mt8186-vdecsys";
> + reg = <0x1602f000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + vencsys: clock-controller@17000000 {
> + compatible = "mediatek,mt8186-vencsys";
> + reg = <0x17000000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + camsys: clock-controller@1a000000 {
> + compatible = "mediatek,mt8186-camsys";
> + reg = <0x1a000000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + camsys_rawa: clock-controller@1a04f000 {
> + compatible = "mediatek,mt8186-camsys_rawa";
> + reg = <0x1a04f000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + camsys_rawb: clock-controller@1a06f000 {
> + compatible = "mediatek,mt8186-camsys_rawb";
> + reg = <0x1a06f000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + mdpsys: clock-controller@1b000000 {
> + compatible = "mediatek,mt8186-mdpsys";
> + reg = <0x1b000000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + ipesys: clock-controller@1c000000 {
> + compatible = "mediatek,mt8186-ipesys";
> + reg = <0x1c000000 0x1000>;
> + #clock-cells = <1>;
> + };
There's little point in enumerating every possible compatible. 1 example
is more than enough.
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
> new file mode 100644
> index 000000000000..11473971a165
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Mediatek System Clock Controller for MT8186
> +
> +maintainers:
> + - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +description:
> + The clock architecture in Mediatek like below
> + PLLs -->
> + dividers -->
> + muxes
> + -->
> + clock gate
> +
> + The apmixedsys provides most of PLLs which generated from SoC 26m.
> + The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
> + The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
> + The mcusys provides mux control to select the clock source in AP MCU.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8186-mcusys
> + - mediatek,mt8186-topckgen
> + - mediatek,mt8186-infracfg_ao
> + - mediatek,mt8186-apmixedsys
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + mcusys: syscon@c53a000 {
clock-controller@...
Drop unused labels.
> + compatible = "mediatek,mt8186-mcusys", "syscon";
> + reg = <0xc53a000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8186-topckgen", "syscon";
> + reg = <0x10000000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + infracfg_ao: syscon@10001000 {
> + compatible = "mediatek,mt8186-infracfg_ao", "syscon";
> + reg = <0x10001000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + - |
> + apmixedsys: syscon@1000c000 {
> + compatible = "mediatek,mt8186-apmixedsys", "syscon";
> + reg = <0x1000c000 0x1000>;
> + #clock-cells = <1>;
> + };
Again, 1 example is enough.
^ permalink raw reply
* Re: [v1 02/16] clk: mediatek: Add dt-bindings of MT8186 clocks
From: Rob Herring @ 2022-01-22 0:27 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, linux-arm-kernel,
linux-kernel, linux-mediatek, linux-clk, devicetree,
srv_heupstream, Project_Global_Chrome_Upstream_Group
In-Reply-To: <20220110134416.5191-3-chun-jie.chen@mediatek.com>
On Mon, Jan 10, 2022 at 09:44:02PM +0800, Chun-Jie Chen wrote:
> Add MT8186 clock dt-bindings, includes topckgen, apmixedsys,
> infracfg_ao, mcusys and subsystem clocks.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> include/dt-bindings/clock/mt8186-clk.h | 445 +++++++++++++++++++++++++
> 1 file changed, 445 insertions(+)
> create mode 100644 include/dt-bindings/clock/mt8186-clk.h
As mentioned, squash with patch 1.
>
> diff --git a/include/dt-bindings/clock/mt8186-clk.h b/include/dt-bindings/clock/mt8186-clk.h
> new file mode 100644
> index 000000000000..6a291750cea4
> --- /dev/null
> +++ b/include/dt-bindings/clock/mt8186-clk.h
> @@ -0,0 +1,445 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
Dual license please.
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MT8186_H
> +#define _DT_BINDINGS_CLK_MT8186_H
> +
> +/* MCUSYS */
> +
> +#define CLK_MCU_ARMPLL_LL_SEL 0
> +#define CLK_MCU_ARMPLL_BL_SEL 1
> +#define CLK_MCU_ARMPLL_BUS_SEL 2
> +#define CLK_MCU_NR_CLK 3
> +
> +/* TOPCKGEN */
> +
> +#define CLK_TOP_AXI 0
> +#define CLK_TOP_SCP 1
> +#define CLK_TOP_MFG 2
> +#define CLK_TOP_CAMTG 3
> +#define CLK_TOP_CAMTG1 4
> +#define CLK_TOP_CAMTG2 5
> +#define CLK_TOP_CAMTG3 6
> +#define CLK_TOP_CAMTG4 7
> +#define CLK_TOP_CAMTG5 8
> +#define CLK_TOP_CAMTG6 9
> +#define CLK_TOP_UART 10
> +#define CLK_TOP_SPI 11
> +#define CLK_TOP_MSDC50_0_HCLK 12
> +#define CLK_TOP_MSDC50_0 13
> +#define CLK_TOP_MSDC30_1 14
> +#define CLK_TOP_AUDIO 15
> +#define CLK_TOP_AUD_INTBUS 16
> +#define CLK_TOP_AUD_1 17
> +#define CLK_TOP_AUD_2 18
> +#define CLK_TOP_AUD_ENGEN1 19
> +#define CLK_TOP_AUD_ENGEN2 20
> +#define CLK_TOP_DISP_PWM 21
> +#define CLK_TOP_SSPM 22
> +#define CLK_TOP_DXCC 23
> +#define CLK_TOP_USB_TOP 24
> +#define CLK_TOP_SRCK 25
> +#define CLK_TOP_SPM 26
> +#define CLK_TOP_I2C 27
> +#define CLK_TOP_PWM 28
> +#define CLK_TOP_SENINF 29
> +#define CLK_TOP_SENINF1 30
> +#define CLK_TOP_SENINF2 31
> +#define CLK_TOP_SENINF3 32
> +#define CLK_TOP_AES_MSDCFDE 33
> +#define CLK_TOP_PWRAP_ULPOSC 34
> +#define CLK_TOP_CAMTM 35
> +#define CLK_TOP_VENC 36
> +#define CLK_TOP_CAM 37
> +#define CLK_TOP_IMG1 38
> +#define CLK_TOP_IPE 39
> +#define CLK_TOP_DPMAIF 40
> +#define CLK_TOP_VDEC 41
> +#define CLK_TOP_DISP 42
> +#define CLK_TOP_MDP 43
> +#define CLK_TOP_AUDIO_H 44
> +#define CLK_TOP_UFS 45
> +#define CLK_TOP_AES_FDE 46
> +#define CLK_TOP_AUDIODSP 47
> +#define CLK_TOP_DVFSRC 48
> +#define CLK_TOP_DSI_OCC 49
> +#define CLK_TOP_SPMI_MST 50
> +#define CLK_TOP_SPINOR 51
> +#define CLK_TOP_NNA 52
> +#define CLK_TOP_NNA1 53
> +#define CLK_TOP_NNA2 54
> +#define CLK_TOP_SSUSB_XHCI 55
> +#define CLK_TOP_SSUSB_TOP_1P 56
> +#define CLK_TOP_SSUSB_XHCI_1P 57
> +#define CLK_TOP_WPE 58
> +#define CLK_TOP_DPI 59
> +#define CLK_TOP_U3_OCC_250M 60
> +#define CLK_TOP_U3_OCC_500M 61
> +#define CLK_TOP_ADSP_BUS 62
> +#define CLK_TOP_APLL_I2S0_MCK_SEL 63
> +#define CLK_TOP_APLL_I2S1_MCK_SEL 64
> +#define CLK_TOP_APLL_I2S2_MCK_SEL 65
> +#define CLK_TOP_APLL_I2S4_MCK_SEL 66
> +#define CLK_TOP_APLL_TDMOUT_MCK_SEL 67
> +#define CLK_TOP_MAINPLL_D2 68
> +#define CLK_TOP_MAINPLL_D2_D2 69
> +#define CLK_TOP_MAINPLL_D2_D4 70
> +#define CLK_TOP_MAINPLL_D2_D16 71
> +#define CLK_TOP_MAINPLL_D3 72
> +#define CLK_TOP_MAINPLL_D3_D2 73
> +#define CLK_TOP_MAINPLL_D3_D4 74
> +#define CLK_TOP_MAINPLL_D5 75
> +#define CLK_TOP_MAINPLL_D5_D2 76
> +#define CLK_TOP_MAINPLL_D5_D4 77
> +#define CLK_TOP_MAINPLL_D7 78
> +#define CLK_TOP_MAINPLL_D7_D2 79
> +#define CLK_TOP_MAINPLL_D7_D4 80
> +#define CLK_TOP_UNIVPLL 81
> +#define CLK_TOP_UNIVPLL_D2 82
> +#define CLK_TOP_UNIVPLL_D2_D2 83
> +#define CLK_TOP_UNIVPLL_D2_D4 84
> +#define CLK_TOP_UNIVPLL_D3 85
> +#define CLK_TOP_UNIVPLL_D3_D2 86
> +#define CLK_TOP_UNIVPLL_D3_D4 87
> +#define CLK_TOP_UNIVPLL_D3_D8 88
> +#define CLK_TOP_UNIVPLL_D3_D32 89
> +#define CLK_TOP_UNIVPLL_D5 90
> +#define CLK_TOP_UNIVPLL_D5_D2 91
> +#define CLK_TOP_UNIVPLL_D5_D4 92
> +#define CLK_TOP_UNIVPLL_D7 93
> +#define CLK_TOP_UNIVPLL_192M 94
> +#define CLK_TOP_UNIVPLL_192M_D4 95
> +#define CLK_TOP_UNIVPLL_192M_D8 96
> +#define CLK_TOP_UNIVPLL_192M_D16 97
> +#define CLK_TOP_UNIVPLL_192M_D32 98
> +#define CLK_TOP_APLL1_D2 99
> +#define CLK_TOP_APLL1_D4 100
> +#define CLK_TOP_APLL1_D8 101
> +#define CLK_TOP_APLL2_D2 102
> +#define CLK_TOP_APLL2_D4 103
> +#define CLK_TOP_APLL2_D8 104
> +#define CLK_TOP_MMPLL_D2 105
> +#define CLK_TOP_TVDPLL_D2 106
> +#define CLK_TOP_TVDPLL_D4 107
> +#define CLK_TOP_TVDPLL_D8 108
> +#define CLK_TOP_TVDPLL_D16 109
> +#define CLK_TOP_TVDPLL_D32 110
> +#define CLK_TOP_MSDCPLL_D2 111
> +#define CLK_TOP_ULPOSC1 112
> +#define CLK_TOP_ULPOSC1_D2 113
> +#define CLK_TOP_ULPOSC1_D4 114
> +#define CLK_TOP_ULPOSC1_D8 115
> +#define CLK_TOP_ULPOSC1_D10 116
> +#define CLK_TOP_ULPOSC1_D16 117
> +#define CLK_TOP_ULPOSC1_D32 118
> +#define CLK_TOP_ADSPPLL_D2 119
> +#define CLK_TOP_ADSPPLL_D4 120
> +#define CLK_TOP_ADSPPLL_D8 121
> +#define CLK_TOP_NNAPLL_D2 122
> +#define CLK_TOP_NNAPLL_D4 123
> +#define CLK_TOP_NNAPLL_D8 124
> +#define CLK_TOP_NNA2PLL_D2 125
> +#define CLK_TOP_NNA2PLL_D4 126
> +#define CLK_TOP_NNA2PLL_D8 127
> +#define CLK_TOP_F_BIST2FPC 128
> +#define CLK_TOP_466M_FMEM 129
> +#define CLK_TOP_MPLL 130
> +#define CLK_TOP_APLL12_CK_DIV0 131
> +#define CLK_TOP_APLL12_CK_DIV1 132
> +#define CLK_TOP_APLL12_CK_DIV2 133
> +#define CLK_TOP_APLL12_CK_DIV4 134
> +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 135
> +#define CLK_TOP_NR_CLK 136
> +
> +/* INFRACFG_AO */
> +
> +#define CLK_INFRA_AO_PMIC_TMR 0
> +#define CLK_INFRA_AO_PMIC_AP 1
> +#define CLK_INFRA_AO_PMIC_MD 2
> +#define CLK_INFRA_AO_PMIC_CONN 3
> +#define CLK_INFRA_AO_SCP_CORE 4
> +#define CLK_INFRA_AO_SEJ 5
> +#define CLK_INFRA_AO_APXGPT 6
> +#define CLK_INFRA_AO_ICUSB 7
> +#define CLK_INFRA_AO_GCE 8
> +#define CLK_INFRA_AO_THERM 9
> +#define CLK_INFRA_AO_I2C_AP 10
> +#define CLK_INFRA_AO_I2C_CCU 11
> +#define CLK_INFRA_AO_I2C_SSPM 12
> +#define CLK_INFRA_AO_I2C_RSV 13
> +#define CLK_INFRA_AO_PWM_HCLK 14
> +#define CLK_INFRA_AO_PWM1 15
> +#define CLK_INFRA_AO_PWM2 16
> +#define CLK_INFRA_AO_PWM3 17
> +#define CLK_INFRA_AO_PWM4 18
> +#define CLK_INFRA_AO_PWM5 19
> +#define CLK_INFRA_AO_PWM 20
> +#define CLK_INFRA_AO_UART0 21
> +#define CLK_INFRA_AO_UART1 22
> +#define CLK_INFRA_AO_UART2 23
> +#define CLK_INFRA_AO_GCE_26M 24
> +#define CLK_INFRA_AO_CQ_DMA_FPC 25
> +#define CLK_INFRA_AO_BTIF 26
> +#define CLK_INFRA_AO_SPI0 27
> +#define CLK_INFRA_AO_MSDC0 28
> +#define CLK_INFRA_AO_MSDCFDE 29
> +#define CLK_INFRA_AO_MSDC1 30
> +#define CLK_INFRA_AO_DVFSRC 31
> +#define CLK_INFRA_AO_GCPU 32
> +#define CLK_INFRA_AO_TRNG 33
> +#define CLK_INFRA_AO_AUXADC 34
> +#define CLK_INFRA_AO_CPUM 35
> +#define CLK_INFRA_AO_CCIF1_AP 36
> +#define CLK_INFRA_AO_CCIF1_MD 37
> +#define CLK_INFRA_AO_AUXADC_MD 38
> +#define CLK_INFRA_AO_AP_DMA 39
> +#define CLK_INFRA_AO_XIU 40
> +#define CLK_INFRA_AO_DEVICE_APC 41
> +#define CLK_INFRA_AO_CCIF_AP 42
> +#define CLK_INFRA_AO_DEBUGTOP 43
> +#define CLK_INFRA_AO_AUDIO 44
> +#define CLK_INFRA_AO_CCIF_MD 45
> +#define CLK_INFRA_AO_DXCC_SEC_CORE 46
> +#define CLK_INFRA_AO_DXCC_AO 47
> +#define CLK_INFRA_AO_IMP_IIC 48
> +#define CLK_INFRA_AO_DRAMC_F26M 49
> +#define CLK_INFRA_AO_RG_PWM_FBCLK6 50
> +#define CLK_INFRA_AO_SSUSB_TOP_HCLK 51
> +#define CLK_INFRA_AO_DISP_PWM 52
> +#define CLK_INFRA_AO_CLDMA_BCLK 53
> +#define CLK_INFRA_AO_AUDIO_26M_BCLK 54
> +#define CLK_INFRA_AO_SSUSB_TOP_P1_HCLK 55
> +#define CLK_INFRA_AO_SPI1 56
> +#define CLK_INFRA_AO_I2C4 57
> +#define CLK_INFRA_AO_MODEM_TEMP_SHARE 58
> +#define CLK_INFRA_AO_SPI2 59
> +#define CLK_INFRA_AO_SPI3 60
> +#define CLK_INFRA_AO_SSUSB_TOP_REF 61
> +#define CLK_INFRA_AO_SSUSB_TOP_XHCI 62
> +#define CLK_INFRA_AO_SSUSB_TOP_P1_REF 63
> +#define CLK_INFRA_AO_SSUSB_TOP_P1_XHCI 64
> +#define CLK_INFRA_AO_SSPM 65
> +#define CLK_INFRA_AO_SSUSB_TOP_P1_SYS 66
> +#define CLK_INFRA_AO_I2C5 67
> +#define CLK_INFRA_AO_I2C5_ARBITER 68
> +#define CLK_INFRA_AO_I2C5_IMM 69
> +#define CLK_INFRA_AO_I2C1_ARBITER 70
> +#define CLK_INFRA_AO_I2C1_IMM 71
> +#define CLK_INFRA_AO_I2C2_ARBITER 72
> +#define CLK_INFRA_AO_I2C2_IMM 73
> +#define CLK_INFRA_AO_SPI4 74
> +#define CLK_INFRA_AO_SPI5 75
> +#define CLK_INFRA_AO_CQ_DMA 76
> +#define CLK_INFRA_AO_BIST2FPC 77
> +#define CLK_INFRA_AO_MSDC0_SELF 78
> +#define CLK_INFRA_AO_SPINOR 79
> +#define CLK_INFRA_AO_SSPM_26M_SELF 80
> +#define CLK_INFRA_AO_SSPM_32K_SELF 81
> +#define CLK_INFRA_AO_I2C6 82
> +#define CLK_INFRA_AO_AP_MSDC0 83
> +#define CLK_INFRA_AO_MD_MSDC0 84
> +#define CLK_INFRA_AO_MSDC0_SRC 85
> +#define CLK_INFRA_AO_MSDC1_SRC 86
> +#define CLK_INFRA_AO_SEJ_F13M 87
> +#define CLK_INFRA_AO_AES_TOP0_BCLK 88
> +#define CLK_INFRA_AO_MCU_PM_BCLK 89
> +#define CLK_INFRA_AO_CCIF2_AP 90
> +#define CLK_INFRA_AO_CCIF2_MD 91
> +#define CLK_INFRA_AO_CCIF3_AP 92
> +#define CLK_INFRA_AO_CCIF3_MD 93
> +#define CLK_INFRA_AO_FADSP_26M 94
> +#define CLK_INFRA_AO_FADSP_32K 95
> +#define CLK_INFRA_AO_CCIF4_AP 96
> +#define CLK_INFRA_AO_CCIF4_MD 97
> +#define CLK_INFRA_AO_FADSP 98
> +#define CLK_INFRA_AO_FLASHIF_133M 99
> +#define CLK_INFRA_AO_FLASHIF_66M 100
> +#define CLK_INFRA_AO_NR_CLK 101
> +
> +/* APMIXEDSYS */
> +
> +#define CLK_APMIXED_ARMPLL_LL 0
> +#define CLK_APMIXED_ARMPLL_BL 1
> +#define CLK_APMIXED_CCIPLL 2
> +#define CLK_APMIXED_MAINPLL 3
> +#define CLK_APMIXED_UNIV2PLL 4
> +#define CLK_APMIXED_MSDCPLL 5
> +#define CLK_APMIXED_MMPLL 6
> +#define CLK_APMIXED_NNAPLL 7
> +#define CLK_APMIXED_NNA2PLL 8
> +#define CLK_APMIXED_ADSPPLL 9
> +#define CLK_APMIXED_MFGPLL 10
> +#define CLK_APMIXED_TVDPLL 11
> +#define CLK_APMIXED_APLL1 12
> +#define CLK_APMIXED_APLL2 13
> +#define CLK_APMIXED_NR_CLK 14
> +
> +/* IMP_IIC_WRAP */
> +
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 0
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 1
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 2
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 3
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 4
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 5
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 6
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 7
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 8
> +#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 9
> +#define CLK_IMP_IIC_WRAP_NR_CLK 10
> +
> +/* MFGCFG */
> +
> +#define CLK_MFG_BG3D 0
> +#define CLK_MFG_NR_CLK 1
> +
> +/* MMSYS */
> +
> +#define CLK_MM_DISP_MUTEX0 0
> +#define CLK_MM_APB_MM_BUS 1
> +#define CLK_MM_DISP_OVL0 2
> +#define CLK_MM_DISP_RDMA0 3
> +#define CLK_MM_DISP_OVL0_2L 4
> +#define CLK_MM_DISP_WDMA0 5
> +#define CLK_MM_DISP_RSZ0 6
> +#define CLK_MM_DISP_AAL0 7
> +#define CLK_MM_DISP_CCORR0 8
> +#define CLK_MM_DISP_COLOR0 9
> +#define CLK_MM_SMI_INFRA 10
> +#define CLK_MM_DISP_DSC_WRAP0 11
> +#define CLK_MM_DISP_GAMMA0 12
> +#define CLK_MM_DISP_POSTMASK0 13
> +#define CLK_MM_DISP_DITHER0 14
> +#define CLK_MM_SMI_COMMON 15
> +#define CLK_MM_DSI0 16
> +#define CLK_MM_DISP_FAKE_ENG0 17
> +#define CLK_MM_DISP_FAKE_ENG1 18
> +#define CLK_MM_SMI_GALS 19
> +#define CLK_MM_SMI_IOMMU 20
> +#define CLK_MM_DISP_RDMA1 21
> +#define CLK_MM_DISP_DPI 22
> +#define CLK_MM_DSI0_DSI_CK_DOMAIN 23
> +#define CLK_MM_DISP_26M 24
> +#define CLK_MM_NR_CLK 25
> +
> +/* WPESYS */
> +
> +#define CLK_WPE_CK_EN 0
> +#define CLK_WPE_SMI_LARB8_CK_EN 1
> +#define CLK_WPE_SYS_EVENT_TX_CK_EN 2
> +#define CLK_WPE_SMI_LARB8_PCLK_EN 3
> +#define CLK_WPE_NR_CLK 4
> +
> +/* IMGSYS1 */
> +
> +#define CLK_IMG1_LARB9_IMG1 0
> +#define CLK_IMG1_LARB10_IMG1 1
> +#define CLK_IMG1_DIP 2
> +#define CLK_IMG1_GALS_IMG1 3
> +#define CLK_IMG1_NR_CLK 4
> +
> +/* IMGSYS2 */
> +
> +#define CLK_IMG2_LARB9_IMG2 0
> +#define CLK_IMG2_LARB10_IMG2 1
> +#define CLK_IMG2_MFB 2
> +#define CLK_IMG2_WPE 3
> +#define CLK_IMG2_MSS 4
> +#define CLK_IMG2_GALS_IMG2 5
> +#define CLK_IMG2_NR_CLK 6
> +
> +/* VDECSYS */
> +
> +#define CLK_VDEC_LARB1_CKEN 0
> +#define CLK_VDEC_LAT_CKEN 1
> +#define CLK_VDEC_LAT_ACTIVE 2
> +#define CLK_VDEC_LAT_CKEN_ENG 3
> +#define CLK_VDEC_MINI_MDP_CKEN_CFG_RG 4
> +#define CLK_VDEC_CKEN 5
> +#define CLK_VDEC_ACTIVE 6
> +#define CLK_VDEC_CKEN_ENG 7
> +#define CLK_VDEC_NR_CLK 8
> +
> +/* VENCSYS */
> +
> +#define CLK_VENC_CKE0_LARB 0
> +#define CLK_VENC_CKE1_VENC 1
> +#define CLK_VENC_CKE2_JPGENC 2
> +#define CLK_VENC_CKE5_GALS 3
> +#define CLK_VENC_NR_CLK 4
> +
> +/* CAMSYS */
> +
> +#define CLK_CAM_LARB13 0
> +#define CLK_CAM_DFP_VAD 1
> +#define CLK_CAM_LARB14 2
> +#define CLK_CAM 3
> +#define CLK_CAMTG 4
> +#define CLK_CAM_SENINF 5
> +#define CLK_CAMSV1 6
> +#define CLK_CAMSV2 7
> +#define CLK_CAMSV3 8
> +#define CLK_CAM_CCU0 9
> +#define CLK_CAM_CCU1 10
> +#define CLK_CAM_MRAW0 11
> +#define CLK_CAM_FAKE_ENG 12
> +#define CLK_CAM_CCU_GALS 13
> +#define CLK_CAM2MM_GALS 14
> +#define CLK_CAM_NR_CLK 15
> +
> +/* CAMSYS_RAWA */
> +
> +#define CLK_CAM_RAWA_LARBX_RAWA 0
> +#define CLK_CAM_RAWA 1
> +#define CLK_CAM_RAWA_CAMTG_RAWA 2
> +#define CLK_CAM_RAWA_NR_CLK 3
> +
> +/* CAMSYS_RAWB */
> +
> +#define CLK_CAM_RAWB_LARBX_RAWB 0
> +#define CLK_CAM_RAWB 1
> +#define CLK_CAM_RAWB_CAMTG_RAWB 2
> +#define CLK_CAM_RAWB_NR_CLK 3
> +
> +/* MDPSYS */
> +
> +#define CLK_MDP_RDMA0 0
> +#define CLK_MDP_TDSHP0 1
> +#define CLK_MDP_IMG_DL_ASYNC0 2
> +#define CLK_MDP_IMG_DL_ASYNC1 3
> +#define CLK_MDP_DISP_RDMA 4
> +#define CLK_MDP_HMS 5
> +#define CLK_MDP_SMI0 6
> +#define CLK_MDP_APB_BUS 7
> +#define CLK_MDP_WROT0 8
> +#define CLK_MDP_RSZ0 9
> +#define CLK_MDP_HDR0 10
> +#define CLK_MDP_MUTEX0 11
> +#define CLK_MDP_WROT1 12
> +#define CLK_MDP_RSZ1 13
> +#define CLK_MDP_FAKE_ENG0 14
> +#define CLK_MDP_AAL0 15
> +#define CLK_MDP_DISP_WDMA 16
> +#define CLK_MDP_COLOR 17
> +#define CLK_MDP_IMG_DL_ASYNC2 18
> +#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 19
> +#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 20
> +#define CLK_MDP_IMG_DL_RELAY2_ASYNC2 21
> +#define CLK_MDP_NR_CLK 22
> +
> +/* IPESYS */
> +
> +#define CLK_IPE_LARB19 0
> +#define CLK_IPE_LARB20 1
> +#define CLK_IPE_SMI_SUBCOM 2
> +#define CLK_IPE_FD 3
> +#define CLK_IPE_FE 4
> +#define CLK_IPE_RSC 5
> +#define CLK_IPE_DPE 6
> +#define CLK_IPE_GALS_IPE 7
> +#define CLK_IPE_NR_CLK 8
> +
> +#endif /* _DT_BINDINGS_CLK_MT8186_H */
> --
> 2.18.0
>
>
^ permalink raw reply
* Re: [PATCH v2.1 03/11] dt-bindings: media: i2c: max9286: Add property to select bus width
From: Rob Herring @ 2022-01-22 0:28 UTC (permalink / raw)
To: Laurent Pinchart
Cc: devicetree, Rob Herring, Thomas Nizan, Niklas Söderlund,
linux-media, Jacopo Mondi, linux-renesas-soc, Kieran Bingham
In-Reply-To: <20220110212446.3021-1-laurent.pinchart+renesas@ideasonboard.com>
On Mon, 10 Jan 2022 23:24:46 +0200, Laurent Pinchart wrote:
> The GMSL serial data bus width is normally selected by the BWS pin, but
> it can also be configured by software. Add a DT property that allows
> overriding the value of the BWS-selected bus width to support systems
> whose BWS pin doesn't result in the correct value.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> ---
> Changes since v2:
>
> - Specify the property type
> ---
> .../devicetree/bindings/media/i2c/maxim,max9286.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [RFC PATCH 1/2] dt-bindings: mtd: partitions: Document new dynamic-partitions node
From: Ansuel Smith @ 2022-01-22 0:29 UTC (permalink / raw)
To: Rob Herring
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra, linux-mtd,
devicetree, linux-kernel
In-Reply-To: <YeoRJlTbILNtZgoW@robh.at.kernel.org>
On Thu, Jan 20, 2022 at 07:49:26PM -0600, Rob Herring wrote:
> On Thu, Jan 20, 2022 at 09:26:14PM +0100, Ansuel Smith wrote:
> > Document new dynamic-partitions node used to provide an of node for
> > partition registred at runtime by parsers. This is required for nvmem
> > system to declare and detect nvmem-cells.
>
> So you have some discoverable way to find all the partitions and the
> nvmem cells are at an unknown (to the DT) location, but still need to be
> described in DT?
>
Example: smem partition layout is saved in the bootloader and static. To
know the layout just boot the device and extract it. Aside from this the
naming convention is ""standard"" (example the standard nvmem location
for this is named 0:art)
What needs to be described in the DT is the cell offset and the
partition name (the location)
NVMEM doesn't support this and honestly I can't think of a simple and
direct way to solve this. Considering partition in this case are just
filled at runtime and they doesn't change (or at worst the partition
offset change but NEVER the name) it seems a good way to fix this by
describing a nvmem cells partition name and assign a of node to the
runtime filled partition.
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> > .../mtd/partitions/dynamic-partitions.yaml | 59 +++++++++++++++++++
> > 1 file changed, 59 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml b/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
> > new file mode 100644
> > index 000000000000..7528e49f2d7e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/partitions/dynamic-partitions.yaml
> > @@ -0,0 +1,59 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mtd/partitions/dynamic-partitions.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Dynamic partitions
> > +
> > +description: |
> > + This binding can be used on platforms which have partitions registered at
> > + runtime by parsers or partition table present on the flash. Example are
> > + partitions declared from smem parser or cmdlinepart. This will create an
>
> Some information in DT and some on the cmdline seems broken to me. Pick
> one or the other.
>
Converting a system from cmdline to fixedpartition is problematic
if the cmdline is dynamic. Example some system have dual partition and
are handled by editing the cmdline partition description. In this
cmdline tho the nvmem cell of our interest doesn't change and we can use
this new implemenation to add support for nvmem cells.
So really there are some case where nvmem won't work and it's not
possible to provide a correct configuration for nvmem to work correctly.
Is it that bad to have information in the DT about nvmem cells for a
partition named with a particular label that won't change.
> > + of node for these dynamic partition where systems like Nvmem can get a
> > + reference to register nvmem-cells.
> > +
> > + The partition table should be a node named "dynamic-partitions".
> > + Partitions are then defined as subnodes. Only the label is required
> > + as any other data will be taken from the parser.
> > +
> > +maintainers:
> > + - Ansuel Smith <ansuelsmth@gmail.com>
> > +
> > +properties:
> > + compatible:
> > + const: dynamic-partitions
>
> This is useless. This tells me nothing about the what's in the
> partitions.
>
> > +
> > +patternProperties:
> > + "@[0-9a-f]+$":
> > + $ref: "partition.yaml#"
> > +
> > +additionalProperties: true
> > +
> > +examples:
> > + - |
> > + partitions {
> > + compatible = "qcom,smem";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + };
> > +
> > + dynamic-partitions {
> > + compatible = "dynamic-partitions";
> > +
> > + art: art {
> > + label = "0:art";
> > + read-only;
> > + compatible = "nvmem-cells";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + macaddr_art_0: macaddr@0 {
> > + reg = <0x0 0x6>;
> > + };
> > +
> > + macaddr_art_6: macaddr@6 {
> > + reg = <0x6 0x6>;
> > + };
> > + };
> > + };
> > --
> > 2.33.1
> >
> >
--
Ansuel
^ permalink raw reply
* Re: [PATCH v3 1/8] media: dt-bindings: media: camss: Fixup vdda regulator descriptions sdm845
From: Rob Herring @ 2022-01-22 0:33 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: bjorn.andersson, robert.foss, jgrahsl, dmitry.baryshkov, mchehab,
vladimir.zapolskiy, jonathan, todor.too, andrey.konovalov,
hverkuil, linux-media, devicetree, hfink, linux-arm-msm, agross
In-Reply-To: <20220111125212.2343184-2-bryan.odonoghue@linaro.org>
On Tue, 11 Jan 2022 12:52:05 +0000, Bryan O'Donoghue wrote:
> If we review the schematic for RB3 Thundercomm document Turbox-845 we see
> that the CAMSS CSI PHY has the same basic power-rail layout as UFS, PCIe
> and USB PHYs.
>
> We should therefore have two regulator declarations as is the case for UFS,
> PCIe and USB.
>
> Cc: devicetree@vger.kernel.org
> Cc: robh@kernel.org
> Reviewed-by: Robert Foss <robert.foss@linaro.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> .../bindings/media/qcom,sdm845-camss.yaml | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v3 2/8] media: dt-bindings: media: camss: Add vdda supply declarations sm8250
From: Rob Herring @ 2022-01-22 0:34 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: jonathan, bjorn.andersson, devicetree, hverkuil, linux-arm-msm,
andrey.konovalov, agross, linux-media, dmitry.baryshkov, hfink,
todor.too, vladimir.zapolskiy, mchehab, robert.foss, jgrahsl
In-Reply-To: <20220111125212.2343184-3-bryan.odonoghue@linaro.org>
On Tue, 11 Jan 2022 12:52:06 +0000, Bryan O'Donoghue wrote:
> Add in missing vdda-phy-supply and vdda-pll-supply declarations. The
> sm8250 USB, PCIe, UFS, DSI and CSI PHYs use a common set of vdda rails.
> Define the CSI vdda regulators in the same way the qmp PHY does.
>
> Cc: devicetree@vger.kernel.org
> Cc: robh@kernel.org
> Reviewed-by: Robert Foss <robert.foss@linaro.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> .../bindings/media/qcom,sm8250-camss.yaml | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-binding: media: hynix,hi846: use $defs/port-base port description
From: Rob Herring @ 2022-01-22 0:38 UTC (permalink / raw)
To: Martin Kepplinger
Cc: devicetree, sakari.ailus, geert, mchehab, laurent.pinchart,
linux-kernel, linux-media
In-Reply-To: <20220111133937.1099917-1-martin.kepplinger@puri.sm>
On Tue, 11 Jan 2022 14:39:36 +0100, Martin Kepplinger wrote:
> This is supposed to fix "make dt_binding_check":
>
> Documentation/devicetree/bindings/media/i2c/hynix,hi846.example.dt.yaml:
> camera@20: port:endpoint: Unevaluated properties are not allowed
> ('link-frequencies', 'data-lanes' were unexpected)
> From schema: Documentation/devicetree/bindings/media/i2c/hynix,hi846.yaml
>
> Fixes: f3ce7200ca18 ("media: dt-bindings: media: document SK Hynix Hi-846 MIPI CSI-2 8M pixel sensor")
> Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
> ---
>
>
> revision history
> ----------------
> v2: thank you, Laurent
> * add unevaluatedProperties: false
> v1:
> https://lore.kernel.org/linux-media/20220110123804.377944-1-martin.kepplinger@puri.sm/
>
>
> Documentation/devicetree/bindings/media/i2c/hynix,hi846.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 2/2] dt-bindings: media: hynix,hi846: add link-frequencies description
From: Rob Herring @ 2022-01-22 0:39 UTC (permalink / raw)
To: Martin Kepplinger
Cc: devicetree, linux-kernel, geert, mchehab, linux-media,
laurent.pinchart, sakari.ailus
In-Reply-To: <20220111133937.1099917-2-martin.kepplinger@puri.sm>
On Tue, 11 Jan 2022 14:39:37 +0100, Martin Kepplinger wrote:
> link-frequencies is required but only mentioned in the example. Add
> it to the description.
>
> Fixes: f3ce7200ca18 ("media: dt-bindings: media: document SK Hynix Hi-846 MIPI CSI-2 8M pixel sensor")
> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> Documentation/devicetree/bindings/media/i2c/hynix,hi846.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: mfd: convert to yaml Qualcomm SPMI PMIC
From: Rob Herring @ 2022-01-22 0:47 UTC (permalink / raw)
To: David Heidelberg
Cc: Andy Gross, Bjorn Andersson, Lee Jones, Stephen Boyd,
~okias/devicetree, Caleb Connolly, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <20220111220026.102838-1-david@ixit.cz>
On Tue, Jan 11, 2022 at 11:00:25PM +0100, David Heidelberg wrote:
> Convert Qualcomm SPMI PMIC binding to yaml format.
>
> Additional changes:
> - filled many missing compatibles
>
> Co-developed-by: Caleb Connolly <caleb@connolly.tech>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> to pass tests correctly
> depends on patch "arm64: dts: qcom: pms405: assign device specific compatible"
>
> v2:
> - changed author to myself, kept Caleb as co-author
> - moved nodename to properties
> - add nodenames for pm* with deprecated property
> - add ^$ to pattern properties
> - dropped interrupt-names property
> - added reg prop. to the nodes which have register in nodename
> - added compatible pmx55
>
> .../bindings/mfd/qcom,spmi-pmic.txt | 93 -----------
> .../bindings/mfd/qcom,spmi-pmic.yaml | 156 ++++++++++++++++++
> 2 files changed, 156 insertions(+), 93 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
> create mode 100644 Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
> diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
> new file mode 100644
> index 000000000000..595a22b185fd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
> @@ -0,0 +1,156 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SPMI PMICs multi-function device
> +
> +description: |
> + Some Qualcomm PMICs used with the Snapdragon series SoCs are interfaced
> + to the chip via the SPMI (System Power Management Interface) bus.
> + Support for multiple independent functions are implemented by splitting the
> + 16-bit SPMI peripheral address space into 256 smaller fixed-size regions, 256 bytes
> + each. A function can consume one or more of these fixed-size register regions.
> +
> + The Qualcomm SPMI series includes the PM8941, PM8841, PMA8084, PM8998 and other
> + PMICs. These PMICs use a "QPNP" scheme through SPMI interface.
> + QPNP is effectively a partitioning scheme for dividing the SPMI extended
> + register space up into logical pieces, and set of fixed register
> + locations/definitions within these regions, with some of these regions
> + specifically used for interrupt handling.
> +
> +maintainers:
> + - Stephen Boyd <sboyd@kernel.org>
> +
> +properties:
> + $nodename:
> + oneOf:
> + - pattern: '^pmic@.*$'
> + - pattern: '^pm(a|s)?[0-9]*@.*$'
> + deprecated: true
> +
> + compatible:
> + items:
> + - enum:
> + - qcom,pm660
> + - qcom,pm660l
> + - qcom,pm6150
> + - qcom,pm6150l
> + - qcom,pm6350
> + - qcom,pm7325
> + - qcom,pm8004
> + - qcom,pm8005
> + - qcom,pm8009
> + - qcom,pm8019
> + - qcom,pm8110
> + - qcom,pm8150
> + - qcom,pm8150b
> + - qcom,pm8150l
> + - qcom,pm8226
> + - qcom,pm8350
> + - qcom,pm8350b
> + - qcom,pm8350c
> + - qcom,pm8841
> + - qcom,pm8909
> + - qcom,pm8916
> + - qcom,pm8941
> + - qcom,pm8950
> + - qcom,pm8994
> + - qcom,pm8998
> + - qcom,pma8084
> + - qcom,pmd9635
> + - qcom,pmi8950
> + - qcom,pmi8962
> + - qcom,pmi8994
> + - qcom,pmi8998
> + - qcom,pmk8350
> + - qcom,pmm8155au
> + - qcom,pmr735a
> + - qcom,pmr735b
> + - qcom,pms405
> + - qcom,pmx55
> + - qcom,smb2351
> + - const: qcom,spmi-pmic
> +
> + reg: true
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> +
> +patternProperties:
> + '^(labibb|([a-z][a-z0-9]+-)?regulators)$':
> + type: object
> +
> + required:
> + - compatible
> +
> + '@[0-9a-f]+$':
> + type: object
> + description: >
> + Each child node of the PMIC represents a function of it.
> +
> + properties:
> + reg: true
> +
> + interrupts:
> + description: >
> + Interrupts are specified as a 4-tuple. For more information see
> + Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
> +
> + required:
> + - compatible
> +
> + additionalProperties: true
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/spmi/spmi.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + spmi@c440000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0x0c440000 0x1100>,
> + <0x0c600000 0x2000000>,
> + <0x0e600000 0x100000>,
> + <0x0e700000 0xa0000>,
> + <0x0c40a000 0x26000>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + interrupt-controller;
> + #interrupt-cells = <4>;
It's preferred if you just have a minimal 'spmi' bus node rather than
something complete and probably duplicated from the "qcom,spmi-pmic-arb"
binding.
> + cell-index = <0>;
That shouldn't be valid.
> +
> + pmi8998_lsid0: pmic@2 {
> + compatible = "qcom,pmi8998", "qcom,spmi-pmic";
> + reg = <0x2 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
Would be nice to show some regulators...
> + pmi8998_gpio: gpios@c000 {
> + compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + gpio-ranges = <&pmi8998_gpio 0 0 14>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> + };
> --
> 2.34.1
>
>
^ permalink raw reply
* Re: [PATCH V2 1/3] dt-bindings: spi: Convert spi-slave-mt27xx to json-schema
From: Rob Herring @ 2022-01-22 0:53 UTC (permalink / raw)
To: Leilk Liu
Cc: Mark Brown, Matthias Brugger, devicetree, linux-kernel,
linux-arm-kernel, linux-spi, linux-mediatek
In-Reply-To: <20220112103609.17421-2-leilk.liu@mediatek.com>
On Wed, Jan 12, 2022 at 06:36:07PM +0800, Leilk Liu wrote:
> Convert Mediatek ARM SOC's SPI Slave controller binding
> to json-schema format.
>
> Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
> ---
> .../spi/mediatek,spi-slave-mt27xx.yaml | 73 +++++++++++++++++++
> .../bindings/spi/spi-slave-mt27xx.txt | 33 ---------
> 2 files changed, 73 insertions(+), 33 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml
> delete mode 100644 Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt
>
> diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml
> new file mode 100644
> index 000000000000..3364fff08cca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/mediatek,spi-slave-mt27xx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SPI Slave controller for MediaTek ARM SoCs
> +
> +maintainers:
> + - Leilk Liu <leilk.liu@mediatek.com>
> +
> +allOf:
> + - $ref: /spi/spi-controller.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - mediatek,mt2712-spi-slave
> + - items:
> + - enum:
> + - mediatek,mt8195-spi-slave
Just:
enum:
- mediatek,mt2712-spi-slave
- mediatek,mt8195-spi-slave
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: clock used for the clock gate
Just 'maxItems: 1'
> +
> + clock-names:
> + items:
> + - const: spi
> +
> + assigned-clocks:
> + maxItems: 1
> + description: |
> + The mux clock for the given platform.
> +
> + assigned-clock-parents:
> + maxItems: 1
> + description: |
> + The parent of mux clock for the given platform.
You can drop assigned-clocks. They are always allowed on nodes with
'clocks'.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt2712-clk.h>
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + spi@10013000 {
> + compatible = "mediatek,mt2712-spi-slave";
> + reg = <0x10013000 0x100>;
> + interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_INFRA_AO_SPI1>;
> + clock-names = "spi";
> + assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
> + };
^ permalink raw reply
* Re: [PATCH V2 2/3] dt-bindings: spi: Convert spi-mt65xx to json-schema
From: Rob Herring @ 2022-01-22 0:57 UTC (permalink / raw)
To: Leilk Liu
Cc: Mark Brown, Matthias Brugger, devicetree, linux-kernel,
linux-arm-kernel, linux-spi, linux-mediatek
In-Reply-To: <20220112103609.17421-3-leilk.liu@mediatek.com>
On Wed, Jan 12, 2022 at 06:36:08PM +0800, Leilk Liu wrote:
> Convert Mediatek ARM SOC's SPI Master controller binding
> to json-schema format.
>
> Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
> ---
> .../bindings/spi/mediatek,spi-mt65xx.yaml | 99 +++++++++++++++++++
> .../devicetree/bindings/spi/spi-mt65xx.txt | 68 -------------
> 2 files changed, 99 insertions(+), 68 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
> delete mode 100644 Documentation/devicetree/bindings/spi/spi-mt65xx.txt
>
> diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
> new file mode 100644
> index 000000000000..71f0cf6e5d70
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
> @@ -0,0 +1,99 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SPI Bus controller for MediaTek ARM SoCs
> +
> +maintainers:
> + - Leilk Liu <leilk.liu@mediatek.com>
> +
> +allOf:
> + - $ref: /spi/spi-controller.yaml#
/schemas/spi/spi-controller.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - mediatek,mt7629-spi
> + - const: mediatek,mt7622-spi
> + - items:
> + - enum:
> + - mediatek,mt8516-spi
> + - const: mediatek,mt2712-spi
> + - items:
> + - enum:
> + - mediatek,mt6779-spi
> + - mediatek,mt8192-spi
> + - mediatek,mt8195-spi
> + - const: mediatek,mt6765-spi
> + - const: mediatek,mt2701-spi
> + - const: mediatek,mt2712-spi
> + - const: mediatek,mt6589-spi
> + - const: mediatek,mt6765-spi
> + - const: mediatek,mt6893-spi
> + - const: mediatek,mt7622-spi
> + - const: mediatek,mt8135-spi
> + - const: mediatek,mt8173-spi
> + - const: mediatek,mt8183-spi
All these can be 1 enum.
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: clock used for the parent clock
> + - description: clock used for the muxes clock
> + - description: clock used for the clock gate
> +
> + clock-names:
> + items:
> + - const: parent-clk
> + - const: sel-clk
> + - const: spi-clk
> +
> + mediatek,pad-select:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + maxItems: 4
> + items:
> + enum: [0, 1, 2, 3]
> + description:
> + specify which pins group(ck/mi/mo/cs) spi controller used.
> + This is an array.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - '#address-cells'
> + - '#size-cells'
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8173-clk.h>
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + spi@1100a000 {
> + compatible = "mediatek,mt8173-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x1100a000 0x1000>;
> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&pericfg CLK_PERI_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
> + mediatek,pad-select = <1>, <0>;
> + };
^ permalink raw reply
* Re: [PATCH V2 3/3] dt-bindings: spi: Add compatible for Mediatek MT8186
From: Rob Herring @ 2022-01-22 0:57 UTC (permalink / raw)
To: Leilk Liu
Cc: linux-arm-kernel, Matthias Brugger, devicetree, Mark Brown,
linux-mediatek, linux-spi, Rob Herring, linux-kernel
In-Reply-To: <20220112103609.17421-4-leilk.liu@mediatek.com>
On Wed, 12 Jan 2022 18:36:09 +0800, Leilk Liu wrote:
> This commit adds dt-binding documentation of spi bus for Mediatek MT8186 SoC
> Platform.
>
> Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
> ---
> Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: dmaengine: zynqmp_dma: convert to yaml
From: Rob Herring @ 2022-01-22 0:59 UTC (permalink / raw)
To: Michael Tretter
Cc: robh+dt, michal.simek, devicetree, linux-arm-kernel, kernel,
dmaengine
In-Reply-To: <20220112151541.1328732-2-m.tretter@pengutronix.de>
On Wed, 12 Jan 2022 16:15:39 +0100, Michael Tretter wrote:
> Convert the Xilinx ZynqMP DMA engine bindings to Yaml.
>
> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
> ---
> .../dma/xilinx/xlnx,zynqmp-dma-1.0.yaml | 85 +++++++++++++++++++
> .../bindings/dma/xilinx/zynqmp_dma.txt | 26 ------
> 2 files changed, 85 insertions(+), 26 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
> delete mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>
Applied, thanks!
^ permalink raw reply
* Re: [RFC 17/28] dt-bindings: display: renesas,du: Document r9a07g044l bindings
From: Rob Herring @ 2022-01-22 1:01 UTC (permalink / raw)
To: Biju Das
Cc: David Airlie, Daniel Vetter, Laurent Pinchart, Kieran Bingham,
dri-devel, linux-renesas-soc, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
In-Reply-To: <20220112174612.10773-18-biju.das.jz@bp.renesas.com>
On Wed, Jan 12, 2022 at 05:46:01PM +0000, Biju Das wrote:
> Extend the Renesas DU display bindings to support the r9a07g044l RZ/G2L.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/display/renesas,du.yaml | 54 +++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml
> index 13efea574584..fc050b1088f3 100644
> --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> @@ -40,6 +40,7 @@ properties:
> - renesas,du-r8a77990 # for R-Car E3 compatible DU
> - renesas,du-r8a77995 # for R-Car D3 compatible DU
> - renesas,du-r8a779a0 # for R-Car V3U compatible DU
> + - renesas,du-r9a07g044l # for RZ/G2L compatible DU
>
> reg:
> maxItems: 1
> @@ -824,6 +825,59 @@ allOf:
> - reset-names
> - renesas,vsps
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,du-r9a07g044l
> + then:
> + properties:
> + clocks:
> + items:
> + - description: LCDC Main clock
> + - description: LCDC Register Access Clock
> + - description: LCDC Video Clock
> +
> + clock-names:
> + items:
> + - const: du.0
> + - const: pclk
> + - const: vclk
> +
> + interrupts:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + items:
> + - const: du.0
> +
> + ports:
> + properties:
> + port@0:
> + description: DPAD 0
> + port@1:
> + description: DSI 0
> + port@2: false
> + port@3: false
> +
> + required:
> + - port@0
> + - port@1
> +
> + renesas,vsps:
> + minItems: 1
The minimum number of items is 1 by default if not otherwise specified.
maxItems: 1 ???
> +
> + required:
> + - clock-names
> + - interrupts
> + - resets
> + - reset-names
> + - renesas,vsps
> +
> additionalProperties: false
>
> examples:
> --
> 2.17.1
>
>
^ permalink raw reply
* Re: [RFC 19/28] media: dt-bindings: media: renesas,vsp1: Document RZ/{G2L,V2L} VSPD bindings
From: Rob Herring @ 2022-01-22 1:02 UTC (permalink / raw)
To: Biju Das
Cc: Mauro Carvalho Chehab, Laurent Pinchart, Kieran Bingham,
linux-media, linux-renesas-soc, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
In-Reply-To: <20220112174612.10773-20-biju.das.jz@bp.renesas.com>
On Wed, Jan 12, 2022 at 05:46:03PM +0000, Biju Das wrote:
> Document VSPD found in RZ/G2L and RZ/V2L family SoC's.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/media/renesas,vsp1.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> index 990e9c1dbc43..b27ee23d2b29 100644
> --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> @@ -19,6 +19,7 @@ properties:
> enum:
> - renesas,vsp1 # R-Car Gen2 and RZ/G1
> - renesas,vsp2 # R-Car Gen3 and RZ/G2
> + - renesas,vsp2-r9a07g044 # RZ/G2L and RZ/V2L
>
> reg:
> maxItems: 1
> @@ -27,7 +28,8 @@ properties:
> maxItems: 1
>
> clocks:
> - maxItems: 1
> + minItems: 1
> + maxItems: 3
You have to define what each one is once you have more than 1.
>
> power-domains:
> maxItems: 1
> --
> 2.17.1
>
>
^ permalink raw reply
* Re: [RFC 21/28] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
From: Rob Herring @ 2022-01-22 1:05 UTC (permalink / raw)
To: Biju Das
Cc: David Airlie, Daniel Vetter, dri-devel, devicetree,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
In-Reply-To: <20220112174612.10773-22-biju.das.jz@bp.renesas.com>
On Wed, Jan 12, 2022 at 05:46:05PM +0000, Biju Das wrote:
> The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
> can operate in DSI mode, with up to four data lanes.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/display/bridge/renesas,dsi.yaml | 143 ++++++++++++++++++
> 1 file changed, 143 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> new file mode 100644
> index 000000000000..8e56a9c53cc5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> @@ -0,0 +1,143 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas R-Car MIPI DSI Encoder
> +
> +maintainers:
> + - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +description: |
> + This binding describes the MIPI DSI encoder embedded in the Renesas
> + RZ/G2L family of SoC's. The encoder can operate in DSI mode with up
> + to four data lanes.
Need a ref to dsi-controller.yaml.
> +
> +properties:
> + compatible:
> + enum:
> + - renesas,r9a07g044-mipi-dsi # for RZ/G2L
> +
> + reg:
> + items:
> + - description: Link register
> + - description: D-PHY register
D-PHY isn't a separate block?
> +
> + clocks:
> + items:
> + - description: DSI D-PHY PLL multiplied clock
> + - description: DSI D-PHY system clock
> + - description: DSI AXI bus clock
> + - description: DSI Register access clock
> + - description: DSI Video clock
> + - description: DSI D_PHY Escape mode Receive clock
> +
> + clock-names:
> + items:
> + - const: pllclk
> + - const: sysclk
> + - const: aclk
> + - const: pclk
> + - const: vclk
> + - const: lpclk
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + items:
> + - description: MIPI_DSI_CMN_RSTB
> + - description: MIPI_DSI_ARESET_N
> + - description: MIPI_DSI_PRESET_N
> +
> + reset-names:
> + items:
> + - const: rst
> + - const: arst
> + - const: prst
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Parallel input port
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: DSI output port
> +
> + properties:
> + endpoint:
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + required:
> + - port@0
> + - port@1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - power-domains
> + - resets
> + - reset-names
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> + dsi0: dsi@10860000 {
> + compatible = "renesas,r9a07g044-mipi-dsi";
> + reg = <0x10860000 0x10000>,
> + <0x10850000 0x10000>;
> + power-domains = <&cpg>;
> + clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
> + <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
> + <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
> + <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
> + <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
> + <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
> + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
> + resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
> + <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
> + <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
> + reset-names = "rst", "arst", "prst";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&du_out_dsi0>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + data-lanes = <1 2 3 4>;
> + remote-endpoint = <&adv7535_in>;
> + };
> + };
> + };
> + };
> +...
> --
> 2.17.1
>
>
^ permalink raw reply
* Re: [PATCH v2 6/6] dt-bindings:net:wireless:mediatek,mt76: add disable-radar-offchan
From: Rob Herring @ 2022-01-22 1:07 UTC (permalink / raw)
To: Lorenzo Bianconi
Cc: lorenzo.bianconi, owen.peng, evelyn.tsai, nbd, ryder.lee,
devicetree, linux-wireless
In-Reply-To: <221dab8bcc95160652e608def16d822da78717bd.1642009736.git.lorenzo@kernel.org>
On Wed, 12 Jan 2022 18:53:55 +0100, Lorenzo Bianconi wrote:
> Add the capability to disable/enable radar/CAC detection running on
> a dedicated offchannel chain available on some hw.
> Offchannel radar/CAC detection allows to avoid CAC downtime switching
> on a different channel during CAC detection on the selected radar
> channel.
>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
> .../devicetree/bindings/net/wireless/mediatek,mt76.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH net-next 1/2] net: dsa: microchip: Document property to disable reference clock
From: Rob Herring @ 2022-01-22 1:08 UTC (permalink / raw)
To: Robert Hancock
Cc: devicetree, netdev, davem, marex, woojung.huh, andrew,
UNGLinuxDriver, olteanv, f.fainelli, kuba, robh+dt,
vivien.didelot
In-Reply-To: <20220112182251.876098-2-robert.hancock@calian.com>
On Wed, 12 Jan 2022 12:22:50 -0600, Robert Hancock wrote:
> Document the new microchip,synclko-disable property which can be
> specified to disable the reference clock output from the device if not
> required by the board design.
>
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> ---
> Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v3 14/16] arm64: dts: fsd: Add initial device tree support
From: Stefan Wahren @ 2022-01-22 1:36 UTC (permalink / raw)
To: Alim Akhtar, linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, krzysztof.kozlowski, s.nawrocki,
linux-samsung-soc, pankaj.dubey, sboyd, linux-fsd, Arjun K V,
Aswani Reddy, Ajay Kumar, Sriranjani P, Chandrasekar R,
Shashank Prashar
In-Reply-To: <20220121172840.12121-15-alim.akhtar@samsung.com>
Hi Alim,
Am 21.01.22 um 18:28 schrieb Alim Akhtar:
> Add initial device tree support for "Full Self-Driving" (FSD) SoC
> This SoC contain three clusters of four cortex-a72 CPUs and various
> peripheral IPs.
>
> Cc: linux-fsd@tesla.com
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Signed-off-by: Arjun K V <arjun.kv@samsung.com>
> Signed-off-by: Aswani Reddy <aswani.reddy@samsung.com>
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> Signed-off-by: Sriranjani P <sriranjani.p@samsung.com>
> Signed-off-by: Chandrasekar R <rcsekar@samsung.com>
> Signed-off-by: Shashank Prashar <s.prashar@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> MAINTAINERS | 8 +
> arch/arm64/Kconfig.platforms | 6 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/tesla/Makefile | 3 +
> arch/arm64/boot/dts/tesla/fsd-evb.dts | 39 ++
> arch/arm64/boot/dts/tesla/fsd.dtsi | 651 ++++++++++++++++++++++++++
> 6 files changed, 708 insertions(+)
> create mode 100644 arch/arm64/boot/dts/tesla/Makefile
> create mode 100644 arch/arm64/boot/dts/tesla/fsd-evb.dts
> create mode 100644 arch/arm64/boot/dts/tesla/fsd.dtsi
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 27730a5a6345..ed1c10c26e5b 100644
> diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
> new file mode 100644
> index 000000000000..9a2b88f58c13
> --- /dev/null
> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
> @@ -0,0 +1,651 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Tesla Full Self-Driving SoC device tree source
> + *
> + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
> + * https://www.samsung.com
> + * Copyright (c) 2017-2022 Tesla, Inc.
> + * https://www.tesla.com
> + */
> +
> +#include <dt-bindings/clock/fsd-clk.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
...
> + pwm_1: pwm@14110000 {
> + compatible = "samsung,exynos4210-pwm";
> + reg = <0x0 0x14110000 0x0 0x100>;
> + samsung,pwm-outputs = <0>, <1>, <2>, <3>;
> + #pwm-cells = <3>;
> + clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>;
> + clock-names = "timers";
> + status = "disabled";
> + };
> +
> + hsi2c_0: hsi2c@14200000 {
since this is a i2c interface the node name should be changed to i2c:
hi2c_0: i2c@...
and the following ones.
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x0 0x14200000 0x0 0x1000>;
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c0_bus>;
> + clocks = <&clock_peric PERIC_PCLK_HSI2C0>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_1: hsi2c@14210000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x0 0x14210000 0x0 0x1000>;
> + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c1_bus>;
> + clocks = <&clock_peric PERIC_PCLK_HSI2C1>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_2: hsi2c@14220000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x0 0x14220000 0x0 0x1000>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c2_bus>;
> + clocks = <&clock_peric PERIC_PCLK_HSI2C2>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_3: hsi2c@14230000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x0 0x14230000 0x0 0x1000>;
> + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c3_bus>;
> + clocks = <&clock_peric PERIC_PCLK_HSI2C3>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_4: hsi2c@14240000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x0 0x14240000 0x0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c4_bus>;
> + clocks = <&clock_peric PERIC_PCLK_HSI2C4>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_5: hsi2c@14250000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x0 0x14250000 0x0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c5_bus>;
> + clocks = <&clock_peric PERIC_PCLK_HSI2C5>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_6: hsi2c@14260000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x0 0x14260000 0x0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c6_bus>;
> + clocks = <&clock_peric PERIC_PCLK_HSI2C6>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_7: hsi2c@14270000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x0 0x14270000 0x0 0x1000>;
> + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c7_bus>;
> + clocks = <&clock_peric PERIC_PCLK_HSI2C7>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> + };
> +};
^ permalink raw reply
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