* Re: [PATCH v2 4/5] drivers: bus: add driver for initializing the SSC bus on (some) qcom SoCs
From: Philipp Zabel @ 2022-01-24 12:22 UTC (permalink / raw)
To: michael.srba, Andy Gross, Bjorn Andersson, Rob Herring,
Stephen Boyd
Cc: Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree
In-Reply-To: <20220124112740.22790-1-michael.srba@seznam.cz>
Hi Michael,
On Mon, 2022-01-24 at 12:27 +0100, michael.srba@seznam.cz wrote:
[...]
> +
> +static int qcom_ssc_block_bus_init(struct device *dev)
> +{
> + int ret;
> +
> + struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev);
> +
> + clk_prepare_enable(data->xo_clk);
> + clk_prepare_enable(data->aggre2_clk);
> +
> + clk_prepare_enable(data->gcc_im_sleep_clk);
Those should be disabled on failure below, otherwise they could
accumulate enable_counts with multiple failed block_bus_init calls.
(Assuming that the reset_control_* can fail in practice.)
> +
> + reg32_clear_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5));
> + reg32_clear_bits(data->reg_mpm_sscaon_config1, BIT(31));
> +
> + clk_disable(data->aggre2_north_clk);
Where was this clock enabled before?
> +
> + ret = reset_control_deassert(data->ssc_reset);
> + if (ret) {
> + dev_err(dev, "error deasserting ssc_reset: %d\n", ret);
> + return ret;
And leave the aggre2_north_clk disabled? See below.
> + }
> +
> + clk_prepare_enable(data->aggre2_north_clk);
> +
> + ret = reset_control_deassert(data->ssc_bcr);
> + if (ret) {
> + dev_err(dev, "error deasserting ssc_bcr: %d\n", ret);
> + return ret;
And leave the aggre2_north_clk enabled? This needs to be consistent.
> + }
> +
> + regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 0);
> +
> + clk_prepare_enable(data->ssc_xo_clk);
> +
> + clk_prepare_enable(data->ssc_ahbs_clk);
> +
> + return 0;
> +}
> +
> +static int qcom_ssc_block_bus_deinit(struct device *dev)
Why does this return int when its result is never checked?
> +{
> + int ret;
> +
> + struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev);
> +
> + clk_disable(data->ssc_xo_clk);
> + clk_disable(data->ssc_ahbs_clk);
> +
> + ret = reset_control_assert(data->ssc_bcr);
> + if (ret) {
> + dev_err(dev, "error asserting ssc_bcr: %d\n", ret);
> + return ret;
And leave clocks below enabled?
> + }
> +
> + regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 1);
> +
> + reg32_set_bits(data->reg_mpm_sscaon_config1, BIT(31));
> + reg32_set_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5));
> +
> + ret = reset_control_assert(data->ssc_reset);
> + if (ret) {
> + dev_err(dev, "error asserting ssc_reset: %d\n", ret);
> + return ret;
Same as above.
> + }
> +
> + clk_disable(data->gcc_im_sleep_clk);
> +
> + clk_disable(data->aggre2_north_clk);
> +
> + clk_disable(data->aggre2_clk);
> + clk_disable(data->xo_clk);
> +
> + return 0;
> +}
[...]
> +static int qcom_ssc_block_bus_probe(struct platform_device *pdev)
> +{
> + struct qcom_ssc_block_bus_data *data;
> + struct device_node *np = pdev->dev.of_node;
> + struct of_phandle_args halt_args;
> + struct resource *res;
> + int ret;
> +
> + if (np)
> + of_platform_populate(np, NULL, NULL, &pdev->dev);
> +
> + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, data);
> +
> + data->pd_names = qcom_ssc_block_pd_names;
> + data->num_pds = ARRAY_SIZE(qcom_ssc_block_pd_names);
> +
> + ret = qcom_ssc_block_bus_pds_attach(&pdev->dev, data->pds, data->pd_names, data->num_pds);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "error when attaching power domains: %d\n", ret);
> + return ret;
> + }
> +
> + ret = qcom_ssc_block_bus_pds_enable(data->pds, data->num_pds);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "error when enabling power domains: %d\n", ret);
> + return ret;
> + }
> +
> + // the meaning of the bits in these two registers is sadly not documented,
> + // the set/clear operations are just copying what qcom does
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0");
> + data->reg_mpm_sscaon_config0 = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(data->reg_mpm_sscaon_config0)) {
> + ret = PTR_ERR(data->reg_mpm_sscaon_config0);
> + dev_err(&pdev->dev, "failed to ioremap mpm_sscaon_config0 (err: %d)\n", ret);
> + return ret;
> + }
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0");
> + data->reg_mpm_sscaon_config1 = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(data->reg_mpm_sscaon_config1)) {
> + ret = PTR_ERR(data->reg_mpm_sscaon_config1);
> + dev_err(&pdev->dev, "failed to ioremap mpm_sscaon_config1 (err: %d)\n", ret);
> + return ret;
> + }
> +
> + data->ssc_bcr = devm_reset_control_get_exclusive(&pdev->dev, "ssc_bcr");
> + if (IS_ERR(data->ssc_bcr)) {
> + ret = PTR_ERR(data->ssc_bcr);
> + dev_err(&pdev->dev, "failed to acquire reset: scc_bcr (err: %d)\n", ret);
> + return ret;
Why check for -EPROBE_DEFER for the clocks but not here?
You could use dev_err_probe() to simplify all these error returns.
regards
Philipp
^ permalink raw reply
* [PATCH v3 5/5] arm64: dts: qcom: msm8998: reserve potentially inaccessible clocks With the gcc driver now being more complete and describing clocks which might not always be write-accessible to the OS, conservatively specify all such clocks as protected in the SoC dts. The board dts - or even user-supplied dts - can override this property to reflect the actual configuration.
From: michael.srba @ 2022-01-24 12:18 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
Philipp Zabel
Cc: Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree,
Michael Srba, Michael Srba
In-Reply-To: <20220124121853.23600-1-michael.srba@seznam.cz>
From: Michael Srba <michael.srba@seznam.cz>
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
---
CHANGES:
- v2: add this patch
- v3: fix missing Signed-off-by
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index f273bc1ff629..cff83af8c12e 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -863,6 +863,12 @@ gcc: clock-controller@100000 {
clock-names = "xo", "sleep_clk";
clocks = <&xo>, <&sleep_clk>;
+
+ // be conservative by default, the board dts
+ // can overwrite this list
+ protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
+ <SSC_XO>,
+ <SSC_CNOC_AHBS_CLK>;
};
rpm_msg_ram: sram@778000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v3 3/5] dt-bindings: bus: add device tree bindings for qcom,ssc-block-bus
From: michael.srba @ 2022-01-24 12:18 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
Philipp Zabel
Cc: Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree,
Michael Srba
In-Reply-To: <20220124121853.23600-1-michael.srba@seznam.cz>
From: Michael Srba <Michael.Srba@seznam.cz>
This patch adds bindings for the AHB bus which exposes the SCC block in
the global address space. This bus (and the SSC block itself) is present
on certain qcom SoCs.
In typical configuration, this bus (as some of the clocks and registers
that we need to manipulate) is not accessible to the OS, and the
resources on this bus are indirectly accessed by communicating with a
hexagon CPU core residing in the SSC block. In this configuration, the
hypervisor is the one performing the bus initialization for the purposes
of bringing the haxagon CPU core out of reset.
However, it is possible to change the configuration, in which case this
binding serves to allow the OS to initialize the bus.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
---
CHANGES:
- v2: fix issues caught by by dt-schema
- v3: none
---
Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml | 159 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 159 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml
diff --git a/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml
new file mode 100644
index 000000000000..f3f4a991337b
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
+
+maintainers:
+ - Michael Srba <Michael.Srba@seznam.cz>
+
+description: |
+ This binding describes the dependencies (clocks, resets, power domains) which
+ need to be turned on in a sequence before communication over the AHB bus
+ becomes possible.
+
+ Additionally, the reg property is used to pass to the driver the location of
+ two sadly undocumented registers which need to be poked as part of the sequence.
+
+ Currently, this binding is known to apply to msm8998. If the binding applies
+ in it's current form, the compatible should contain "qcom,ssc-block-bus-v1".
+ If the binding needs tweaking in order to apply to another SoC, this binding
+ shall be extended.
+
+
+properties:
+ compatible:
+ contains:
+ items:
+ - enum: [ qcom,ssc-block-bus-v1 ]
+ - const: qcom,ssc-block-bus
+ description:
+ Shall contain "qcom,ssc-block-bus"
+
+ reg:
+ description: |
+ Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1
+ registers
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: mpm_sscaon_config0
+ - const: mpm_sscaon_config1
+
+ '#address-cells':
+ enum: [ 1, 2 ]
+
+ '#size-cells':
+ enum: [ 1, 2 ]
+
+ ranges: true
+
+ clocks:
+ description: |
+ Clock phandles for the xo, aggre2, gcc_im_sleep, aggre2_north,
+ ssc_xo and ssc_ahbs clocks
+ minItems: 6
+ maxItems: 6
+
+ clock-names:
+ items:
+ - const: xo
+ - const: aggre2
+ - const: gcc_im_sleep
+ - const: aggre2_north
+ - const: ssc_xo
+ - const: ssc_ahbs
+
+ power-domains:
+ description: Power domain phandles for the ssc_cx and ssc_mx power domains
+ minItems: 2
+ maxItems: 2
+
+ power-domain-names:
+ items:
+ - const: ssc_cx
+ - const: ssc_mx
+
+ resets:
+ description: |
+ Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the
+ branch control register associated with the ssc_xo and ssc_ahbs clocks)
+ minItems: 2
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: ssc_reset
+ - const: ssc_bcr
+
+ qcom,halt-regs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle reference to a syscon representing TCSR followed by the
+ offset within syscon for the ssc AXI halt register.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - '#address-cells'
+ - '#size-cells'
+ - ranges
+ - clocks
+ - clock-names
+ - power-domains
+ - power-domain-names
+ - resets
+ - reset-names
+ - qcom,halt-regs
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8998.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ssc_ahb_slave: bus@10ac008 { // devices under this node are physically located in the SSC block, connected to an ssc-internal bus;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ compatible = "qcom,ssc-block-bus";
+ reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
+ reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
+
+ clocks = <&xo>,
+ <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
+ <&gcc GCC_IM_SLEEP>,
+ <&gcc AGGRE2_SNOC_NORTH_AXI>,
+ <&gcc SSC_XO>,
+ <&gcc SSC_CNOC_AHBS_CLK>;
+ clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
+
+ resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;
+ reset-names = "ssc_reset", "ssc_bcr";
+
+ power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
+ power-domain-names = "ssc_cx", "ssc_mx";
+
+ qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
+
+ ssc_tlmm: pinctrl@5e10000 {
+ compatible = "qcom,msm8998-ssc-tlmm-pinctrl";
+ reg = <0x5E10000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ssc_tlmm 0 0 20>;
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related
* [PATCH v3 1/5] dt-bindings: clock: gcc-msm8998: Add definitions of SSC-related clocks
From: michael.srba @ 2022-01-24 12:18 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
Philipp Zabel
Cc: Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree,
Michael Srba
From: Michael Srba <Michael.Srba@seznam.cz>
This patch adds definitions of four clocks which need to be manipulated
in order to initialize the AHB bus which exposes the SCC block in the
global address space.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
---
CHANGES:
- v2: none
- v3: none
---
include/dt-bindings/clock/qcom,gcc-msm8998.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
index 72c99e486d86..1badb4f9c58f 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8998.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -186,6 +186,10 @@
#define UFS_UNIPRO_CORE_CLK_SRC 177
#define GCC_MMSS_GPLL0_CLK 178
#define HMSS_GPLL0_CLK_SRC 179
+#define GCC_IM_SLEEP 180
+#define AGGRE2_SNOC_NORTH_AXI 181
+#define SSC_XO 182
+#define SSC_CNOC_AHBS_CLK 183
#define PCIE_0_GDSC 0
#define UFS_GDSC 1
--
2.34.1
^ permalink raw reply related
* [PATCH v3 2/5] clk: qcom: gcc-msm8998: add SSC-related clocks
From: michael.srba @ 2022-01-24 12:18 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
Philipp Zabel
Cc: Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree,
Michael Srba
In-Reply-To: <20220124121853.23600-1-michael.srba@seznam.cz>
From: Michael Srba <Michael.Srba@seznam.cz>
This patch adds four clocks which need to be manipulated in order to
initialize the AHB bus which exposes the SCC block in the global address
space.
Care should be taken not to write to these registers unless the device is
known to be configured such that writing to these registers from Linux
is permitted.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
---
CHANGES:
- v2: none
- v3: none
---
drivers/clk/qcom/gcc-msm8998.c | 56 ++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 407e2c5caea4..2d14c3d672fc 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -2833,6 +2833,58 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {
},
};
+static struct clk_branch gcc_im_sleep_clk = {
+ .halt_reg = 0x4300C,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4300C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_im_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch aggre2_snoc_north_axi_clk = {
+ .halt_reg = 0x83010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x83010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "aggre2_snoc_north_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ssc_xo_clk = {
+ .halt_reg = 0x63018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x63018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "ssc_xo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ssc_cnoc_ahbs_clk = {
+ .halt_reg = 0x6300C,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6300C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "ssc_cnoc_ahbs_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.gds_hw_ctrl = 0x0,
@@ -3036,6 +3088,10 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
[GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
+ [GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr,
+ [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr,
+ [SSC_XO] = &ssc_xo_clk.clkr,
+ [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr,
};
static struct gdsc *gcc_msm8998_gdscs[] = {
--
2.34.1
^ permalink raw reply related
* [PATCH v3 4/5] drivers: bus: add driver for initializing the SSC bus on (some) qcom SoCs
From: michael.srba @ 2022-01-24 12:18 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
Philipp Zabel
Cc: Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree,
Michael Srba
In-Reply-To: <20220124121853.23600-1-michael.srba@seznam.cz>
From: Michael Srba <Michael.Srba@seznam.cz>
This patch adds bindings for the AHB bus which exposes the SCC block in
the global address space. This bus (and the SSC block itself) is present
on certain qcom SoCs.
In typical configuration, this bus (as some of the clocks and registers
that we need to manipulate) is not accessible to Linux, and the resources
on this bus are indirectly accessed by communicating with a hexagon CPU
core residing in the SSC block. In this configuration, the hypervisor is
the one performing the bus initialization for the purposes of bringing
the haxagon CPU core out of reset.
However, it is possible to change the configuration, in which case this
driver will initialize the bus.
In combination with drivers for resources on the SSC bus, this driver can
aid in debugging, and for example with a TLMM driver can be used to
directly access SSC-dedicated GPIO pins, removing the need to commit
to a particular usecase during hw design.
Finally, until open firmware for the hexagon core is available, this
approach allows for using sensors hooked up to SSC-dedicated GPIO pins
on mainline Linux simply by utilizing the existing in-tree drivers for
these sensors.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
---
CHANGES:
- v2: none
- v3: fix clang warning
---
drivers/bus/Kconfig | 6 +
drivers/bus/Makefile | 1 +
drivers/bus/qcom-ssc-block-bus.c | 365 +++++++++++++++++++++++++++++++
3 files changed, 372 insertions(+)
create mode 100644 drivers/bus/qcom-ssc-block-bus.c
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 3c68e174a113..f2b2e3098491 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -173,6 +173,12 @@ config SUNXI_RSB
with various RSB based devices, such as AXP223, AXP8XX PMICs,
and AC100/AC200 ICs.
+config QCOM_SSC_BLOCK_BUS
+ bool "Qualcomm SSC Block Bus Init Driver"
+ help
+ Say y here to enable support for initializing the bus that connects the SSC block's internal
+ bus to the cNoC on (some) qcom SoCs
+
config TEGRA_ACONNECT
tristate "Tegra ACONNECT Bus Driver"
depends on ARCH_TEGRA_210_SOC
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 52c2f35a26a9..e6756e83a9c4 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o
+obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o
obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
obj-$(CONFIG_OF) += simple-pm-bus.o
diff --git a/drivers/bus/qcom-ssc-block-bus.c b/drivers/bus/qcom-ssc-block-bus.c
new file mode 100644
index 000000000000..a93c7350a231
--- /dev/null
+++ b/drivers/bus/qcom-ssc-block-bus.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (c) 2021, Michael Srba
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* AXI Halt Register Offsets */
+#define AXI_HALTREQ_REG 0x0
+#define AXI_HALTACK_REG 0x4
+#define AXI_IDLE_REG 0x8
+
+static const char *qcom_ssc_block_pd_names[] = {
+ "ssc_cx",
+ "ssc_mx"
+};
+
+struct qcom_ssc_block_bus_data {
+ int num_pds;
+ const char **pd_names;
+ struct device *pds[ARRAY_SIZE(qcom_ssc_block_pd_names)];
+ char __iomem *reg_mpm_sscaon_config0; // MPM - msm power manager; AON - always-on
+ char __iomem *reg_mpm_sscaon_config1; // that's as much as we know about these
+ struct regmap *halt_map;
+ u32 ssc_axi_halt;
+ struct clk *xo_clk;
+ struct clk *aggre2_clk;
+ struct clk *gcc_im_sleep_clk;
+ struct clk *aggre2_north_clk;
+ struct clk *ssc_xo_clk;
+ struct clk *ssc_ahbs_clk;
+ struct reset_control *ssc_bcr;
+ struct reset_control *ssc_reset;
+};
+
+static void reg32_set_bits(char __iomem *reg, u32 value)
+{
+ u32 tmp = ioread32(reg);
+
+ iowrite32(tmp | value, reg);
+}
+
+static void reg32_clear_bits(char __iomem *reg, u32 value)
+{
+ u32 tmp = ioread32(reg);
+
+ iowrite32(tmp & (~value), reg);
+}
+
+
+static int qcom_ssc_block_bus_init(struct device *dev)
+{
+ int ret;
+
+ struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev);
+
+ clk_prepare_enable(data->xo_clk);
+ clk_prepare_enable(data->aggre2_clk);
+
+ clk_prepare_enable(data->gcc_im_sleep_clk);
+
+ reg32_clear_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5));
+ reg32_clear_bits(data->reg_mpm_sscaon_config1, BIT(31));
+
+ clk_disable(data->aggre2_north_clk);
+
+ ret = reset_control_deassert(data->ssc_reset);
+ if (ret) {
+ dev_err(dev, "error deasserting ssc_reset: %d\n", ret);
+ return ret;
+ }
+
+ clk_prepare_enable(data->aggre2_north_clk);
+
+ ret = reset_control_deassert(data->ssc_bcr);
+ if (ret) {
+ dev_err(dev, "error deasserting ssc_bcr: %d\n", ret);
+ return ret;
+ }
+
+ regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 0);
+
+ clk_prepare_enable(data->ssc_xo_clk);
+
+ clk_prepare_enable(data->ssc_ahbs_clk);
+
+ return 0;
+}
+
+static int qcom_ssc_block_bus_deinit(struct device *dev)
+{
+ int ret;
+
+ struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev);
+
+ clk_disable(data->ssc_xo_clk);
+ clk_disable(data->ssc_ahbs_clk);
+
+ ret = reset_control_assert(data->ssc_bcr);
+ if (ret) {
+ dev_err(dev, "error asserting ssc_bcr: %d\n", ret);
+ return ret;
+ }
+
+ regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 1);
+
+ reg32_set_bits(data->reg_mpm_sscaon_config1, BIT(31));
+ reg32_set_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5));
+
+ ret = reset_control_assert(data->ssc_reset);
+ if (ret) {
+ dev_err(dev, "error asserting ssc_reset: %d\n", ret);
+ return ret;
+ }
+
+ clk_disable(data->gcc_im_sleep_clk);
+
+ clk_disable(data->aggre2_north_clk);
+
+ clk_disable(data->aggre2_clk);
+ clk_disable(data->xo_clk);
+
+ return 0;
+}
+
+
+static int qcom_ssc_block_bus_pds_attach(struct device *dev, struct device **pds,
+ const char **pd_names, size_t num_pds)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < num_pds; i++) {
+ pds[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
+ if (IS_ERR_OR_NULL(pds[i])) {
+ ret = PTR_ERR(pds[i]) ? : -ENODATA;
+ goto unroll_attach;
+ }
+ }
+
+ return num_pds;
+
+unroll_attach:
+ for (i--; i >= 0; i--)
+ dev_pm_domain_detach(pds[i], false);
+
+ return ret;
+};
+
+static void qcom_ssc_block_bus_pds_detach(struct device *dev, struct device **pds, size_t num_pds)
+{
+ int i;
+
+ for (i = 0; i < num_pds; i++)
+ dev_pm_domain_detach(pds[i], false);
+}
+
+static int qcom_ssc_block_bus_pds_enable(struct device **pds, size_t num_pds)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < num_pds; i++) {
+ dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
+ ret = pm_runtime_get_sync(pds[i]);
+ if (ret < 0)
+ goto unroll_pd_votes;
+ }
+
+ return 0;
+
+unroll_pd_votes:
+ for (i--; i >= 0; i--) {
+ dev_pm_genpd_set_performance_state(pds[i], 0);
+ pm_runtime_put(pds[i]);
+ }
+
+ return ret;
+};
+
+static void qcom_ssc_block_bus_pds_disable(struct device **pds, size_t num_pds)
+{
+ int i;
+
+ for (i = 0; i < num_pds; i++) {
+ dev_pm_genpd_set_performance_state(pds[i], 0);
+ pm_runtime_put(pds[i]);
+ }
+}
+
+static int qcom_ssc_block_bus_probe(struct platform_device *pdev)
+{
+ struct qcom_ssc_block_bus_data *data;
+ struct device_node *np = pdev->dev.of_node;
+ struct of_phandle_args halt_args;
+ struct resource *res;
+ int ret;
+
+ if (np)
+ of_platform_populate(np, NULL, NULL, &pdev->dev);
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, data);
+
+ data->pd_names = qcom_ssc_block_pd_names;
+ data->num_pds = ARRAY_SIZE(qcom_ssc_block_pd_names);
+
+ ret = qcom_ssc_block_bus_pds_attach(&pdev->dev, data->pds, data->pd_names, data->num_pds);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "error when attaching power domains: %d\n", ret);
+ return ret;
+ }
+
+ ret = qcom_ssc_block_bus_pds_enable(data->pds, data->num_pds);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "error when enabling power domains: %d\n", ret);
+ return ret;
+ }
+
+ // the meaning of the bits in these two registers is sadly not documented,
+ // the set/clear operations are just copying what qcom does
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0");
+ data->reg_mpm_sscaon_config0 = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->reg_mpm_sscaon_config0)) {
+ ret = PTR_ERR(data->reg_mpm_sscaon_config0);
+ dev_err(&pdev->dev, "failed to ioremap mpm_sscaon_config0 (err: %d)\n", ret);
+ return ret;
+ }
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0");
+ data->reg_mpm_sscaon_config1 = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->reg_mpm_sscaon_config1)) {
+ ret = PTR_ERR(data->reg_mpm_sscaon_config1);
+ dev_err(&pdev->dev, "failed to ioremap mpm_sscaon_config1 (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->ssc_bcr = devm_reset_control_get_exclusive(&pdev->dev, "ssc_bcr");
+ if (IS_ERR(data->ssc_bcr)) {
+ ret = PTR_ERR(data->ssc_bcr);
+ dev_err(&pdev->dev, "failed to acquire reset: scc_bcr (err: %d)\n", ret);
+ return ret;
+ }
+ data->ssc_reset = devm_reset_control_get_exclusive(&pdev->dev, "ssc_reset");
+ if (IS_ERR(data->ssc_reset)) {
+ ret = PTR_ERR(data->ssc_reset);
+ dev_err(&pdev->dev, "failed to acquire reset: ssc_reset: (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->xo_clk = devm_clk_get(&pdev->dev, "xo");
+ if (IS_ERR(data->xo_clk)) {
+ ret = PTR_ERR(data->xo_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: xo (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->aggre2_clk = devm_clk_get(&pdev->dev, "aggre2");
+ if (IS_ERR(data->aggre2_clk)) {
+ ret = PTR_ERR(data->aggre2_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: aggre2 (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->gcc_im_sleep_clk = devm_clk_get(&pdev->dev, "gcc_im_sleep");
+ if (IS_ERR(data->gcc_im_sleep_clk)) {
+ ret = PTR_ERR(data->gcc_im_sleep_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: gcc_im_sleep (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->aggre2_north_clk = devm_clk_get(&pdev->dev, "aggre2_north");
+ if (IS_ERR(data->aggre2_north_clk)) {
+ ret = PTR_ERR(data->aggre2_north_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: aggre2_north (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->ssc_xo_clk = devm_clk_get(&pdev->dev, "ssc_xo");
+ if (IS_ERR(data->ssc_xo_clk)) {
+ ret = PTR_ERR(data->ssc_xo_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: ssc_xo (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->ssc_ahbs_clk = devm_clk_get(&pdev->dev, "ssc_ahbs");
+ if (IS_ERR(data->ssc_ahbs_clk)) {
+ ret = PTR_ERR(data->ssc_ahbs_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: ssc_ahbs (err: %d)\n", ret);
+ return ret;
+ }
+
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, "qcom,halt-regs", 1, 0,
+ &halt_args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
+ return -EINVAL;
+ }
+
+ data->halt_map = syscon_node_to_regmap(halt_args.np);
+ of_node_put(halt_args.np);
+ if (IS_ERR(data->halt_map))
+ return PTR_ERR(data->halt_map);
+
+ data->ssc_axi_halt = halt_args.args[0];
+
+ qcom_ssc_block_bus_init(&pdev->dev);
+
+ return 0;
+}
+
+static int qcom_ssc_block_bus_remove(struct platform_device *pdev)
+{
+ struct qcom_ssc_block_bus_data *data = platform_get_drvdata(pdev);
+
+ qcom_ssc_block_bus_deinit(&pdev->dev);
+
+ iounmap(data->reg_mpm_sscaon_config0);
+ iounmap(data->reg_mpm_sscaon_config1);
+
+ qcom_ssc_block_bus_pds_disable(data->pds, data->num_pds);
+ qcom_ssc_block_bus_pds_detach(&pdev->dev, data->pds, data->num_pds);
+ pm_runtime_disable(&pdev->dev);
+ pm_clk_destroy(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id qcom_ssc_block_bus_of_match[] = {
+ { .compatible = "qcom,ssc-block-bus", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, qcom_ssc_block_bus_of_match);
+
+static struct platform_driver qcom_ssc_block_bus_driver = {
+ .probe = qcom_ssc_block_bus_probe,
+ .remove = qcom_ssc_block_bus_remove,
+ .driver = {
+ .name = "qcom-ssc-block-bus",
+ .of_match_table = qcom_ssc_block_bus_of_match,
+ },
+};
+
+module_platform_driver(qcom_ssc_block_bus_driver);
+
+MODULE_DESCRIPTION("A driver for handling the init sequence needed for accessing the SSC block on (some) qcom SoCs over AHB");
+MODULE_AUTHOR("Michael Srba <Michael.Srba@seznam.cz>");
+MODULE_LICENSE("GPL v2");
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 3/3] arm64: zynqmp: Rename dma to dma-controller
From: Michal Simek @ 2022-01-24 12:18 UTC (permalink / raw)
To: Michael Tretter, devicetree, linux-arm-kernel, dmaengine
Cc: robh+dt, michal.simek, kernel
In-Reply-To: <20220112151541.1328732-4-m.tretter@pengutronix.de>
On 1/12/22 16:15, Michael Tretter wrote:
> The ZynqMP dma engines are actually dma-controllers as specified by the
> device tree binding. Rename the device tree nodes accordingly.
>
> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 32 +++++++++++++-------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 6d96b6b99f84..3e15391e5b37 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -254,7 +254,7 @@ pmu@9000 {
> };
>
> /* GDMA */
> - fpd_dma_chan1: dma@fd500000 {
> + fpd_dma_chan1: dma-controller@fd500000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd500000 0x0 0x1000>;
> @@ -267,7 +267,7 @@ fpd_dma_chan1: dma@fd500000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan2: dma@fd510000 {
> + fpd_dma_chan2: dma-controller@fd510000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd510000 0x0 0x1000>;
> @@ -280,7 +280,7 @@ fpd_dma_chan2: dma@fd510000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan3: dma@fd520000 {
> + fpd_dma_chan3: dma-controller@fd520000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd520000 0x0 0x1000>;
> @@ -293,7 +293,7 @@ fpd_dma_chan3: dma@fd520000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan4: dma@fd530000 {
> + fpd_dma_chan4: dma-controller@fd530000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd530000 0x0 0x1000>;
> @@ -306,7 +306,7 @@ fpd_dma_chan4: dma@fd530000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan5: dma@fd540000 {
> + fpd_dma_chan5: dma-controller@fd540000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd540000 0x0 0x1000>;
> @@ -319,7 +319,7 @@ fpd_dma_chan5: dma@fd540000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan6: dma@fd550000 {
> + fpd_dma_chan6: dma-controller@fd550000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd550000 0x0 0x1000>;
> @@ -332,7 +332,7 @@ fpd_dma_chan6: dma@fd550000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan7: dma@fd560000 {
> + fpd_dma_chan7: dma-controller@fd560000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd560000 0x0 0x1000>;
> @@ -345,7 +345,7 @@ fpd_dma_chan7: dma@fd560000 {
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> - fpd_dma_chan8: dma@fd570000 {
> + fpd_dma_chan8: dma-controller@fd570000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xfd570000 0x0 0x1000>;
> @@ -375,7 +375,7 @@ gic: interrupt-controller@f9010000 {
> * These dma channels, Users should ensure that these dma
> * Channels are allowed for non secure access.
> */
> - lpd_dma_chan1: dma@ffa80000 {
> + lpd_dma_chan1: dma-controller@ffa80000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffa80000 0x0 0x1000>;
> @@ -388,7 +388,7 @@ lpd_dma_chan1: dma@ffa80000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan2: dma@ffa90000 {
> + lpd_dma_chan2: dma-controller@ffa90000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffa90000 0x0 0x1000>;
> @@ -401,7 +401,7 @@ lpd_dma_chan2: dma@ffa90000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan3: dma@ffaa0000 {
> + lpd_dma_chan3: dma-controller@ffaa0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffaa0000 0x0 0x1000>;
> @@ -414,7 +414,7 @@ lpd_dma_chan3: dma@ffaa0000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan4: dma@ffab0000 {
> + lpd_dma_chan4: dma-controller@ffab0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffab0000 0x0 0x1000>;
> @@ -427,7 +427,7 @@ lpd_dma_chan4: dma@ffab0000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan5: dma@ffac0000 {
> + lpd_dma_chan5: dma-controller@ffac0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffac0000 0x0 0x1000>;
> @@ -440,7 +440,7 @@ lpd_dma_chan5: dma@ffac0000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan6: dma@ffad0000 {
> + lpd_dma_chan6: dma-controller@ffad0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffad0000 0x0 0x1000>;
> @@ -453,7 +453,7 @@ lpd_dma_chan6: dma@ffad0000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan7: dma@ffae0000 {
> + lpd_dma_chan7: dma-controller@ffae0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffae0000 0x0 0x1000>;
> @@ -466,7 +466,7 @@ lpd_dma_chan7: dma@ffae0000 {
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> - lpd_dma_chan8: dma@ffaf0000 {
> + lpd_dma_chan8: dma-controller@ffaf0000 {
> status = "disabled";
> compatible = "xlnx,zynqmp-dma-1.0";
> reg = <0x0 0xffaf0000 0x0 0x1000>;
Applied.
M
^ permalink raw reply
* Re: [PATCH 2/3] arm64: zynqmp: Add missing #dma-cells property
From: Michal Simek @ 2022-01-24 12:18 UTC (permalink / raw)
To: Michael Tretter, devicetree, linux-arm-kernel, dmaengine
Cc: robh+dt, michal.simek, kernel
In-Reply-To: <20220112151541.1328732-3-m.tretter@pengutronix.de>
On 1/12/22 16:15, Michael Tretter wrote:
> Requesting the dma controllers fails if #dma-cells is not defined. Add
> the missing property.
>
> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 493719f71fb5..6d96b6b99f84 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -261,6 +261,7 @@ fpd_dma_chan1: dma@fd500000 {
> interrupt-parent = <&gic>;
> interrupts = <0 124 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14e8>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -273,6 +274,7 @@ fpd_dma_chan2: dma@fd510000 {
> interrupt-parent = <&gic>;
> interrupts = <0 125 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14e9>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -285,6 +287,7 @@ fpd_dma_chan3: dma@fd520000 {
> interrupt-parent = <&gic>;
> interrupts = <0 126 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14ea>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -297,6 +300,7 @@ fpd_dma_chan4: dma@fd530000 {
> interrupt-parent = <&gic>;
> interrupts = <0 127 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14eb>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -309,6 +313,7 @@ fpd_dma_chan5: dma@fd540000 {
> interrupt-parent = <&gic>;
> interrupts = <0 128 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14ec>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -321,6 +326,7 @@ fpd_dma_chan6: dma@fd550000 {
> interrupt-parent = <&gic>;
> interrupts = <0 129 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14ed>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -333,6 +339,7 @@ fpd_dma_chan7: dma@fd560000 {
> interrupt-parent = <&gic>;
> interrupts = <0 130 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14ee>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -345,6 +352,7 @@ fpd_dma_chan8: dma@fd570000 {
> interrupt-parent = <&gic>;
> interrupts = <0 131 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <128>;
> iommus = <&smmu 0x14ef>;
> power-domains = <&zynqmp_firmware PD_GDMA>;
> @@ -374,6 +382,7 @@ lpd_dma_chan1: dma@ffa80000 {
> interrupt-parent = <&gic>;
> interrupts = <0 77 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x868>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -386,6 +395,7 @@ lpd_dma_chan2: dma@ffa90000 {
> interrupt-parent = <&gic>;
> interrupts = <0 78 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x869>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -398,6 +408,7 @@ lpd_dma_chan3: dma@ffaa0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 79 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86a>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -410,6 +421,7 @@ lpd_dma_chan4: dma@ffab0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 80 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86b>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -422,6 +434,7 @@ lpd_dma_chan5: dma@ffac0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 81 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86c>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -434,6 +447,7 @@ lpd_dma_chan6: dma@ffad0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 82 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86d>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -446,6 +460,7 @@ lpd_dma_chan7: dma@ffae0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 83 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86e>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
> @@ -458,6 +473,7 @@ lpd_dma_chan8: dma@ffaf0000 {
> interrupt-parent = <&gic>;
> interrupts = <0 84 4>;
> clock-names = "clk_main", "clk_apb";
> + #dma-cells = <1>;
> xlnx,bus-width = <64>;
> iommus = <&smmu 0x86f>;
> power-domains = <&zynqmp_firmware PD_ADMA>;
Applied.
M
^ permalink raw reply
* [PATCH v18 8/8] ARM: dts: imx7d-remarkable2: Enable lcdif
From: Alistair Francis @ 2022-01-24 12:10 UTC (permalink / raw)
To: broonie, robh+dt, kernel, lgirdwood, lee.jones
Cc: linux-pm, linux-hwmon, devicetree, linux-imx, rui.zhang,
alistair23, amitk, linux-arm-kernel, andreas, s.hauer,
linux-kernel, shawnguo, Alistair Francis
In-Reply-To: <20220124121009.108649-1-alistair@alistair23.me>
Connect the dispaly on the reMarkable2.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
---
| 74 +++++++++++++++++++++++++
1 file changed, 74 insertions(+)
--git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/imx7d-remarkable2.dts
index 99ac0d242936..03a4029e1e57 100644
--- a/arch/arm/boot/dts/imx7d-remarkable2.dts
+++ b/arch/arm/boot/dts/imx7d-remarkable2.dts
@@ -68,6 +68,16 @@ reg_digitizer: regulator-digitizer {
startup-delay-us = <100000>; /* 100 ms */
};
+ reg_sdoe: regulator-sdoe {
+ compatible = "regulator-fixed";
+ regulator-name = "SDOE";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_sdoe_reg>;
+ pinctrl-1 = <&pinctrl_sdoe_reg>;
+ gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
@@ -76,6 +86,16 @@ wifi_pwrseq: wifi_pwrseq {
clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
clock-names = "ext_clock";
};
+
+ panel {
+ compatible = "eink,vb3300-kca";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
};
&clks {
@@ -132,6 +152,20 @@ reg_epdpmic: vcom {
};
};
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ lcd-supply = <®_epdpmic>;
+ lcd2-supply = <®_sdoe>;
+ status = "okay";
+
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -246,6 +280,46 @@ MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
>;
};
+ pinctrl_lcdif: lcdifgrp {
+ fsl,pins = <
+ MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
+ MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
+ MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
+ MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
+ MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
+ MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
+ MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
+ MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
+ MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
+ MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
+ MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
+ MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
+ MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
+ MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
+ MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
+ MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
+
+ MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
+ MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
+ MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
+ MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
+ MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
+
+ MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
+ MX7D_PAD_LCD_CLK__LCD_CLK 0x79
+ MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
+ MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
+ MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
+ MX7D_PAD_LCD_RESET__LCD_RESET 0x79
+ >;
+ };
+
+ pinctrl_sdoe_reg: sdoereggrp {
+ fsl,pins = <
+ MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
--
2.31.1
^ permalink raw reply related
* [PATCH v18 7/8] ARM: dts: imx7d-remarkable2: Enable silergy,sy7636a
From: Alistair Francis @ 2022-01-24 12:10 UTC (permalink / raw)
To: broonie, robh+dt, kernel, lgirdwood, lee.jones
Cc: linux-pm, linux-hwmon, devicetree, linux-imx, rui.zhang,
alistair23, amitk, linux-arm-kernel, andreas, s.hauer,
linux-kernel, shawnguo, Alistair Francis
In-Reply-To: <20220124121009.108649-1-alistair@alistair23.me>
Enable the silergy,sy7636a and silergy,sy7636a-regulator on the
reMarkable2.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
---
| 62 +++++++++++++++++++++++++
1 file changed, 62 insertions(+)
--git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/imx7d-remarkable2.dts
index a2a91bfdd98e..99ac0d242936 100644
--- a/arch/arm/boot/dts/imx7d-remarkable2.dts
+++ b/arch/arm/boot/dts/imx7d-remarkable2.dts
@@ -22,6 +22,27 @@ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
+ thermal-zones {
+ epd-thermal {
+ thermal-sensors = <&epd_pmic>;
+ polling-delay-passive = <30000>;
+ polling-delay = <30000>;
+ trips {
+ trip0 {
+ temperature = <49000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
reg_brcm: regulator-brcm {
compatible = "regulator-fixed";
regulator-name = "brcm_reg";
@@ -84,6 +105,33 @@ wacom_digitizer: digitizer@9 {
};
};
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ epd_pmic: sy7636a@62 {
+ compatible = "silergy,sy7636a";
+ reg = <0x62>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epdpmic>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <0>;
+
+ epd-pwr-good-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
+ regulators {
+ reg_epdpmic: vcom {
+ regulator-name = "vcom";
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -177,6 +225,13 @@ MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x14
>;
};
+ pinctrl_epdpmic: epdpmicgrp {
+ fsl,pins = <
+ MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x00000074
+ MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x00000014
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
@@ -184,6 +239,13 @@ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
>;
};
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
+ MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
--
2.31.1
^ permalink raw reply related
* [PATCH v18 6/8] ARM: imx_v6_v7_defconfig: Enable silergy,sy7636a
From: Alistair Francis @ 2022-01-24 12:10 UTC (permalink / raw)
To: broonie, robh+dt, kernel, lgirdwood, lee.jones
Cc: linux-pm, linux-hwmon, devicetree, linux-imx, rui.zhang,
alistair23, amitk, linux-arm-kernel, andreas, s.hauer,
linux-kernel, shawnguo, Alistair Francis
In-Reply-To: <20220124121009.108649-1-alistair@alistair23.me>
Enable the silergy,sy7636a and silergy,sy7636a-regulator for the
reMarkable2.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
---
arch/arm/configs/imx_v6_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index f7498df08dfe..37ec95fce3be 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -223,6 +223,7 @@ CONFIG_RN5T618_POWER=m
CONFIG_SENSORS_MC13783_ADC=y
CONFIG_SENSORS_GPIO_FAN=y
CONFIG_SENSORS_IIO_HWMON=y
+CONFIG_SENSORS_SY7636A=y
CONFIG_THERMAL_STATISTICS=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_CPU_THERMAL=y
@@ -239,6 +240,7 @@ CONFIG_MFD_DA9063=y
CONFIG_MFD_MC13XXX_SPI=y
CONFIG_MFD_MC13XXX_I2C=y
CONFIG_MFD_RN5T618=y
+CONFIG_MFD_SIMPLE_MFD_I2C=y
CONFIG_MFD_STMPE=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_ANATOP=y
@@ -251,6 +253,7 @@ CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_REGULATOR_PFUZE100=y
CONFIG_REGULATOR_RN5T618=y
+CONFIG_REGULATOR_SY7636A=y
CONFIG_RC_CORE=y
CONFIG_RC_DEVICES=y
CONFIG_IR_GPIO_CIR=y
--
2.31.1
^ permalink raw reply related
* [PATCH v18 5/8] hwmon: sy7636a: Add temperature driver for sy7636a
From: Alistair Francis @ 2022-01-24 12:10 UTC (permalink / raw)
To: broonie, robh+dt, kernel, lgirdwood, lee.jones
Cc: linux-pm, linux-hwmon, devicetree, linux-imx, rui.zhang,
alistair23, amitk, linux-arm-kernel, andreas, s.hauer,
linux-kernel, shawnguo, Alistair Francis, Guenter Roeck
In-Reply-To: <20220124121009.108649-1-alistair@alistair23.me>
This is a multi-function device to interface with the sy7636a
EPD PMIC chip from Silergy.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Acked-by: Guenter Roeck <linux@roeck-us.net>
---
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/sy7636a-hwmon.rst | 26 +++++++
drivers/hwmon/Kconfig | 9 +++
drivers/hwmon/Makefile | 1 +
drivers/hwmon/sy7636a-hwmon.c | 106 ++++++++++++++++++++++++++
5 files changed, 143 insertions(+)
create mode 100644 Documentation/hwmon/sy7636a-hwmon.rst
create mode 100644 drivers/hwmon/sy7636a-hwmon.c
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index df20022c741f..6e0906ef5d25 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -185,6 +185,7 @@ Hardware Monitoring Kernel Drivers
smsc47m1
sparx5-temp
stpddc60
+ sy7636a-hwmon
tc654
tc74
thmc50
diff --git a/Documentation/hwmon/sy7636a-hwmon.rst b/Documentation/hwmon/sy7636a-hwmon.rst
new file mode 100644
index 000000000000..5612079397d5
--- /dev/null
+++ b/Documentation/hwmon/sy7636a-hwmon.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Kernel driver sy7636a-hwmon
+=========================
+
+Supported chips:
+
+ * Silergy SY7636A PMIC
+
+
+Description
+-----------
+
+This driver adds hardware temperature reading support for
+the Silergy SY7636A PMIC.
+
+The following sensors are supported
+
+ * Temperature
+ - SoC on-die temperature in milli-degree C
+
+sysfs-Interface
+---------------
+
+temp0_input
+ - SoC on-die temperature (milli-degree C)
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 8df25f1079ba..aa5785e657a4 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1672,6 +1672,15 @@ config SENSORS_SIS5595
This driver can also be built as a module. If so, the module
will be called sis5595.
+config SENSORS_SY7636A
+ tristate "Silergy SY7636A"
+ help
+ If you say yes here you get support for the thermistor readout of
+ the Silergy SY7636A PMIC.
+
+ This driver can also be built as a module. If so, the module
+ will be called sy7636a-hwmon.
+
config SENSORS_DME1737
tristate "SMSC DME1737, SCH311x and compatibles"
depends on I2C && !PPC
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 185f946d698b..fe54a3dfdb03 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -186,6 +186,7 @@ obj-$(CONFIG_SENSORS_SMSC47M1) += smsc47m1.o
obj-$(CONFIG_SENSORS_SMSC47M192)+= smsc47m192.o
obj-$(CONFIG_SENSORS_SPARX5) += sparx5-temp.o
obj-$(CONFIG_SENSORS_STTS751) += stts751.o
+obj-$(CONFIG_SENSORS_SY7636A) += sy7636a-hwmon.o
obj-$(CONFIG_SENSORS_AMC6821) += amc6821.o
obj-$(CONFIG_SENSORS_TC74) += tc74.o
obj-$(CONFIG_SENSORS_THMC50) += thmc50.o
diff --git a/drivers/hwmon/sy7636a-hwmon.c b/drivers/hwmon/sy7636a-hwmon.c
new file mode 100644
index 000000000000..6dd9c2a0f0e0
--- /dev/null
+++ b/drivers/hwmon/sy7636a-hwmon.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Functions to access SY3686A power management chip temperature
+ *
+ * Copyright (C) 2021 reMarkable AS - http://www.remarkable.com/
+ *
+ * Authors: Lars Ivar Miljeteig <lars.ivar.miljeteig@remarkable.com>
+ * Alistair Francis <alistair@alistair23.me>
+ */
+
+#include <linux/err.h>
+#include <linux/hwmon.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/machine.h>
+
+#include <linux/mfd/sy7636a.h>
+
+static int sy7636a_read(struct device *dev, enum hwmon_sensor_types type,
+ u32 attr, int channel, long *temp)
+{
+ struct regmap *regmap = dev_get_drvdata(dev);
+ int ret, reg_val;
+
+ ret = regmap_read(regmap,
+ SY7636A_REG_TERMISTOR_READOUT, ®_val);
+ if (ret)
+ return ret;
+
+ *temp = reg_val * 1000;
+
+ return 0;
+}
+
+static umode_t sy7636a_is_visible(const void *data,
+ enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+ if (type != hwmon_temp)
+ return 0;
+
+ if (attr != hwmon_temp_input)
+ return 0;
+
+ return 0444;
+}
+
+static const struct hwmon_ops sy7636a_hwmon_ops = {
+ .is_visible = sy7636a_is_visible,
+ .read = sy7636a_read,
+};
+
+static const struct hwmon_channel_info *sy7636a_info[] = {
+ HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
+ HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
+ NULL
+};
+
+static const struct hwmon_chip_info sy7636a_chip_info = {
+ .ops = &sy7636a_hwmon_ops,
+ .info = sy7636a_info,
+};
+
+static int sy7636a_sensor_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ struct regulator *regulator;
+ struct device *hwmon_dev;
+ int err;
+
+ if (!regmap)
+ return -EPROBE_DEFER;
+
+ regulator = devm_regulator_get(&pdev->dev, "vcom");
+ if (IS_ERR(regulator))
+ return PTR_ERR(regulator);
+
+ err = regulator_enable(regulator);
+ if (err)
+ return err;
+
+ hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
+ "sy7636a_temperature", regmap,
+ &sy7636a_chip_info, NULL);
+
+ if (IS_ERR(hwmon_dev)) {
+ err = PTR_ERR(hwmon_dev);
+ dev_err(&pdev->dev, "Unable to register hwmon device, returned %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static struct platform_driver sy7636a_sensor_driver = {
+ .probe = sy7636a_sensor_probe,
+ .driver = {
+ .name = "sy7636a-temperature",
+ },
+};
+module_platform_driver(sy7636a_sensor_driver);
+
+MODULE_DESCRIPTION("SY7636A sensor driver");
+MODULE_LICENSE("GPL");
--
2.31.1
^ permalink raw reply related
* [PATCH v18 4/8] regulator: sy7636a: Remove requirement on sy7636a mfd
From: Alistair Francis @ 2022-01-24 12:10 UTC (permalink / raw)
To: broonie, robh+dt, kernel, lgirdwood, lee.jones
Cc: linux-pm, linux-hwmon, devicetree, linux-imx, rui.zhang,
alistair23, amitk, linux-arm-kernel, andreas, s.hauer,
linux-kernel, shawnguo, Alistair Francis
In-Reply-To: <20220124121009.108649-1-alistair@alistair23.me>
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Acked-by: Mark Brown <broonie@kernel.org>
---
drivers/regulator/Kconfig | 1 -
drivers/regulator/sy7636a-regulator.c | 7 +++++--
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 1c35fed20d34..25ae5f087ff9 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -1208,7 +1208,6 @@ config REGULATOR_STW481X_VMMC
config REGULATOR_SY7636A
tristate "Silergy SY7636A voltage regulator"
- depends on MFD_SY7636A
help
This driver supports Silergy SY3686A voltage regulator.
diff --git a/drivers/regulator/sy7636a-regulator.c b/drivers/regulator/sy7636a-regulator.c
index 22fddf868e4c..29fc27c2cda0 100644
--- a/drivers/regulator/sy7636a-regulator.c
+++ b/drivers/regulator/sy7636a-regulator.c
@@ -7,11 +7,14 @@
// Authors: Lars Ivar Miljeteig <lars.ivar.miljeteig@remarkable.com>
// Alistair Francis <alistair@alistair23.me>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/mfd/sy7636a.h>
#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
#include <linux/regmap.h>
-#include <linux/gpio/consumer.h>
-#include <linux/mfd/sy7636a.h>
struct sy7636a_data {
struct regmap *regmap;
--
2.31.1
^ permalink raw reply related
* [PATCH v18 3/8] mfd: simple-mfd-i2c: Enable support for the silergy,sy7636a
From: Alistair Francis @ 2022-01-24 12:10 UTC (permalink / raw)
To: broonie, robh+dt, kernel, lgirdwood, lee.jones
Cc: linux-pm, linux-hwmon, devicetree, linux-imx, rui.zhang,
alistair23, amitk, linux-arm-kernel, andreas, s.hauer,
linux-kernel, shawnguo, Alistair Francis
In-Reply-To: <20220124121009.108649-1-alistair@alistair23.me>
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mfd/simple-mfd-i2c.c | 11 +++++++++++
include/linux/mfd/sy7636a.h | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+)
create mode 100644 include/linux/mfd/sy7636a.h
diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c
index 51536691ad9d..f4c8fc3ee463 100644
--- a/drivers/mfd/simple-mfd-i2c.c
+++ b/drivers/mfd/simple-mfd-i2c.c
@@ -62,8 +62,19 @@ static int simple_mfd_i2c_probe(struct i2c_client *i2c)
return ret;
}
+static const struct mfd_cell sy7636a_cells[] = {
+ { .name = "sy7636a-regulator", },
+ { .name = "sy7636a-temperature", },
+};
+
+static const struct simple_mfd_data silergy_sy7636a = {
+ .mfd_cell = sy7636a_cells,
+ .mfd_cell_size = ARRAY_SIZE(sy7636a_cells),
+};
+
static const struct of_device_id simple_mfd_i2c_of_match[] = {
{ .compatible = "kontron,sl28cpld" },
+ { .compatible = "silergy,sy7636a", .data = &silergy_sy7636a},
{}
};
MODULE_DEVICE_TABLE(of, simple_mfd_i2c_of_match);
diff --git a/include/linux/mfd/sy7636a.h b/include/linux/mfd/sy7636a.h
new file mode 100644
index 000000000000..22f03b2f851e
--- /dev/null
+++ b/include/linux/mfd/sy7636a.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Functions to access SY3686A power management chip.
+ *
+ * Copyright (C) 2021 reMarkable AS - http://www.remarkable.com/
+ */
+
+#ifndef __MFD_SY7636A_H
+#define __MFD_SY7636A_H
+
+#define SY7636A_REG_OPERATION_MODE_CRL 0x00
+/* It is set if a gpio is used to control the regulator */
+#define SY7636A_OPERATION_MODE_CRL_VCOMCTL BIT(6)
+#define SY7636A_OPERATION_MODE_CRL_ONOFF BIT(7)
+#define SY7636A_REG_VCOM_ADJUST_CTRL_L 0x01
+#define SY7636A_REG_VCOM_ADJUST_CTRL_H 0x02
+#define SY7636A_REG_VCOM_ADJUST_CTRL_MASK 0x01ff
+#define SY7636A_REG_VLDO_VOLTAGE_ADJULST_CTRL 0x03
+#define SY7636A_REG_POWER_ON_DELAY_TIME 0x06
+#define SY7636A_REG_FAULT_FLAG 0x07
+#define SY7636A_FAULT_FLAG_PG BIT(0)
+#define SY7636A_REG_TERMISTOR_READOUT 0x08
+
+#define SY7636A_REG_MAX 0x08
+
+#define VCOM_ADJUST_CTRL_MASK 0x1ff
+// Used to shift the high byte
+#define VCOM_ADJUST_CTRL_SHIFT 8
+// Used to scale from VCOM_ADJUST_CTRL to mv
+#define VCOM_ADJUST_CTRL_SCAL 10000
+
+#define FAULT_FLAG_SHIFT 1
+
+#endif /* __LINUX_MFD_SY7636A_H */
--
2.31.1
^ permalink raw reply related
* [PATCH v18 2/8] mfd: simple-mfd-i2c: Add a Kconfig name
From: Alistair Francis @ 2022-01-24 12:10 UTC (permalink / raw)
To: broonie, robh+dt, kernel, lgirdwood, lee.jones
Cc: linux-pm, linux-hwmon, devicetree, linux-imx, rui.zhang,
alistair23, amitk, linux-arm-kernel, andreas, s.hauer,
linux-kernel, shawnguo, Alistair Francis
In-Reply-To: <20220124121009.108649-1-alistair@alistair23.me>
Add a Kconfig name to the "Simple Multi-Functional Device support (I2C)"
device so that it can be enabled via menuconfig.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mfd/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index ba0b3eb131f1..e0d2fcb10a0c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1188,7 +1188,7 @@ config MFD_SI476X_CORE
module will be called si476x-core.
config MFD_SIMPLE_MFD_I2C
- tristate
+ tristate "Simple Multi-Functional Device support (I2C)"
depends on I2C
select MFD_CORE
select REGMAP_I2C
--
2.31.1
^ permalink raw reply related
* [PATCH v18 1/8] dt-bindings: mfd: Initial commit of silergy,sy7636a.yaml
From: Alistair Francis @ 2022-01-24 12:10 UTC (permalink / raw)
To: broonie, robh+dt, kernel, lgirdwood, lee.jones
Cc: linux-pm, linux-hwmon, devicetree, linux-imx, rui.zhang,
alistair23, amitk, linux-arm-kernel, andreas, s.hauer,
linux-kernel, shawnguo, Alistair Francis, Rob Herring
In-Reply-To: <20220124121009.108649-1-alistair@alistair23.me>
Initial support for the Silergy SY7636A Power Management chip
and regulator.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
.../bindings/mfd/silergy,sy7636a.yaml | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/silergy,sy7636a.yaml
diff --git a/Documentation/devicetree/bindings/mfd/silergy,sy7636a.yaml b/Documentation/devicetree/bindings/mfd/silergy,sy7636a.yaml
new file mode 100644
index 000000000000..6de74c701635
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/silergy,sy7636a.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/silergy,sy7636a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: silergy sy7636a PMIC
+
+maintainers:
+ - Alistair Francis <alistair@alistair23.me>
+
+properties:
+ compatible:
+ const: silergy,sy7636a
+
+ reg:
+ description:
+ I2C device address.
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ '#thermal-sensor-cells':
+ const: 0
+
+ epd-pwr-good-gpios:
+ description:
+ Specifying the power good GPIOs.
+ maxItems: 1
+
+ regulators:
+ type: object
+
+ properties:
+ compatible:
+ const: silergy,sy7636a-regulator
+
+ vcom:
+ type: object
+ $ref: /schemas/regulator/regulator.yaml#
+ description:
+ The regulator for the compenstation voltage. Enabling/disabling this
+ enables/disables the entire device.
+ properties:
+ regulator-name:
+ const: vcom
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#thermal-sensor-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@62 {
+ compatible = "silergy,sy7636a";
+ reg = <0x62>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epdpmic>;
+ #thermal-sensor-cells = <0>;
+
+ regulators {
+ reg_epdpmic: vcom {
+ regulator-name = "vcom";
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+...
--
2.31.1
^ permalink raw reply related
* [PATCH v18 0/8] Add support for the silergy,sy7636a
From: Alistair Francis @ 2022-01-24 12:10 UTC (permalink / raw)
To: broonie, robh+dt, kernel, lgirdwood, lee.jones
Cc: linux-pm, linux-hwmon, devicetree, linux-imx, rui.zhang,
alistair23, amitk, linux-arm-kernel, andreas, s.hauer,
linux-kernel, shawnguo, Alistair Francis
v18:
- Rebase
v17:
- Rebase and fix build issues
v16:
- Improve vdd regulator comments
v15:
- Address comments on the patches
v14:
- Merge the thermal driver and hwmon
v13:
- Address comments on thermal driver
- Rebase on master (without other patches)
v12:
- Rebase
v11:
- Address comments on hwmon
- Improve "mfd: simple-mfd-i2c: Add a Kconfig name" commit message
v10:
- Use dev_get_regmap() instead of dev_get_drvdata()
v9:
- Convert to use the simple-mfd-i2c instead
Alistair Francis (8):
dt-bindings: mfd: Initial commit of silergy,sy7636a.yaml
mfd: simple-mfd-i2c: Add a Kconfig name
mfd: simple-mfd-i2c: Enable support for the silergy,sy7636a
regulator: sy7636a: Remove requirement on sy7636a mfd
hwmon: sy7636a: Add temperature driver for sy7636a
ARM: imx_v6_v7_defconfig: Enable silergy,sy7636a
ARM: dts: imx7d-remarkable2: Enable silergy,sy7636a
ARM: dts: imx7d-remarkable2: Enable lcdif
.../bindings/mfd/silergy,sy7636a.yaml | 82 +++++++++++
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/sy7636a-hwmon.rst | 26 ++++
arch/arm/boot/dts/imx7d-remarkable2.dts | 136 ++++++++++++++++++
arch/arm/configs/imx_v6_v7_defconfig | 3 +
drivers/hwmon/Kconfig | 9 ++
drivers/hwmon/Makefile | 1 +
drivers/hwmon/sy7636a-hwmon.c | 106 ++++++++++++++
drivers/mfd/Kconfig | 2 +-
drivers/mfd/simple-mfd-i2c.c | 11 ++
drivers/regulator/Kconfig | 1 -
drivers/regulator/sy7636a-regulator.c | 7 +-
include/linux/mfd/sy7636a.h | 34 +++++
13 files changed, 415 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/silergy,sy7636a.yaml
create mode 100644 Documentation/hwmon/sy7636a-hwmon.rst
create mode 100644 drivers/hwmon/sy7636a-hwmon.c
create mode 100644 include/linux/mfd/sy7636a.h
--
2.31.1
^ permalink raw reply
* [PATCH v2] watchdog: imx2_wdg: Alow ping on suspend
From: Alistair Francis @ 2022-01-24 12:00 UTC (permalink / raw)
To: linux-arm-kernel, linux, shawnguo, linux-kernel, s.hauer,
linux-watchdog, wim
Cc: devicetree, festevam, linux-imx, robh+dt, kernel,
Alistair Francis
The i.MX watchdog cannot be disabled by softwrae once it has been
enabled. This means that it can't be stopped before suspend.
For systems that enter low power mode this is fine, as the watchdog will
be automatically stopped by hardwrae in low power mode. Not all i.MX
platforms support low power mode in the mainline kernel. For example the
i.MX7D does not enter low power mode and so will be rebooted 2 minutes
after entering freeze or mem sleep states.
This patch introduces a device tree property "fsl,ping-during-suspend"
that can be used to enable ping on suspend support for these systems.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
---
drivers/watchdog/imx2_wdt.c | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
index 51bfb796898b..d0c5d47ddede 100644
--- a/drivers/watchdog/imx2_wdt.c
+++ b/drivers/watchdog/imx2_wdt.c
@@ -66,6 +66,7 @@ struct imx2_wdt_device {
struct watchdog_device wdog;
bool ext_reset;
bool clk_is_on;
+ bool no_ping;
};
static bool nowayout = WATCHDOG_NOWAYOUT;
@@ -312,12 +313,18 @@ static int __init imx2_wdt_probe(struct platform_device *pdev)
wdev->ext_reset = of_property_read_bool(dev->of_node,
"fsl,ext-reset-output");
+ /*
+ * The i.MX7D doesn't support low power mode, so we need to ping the watchdog
+ * during suspend.
+ */
+ wdev->no_ping = !of_device_is_compatible(dev->of_node, "fsl,imx7d-wdt");
platform_set_drvdata(pdev, wdog);
watchdog_set_drvdata(wdog, wdev);
watchdog_set_nowayout(wdog, nowayout);
watchdog_set_restart_priority(wdog, 128);
watchdog_init_timeout(wdog, timeout, dev);
- watchdog_stop_ping_on_suspend(wdog);
+ if (wdev->no_ping)
+ watchdog_stop_ping_on_suspend(wdog);
if (imx2_wdt_is_running(wdev)) {
imx2_wdt_set_timeout(wdog, wdog->timeout);
@@ -366,9 +373,11 @@ static int __maybe_unused imx2_wdt_suspend(struct device *dev)
imx2_wdt_ping(wdog);
}
- clk_disable_unprepare(wdev->clk);
+ if (wdev->no_ping) {
+ clk_disable_unprepare(wdev->clk);
- wdev->clk_is_on = false;
+ wdev->clk_is_on = false;
+ }
return 0;
}
@@ -380,11 +389,14 @@ static int __maybe_unused imx2_wdt_resume(struct device *dev)
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
int ret;
- ret = clk_prepare_enable(wdev->clk);
- if (ret)
- return ret;
+ if (wdev->no_ping) {
+ ret = clk_prepare_enable(wdev->clk);
- wdev->clk_is_on = true;
+ if (ret)
+ return ret;
+
+ wdev->clk_is_on = true;
+ }
if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
/*
@@ -407,6 +419,7 @@ static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
static const struct of_device_id imx2_wdt_dt_ids[] = {
{ .compatible = "fsl,imx21-wdt", },
+ { .compatible = "fsl,imx7d-wdt", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
--
2.31.1
^ permalink raw reply related
* Aw: Re: Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Bananapi R2 Pro
From: Frank Wunderlich @ 2022-01-24 11:49 UTC (permalink / raw)
To: Sascha Hauer
Cc: Frank Wunderlich, linux-rockchip, Rob Herring, Heiko Stuebner,
Peter Geis, Johan Jonker, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20220124110331.GZ23490@pengutronix.de>
> Gesendet: Montag, 24. Januar 2022 um 12:03 Uhr
> Von: "Sascha Hauer" <sha@pengutronix.de>
> On Mon, Jan 24, 2022 at 09:55:05AM +0100, Frank Wunderlich wrote:
> > took this from the 3568-EVB (like the most parts, as the board is
> > mostly the same), and in linux it's the same and working. The switch
> > have also phy-id 0 on mdio bus #1, are you sure this is invalid?
just to clarify: in linux dts only the basics were taken from evb and changed if
needed (like iodomain, regulators).
mixed this with the barebox submsission where i mainly used the evb dts.
should i add a note in head that some parts are taken from EVB and vendors dts?
As this is my first new DTS, i want to be sure the legal notice is correct.
> It's not invalid, it's just the broadcast address to which other phys
> might answer as well. Anyway, as long as there's only a single phy on
> the bus it's probably okay.
ok, on mdio0 there is the rtl8211 phy and on mdio1 there is the rtl8367rb switch,
so only 1 device per bus. I was not aware that 0 is broadcast.
regards Frank
^ permalink raw reply
* Re: [PATCH v21 7/8] arm64: dts: mt8192: add svs device information
From: AngeloGioacchino Del Regno @ 2022-01-24 11:49 UTC (permalink / raw)
To: Roger Lu, Matthias Brugger, Enric Balletbo Serra, Kevin Hilman,
Rob Herring, Nicolas Boichat, Stephen Boyd, Philipp Zabel
Cc: Fan Chen, HenryC Chen, Xiaoqing Liu, Charles Yang, Angus Lin,
Mark Rutland, Nishanth Menon, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel, linux-pm,
Project_Global_Chrome_Upstream_Group, Guenter Roeck
In-Reply-To: <3d3518ff5c332129af5d10766477b9776bbbf55e.camel@mediatek.com>
Il 24/01/22 11:48, Roger Lu ha scritto:
> Hi AngeloGioacchino,
>
> On Fri, 2022-01-07 at 15:33 +0100, AngeloGioacchino Del Regno wrote:
>> Il 07/01/22 10:51, Roger Lu ha scritto:
>>> Add compitable/reg/irq/clock/efuse/reset setting in svs node.
>>
>> Typo: compitable => compatible
>> .. also, you're not only adding the svs node, but also efuse: please add that
>> information in the commit description.
>>
>>>
>>> Signed-off-by: Roger Lu <roger.lu@mediatek.com>
>>
>> This patch seems to not apply on top of the current linux-next, can you please
>> rebase it? That would resolve issues with this series and would be picked
>> sooner.
>>
>> Apart from that...
>
> Sorry to make you confuse. After having discussion internally, we'll submit
> another complete mt8192.dtsi patch including this svs node. Therefore, I'll drop
> this path from svs patchset in order not to make the reviewer confuse. Thanks
> for the comments a lot.
>
Yes that decision looks good to me, as this allows different maintainers
to apply patches on a per-subsystem basis.
Thanks!
Regards,
Angelo
^ permalink raw reply
* Re: [PATCH v11 1/3] dt-binding: mt8183: add Mediatek MDP3 dt-bindings
From: AngeloGioacchino Del Regno @ 2022-01-24 11:40 UTC (permalink / raw)
To: Rob Herring, Moudy Ho
Cc: Mauro Carvalho Chehab, Matthias Brugger, Hans Verkuil,
Jernej Skrabec, Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley,
Laurent Pinchart, linux-media, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel, Alexandre Courbot, tfiga, drinkcat,
pihsun, hsinyi, Maoguang Meng, daoyuan huang, Ping-Hsun Wu,
menghui.lin, sj.huang, allen-kh.cheng, randy.wu, jason-jh.lin,
roy-cw.yeh, river.cheng, srv_heupstream
In-Reply-To: <YesiwTSxa9HJ1lxG@robh.at.kernel.org>
Il 21/01/22 22:16, Rob Herring ha scritto:
> On Wed, Jan 05, 2022 at 05:37:56PM +0800, Moudy Ho wrote:
Hello Rob,
since I'm not the best at reviewing dt-bindings, I always try to leave that to
other reviewers; in which case, thank you for your awesome review activity on
all of these (and helping me a lot on some of my attempts to write yaml..!!)
In this case, though, since I do have knowledge about the platform, it's probably
worth for me to try to address some of your questions, on at least this one.
>> This patch adds DT binding document for Media Data Path 3 (MDP3)
>> a unit in multimedia system used for scaling and color format convert.
>>
>> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
>> ---
>> .../bindings/media/mediatek,mdp3-rdma.yaml | 193 ++++++++++++++++++
>> .../bindings/media/mediatek,mdp3-rsz.yaml | 55 +++++
>> .../bindings/media/mediatek,mdp3-wrot.yaml | 57 ++++++
>> .../bindings/soc/mediatek/mediatek,ccorr.yaml | 47 +++++
>> .../bindings/soc/mediatek/mediatek,wdma.yaml | 58 ++++++
>> 5 files changed, 410 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
>> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
>> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
>> create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
>> create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
>> new file mode 100644
>> index 000000000000..002503383934
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
>> @@ -0,0 +1,193 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Mediatek Read Direct Memory Access
>> +
>> +maintainers:
>> + - Matthias Brugger <matthias.bgg@gmail.com>
>> +
>> +description: |
>> + Mediatek Read Direct Memory Access(RDMA) component used to do read DMA.
>> + It contains one line buffer to store the sufficient pixel data, and
>> + must be siblings to the central MMSYS_CONFIG node.
>> + For a description of the MMSYS_CONFIG binding, see
>> + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
>> + for details.
>> + The 1st RDMA is also used to be a controller node in Media Data Path 3(MDP3)
>> + that containing MMSYS, MUTEX, GCE and SCP settings.
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - items:
>> + # MDP3 controller node
>> + - const: mediatek,mt8183-mdp3
>
> How is this more specific than this:
>
>> + - const: mediatek,mt8183-mdp3-rdma0
>
Probably, oneOf is not the right choice here... "mediatek,mt8183-mdp3" is needed
to probe the "main" mdp3 core pdev, while RDMA0 is a necessary component (as in
this driver uses the component framework, and rdma0 is required for functionality,
as far as I understand).
This shouldn't be a choice, meaning that defining mdp3-rdma0 without mdp3 is
completely useless, as there wouldn't be anything else initializing that component,
nor sub-components of that.
>> + - items:
>> + # normal RDMA conponent
>> + - const: mediatek,mt8183-mdp3-rdma0
>> +
>> + mediatek,scp:
>> + description: The node of system control processor (SCP), using
>> + the remoteproc & rpmsg framework.
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + maxItems: 1
>> +
>> + mediatek,mdp3-comps:
>> + description: MTK sub-system of direct-link or DIP
>
> This needs a better description. What is DIP? What is direct-link?
I agree, this needs a better description.
>
>> + $ref: /schemas/types.yaml#/definitions/string-array
>> + items:
>> + - enum:
>> + # MDP direct-link input path selection, create a
>> + # component for path connectedness of HW pipe control
>> + - mediatek,mt8183-mdp3-dl1
>> + - enum:
>> + - mediatek,mt8183-mdp3-dl2
>> + - enum:
>> + # MDP direct-link output path selection, create a
>> + # component for path connectedness of HW pipe control
>> + - mediatek,mt8183-mdp3-path1
>> + - enum:
>> + - mediatek,mt8183-mdp3-path2
>> + - enum:
>> + # Input DMA of ISP PASS2 (DIP) module for raw image input
>> + - mediatek,mt8183-mdp3-imgi
>> + - enum:
>> + # Output DMA of ISP PASS2 (DIP) module for YUV image output
>> + - mediatek,mt8183-mdp3-exto
>
> There's only 1 possible value for mediatek,mdp3-comps, so why does it
> need to be in DT?
>
The wanted logic here (I believe) is that, depending on firmware capabilities
and/or platform/board capabilities, you may miss some subcomponents like IMGI
and/or EXTO.
As for DL1/2 and PATH1/2... DL1+PATH1 is surely critically necessary for the
functionality of the MDP3 RDMA... I don't know whether it's possible that we
get any fw/platform/device that's not using DL2/PATH2 at all.
Moudy, can you please explain?
>> +
>> + reg:
>> + items:
>> + - description: basic RDMA HW address
>> + - description: MDP direct-link 1st and 2nd input
>> + - description: MDP direct-link 1st output
>> + - description: MDP direct-link 2nd output
>> + - description: ISP input and output
>> +
>> + mediatek,gce-client-reg:
>> + description: The register of client driver can be configured by gce with
>> + 4 arguments defined in this property, such as phandle of gce, subsys id,
>> + register offset and size. Each GCE subsys id is mapping to a client
>> + defined in the header include/dt-bindings/gce/<chip>-gce.h.
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + - description: GCE client for RDMA
>> + - description: GCR client for MDP direct-link 1st and 2nd input
>> + - description: GCR client for MDP direct-link 1st output
>> + - description: GCR client for MDP direct-link 2nd output
>> + - description: GCR client for ISP input and output
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: RDMA clock
>> + - description: RSZ clock
>> + - description: direck-link TX clock in MDP side
>> + - description: direck-link RX clock in MDP side
>> + - description: direck-link TX clock in ISP side
>> + - description: direck-link RX clock in ISP side
>> +
>> + iommus:
>> + maxItems: 1
>> +
>> + mediatek,mmsys:
>> + description: The node of mux(multiplexer) controller for HW connections.
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> +
>> + mediatek,mm-mutex:
>
> Is this some sort of h/w lock? We have a standard binding for that.
>
There's a story behind that one: this was part of mtk (display) DRM drivers, then
it was moved to soc/mediatek/mtk-mutex.c as it started being shared.
I wonder if the mm-mutex can be rewritten and moved to hwspinlock... this driver
is growing and now, with the introduction of MDP3, we're seeing some more.
Though, it's definitely worth mentioning that the usage of MediaTek's mm-mutex is
varying a bit between the drm case and the mdp3 case as, here, we have a "command
queue" mechanism that is used for commands ordering in HW.
This is a very complex architecture that has very specific requirements.
For how I see it, migrating that to hwspinlock would require an almost complete
reimplementation of soc/mediatek/*, which would take a considerable amount of
time and efforts.
I'm mostly sure that I can help with that, but for how things are looking right
now, between refactoring, getting code solid, going through sane reviews and a
final merge, I'd say that this will take 8-12 months from now.
For this reason, I would propose to perform a slow and steady migration of the
MediaTek mmsys, scpsys, mutex over time, but only after getting in the support
for the new SoCs and functionality for the older ones, provided in this series
and some others that were already sent by MTK, half (or more) of which have
already been merged.
>> + description: The node of sof(start of frame) signal controller.
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + maxItems: 1
>> +
>> + mediatek,mailbox-gce:
>> + description: The node of global command engine (GCE), used to read/write
>> + registers with critical time limitation.
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> +
>> + mboxes:
>> + items:
>> + - description: used for 1st data pipe from RDMA
>> + - description: used for 2nd data pipe from RDMA
>> + - description: used for 3rd data pipe from Direct-Link
>> + - description: used for 4th data pipe from Direct-Link
>> +
>> + gce-subsys:
>> + description: sub-system id corresponding to the global command engine (GCE)
>> + register address.
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> +
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: mediatek,mt8183-mdp3
>> +
>> +then:
>> + required:
>> + - mediatek,scp
>> + - mediatek,mmsys
>> + - mediatek,mm-mutex
>> + - mediatek,mailbox-gce
>> + - mboxes
>> + - gce-subsys
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - mediatek,gce-client-reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/mt8183-clk.h>
>> + #include <dt-bindings/gce/mt8183-gce.h>
>> + #include <dt-bindings/power/mt8183-power.h>
>> + #include <dt-bindings/memory/mt8183-larb-port.h>
>> +
>> + mdp3_rdma0: mdp3_rdma0@14001000 {
>> + compatible = "mediatek,mt8183-mdp3",
>> + "mediatek,mt8183-mdp3-rdma0";
>> + mediatek,scp = <&scp>;
>> + mediatek,mdp3-comps = "mediatek,mt8183-mdp3-dl1",
>> + "mediatek,mt8183-mdp3-dl2",
>> + "mediatek,mt8183-mdp3-path1",
>> + "mediatek,mt8183-mdp3-path2",
>> + "mediatek,mt8183-mdp3-imgi",
>> + "mediatek,mt8183-mdp3-exto";
>> + reg = <0x14001000 0x1000>,
>> + <0x14000000 0x1000>,
>> + <0x14005000 0x1000>,
>> + <0x14006000 0x1000>,
>> + <0x15020000 0x1000>;
>> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
>> + <&gce SUBSYS_1400XXXX 0 0x1000>,
>> + <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
>> + <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
>> + <&gce SUBSYS_1502XXXX 0 0x1000>;
>> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
>> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
>> + <&mmsys CLK_MM_MDP_RSZ1>,
>> + <&mmsys CLK_MM_MDP_DL_TXCK>,
>> + <&mmsys CLK_MM_MDP_DL_RX>,
>> + <&mmsys CLK_MM_IPU_DL_TXCK>,
>> + <&mmsys CLK_MM_IPU_DL_RX>;
>> + iommus = <&iommu>;
>> + mediatek,mmsys = <&mmsys>;
>> + mediatek,mm-mutex = <&mutex>;
>> + mediatek,mailbox-gce = <&gce>;
>> + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
>> + <&gce 21 CMDQ_THR_PRIO_LOWEST>,
>> + <&gce 22 CMDQ_THR_PRIO_LOWEST>,
>> + <&gce 23 CMDQ_THR_PRIO_LOWEST>;
>> + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
>> + <&gce 0x14010000 SUBSYS_1401XXXX>,
>> + <&gce 0x14020000 SUBSYS_1402XXXX>,
>> + <&gce 0x15020000 SUBSYS_1502XXXX>;
>> + };
>> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
>> new file mode 100644
>> index 000000000000..cd4cf1531535
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
>> @@ -0,0 +1,55 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Mediatek Resizer
>> +
>> +maintainers:
>> + - Matthias Brugger <matthias.bgg@gmail.com>
>> +
>> +description: |
>> + One of Media Data Path 3 (MDP3) components used to do frame resizing.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - mediatek,mt8183-mdp3-rsz0
>> + - mediatek,mt8183-mdp3-rsz1
>
> Again, what's the difference between 0 and 1?
>
> I've probably asked that before, but without a sufficient reasoning
> here in the schema I'm just going to keep asking the same question.
This can probably be, instead, something like
compatible = "mediatek,mt8183-mdp3-rsz";
reg = < .... >;
mediatek,instance-id = <0>;
gce reg, clocks, blah...
or
compatible = "mediatek,mt8183-mdp3-rsz";
reg = < ...rsz0... >, < ...rsz1... >;
reg-names = "rsz0", "rsz1";
gce reg, clocks, blah...
...In any case, if MediaTek chose to separate these like that, I guess that
there will be differences in newer SoCs that would make that kind of binding
much necessary.
Please Moudy, can you explain why you didn't write that like the examples
that I provided there?
>
> Rob
>
^ permalink raw reply
* [PATCH v2 4/5] drivers: bus: add driver for initializing the SSC bus on (some) qcom SoCs
From: michael.srba @ 2022-01-24 11:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Stephen Boyd,
Philipp Zabel
Cc: Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree,
Michael Srba
From: Michael Srba <Michael.Srba@seznam.cz>
This patch adds bindings for the AHB bus which exposes the SCC block in
the global address space. This bus (and the SSC block itself) is present
on certain qcom SoCs.
In typical configuration, this bus (as some of the clocks and registers
that we need to manipulate) is not accessible to Linux, and the resources
on this bus are indirectly accessed by communicating with a hexagon CPU
core residing in the SSC block. In this configuration, the hypervisor is
the one performing the bus initialization for the purposes of bringing
the haxagon CPU core out of reset.
However, it is possible to change the configuration, in which case this
driver will initialize the bus.
In combination with drivers for resources on the SSC bus, this driver can
aid in debugging, and for example with a TLMM driver can be used to
directly access SSC-dedicated GPIO pins, removing the need to commit
to a particular usecase during hw design.
Finally, until open firmware for the hexagon core is available, this
approach allows for using sensors hooked up to SSC-dedicated GPIO pins
on mainline Linux simply by utilizing the existing in-tree drivers for
these sensors.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
---
CHANGES:
- v2: fix clang warning
---
drivers/bus/Kconfig | 6 +
drivers/bus/Makefile | 1 +
drivers/bus/qcom-ssc-block-bus.c | 365 +++++++++++++++++++++++++++++++
3 files changed, 372 insertions(+)
create mode 100644 drivers/bus/qcom-ssc-block-bus.c
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 3c68e174a113..f2b2e3098491 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -173,6 +173,12 @@ config SUNXI_RSB
with various RSB based devices, such as AXP223, AXP8XX PMICs,
and AC100/AC200 ICs.
+config QCOM_SSC_BLOCK_BUS
+ bool "Qualcomm SSC Block Bus Init Driver"
+ help
+ Say y here to enable support for initializing the bus that connects the SSC block's internal
+ bus to the cNoC on (some) qcom SoCs
+
config TEGRA_ACONNECT
tristate "Tegra ACONNECT Bus Driver"
depends on ARCH_TEGRA_210_SOC
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 52c2f35a26a9..e6756e83a9c4 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o
+obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o
obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
obj-$(CONFIG_OF) += simple-pm-bus.o
diff --git a/drivers/bus/qcom-ssc-block-bus.c b/drivers/bus/qcom-ssc-block-bus.c
new file mode 100644
index 000000000000..a93c7350a231
--- /dev/null
+++ b/drivers/bus/qcom-ssc-block-bus.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (c) 2021, Michael Srba
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* AXI Halt Register Offsets */
+#define AXI_HALTREQ_REG 0x0
+#define AXI_HALTACK_REG 0x4
+#define AXI_IDLE_REG 0x8
+
+static const char *qcom_ssc_block_pd_names[] = {
+ "ssc_cx",
+ "ssc_mx"
+};
+
+struct qcom_ssc_block_bus_data {
+ int num_pds;
+ const char **pd_names;
+ struct device *pds[ARRAY_SIZE(qcom_ssc_block_pd_names)];
+ char __iomem *reg_mpm_sscaon_config0; // MPM - msm power manager; AON - always-on
+ char __iomem *reg_mpm_sscaon_config1; // that's as much as we know about these
+ struct regmap *halt_map;
+ u32 ssc_axi_halt;
+ struct clk *xo_clk;
+ struct clk *aggre2_clk;
+ struct clk *gcc_im_sleep_clk;
+ struct clk *aggre2_north_clk;
+ struct clk *ssc_xo_clk;
+ struct clk *ssc_ahbs_clk;
+ struct reset_control *ssc_bcr;
+ struct reset_control *ssc_reset;
+};
+
+static void reg32_set_bits(char __iomem *reg, u32 value)
+{
+ u32 tmp = ioread32(reg);
+
+ iowrite32(tmp | value, reg);
+}
+
+static void reg32_clear_bits(char __iomem *reg, u32 value)
+{
+ u32 tmp = ioread32(reg);
+
+ iowrite32(tmp & (~value), reg);
+}
+
+
+static int qcom_ssc_block_bus_init(struct device *dev)
+{
+ int ret;
+
+ struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev);
+
+ clk_prepare_enable(data->xo_clk);
+ clk_prepare_enable(data->aggre2_clk);
+
+ clk_prepare_enable(data->gcc_im_sleep_clk);
+
+ reg32_clear_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5));
+ reg32_clear_bits(data->reg_mpm_sscaon_config1, BIT(31));
+
+ clk_disable(data->aggre2_north_clk);
+
+ ret = reset_control_deassert(data->ssc_reset);
+ if (ret) {
+ dev_err(dev, "error deasserting ssc_reset: %d\n", ret);
+ return ret;
+ }
+
+ clk_prepare_enable(data->aggre2_north_clk);
+
+ ret = reset_control_deassert(data->ssc_bcr);
+ if (ret) {
+ dev_err(dev, "error deasserting ssc_bcr: %d\n", ret);
+ return ret;
+ }
+
+ regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 0);
+
+ clk_prepare_enable(data->ssc_xo_clk);
+
+ clk_prepare_enable(data->ssc_ahbs_clk);
+
+ return 0;
+}
+
+static int qcom_ssc_block_bus_deinit(struct device *dev)
+{
+ int ret;
+
+ struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev);
+
+ clk_disable(data->ssc_xo_clk);
+ clk_disable(data->ssc_ahbs_clk);
+
+ ret = reset_control_assert(data->ssc_bcr);
+ if (ret) {
+ dev_err(dev, "error asserting ssc_bcr: %d\n", ret);
+ return ret;
+ }
+
+ regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 1);
+
+ reg32_set_bits(data->reg_mpm_sscaon_config1, BIT(31));
+ reg32_set_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5));
+
+ ret = reset_control_assert(data->ssc_reset);
+ if (ret) {
+ dev_err(dev, "error asserting ssc_reset: %d\n", ret);
+ return ret;
+ }
+
+ clk_disable(data->gcc_im_sleep_clk);
+
+ clk_disable(data->aggre2_north_clk);
+
+ clk_disable(data->aggre2_clk);
+ clk_disable(data->xo_clk);
+
+ return 0;
+}
+
+
+static int qcom_ssc_block_bus_pds_attach(struct device *dev, struct device **pds,
+ const char **pd_names, size_t num_pds)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < num_pds; i++) {
+ pds[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
+ if (IS_ERR_OR_NULL(pds[i])) {
+ ret = PTR_ERR(pds[i]) ? : -ENODATA;
+ goto unroll_attach;
+ }
+ }
+
+ return num_pds;
+
+unroll_attach:
+ for (i--; i >= 0; i--)
+ dev_pm_domain_detach(pds[i], false);
+
+ return ret;
+};
+
+static void qcom_ssc_block_bus_pds_detach(struct device *dev, struct device **pds, size_t num_pds)
+{
+ int i;
+
+ for (i = 0; i < num_pds; i++)
+ dev_pm_domain_detach(pds[i], false);
+}
+
+static int qcom_ssc_block_bus_pds_enable(struct device **pds, size_t num_pds)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < num_pds; i++) {
+ dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
+ ret = pm_runtime_get_sync(pds[i]);
+ if (ret < 0)
+ goto unroll_pd_votes;
+ }
+
+ return 0;
+
+unroll_pd_votes:
+ for (i--; i >= 0; i--) {
+ dev_pm_genpd_set_performance_state(pds[i], 0);
+ pm_runtime_put(pds[i]);
+ }
+
+ return ret;
+};
+
+static void qcom_ssc_block_bus_pds_disable(struct device **pds, size_t num_pds)
+{
+ int i;
+
+ for (i = 0; i < num_pds; i++) {
+ dev_pm_genpd_set_performance_state(pds[i], 0);
+ pm_runtime_put(pds[i]);
+ }
+}
+
+static int qcom_ssc_block_bus_probe(struct platform_device *pdev)
+{
+ struct qcom_ssc_block_bus_data *data;
+ struct device_node *np = pdev->dev.of_node;
+ struct of_phandle_args halt_args;
+ struct resource *res;
+ int ret;
+
+ if (np)
+ of_platform_populate(np, NULL, NULL, &pdev->dev);
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, data);
+
+ data->pd_names = qcom_ssc_block_pd_names;
+ data->num_pds = ARRAY_SIZE(qcom_ssc_block_pd_names);
+
+ ret = qcom_ssc_block_bus_pds_attach(&pdev->dev, data->pds, data->pd_names, data->num_pds);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "error when attaching power domains: %d\n", ret);
+ return ret;
+ }
+
+ ret = qcom_ssc_block_bus_pds_enable(data->pds, data->num_pds);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "error when enabling power domains: %d\n", ret);
+ return ret;
+ }
+
+ // the meaning of the bits in these two registers is sadly not documented,
+ // the set/clear operations are just copying what qcom does
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0");
+ data->reg_mpm_sscaon_config0 = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->reg_mpm_sscaon_config0)) {
+ ret = PTR_ERR(data->reg_mpm_sscaon_config0);
+ dev_err(&pdev->dev, "failed to ioremap mpm_sscaon_config0 (err: %d)\n", ret);
+ return ret;
+ }
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0");
+ data->reg_mpm_sscaon_config1 = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->reg_mpm_sscaon_config1)) {
+ ret = PTR_ERR(data->reg_mpm_sscaon_config1);
+ dev_err(&pdev->dev, "failed to ioremap mpm_sscaon_config1 (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->ssc_bcr = devm_reset_control_get_exclusive(&pdev->dev, "ssc_bcr");
+ if (IS_ERR(data->ssc_bcr)) {
+ ret = PTR_ERR(data->ssc_bcr);
+ dev_err(&pdev->dev, "failed to acquire reset: scc_bcr (err: %d)\n", ret);
+ return ret;
+ }
+ data->ssc_reset = devm_reset_control_get_exclusive(&pdev->dev, "ssc_reset");
+ if (IS_ERR(data->ssc_reset)) {
+ ret = PTR_ERR(data->ssc_reset);
+ dev_err(&pdev->dev, "failed to acquire reset: ssc_reset: (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->xo_clk = devm_clk_get(&pdev->dev, "xo");
+ if (IS_ERR(data->xo_clk)) {
+ ret = PTR_ERR(data->xo_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: xo (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->aggre2_clk = devm_clk_get(&pdev->dev, "aggre2");
+ if (IS_ERR(data->aggre2_clk)) {
+ ret = PTR_ERR(data->aggre2_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: aggre2 (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->gcc_im_sleep_clk = devm_clk_get(&pdev->dev, "gcc_im_sleep");
+ if (IS_ERR(data->gcc_im_sleep_clk)) {
+ ret = PTR_ERR(data->gcc_im_sleep_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: gcc_im_sleep (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->aggre2_north_clk = devm_clk_get(&pdev->dev, "aggre2_north");
+ if (IS_ERR(data->aggre2_north_clk)) {
+ ret = PTR_ERR(data->aggre2_north_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: aggre2_north (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->ssc_xo_clk = devm_clk_get(&pdev->dev, "ssc_xo");
+ if (IS_ERR(data->ssc_xo_clk)) {
+ ret = PTR_ERR(data->ssc_xo_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: ssc_xo (err: %d)\n", ret);
+ return ret;
+ }
+
+ data->ssc_ahbs_clk = devm_clk_get(&pdev->dev, "ssc_ahbs");
+ if (IS_ERR(data->ssc_ahbs_clk)) {
+ ret = PTR_ERR(data->ssc_ahbs_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Failed to get clock: ssc_ahbs (err: %d)\n", ret);
+ return ret;
+ }
+
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, "qcom,halt-regs", 1, 0,
+ &halt_args);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
+ return -EINVAL;
+ }
+
+ data->halt_map = syscon_node_to_regmap(halt_args.np);
+ of_node_put(halt_args.np);
+ if (IS_ERR(data->halt_map))
+ return PTR_ERR(data->halt_map);
+
+ data->ssc_axi_halt = halt_args.args[0];
+
+ qcom_ssc_block_bus_init(&pdev->dev);
+
+ return 0;
+}
+
+static int qcom_ssc_block_bus_remove(struct platform_device *pdev)
+{
+ struct qcom_ssc_block_bus_data *data = platform_get_drvdata(pdev);
+
+ qcom_ssc_block_bus_deinit(&pdev->dev);
+
+ iounmap(data->reg_mpm_sscaon_config0);
+ iounmap(data->reg_mpm_sscaon_config1);
+
+ qcom_ssc_block_bus_pds_disable(data->pds, data->num_pds);
+ qcom_ssc_block_bus_pds_detach(&pdev->dev, data->pds, data->num_pds);
+ pm_runtime_disable(&pdev->dev);
+ pm_clk_destroy(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id qcom_ssc_block_bus_of_match[] = {
+ { .compatible = "qcom,ssc-block-bus", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, qcom_ssc_block_bus_of_match);
+
+static struct platform_driver qcom_ssc_block_bus_driver = {
+ .probe = qcom_ssc_block_bus_probe,
+ .remove = qcom_ssc_block_bus_remove,
+ .driver = {
+ .name = "qcom-ssc-block-bus",
+ .of_match_table = qcom_ssc_block_bus_of_match,
+ },
+};
+
+module_platform_driver(qcom_ssc_block_bus_driver);
+
+MODULE_DESCRIPTION("A driver for handling the init sequence needed for accessing the SSC block on (some) qcom SoCs over AHB");
+MODULE_AUTHOR("Michael Srba <Michael.Srba@seznam.cz>");
+MODULE_LICENSE("GPL v2");
--
2.34.1
^ permalink raw reply related
* [PATCH v3 4/4] arm64: tegra: Add Tegra234 PWM devicetree nodes
From: Akhil R @ 2022-01-24 11:18 UTC (permalink / raw)
To: devicetree, digetx, jonathanh, ldewangan, linux-i2c, linux-kernel,
linux-tegra, mperttunen, robh+dt, thierry.reding
Cc: akhilrajeev
In-Reply-To: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com>
Add device tree nodes for Tegra234 PWM
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index c686827..cbebf1e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -234,6 +234,18 @@
reset-names = "i2c";
};
+ pwm1: pwm@3280000 {
+ compatible = "nvidia,tegra194-pwm",
+ "nvidia,tegra186-pwm";
+ reg = <0x3280000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM1>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM1>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
mmc@3460000 {
compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
reg = <0x03460000 0x20000>;
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/4] dt-bindings: Add headers for Tegra234 I2C
From: Akhil R @ 2022-01-24 11:18 UTC (permalink / raw)
To: devicetree, digetx, jonathanh, ldewangan, linux-i2c, linux-kernel,
linux-tegra, mperttunen, robh+dt, thierry.reding
Cc: akhilrajeev
In-Reply-To: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com>
Add dt-bindings header files for I2C controllers for Tegra234
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
include/dt-bindings/clock/tegra234-clock.h | 19 ++++++++++++++++++-
include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index 8d7e66e..dc524e6 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -20,6 +20,24 @@
#define TEGRA234_CLK_EMC 31U
/** @brief output of gate CLK_ENB_FUSE */
#define TEGRA234_CLK_FUSE 40U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
+#define TEGRA234_CLK_I2C1 48U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
+#define TEGRA234_CLK_I2C2 49U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
+#define TEGRA234_CLK_I2C3 50U
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
+#define TEGRA234_CLK_I2C4 51U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
+#define TEGRA234_CLK_I2C6 52U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
+#define TEGRA234_CLK_I2C7 53U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
+#define TEGRA234_CLK_I2C8 54U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
+#define TEGRA234_CLK_I2C9 55U
+/** @brief PLLP clk output */
+#define TEGRA234_CLK_PLLP_OUT0 102U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
#define TEGRA234_CLK_SDMMC4 123U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
@@ -30,5 +48,4 @@
#define TEGRA234_CLK_PLLC4 237U
/** @brief 32K input clock provided by PMIC */
#define TEGRA234_CLK_CLK_32K 289U
-
#endif
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index 50e13bc..2963259 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -10,6 +10,14 @@
* @brief Identifiers for Resets controllable by firmware
* @{
*/
+#define TEGRA234_RESET_I2C1 24U
+#define TEGRA234_RESET_I2C2 29U
+#define TEGRA234_RESET_I2C3 30U
+#define TEGRA234_RESET_I2C4 31U
+#define TEGRA234_RESET_I2C6 32U
+#define TEGRA234_RESET_I2C7 33U
+#define TEGRA234_RESET_I2C8 34U
+#define TEGRA234_RESET_I2C9 35U
#define TEGRA234_RESET_SDMMC4 85U
#define TEGRA234_RESET_UARTA 100U
--
2.7.4
^ permalink raw reply related
* [PATCH v3 3/4] dt-bindings: Add headers for Tegra234 PWM
From: Akhil R @ 2022-01-24 11:18 UTC (permalink / raw)
To: devicetree, digetx, jonathanh, ldewangan, linux-i2c, linux-kernel,
linux-tegra, mperttunen, robh+dt, thierry.reding
Cc: akhilrajeev
In-Reply-To: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com>
Add dt-bindings header files for PWM of Tegra234
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
include/dt-bindings/clock/tegra234-clock.h | 16 ++++++++++++++++
include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++
2 files changed, 24 insertions(+)
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index dc524e6..2529e7e 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -38,6 +38,22 @@
#define TEGRA234_CLK_I2C9 55U
/** @brief PLLP clk output */
#define TEGRA234_CLK_PLLP_OUT0 102U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
+#define TEGRA234_CLK_PWM1 105U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
+#define TEGRA234_CLK_PWM2 106U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
+#define TEGRA234_CLK_PWM3 107U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
+#define TEGRA234_CLK_PWM4 108U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
+#define TEGRA234_CLK_PWM5 109U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
+#define TEGRA234_CLK_PWM6 110U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
+#define TEGRA234_CLK_PWM7 111U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
+#define TEGRA234_CLK_PWM8 112U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
#define TEGRA234_CLK_SDMMC4 123U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index 2963259..ba390b8 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -18,6 +18,14 @@
#define TEGRA234_RESET_I2C7 33U
#define TEGRA234_RESET_I2C8 34U
#define TEGRA234_RESET_I2C9 35U
+#define TEGRA234_RESET_PWM1 68U
+#define TEGRA234_RESET_PWM2 69U
+#define TEGRA234_RESET_PWM3 70U
+#define TEGRA234_RESET_PWM4 71U
+#define TEGRA234_RESET_PWM5 72U
+#define TEGRA234_RESET_PWM6 73U
+#define TEGRA234_RESET_PWM7 74U
+#define TEGRA234_RESET_PWM8 75U
#define TEGRA234_RESET_SDMMC4 85U
#define TEGRA234_RESET_UARTA 100U
--
2.7.4
^ permalink raw reply related
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