* Re: [PATCH v3 5/5] arm64: dts: qcom: msm8998: reserve potentially inaccessible clocks With the gcc driver now being more complete and describing clocks which might not always be write-accessible to the OS, conservatively specify all such clocks as protected in the SoC dts. The board dts - or even user-supplied dts - can override this property to reflect the actual configuration.
From: Bjorn Andersson @ 2022-01-26 3:48 UTC (permalink / raw)
To: michael.srba
Cc: Andy Gross, Rob Herring, Stephen Boyd, Philipp Zabel,
Linus Walleij, Florian Fainelli, Arnd Bergmann,
Greg Kroah-Hartman, Saravana Kannan, linux-arm-msm, devicetree
In-Reply-To: <20220124121853.23600-5-michael.srba@seznam.cz>
On Mon 24 Jan 06:18 CST 2022, michael.srba@seznam.cz wrote:
> From: Michael Srba <michael.srba@seznam.cz>
>
Something is off with your $subject, perhaps the entire commit message
was treated as the subject?
> Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
> ---
> CHANGES:
> - v2: add this patch
> - v3: fix missing Signed-off-by
> ---
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index f273bc1ff629..cff83af8c12e 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -863,6 +863,12 @@ gcc: clock-controller@100000 {
>
> clock-names = "xo", "sleep_clk";
> clocks = <&xo>, <&sleep_clk>;
> +
> + // be conservative by default, the board dts
> + // can overwrite this list
By next week we've forgotten why these clocks are listed here and then
it's not really going to help to know that it's a conservative list.
Please spell out why these clocks are listed here, and please use /* */
Thanks,
Bjorn
> + protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
> + <SSC_XO>,
> + <SSC_CNOC_AHBS_CLK>;
> };
>
> rpm_msg_ram: sram@778000 {
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH 3/3] ARM: dts: qcom: basic HP TouchPad support
From: Bjorn Andersson @ 2022-01-26 4:13 UTC (permalink / raw)
To: Ben Wolsieffer, linus.walleij
Cc: Andy Gross, Rob Herring, Arnd Bergmann, Olof Johansson, soc,
Stephen Boyd, linux-arm-msm, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <9f19df2a0017b71547445ac34df221e827c45bd0.1643075547.git.benwolsieffer@gmail.com>
On Mon 24 Jan 20:07 CST 2022, Ben Wolsieffer wrote:
> Modify the Dragonboard device tree to support the most basic hardware on
> the HP TouchPad. The headphone UART port and eMMC are supported.
>
We typically don't have one commit for the cloning and then one to
update the content, in particular since your diffstat became rather
weird.
That said, got some comments below, things that I wouldn't have spotted
if you sent this as just a new file.
> Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com>
> ---
@Linus, please take a look at the regulator question below.
> arch/arm/boot/dts/qcom-apq8060-tenderloin.dts | 549 ++----------------
> 1 file changed, 45 insertions(+), 504 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8060-tenderloin.dts b/arch/arm/boot/dts/qcom-apq8060-tenderloin.dts
> index 996e73aa0b0b..e294f3920b9f 100644
> --- a/arch/arm/boot/dts/qcom-apq8060-tenderloin.dts
> +++ b/arch/arm/boot/dts/qcom-apq8060-tenderloin.dts
> @@ -14,6 +14,8 @@ aliases {
> };
>
> chosen {
> + /* Bootloader passes console=tty1, which overrides stdout-path */
> + bootargs = "console=ttyMSM0,115200 earlycon";
> stdout-path = "serial0:115200n8";
> };
[..]
>
> soc {
> pinctrl@800000 {
> - /* eMMMC pins, all 8 data lines connected */
It would be nice if you could throw a separate patch on the list that
fixes this spelling mistake in the original as well.
> - dragon_sdcc1_pins: sdcc1 {
> + /* eMMC pins, all 8 data lines connected */
> + emmc_pins: sdcc1 {
> mux {
> pins = "gpio159", "gpio160", "gpio161",
> "gpio162", "gpio163", "gpio164",
> "gpio165", "gpio166", "gpio167",
> "gpio168";
> - function = "sdc1";
> + function = "sdc1";
> };
> clk {
> pins = "gpio167"; /* SDC1 CLK */
[..]
> @@ -171,205 +77,33 @@ pinconf {
> };
> };
>
> - dragon_gsbi12_i2c_pins: gsbi12_i2c {
> - mux {
> - pins = "gpio115", "gpio116";
> - function = "gsbi12";
> - };
> - pinconf {
> - pins = "gpio115", "gpio116";
> - drive-strength = <16>;
> - /* These have external pull-up 4.7kOhm to 1.8V */
> - bias-disable;
> - };
> - };
> -
> - /* Primary serial port uart 0 pins */
> - dragon_gsbi12_serial_pins: gsbi12_serial {
> + /* Headphone UART pins */
> + headphone_uart_pins: gsbi12_serial {
> mux {
> pins = "gpio117", "gpio118";
> function = "gsbi12";
> };
> - tx {
> - pins = "gpio117";
> - drive-strength = <8>;
> - bias-disable;
> - };
> rx {
> - pins = "gpio118";
> + pins = "gpio117";
> drive-strength = <2>;
> bias-pull-up;
> };
> - };
I find it hard to conclude what the resulting snippet is from this
chunk, did rx swap place from gpio118 to gpio117?
[..]
> @@ -814,14 +378,16 @@ l20 {
> bias-pull-down;
> };
> l21 {
> - // 1.1 V according to schematic
> regulator-min-microvolt = <1200000>;
> regulator-max-microvolt = <1200000>;
> bias-pull-down;
> - regulator-always-on;
> + /*
> + * RPM driver can't handle always-on regulators that are
> + * supplied by regulators initialized after them.
> + */
That looks like an oversight that should be corrected, perhaps it needs
similar attention that was given to the smd-rpm driver recently?
But this makes me wonder, how can this work on the other board? Linus?
> + // regulator-always-on;
> };
> l22 {
> - // 1.2 V according to schematic
> regulator-min-microvolt = <1150000>;
> regulator-max-microvolt = <1150000>;
> bias-pull-down;
> @@ -845,7 +411,7 @@ l25 {
> };
>
> s0 {
> - // regulator-min-microvolt = <500000>;
> + // regulator-min-microvolt = <800000>;
> // regulator-max-microvolt = <1325000>;
This looks like the full range the regulator could do, do you see a
reason for documenting that here? Unless there's a good reason I think
you should leave the commented min/max out.
> regulator-min-microvolt = <1100000>;
> regulator-max-microvolt = <1100000>;
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCH 2/3] dt-bindings: arm: qcom: document HP TouchPad
From: Bjorn Andersson @ 2022-01-26 4:13 UTC (permalink / raw)
To: Ben Wolsieffer
Cc: Andy Gross, Rob Herring, Arnd Bergmann, Olof Johansson, soc,
Stephen Boyd, linux-arm-msm, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <aa59002aeae45a95097300213fc34490aa8db250.1643075547.git.benwolsieffer@gmail.com>
On Mon 24 Jan 20:07 CST 2022, Ben Wolsieffer wrote:
> Add binding documentation for the HP TouchPad.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 370aab274cd1..f7418a8a49fc 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -119,6 +119,7 @@ properties:
> - items:
> - enum:
> - qcom,apq8060-dragonboard
> + - qcom,apq8060-tenderloin
> - qcom,msm8660-surf
> - const: qcom,msm8660
>
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH V4 2/6] bindings: usb: dwc3: Update dwc3 properties for EUD connector
From: Bjorn Andersson @ 2022-01-26 4:21 UTC (permalink / raw)
To: Souradeep Chowdhury
Cc: linux-arm-msm, linux-usb, devicetree, pure.logic, greg, robh,
linux-kernel, quic_tsoni, quic_psodagud, quic_satyap,
quic_pheragu, quic_rjendra, quic_sibis, quic_saipraka
In-Reply-To: <7ddaf7dc192c5f03f70d27297551e758a39a4ab5.1642768837.git.quic_schowdhu@quicinc.com>
On Fri 21 Jan 07:53 CST 2022, Souradeep Chowdhury wrote:
> Add the ports property for dwc3 node. This port can be used
> by the Embedded USB Debugger for role switching the controller
> from device to host mode and vice versa.
>
> Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
> ---
> Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> index d29ffcd..ccb1236 100644
> --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> @@ -332,6 +332,16 @@ properties:
> items:
> enum: [1, 4, 8, 16, 32, 64, 128, 256]
>
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + description:
> + This port is to be attached to the endpoint of the Embedded USB Debugger.
More generally this is used together with the already documented
usb-role-switch property to connect the dwc3 to the Type-C connector.
Which makes me feel that we don't actually need ports/port, but could do
with just port? Perhaps I'm missing some usecase?
I'm somewhat confused to why this isn't already documented...
Regards,
Bjorn
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Connector endpoint of Embedded USB debugger.
> +
> unevaluatedProperties: false
>
> required:
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH V4 1/6] dt-bindings: Add the yaml bindings for EUD
From: Bjorn Andersson @ 2022-01-26 4:22 UTC (permalink / raw)
To: Souradeep Chowdhury
Cc: linux-arm-msm, linux-usb, devicetree, pure.logic, greg, robh,
linux-kernel, quic_tsoni, quic_psodagud, quic_satyap,
quic_pheragu, quic_rjendra, quic_sibis, quic_saipraka
In-Reply-To: <91c61d815123fb0b7e067e368d784e3434997068.1642768837.git.quic_schowdhu@quicinc.com>
On Fri 21 Jan 07:53 CST 2022, Souradeep Chowdhury wrote:
> Documentation for Embedded USB Debugger(EUD) device tree
> bindings in yaml format.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
> ---
> .../devicetree/bindings/soc/qcom/qcom,eud.yaml | 77 ++++++++++++++++++++++
> 1 file changed, 77 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
> new file mode 100644
> index 0000000..c98aab2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/soc/qcom/qcom,eud.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Qualcomm Embedded USB Debugger
> +
> +maintainers:
> + - Souradeep Chowdhury <quic_schowdhu@quicinc.com>
> +
> +description:
> + This binding is used to describe the Qualcomm Embedded USB Debugger, which is
> + mini USB-hub implemented on chip to support USB-based debug capabilities.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - qcom,sc7280-eud
> + - const: qcom,eud
> +
> + reg:
> + items:
> + - description: EUD Base Register Region
> + - description: EUD Mode Manager Register
> +
> + interrupts:
> + description: EUD interrupt
> + maxItems: 1
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + description:
> + These ports are to be attached to the endpoint of the DWC3 controller node
> + and type C connector node. The controller has the "usb-role-switch"
> + property.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: This port is to be attached to the DWC3 controller.
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: This port is to be attached to the type C connector.
> +
> +required:
> + - compatible
> + - reg
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + eud@88e0000 {
> + compatible = "qcom,sc7280-eud","qcom,eud";
> + reg = <0x88e0000 0x2000>,
> + <0x88e2000 0x1000>;
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + eud_ep: endpoint {
> + remote-endpoint = <&usb2_role_switch>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + eud_con: endpoint {
> + remote-endpoint = <&con_eud>;
> + };
> + };
> + };
> + };
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH V4 4/6] arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connector
From: Bjorn Andersson @ 2022-01-26 4:28 UTC (permalink / raw)
To: Souradeep Chowdhury
Cc: linux-arm-msm, linux-usb, devicetree, pure.logic, greg, robh,
linux-kernel, quic_tsoni, quic_psodagud, quic_satyap,
quic_pheragu, quic_rjendra, quic_sibis, quic_saipraka
In-Reply-To: <3ca56ffa9e4aa73f3c3f36d0edad0827ee11d953.1642768837.git.quic_schowdhu@quicinc.com>
On Fri 21 Jan 07:53 CST 2022, Souradeep Chowdhury wrote:
> Add the Embedded USB Debugger(EUD) device tree node. The
> node contains EUD base register region and EUD mode
> manager register regions along with the interrupt entry.
> Also add the typec connector node for EUD which is attached to
> EUD node via port. EUD is also attached to DWC3 node via port.
> Also add the role-switch property to dwc3 node.
>
> Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 39 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 937c2e0..daac831 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2583,6 +2583,14 @@
> phys = <&usb_2_hsphy>;
> phy-names = "usb2-phy";
> maximum-speed = "high-speed";
> + usb-role-switch;
> + ports {
> + port@0 {
> + usb2_role_switch: endpoint {
> + remote-endpoint = <&eud_ep>;
> + };
> + };
> + };
> };
> };
>
> @@ -2624,6 +2632,37 @@
> interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + eud: eud@88e0000 {
> + compatible = "qcom,sc7280-eud","qcom,eud";
> + reg = <0 0x88e0000 0 0x2000>,
> + <0 0x88e2000 0 0x1000>;
> + interrupt-parent = <&pdc>;
> + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
I find "interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;" cleaner
than having to specify both parent and interrupts.
> + ports {
> + port@0 {
> + eud_ep: endpoint {
> + remote-endpoint = <&usb2_role_switch>;
> + };
> + };
> + port@1 {
> + eud_con: endpoint {
> + remote-endpoint = <&con_eud>;
> + };
> + };
> + };
> + };
> +
> + eud_typec: connector {
The connector should be a child of the Type-C controller, which I know
differs between the various devices on this platform. So you should
leave &eud_con without a remote-endpoint and then fill that in for each
device, based on respective Type-C controller.
But beyond that, I think this design looks good now!
Regards,
Bjorn
> + compatible = "usb-c-connector";
> + ports {
> + port@0 {
> + con_eud: endpoint {
> + remote-endpoint = <&eud_con>;
> + };
> + };
> + };
> + };
> +
> nsp_noc: interconnect@a0c0000 {
> reg = <0 0x0a0c0000 0 0x10000>;
> compatible = "qcom,sc7280-nsp-noc";
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH V4 5/6] arm64: dts: qcom: sc7280: Set the default dr_mode for usb2
From: Bjorn Andersson @ 2022-01-26 4:29 UTC (permalink / raw)
To: Souradeep Chowdhury
Cc: linux-arm-msm, linux-usb, devicetree, pure.logic, greg, robh,
linux-kernel, quic_tsoni, quic_psodagud, quic_satyap,
quic_pheragu, quic_rjendra, quic_sibis, quic_saipraka
In-Reply-To: <232f37a6f76c3f24a122f32978b5c1e73dc7e7c4.1642768837.git.quic_schowdhu@quicinc.com>
On Fri 21 Jan 07:53 CST 2022, Souradeep Chowdhury wrote:
> Set the default dr_mode for usb2 node to "otg" to enable
> role-switch for EUD(Embedded USB Debugger) connector node.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index 9b991ba..f40eaa5 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -61,6 +61,10 @@
> modem-init;
> };
>
> +&usb_2_dwc3 {
> + dr_mode = "otg";
> +};
> +
> &pmk8350_rtc {
> status = "okay";
> };
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH V4 6/6] MAINTAINERS: Add maintainer entry for EUD
From: Bjorn Andersson @ 2022-01-26 4:29 UTC (permalink / raw)
To: Souradeep Chowdhury
Cc: linux-arm-msm, linux-usb, devicetree, pure.logic, greg, robh,
linux-kernel, quic_tsoni, quic_psodagud, quic_satyap,
quic_pheragu, quic_rjendra, quic_sibis, quic_saipraka
In-Reply-To: <d8079cb1001675cd876f1e051647a65a7733b81c.1642768837.git.quic_schowdhu@quicinc.com>
On Fri 21 Jan 07:53 CST 2022, Souradeep Chowdhury wrote:
> Add the entry for maintainer for EUD driver
> and other associated files.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
> ---
> MAINTAINERS | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b84e2d5..0fa9d54 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7227,6 +7227,14 @@ F: include/uapi/linux/mdio.h
> F: include/uapi/linux/mii.h
> F: net/core/of_net.c
>
> +QCOM EMBEDDED USB DEBUGGER(EUD)
> +M: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
> +L: linux-arm-msm@vger.kernel.org
> +S: Maintained
> +F: Documentation/ABI/testing/sysfs-driver-eud
> +F: Documentation/devicetree/bindings/arm/msm/qcom,eud.yaml
> +F: drivers/usb/common/qcom_eud.c
> +
> EXEC & BINFMT API
> R: Eric Biederman <ebiederm@xmission.com>
> R: Kees Cook <keescook@chromium.org>
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH V4 3/6] soc: qcom: eud: Add driver support for Embedded USB Debugger(EUD)
From: Bjorn Andersson @ 2022-01-26 4:47 UTC (permalink / raw)
To: Souradeep Chowdhury
Cc: linux-arm-msm, linux-usb, devicetree, pure.logic, greg, robh,
linux-kernel, quic_tsoni, quic_psodagud, quic_satyap,
quic_pheragu, quic_rjendra, quic_sibis, quic_saipraka
In-Reply-To: <7ccee5ae484e6917f5838c8abde368680ec63d05.1642768837.git.quic_schowdhu@quicinc.com>
On Fri 21 Jan 07:53 CST 2022, Souradeep Chowdhury wrote:
> Add support for control peripheral of EUD (Embedded USB Debugger) to
> listen to events such as USB attach/detach, pet EUD to indicate software
> is functional.Reusing the platform device kobj, sysfs entry 'enable' is
> created to enable or disable EUD.
>
> To enable the eud the following needs to be done
> echo 1 > /sys/bus/platform/.../enable
>
> To disable eud, following is the command
> echo 0 > /sys/bus/platform/.../enable
>
> Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
> ---
> Documentation/ABI/testing/sysfs-driver-eud | 9 ++
> drivers/soc/qcom/Kconfig | 10 ++
> drivers/soc/qcom/Makefile | 1 +
> drivers/soc/qcom/qcom_eud.c | 250 +++++++++++++++++++++++++++++
> 4 files changed, 270 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-driver-eud
> create mode 100644 drivers/soc/qcom/qcom_eud.c
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-eud b/Documentation/ABI/testing/sysfs-driver-eud
> new file mode 100644
> index 0000000..2381552
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-driver-eud
> @@ -0,0 +1,9 @@
> +What: /sys/bus/platform/drivers/eud/.../enable
> +Date: January 2022
> +Contact: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
> +Description:
> + The Enable/Disable sysfs interface for Embedded
> + USB Debugger(EUD). This enables and disables the
> + EUD based on a 1 or a 0 value. By enabling EUD,
> + the user is able to activate the mini-usb hub of
> + EUD for debug and trace capabilities.
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index e718b87..abc6be0 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -42,6 +42,16 @@ config QCOM_CPR
> To compile this driver as a module, choose M here: the module will
> be called qcom-cpr
>
> +config QCOM_EUD
> + tristate "QCOM Embedded USB Debugger(EUD) Driver"
The indentation looks off here.
> + select USB_ROLE_SWITCH
> + help
> + This module enables support for Qualcomm Technologies, Inc.
> + Embedded USB Debugger (EUD). The EUD is a control peripheral
> + which reports VBUS attach/detach events and has USB-based
> + debug and trace capabilities. On selecting m, the module name
> + that is built is qcom_eud.ko
> +
> config QCOM_GENI_SE
> tristate "QCOM GENI Serial Engine Driver"
> depends on ARCH_QCOM || COMPILE_TEST
> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> index 70d5de6..e0c7d2d 100644
> --- a/drivers/soc/qcom/Makefile
> +++ b/drivers/soc/qcom/Makefile
> @@ -4,6 +4,7 @@ obj-$(CONFIG_QCOM_AOSS_QMP) += qcom_aoss.o
> obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
> obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
> obj-$(CONFIG_QCOM_CPR) += cpr.o
> +obj-$(CONFIG_QCOM_EUD) += qcom_eud.o
> obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
> obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
> obj-$(CONFIG_QCOM_OCMEM) += ocmem.o
> diff --git a/drivers/soc/qcom/qcom_eud.c b/drivers/soc/qcom/qcom_eud.c
> new file mode 100644
> index 0000000..a538645
> --- /dev/null
> +++ b/drivers/soc/qcom/qcom_eud.c
> @@ -0,0 +1,250 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/err.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/sysfs.h>
> +#include <linux/usb/role.h>
> +
> +#define EUD_REG_INT1_EN_MASK 0x0024
> +#define EUD_REG_INT_STATUS_1 0x0044
> +#define EUD_REG_CTL_OUT_1 0x0074
> +#define EUD_REG_VBUS_INT_CLR 0x0080
> +#define EUD_REG_CSR_EUD_EN 0x1014
> +#define EUD_REG_SW_ATTACH_DET 0x1018
> +#define EUD_REG_EUD_EN2 0x0000
> +
> +#define EUD_ENABLE BIT(0)
> +#define EUD_INT_PET_EUD BIT(0)
> +#define EUD_INT_VBUS BIT(2)
> +#define EUD_INT_SAFE_MODE BIT(4)
> +#define EUD_INT_ALL (EUD_INT_VBUS|EUD_INT_SAFE_MODE)
> +
> +struct eud_chip {
> + struct device *dev;
> + struct usb_role_switch *role_sw;
> + void __iomem *base;
> + void __iomem *mode_mgr;
> + unsigned int int_status;
> + int irq;
> + bool enabled;
> + bool usb_attached;
> +};
> +
> +static int enable_eud(struct eud_chip *priv)
> +{
> + writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN);
> + writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE,
> + priv->base + EUD_REG_INT1_EN_MASK);
> + writel(1, priv->mode_mgr + EUD_REG_EUD_EN2);
> +
> + return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE);
So we won't get EUD_INT_VBUS when we enable the EUD and can rely on the
irq handler to set the role?
> +}
> +
> +static void disable_eud(struct eud_chip *priv)
> +{
> + writel(0, priv->base + EUD_REG_CSR_EUD_EN);
> + writel(0, priv->mode_mgr + EUD_REG_EUD_EN2);
> +}
> +
> +static ssize_t enable_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct eud_chip *chip = dev_get_drvdata(dev);
> +
> + return sysfs_emit(buf, "%d\n", chip->enabled);
> +}
> +
> +static ssize_t enable_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct eud_chip *chip = dev_get_drvdata(dev);
> + bool enable;
> + int ret;
> +
> + if (kstrtobool(buf, &enable))
> + return -EINVAL;
> +
> + if (enable) {
> + ret = enable_eud(chip);
> + if (!ret)
> + chip->enabled = enable;
> + else
> + disable_eud(chip);
> + } else {
> + disable_eud(chip);
> + }
> +
> + return count;
> +}
> +
> +static DEVICE_ATTR_RW(enable);
> +
> +static struct attribute *eud_attrs[] = {
> + &dev_attr_enable.attr,
> + NULL,
> +};
> +ATTRIBUTE_GROUPS(eud);
> +
> +static void usb_attach_detach(struct eud_chip *chip)
> +{
> + u32 reg;
> +
> + /* read ctl_out_1[4] to find USB attach or detach event */
> + reg = readl(chip->base + EUD_REG_CTL_OUT_1);
> + chip->usb_attached = reg & EUD_INT_SAFE_MODE;
> +}
> +
> +static void pet_eud(struct eud_chip *chip)
> +{
> + u32 reg;
> + int ret;
> +
> + /* When the EUD_INT_PET_EUD in SW_ATTACH_DET is set, the cable has been
> + * disconnected and we need to detach the pet to check if EUD is in safe
> + * mode before attaching again.
> + */
> + reg = readl(chip->base + EUD_REG_SW_ATTACH_DET);
> + if (reg & EUD_INT_PET_EUD) {
> + /* Detach & Attach pet for EUD */
> + writel(0, chip->base + EUD_REG_SW_ATTACH_DET);
> + /* Delay to make sure detach pet is done before attach pet */
> + ret = readl_poll_timeout(chip->base + EUD_REG_SW_ATTACH_DET,
> + reg, (reg == 0), 1, 100);
> + if (ret) {
> + dev_err(chip->dev, "Detach pet failed\n");
> + return;
> + }
> + }
> + /* Attach pet for EUD */
> + writel(EUD_INT_PET_EUD, chip->base +EUD_REG_SW_ATTACH_DET);
> +}
> +
> +static irqreturn_t handle_eud_irq(int irq, void *data)
> +{
> + struct eud_chip *chip = data;
> + u32 reg;
> +
> + reg = readl(chip->base + EUD_REG_INT_STATUS_1);
> + switch (reg & EUD_INT_ALL) {
> + case EUD_INT_VBUS:
> + chip->int_status = EUD_INT_VBUS;
The first time that reg & EUD_INT_VBUS is set, you assign int_status
EUD_INT_VBUS, you never clear it again.
This is also the only path where you wake up the thread, so int_status
will always be EUD_INT_VBUS when you reach handle_eud_irq_thread().
Which means that int_status serves no purpose and if you're happy with
how this implementation currently works you can just drop "int_status"
and the conditional below.
> + usb_attach_detach(chip);
> + return IRQ_WAKE_THREAD;
> + case EUD_INT_SAFE_MODE:
> + pet_eud(chip);
> + return IRQ_HANDLED;
> + default:
> + return IRQ_NONE;
> + }
> +}
> +
> +static irqreturn_t handle_eud_irq_thread(int irq, void *data)
> +{
> + struct eud_chip *chip = data;
> + int ret;
> +
> + if (chip->int_status == EUD_INT_VBUS) {
> + if (chip->usb_attached)
> + ret = usb_role_switch_set_role(chip->role_sw, USB_ROLE_DEVICE);
> + else
> + ret = usb_role_switch_set_role(chip->role_sw, USB_ROLE_HOST);
> + if (ret)
> + dev_err(chip->dev, "failed to set role switch\n");
> + }
> +
> + /* set and clear vbus_int_clr[0] to clear interrupt */
> + writel(BIT(0), chip->base + EUD_REG_VBUS_INT_CLR);
> + writel(0, chip->base + EUD_REG_VBUS_INT_CLR);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int eud_probe(struct platform_device *pdev)
> +{
> + struct eud_chip *chip;
> + struct fwnode_handle *fwnode = pdev->dev.fwnode, *dwc3;
> + int ret;
> +
> + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
> + if (!chip)
> + return -ENOMEM;
> +
> + chip->dev = &pdev->dev;
> +
> + dwc3 = fwnode_graph_get_next_endpoint(fwnode, NULL);
This will pick the first endpoint, but if you instead use
chip->role_sw = usb_role_switch_get(&pdev->dev);
you should get whichever port that points to a usb-role-switch node,
without having to do the fwnode dance (and refcounting, which you forgot
to release).
> + if (!dwc3)
> + return -ENODEV;
> +
> + chip->role_sw = fwnode_usb_role_switch_get(dwc3);
> + if (IS_ERR(chip->role_sw)) {
> + ret = PTR_ERR(chip->role_sw);
> + usb_role_switch_put(chip->role_sw);
You don't need to return the role_sw if it's IS_ERR().
> + return dev_err_probe(chip->dev, ret,
> + "failed to get role switch\n");
> + }
> +
> + chip->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(chip->base))
You're not usb_role_switch_put() your role_sw here, or below return
cases. I would recommend devm_add_action_or_reset() to avoid the hassle
of adding the necessary cleanup logic.
> + return PTR_ERR(chip->base);
> +
> + chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(chip->mode_mgr))
> + return PTR_ERR(chip->mode_mgr);
> +
> + chip->irq = platform_get_irq(pdev, 0);
> + ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq,
> + handle_eud_irq_thread, IRQF_ONESHOT, NULL, chip);
> + if (ret)
> + return dev_err_probe(chip->dev, ret, "failed to allocate irq\n");
> +
> + enable_irq_wake(chip->irq);
> +
> + platform_set_drvdata(pdev, chip);
> +
> + return 0;
Per the updated binding, the EUD would now be a usb-role-switch as well
and when not enabled should simply propagate the incoming requests. So I
was expecting this to register as a usb_role_switch as well...
> +}
> +
> +static int eud_remove(struct platform_device *pdev)
> +{
> + struct eud_chip *chip = platform_get_drvdata(pdev);
> +
> + if (chip->enabled)
> + disable_eud(chip);
> +
> + device_init_wakeup(&pdev->dev, false);
> + disable_irq_wake(chip->irq);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id eud_dt_match[] = {
> + { .compatible = "qcom,sc7280-eud" },
Do you see any reason for not just adding qcom,eud here? Are there any
differences from other platforms that has this block that means that we
need per-platform driver support (the dts should have both
compatibles still)?
Regards,
Bjorn
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, eud_dt_match);
> +
> +static struct platform_driver eud_driver = {
> + .probe = eud_probe,
> + .remove = eud_remove,
> + .driver = {
> + .name = "qcom_eud",
> + .dev_groups = eud_groups,
> + .of_match_table = eud_dt_match,
> + },
> +};
> +module_platform_driver(eud_driver);
> +
> +MODULE_DESCRIPTION("QTI EUD driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH 0/3] arm64: dts: meson: add ATF BL32 reserved-memory regions
From: Christian Hewitt @ 2022-01-26 4:49 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kevin Hilman, Neil Armstrong,
devicetree, linux-arm-kernel, linux-amlogic, linux-kernel
Cc: Christian Hewitt
This series supersedes [0] which fixed a long-running kernel panic issue
seen with Beelink G12B devices booted from Amlogic vendor firmware. The
same issue exists with a wider set of devices from GXBB to SM1, although
it is not often seen due to my kernel fork including 'catch-all' patches
for some time (the meson-gx patch was suggested by Matheusz in 2019) and
many distros actively supporting Amlogic hardware consuming some or all
of my regular patchset.
I've also included a cleanup to the SEI510/SEI610 board files. If that's
not desirable feel free to ignore that patch. I also dropped the fixes
tagging as I'm not sure what original commits could be targetted. If you
think fixes are good please provide some guidance and I'll be happy to
send a revised series.
[0] https://patchwork.kernel.org/project/linux-amlogic/list/?series=607446
Christian Hewitt (3):
arm64: dts: meson-gx: add ATF BL32 reserved-memory region
arm64: dts: meson-g12: add ATF BL32 reserved-memory region
arm64: dts: meson-g12: drop BL32 region from SEI510/SEI610
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 6 ++++++
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | 8 --------
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 6 ++++++
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts | 8 --------
4 files changed, 12 insertions(+), 16 deletions(-)
--
2.17.1
^ permalink raw reply
* [PATCH 1/3] arm64: dts: meson-gx: add ATF BL32 reserved-memory region
From: Christian Hewitt @ 2022-01-26 4:49 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kevin Hilman, Neil Armstrong,
devicetree, linux-arm-kernel, linux-amlogic, linux-kernel
Cc: Christian Hewitt
In-Reply-To: <20220126044954.19069-1-christianshewitt@gmail.com>
Add an additional reserved memory region for the BL32 trusted firmware
present in many devices that boot from Amlogic vendor u-boot.
Suggested-by: Mateusz Krzak <kszaquitto@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 6b457b2c30a4..aa14ea017a61 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -49,6 +49,12 @@
no-map;
};
+ /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
+ secmon_reserved_bl32: secmon@5300000 {
+ reg = <0x0 0x05300000 0x0 0x2000000>;
+ no-map;
+ };
+
linux,cma {
compatible = "shared-dma-pool";
reusable;
--
2.17.1
^ permalink raw reply related
* [PATCH 3/3] arm64: dts: meson-g12: drop BL32 region from SEI510/SEI610
From: Christian Hewitt @ 2022-01-26 4:49 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kevin Hilman, Neil Armstrong,
devicetree, linux-arm-kernel, linux-amlogic, linux-kernel
Cc: Christian Hewitt
In-Reply-To: <20220126044954.19069-1-christianshewitt@gmail.com>
The BL32/TEE reserved-memory region is now inherited from the common
family dtsi (meson-g12-common) so we can drop it from board files.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | 8 --------
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts | 8 --------
2 files changed, 16 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
index d8838dde0f0f..4fb31c2ba31c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
@@ -157,14 +157,6 @@
regulator-always-on;
};
- reserved-memory {
- /* TEE Reserved Memory */
- bl32_reserved: bl32@5000000 {
- reg = <0x0 0x05300000 0x0 0x2000000>;
- no-map;
- };
- };
-
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
index 427475846fc7..a5d79f2f7c19 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
@@ -203,14 +203,6 @@
regulator-always-on;
};
- reserved-memory {
- /* TEE Reserved Memory */
- bl32_reserved: bl32@5000000 {
- reg = <0x0 0x05300000 0x0 0x2000000>;
- no-map;
- };
- };
-
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
--
2.17.1
^ permalink raw reply related
* [PATCH 2/3] arm64: dts: meson-g12: add ATF BL32 reserved-memory region
From: Christian Hewitt @ 2022-01-26 4:49 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kevin Hilman, Neil Armstrong,
devicetree, linux-arm-kernel, linux-amlogic, linux-kernel
Cc: Christian Hewitt
In-Reply-To: <20220126044954.19069-1-christianshewitt@gmail.com>
Add an additional reserved memory region for the BL32 trusted firmware
present in many devices that boot from Amlogic vendor u-boot.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index 6d99c23261fb..45947c1031c4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -107,6 +107,12 @@
no-map;
};
+ /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
+ secmon_reserved_bl32: secmon@5300000 {
+ reg = <0x0 0x05300000 0x0 0x2000000>;
+ no-map;
+ };
+
linux,cma {
compatible = "shared-dma-pool";
reusable;
--
2.17.1
^ permalink raw reply related
* Re: [PATCH 1/3] arm64: dts: meson-gx: add ATF BL32 reserved-memory region
From: Vyacheslav @ 2022-01-26 5:35 UTC (permalink / raw)
To: Christian Hewitt, Rob Herring, Mark Rutland, Kevin Hilman,
Neil Armstrong, devicetree, linux-arm-kernel, linux-amlogic,
linux-kernel
In-Reply-To: <20220126044954.19069-2-christianshewitt@gmail.com>
Hi!
26.01.2022 07:49, Christian Hewitt wrote:
> Add an additional reserved memory region for the BL32 trusted firmware
> present in many devices that boot from Amlogic vendor u-boot.
>
> Suggested-by: Mateusz Krzak <kszaquitto@gmail.com>
> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index 6b457b2c30a4..aa14ea017a61 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -49,6 +49,12 @@
> no-map;
> };
>
> + /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
> + secmon_reserved_bl32: secmon@5300000 {
> + reg = <0x0 0x05300000 0x0 0x2000000>;
> + no-map;
> + };
> +
How do I check if we need a similar patch for axg boards?
> linux,cma {
> compatible = "shared-dma-pool";
> reusable;
>
^ permalink raw reply
* [PATCH V1 Create empty OF root 0/1] XRT Alveo driver infrastructure overview
From: Lizhi Hou @ 2022-01-26 5:48 UTC (permalink / raw)
To: devicetree, robh
Cc: Lizhi Hou, linux-kernel, yilun.xu, maxz, sonal.santan, yliu,
michal.simek, stefanos, trix, mdf, dwmw2
Hello,
Xilinx Alveo PCIe accelerator cards use flattened device tree to describe
HW subsystems or endpoints. Each device tree node represents a hardware
endpoint and each endpoint is an hardware unit which requires a driver.
The product detail:
https://www.xilinx.com/products/boards-and-kits/alveo.html
The feedback from the previous patches was to create a base tree if there
is not one and apply the unflattened device nodes by existing Linux
platform device and OF infrastructure. Please refer to previous discussion
with device tree and fpga maintainers.
https://lore.kernel.org/lkml/CAL_JsqJfyRymB=VxLuQqLpep+Q1Eie48dobv9sC5OizDz0d2DQ@mail.gmail.com/
https://lore.kernel.org/lkml/20220105225013.1567871-1-lizhi.hou@xilinx.com/
This patch adds OF_EMPTY_ROOT config. When it is selected and there is not
a device tree, create an empty device tree root node.
Lizhi Hou (1):
of: create empty of root
drivers/of/Kconfig | 3 +++
drivers/of/Makefile | 1 +
drivers/of/of_empty_root.c | 51 ++++++++++++++++++++++++++++++++++++++
3 files changed, 55 insertions(+)
create mode 100644 drivers/of/of_empty_root.c
--
2.27.0
^ permalink raw reply
* [PATCH V1 Create empty OF root 1/1] of: create empty of root
From: Lizhi Hou @ 2022-01-26 5:48 UTC (permalink / raw)
To: devicetree, robh
Cc: Lizhi Hou, linux-kernel, yilun.xu, maxz, sonal.santan, yliu,
michal.simek, stefanos, trix, mdf, dwmw2, Max Zhen
In-Reply-To: <20220126054807.492651-1-lizhi.hou@xilinx.com>
Add OF_EMPTY_ROOT config. When it is selected and there is not a device
tree, create an empty device tree root node.
Signed-off-by: Sonal Santan <sonal.santan@xilinx.com>
Signed-off-by: Max Zhen <max.zhen@xilinx.com>
Signed-off-by: Lizhi Hou <lizhi.hou@xilinx.com>
---
drivers/of/Kconfig | 3 +++
drivers/of/Makefile | 1 +
drivers/of/of_empty_root.c | 51 ++++++++++++++++++++++++++++++++++++++
3 files changed, 55 insertions(+)
create mode 100644 drivers/of/of_empty_root.c
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index 80b5fd44ab1c..42afb126f91a 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -94,4 +94,7 @@ config OF_DMA_DEFAULT_COHERENT
# arches should select this if DMA is coherent by default for OF devices
bool
+config OF_EMPTY_ROOT
+ bool
+
endif # OF
diff --git a/drivers/of/Makefile b/drivers/of/Makefile
index e0360a44306e..c65364f32935 100644
--- a/drivers/of/Makefile
+++ b/drivers/of/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o
obj-$(CONFIG_OF_RESOLVE) += resolver.o
obj-$(CONFIG_OF_OVERLAY) += overlay.o
obj-$(CONFIG_OF_NUMA) += of_numa.o
+obj-$(CONFIG_OF_EMPTY_ROOT) += of_empty_root.o
ifdef CONFIG_KEXEC_FILE
ifdef CONFIG_OF_FLATTREE
diff --git a/drivers/of/of_empty_root.c b/drivers/of/of_empty_root.c
new file mode 100644
index 000000000000..5c429c7a27bd
--- /dev/null
+++ b/drivers/of/of_empty_root.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Xilinx, Inc.
+ */
+
+#include <linux/of.h>
+#include <linux/slab.h>
+
+#include "of_private.h"
+
+static int __init of_root_init(void)
+{
+ struct property *prop = NULL;
+ struct device_node *node;
+ __be32 *val = NULL;
+
+ if (of_root)
+ return 0;
+
+ pr_info("Create empty OF root node\n");
+ node = kzalloc(sizeof(*node), GFP_KERNEL);
+ if (!node)
+ return -ENOMEM;
+ of_node_init(node);
+ node->full_name = "/";
+
+ prop = kcalloc(2, sizeof(*prop), GFP_KERNEL);
+ if (!prop)
+ return -ENOMEM;
+
+ val = kzalloc(sizeof(*val), GFP_KERNEL);
+ if (!val)
+ return -ENOMEM;
+ *val = cpu_to_be32(sizeof(void *) / sizeof(u32));
+
+ prop->name = "#address-cells";
+ prop->value = val;
+ prop->length = sizeof(u32);
+ of_add_property(node, prop);
+ prop++;
+ prop->name = "#size-cells";
+ prop->value = val;
+ prop->length = sizeof(u32);
+ of_add_property(node, prop);
+ of_root = node;
+ for_each_of_allnodes(node)
+ __of_attach_node_sysfs(node);
+
+ return 0;
+}
+pure_initcall(of_root_init);
--
2.27.0
^ permalink raw reply related
* [PATCH v5 08/10] bindings: spmi: spmi-pmic-arb: mark interrupt properties as optional
From: Fenglin Wu @ 2022-01-26 6:31 UTC (permalink / raw)
To: linux-arm-msm, linux-kernel, sboyd, Andy Gross, Bjorn Andersson,
Rob Herring, devicetree
Cc: collinsd, subbaram, quic_fenglinw, tglx, maz
In-Reply-To: <1643178713-17178-1-git-send-email-quic_fenglinw@quicinc.com>
From: David Collins <collinsd@codeaurora.org>
Mark all interrupt related properties as optional instead of
required. Some boards do not required PMIC IRQ support and it
isn't needed to handle SPMI bus transactions, so specify it as
optional.
Signed-off-by: David Collins <collinsd@codeaurora.org>
Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com>
---
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
index ca645e2..6332507 100644
--- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
+++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
@@ -29,6 +29,8 @@ Required properties:
- #size-cells : must be set to 0
- qcom,ee : indicates the active Execution Environment identifier (0-5)
- qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5)
+
+Optional properties:
- interrupts : interrupt list for the PMIC Arb controller, must contain a
single interrupt entry for the peripheral interrupt
- interrupt-names : corresponding interrupt names for the interrupts
--
2.7.4
^ permalink raw reply related
* Re: (EXT) [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
From: Alexander Stein @ 2022-01-26 6:42 UTC (permalink / raw)
To: Adam Ford
Cc: linux-media, aford, cphealy, Adam Ford, Ezequiel Garcia,
Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Greg Kroah-Hartman, Lucas Stach, linux-rockchip,
devicetree, linux-arm-kernel, linux-kernel, linux-staging
In-Reply-To: <20220125171129.472775-2-aford173@gmail.com>
Am Dienstag, 25. Januar 2022, 18:11:18 CET schrieb Adam Ford:
> The vpu is enabled by default, so there is no need to manually
> enable it.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi index
> 8aedcddfeab8..38ffcd145b33 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> @@ -272,10 +272,6 @@ &usdhc1 {
> status = "okay";
> };
>
> -&vpu {
> - status = "okay";
> -};
> -
> /* Attention: wdog reset forcing POR needs baseboard support */
> &wdog1 {
> status = "okay";
^ permalink raw reply
* Re: (EXT) [PATCH V4 09/11] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm
From: Alexander Stein @ 2022-01-26 6:45 UTC (permalink / raw)
To: Adam Ford
Cc: linux-media, aford, cphealy, Adam Ford, Ezequiel Garcia,
Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Greg Kroah-Hartman, Lucas Stach, linux-rockchip,
devicetree, linux-arm-kernel, linux-kernel, linux-staging
In-Reply-To: <20220125171129.472775-10-aford173@gmail.com>
Am Dienstag, 25. Januar 2022, 18:11:26 CET schrieb Adam Ford:
> The i.MX8M mini appears to have a similar G1 decoder but the
> post-processing isn't present, so different compatible flag is required.
> Since all the other parameters are the same with imx8mq, just add
> the new compatible flag to nxp,imx8mq-vpu.yaml.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
>
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml index
> 9c28d562112b..7dc13a4b1805 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> @@ -5,7 +5,7 @@
> $id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#"
> $schema: "http://devicetree.org/meta-schemas/core.yaml#"
>
> -title: Hantro G1/G2 VPU codecs implemented on i.MX8MQ SoCs
> +title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs
>
> maintainers:
> - Philipp Zabel <p.zabel@pengutronix.de>
> @@ -20,6 +20,7 @@ properties:
> deprecated: true
> - const: nxp,imx8mq-vpu-g1
> - const: nxp,imx8mq-vpu-g2
> + - const: nxp,imx8mm-vpu-g1
>
> reg:
> maxItems: 1
Is there no rule that items are sorted alphabetically?
Regards,
Alexander
^ permalink raw reply
* RE: [PATCH v5 00/16] Add support for Tesla Full Self-Driving (FSD) SoC
From: Alim Akhtar @ 2022-01-26 6:50 UTC (permalink / raw)
To: 'Krzysztof Kozlowski', linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, s.nawrocki, linux-samsung-soc,
pankaj.dubey, sboyd
In-Reply-To: <4cfcde38-50cb-646a-0d17-c2cb2977a2e4@canonical.com>
Hi Krzysztof
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@canonical.com]
>Sent: Tuesday, January 25, 2022 10:56 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org
>Cc: soc@kernel.org; linux-clk@vger.kernel.org; devicetree@vger.kernel.org;
>olof@lixom.net; arnd@arndb.de; linus.walleij@linaro.org;
>catalin.marinas@arm.com; robh+dt@kernel.org; s.nawrocki@samsung.com;
>linux-samsung-soc@vger.kernel.org; pankaj.dubey@samsung.com;
>sboyd@kernel.org
>Subject: Re: [PATCH v5 00/16] Add support for Tesla Full Self-Driving (FSD) SoC
>
>On 25/01/2022 18:12, Krzysztof Kozlowski wrote:
>> On 24/01/2022 15:16, Alim Akhtar wrote:
>>> Adds basic support for the Tesla Full Self-Driving (FSD) SoC. This
>>> SoC contains three clusters of four Cortex-A72 CPUs, as well as
>>> several IPs.
>>>
>>> Patches 1 to 9 provide support for the clock controller (which is
>>> designed similarly to Exynos SoCs).
>>>
>>> The remaining changes provide pinmux support, initial device tree support.
>>>
>>> - Changes since v4
>>> * fixed 'make dtbs_check' warnings on patch 14/16
>>>
>>> - Changes since v3
>>> * Addressed Stefen's review comments on patch 14/16
>>> * Fixed kernel test robot warning on patch 04/16
>>> * rebsaed this series on Krzysztof's pinmux new binding schema work
>>> [1]
>>>
>>> - Changes since v2
>>> * Addressed Krzysztof's and Stephen's review comments
>>> * Added Reviewed-by and Acked-by tags
>>> * Rebased on next-20220120
>>>
>>> - Changes since v1
>>> * fixed make dt_binding_check error as pointed by Rob
>>> * Addressed Krzysztof's and Rob's review comments
>>> * Added Reviewed-by and Acked-by tags
>>> * Dropped SPI, MCT and ADC from this series (to be posted in small
>>> sets)
>>>
>>> NOTE: These patches are based on Krzysztof's pinmux for-next branch
>>> commit 832ae134ccc1 ("pinctrl: samsung: add support for Exynos850 and
>>> ExynosAutov9 wake-ups") [1]
>>> https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git/l
>>> og/?h=for-next
>>>
>>>
>>
>> Thanks, applied DTS/soc and pinctrl patches.
>>
>> I expect Sylwester will pick up the clock ones. Otherwise please let
>> me know to pick it up as well.
>
>I forgot that clock macros are used in DTS. This does not compile and I cannot
>take drivers into DTS branch.
>
>Alim,
>DTS changes dropped. Please resend with the same trick we did for
>Exynos850 board - hard-coded clock IDs as defines. See:
>
>https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git/diff/arch/arm6
>4/boot/dts/exynos/exynos850.dtsi?h=samsung-dt64-5.17-
>2&id=e3493220fd3e474abcdcefbe14fb60485097ce06
>
Ok, I will resend patch 14 and 15 (DTS changes) only as suggested above.
>
>Best regards,
>Krzysztof
^ permalink raw reply
* RE: [PATCH v5 00/16] Add support for Tesla Full Self-Driving (FSD) SoC
From: Alim Akhtar @ 2022-01-26 6:52 UTC (permalink / raw)
To: 'Krzysztof Kozlowski', linux-arm-kernel, linux-kernel
Cc: soc, linux-clk, devicetree, olof, arnd, linus.walleij,
catalin.marinas, robh+dt, s.nawrocki, linux-samsung-soc,
pankaj.dubey, sboyd
In-Reply-To: <d9682f16-13b7-b6dc-5afd-b2d319143de5@canonical.com>
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@canonical.com]
>Sent: Tuesday, January 25, 2022 10:42 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; linux-arm-
>kernel@lists.infradead.org; linux-kernel@vger.kernel.org
>Cc: soc@kernel.org; linux-clk@vger.kernel.org; devicetree@vger.kernel.org;
>olof@lixom.net; arnd@arndb.de; linus.walleij@linaro.org;
>catalin.marinas@arm.com; robh+dt@kernel.org; s.nawrocki@samsung.com;
>linux-samsung-soc@vger.kernel.org; pankaj.dubey@samsung.com;
>sboyd@kernel.org
>Subject: Re: [PATCH v5 00/16] Add support for Tesla Full Self-Driving (FSD) SoC
>
>On 24/01/2022 15:16, Alim Akhtar wrote:
>> Adds basic support for the Tesla Full Self-Driving (FSD) SoC. This SoC
>> contains three clusters of four Cortex-A72 CPUs, as well as several
>> IPs.
>>
>> Patches 1 to 9 provide support for the clock controller (which is
>> designed similarly to Exynos SoCs).
>>
>> The remaining changes provide pinmux support, initial device tree support.
>>
>> - Changes since v4
>> * fixed 'make dtbs_check' warnings on patch 14/16
>>
>> - Changes since v3
>> * Addressed Stefen's review comments on patch 14/16
>> * Fixed kernel test robot warning on patch 04/16
>> * rebsaed this series on Krzysztof's pinmux new binding schema work
>> [1]
>>
>> - Changes since v2
>> * Addressed Krzysztof's and Stephen's review comments
>> * Added Reviewed-by and Acked-by tags
>> * Rebased on next-20220120
>>
>> - Changes since v1
>> * fixed make dt_binding_check error as pointed by Rob
>> * Addressed Krzysztof's and Rob's review comments
>> * Added Reviewed-by and Acked-by tags
>> * Dropped SPI, MCT and ADC from this series (to be posted in small
>> sets)
>>
>> NOTE: These patches are based on Krzysztof's pinmux for-next branch
>> commit 832ae134ccc1 ("pinctrl: samsung: add support for Exynos850 and
>> ExynosAutov9 wake-ups") [1]
>> https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git/lo
>> g/?h=for-next
>>
>>
>
>Thanks, applied DTS/soc and pinctrl patches.
>
Thanks Krzysztof
>I expect Sylwester will pick up the clock ones. Otherwise please let me know
>to pick it up as well.
>
Hi Sylwester, hope you will be taking clock changes, or let Krzysztof know otherwise.
Thanks
>
>Best regards,
>Krzysztof
^ permalink raw reply
* Re: [PATCH 01/12] arm64: dts: exynos: add USB DWC3 supplies to Espresso board
From: Alim Akhtar @ 2022-01-26 6:58 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Greg Kroah-Hartman, Rob Herring, linux-usb, devicetree,
linux-arm-kernel, linux-samsung-soc, open list
In-Reply-To: <20220123111644.25540-2-krzysztof.kozlowski@canonical.com>
Hi Krzysztof
On Mon, Jan 24, 2022 at 1:34 PM Krzysztof Kozlowski
<krzysztof.kozlowski@canonical.com> wrote:
>
> Add required voltage regulators for USB DWC3 block on Exynos7 Espresso
> board. Due to lack of schematics of Espresso board, the choice of
> regulators is approximate. What bindings call VDD10, for Exynos7 should
> be actually called VDD09 (0.9 V). Use regulators with a matching
> voltage range based on vendor sources for Meizu Pro 5 M576 handset (also
> with Exynos7420).
>
I checked Espresso board schematic, it is 0.9V for the USB and supplied by LDO4
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 5 +++++
> arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> index 125c03f351d9..4c45e689d34a 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> @@ -412,6 +412,11 @@ &ufs {
> status = "okay";
> };
>
> +&usbdrd {
> + vdd10-supply = <&ldo4_reg>;
> + vdd33-supply = <&ldo6_reg>;
> +};
> +
> &usbdrd_phy {
> vbus-supply = <&usb30_vbus_reg>;
> vbus-boost-supply = <&usb3drd_boost_5v>;
> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index c3efbc8add38..01b4210d8b62 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -672,7 +672,7 @@ usbdrd_phy: phy@15500000 {
> #phy-cells = <1>;
> };
>
> - usbdrd3 {
> + usbdrd: usb {
> compatible = "samsung,exynos7-dwusb3";
> clocks = <&clock_fsys0 ACLK_USBDRD300>,
> <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
> --
> 2.32.0
>
--
Regards,
Alim
^ permalink raw reply
* [PATCH REBASED 1/2] dt-bindings: nvmem: extract NVMEM cell to separated file
From: Rafał Miłecki @ 2022-01-26 7:07 UTC (permalink / raw)
To: Rob Herring, Srinivas Kandagatla, Michael Walle
Cc: linux-mtd, devicetree, linux-kernel, linux-arm-kernel, netdev,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra, Shawn Guo,
Li Yang, Frank Rowand, David S . Miller, Jakub Kicinski,
Ansuel Smith, Andrew Lunn, Florian Fainelli, Hauke Mehrtens,
Rafał Miłecki
In-Reply-To: <20220125180114.12286-1-zajec5@gmail.com>
From: Rafał Miłecki <rafal@milecki.pl>
This will allow adding binding for more specific cells and reusing
(sharing) common code.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
.../devicetree/bindings/nvmem/cells/cell.yaml | 34 +++++++++++++++++++
.../devicetree/bindings/nvmem/nvmem.yaml | 22 +-----------
2 files changed, 35 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/nvmem/cells/cell.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/cells/cell.yaml b/Documentation/devicetree/bindings/nvmem/cells/cell.yaml
new file mode 100644
index 000000000000..adfc2e639f43
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/cells/cell.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/cells/cell.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVMEM cell
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: NVMEM cell is a data entry of NVMEM device.
+
+properties:
+ reg:
+ maxItems: 1
+ description:
+ Offset and size in bytes within the storage device.
+
+ bits:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - minimum: 0
+ maximum: 7
+ description:
+ Offset in bit within the address range specified by reg.
+ - minimum: 1
+ description:
+ Size in bit within the address range specified by reg.
+
+required:
+ - reg
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/nvmem/nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
index 43ed7e32e5ac..b79b51e98ee8 100644
--- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml
+++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
@@ -41,27 +41,7 @@ properties:
patternProperties:
"@[0-9a-f]+(,[0-7])?$":
- type: object
-
- properties:
- reg:
- maxItems: 1
- description:
- Offset and size in bytes within the storage device.
-
- bits:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- items:
- - minimum: 0
- maximum: 7
- description:
- Offset in bit within the address range specified by reg.
- - minimum: 1
- description:
- Size in bit within the address range specified by reg.
-
- required:
- - reg
+ $ref: cells/cell.yaml#
additionalProperties: true
--
2.31.1
^ permalink raw reply related
* [PATCH REBASED 2/2] dt-bindings: nvmem: cells: add MAC address cell
From: Rafał Miłecki @ 2022-01-26 7:07 UTC (permalink / raw)
To: Rob Herring, Srinivas Kandagatla, Michael Walle
Cc: linux-mtd, devicetree, linux-kernel, linux-arm-kernel, netdev,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra, Shawn Guo,
Li Yang, Frank Rowand, David S . Miller, Jakub Kicinski,
Ansuel Smith, Andrew Lunn, Florian Fainelli, Hauke Mehrtens,
Rafał Miłecki
In-Reply-To: <20220126070745.32305-1-zajec5@gmail.com>
From: Rafał Miłecki <rafal@milecki.pl>
This adds support for describing details of NVMEM cell containing MAC
address. Those are often device specific and could be nicely stored in
DT.
Initial documentation includes support for describing:
1. Cell data format (e.g. Broadcom's NVRAM uses ASCII to store MAC)
2. Reversed bytes flash (required for i.MX6/i.MX7 OCOTP support)
3. Source for multiple addresses (very common in home routers)
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
.../bindings/nvmem/cells/mac-address.yaml | 94 +++++++++++++++++++
1 file changed, 94 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/cells/mac-address.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/cells/mac-address.yaml b/Documentation/devicetree/bindings/nvmem/cells/mac-address.yaml
new file mode 100644
index 000000000000..f8d19e87cdf0
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/cells/mac-address.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/cells/mac-address.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVMEM cell containing a MAC address
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
+properties:
+ compatible:
+ const: mac-address
+
+ format:
+ description: |
+ Some NVMEM cells contain MAC in a non-binary format.
+
+ ASCII should be specified if MAC is string formatted like:
+ - "01:23:45:67:89:AB" (30 31 3a 32 33 3a 34 35 3a 36 37 3a 38 39 3a 41 42)
+ - "01-23-45-67-89-AB"
+ - "0123456789AB"
+ enum:
+ - ascii
+
+ reversed-bytes:
+ type: boolean
+ description: |
+ MAC is stored in reversed bytes order. Example:
+ Stored value: AB 89 67 45 23 01
+ Actual MAC: 01 23 45 67 89 AB
+
+ base-address:
+ type: boolean
+ description: |
+ Marks NVMEM cell as provider of multiple addresses that are relative to
+ the one actually stored physically. Respective addresses can be requested
+ by specifying cell index of NVMEM cell.
+
+allOf:
+ - $ref: cell.yaml#
+ - if:
+ required:
+ - base-address
+ then:
+ properties:
+ "#nvmem-cell-cells":
+ const: 1
+ required:
+ - "#nvmem-cell-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@f00000 {
+ compatible = "nvmem-cells";
+ label = "calibration";
+ reg = <0xf00000 0x100000>;
+ ranges = <0 0xf00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mac@100 {
+ compatible = "mac-address";
+ reg = <0x100 0x6>;
+ };
+
+ mac@200 {
+ compatible = "mac-address";
+ reg = <0x200 0x6>;
+ reversed-bytes;
+ };
+
+ mac@300 {
+ compatible = "mac-address";
+ reg = <0x300 0x11>;
+ format = "ascii";
+ };
+
+ mac@400 {
+ compatible = "mac-address";
+ reg = <0x400 0x6>;
+ base-address;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
--
2.31.1
^ permalink raw reply related
* Re: [PATCH 1/3] arm64: dts: meson-gx: add ATF BL32 reserved-memory region
From: Christian Hewitt @ 2022-01-26 7:12 UTC (permalink / raw)
To: Vyacheslav
Cc: Rob Herring, Mark Rutland, Kevin Hilman, Neil Armstrong,
devicetree, linux-arm-kernel, linux-amlogic, linux-kernel
In-Reply-To: <a279c365-0615-1c7f-5596-dec9ad1c8229@lexina.in>
> On 26 Jan 2022, at 9:35 am, Vyacheslav <adeep@lexina.in> wrote:
>
> Hi!
>
> 26.01.2022 07:49, Christian Hewitt wrote:
>> Add an additional reserved memory region for the BL32 trusted firmware
>> present in many devices that boot from Amlogic vendor u-boot.
>> Suggested-by: Mateusz Krzak <kszaquitto@gmail.com>
>> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 6 ++++++
>> 1 file changed, 6 insertions(+)
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
>> index 6b457b2c30a4..aa14ea017a61 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
>> @@ -49,6 +49,12 @@
>> no-map;
>> };
>> + /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
>> + secmon_reserved_bl32: secmon@5300000 {
>> + reg = <0x0 0x05300000 0x0 0x2000000>;
>> + no-map;
>> + };
>> +
> How do I check if we need a similar patch for axg boards?
Are they booting using Amlogic (vendor) u-boot sources that
include bl32.img in the FIP signing recipe?
If booting from upstream u-boot, like JetHome boards, it’s
nothing to worry about.
Christian
^ permalink raw reply
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