* [PATCH 1/4] dts: rockchip: Add chasis-type for Powkiddy rk3566 devices
From: Chris Morgan @ 2024-03-25 17:51 UTC (permalink / raw)
To: linux-rockchip
Cc: devicetree, heiko, conor+dt, krzysztof.kozlowski+dt, robh,
Chris Morgan
In-Reply-To: <20240325175133.19393-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Add the optional node of chasis-type for Powkiddy RK3566 based
devices.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi | 2 ++
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi
index 3ab751a01cb2..bd332714a023 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi
@@ -10,6 +10,8 @@
#include "rk3566.dtsi"
/ {
+ chassis-type = "handset";
+
aliases {
mmc1 = &sdmmc0;
mmc2 = &sdmmc1;
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts
index 4786b19fd017..5a648db41f35 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts
@@ -11,6 +11,7 @@
/ {
model = "Powkiddy x55";
+ chassis-type = "handset";
compatible = "powkiddy,x55", "rockchip,rk3566";
aliases {
--
2.34.1
^ permalink raw reply related
* [PATCH 2/4] arm64: dts: rockchip: Update sdmmc node for wifi on powkiddy rk3566
From: Chris Morgan @ 2024-03-25 17:51 UTC (permalink / raw)
To: linux-rockchip
Cc: devicetree, heiko, conor+dt, krzysztof.kozlowski+dt, robh,
Chris Morgan
In-Reply-To: <20240325175133.19393-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Update the sdmmc nodes responsible for WiFi on the Powkiddy RK3566
based devices. For the RGB30, RK2023, and X55 we also add the
sd-uhs-sdr50 parameter. For the RGB10Max3 this parameter is not
supported by the WiFi card.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts | 4 ++++
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts | 4 ++++
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi | 2 ++
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts | 3 +++
4 files changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
index 1f567a14ac84..f0f5ee595938 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
@@ -55,3 +55,7 @@ regulator-state-mem {
};
};
};
+
+&sdmmc2 {
+ sd-uhs-sdr50;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts
index bc9933d9e262..661abceaba9c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts
@@ -54,3 +54,7 @@ regulator-state-mem {
};
};
};
+
+&sdmmc2 {
+ sd-uhs-sdr50;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi
index bd332714a023..10089921c62d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi
@@ -771,6 +771,8 @@ &sdmmc2 {
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
+ no-mmc;
+ no-sd;
non-removable;
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts
index 5a648db41f35..ccdf654a3f48 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts
@@ -835,9 +835,12 @@ &sdmmc1 {
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
+ no-mmc;
+ no-sd;
non-removable;
pinctrl-0 = <&sdmmc1_bus4>, <&sdmmc1_cmd>, <&sdmmc1_clk>;
pinctrl-names = "default";
+ sd-uhs-sdr50;
vmmc-supply = <&vcc_wifi>;
status = "okay";
};
--
2.34.1
^ permalink raw reply related
* [PATCH 0/4] User Requested Fixes for Powkiddy RK3566 Devices
From: Chris Morgan @ 2024-03-25 17:51 UTC (permalink / raw)
To: linux-rockchip
Cc: devicetree, heiko, conor+dt, krzysztof.kozlowski+dt, robh,
Chris Morgan
From: Chris Morgan <macromorgan@hotmail.com>
Users have requested fixes for Powkiddy devices to help with some
intermittent WiFi issues by adding additional properties to the
SDMMC2 node. They have also requested that the model name be
represented consistently with both the manufacturer name and model
name. Lastly, there exists a second configuration of the RGB30 with
a slightly different regulator layout we need to describe.
I have added the new/additional property of "chasis-type" as well.
Chris Morgan (4):
dts: rockchip: Add chasis-type for Powkiddy rk3566 devices
arm64: dts: rockchip: Update sdmmc node for wifi on powkiddy rk3566
arm64: dts: rockchip: Correct model name for Powkiddy RK3566 Devices
arm64: dts: rockchip: Describe Alternate Regulator Config on RGB30
.../dts/rockchip/rk3566-powkiddy-rgb30.dts | 30 ++++++++++++++++++-
.../dts/rockchip/rk3566-powkiddy-rk2023.dts | 6 +++-
.../dts/rockchip/rk3566-powkiddy-rk2023.dtsi | 4 +++
.../boot/dts/rockchip/rk3566-powkiddy-x55.dts | 4 +++
4 files changed, 42 insertions(+), 2 deletions(-)
--
2.34.1
^ permalink raw reply
* [PATCH 3/4] arm64: dts: rockchip: Correct model name for Powkiddy RK3566 Devices
From: Chris Morgan @ 2024-03-25 17:51 UTC (permalink / raw)
To: linux-rockchip
Cc: devicetree, heiko, conor+dt, krzysztof.kozlowski+dt, robh,
Chris Morgan
In-Reply-To: <20240325175133.19393-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Some Powkiddy model names begin with the company "Powkiddy" and others
simply list the model number. Make this consistent across the device
lineup by including the manufacturer in the model name.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts | 2 +-
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
index f0f5ee595938..e359465eebe9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
@@ -8,7 +8,7 @@
#include "rk3566-powkiddy-rk2023.dtsi"
/ {
- model = "RGB30";
+ model = "Powkiddy RGB30";
compatible = "powkiddy,rgb30", "rockchip,rk3566";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts
index 661abceaba9c..b83116c56584 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts
@@ -8,7 +8,7 @@
#include "rk3566-powkiddy-rk2023.dtsi"
/ {
- model = "RK2023";
+ model = "Powkiddy RK2023";
compatible = "powkiddy,rk2023", "rockchip,rk3566";
};
--
2.34.1
^ permalink raw reply related
* [PATCH 4/4] arm64: dts: rockchip: Describe Alternate Regulator Config on RGB30
From: Chris Morgan @ 2024-03-25 17:51 UTC (permalink / raw)
To: linux-rockchip
Cc: devicetree, heiko, conor+dt, krzysztof.kozlowski+dt, robh,
Chris Morgan
In-Reply-To: <20240325175133.19393-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Describe a possible secondary regulator configuration for the RGB30.
At some point Powkiddy altered the CPU regulator for the RGB30 without
creating a new model revision. Note this in the device-tree in the
hopes that it may alleviate a user's confusion (or possibly allow a
bootloader to manipulate the tree to swap out the regulators when the
alternate configuration is detected).
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
.../dts/rockchip/rk3566-powkiddy-rgb30.dts | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
index e359465eebe9..484f097e9f11 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
@@ -54,6 +54,30 @@ regulator-state-mem {
regulator-off-in-suspend;
};
};
+
+ /*
+ * Some RGB30 devices use a different CPU regulator. These
+ * devices have no external markings to denote a different
+ * model revision.
+ */
+ vdd_cpu_alt: regulator@40 {
+ compatible = "tcs,tcs4525";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-name = "vdd_cpu_alt";
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sys>;
+
+ status = "disabled";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
};
&sdmmc2 {
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 0/4] User Requested Fixes for Powkiddy RK3566 Devices
From: Dragan Simic @ 2024-03-25 17:57 UTC (permalink / raw)
To: Chris Morgan
Cc: linux-rockchip, devicetree, heiko, conor+dt,
krzysztof.kozlowski+dt, robh, Chris Morgan
In-Reply-To: <20240325175133.19393-1-macroalpha82@gmail.com>
Hello Chris,
On 2024-03-25 18:51, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Users have requested fixes for Powkiddy devices to help with some
> intermittent WiFi issues by adding additional properties to the
> SDMMC2 node. They have also requested that the model name be
> represented consistently with both the manufacturer name and model
> name. Lastly, there exists a second configuration of the RGB30 with
> a slightly different regulator layout we need to describe.
>
> I have added the new/additional property of "chasis-type" as well.
Shouldn't this series be labeled as v2?
By the way, regarding renaming the mmcX aliases, maybe that would
actually be doable, but only if you have full control over software
that runs on these devices.
> Chris Morgan (4):
> dts: rockchip: Add chasis-type for Powkiddy rk3566 devices
> arm64: dts: rockchip: Update sdmmc node for wifi on powkiddy rk3566
> arm64: dts: rockchip: Correct model name for Powkiddy RK3566 Devices
> arm64: dts: rockchip: Describe Alternate Regulator Config on RGB30
>
> .../dts/rockchip/rk3566-powkiddy-rgb30.dts | 30 ++++++++++++++++++-
> .../dts/rockchip/rk3566-powkiddy-rk2023.dts | 6 +++-
> .../dts/rockchip/rk3566-powkiddy-rk2023.dtsi | 4 +++
> .../boot/dts/rockchip/rk3566-powkiddy-x55.dts | 4 +++
> 4 files changed, 42 insertions(+), 2 deletions(-)
^ permalink raw reply
* Re: [RESEND PATCH] dt-bindings: display: sony,td4353-jdi: allow width-mm and height-mm
From: Krzysztof Kozlowski @ 2024-03-25 17:57 UTC (permalink / raw)
To: Rob Herring
Cc: Konrad Dybcio, Krzysztof Kozlowski, Neil Armstrong, dri-devel,
linux-kernel, Daniel Vetter, Maarten Lankhorst, devicetree,
Thomas Zimmermann, Jessica Zhang, Sam Ravnborg, David Airlie,
Maxime Ripard, Conor Dooley, Conor Dooley
In-Reply-To: <171137719526.3318300.16563684034350324718.robh@kernel.org>
On 25/03/2024 15:33, Rob Herring wrote:
> On Mon, 25 Mar 2024 11:32:27 +0100, Krzysztof Kozlowski wrote:
>> Allow width and height properties from panel-common.yaml, already used
>> on some boards:
>>
>> sdm845-sony-xperia-tama-apollo.dtb: panel@0: 'height-mm', 'width-mm' do not match any of the regexes: 'pinctrl-[0-9]+'
>>
>> Acked-by: Conor Dooley <conor.dooley@microchip.com>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>>
>> Rob, could you pick up this one? Was on the list for almost a year.
>>
>>
>> .../devicetree/bindings/display/panel/sony,td4353-jdi.yaml | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>
> Applied, thanks!
Few hours earlier Neil Armstrong took it, so I think you can drop it.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v4 0/4] Add support for QoS configuration
From: Odelu Kukatla @ 2024-03-25 18:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Georgi Djakov, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Kees Cook, cros-qcom-dts-watchers, Gustavo A . R . Silva,
linux-arm-msm, linux-pm, devicetree, linux-kernel,
linux-hardening, quic_rlaggysh, quic_mdtipton
This series adds QoS support for QNOC type device which can be found on
SC7280 platform. It adds support for programming priority,
priority forward disable and urgency forwarding. This helps in
priortizing the traffic originating from different interconnect masters
at NOC(Network On Chip).
Changes in v4:
- Addressed comments related to spacing and line wrapping.
- Changed the print level from warn to info for regmap related errors.
- Use of GENMASK instead of BIT_MASK for bit mask creation.
Odelu Kukatla (4):
interconnect: qcom: icc-rpmh: Add QoS configuration support
interconnect: qcom: sc7280: enable QoS programming
dt-bindings: interconnect: add clock property to enable QOS on SC7280
arm64: dts: qcom: sc7280: Add clocks for QOS configuration
.../interconnect/qcom,sc7280-rpmh.yaml | 14 +
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +
drivers/interconnect/qcom/icc-rpmh.c | 99 ++++++
drivers/interconnect/qcom/icc-rpmh.h | 34 ++
drivers/interconnect/qcom/sc7280.c | 332 ++++++++++++++++++
5 files changed, 482 insertions(+)
--
2.17.1
^ permalink raw reply
* [PATCH v4 1/4] interconnect: qcom: icc-rpmh: Add QoS configuration support
From: Odelu Kukatla @ 2024-03-25 18:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Georgi Djakov, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Kees Cook, cros-qcom-dts-watchers, Gustavo A . R . Silva,
linux-arm-msm, linux-pm, devicetree, linux-kernel,
linux-hardening, quic_rlaggysh, quic_mdtipton
In-Reply-To: <20240325181628.9407-1-quic_okukatla@quicinc.com>
It adds QoS support for QNOC device and includes support for
configuring priority, priority forward disable, urgency forwarding.
This helps in priortizing the traffic originating from different
interconnect masters at NoC(Network On Chip).
Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
---
drivers/interconnect/qcom/icc-rpmh.c | 99 ++++++++++++++++++++++++++++
drivers/interconnect/qcom/icc-rpmh.h | 34 ++++++++++
2 files changed, 133 insertions(+)
diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
index c1aa265c1f4e..bc85701ee027 100644
--- a/drivers/interconnect/qcom/icc-rpmh.c
+++ b/drivers/interconnect/qcom/icc-rpmh.c
@@ -1,8 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
+#include <linux/bitfield.h>
+#include <linux/clk.h>
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
#include <linux/module.h>
@@ -14,6 +17,38 @@
#include "icc-common.h"
#include "icc-rpmh.h"
+/* QNOC QoS */
+#define QOSGEN_MAINCTL_LO(p, qp) (0x8 + (p->port_offsets[qp]))
+#define QOS_SLV_URG_MSG_EN_MASK GENMASK(3, 3)
+#define QOS_DFLT_PRIO_MASK GENMASK(6, 4)
+#define QOS_DISABLE_MASK GENMASK(24, 24)
+
+/**
+ * qcom_icc_set_qos - initialize static QoS configurations
+ * @qp: qcom icc provider to which @node belongs
+ * @node: qcom icc node to operate on
+ */
+static void qcom_icc_set_qos(struct qcom_icc_provider *qp,
+ struct qcom_icc_node *node)
+{
+ const struct qcom_icc_qosbox *qos = node->qosbox;
+ int port;
+
+ for (port = 0; port < qos->num_ports; port++) {
+ regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
+ QOS_DISABLE_MASK,
+ FIELD_PREP(QOS_DISABLE_MASK, qos->prio_fwd_disable));
+
+ regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
+ QOS_DFLT_PRIO_MASK,
+ FIELD_PREP(QOS_DFLT_PRIO_MASK, qos->prio));
+
+ regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
+ QOS_SLV_URG_MSG_EN_MASK,
+ FIELD_PREP(QOS_SLV_URG_MSG_EN_MASK, qos->urg_fwd));
+ }
+}
+
/**
* qcom_icc_pre_aggregate - cleans up stale values from prior icc_set
* @node: icc node to operate on
@@ -159,6 +194,36 @@ int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev)
}
EXPORT_SYMBOL_GPL(qcom_icc_bcm_init);
+/**
+ * qcom_icc_rpmh_configure_qos - configure QoS parameters
+ * @qp: qcom icc provider associated with QoS endpoint nodes
+ *
+ * Return: 0 on success, or an error code otherwise
+ */
+static int qcom_icc_rpmh_configure_qos(struct qcom_icc_provider *qp)
+{
+ struct qcom_icc_node *qnode;
+ size_t i;
+ int ret;
+
+ ret = clk_bulk_prepare_enable(qp->num_clks, qp->clks);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < qp->num_nodes; i++) {
+ qnode = qp->nodes[i];
+ if (!qnode)
+ continue;
+
+ if (qnode->qosbox)
+ qcom_icc_set_qos(qp, qnode);
+ }
+
+ clk_bulk_disable_unprepare(qp->num_clks, qp->clks);
+
+ return ret;
+}
+
int qcom_icc_rpmh_probe(struct platform_device *pdev)
{
const struct qcom_icc_desc *desc;
@@ -199,7 +264,9 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
qp->dev = dev;
qp->bcms = desc->bcms;
+ qp->nodes = desc->nodes;
qp->num_bcms = desc->num_bcms;
+ qp->num_nodes = desc->num_nodes;
qp->voter = of_bcm_voter_get(qp->dev, NULL);
if (IS_ERR(qp->voter))
@@ -229,6 +296,38 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
data->nodes[i] = node;
}
+ if (desc->config) {
+ struct resource *res;
+ void __iomem *base;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ goto skip_qos_config;
+
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base)) {
+ dev_info(dev, "Skipping QoS, ioremap failed: %ld\n", PTR_ERR(base));
+ goto skip_qos_config;
+ };
+
+ qp->regmap = devm_regmap_init_mmio(dev, base, desc->config);
+ if (IS_ERR(qp->regmap)) {
+ dev_info(dev, "Skipping QoS, regmap failed; %ld\n", PTR_ERR(qp->regmap));
+ goto skip_qos_config;
+ }
+
+ qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks);
+ if (qp->num_clks < 0) {
+ dev_info(dev, "Skipping QoS, failed to get clk: %d\n", qp->num_clks);
+ goto skip_qos_config;
+ }
+
+ ret = qcom_icc_rpmh_configure_qos(qp);
+ if (ret)
+ dev_info(dev, "Failed to program QoS: %d\n", ret);
+ }
+
+skip_qos_config:
ret = icc_provider_register(provider);
if (ret)
goto err_remove_nodes;
diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
index 2de29460e808..4fdc75c84c95 100644
--- a/drivers/interconnect/qcom/icc-rpmh.h
+++ b/drivers/interconnect/qcom/icc-rpmh.h
@@ -1,12 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
#define __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <linux/regmap.h>
#define to_qcom_provider(_provider) \
container_of(_provider, struct qcom_icc_provider, provider)
@@ -18,6 +20,11 @@
* @bcms: list of bcms that maps to the provider
* @num_bcms: number of @bcms
* @voter: bcm voter targeted by this provider
+ * @nodes: list of icc nodes that maps to the provider
+ * @num_nodes: number of @nodes
+ * @regmap: used for QoS, register access
+ * @clks : clks required for register access
+ * @num_clks: number of @clks
*/
struct qcom_icc_provider {
struct icc_provider provider;
@@ -25,6 +32,11 @@ struct qcom_icc_provider {
struct qcom_icc_bcm * const *bcms;
size_t num_bcms;
struct bcm_voter *voter;
+ struct qcom_icc_node * const *nodes;
+ size_t num_nodes;
+ struct regmap *regmap;
+ struct clk_bulk_data *clks;
+ int num_clks;
};
/**
@@ -41,6 +53,25 @@ struct bcm_db {
u8 reserved;
};
+/**
+ * struct qcom_icc_qosbox - Qualcomm specific QoS config
+ * @prio: priority value assigned to requests on the node
+ * @urg_fwd: whether to forward the urgency promotion issued by master
+ * (endpoint), or discard
+ * @prio_fwd_disable: whether to forward the priority driven by master, or
+ * override by @prio
+ * @num_ports: number of @ports
+ * @port_offsets: qos register offsets
+ */
+
+struct qcom_icc_qosbox {
+ const u32 prio;
+ const bool urg_fwd;
+ const bool prio_fwd_disable;
+ const u32 num_ports;
+ const u32 port_offsets[] __counted_by(num_ports);
+};
+
#define MAX_LINKS 128
#define MAX_BCMS 64
#define MAX_BCM_PER_NODE 3
@@ -58,6 +89,7 @@ struct bcm_db {
* @max_peak: current max aggregate value of all peak bw requests
* @bcms: list of bcms associated with this logical node
* @num_bcms: num of @bcms
+ * @qosbox: qos config data associated with node
*/
struct qcom_icc_node {
const char *name;
@@ -70,6 +102,7 @@ struct qcom_icc_node {
u64 max_peak[QCOM_ICC_NUM_BUCKETS];
struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE];
size_t num_bcms;
+ const struct qcom_icc_qosbox *qosbox;
};
/**
@@ -114,6 +147,7 @@ struct qcom_icc_fabric {
};
struct qcom_icc_desc {
+ const struct regmap_config *config;
struct qcom_icc_node * const *nodes;
size_t num_nodes;
struct qcom_icc_bcm * const *bcms;
--
2.17.1
^ permalink raw reply related
* [PATCH v4 2/4] interconnect: qcom: sc7280: enable QoS programming
From: Odelu Kukatla @ 2024-03-25 18:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Georgi Djakov, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Kees Cook, cros-qcom-dts-watchers, Gustavo A . R . Silva,
linux-arm-msm, linux-pm, devicetree, linux-kernel,
linux-hardening, quic_rlaggysh, quic_mdtipton
In-Reply-To: <20240325181628.9407-1-quic_okukatla@quicinc.com>
Enable QoS for the master ports with predefined values
for priority and urgency.
Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
---
drivers/interconnect/qcom/sc7280.c | 332 +++++++++++++++++++++++++++++
1 file changed, 332 insertions(+)
diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c
index 7d33694368e8..1e1002c4d3d8 100644
--- a/drivers/interconnect/qcom/sc7280.c
+++ b/drivers/interconnect/qcom/sc7280.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
*/
@@ -16,29 +17,53 @@
#include "icc-rpmh.h"
#include "sc7280.h"
+static const struct qcom_icc_qosbox qhm_qspi_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x7000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
.id = SC7280_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
+ .qosbox = &qhm_qspi_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
+static const struct qcom_icc_qosbox qhm_qup0_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x11000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
.id = SC7280_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
+ .qosbox = &qhm_qup0_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
+static const struct qcom_icc_qosbox qhm_qup1_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x8000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
.id = SC7280_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
+ .qosbox = &qhm_qup1_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
@@ -52,38 +77,70 @@ static struct qcom_icc_node qnm_a1noc_cfg = {
.links = { SC7280_SLAVE_SERVICE_A1NOC },
};
+static const struct qcom_icc_qosbox xm_sdc1_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xc000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
.id = SC7280_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_sdc1_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
+static const struct qcom_icc_qosbox xm_sdc2_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xe000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
.id = SC7280_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_sdc2_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
+static const struct qcom_icc_qosbox xm_sdc4_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x9000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
.id = SC7280_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_sdc4_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
+static const struct qcom_icc_qosbox xm_ufs_mem_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xa000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
.id = SC7280_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_ufs_mem_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
@@ -97,20 +154,36 @@ static struct qcom_icc_node xm_usb2 = {
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
+static const struct qcom_icc_qosbox xm_usb3_0_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xb000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
.id = SC7280_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_usb3_0_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
+static const struct qcom_icc_qosbox qhm_qdss_bam_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x18000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.id = SC7280_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
+ .qosbox = &qhm_qdss_bam_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A2NOC_SNOC },
};
@@ -124,29 +197,53 @@ static struct qcom_icc_node qnm_a2noc_cfg = {
.links = { SC7280_SLAVE_SERVICE_A2NOC },
};
+static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x1c000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
.id = SC7280_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qnm_cnoc_datapath_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A2NOC_SNOC },
};
+static const struct qcom_icc_qosbox qxm_crypto_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x1d000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
.id = SC7280_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qxm_crypto_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A2NOC_SNOC },
};
+static const struct qcom_icc_qosbox qxm_ipa_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x10000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
.id = SC7280_MASTER_IPA,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qxm_ipa_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A2NOC_SNOC },
};
@@ -168,11 +265,19 @@ static struct qcom_icc_node xm_pcie3_1 = {
.links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
};
+static const struct qcom_icc_qosbox xm_qdss_etr_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x15000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
.id = SC7280_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_qdss_etr_qos,
.num_links = 1,
.links = { SC7280_SLAVE_A2NOC_SNOC },
};
@@ -300,20 +405,36 @@ static struct qcom_icc_node qnm_cnoc_dc_noc = {
.links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG },
};
+static const struct qcom_icc_qosbox alm_gpu_tcu_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xd7000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
.id = SC7280_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
+ .qosbox = &alm_gpu_tcu_qos,
.num_links = 2,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
+static const struct qcom_icc_qosbox alm_sys_tcu_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xd6000 },
+ .prio = 6,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
.id = SC7280_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
+ .qosbox = &alm_sys_tcu_qos,
.num_links = 2,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
@@ -328,11 +449,19 @@ static struct qcom_icc_node chm_apps = {
SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
};
+static const struct qcom_icc_qosbox qnm_cmpnoc_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x21000, 0x61000 },
+ .prio = 0,
+ .urg_fwd = 1,
+};
+
static struct qcom_icc_node qnm_cmpnoc = {
.name = "qnm_cmpnoc",
.id = SC7280_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_cmpnoc_qos,
.num_links = 2,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
@@ -348,29 +477,53 @@ static struct qcom_icc_node qnm_gemnoc_cfg = {
SC7280_SLAVE_SERVICE_GEM_NOC },
};
+static const struct qcom_icc_qosbox qnm_gpu_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x22000, 0x62000 },
+ .prio = 0,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
.id = SC7280_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_gpu_qos,
.num_links = 2,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
+static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x23000, 0x63000 },
+ .prio = 0,
+ .urg_fwd = 1,
+};
+
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
.id = SC7280_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_mnoc_hf_qos,
.num_links = 1,
.links = { SC7280_SLAVE_LLCC },
};
+static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xcf000 },
+ .prio = 0,
+ .urg_fwd = 1,
+};
+
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
.id = SC7280_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
+ .qosbox = &qnm_mnoc_sf_qos,
.num_links = 2,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
@@ -384,20 +537,36 @@ static struct qcom_icc_node qnm_pcie = {
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
+static const struct qcom_icc_qosbox qnm_snoc_gc_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xd3000 },
+ .prio = 0,
+ .urg_fwd = 1,
+};
+
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.id = SC7280_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qnm_snoc_gc_qos,
.num_links = 1,
.links = { SC7280_SLAVE_LLCC },
};
+static const struct qcom_icc_qosbox qnm_snoc_sf_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xd4000 },
+ .prio = 0,
+ .urg_fwd = 1,
+};
+
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
.id = SC7280_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
+ .qosbox = &qnm_snoc_sf_qos,
.num_links = 3,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
@@ -432,56 +601,104 @@ static struct qcom_icc_node qnm_mnoc_cfg = {
.links = { SC7280_SLAVE_SERVICE_MNOC },
};
+static const struct qcom_icc_qosbox qnm_video0_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x14000 },
+ .prio = 0,
+ .urg_fwd = 1,
+};
+
static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
.id = SC7280_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
+ .qosbox = &qnm_video0_qos,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
};
+static const struct qcom_icc_qosbox qnm_video_cpu_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x15000 },
+ .prio = 0,
+ .urg_fwd = 1,
+};
+
static struct qcom_icc_node qnm_video_cpu = {
.name = "qnm_video_cpu",
.id = SC7280_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qnm_video_cpu_qos,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
};
+static const struct qcom_icc_qosbox qxm_camnoc_hf_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x10000, 0x10180 },
+ .prio = 0,
+ .urg_fwd = 1,
+};
+
static struct qcom_icc_node qxm_camnoc_hf = {
.name = "qxm_camnoc_hf",
.id = SC7280_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qxm_camnoc_hf_qos,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
};
+static const struct qcom_icc_qosbox qxm_camnoc_icp_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x11000 },
+ .prio = 0,
+ .urg_fwd = 1,
+};
+
static struct qcom_icc_node qxm_camnoc_icp = {
.name = "qxm_camnoc_icp",
.id = SC7280_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qxm_camnoc_icp_qos,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
};
+static const struct qcom_icc_qosbox qxm_camnoc_sf_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x12000 },
+ .prio = 0,
+ .urg_fwd = 1,
+};
+
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
.id = SC7280_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
+ .qosbox = &qxm_camnoc_sf_qos,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
};
+static const struct qcom_icc_qosbox qxm_mdp0_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x16000 },
+ .prio = 0,
+ .urg_fwd = 1,
+};
+
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
.id = SC7280_MASTER_MDP0,
.channels = 1,
.buswidth = 32,
+ .qosbox = &qxm_mdp0_qos,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
};
@@ -531,20 +748,36 @@ static struct qcom_icc_node qnm_snoc_cfg = {
.links = { SC7280_SLAVE_SERVICE_SNOC },
};
+static const struct qcom_icc_qosbox qxm_pimem_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x8000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
.id = SC7280_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qxm_pimem_qos,
.num_links = 1,
.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
};
+static const struct qcom_icc_qosbox xm_gic_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xa000 },
+ .prio = 2,
+ .urg_fwd = 0,
+};
+
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
.id = SC7280_MASTER_GIC,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_gic_qos,
.num_links = 1,
.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
};
@@ -1502,7 +1735,16 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
};
+static const struct regmap_config sc7280_aggre1_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1c080,
+ .fast_io = true,
+};
+
static const struct qcom_icc_desc sc7280_aggre1_noc = {
+ .config = &sc7280_aggre1_noc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1513,6 +1755,14 @@ static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
&bcm_ce0,
};
+static const struct regmap_config sc7280_aggre2_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x2b080,
+ .fast_io = true,
+};
+
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
@@ -1525,6 +1775,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sc7280_aggre2_noc = {
+ .config = &sc7280_aggre2_noc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1605,7 +1856,16 @@ static struct qcom_icc_node * const cnoc2_nodes[] = {
[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
};
+static const struct regmap_config sc7280_cnoc2_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1000,
+ .fast_io = true,
+};
+
static const struct qcom_icc_desc sc7280_cnoc2 = {
+ .config = &sc7280_cnoc2_regmap_config,
.nodes = cnoc2_nodes,
.num_nodes = ARRAY_SIZE(cnoc2_nodes),
.bcms = cnoc2_bcms,
@@ -1637,7 +1897,16 @@ static struct qcom_icc_node * const cnoc3_nodes[] = {
[SLAVE_TCU] = &xs_sys_tcu_cfg,
};
+static const struct regmap_config sc7280_cnoc3_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1000,
+ .fast_io = true,
+};
+
static const struct qcom_icc_desc sc7280_cnoc3 = {
+ .config = &sc7280_cnoc3_regmap_config,
.nodes = cnoc3_nodes,
.num_nodes = ARRAY_SIZE(cnoc3_nodes),
.bcms = cnoc3_bcms,
@@ -1653,7 +1922,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
};
+static const struct regmap_config sc7280_dc_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x5080,
+ .fast_io = true,
+};
+
static const struct qcom_icc_desc sc7280_dc_noc = {
+ .config = &sc7280_dc_noc_regmap_config,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -1689,7 +1967,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
};
+static const struct regmap_config sc7280_gem_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xe2200,
+ .fast_io = true,
+};
+
static const struct qcom_icc_desc sc7280_gem_noc = {
+ .config = &sc7280_gem_noc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1709,7 +1996,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
};
+static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xf080,
+ .fast_io = true,
+};
+
static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
+ .config = &sc7280_lpass_ag_noc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1726,7 +2022,16 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
[SLAVE_EBI1] = &ebi,
};
+static const struct regmap_config sc7280_mc_virt_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x4,
+ .fast_io = true,
+};
+
static const struct qcom_icc_desc sc7280_mc_virt = {
+ .config = &sc7280_mc_virt_regmap_config,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1753,7 +2058,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
};
+static const struct regmap_config sc7280_mmss_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1e080,
+ .fast_io = true,
+};
+
static const struct qcom_icc_desc sc7280_mmss_noc = {
+ .config = &sc7280_mmss_noc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1772,7 +2086,16 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
};
+static const struct regmap_config sc7280_nsp_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x10000,
+ .fast_io = true,
+};
+
static const struct qcom_icc_desc sc7280_nsp_noc = {
+ .config = &sc7280_nsp_noc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1797,7 +2120,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
};
+static const struct regmap_config sc7280_system_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x15480,
+ .fast_io = true,
+};
+
static const struct qcom_icc_desc sc7280_system_noc = {
+ .config = &sc7280_system_noc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
--
2.17.1
^ permalink raw reply related
* [PATCH v4 3/4] dt-bindings: interconnect: add clock property to enable QOS on SC7280
From: Odelu Kukatla @ 2024-03-25 18:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Georgi Djakov, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Kees Cook, cros-qcom-dts-watchers, Gustavo A . R . Silva,
linux-arm-msm, linux-pm, devicetree, linux-kernel,
linux-hardening, quic_rlaggysh, quic_mdtipton
In-Reply-To: <20240325181628.9407-1-quic_okukatla@quicinc.com>
Added clock property to enable clocks required for accessing
qos registers.
Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
---
.../bindings/interconnect/qcom,sc7280-rpmh.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
index b135597d9489..950ecdd5252e 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
@@ -35,6 +35,10 @@ properties:
reg:
maxItems: 1
+ clocks:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
@@ -57,6 +61,7 @@ unevaluatedProperties: false
examples:
- |
+ #include <dt-bindings/clock/qcom,gcc-sc7280.h>
interconnect {
compatible = "qcom,sc7280-clk-virt";
#interconnect-cells = <2>;
@@ -69,3 +74,12 @@ examples:
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
+
+ interconnect@16e0000 {
+ reg = <0x016e0000 0x1c080>;
+ compatible = "qcom,sc7280-aggre1-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+ };
--
2.17.1
^ permalink raw reply related
* [PATCH v4 4/4] arm64: dts: qcom: sc7280: Add clocks for QOS configuration
From: Odelu Kukatla @ 2024-03-25 18:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Georgi Djakov, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Kees Cook, cros-qcom-dts-watchers, Gustavo A . R . Silva,
linux-arm-msm, linux-pm, devicetree, linux-kernel,
linux-hardening, quic_rlaggysh, quic_mdtipton
In-Reply-To: <20240325181628.9407-1-quic_okukatla@quicinc.com>
Add handles for required clocks to be enabled for configuring
QoS on sc7280.
Signed-off-by: Odelu Kukatla <quic_okukatla@quicinc.com>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 41f51d326111..981f66a88967 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2129,6 +2129,8 @@
reg = <0 0x016e0000 0 0x1c080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
aggre2_noc: interconnect@1700000 {
@@ -2136,6 +2138,7 @@
compatible = "qcom,sc7280-aggre2-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
};
mmss_noc: interconnect@1740000 {
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v6 1/4] dt-bindings: media: add Maxim MAX96717 GMSL2 Serializer
From: Conor Dooley @ 2024-03-25 18:17 UTC (permalink / raw)
To: Julien Massot
Cc: linux-media, devicetree, kernel, linux-kernel, mchehab, robh+dt,
krzysztof.kozlowski+dt, conor+dt, sakari.ailus
In-Reply-To: <20240325131634.165361-2-julien.massot@collabora.com>
[-- Attachment #1: Type: text/plain, Size: 409 bytes --]
On Mon, Mar 25, 2024 at 02:16:31PM +0100, Julien Massot wrote:
> Add DT bindings for Maxim MAX96717 GMSL2 Serializer.
>
> Signed-off-by: Julien Massot <julien.massot@collabora.com>
> ---
> Change since v5:
> - Reverse the fallback MAX96717 can fallback to MAX96717F
> - Use const instead of enum for MAX96717F compatible
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* [PATCH] ASoC: dt-bindings: wm8974: Convert to dtschema
From: Kartik Agarwala @ 2024-03-25 18:19 UTC (permalink / raw)
To: lgirdwood, broonie, robh, krzysztof.kozlowski+dt, conor+dt
Cc: Kartik Agarwala, patches, linux-sound, devicetree, linux-kernel,
javier.carrasco.cruz
Convert WM8974 audio CODEC bindings from text to dtschema.
Signed-off-by: Kartik Agarwala <agarwala.kartik@gmail.com>
---
.../devicetree/bindings/sound/wlf,wm8974.txt | 15 -------
.../devicetree/bindings/sound/wlf,wm8974.yaml | 41 +++++++++++++++++++
2 files changed, 41 insertions(+), 15 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/wlf,wm8974.txt
create mode 100644 Documentation/devicetree/bindings/sound/wlf,wm8974.yaml
diff --git a/Documentation/devicetree/bindings/sound/wlf,wm8974.txt b/Documentation/devicetree/bindings/sound/wlf,wm8974.txt
deleted file mode 100644
index 01d3a7c83..000000000
--- a/Documentation/devicetree/bindings/sound/wlf,wm8974.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-WM8974 audio CODEC
-
-This device supports both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
- - compatible: "wlf,wm8974"
- - reg: the I2C address or SPI chip select number of the device
-
-Examples:
-
-codec: wm8974@1a {
- compatible = "wlf,wm8974";
- reg = <0x1a>;
-};
diff --git a/Documentation/devicetree/bindings/sound/wlf,wm8974.yaml b/Documentation/devicetree/bindings/sound/wlf,wm8974.yaml
new file mode 100644
index 000000000..d27300207
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wlf,wm8974.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/wlf,wm8974.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: WM8974 audio CODEC
+
+maintainers:
+ - patches@opensource.cirrus.com
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: wlf,wm8974
+
+ reg:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec@1a {
+ compatible = "wlf,wm8974";
+ reg = <0x1a>;
+ };
+ };
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v6 08/15] dt-bindings: media: Add bindings for bcm2835-unicam
From: Sakari Ailus @ 2024-03-25 18:28 UTC (permalink / raw)
To: Laurent Pinchart
Cc: linux-media, Dave Stevenson, David Plowman, Jean-Michel Hautbois,
Hans Verkuil, Naushir Patuck, kernel-list, linux-rpi-kernel,
Florian Fainelli, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Conor Dooley, Krzysztof Kozlowski,
Rob Herring, devicetree
In-Reply-To: <20240301213231.10340-9-laurent.pinchart@ideasonboard.com>
Hi Laurent,
Thanks for the set.
On Fri, Mar 01, 2024 at 11:32:23PM +0200, Laurent Pinchart wrote:
> From: Dave Stevenson <dave.stevenson@raspberrypi.com>
>
> Introduce the dt-bindings documentation for bcm2835 CCP2/CSI2 Unicam
> camera interface.
>
> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> Co-developed-by: Naushir Patuck <naush@raspberrypi.com>
> Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
> Co-developed-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> Changes since v5:
>
> - Squash MAINTAINERS changes in
>
> Changes since v3:
>
> - Make MAINTAINERS its own patch
> - Describe the reg and clocks correctly
> - Use a vendor entry for the number of data lanes
> ---
> .../bindings/media/brcm,bcm2835-unicam.yaml | 117 ++++++++++++++++++
> MAINTAINERS | 6 +
> 2 files changed, 123 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml b/Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
> new file mode 100644
> index 000000000000..1938ace23b3d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
> @@ -0,0 +1,117 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/brcm,bcm2835-unicam.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Broadcom BCM283x Camera Interface (Unicam)
> +
> +maintainers:
> + - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
> +
> +description: |-
> + The Unicam block on BCM283x SoCs is the receiver for either
> + CSI-2 or CCP2 data from image sensors or similar devices.
> +
> + The main platform using this SoC is the Raspberry Pi family of boards. On
> + the Pi the VideoCore firmware can also control this hardware block, and
> + driving it from two different processors will cause issues. To avoid this,
> + the firmware checks the device tree configuration during boot. If it finds
> + device tree nodes whose name starts with 'csi' then it will stop the firmware
> + accessing the block, and it can then safely be used via the device tree
> + binding.
> +
> +properties:
> + compatible:
> + const: brcm,bcm2835-unicam
> +
> + reg:
> + items:
> + - description: Unicam block.
> + - description: Clock Manager Image (CMI) block.
> +
> + reg-names:
> + items:
> + - const: unicam
> + - const: cmi
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Clock to drive the LP state machine of Unicam.
> + - description: Clock for the VPU (core clock).
> +
> + clock-names:
> + items:
> + - const: lp
> + - const: vpu
> +
> + power-domains:
> + items:
> + - description: Unicam power domain
> +
> + brcm,num-data-lanes:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [ 2, 4 ]
> + description: |
> + Number of CSI-2 data lanes supported by this Unicam instance. The number
> + of data lanes actively used is specified with the data-lanes endpoint
> + property.
> +
> + port:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> +
> + properties:
> + endpoint:
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes: true
> +
> + required:
> + - data-lanes
As the device supports multiple data interfaces (at least so it seems when
looking at the driver code), you need to list the bus-type property here,
too.
> +
> + required:
> + - endpoint
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - clocks
> + - clock-names
> + - power-domains
> + - brcm,num-data-lanes
> + - port
> +
> +additionalProperties: False
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/bcm2835.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/raspberrypi-power.h>
> + csi1: csi@7e801000 {
> + compatible = "brcm,bcm2835-unicam";
> + reg = <0x7e801000 0x800>,
> + <0x7e802004 0x4>;
> + reg-names = "unicam", "cmi";
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clocks BCM2835_CLOCK_CAM1>,
> + <&firmware_clocks 4>;
> + clock-names = "lp", "vpu";
> + power-domains = <&power RPI_POWER_DOMAIN_UNICAM1>;
> + brcm,num-data-lanes = <2>;
> + port {
> + csi1_ep: endpoint {
> + remote-endpoint = <&imx219_0>;
> + data-lanes = <1 2>;
> + };
> + };
> + };
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fada59148cb5..e50a59654e6e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3997,6 +3997,12 @@ N: bcm113*
> N: bcm216*
> N: kona
>
> +BROADCOM BCM2835 CAMERA DRIVERS
> +M: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
> +L: linux-media@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
> +
> BROADCOM BCM47XX MIPS ARCHITECTURE
> M: Hauke Mehrtens <hauke@hauke-m.de>
> M: Rafał Miłecki <zajec5@gmail.com>
--
Regards,
Sakari Ailus
^ permalink raw reply
* Re: [PATCH v5 1/2] dt-bindings: hwmon: Add NCT7363Y documentation
From: Krzysztof Kozlowski @ 2024-03-25 18:29 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, baneric926
Cc: linux-hwmon, krzysztof.kozlowski+dt, robh+dt, conor+dt, corbet,
jdelvare, kwliu, kcfeng0, Paul Menzel, linux-kernel, devicetree,
Bonnie_Lo, linux-doc, DELPHINE_CHIU, openbmc
In-Reply-To: <22fcad13-dd9b-4e9a-90aa-d20fb78e6a0d@roeck-us.net>
On 25/03/2024 18:09, Guenter Roeck wrote:
> On 3/22/24 02:26, Rob Herring wrote:
>>
>> On Fri, 22 Mar 2024 16:11:57 +0800, baneric926@gmail.com wrote:
>>> From: Ban Feng <kcfeng0@nuvoton.com>
>>>
>>> Add bindings for the Nuvoton NCT7363Y Fan Controller
>>>
>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
>>> Signed-off-by: Ban Feng <kcfeng0@nuvoton.com>
>>> ---
>>> .../bindings/hwmon/nuvoton,nct7363.yaml | 66 +++++++++++++++++++
>>> MAINTAINERS | 6 ++
>>> 2 files changed, 72 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.yaml
>>>
>>
>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>
>> yamllint warnings/errors:
>>
>> dtschema/dtc warnings/errors:
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.yaml:
>> Error in referenced schema matching $id: http://devicetree.org/schemas/hwmon/fan-common.yaml
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.example.dtb: hwmon@22: fan-0: False schema does not allow {'pwms': [[1, 0, 50000]], 'tach-ch': ['']}
>> from schema $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7363.yaml#
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.example.dtb: hwmon@22: fan-0: Unevaluated properties are not allowed ('pwms', 'tach-ch' were unexpected)
>> from schema $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7363.yaml#
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.example.dtb: hwmon@22: fan-1: False schema does not allow {'pwms': [[1, 1, 50000]], 'tach-ch': b'\x01'}
>> from schema $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7363.yaml#
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.example.dtb: hwmon@22: fan-1: Unevaluated properties are not allowed ('pwms', 'tach-ch' were unexpected)
>> from schema $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7363.yaml#
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.example.dtb: fan-1: tach-ch: b'\x01' is not of type 'object', 'array', 'boolean', 'null'
>> from schema $id: http://devicetree.org/schemas/dt-core.yaml#
>>
>> doc reference errors (make refcheckdocs):
>>
>> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240322081158.4106326-2-kcfeng0@nuvoton.com
>>
>> The base for the series is generally the latest rc1. A different dependency
>> should be noted in *this* patch.
>>
>> If you already ran 'make dt_binding_check' and didn't see the above
>> error(s), then make sure 'yamllint' is installed and dt-schema is up to
>> date:
>>
>> pip3 install dtschema --upgrade
>>
>> Please check and re-submit after running the above command yourself. Note
>> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
>> your schema. However, it must be unset to test all examples with your schema.
>>
>
> I am a bit puzzled by this one. The patch has a Reviewed-by: tag from Rob,
> but then Rob's bot complains about errors. hat am I missing ?
The warning is a result of missing fan-common.yaml in the tree used as a
base.
I checked now and I don't see warnings on next or v6.9-rc1, so it is
safe for you to apply it.
For the record:
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH] ARM: dts: stm32: add heartbeat led for stm32mp157c-ed1
From: Krzysztof Kozlowski @ 2024-03-25 18:29 UTC (permalink / raw)
To: patrice.chotard, robh+dt, Krzysztof Kozlowski, alexandre.torgue
Cc: linux-stm32, linux-arm-kernel, linux-kernel, devicetree
In-Reply-To: <20240325170656.2829600-1-patrice.chotard@foss.st.com>
On 25/03/2024 18:06, patrice.chotard@foss.st.com wrote:
> From: Patrice Chotard <patrice.chotard@foss.st.com>
>
> Add heartbeat led for stm32mp157c-ed1.
>
> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
> ---
> arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
> index 66ed5f9921ba..bd727455a7e4 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
> @@ -24,6 +24,15 @@ chosen {
> stdout-path = "serial0:115200n8";
> };
>
> + led {
> + compatible = "gpio-leds";
> + led-blue {
> + gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + default-state = "off";
Please add function and color properties.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 4/7] dt-bindings: iio: accel: adxl345: Add spi-3wire
From: Krzysztof Kozlowski @ 2024-03-25 18:32 UTC (permalink / raw)
To: Lothar Rubusch, lars, Michael.Hennerich, jic23, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: linux-iio, devicetree, linux-kernel, eraretuya
In-Reply-To: <20240325153356.46112-5-l.rubusch@gmail.com>
On 25/03/2024 16:33, Lothar Rubusch wrote:
> Add spi-3wire because the driver optionally supports spi-3wire.
This is a friendly reminder during the review process.
It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.
Thank you.
>
> Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> ---
This is a friendly reminder during the review process.
It looks like you received a tag and forgot to add it.
If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions, under or above your Signed-off-by tag. Tag is "received", when
provided in a message replied to you on the mailing list. Tools like b4
can help here. However, there's no need to repost patches *only* to add
the tags. The upstream maintainer will do that for tags received on the
version they apply.
https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
If a tag was not added on purpose, please state why and what changed.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: add wolfvision vendor prefix
From: Krzysztof Kozlowski @ 2024-03-25 18:32 UTC (permalink / raw)
To: Michael Riesch, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20240325-feature-wolfvision-pf5-v1-1-5725445f792a@wolfvision.net>
On 25/03/2024 15:22, Michael Riesch wrote:
> Add vendor prefix for WolfVision GmbH (https://wolfvision.com).
>
> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 2/4] dt-bindings: arm: rockchip: add wolfvision pf5 mainboard
From: Krzysztof Kozlowski @ 2024-03-25 18:33 UTC (permalink / raw)
To: Michael Riesch, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20240325-feature-wolfvision-pf5-v1-2-5725445f792a@wolfvision.net>
On 25/03/2024 15:22, Michael Riesch wrote:
> Add the WolfVision PF5 mainboard, which serves as base for recent
> WolfVision products. It features the Rockchip RK3568 SoC and can
> be extended with several different extension boards.
>
> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
> ---
> Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
> index fcf7316ecd74..99bd5e2c76a0 100644
> --- a/Documentation/devicetree/bindings/arm/rockchip.yaml
> +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
> @@ -927,6 +927,11 @@ properties:
> - const: turing,rk1
> - const: rockchip,rk3588
>
> + - description: WolfVision PF5 mainboard
> + items:
> + - const: wolfvision,rk3568-pf5
> + - const: rockchip,rk3568
Assuming you keep existing order of entries (whatever it is):
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
This is an automated instruction, just in case, because many review tags
are being ignored. If you know the process, you can skip it (please do
not feel offended by me posting it here - no bad intentions intended).
If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions, under or above your Signed-off-by tag. Tag is "received", when
provided in a message replied to you on the mailing list. Tools like b4
can help here. However, there's no need to repost patches *only* to add
the tags. The upstream maintainer will do that for tags received on the
version they apply.
https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v6 09/15] media: bcm2835-unicam: Add support for CCP2/CSI2 camera interface
From: Sakari Ailus @ 2024-03-25 18:36 UTC (permalink / raw)
To: Laurent Pinchart
Cc: linux-media, Dave Stevenson, David Plowman, Jean-Michel Hautbois,
Hans Verkuil, Naushir Patuck, kernel-list, linux-rpi-kernel,
Florian Fainelli, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Conor Dooley, Krzysztof Kozlowski,
Rob Herring, devicetree
In-Reply-To: <20240301213231.10340-10-laurent.pinchart@ideasonboard.com>
Hi Laurent,
On Fri, Mar 01, 2024 at 11:32:24PM +0200, Laurent Pinchart wrote:
> From: Dave Stevenson <dave.stevenson@raspberrypi.com>
>
> Add a driver for the Unicam camera receiver block on BCM283x processors.
> It is represented as two video device nodes: unicam-image and
> unicam-embedded which are connected to an internal subdev (named
> unicam-subdev) in order to manage streams routing.
>
> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> Co-developed-by: Naushir Patuck <naush@raspberrypi.com>
> Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
> Co-developed-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@ideasonboard.com>
> Co-developed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Thanks for submitting this, it's the cleanest and neatest Unicom driver
I've ever seen!
Some mostly unimportant comments below, however the bus-type issue needs to
be addressed.
> ---
> Changes since v5:
>
> - Move to drivers/media/platform/broadcom/
> - Port to the upstream V4L2 streams API
> - Rebase on latest metadata API proposal
> - Add missing error message
> - Drop unneeded documentation block for unicam_isr()
> - Drop unneeded dev_dbg() and dev_err() messages
> - Drop unneeded streams_mask and fmt checks
> - Drop unused unicam_sd_pad_is_sink()
> - Drop unneeded includes
> - Drop v4l2_ctrl_subscribe_event() call
> - Use pm_runtime_resume_and_get()
> - Indentation and line wrap fixes
> - Let the framework set bus_info
> - Use v4l2_fwnode_endpoint_parse()
> - Fix media device cleanup
> - Drop lane reordering checks
> - Fix subdev state locking
> - Drop extra debug messages
> - Move clock handling to runtime PM handlers
> - Reorder functions
> - Rename init functions for more clarity
> - Initialize runtime PM earlier
> - Clarify error messages
> - Simplify subdev init with local variable
> - Fix subdev cleanup
> - Fix typos and indentation
> - Don't initialize local variables needlessly
> - Simplify num lanes check
> - Fix metadata handling in subdev set_fmt
> - Drop manual fallback to .s_stream()
> - Pass v4l2_pix_format to unicam_calc_format_size_bpl()
> - Simplify unicam_set_default_format()
> - Fix default format settings
> - Add busy check in unicam_s_fmt_meta()
> - Add missing \n at end of format strings
> - Fix metadata handling in subdev set_fmt
> - Fix locking when starting streaming
> - Return buffers from start streaming fails
> - Fix format validation for metadata node
> - Use video_device_pipeline_{start,stop}() helpers
> - Simplify format enumeration
> - Drop unset variable
> - Update MAINTAINERS entry
> - Update to the upstream v4l2_async_nf API
> - Update to the latest subdev routing API
> - Update to the latest subdev state API
> - Move from subdev .init_cfg() to .init_state()
> - Update to the latest videobuf2 API
> - Fix v4l2_subdev_enable_streams() error check
> - Use correct pad for the connected subdev
> - Return buffers to vb2 when start streaming fails
> - Improve debugging in start streaming handler
> - Simplify DMA address management
> - Drop comment about bcm2835-camera driver
> - Clarify comments that explain min/max sizes
> - Pass v4l2_pix_format to unicam_try_fmt()
> - Drop unneeded local variables
> - Rename image-related constants and functions
> - Turn unicam_fmt.metadata_fmt into bool
> - Rename unicam_fmt to unicam_format_info
> - Rename unicam_format_info variables to fmtinfo
> - Rename unicam_node.v_fmt to fmt
> - Add metadata formats for RAW10, RAW12 and RAW14
> - Make metadata formats line-based
> - Validate format on metadata video device
> - Add Co-devlopped-by tags
>
> Changes since v3:
>
> - Add the vendor prefix for DT name
> - Use the reg-names in DT parsing
> - Remove MAINTAINERS entry
>
> Changes since v2:
>
> - Change code organization
> - Remove unused variables
> - Correct the fmt_meta functions
> - Rewrite the start/stop streaming
> - You can now start the image node alone, but not the metadata one
> - The buffers are allocated per-node
> - only the required stream is started, if the route exists and is
> enabled
> - Prefix the macros with UNICAM_ to not have too generic names
> - Drop colorspace support
>
> Changes since v1:
>
> - Replace the unicam_{info,debug,error} macros with dev_*()
> ---
> MAINTAINERS | 1 +
> drivers/media/platform/Kconfig | 1 +
> drivers/media/platform/Makefile | 1 +
> drivers/media/platform/broadcom/Kconfig | 23 +
> drivers/media/platform/broadcom/Makefile | 3 +
> .../platform/broadcom/bcm2835-unicam-regs.h | 255 ++
> .../media/platform/broadcom/bcm2835-unicam.c | 2607 +++++++++++++++++
> 7 files changed, 2891 insertions(+)
> create mode 100644 drivers/media/platform/broadcom/Kconfig
> create mode 100644 drivers/media/platform/broadcom/Makefile
> create mode 100644 drivers/media/platform/broadcom/bcm2835-unicam-regs.h
> create mode 100644 drivers/media/platform/broadcom/bcm2835-unicam.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e50a59654e6e..cc350729f467 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -4002,6 +4002,7 @@ M: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
> L: linux-media@vger.kernel.org
> S: Maintained
> F: Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
> +F: drivers/media/platform/bcm2835/
>
> BROADCOM BCM47XX MIPS ARCHITECTURE
> M: Hauke Mehrtens <hauke@hauke-m.de>
> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> index 91e54215de3a..2d79bfc68c15 100644
> --- a/drivers/media/platform/Kconfig
> +++ b/drivers/media/platform/Kconfig
> @@ -67,6 +67,7 @@ source "drivers/media/platform/amlogic/Kconfig"
> source "drivers/media/platform/amphion/Kconfig"
> source "drivers/media/platform/aspeed/Kconfig"
> source "drivers/media/platform/atmel/Kconfig"
> +source "drivers/media/platform/broadcom/Kconfig"
> source "drivers/media/platform/cadence/Kconfig"
> source "drivers/media/platform/chips-media/Kconfig"
> source "drivers/media/platform/intel/Kconfig"
> diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
> index 3296ec1ebe16..da17301f7439 100644
> --- a/drivers/media/platform/Makefile
> +++ b/drivers/media/platform/Makefile
> @@ -10,6 +10,7 @@ obj-y += amlogic/
> obj-y += amphion/
> obj-y += aspeed/
> obj-y += atmel/
> +obj-y += broadcom/
> obj-y += cadence/
> obj-y += chips-media/
> obj-y += intel/
> diff --git a/drivers/media/platform/broadcom/Kconfig b/drivers/media/platform/broadcom/Kconfig
> new file mode 100644
> index 000000000000..cc2c9afcc948
> --- /dev/null
> +++ b/drivers/media/platform/broadcom/Kconfig
> @@ -0,0 +1,23 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +config VIDEO_BCM2835_UNICAM
> + tristate "Broadcom BCM283x/BCM271x Unicam video capture driver"
> + depends on ARCH_BCM2835 || COMPILE_TEST
> + depends on PM
> + depends on VIDEO_DEV
> + select MEDIA_CONTROLLER
> + select V4L2_FWNODE
> + select VIDEO_V4L2_SUBDEV_API
> + select VIDEOBUF2_DMA_CONTIG
> + help
> + Say Y here to enable support for the BCM283x/BCM271x CSI-2 receiver.
> + This is a V4L2 driver that controls the CSI-2 receiver directly,
> + independently from the VC4 firmware.
> +
> + This driver is mutually exclusive with the use of bcm2835-camera. The
> + firmware will disable all access to the peripheral from within the
> + firmware if it finds a DT node using it, and bcm2835-camera will
> + therefore fail to probe.
> +
> + To compile this driver as a module, choose M here. The module will be
> + called bcm2835-unicam.
> diff --git a/drivers/media/platform/broadcom/Makefile b/drivers/media/platform/broadcom/Makefile
> new file mode 100644
> index 000000000000..03d2045aba2e
> --- /dev/null
> +++ b/drivers/media/platform/broadcom/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o
> diff --git a/drivers/media/platform/broadcom/bcm2835-unicam-regs.h b/drivers/media/platform/broadcom/bcm2835-unicam-regs.h
> new file mode 100644
> index 000000000000..84775fd2fac5
> --- /dev/null
> +++ b/drivers/media/platform/broadcom/bcm2835-unicam-regs.h
> @@ -0,0 +1,255 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +/*
> + * Copyright (C) 2017-2020 Raspberry Pi Trading.
Anything up to 2024?
> + * Dave Stevenson <dave.stevenson@raspberrypi.com>
> + */
> +
> +#ifndef VC4_REGS_UNICAM_H
> +#define VC4_REGS_UNICAM_H
> +
> +#include <linux/bits.h>
> +
> +/*
> + * The following values are taken from files found within the code drop
> + * made by Broadcom for the BCM21553 Graphics Driver, predominantly in
> + * brcm_usrlib/dag/vmcsx/vcinclude/hardware_vc4.h.
> + * They have been modified to be only the register offset.
> + */
> +#define UNICAM_CTRL 0x000
> +#define UNICAM_STA 0x004
> +#define UNICAM_ANA 0x008
> +#define UNICAM_PRI 0x00c
> +#define UNICAM_CLK 0x010
> +#define UNICAM_CLT 0x014
> +#define UNICAM_DAT0 0x018
> +#define UNICAM_DAT1 0x01c
> +#define UNICAM_DAT2 0x020
> +#define UNICAM_DAT3 0x024
> +#define UNICAM_DLT 0x028
> +#define UNICAM_CMP0 0x02c
> +#define UNICAM_CMP1 0x030
> +#define UNICAM_CAP0 0x034
> +#define UNICAM_CAP1 0x038
> +#define UNICAM_ICTL 0x100
> +#define UNICAM_ISTA 0x104
> +#define UNICAM_IDI0 0x108
> +#define UNICAM_IPIPE 0x10c
> +#define UNICAM_IBSA0 0x110
> +#define UNICAM_IBEA0 0x114
> +#define UNICAM_IBLS 0x118
> +#define UNICAM_IBWP 0x11c
> +#define UNICAM_IHWIN 0x120
> +#define UNICAM_IHSTA 0x124
> +#define UNICAM_IVWIN 0x128
> +#define UNICAM_IVSTA 0x12c
> +#define UNICAM_ICC 0x130
> +#define UNICAM_ICS 0x134
> +#define UNICAM_IDC 0x138
> +#define UNICAM_IDPO 0x13c
> +#define UNICAM_IDCA 0x140
> +#define UNICAM_IDCD 0x144
> +#define UNICAM_IDS 0x148
> +#define UNICAM_DCS 0x200
> +#define UNICAM_DBSA0 0x204
> +#define UNICAM_DBEA0 0x208
> +#define UNICAM_DBWP 0x20c
> +#define UNICAM_DBCTL 0x300
> +#define UNICAM_IBSA1 0x304
> +#define UNICAM_IBEA1 0x308
> +#define UNICAM_IDI1 0x30c
> +#define UNICAM_DBSA1 0x310
> +#define UNICAM_DBEA1 0x314
> +#define UNICAM_MISC 0x400
> +
> +/*
> + * The following bitmasks are from the kernel released by Broadcom
> + * for Android - https://android.googlesource.com/kernel/bcm/
> + * The Rhea, Hawaii, and Java chips all contain the same VideoCore4
> + * Unicam block as BCM2835, as defined in eg
> + * arch/arm/mach-rhea/include/mach/rdb_A0/brcm_rdb_cam.h and similar.
> + * Values reworked to use the kernel BIT and GENMASK macros.
> + *
> + * Some of the bit mnenomics have been amended to match the datasheet.
> + */
> +/* UNICAM_CTRL Register */
> +#define UNICAM_CPE BIT(0)
> +#define UNICAM_MEM BIT(1)
> +#define UNICAM_CPR BIT(2)
> +#define UNICAM_CPM_MASK GENMASK(3, 3)
> +#define UNICAM_CPM_CSI2 0
> +#define UNICAM_CPM_CCP2 1
> +#define UNICAM_SOE BIT(4)
> +#define UNICAM_DCM_MASK GENMASK(5, 5)
> +#define UNICAM_DCM_STROBE 0
> +#define UNICAM_DCM_DATA 1
> +#define UNICAM_SLS BIT(6)
> +#define UNICAM_PFT_MASK GENMASK(11, 8)
> +#define UNICAM_OET_MASK GENMASK(20, 12)
> +
> +/* UNICAM_STA Register */
> +#define UNICAM_SYN BIT(0)
> +#define UNICAM_CS BIT(1)
> +#define UNICAM_SBE BIT(2)
> +#define UNICAM_PBE BIT(3)
> +#define UNICAM_HOE BIT(4)
> +#define UNICAM_PLE BIT(5)
> +#define UNICAM_SSC BIT(6)
> +#define UNICAM_CRCE BIT(7)
> +#define UNICAM_OES BIT(8)
> +#define UNICAM_IFO BIT(9)
> +#define UNICAM_OFO BIT(10)
> +#define UNICAM_BFO BIT(11)
> +#define UNICAM_DL BIT(12)
> +#define UNICAM_PS BIT(13)
> +#define UNICAM_IS BIT(14)
> +#define UNICAM_PI0 BIT(15)
> +#define UNICAM_PI1 BIT(16)
> +#define UNICAM_FSI_S BIT(17)
> +#define UNICAM_FEI_S BIT(18)
> +#define UNICAM_LCI_S BIT(19)
> +#define UNICAM_BUF0_RDY BIT(20)
> +#define UNICAM_BUF0_NO BIT(21)
> +#define UNICAM_BUF1_RDY BIT(22)
> +#define UNICAM_BUF1_NO BIT(23)
> +#define UNICAM_DI BIT(24)
> +
> +#define UNICAM_STA_MASK_ALL \
> + (UNICAM_DL | \
> + UNICAM_SBE | \
This and the lines below should start at right of the opening parenthesis,
not at it.
> + UNICAM_PBE | \
> + UNICAM_HOE | \
> + UNICAM_PLE | \
> + UNICAM_SSC | \
> + UNICAM_CRCE | \
> + UNICAM_IFO | \
> + UNICAM_OFO | \
> + UNICAM_PS | \
> + UNICAM_PI0 | \
> + UNICAM_PI1)
> +
> +/* UNICAM_ANA Register */
> +#define UNICAM_APD BIT(0)
> +#define UNICAM_BPD BIT(1)
> +#define UNICAM_AR BIT(2)
> +#define UNICAM_DDL BIT(3)
> +#define UNICAM_CTATADJ_MASK GENMASK(7, 4)
> +#define UNICAM_PTATADJ_MASK GENMASK(11, 8)
> +
> +/* UNICAM_PRI Register */
> +#define UNICAM_PE BIT(0)
> +#define UNICAM_PT_MASK GENMASK(2, 1)
> +#define UNICAM_NP_MASK GENMASK(7, 4)
> +#define UNICAM_PP_MASK GENMASK(11, 8)
> +#define UNICAM_BS_MASK GENMASK(15, 12)
> +#define UNICAM_BL_MASK GENMASK(17, 16)
> +
> +/* UNICAM_CLK Register */
> +#define UNICAM_CLE BIT(0)
> +#define UNICAM_CLPD BIT(1)
> +#define UNICAM_CLLPE BIT(2)
> +#define UNICAM_CLHSE BIT(3)
> +#define UNICAM_CLTRE BIT(4)
> +#define UNICAM_CLAC_MASK GENMASK(8, 5)
> +#define UNICAM_CLSTE BIT(29)
> +
> +/* UNICAM_CLT Register */
> +#define UNICAM_CLT1_MASK GENMASK(7, 0)
> +#define UNICAM_CLT2_MASK GENMASK(15, 8)
> +
> +/* UNICAM_DATn Registers */
> +#define UNICAM_DLE BIT(0)
> +#define UNICAM_DLPD BIT(1)
> +#define UNICAM_DLLPE BIT(2)
> +#define UNICAM_DLHSE BIT(3)
> +#define UNICAM_DLTRE BIT(4)
> +#define UNICAM_DLSM BIT(5)
> +#define UNICAM_DLFO BIT(28)
> +#define UNICAM_DLSTE BIT(29)
> +
> +#define UNICAM_DAT_MASK_ALL (UNICAM_DLSTE | UNICAM_DLFO)
> +
> +/* UNICAM_DLT Register */
> +#define UNICAM_DLT1_MASK GENMASK(7, 0)
> +#define UNICAM_DLT2_MASK GENMASK(15, 8)
> +#define UNICAM_DLT3_MASK GENMASK(23, 16)
> +
> +/* UNICAM_ICTL Register */
> +#define UNICAM_FSIE BIT(0)
> +#define UNICAM_FEIE BIT(1)
> +#define UNICAM_IBOB BIT(2)
> +#define UNICAM_FCM BIT(3)
> +#define UNICAM_TFC BIT(4)
> +#define UNICAM_LIP_MASK GENMASK(6, 5)
> +#define UNICAM_LCIE_MASK GENMASK(28, 16)
> +
> +/* UNICAM_IDI0/1 Register */
> +#define UNICAM_ID0_MASK GENMASK(7, 0)
> +#define UNICAM_ID1_MASK GENMASK(15, 8)
> +#define UNICAM_ID2_MASK GENMASK(23, 16)
> +#define UNICAM_ID3_MASK GENMASK(31, 24)
> +
> +/* UNICAM_ISTA Register */
> +#define UNICAM_FSI BIT(0)
> +#define UNICAM_FEI BIT(1)
> +#define UNICAM_LCI BIT(2)
> +
> +#define UNICAM_ISTA_MASK_ALL (UNICAM_FSI | UNICAM_FEI | UNICAM_LCI)
> +
> +/* UNICAM_IPIPE Register */
> +#define UNICAM_PUM_MASK GENMASK(2, 0)
> +/* Unpacking modes */
> +#define UNICAM_PUM_NONE 0
> +#define UNICAM_PUM_UNPACK6 1
> +#define UNICAM_PUM_UNPACK7 2
> +#define UNICAM_PUM_UNPACK8 3
> +#define UNICAM_PUM_UNPACK10 4
> +#define UNICAM_PUM_UNPACK12 5
> +#define UNICAM_PUM_UNPACK14 6
> +#define UNICAM_PUM_UNPACK16 7
> +#define UNICAM_DDM_MASK GENMASK(6, 3)
> +#define UNICAM_PPM_MASK GENMASK(9, 7)
> +/* Packing modes */
> +#define UNICAM_PPM_NONE 0
> +#define UNICAM_PPM_PACK8 1
> +#define UNICAM_PPM_PACK10 2
> +#define UNICAM_PPM_PACK12 3
> +#define UNICAM_PPM_PACK14 4
> +#define UNICAM_PPM_PACK16 5
> +#define UNICAM_DEM_MASK GENMASK(11, 10)
> +#define UNICAM_DEBL_MASK GENMASK(14, 12)
> +#define UNICAM_ICM_MASK GENMASK(16, 15)
> +#define UNICAM_IDM_MASK GENMASK(17, 17)
> +
> +/* UNICAM_ICC Register */
> +#define UNICAM_ICFL_MASK GENMASK(4, 0)
> +#define UNICAM_ICFH_MASK GENMASK(9, 5)
> +#define UNICAM_ICST_MASK GENMASK(12, 10)
> +#define UNICAM_ICLT_MASK GENMASK(15, 13)
> +#define UNICAM_ICLL_MASK GENMASK(31, 16)
> +
> +/* UNICAM_DCS Register */
> +#define UNICAM_DIE BIT(0)
> +#define UNICAM_DIM BIT(1)
> +#define UNICAM_DBOB BIT(3)
> +#define UNICAM_FDE BIT(4)
> +#define UNICAM_LDP BIT(5)
> +#define UNICAM_EDL_MASK GENMASK(15, 8)
> +
> +/* UNICAM_DBCTL Register */
> +#define UNICAM_DBEN BIT(0)
> +#define UNICAM_BUF0_IE BIT(1)
> +#define UNICAM_BUF1_IE BIT(2)
> +
> +/* UNICAM_CMP[0,1] register */
> +#define UNICAM_PCE BIT(31)
> +#define UNICAM_GI BIT(9)
> +#define UNICAM_CPH BIT(8)
> +#define UNICAM_PCVC_MASK GENMASK(7, 6)
> +#define UNICAM_PCDT_MASK GENMASK(5, 0)
> +
> +/* UNICAM_MISC register */
> +#define UNICAM_FL0 BIT(6)
> +#define UNICAM_FL1 BIT(9)
> +
> +#endif
> diff --git a/drivers/media/platform/broadcom/bcm2835-unicam.c b/drivers/media/platform/broadcom/bcm2835-unicam.c
> new file mode 100644
> index 000000000000..716c89b8a217
> --- /dev/null
> +++ b/drivers/media/platform/broadcom/bcm2835-unicam.c
> @@ -0,0 +1,2607 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * BCM283x / BCM271x Unicam Capture Driver
> + *
> + * Copyright (C) 2017-2020 - Raspberry Pi (Trading) Ltd.
> + *
> + * Dave Stevenson <dave.stevenson@raspberrypi.com>
> + *
> + * Based on TI am437x driver by
> + * Benoit Parrot <bparrot@ti.com>
> + * Lad, Prabhakar <prabhakar.csengg@gmail.com>
> + *
> + * and TI CAL camera interface driver by
> + * Benoit Parrot <bparrot@ti.com>
> + *
> + *
> + * There are two camera drivers in the kernel for BCM283x - this one and
> + * bcm2835-camera (currently in staging).
> + *
> + * This driver directly controls the Unicam peripheral - there is no
> + * involvement with the VideoCore firmware. Unicam receives CSI-2 or CCP2 data
> + * and writes it into SDRAM. The only potential processing options are to
> + * repack Bayer data into an alternate format, and applying windowing. The
> + * repacking does not shift the data, so can repack V4L2_PIX_FMT_Sxxxx10P to
> + * V4L2_PIX_FMT_Sxxxx10, or V4L2_PIX_FMT_Sxxxx12P to V4L2_PIX_FMT_Sxxxx12, but
> + * not generically up to V4L2_PIX_FMT_Sxxxx16. The driver will add both formats
> + * where the relevant formats are defined, and will automatically configure the
> + * repacking as required. Support for windowing may be added later.
> + *
> + * It should be possible to connect this driver to any sensor with a suitable
> + * output interface and V4L2 subdevice driver.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/err.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/slab.h>
> +#include <linux/videodev2.h>
> +
> +#include <media/v4l2-async.h>
> +#include <media/v4l2-common.h>
> +#include <media/v4l2-dev.h>
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-event.h>
> +#include <media/v4l2-ioctl.h>
> +#include <media/v4l2-fwnode.h>
> +#include <media/v4l2-mc.h>
> +#include <media/videobuf2-dma-contig.h>
> +
> +#include "bcm2835-unicam-regs.h"
> +
> +#define UNICAM_MODULE_NAME "unicam"
> +
> +/*
> + * Unicam must request a minimum of 250Mhz from the VPU clock.
> + * Otherwise the input FIFOs overrun and cause image corruption.
> + */
> +#define UNICAM_MIN_VPU_CLOCK_RATE (250 * 1000 * 1000)
> +
> +/* Unicam has an internal DMA alignment constraint of 16 bytes for each line. */
> +#define UNICAM_DMA_BPL_ALIGNMENT 16
> +
> +/*
> + * The image stride is stored in a 16 bit register, and needs to be aligned to
> + * the DMA constraint. As the ISP in the same SoC has a 32 bytes alignment
> + * constraint on its input, set the image stride alignment to 32 bytes here as
> + * well to avoid incompatible configurations.
> + */
> +#define UNICAM_IMAGE_BPL_ALIGNMENT 32
> +#define UNICAM_IMAGE_MAX_BPL ((1 << 16) - UNICAM_IMAGE_BPL_ALIGNMENT)
Bit shifted values should be unsigned.
> +
> +/*
> + * Max width is therefore determined by the max stride divided by the number of
> + * bits per pixel. Take 32bpp as a worst case. No imposed limit on the height,
> + * so adopt a square image for want of anything better.
> + */
> +#define UNICAM_IMAGE_MIN_WIDTH 16
> +#define UNICAM_IMAGE_MIN_HEIGHT 16
> +#define UNICAM_IMAGE_MAX_WIDTH (UNICAM_IMAGE_MAX_BPL / 4)
> +#define UNICAM_IMAGE_MAX_HEIGHT UNICAM_IMAGE_MAX_WIDTH
> +
> +/*
> + * There's no intrinsic limits on the width and height for embedded dat. Use
> + * the same maximum values as for the image, to avoid overflows in the image
> + * size computation.
> + */
> +#define UNICAM_META_MIN_WIDTH 1
> +#define UNICAM_META_MIN_HEIGHT 1
> +#define UNICAM_META_MAX_WIDTH UNICAM_IMAGE_MAX_WIDTH
> +#define UNICAM_META_MAX_HEIGHT UNICAM_IMAGE_MAX_HEIGHT
> +
> +/*
> + * Size of the dummy buffer. Can be any size really, but the DMA
> + * allocation works in units of page sizes.
> + */
> +#define UNICAM_DUMMY_BUF_SIZE PAGE_SIZE
> +
> +#define UNICAM_SD_PAD_SINK 0
> +#define UNICAM_SD_PAD_SOURCE_IMAGE 1
> +#define UNICAM_SD_PAD_SOURCE_METADATA 2
> +#define UNICAM_SD_NUM_PADS (1 + UNICAM_SD_PAD_SOURCE_METADATA)
> +
> +enum unicam_node_type {
> + UNICAM_IMAGE_NODE,
> + UNICAM_METADATA_NODE,
> + UNICAM_MAX_NODES
> +};
> +
> +/*
> + * struct unicam_format_info - Unicam media bus format information
> + * @fourcc: V4L2 pixel format FCC identifier. 0 if n/a.
> + * @unpacked_fourcc: V4L2 pixel format FCC identifier if the data is expanded
> + * out to 16bpp. 0 if n/a.
> + * @code: V4L2 media bus format code.
> + * @depth: Bits per pixel as delivered from the source.
> + * @csi_dt: CSI data type.
> + * @metadata_fmt: This format only applies to the metadata pad.
> + */
> +struct unicam_format_info {
> + u32 fourcc;
> + u32 unpacked_fourcc;
> + u32 code;
> + u8 depth;
> + u8 csi_dt;
> + bool metadata_fmt;
> +};
> +
> +struct unicam_buffer {
> + struct vb2_v4l2_buffer vb;
> + struct list_head list;
> + dma_addr_t dma_addr;
> + unsigned int size;
> +};
> +
> +static inline struct unicam_buffer *to_unicam_buffer(struct vb2_buffer *vb)
> +{
> + return container_of(vb, struct unicam_buffer, vb.vb2_buf);
> +}
> +
> +struct unicam_node {
> + bool registered;
> + bool streaming;
> + unsigned int id;
> +
> + /* Pointer to the current v4l2_buffer */
> + struct unicam_buffer *cur_frm;
> + /* Pointer to the next v4l2_buffer */
> + struct unicam_buffer *next_frm;
> + /* video capture */
> + const struct unicam_format_info *fmtinfo;
> + /* Used to store current pixel format */
> + struct v4l2_format fmt;
> + /* Buffer queue used in video-buf */
> + struct vb2_queue buffer_queue;
> + /* Queue of filled frames */
> + struct list_head dma_queue;
> + /* IRQ lock for DMA queue */
> + spinlock_t dma_queue_lock;
> + /* lock used to access this structure */
> + struct mutex lock;
> + /* Identifies video device for this channel */
> + struct video_device video_dev;
> + /* Pointer to the parent handle */
> + struct unicam_device *dev;
> + struct media_pad pad;
> + /*
> + * Dummy buffer intended to be used by unicam
> + * if we have no other queued buffers to swap to.
> + */
> + struct unicam_buffer dummy_buf;
> + void *dummy_buf_cpu_addr;
> +};
> +
> +struct unicam_device {
> + struct kref kref;
> +
> + /* peripheral base address */
> + void __iomem *base;
> + /* clock gating base address */
> + void __iomem *clk_gate_base;
> + /* lp clock handle */
> + struct clk *clock;
> + /* vpu clock handle */
> + struct clk *vpu_clock;
> + /* V4l2 device */
> + struct v4l2_device v4l2_dev;
> + struct media_device mdev;
> +
> + /* parent device */
> + struct device *dev;
> + /* subdevice async Notifier */
> + struct v4l2_async_notifier notifier;
> + unsigned int sequence;
> +
> + /* Sensor node */
> + struct {
> + struct v4l2_subdev *subdev;
> + struct media_pad *pad;
> + } sensor;
> +
> + /* Internal subdev */
> + struct {
> + struct v4l2_subdev sd;
> + struct media_pad pads[UNICAM_SD_NUM_PADS];
> + bool streaming;
> + } subdev;
> +
> + enum v4l2_mbus_type bus_type;
> + /*
> + * Stores bus.mipi_csi2.flags for CSI2 sensors, or
> + * bus.mipi_csi1.strobe for CCP2.
> + */
> + unsigned int bus_flags;
> + unsigned int max_data_lanes;
> + unsigned int active_data_lanes;
> +
> + struct media_pipeline pipe;
> +
> + struct unicam_node node[UNICAM_MAX_NODES];
> +};
> +
> +static inline struct unicam_device *
> +notifier_to_unicam_device(struct v4l2_async_notifier *notifier)
> +{
> + return container_of(notifier, struct unicam_device, notifier);
> +}
> +
> +static inline struct unicam_device *
> +sd_to_unicam_device(struct v4l2_subdev *sd)
> +{
> + return container_of(sd, struct unicam_device, subdev.sd);
> +}
> +
> +static void unicam_release(struct kref *kref)
> +{
> + struct unicam_device *unicam =
> + container_of(kref, struct unicam_device, kref);
> +
> + if (unicam->mdev.dev)
> + media_device_cleanup(&unicam->mdev);
> +
> + kfree(unicam);
> +}
> +
> +static struct unicam_device *unicam_get(struct unicam_device *unicam)
> +{
> + kref_get(&unicam->kref);
A newline here would be nice.
> + return unicam;
> +}
> +
> +static void unicam_put(struct unicam_device *unicam)
> +{
> + kref_put(&unicam->kref, unicam_release);
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * Misc helper functions
> + */
> +
> +static inline bool unicam_sd_pad_is_source(u32 pad)
> +{
> + /* Camera RX has 1 sink pad, and N source pads */
> + return pad != UNICAM_SD_PAD_SINK;
> +}
> +
> +static inline bool is_metadata_node(struct unicam_node *node)
> +{
> + return node->video_dev.device_caps & V4L2_CAP_META_CAPTURE;
> +}
> +
> +static inline bool is_image_node(struct unicam_node *node)
> +{
> + return node->video_dev.device_caps & V4L2_CAP_VIDEO_CAPTURE;
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * Format data table and helper functions
> + */
> +
> +static const struct v4l2_mbus_framefmt unicam_default_image_format = {
> + .width = 640,
> + .height = 480,
> + .code = MEDIA_BUS_FMT_UYVY8_1X16,
> + .field = V4L2_FIELD_NONE,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .ycbcr_enc = V4L2_YCBCR_ENC_601,
> + .quantization = V4L2_QUANTIZATION_LIM_RANGE,
> + .xfer_func = V4L2_XFER_FUNC_SRGB,
> + .flags = 0,
> +};
> +
> +static const struct v4l2_mbus_framefmt unicam_default_meta_format = {
> + .width = 640,
> + .height = 2,
> + .code = MEDIA_BUS_FMT_META_8,
> + .field = V4L2_FIELD_NONE,
> +};
> +
> +static const struct unicam_format_info unicam_image_formats[] = {
> + /* YUV Formats */
> + {
> + .fourcc = V4L2_PIX_FMT_YUYV,
> + .code = MEDIA_BUS_FMT_YUYV8_1X16,
> + .depth = 16,
> + .csi_dt = 0x1e,
> + }, {
> + .fourcc = V4L2_PIX_FMT_UYVY,
> + .code = MEDIA_BUS_FMT_UYVY8_1X16,
> + .depth = 16,
> + .csi_dt = 0x1e,
> + }, {
> + .fourcc = V4L2_PIX_FMT_YVYU,
> + .code = MEDIA_BUS_FMT_YVYU8_1X16,
> + .depth = 16,
> + .csi_dt = 0x1e,
> + }, {
> + .fourcc = V4L2_PIX_FMT_VYUY,
> + .code = MEDIA_BUS_FMT_VYUY8_1X16,
> + .depth = 16,
> + .csi_dt = 0x1e,
> + }, {
> + /* RGB Formats */
> + .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */
> + .code = MEDIA_BUS_FMT_RGB565_1X16,
> + .depth = 16,
> + .csi_dt = 0x22,
> + }, {
> + .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */
> + .code = MEDIA_BUS_FMT_RGB888_1X24,
> + .depth = 24,
> + .csi_dt = 0x24,
> + }, {
> + .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */
> + .code = MEDIA_BUS_FMT_BGR888_1X24,
> + .depth = 24,
> + .csi_dt = 0x24,
> + }, {
> + /* Bayer Formats */
> + .fourcc = V4L2_PIX_FMT_SBGGR8,
> + .code = MEDIA_BUS_FMT_SBGGR8_1X8,
> + .depth = 8,
> + .csi_dt = 0x2a,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGBRG8,
> + .code = MEDIA_BUS_FMT_SGBRG8_1X8,
> + .depth = 8,
> + .csi_dt = 0x2a,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGRBG8,
> + .code = MEDIA_BUS_FMT_SGRBG8_1X8,
> + .depth = 8,
> + .csi_dt = 0x2a,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SRGGB8,
> + .code = MEDIA_BUS_FMT_SRGGB8_1X8,
> + .depth = 8,
> + .csi_dt = 0x2a,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SBGGR10P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SBGGR10,
> + .code = MEDIA_BUS_FMT_SBGGR10_1X10,
> + .depth = 10,
> + .csi_dt = 0x2b,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGBRG10P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SGBRG10,
> + .code = MEDIA_BUS_FMT_SGBRG10_1X10,
> + .depth = 10,
> + .csi_dt = 0x2b,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGRBG10P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SGRBG10,
> + .code = MEDIA_BUS_FMT_SGRBG10_1X10,
> + .depth = 10,
> + .csi_dt = 0x2b,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SRGGB10P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SRGGB10,
> + .code = MEDIA_BUS_FMT_SRGGB10_1X10,
> + .depth = 10,
> + .csi_dt = 0x2b,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SBGGR12P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SBGGR12,
> + .code = MEDIA_BUS_FMT_SBGGR12_1X12,
> + .depth = 12,
> + .csi_dt = 0x2c,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGBRG12P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SGBRG12,
> + .code = MEDIA_BUS_FMT_SGBRG12_1X12,
> + .depth = 12,
> + .csi_dt = 0x2c,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGRBG12P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SGRBG12,
> + .code = MEDIA_BUS_FMT_SGRBG12_1X12,
> + .depth = 12,
> + .csi_dt = 0x2c,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SRGGB12P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SRGGB12,
> + .code = MEDIA_BUS_FMT_SRGGB12_1X12,
> + .depth = 12,
> + .csi_dt = 0x2c,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SBGGR14P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SBGGR14,
> + .code = MEDIA_BUS_FMT_SBGGR14_1X14,
> + .depth = 14,
> + .csi_dt = 0x2d,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGBRG14P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SGBRG14,
> + .code = MEDIA_BUS_FMT_SGBRG14_1X14,
> + .depth = 14,
> + .csi_dt = 0x2d,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SGRBG14P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SGRBG14,
> + .code = MEDIA_BUS_FMT_SGRBG14_1X14,
> + .depth = 14,
> + .csi_dt = 0x2d,
> + }, {
> + .fourcc = V4L2_PIX_FMT_SRGGB14P,
> + .unpacked_fourcc = V4L2_PIX_FMT_SRGGB14,
> + .code = MEDIA_BUS_FMT_SRGGB14_1X14,
> + .depth = 14,
> + .csi_dt = 0x2d,
> + }, {
> + /* 16 bit Bayer formats could be supported. */
> +
> + /* Greyscale formats */
> + .fourcc = V4L2_PIX_FMT_GREY,
> + .code = MEDIA_BUS_FMT_Y8_1X8,
> + .depth = 8,
> + .csi_dt = 0x2a,
> + }, {
> + .fourcc = V4L2_PIX_FMT_Y10P,
> + .unpacked_fourcc = V4L2_PIX_FMT_Y10,
> + .code = MEDIA_BUS_FMT_Y10_1X10,
> + .depth = 10,
> + .csi_dt = 0x2b,
> + }, {
> + .fourcc = V4L2_PIX_FMT_Y12P,
> + .unpacked_fourcc = V4L2_PIX_FMT_Y12,
> + .code = MEDIA_BUS_FMT_Y12_1X12,
> + .depth = 12,
> + .csi_dt = 0x2c,
> + }, {
> + .fourcc = V4L2_PIX_FMT_Y14P,
> + .unpacked_fourcc = V4L2_PIX_FMT_Y14,
> + .code = MEDIA_BUS_FMT_Y14_1X14,
> + .depth = 14,
> + .csi_dt = 0x2d,
> + },
> +};
> +
> +static const struct unicam_format_info unicam_meta_formats[] = {
> + {
> + .fourcc = V4L2_META_FMT_GENERIC_8,
> + .code = MEDIA_BUS_FMT_META_8,
> + .depth = 8,
> + .metadata_fmt = true,
> + }, {
> + .fourcc = V4L2_META_FMT_GENERIC_CSI2_10,
> + .code = MEDIA_BUS_FMT_META_10,
> + .depth = 10,
> + .metadata_fmt = true,
> + }, {
> + .fourcc = V4L2_META_FMT_GENERIC_CSI2_12,
> + .code = MEDIA_BUS_FMT_META_12,
> + .depth = 12,
> + .metadata_fmt = true,
> + }, {
> + .fourcc = V4L2_META_FMT_GENERIC_CSI2_14,
> + .code = MEDIA_BUS_FMT_META_14,
> + .depth = 14,
> + .metadata_fmt = true,
> + },
> +};
> +
> +/* Format setup functions */
> +static const struct unicam_format_info *
> +unicam_find_format_by_code(u32 code, u32 pad)
> +{
> + const struct unicam_format_info *formats;
> + unsigned int num_formats;
> + unsigned int i;
> +
> + if (pad == UNICAM_SD_PAD_SOURCE_IMAGE) {
> + formats = unicam_image_formats;
> + num_formats = ARRAY_SIZE(unicam_image_formats);
> + } else {
> + formats = unicam_meta_formats;
> + num_formats = ARRAY_SIZE(unicam_meta_formats);
> + }
> +
> + for (i = 0; i < num_formats; i++) {
> + if (formats[i].code == code)
> + return &formats[i];
> + }
> +
> + return NULL;
> +}
> +
> +static const struct unicam_format_info *
> +unicam_find_format_by_fourcc(u32 fourcc, u32 pad)
> +{
> + const struct unicam_format_info *formats;
> + unsigned int num_formats;
> + unsigned int i;
> +
> + if (pad == UNICAM_SD_PAD_SOURCE_IMAGE) {
> + formats = unicam_image_formats;
> + num_formats = ARRAY_SIZE(unicam_image_formats);
> + } else {
> + formats = unicam_meta_formats;
> + num_formats = ARRAY_SIZE(unicam_meta_formats);
> + }
> +
> + for (i = 0; i < num_formats; ++i) {
> + if (formats[i].fourcc == fourcc)
> + return &formats[i];
> + }
> +
> + return NULL;
> +}
> +
> +static void unicam_calc_image_size_bpl(struct unicam_device *unicam,
> + const struct unicam_format_info *fmtinfo,
> + struct v4l2_pix_format *pix)
> +{
> + u32 min_bpl;
> +
> + v4l_bound_align_image(&pix->width, UNICAM_IMAGE_MIN_WIDTH,
> + UNICAM_IMAGE_MAX_WIDTH, 2,
> + &pix->height, UNICAM_IMAGE_MIN_HEIGHT,
> + UNICAM_IMAGE_MAX_HEIGHT, 0, 0);
> +
> + /* Unpacking always goes to 16bpp */
> + if (pix->pixelformat == fmtinfo->unpacked_fourcc)
> + min_bpl = pix->width * 2;
> + else
> + min_bpl = pix->width * fmtinfo->depth / 8;
> + min_bpl = ALIGN(min_bpl, UNICAM_IMAGE_BPL_ALIGNMENT);
> +
> + pix->bytesperline = ALIGN(pix->bytesperline, UNICAM_IMAGE_BPL_ALIGNMENT);
> + pix->bytesperline = clamp_t(unsigned int, pix->bytesperline, min_bpl,
> + UNICAM_IMAGE_MAX_BPL);
> +
> + pix->sizeimage = pix->height * pix->bytesperline;
> +}
> +
> +static void unicam_calc_meta_size_bpl(struct unicam_device *unicam,
> + const struct unicam_format_info *fmtinfo,
> + struct v4l2_meta_format *meta)
> +{
> + v4l_bound_align_image(&meta->width, UNICAM_META_MIN_WIDTH,
> + UNICAM_META_MAX_WIDTH, 0,
> + &meta->height, UNICAM_META_MIN_HEIGHT,
> + UNICAM_META_MAX_HEIGHT, 0, 0);
> +
> + meta->bytesperline = ALIGN(meta->width * fmtinfo->depth / 8,
> + UNICAM_DMA_BPL_ALIGNMENT);
> + meta->buffersize = meta->height * meta->bytesperline;
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * Hardware handling
> + */
> +
> +static inline void unicam_clk_write(struct unicam_device *unicam, u32 val)
> +{
> + /* Pass the CM_PASSWORD along with the value. */
> + writel(val | 0x5a000000, unicam->clk_gate_base);
> +}
> +
> +static inline u32 unicam_reg_read(struct unicam_device *unicam, u32 offset)
> +{
> + return readl(unicam->base + offset);
> +}
> +
> +static inline void unicam_reg_write(struct unicam_device *unicam, u32 offset, u32 val)
> +{
> + writel(val, unicam->base + offset);
> +}
> +
> +static inline int unicam_get_field(u32 value, u32 mask)
> +{
> + return (value & mask) >> __ffs(mask);
> +}
> +
> +static inline void unicam_set_field(u32 *valp, u32 field, u32 mask)
> +{
> + u32 val = *valp;
> +
> + val &= ~mask;
> + val |= (field << __ffs(mask)) & mask;
> + *valp = val;
> +}
> +
> +static inline void unicam_reg_write_field(struct unicam_device *unicam, u32 offset,
> + u32 field, u32 mask)
> +{
> + u32 val = unicam_reg_read(unicam, offset);
> +
> + unicam_set_field(&val, field, mask);
> + unicam_reg_write(unicam, offset, val);
> +}
> +
> +static void unicam_wr_dma_addr(struct unicam_node *node,
> + struct unicam_buffer *buf)
> +{
> + dma_addr_t endaddr = buf->dma_addr + buf->size;
> +
> + if (node->id == UNICAM_IMAGE_NODE) {
> + unicam_reg_write(node->dev, UNICAM_IBSA0, buf->dma_addr);
> + unicam_reg_write(node->dev, UNICAM_IBEA0, endaddr);
> + } else {
> + unicam_reg_write(node->dev, UNICAM_DBSA0, buf->dma_addr);
> + unicam_reg_write(node->dev, UNICAM_DBEA0, endaddr);
> + }
> +}
> +
> +static unsigned int unicam_get_lines_done(struct unicam_device *unicam)
> +{
> + struct unicam_node *node = &unicam->node[UNICAM_IMAGE_NODE];
> + unsigned int stride = node->fmt.fmt.pix.bytesperline;
> + struct unicam_buffer *frm = node->cur_frm;
> + dma_addr_t cur_addr;
> +
> + if (!frm)
> + return 0;
> +
> + cur_addr = unicam_reg_read(unicam, UNICAM_IBWP);
> + return (unsigned int)(cur_addr - frm->dma_addr) / stride;
> +}
> +
> +static void unicam_schedule_next_buffer(struct unicam_node *node)
> +{
> + struct unicam_buffer *buf;
> +
> + buf = list_first_entry(&node->dma_queue, struct unicam_buffer, list);
> + node->next_frm = buf;
> + list_del(&buf->list);
> +
> + unicam_wr_dma_addr(node, buf);
> +}
> +
> +static void unicam_schedule_dummy_buffer(struct unicam_node *node)
> +{
> + int node_id = is_image_node(node) ? UNICAM_IMAGE_NODE : UNICAM_METADATA_NODE;
> +
> + dev_dbg(node->dev->dev, "Scheduling dummy buffer for node %d\n", node_id);
> +
> + unicam_wr_dma_addr(node, &node->dummy_buf);
> +
> + node->next_frm = NULL;
> +}
> +
> +static void unicam_process_buffer_complete(struct unicam_node *node,
> + unsigned int sequence)
> +{
> + node->cur_frm->vb.field = node->fmt.fmt.pix.field;
> + node->cur_frm->vb.sequence = sequence;
> +
> + vb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
> +}
> +
> +static void unicam_queue_event_sof(struct unicam_device *unicam)
> +{
> + struct unicam_node *node = &unicam->node[UNICAM_IMAGE_NODE];
> +
Extra newline.
> + struct v4l2_event event = {
> + .type = V4L2_EVENT_FRAME_SYNC,
> + .u.frame_sync.frame_sequence = unicam->sequence,
> + };
> +
> + v4l2_event_queue(&node->video_dev, &event);
> +}
> +
> +static irqreturn_t unicam_isr(int irq, void *dev)
> +{
> + struct unicam_device *unicam = dev;
> + unsigned int lines_done = unicam_get_lines_done(dev);
> + unsigned int sequence = unicam->sequence;
> + unsigned int i;
> + u32 ista, sta;
> + bool fe;
> + u64 ts;
> +
> + sta = unicam_reg_read(unicam, UNICAM_STA);
> + /* Write value back to clear the interrupts */
> + unicam_reg_write(unicam, UNICAM_STA, sta);
> +
> + ista = unicam_reg_read(unicam, UNICAM_ISTA);
> + /* Write value back to clear the interrupts */
> + unicam_reg_write(unicam, UNICAM_ISTA, ista);
> +
> + dev_dbg(unicam->dev, "ISR: ISTA: 0x%X, STA: 0x%X, sequence %d, lines done %d\n",
> + ista, sta, sequence, lines_done);
> +
> + if (!(sta & (UNICAM_IS | UNICAM_PI0)))
> + return IRQ_HANDLED;
> +
> + /*
> + * Look for either the Frame End interrupt or the Packet Capture status
> + * to signal a frame end.
> + */
> + fe = ista & UNICAM_FEI || sta & UNICAM_PI0;
> +
> + /*
> + * We must run the frame end handler first. If we have a valid next_frm
> + * and we get a simultaneout FE + FS interrupt, running the FS handler
> + * first would null out the next_frm ptr and we would have lost the
> + * buffer forever.
> + */
> + if (fe) {
> + /*
> + * Ensure we have swapped buffers already as we can't
> + * stop the peripheral. If no buffer is available, use a
> + * dummy buffer to dump out frames until we get a new buffer
> + * to use.
> + */
> + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
> + if (!unicam->node[i].streaming)
> + continue;
> +
> + /*
> + * If cur_frm == next_frm, it means we have not had
> + * a chance to swap buffers, likely due to having
> + * multiple interrupts occurring simultaneously (like FE
> + * + FS + LS). In this case, we cannot signal the buffer
> + * as complete, as the HW will reuse that buffer.
> + */
> + if (unicam->node[i].cur_frm &&
> + unicam->node[i].cur_frm != unicam->node[i].next_frm)
> + unicam_process_buffer_complete(&unicam->node[i],
> + sequence);
> + unicam->node[i].cur_frm = unicam->node[i].next_frm;
> + }
> + unicam->sequence++;
Does access to this data need to be serialised somehow.
> + }
> +
> + if (ista & UNICAM_FSI) {
> + /*
> + * Timestamp is to be when the first data byte was captured,
> + * aka frame start.
> + */
> + ts = ktime_get_ns();
> + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
> + if (!unicam->node[i].streaming)
> + continue;
> +
> + if (unicam->node[i].cur_frm)
> + unicam->node[i].cur_frm->vb.vb2_buf.timestamp =
> + ts;
> + else
> + dev_dbg(unicam->v4l2_dev.dev,
> + "ISR: [%d] Dropping frame, buffer not available at FS\n",
> + i);
> + /*
> + * Set the next frame output to go to a dummy frame
> + * if we have not managed to obtain another frame
> + * from the queue.
> + */
> + unicam_schedule_dummy_buffer(&unicam->node[i]);
> + }
> +
> + unicam_queue_event_sof(unicam);
> + }
> +
> + /*
> + * Cannot swap buffer at frame end, there may be a race condition
> + * where the HW does not actually swap it if the new frame has
> + * already started.
> + */
> + if (ista & (UNICAM_FSI | UNICAM_LCI) && !fe) {
> + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
> + if (!unicam->node[i].streaming)
> + continue;
> +
> + spin_lock(&unicam->node[i].dma_queue_lock);
> + if (!list_empty(&unicam->node[i].dma_queue) &&
> + !unicam->node[i].next_frm)
> + unicam_schedule_next_buffer(&unicam->node[i]);
> + spin_unlock(&unicam->node[i].dma_queue_lock);
> + }
> + }
> +
> + if (unicam_reg_read(unicam, UNICAM_ICTL) & UNICAM_FCM) {
> + /* Switch out of trigger mode if selected */
> + unicam_reg_write_field(unicam, UNICAM_ICTL, 1, UNICAM_TFC);
> + unicam_reg_write_field(unicam, UNICAM_ICTL, 0, UNICAM_FCM);
> + }
> + return IRQ_HANDLED;
> +}
> +
> +static void unicam_set_packing_config(struct unicam_device *unicam)
> +{
> + struct unicam_node *node = &unicam->node[UNICAM_IMAGE_NODE];
> + u32 pack, unpack;
> + u32 val;
> +
> + if (node->fmt.fmt.pix.pixelformat == node->fmtinfo->fourcc) {
> + unpack = UNICAM_PUM_NONE;
> + pack = UNICAM_PPM_NONE;
> + } else {
> + switch (node->fmtinfo->depth) {
> + case 8:
> + unpack = UNICAM_PUM_UNPACK8;
> + break;
> + case 10:
> + unpack = UNICAM_PUM_UNPACK10;
> + break;
> + case 12:
> + unpack = UNICAM_PUM_UNPACK12;
> + break;
> + case 14:
> + unpack = UNICAM_PUM_UNPACK14;
> + break;
> + case 16:
> + unpack = UNICAM_PUM_UNPACK16;
> + break;
> + default:
> + unpack = UNICAM_PUM_NONE;
> + break;
> + }
> +
> + /* Repacking is always to 16bpp */
> + pack = UNICAM_PPM_PACK16;
Also 8-bit data?
> + }
> +
> + val = 0;
You could do initialisation in declaration.
> + unicam_set_field(&val, unpack, UNICAM_PUM_MASK);
> + unicam_set_field(&val, pack, UNICAM_PPM_MASK);
> + unicam_reg_write(unicam, UNICAM_IPIPE, val);
> +}
> +
> +static void unicam_cfg_image_id(struct unicam_device *unicam)
> +{
> + struct unicam_node *node = &unicam->node[UNICAM_IMAGE_NODE];
> +
> + if (unicam->bus_type == V4L2_MBUS_CSI2_DPHY) {
> + /* CSI2 mode, hardcode VC 0 for now. */
> + unicam_reg_write(unicam, UNICAM_IDI0,
> + (0 << 6) | node->fmtinfo->csi_dt);
> + } else {
> + /* CCP2 mode */
> + unicam_reg_write(unicam, UNICAM_IDI0,
> + 0x80 | node->fmtinfo->csi_dt);
> + }
> +}
> +
> +static void unicam_enable_ed(struct unicam_device *unicam)
> +{
> + u32 val = unicam_reg_read(unicam, UNICAM_DCS);
> +
> + unicam_set_field(&val, 2, UNICAM_EDL_MASK);
> + /* Do not wrap at the end of the embedded data buffer */
> + unicam_set_field(&val, 0, UNICAM_DBOB);
> +
> + unicam_reg_write(unicam, UNICAM_DCS, val);
> +}
> +
> +static void unicam_start_rx(struct unicam_device *unicam,
> + struct unicam_buffer *buf)
> +{
> + struct unicam_node *node = &unicam->node[UNICAM_IMAGE_NODE];
> + int line_int_freq = node->fmt.fmt.pix.height >> 2;
> + unsigned int i;
> + u32 val;
> +
> + if (line_int_freq < 128)
> + line_int_freq = 128;
line_int_freq = max(line_int_freq, 128);
> +
> + /* Enable lane clocks */
> + val = 1;
Initialise in the loop initialisation below, I'd say.
> + for (i = 0; i < unicam->active_data_lanes; i++)
> + val = val << 2 | 1;
> + unicam_clk_write(unicam, val);
> +
> + /* Basic init */
> + unicam_reg_write(unicam, UNICAM_CTRL, UNICAM_MEM);
> +
> + /* Enable analogue control, and leave in reset. */
> + val = UNICAM_AR;
> + unicam_set_field(&val, 7, UNICAM_CTATADJ_MASK);
> + unicam_set_field(&val, 7, UNICAM_PTATADJ_MASK);
> + unicam_reg_write(unicam, UNICAM_ANA, val);
> + usleep_range(1000, 2000);
> +
> + /* Come out of reset */
> + unicam_reg_write_field(unicam, UNICAM_ANA, 0, UNICAM_AR);
> +
> + /* Peripheral reset */
> + unicam_reg_write_field(unicam, UNICAM_CTRL, 1, UNICAM_CPR);
> + unicam_reg_write_field(unicam, UNICAM_CTRL, 0, UNICAM_CPR);
> +
> + unicam_reg_write_field(unicam, UNICAM_CTRL, 0, UNICAM_CPE);
> +
> + /* Enable Rx control. */
> + val = unicam_reg_read(unicam, UNICAM_CTRL);
> + if (unicam->bus_type == V4L2_MBUS_CSI2_DPHY) {
> + unicam_set_field(&val, UNICAM_CPM_CSI2, UNICAM_CPM_MASK);
> + unicam_set_field(&val, UNICAM_DCM_STROBE, UNICAM_DCM_MASK);
> + } else {
> + unicam_set_field(&val, UNICAM_CPM_CCP2, UNICAM_CPM_MASK);
> + unicam_set_field(&val, unicam->bus_flags, UNICAM_DCM_MASK);
> + }
> + /* Packet framer timeout */
> + unicam_set_field(&val, 0xf, UNICAM_PFT_MASK);
> + unicam_set_field(&val, 128, UNICAM_OET_MASK);
> + unicam_reg_write(unicam, UNICAM_CTRL, val);
> +
> + unicam_reg_write(unicam, UNICAM_IHWIN, 0);
> + unicam_reg_write(unicam, UNICAM_IVWIN, 0);
> +
> + /* AXI bus access QoS setup */
> + val = unicam_reg_read(unicam, UNICAM_PRI);
> + unicam_set_field(&val, 0, UNICAM_BL_MASK);
> + unicam_set_field(&val, 0, UNICAM_BS_MASK);
> + unicam_set_field(&val, 0xe, UNICAM_PP_MASK);
> + unicam_set_field(&val, 8, UNICAM_NP_MASK);
> + unicam_set_field(&val, 2, UNICAM_PT_MASK);
> + unicam_set_field(&val, 1, UNICAM_PE);
> + unicam_reg_write(unicam, UNICAM_PRI, val);
> +
> + unicam_reg_write_field(unicam, UNICAM_ANA, 0, UNICAM_DDL);
> +
> + /* Always start in trigger frame capture mode (UNICAM_FCM set) */
> + val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM | UNICAM_IBOB;
> + unicam_set_field(&val, line_int_freq, UNICAM_LCIE_MASK);
> + unicam_reg_write(unicam, UNICAM_ICTL, val);
> + unicam_reg_write(unicam, UNICAM_STA, UNICAM_STA_MASK_ALL);
> + unicam_reg_write(unicam, UNICAM_ISTA, UNICAM_ISTA_MASK_ALL);
> +
> + /* tclk_term_en */
> + unicam_reg_write_field(unicam, UNICAM_CLT, 2, UNICAM_CLT1_MASK);
> + /* tclk_settle */
> + unicam_reg_write_field(unicam, UNICAM_CLT, 6, UNICAM_CLT2_MASK);
> + /* td_term_en */
> + unicam_reg_write_field(unicam, UNICAM_DLT, 2, UNICAM_DLT1_MASK);
> + /* ths_settle */
> + unicam_reg_write_field(unicam, UNICAM_DLT, 6, UNICAM_DLT2_MASK);
> + /* trx_enable */
> + unicam_reg_write_field(unicam, UNICAM_DLT, 0, UNICAM_DLT3_MASK);
> +
> + unicam_reg_write_field(unicam, UNICAM_CTRL, 0, UNICAM_SOE);
> +
> + /* Packet compare setup - required to avoid missing frame ends */
> + val = 0;
> + unicam_set_field(&val, 1, UNICAM_PCE);
> + unicam_set_field(&val, 1, UNICAM_GI);
> + unicam_set_field(&val, 1, UNICAM_CPH);
> + unicam_set_field(&val, 0, UNICAM_PCVC_MASK);
> + unicam_set_field(&val, 1, UNICAM_PCDT_MASK);
> + unicam_reg_write(unicam, UNICAM_CMP0, val);
> +
> + /* Enable clock lane and set up terminations */
> + val = 0;
> + if (unicam->bus_type == V4L2_MBUS_CSI2_DPHY) {
> + /* CSI2 */
> + unicam_set_field(&val, 1, UNICAM_CLE);
> + unicam_set_field(&val, 1, UNICAM_CLLPE);
> + if (!(unicam->bus_flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK)) {
> + unicam_set_field(&val, 1, UNICAM_CLTRE);
> + unicam_set_field(&val, 1, UNICAM_CLHSE);
> + }
> + } else {
> + /* CCP2 */
> + unicam_set_field(&val, 1, UNICAM_CLE);
> + unicam_set_field(&val, 1, UNICAM_CLHSE);
> + unicam_set_field(&val, 1, UNICAM_CLTRE);
> + }
> + unicam_reg_write(unicam, UNICAM_CLK, val);
> +
> + /*
> + * Enable required data lanes with appropriate terminations.
> + * The same value needs to be written to UNICAM_DATn registers for
> + * the active lanes, and 0 for inactive ones.
> + */
> + val = 0;
> + if (unicam->bus_type == V4L2_MBUS_CSI2_DPHY) {
> + /* CSI2 */
> + unicam_set_field(&val, 1, UNICAM_DLE);
> + unicam_set_field(&val, 1, UNICAM_DLLPE);
> + if (!(unicam->bus_flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK)) {
> + unicam_set_field(&val, 1, UNICAM_DLTRE);
> + unicam_set_field(&val, 1, UNICAM_DLHSE);
> + }
> + } else {
> + /* CCP2 */
> + unicam_set_field(&val, 1, UNICAM_DLE);
> + unicam_set_field(&val, 1, UNICAM_DLHSE);
> + unicam_set_field(&val, 1, UNICAM_DLTRE);
> + }
> + unicam_reg_write(unicam, UNICAM_DAT0, val);
> +
> + if (unicam->active_data_lanes == 1)
> + val = 0;
> + unicam_reg_write(unicam, UNICAM_DAT1, val);
> +
> + if (unicam->max_data_lanes > 2) {
> + /*
> + * Registers UNICAM_DAT2 and UNICAM_DAT3 only valid if the
> + * instance supports more than 2 data lanes.
> + */
> + if (unicam->active_data_lanes == 2)
> + val = 0;
> + unicam_reg_write(unicam, UNICAM_DAT2, val);
> +
> + if (unicam->active_data_lanes == 3)
> + val = 0;
> + unicam_reg_write(unicam, UNICAM_DAT3, val);
> + }
> +
> + unicam_reg_write(unicam, UNICAM_IBLS,
> + node->fmt.fmt.pix.bytesperline);
> + unicam_wr_dma_addr(&unicam->node[UNICAM_IMAGE_NODE], buf);
> + unicam_set_packing_config(unicam);
> + unicam_cfg_image_id(unicam);
> +
> + val = unicam_reg_read(unicam, UNICAM_MISC);
> + unicam_set_field(&val, 1, UNICAM_FL0);
> + unicam_set_field(&val, 1, UNICAM_FL1);
> + unicam_reg_write(unicam, UNICAM_MISC, val);
> +
> + /* Enable peripheral */
> + unicam_reg_write_field(unicam, UNICAM_CTRL, 1, UNICAM_CPE);
> +
> + /* Load image pointers */
> + unicam_reg_write_field(unicam, UNICAM_ICTL, 1, UNICAM_LIP_MASK);
> +
> + /*
> + * Enable trigger only for the first frame to
> + * sync correctly to the FS from the source.
> + */
> + unicam_reg_write_field(unicam, UNICAM_ICTL, 1, UNICAM_TFC);
> +}
> +
> +static void unicam_start_metadata(struct unicam_device *unicam,
> + struct unicam_buffer *buf)
> +{
> + struct unicam_node *node = &unicam->node[UNICAM_METADATA_NODE];
> +
> + unicam_enable_ed(unicam);
> + unicam_wr_dma_addr(node, buf);
> + unicam_reg_write_field(unicam, UNICAM_DCS, 1, UNICAM_LDP);
> +}
> +
> +static void unicam_disable(struct unicam_device *unicam)
> +{
> + /* Analogue lane control disable */
> + unicam_reg_write_field(unicam, UNICAM_ANA, 1, UNICAM_DDL);
> +
> + /* Stop the output engine */
> + unicam_reg_write_field(unicam, UNICAM_CTRL, 1, UNICAM_SOE);
> +
> + /* Disable the data lanes. */
> + unicam_reg_write(unicam, UNICAM_DAT0, 0);
> + unicam_reg_write(unicam, UNICAM_DAT1, 0);
> +
> + if (unicam->max_data_lanes > 2) {
> + unicam_reg_write(unicam, UNICAM_DAT2, 0);
> + unicam_reg_write(unicam, UNICAM_DAT3, 0);
> + }
> +
> + /* Peripheral reset */
> + unicam_reg_write_field(unicam, UNICAM_CTRL, 1, UNICAM_CPR);
> + usleep_range(50, 100);
> + unicam_reg_write_field(unicam, UNICAM_CTRL, 0, UNICAM_CPR);
> +
> + /* Disable peripheral */
> + unicam_reg_write_field(unicam, UNICAM_CTRL, 0, UNICAM_CPE);
> +
> + /* Clear ED setup */
> + unicam_reg_write(unicam, UNICAM_DCS, 0);
> +
> + /* Disable all lane clocks */
> + unicam_clk_write(unicam, 0);
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * V4L2 subdev operations
> + */
> +
> +static int __unicam_subdev_set_routing(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state,
> + struct v4l2_subdev_krouting *routing)
> +{
> + struct v4l2_subdev_route *route;
> + int ret;
> +
> + ret = v4l2_subdev_routing_validate(sd, routing,
> + V4L2_SUBDEV_ROUTING_ONLY_1_TO_1);
> + if (ret)
> + return ret;
> +
> + ret = v4l2_subdev_set_routing(sd, state, routing);
> + if (ret)
> + return ret;
> +
> + for_each_active_route(&state->routing, route) {
> + const struct v4l2_mbus_framefmt *def_fmt;
> + struct v4l2_mbus_framefmt *fmt;
> +
> + if (route->source_pad == UNICAM_SD_PAD_SOURCE_IMAGE)
> + def_fmt = &unicam_default_image_format;
> + else
> + def_fmt = &unicam_default_meta_format;
> +
> + fmt = v4l2_subdev_state_get_format(state, route->sink_pad,
> + route->sink_stream);
> + *fmt = *def_fmt;
> + fmt = v4l2_subdev_state_get_format(state, route->source_pad,
> + route->source_stream);
> + *fmt = *def_fmt;
> + }
> +
> + return 0;
> +}
> +
> +static int unicam_subdev_init_state(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state)
> +{
> + struct v4l2_subdev_route routes[] = {
> + {
> + .sink_pad = UNICAM_SD_PAD_SINK,
> + .sink_stream = 0,
> + .source_pad = UNICAM_SD_PAD_SOURCE_IMAGE,
> + .source_stream = 0,
> + .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
> + },
> + };
> +
> + struct v4l2_subdev_krouting routing = {
> + .len_routes = ARRAY_SIZE(routes),
> + .num_routes = ARRAY_SIZE(routes),
> + .routes = routes,
> + };
> +
> + /* Initialize routing to single route to the fist source pad. */
> + return __unicam_subdev_set_routing(sd, state, &routing);
> +}
> +
> +static int unicam_subdev_enum_mbus_code(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state,
> + struct v4l2_subdev_mbus_code_enum *code)
> +{
> + u32 pad, stream;
> + int ret;
> +
> + ret = v4l2_subdev_routing_find_opposite_end(&state->routing,
> + code->pad, code->stream,
> + &pad, &stream);
> + if (ret)
> + return ret;
> +
> + if (unicam_sd_pad_is_source(code->pad)) {
> + /* No transcoding, source and sink codes must match. */
> + const struct v4l2_mbus_framefmt *fmt;
> +
> + fmt = v4l2_subdev_state_get_format(state, pad, stream);
> + if (!fmt)
> + return -EINVAL;
> +
> + if (code->index > 0)
> + return -EINVAL;
> +
> + code->code = fmt->code;
> + } else {
> + const struct unicam_format_info *formats;
> + unsigned int num_formats;
> +
> + if (pad == UNICAM_SD_PAD_SOURCE_IMAGE) {
> + formats = unicam_image_formats;
> + num_formats = ARRAY_SIZE(unicam_image_formats);
> + } else {
> + formats = unicam_meta_formats;
> + num_formats = ARRAY_SIZE(unicam_meta_formats);
> + }
> +
> + if (code->index >= num_formats)
> + return -EINVAL;
> +
> + code->code = formats[code->index].code;
> + }
> +
> + return 0;
> +}
> +
> +static int unicam_subdev_enum_frame_size(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state,
> + struct v4l2_subdev_frame_size_enum *fse)
> +{
> + u32 pad, stream;
> + int ret;
> +
> + if (fse->index > 0)
> + return -EINVAL;
> +
> + ret = v4l2_subdev_routing_find_opposite_end(&state->routing, fse->pad,
> + fse->stream, &pad,
> + &stream);
> + if (ret)
> + return ret;
> +
> + if (unicam_sd_pad_is_source(fse->pad)) {
> + /* No transcoding, source and sink formats must match. */
> + const struct v4l2_mbus_framefmt *fmt;
> +
> + fmt = v4l2_subdev_state_get_format(state, pad, stream);
> + if (!fmt)
> + return -EINVAL;
> +
> + if (fse->code != fmt->code)
> + return -EINVAL;
> +
> + fse->min_width = fmt->width;
> + fse->max_width = fmt->width;
> + fse->min_height = fmt->height;
> + fse->max_height = fmt->height;
> + } else {
> + const struct unicam_format_info *fmtinfo;
> +
> + fmtinfo = unicam_find_format_by_code(fse->code, pad);
> + if (!fmtinfo)
> + return -EINVAL;
> +
> + if (pad == UNICAM_SD_PAD_SOURCE_IMAGE) {
> + fse->min_width = UNICAM_IMAGE_MIN_WIDTH;
> + fse->max_width = UNICAM_IMAGE_MAX_WIDTH;
> + fse->min_height = UNICAM_IMAGE_MIN_HEIGHT;
> + fse->max_height = UNICAM_IMAGE_MAX_HEIGHT;
> + } else {
> + fse->min_width = UNICAM_META_MIN_WIDTH;
> + fse->max_width = UNICAM_META_MAX_WIDTH;
> + fse->min_height = UNICAM_META_MIN_HEIGHT;
> + fse->max_height = UNICAM_META_MAX_HEIGHT;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int unicam_subdev_set_format(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state,
> + struct v4l2_subdev_format *format)
> +{
> + struct unicam_device *unicam = sd_to_unicam_device(sd);
> + struct v4l2_mbus_framefmt *sink_format, *source_format;
> + const struct unicam_format_info *fmtinfo;
> + u32 source_pad, source_stream;
> + int ret;
> +
> + if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE &&
> + unicam->subdev.streaming)
> + return -EBUSY;
> +
> + /* No transcoding, source and sink formats must match. */
> + if (unicam_sd_pad_is_source(format->pad))
> + return v4l2_subdev_get_fmt(sd, state, format);
> +
> + /*
> + * Allowed formats for the stream on the sink pad depend on what source
> + * pad the stream is routed to. Find the corresponding source pad and
> + * use it to validate the media bus code.
> + */
> + ret = v4l2_subdev_routing_find_opposite_end(&state->routing,
> + format->pad, format->stream,
> + &source_pad, &source_stream);
> + if (ret)
> + return ret;
> +
> + fmtinfo = unicam_find_format_by_code(format->format.code, source_pad);
> + if (!fmtinfo) {
> + fmtinfo = source_pad == UNICAM_SD_PAD_SOURCE_IMAGE
> + ? &unicam_image_formats[0] : &unicam_meta_formats[0];
> + format->format.code = fmtinfo->code;
> + }
> +
> + if (source_pad == UNICAM_SD_PAD_SOURCE_IMAGE) {
> + format->format.width = clamp_t(unsigned int,
> + format->format.width,
> + UNICAM_IMAGE_MIN_WIDTH,
> + UNICAM_IMAGE_MAX_WIDTH);
> + format->format.height = clamp_t(unsigned int,
> + format->format.height,
> + UNICAM_IMAGE_MIN_HEIGHT,
> + UNICAM_IMAGE_MAX_HEIGHT);
> + format->format.field = V4L2_FIELD_NONE;
> + } else {
> + format->format.width = clamp_t(unsigned int,
> + format->format.width,
> + UNICAM_META_MIN_WIDTH,
> + UNICAM_META_MAX_WIDTH);
> + format->format.height = clamp_t(unsigned int,
> + format->format.height,
> + UNICAM_META_MIN_HEIGHT,
> + UNICAM_META_MAX_HEIGHT);
> + format->format.field = V4L2_FIELD_NONE;
> +
> + /* Colorspace don't apply to metadata. */
> + format->format.colorspace = 0;
> + format->format.ycbcr_enc = 0;
> + format->format.quantization = 0;
> + format->format.xfer_func = 0;
> + }
> +
> + sink_format = v4l2_subdev_state_get_format(state, format->pad,
> + format->stream);
> + source_format = v4l2_subdev_state_get_format(state, source_pad,
> + source_stream);
> + *sink_format = format->format;
> + *source_format = format->format;
> +
> + return 0;
> +}
> +
> +static int unicam_subdev_set_routing(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state,
> + enum v4l2_subdev_format_whence which,
> + struct v4l2_subdev_krouting *routing)
> +{
> + struct unicam_device *unicam = sd_to_unicam_device(sd);
> +
> + if (which == V4L2_SUBDEV_FORMAT_ACTIVE && unicam->subdev.streaming)
> + return -EBUSY;
> +
> + return __unicam_subdev_set_routing(sd, state, routing);
> +}
> +
> +static int unicam_sd_enable_streams(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state, u32 pad,
> + u64 streams_mask)
> +{
> + struct unicam_device *unicam = sd_to_unicam_device(sd);
> + u32 other_pad, other_stream;
> + int ret;
> +
> + ret = v4l2_subdev_routing_find_opposite_end(&state->routing, pad, 0,
> + &other_pad, &other_stream);
> + if (ret)
> + return ret;
> +
> + unicam->sequence = 0;
> +
> + ret = v4l2_subdev_enable_streams(unicam->sensor.subdev,
> + unicam->sensor.pad->index,
> + BIT(other_stream));
> + if (ret) {
> + dev_err(unicam->dev, "stream on failed in subdev\n");
> + return ret;
> + }
> +
> + unicam->subdev.streaming = true;
> +
> + return 0;
> +}
> +
> +static int unicam_sd_disable_streams(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state, u32 pad,
> + u64 streams_mask)
> +{
> + struct unicam_device *unicam = sd_to_unicam_device(sd);
> + u32 other_pad, other_stream;
> + int ret;
> +
> + ret = v4l2_subdev_routing_find_opposite_end(&state->routing, pad, 0,
> + &other_pad, &other_stream);
> + if (ret)
> + return ret;
> +
> + v4l2_subdev_disable_streams(unicam->sensor.subdev,
> + unicam->sensor.pad->index,
> + BIT(other_stream));
> +
> + unicam->subdev.streaming = false;
> +
> + return 0;
> +}
> +
> +static const struct v4l2_subdev_pad_ops unicam_subdev_pad_ops = {
> + .enum_mbus_code = unicam_subdev_enum_mbus_code,
> + .enum_frame_size = unicam_subdev_enum_frame_size,
> + .get_fmt = v4l2_subdev_get_fmt,
> + .set_fmt = unicam_subdev_set_format,
> + .set_routing = unicam_subdev_set_routing,
> + .enable_streams = unicam_sd_enable_streams,
> + .disable_streams = unicam_sd_disable_streams,
> +};
> +
> +static const struct v4l2_subdev_ops unicam_subdev_ops = {
> + .pad = &unicam_subdev_pad_ops,
> +};
> +
> +static const struct v4l2_subdev_internal_ops unicam_subdev_internal_ops = {
> + .init_state = unicam_subdev_init_state,
> +};
> +
> +static const struct media_entity_operations unicam_subdev_media_ops = {
> + .link_validate = v4l2_subdev_link_validate,
> + .has_pad_interdep = v4l2_subdev_has_pad_interdep,
> +};
> +
> +static int unicam_subdev_init(struct unicam_device *unicam)
> +{
> + struct v4l2_subdev *sd = &unicam->subdev.sd;
> + int ret;
> +
> + v4l2_subdev_init(sd, &unicam_subdev_ops);
> + sd->internal_ops = &unicam_subdev_internal_ops;
> + v4l2_set_subdevdata(sd, unicam);
> +
> + sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
> + sd->entity.ops = &unicam_subdev_media_ops;
> + sd->dev = unicam->dev;
> + sd->owner = THIS_MODULE;
> + sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS;
> +
> + strscpy(sd->name, "unicam", sizeof(sd->name));
> +
> + unicam->subdev.pads[UNICAM_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
> + unicam->subdev.pads[UNICAM_SD_PAD_SOURCE_IMAGE].flags = MEDIA_PAD_FL_SOURCE;
> + unicam->subdev.pads[UNICAM_SD_PAD_SOURCE_METADATA].flags = MEDIA_PAD_FL_SOURCE;
> +
> + ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(unicam->subdev.pads),
> + unicam->subdev.pads);
> + if (ret) {
> + dev_err(unicam->dev, "Failed to initialize media entity: %d\n",
> + ret);
> + return ret;
> + }
> +
> + ret = v4l2_subdev_init_finalize(sd);
> + if (ret) {
> + dev_err(unicam->dev, "Failed to initialize subdev: %d\n", ret);
> + goto err_entity;
> + }
> +
> + ret = v4l2_device_register_subdev(&unicam->v4l2_dev, sd);
> + if (ret) {
> + dev_err(unicam->dev, "Failed to register subdev: %d\n", ret);
> + goto err_subdev;
> + }
> +
> + return 0;
> +
> +err_subdev:
> + v4l2_subdev_cleanup(sd);
> +err_entity:
> + media_entity_cleanup(&sd->entity);
> + return ret;
> +}
> +
> +static void unicam_subdev_cleanup(struct unicam_device *unicam)
> +{
> + v4l2_subdev_cleanup(&unicam->subdev.sd);
> + media_entity_cleanup(&unicam->subdev.sd.entity);
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * Videobuf2 queue operations
> + */
> +
> +static int unicam_queue_setup(struct vb2_queue *vq,
> + unsigned int *nbuffers,
> + unsigned int *nplanes,
> + unsigned int sizes[],
> + struct device *alloc_devs[])
> +{
> + struct unicam_node *node = vb2_get_drv_priv(vq);
> + u32 size = is_image_node(node) ? node->fmt.fmt.pix.sizeimage
> + : node->fmt.fmt.meta.buffersize;
> +
> + if (vq->num_buffers + *nbuffers < 3)
> + *nbuffers = 3 - vq->num_buffers;
> +
> + if (*nplanes) {
> + if (sizes[0] < size) {
> + dev_dbg(node->dev->dev, "sizes[0] %i < size %u\n",
> + sizes[0], size);
> + return -EINVAL;
> + }
> + size = sizes[0];
> + }
> +
> + *nplanes = 1;
> + sizes[0] = size;
> +
> + return 0;
> +}
> +
> +static int unicam_buffer_prepare(struct vb2_buffer *vb)
> +{
> + struct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);
> + struct unicam_buffer *buf = to_unicam_buffer(vb);
> + u32 size = is_image_node(node) ? node->fmt.fmt.pix.sizeimage
> + : node->fmt.fmt.meta.buffersize;
> +
> + if (vb2_plane_size(vb, 0) < size) {
> + dev_dbg(node->dev->dev,
> + "data will not fit into plane (%lu < %u)\n",
> + vb2_plane_size(vb, 0), size);
> + return -EINVAL;
> + }
> +
> + buf->dma_addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
> + buf->size = size;
> +
> + vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
> +
> + return 0;
> +}
> +
> +static void unicam_return_buffers(struct unicam_node *node,
> + enum vb2_buffer_state state)
> +{
> + struct unicam_buffer *buf, *tmp;
> +
> + list_for_each_entry_safe(buf, tmp, &node->dma_queue, list) {
> + list_del(&buf->list);
> + vb2_buffer_done(&buf->vb.vb2_buf, state);
> + }
> +
> + if (node->cur_frm)
> + vb2_buffer_done(&node->cur_frm->vb.vb2_buf,
> + state);
> + if (node->next_frm && node->cur_frm != node->next_frm)
> + vb2_buffer_done(&node->next_frm->vb.vb2_buf,
> + state);
> +
> + node->cur_frm = NULL;
> + node->next_frm = NULL;
> +}
> +
> +static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)
> +{
> + struct unicam_node *node = vb2_get_drv_priv(vq);
> + struct unicam_device *unicam = node->dev;
> + struct v4l2_subdev_state *state;
> + struct unicam_buffer *buf;
> + unsigned long flags;
> + int ret;
> + u32 pad, stream;
> + u32 remote_pad = is_image_node(node) ? UNICAM_SD_PAD_SOURCE_IMAGE
> + : UNICAM_SD_PAD_SOURCE_METADATA;
> +
> + /* Look for the route for the given pad and stream. */
> + state = v4l2_subdev_lock_and_get_active_state(&unicam->subdev.sd);
> + ret = v4l2_subdev_routing_find_opposite_end(&state->routing,
> + remote_pad, 0,
> + &pad, &stream);
> + v4l2_subdev_unlock_state(state);
> +
> + if (ret)
> + goto err_return_buffers;
> +
> + dev_dbg(unicam->dev, "Starting stream on %s: %u/%u -> %u/%u (%s)\n",
> + unicam->subdev.sd.name, pad, stream, remote_pad, 0,
> + is_metadata_node(node) ? "metadata" : "image");
> +
> + /* The metadata node can't be started alone. */
> + if (is_metadata_node(node)) {
> + if (!unicam->node[UNICAM_IMAGE_NODE].streaming) {
> + dev_err(unicam->dev,
> + "Can't start metadata without image\n");
> + ret = -EINVAL;
> + goto err_return_buffers;
> + }
> +
> + spin_lock_irqsave(&node->dma_queue_lock, flags);
> + buf = list_first_entry(&node->dma_queue,
> + struct unicam_buffer, list);
> + dev_dbg(unicam->dev, "buffer %p\n", buf);
> + node->cur_frm = buf;
> + node->next_frm = buf;
> + list_del(&buf->list);
> + spin_unlock_irqrestore(&node->dma_queue_lock, flags);
> +
> + unicam_start_metadata(unicam, buf);
> + node->streaming = true;
> + return 0;
> + }
> +
> + ret = pm_runtime_resume_and_get(unicam->dev);
> + if (ret < 0) {
> + dev_err(unicam->dev, "PM runtime resume failed: %d\n", ret);
> + goto err_return_buffers;
> + }
> +
> + ret = video_device_pipeline_start(&node->video_dev, &unicam->pipe);
> + if (ret < 0) {
> + dev_dbg(unicam->dev, "Failed to start media pipeline: %d\n", ret);
> + goto err_pm_put;
> + }
> +
> + spin_lock_irqsave(&node->dma_queue_lock, flags);
> + buf = list_first_entry(&node->dma_queue,
> + struct unicam_buffer, list);
> + dev_dbg(unicam->dev, "buffer %p\n", buf);
> + node->cur_frm = buf;
> + node->next_frm = buf;
> + list_del(&buf->list);
> + spin_unlock_irqrestore(&node->dma_queue_lock, flags);
> +
> + unicam_start_rx(unicam, buf);
> +
> + ret = v4l2_subdev_enable_streams(&unicam->subdev.sd, remote_pad, BIT(0));
> + if (ret < 0) {
> + dev_err(unicam->dev, "stream on failed in subdev\n");
> + goto error_pipeline;
> + }
> +
> + node->streaming = true;
> +
> + return 0;
> +
> +error_pipeline:
> + video_device_pipeline_stop(&node->video_dev);
> +err_pm_put:
> + pm_runtime_put_sync(unicam->dev);
> +err_return_buffers:
> + unicam_return_buffers(node, VB2_BUF_STATE_QUEUED);
> + return ret;
> +}
> +
> +static void unicam_stop_streaming(struct vb2_queue *vq)
> +{
> + struct unicam_node *node = vb2_get_drv_priv(vq);
> + struct unicam_device *unicam = node->dev;
> + u32 remote_pad_index = is_image_node(node) ? UNICAM_SD_PAD_SOURCE_IMAGE
> + : UNICAM_SD_PAD_SOURCE_METADATA;
> +
> + node->streaming = false;
> +
> + v4l2_subdev_disable_streams(&unicam->subdev.sd, remote_pad_index,
> + BIT(0));
> +
> + /* We can stream only with the image node. */
> + if (is_metadata_node(node)) {
> + /*
> + * Allow the hardware to spin in the dummy buffer.
> + * This is only really needed if the embedded data pad is
> + * disabled before the image pad.
> + */
> + unicam_wr_dma_addr(node, &node->dummy_buf);
> + goto dequeue_buffers;
> + }
> +
> + unicam_disable(unicam);
> +
> + video_device_pipeline_stop(&node->video_dev);
> + pm_runtime_put(unicam->dev);
> +
> +dequeue_buffers:
> + /* Clear all queued buffers for the node */
> + unicam_return_buffers(node, VB2_BUF_STATE_ERROR);
> +}
> +
> +static void unicam_buffer_queue(struct vb2_buffer *vb)
> +{
> + struct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);
> + struct unicam_buffer *buf = to_unicam_buffer(vb);
> +
> + spin_lock_irq(&node->dma_queue_lock);
> + list_add_tail(&buf->list, &node->dma_queue);
> + spin_unlock_irq(&node->dma_queue_lock);
> +}
> +
> +static const struct vb2_ops unicam_video_qops = {
> + .queue_setup = unicam_queue_setup,
> + .wait_prepare = vb2_ops_wait_prepare,
> + .wait_finish = vb2_ops_wait_finish,
> + .buf_prepare = unicam_buffer_prepare,
> + .start_streaming = unicam_start_streaming,
> + .stop_streaming = unicam_stop_streaming,
> + .buf_queue = unicam_buffer_queue,
> +};
> +
> +/* -----------------------------------------------------------------------------
> + * V4L2 video device operations
> + */
> +
> +static int unicam_querycap(struct file *file, void *priv,
> + struct v4l2_capability *cap)
> +{
> + strscpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));
> + strscpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));
> +
> + cap->capabilities |= V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_META_CAPTURE;
> +
> + return 0;
> +}
> +
> +static int unicam_enum_fmt_vid(struct file *file, void *priv,
> + struct v4l2_fmtdesc *f)
> +{
> + unsigned int index;
> + unsigned int i;
> +
> + for (i = 0, index = 0; i < ARRAY_SIZE(unicam_image_formats); i++) {
> + if (f->mbus_code && unicam_image_formats[i].code != f->mbus_code)
> + continue;
> +
> + if (index == f->index) {
> + f->pixelformat = unicam_image_formats[i].fourcc;
> + return 0;
> + }
> +
> + index++;
> +
> + if (!unicam_image_formats[i].unpacked_fourcc)
> + continue;
> +
> + if (index == f->index) {
> + f->pixelformat = unicam_image_formats[i].unpacked_fourcc;
> + return 0;
> + }
> +
> + index++;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int unicam_g_fmt_vid(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> +
> + *f = node->fmt;
> +
> + return 0;
> +}
> +
> +static const struct unicam_format_info *
> +__unicam_try_fmt_vid(struct unicam_node *node, struct v4l2_pix_format *pix)
> +{
> + const struct unicam_format_info *fmtinfo;
> +
> + /*
> + * Default to the first format if the requested pixel format code isn't
> + * supported.
> + */
> + fmtinfo = unicam_find_format_by_fourcc(pix->pixelformat,
> + UNICAM_SD_PAD_SOURCE_IMAGE);
> + if (!fmtinfo) {
> + fmtinfo = &unicam_image_formats[0];
> + pix->pixelformat = fmtinfo->fourcc;
> + }
> +
> + unicam_calc_image_size_bpl(node->dev, fmtinfo, pix);
> +
> + if (pix->field == V4L2_FIELD_ANY)
> + pix->field = V4L2_FIELD_NONE;
> +
> + return fmtinfo;
> +}
> +
> +static int unicam_try_fmt_vid(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> +
> + __unicam_try_fmt_vid(node, &f->fmt.pix);
> + return 0;
> +}
> +
> +static int unicam_s_fmt_vid(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> +
> + if (vb2_is_busy(&node->buffer_queue))
> + return -EBUSY;
> +
> + node->fmtinfo = __unicam_try_fmt_vid(node, &f->fmt.pix);
> + node->fmt = *f;
> +
> + return 0;
> +}
> +
> +static int unicam_enum_fmt_meta(struct file *file, void *priv,
> + struct v4l2_fmtdesc *f)
> +{
> + unsigned int i, index;
> +
> + for (i = 0, index = 0; i < ARRAY_SIZE(unicam_meta_formats); i++) {
> + if (f->mbus_code && unicam_meta_formats[i].code != f->mbus_code)
> + continue;
> + if (!unicam_meta_formats[i].metadata_fmt)
> + continue;
> +
> + if (index == f->index) {
> + f->pixelformat = unicam_meta_formats[i].fourcc;
> + f->type = V4L2_BUF_TYPE_META_CAPTURE;
> + return 0;
> + }
> + index++;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int unicam_g_fmt_meta(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> +
> + f->fmt.meta = node->fmt.fmt.meta;
> +
> + return 0;
> +}
> +
> +static const struct unicam_format_info *
> +__unicam_try_fmt_meta(struct unicam_node *node, struct v4l2_meta_format *meta)
> +{
> + const struct unicam_format_info *fmtinfo;
> +
> + /*
> + * Default to the first format if the requested pixel format code isn't
> + * supported.
> + */
> + fmtinfo = unicam_find_format_by_fourcc(meta->dataformat,
> + UNICAM_SD_PAD_SOURCE_METADATA);
> + if (!fmtinfo) {
> + fmtinfo = &unicam_meta_formats[0];
> + meta->dataformat = fmtinfo->fourcc;
> + }
> +
> + unicam_calc_meta_size_bpl(node->dev, fmtinfo, meta);
> +
> + return fmtinfo;
> +}
> +
> +static int unicam_try_fmt_meta(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> +
> + __unicam_try_fmt_vid(node, &f->fmt.pix);
> + return 0;
> +}
> +
> +static int unicam_s_fmt_meta(struct file *file, void *priv,
> + struct v4l2_format *f)
> +{
> + struct unicam_node *node = video_drvdata(file);
> +
> + if (vb2_is_busy(&node->buffer_queue))
> + return -EBUSY;
> +
> + node->fmtinfo = __unicam_try_fmt_meta(node, &f->fmt.meta);
> + node->fmt = *f;
> +
> + return 0;
> +}
> +
> +static int unicam_enum_framesizes(struct file *file, void *fh,
> + struct v4l2_frmsizeenum *fsize)
> +{
> + struct unicam_node *node = video_drvdata(file);
> + int ret = -EINVAL;
> +
> + if (fsize->index > 0)
> + return ret;
> +
> + if (is_image_node(node)) {
> + if (!unicam_find_format_by_fourcc(fsize->pixel_format,
> + UNICAM_SD_PAD_SOURCE_IMAGE))
> + return ret;
> +
> + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
> + fsize->stepwise.min_width = UNICAM_IMAGE_MIN_WIDTH;
> + fsize->stepwise.max_width = UNICAM_IMAGE_MAX_WIDTH;
> + fsize->stepwise.step_width = 1;
> + fsize->stepwise.min_height = UNICAM_IMAGE_MIN_HEIGHT;
> + fsize->stepwise.max_height = UNICAM_IMAGE_MAX_HEIGHT;
> + fsize->stepwise.step_height = 1;
> + } else {
> + if (!unicam_find_format_by_fourcc(fsize->pixel_format,
> + UNICAM_SD_PAD_SOURCE_METADATA))
> + return ret;
> +
> + fsize->stepwise.min_width = UNICAM_META_MIN_WIDTH;
> + fsize->stepwise.max_width = UNICAM_META_MAX_WIDTH;
> + fsize->stepwise.step_width = 1;
> + fsize->stepwise.min_height = UNICAM_META_MIN_HEIGHT;
> + fsize->stepwise.max_height = UNICAM_META_MAX_HEIGHT;
> + fsize->stepwise.step_height = 1;
> + }
> +
> + return 0;
> +}
> +
> +static int unicam_log_status(struct file *file, void *fh)
> +{
> + struct unicam_node *node = video_drvdata(file);
> + struct unicam_device *unicam = node->dev;
> + u32 reg;
> +
> + /* status for sub devices */
> + v4l2_device_call_all(&unicam->v4l2_dev, 0, core, log_status);
> +
> + dev_info(unicam->dev, "-----Receiver status-----\n");
> + dev_info(unicam->dev, "V4L2 width/height: %ux%u\n",
> + node->fmt.fmt.pix.width, node->fmt.fmt.pix.height);
> + dev_info(unicam->dev, "Mediabus format: %08x\n",
> + node->fmtinfo->code);
> + dev_info(unicam->dev, "V4L2 format: %08x\n",
> + node->fmt.fmt.pix.pixelformat);
> + reg = unicam_reg_read(unicam, UNICAM_IPIPE);
> + dev_info(unicam->dev, "Unpacking/packing: %u / %u\n",
> + unicam_get_field(reg, UNICAM_PUM_MASK),
> + unicam_get_field(reg, UNICAM_PPM_MASK));
> + dev_info(unicam->dev, "----Live data----\n");
> + dev_info(unicam->dev, "Programmed stride: %4u\n",
> + unicam_reg_read(unicam, UNICAM_IBLS));
> + dev_info(unicam->dev, "Detected resolution: %ux%u\n",
> + unicam_reg_read(unicam, UNICAM_IHSTA),
> + unicam_reg_read(unicam, UNICAM_IVSTA));
> + dev_info(unicam->dev, "Write pointer: %08x\n",
> + unicam_reg_read(unicam, UNICAM_IBWP));
> +
> + return 0;
> +}
> +
> +static int unicam_subscribe_event(struct v4l2_fh *fh,
> + const struct v4l2_event_subscription *sub)
> +{
> + switch (sub->type) {
> + case V4L2_EVENT_FRAME_SYNC:
> + return v4l2_event_subscribe(fh, sub, 2, NULL);
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static const struct v4l2_ioctl_ops unicam_ioctl_ops = {
> + .vidioc_querycap = unicam_querycap,
> +
> + .vidioc_enum_fmt_vid_cap = unicam_enum_fmt_vid,
> + .vidioc_g_fmt_vid_cap = unicam_g_fmt_vid,
> + .vidioc_try_fmt_vid_cap = unicam_try_fmt_vid,
> + .vidioc_s_fmt_vid_cap = unicam_s_fmt_vid,
> +
> + .vidioc_enum_fmt_meta_cap = unicam_enum_fmt_meta,
> + .vidioc_g_fmt_meta_cap = unicam_g_fmt_meta,
> + .vidioc_try_fmt_meta_cap = unicam_try_fmt_meta,
> + .vidioc_s_fmt_meta_cap = unicam_s_fmt_meta,
> +
> + .vidioc_enum_framesizes = unicam_enum_framesizes,
> +
> + .vidioc_reqbufs = vb2_ioctl_reqbufs,
> + .vidioc_create_bufs = vb2_ioctl_create_bufs,
> + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
> + .vidioc_querybuf = vb2_ioctl_querybuf,
> + .vidioc_qbuf = vb2_ioctl_qbuf,
> + .vidioc_dqbuf = vb2_ioctl_dqbuf,
> + .vidioc_expbuf = vb2_ioctl_expbuf,
> + .vidioc_streamon = vb2_ioctl_streamon,
> + .vidioc_streamoff = vb2_ioctl_streamoff,
> +
> + .vidioc_log_status = unicam_log_status,
> + .vidioc_subscribe_event = unicam_subscribe_event,
> + .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
> +};
> +
> +/* unicam capture driver file operations */
> +static const struct v4l2_file_operations unicam_fops = {
> + .owner = THIS_MODULE,
> + .open = v4l2_fh_open,
> + .release = vb2_fop_release,
> + .poll = vb2_fop_poll,
> + .unlocked_ioctl = video_ioctl2,
> + .mmap = vb2_fop_mmap,
> +};
> +
> +static int unicam_video_link_validate(struct media_link *link)
> +{
> + struct video_device *vdev =
> + media_entity_to_video_device(link->sink->entity);
> + struct v4l2_subdev *sd =
> + media_entity_to_v4l2_subdev(link->source->entity);
> + struct unicam_node *node = video_get_drvdata(vdev);
> + const u32 pad = is_image_node(node) ? UNICAM_SD_PAD_SOURCE_IMAGE
> + : UNICAM_SD_PAD_SOURCE_METADATA;
> + const struct v4l2_mbus_framefmt *format;
> + struct v4l2_subdev_state *state;
> + int ret = 0;
> +
> + state = v4l2_subdev_lock_and_get_active_state(sd);
> +
> + format = v4l2_subdev_state_get_format(state, pad, 0);
> + if (!format) {
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + if (is_image_node(node)) {
> + const struct v4l2_pix_format *fmt = &node->fmt.fmt.pix;
> +
> + if (node->fmtinfo->code != format->code ||
> + fmt->height != format->height ||
> + fmt->width != format->width ||
> + fmt->field != format->field) {
> + dev_dbg(node->dev->dev,
> + "image: (%u x %u) 0x%08x %s != (%u x %u) 0x%08x %s\n",
> + fmt->width, fmt->height, node->fmtinfo->code,
> + v4l2_field_names[fmt->field],
> + format->width, format->height, format->code,
> + v4l2_field_names[format->field]);
> + ret = -EPIPE;
> + };
> + } else {
> + const struct v4l2_meta_format *fmt = &node->fmt.fmt.meta;
> +
> + if (node->fmtinfo->code != format->code ||
> + fmt->height != format->height ||
> + fmt->width != format->width) {
> + dev_dbg(node->dev->dev,
> + "meta: (%u x %u) 0x%04x != (%u x %u) 0x%04x\n",
> + fmt->width, fmt->height, node->fmtinfo->code,
> + format->width, format->height, format->code);
> + ret = -EPIPE;
> + };
> + }
> +
> +out:
> + v4l2_subdev_unlock_state(state);
> + return ret;
> +}
> +
> +static const struct media_entity_operations unicam_video_media_ops = {
> + .link_validate = unicam_video_link_validate,
> +};
> +
> +static void unicam_node_release(struct video_device *vdev)
> +{
> + struct unicam_node *node = video_get_drvdata(vdev);
> +
> + unicam_put(node->dev);
> +}
> +
> +static void unicam_set_default_format(struct unicam_node *node)
> +{
> + if (is_image_node(node)) {
> + struct v4l2_pix_format *fmt = &node->fmt.fmt.pix;
> +
> + node->fmtinfo = &unicam_image_formats[0];
> + node->fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
> +
> + v4l2_fill_pix_format(fmt, &unicam_default_image_format);
> + fmt->pixelformat = node->fmtinfo->fourcc;
> + unicam_calc_image_size_bpl(node->dev, node->fmtinfo, fmt);
> + } else {
> + struct v4l2_meta_format *fmt = &node->fmt.fmt.meta;
> +
> + node->fmtinfo = &unicam_meta_formats[0];
> + node->fmt.type = V4L2_BUF_TYPE_META_CAPTURE;
> +
> + fmt->dataformat = node->fmtinfo->fourcc;
> + fmt->width = unicam_default_meta_format.width;
> + fmt->height = unicam_default_meta_format.height;
> + unicam_calc_meta_size_bpl(node->dev, node->fmtinfo, fmt);
> + }
> +}
> +
> +static int unicam_register_node(struct unicam_device *unicam,
> + enum unicam_node_type type)
> +{
> + const u32 pad_index = type == UNICAM_IMAGE_NODE
> + ? UNICAM_SD_PAD_SOURCE_IMAGE
> + : UNICAM_SD_PAD_SOURCE_METADATA;
> + struct unicam_node *node = &unicam->node[type];
> + struct video_device *vdev = &node->video_dev;
> + struct vb2_queue *q = &node->buffer_queue;
> + int ret;
> +
> + node->dev = unicam_get(unicam);
> + node->id = type;
> +
> + spin_lock_init(&node->dma_queue_lock);
> + mutex_init(&node->lock);
> +
> + INIT_LIST_HEAD(&node->dma_queue);
> +
> + /* Initialize the videobuf2 queue. */
> + q->type = type == UNICAM_IMAGE_NODE ? V4L2_BUF_TYPE_VIDEO_CAPTURE
> + : V4L2_BUF_TYPE_META_CAPTURE;
> + q->io_modes = VB2_MMAP | VB2_DMABUF;
> + q->drv_priv = node;
> + q->ops = &unicam_video_qops;
> + q->mem_ops = &vb2_dma_contig_memops;
> + q->buf_struct_size = sizeof(struct unicam_buffer);
> + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> + q->lock = &node->lock;
> + q->min_queued_buffers = 1;
> + q->dev = unicam->dev;
> +
> + ret = vb2_queue_init(q);
> + if (ret) {
> + dev_err(unicam->dev, "vb2_queue_init() failed\n");
> + goto err_unicam_put;
> + }
> +
> + /* Initialize the video device. */
> + vdev->release = unicam_node_release;
> + vdev->fops = &unicam_fops;
> + vdev->ioctl_ops = &unicam_ioctl_ops;
> + vdev->v4l2_dev = &unicam->v4l2_dev;
> + vdev->vfl_dir = VFL_DIR_RX;
> + vdev->queue = q;
> + vdev->lock = &node->lock;
> + vdev->device_caps = type == UNICAM_IMAGE_NODE
> + ? V4L2_CAP_VIDEO_CAPTURE : V4L2_CAP_META_CAPTURE;
> + vdev->device_caps |= V4L2_CAP_STREAMING | V4L2_CAP_IO_MC;
> + vdev->entity.ops = &unicam_video_media_ops;
> +
> + snprintf(vdev->name, sizeof(vdev->name), "%s-%s", UNICAM_MODULE_NAME,
> + type == UNICAM_IMAGE_NODE ? "image" : "embedded");
> +
> + video_set_drvdata(vdev, node);
> +
> + if (type == UNICAM_IMAGE_NODE)
> + vdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;
> +
> + node->pad.flags = MEDIA_PAD_FL_SINK;
> +
> + ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
> + if (ret)
> + goto err_unicam_put;
> +
> + node->dummy_buf.size = UNICAM_DUMMY_BUF_SIZE;
> + node->dummy_buf_cpu_addr = dma_alloc_coherent(unicam->dev,
> + node->dummy_buf.size,
> + &node->dummy_buf.dma_addr,
> + GFP_KERNEL);
> + if (!node->dummy_buf_cpu_addr) {
> + dev_err(unicam->dev, "Unable to allocate dummy buffer.\n");
> + ret = -ENOMEM;
> + goto err_entity_cleanup;
> + }
> +
> + unicam_set_default_format(node);
> +
> + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
> + if (ret) {
> + dev_err(unicam->dev, "Unable to register video device %s\n",
> + vdev->name);
> + goto err_dma_free;
> + }
> +
> + node->registered = true;
> +
> + ret = media_create_pad_link(&unicam->subdev.sd.entity,
> + pad_index,
> + &node->video_dev.entity,
> + 0,
> + MEDIA_LNK_FL_ENABLED |
> + MEDIA_LNK_FL_IMMUTABLE);
> + if (ret) {
> + /*
> + * No need for cleanup, the caller will unregister the
> + * video device, which will drop the reference on the
> + * device and trigger the cleanup.
> + */
> + dev_err(unicam->dev, "Unable to create pad link for %s\n",
> + unicam->sensor.subdev->name);
> + return ret;
> + }
> +
> + return 0;
> +
> +err_dma_free:
> + dma_free_coherent(unicam->dev, node->dummy_buf.size,
> + node->dummy_buf_cpu_addr,
> + node->dummy_buf.dma_addr);
> +err_entity_cleanup:
> + media_entity_cleanup(&vdev->entity);
> +err_unicam_put:
> + unicam_put(unicam);
> + return ret;
> +}
> +
> +static void unicam_unregister_nodes(struct unicam_device *unicam)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
> + struct unicam_node *node = &unicam->node[i];
> +
> + if (node->dummy_buf_cpu_addr)
> + dma_free_coherent(unicam->dev, node->dummy_buf.size,
> + node->dummy_buf_cpu_addr,
> + node->dummy_buf.dma_addr);
> +
> + if (node->registered) {
> + video_unregister_device(&node->video_dev);
> + node->registered = false;
> + }
> + }
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * Power management
> + */
> +
> +static int unicam_runtime_resume(struct device *dev)
> +{
> + struct unicam_device *unicam = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = clk_set_min_rate(unicam->vpu_clock, UNICAM_MIN_VPU_CLOCK_RATE);
> + if (ret) {
> + dev_err(unicam->dev, "failed to set up VPU clock\n");
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(unicam->vpu_clock);
> + if (ret) {
> + dev_err(unicam->dev, "Failed to enable VPU clock: %d\n", ret);
> + goto err_vpu_clock;
> + }
> +
> + ret = clk_set_rate(unicam->clock, 100 * 1000 * 1000);
> + if (ret) {
> + dev_err(unicam->dev, "failed to set up CSI clock\n");
> + goto err_vpu_prepare;
> + }
> +
> + ret = clk_prepare_enable(unicam->clock);
> + if (ret) {
> + dev_err(unicam->dev, "Failed to enable CSI clock: %d\n", ret);
> + goto err_vpu_prepare;
> + }
> +
> + return 0;
> +
> +err_vpu_prepare:
> + clk_disable_unprepare(unicam->vpu_clock);
> +err_vpu_clock:
> + if (clk_set_min_rate(unicam->vpu_clock, 0))
> + dev_err(unicam->dev, "failed to reset the VPU clock\n");
> +
> + return ret;
> +}
> +
> +static int unicam_runtime_suspend(struct device *dev)
> +{
> + struct unicam_device *unicam = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(unicam->clock);
> +
> + if (clk_set_min_rate(unicam->vpu_clock, 0))
> + dev_err(unicam->dev, "failed to reset the VPU clock\n");
> +
> + clk_disable_unprepare(unicam->vpu_clock);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops unicam_pm_ops = {
> + RUNTIME_PM_OPS(unicam_runtime_suspend, unicam_runtime_resume, NULL)
> +};
> +
> +/* -----------------------------------------------------------------------------
> + * V4L2 async notifier
> + */
> +
> +static int unicam_async_bound(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *subdev,
> + struct v4l2_async_connection *asc)
> +{
> + struct unicam_device *unicam = notifier_to_unicam_device(notifier);
> + struct media_pad *sink = &unicam->subdev.pads[UNICAM_SD_PAD_SINK];
> + struct media_pad *source;
> + int ret;
> +
> + dev_dbg(unicam->dev, "Using sensor %s for capture\n",
> + subdev->name);
> +
> + ret = v4l2_create_fwnode_links_to_pad(subdev, sink, MEDIA_LNK_FL_ENABLED |
> + MEDIA_LNK_FL_IMMUTABLE);
> + if (ret)
> + return ret;
> +
> + source = media_pad_remote_pad_unique(sink);
> + if (!source) {
> + dev_err(unicam->dev, "No connected sensor pad\n");
> + return -ENOTCONN;
> + }
> +
> + unicam->sensor.subdev = subdev;
> + unicam->sensor.pad = source;
> +
> + return 0;
> +}
> +
> +static int unicam_async_complete(struct v4l2_async_notifier *notifier)
> +{
> + struct unicam_device *unicam = notifier_to_unicam_device(notifier);
> + int ret;
> +
> + ret = unicam_register_node(unicam, UNICAM_IMAGE_NODE);
> + if (ret) {
> + dev_err(unicam->dev, "Unable to register image video device.\n");
> + goto unregister;
> + }
> +
> + ret = unicam_register_node(unicam, UNICAM_METADATA_NODE);
> + if (ret) {
> + dev_err(unicam->dev, "Unable to register metadata video device.\n");
> + goto unregister;
> + }
> +
> + ret = v4l2_device_register_subdev_nodes(&unicam->v4l2_dev);
> + if (ret) {
> + dev_err(unicam->dev, "Unable to register subdev nodes.\n");
> + goto unregister;
> + }
> +
> + return 0;
> +
> +unregister:
> + unicam_unregister_nodes(unicam);
> + unicam_put(unicam);
> +
> + return ret;
> +}
> +
> +static const struct v4l2_async_notifier_operations unicam_async_ops = {
> + .bound = unicam_async_bound,
> + .complete = unicam_async_complete,
> +};
> +
> +static int unicam_async_nf_init(struct unicam_device *unicam)
> +{
> + struct v4l2_fwnode_endpoint ep = { };
If the bus-type property is mandatory and you have no stated defaults
anywhere, this is fine. I.e. all the relevant properties would need to be
mandatory.
> + struct fwnode_handle *ep_handle;
> + struct v4l2_async_connection *asc;
> + int ret;
> +
> + ret = of_property_read_u32(unicam->dev->of_node, "brcm,num-data-lanes",
> + &unicam->max_data_lanes);
> + if (ret < 0) {
> + dev_err(unicam->dev, "Missing %s DT property\n",
> + "brcm,num-data-lanes");
> + return -EINVAL;
> + }
> +
> + /* Get and parse the local endpoint. */
> + ep_handle = fwnode_graph_get_endpoint_by_id(dev_fwnode(unicam->dev), 0, 0,
> + FWNODE_GRAPH_ENDPOINT_NEXT);
> + if (!ep_handle) {
> + dev_err(unicam->dev, "No endpoint found\n");
> + return -ENODEV;
> + }
> +
> + ret = v4l2_fwnode_endpoint_parse(ep_handle, &ep);
> + if (ret) {
> + dev_err(unicam->dev, "Failed to parse endpoint: %d\n", ret);
> + goto error;
> + }
> +
> + unicam->bus_type = ep.bus_type;
> +
> + switch (ep.bus_type) {
> + case V4L2_MBUS_CSI2_DPHY: {
> + unsigned int num_data_lanes = ep.bus.mipi_csi2.num_data_lanes;
> +
> + if (num_data_lanes != 1 && num_data_lanes != 2 &&
> + num_data_lanes != 4) {
> + dev_err(unicam->dev, "%u data lanes not supported\n",
> + num_data_lanes);
> + goto error;
> + }
> +
> + if (num_data_lanes > unicam->max_data_lanes) {
> + dev_err(unicam->dev,
> + "Endpoint uses %u data lanes when %u are supported\n",
> + num_data_lanes, unicam->max_data_lanes);
> + goto error;
> + }
> +
> + unicam->active_data_lanes = num_data_lanes;
> + unicam->bus_flags = ep.bus.mipi_csi2.flags;
> + break;
> + }
> +
> + case V4L2_MBUS_CCP2:
> + unicam->max_data_lanes = 1;
> + unicam->active_data_lanes = 1;
> + unicam->bus_flags = ep.bus.mipi_csi1.strobe;
> + break;
> +
> + default:
> + /* Unsupported bus type */
> + dev_err(unicam->dev, "Unsupported bus type %u\n", ep.bus_type);
> + goto error;
> + }
> +
> + /* Initialize and register the async notifier. */
> + v4l2_async_nf_init(&unicam->notifier, &unicam->v4l2_dev);
> +
> + asc = v4l2_async_nf_add_fwnode_remote(&unicam->notifier, ep_handle,
> + struct v4l2_async_connection);
> + fwnode_handle_put(ep_handle);
> + ep_handle = NULL;
> +
> + if (IS_ERR(asc)) {
> + ret = PTR_ERR(asc);
> + dev_err(unicam->dev, "Failed to add entry to notifier: %d\n",
> + ret);
> + goto error;
> + }
> +
> + unicam->notifier.ops = &unicam_async_ops;
> +
> + ret = v4l2_async_nf_register(&unicam->notifier);
> + if (ret) {
> + dev_err(unicam->dev, "Error registering device notifier: %d\n",
> + ret);
> + goto error;
> + }
> +
> + return 0;
> +
> +error:
> + fwnode_handle_put(ep_handle);
> + return ret;
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * Probe & remove
> + */
> +
> +static int unicam_media_init(struct unicam_device *unicam)
> +{
> + int ret;
> +
> + unicam->mdev.dev = unicam->dev;
> + strscpy(unicam->mdev.model, UNICAM_MODULE_NAME,
> + sizeof(unicam->mdev.model));
> + strscpy(unicam->mdev.serial, "", sizeof(unicam->mdev.serial));
Isn't the field already zeroed?
> + unicam->mdev.hw_revision = 0;
> +
> + media_device_init(&unicam->mdev);
> +
> + unicam->v4l2_dev.mdev = &unicam->mdev;
> +
> + ret = v4l2_device_register(unicam->dev, &unicam->v4l2_dev);
> + if (ret < 0) {
> + dev_err(unicam->dev, "Unable to register v4l2 device\n");
> + goto err_media_cleanup;
> + }
> +
> + ret = media_device_register(&unicam->mdev);
> + if (ret < 0) {
> + dev_err(unicam->dev,
> + "Unable to register media-controller device\n");
> + goto err_v4l2_unregister;
> + }
> +
> + return 0;
> +
> +err_v4l2_unregister:
> + v4l2_device_unregister(&unicam->v4l2_dev);
> +err_media_cleanup:
> + media_device_cleanup(&unicam->mdev);
> + return ret;
> +}
> +
> +static int unicam_probe(struct platform_device *pdev)
> +{
> + struct unicam_device *unicam;
> + int ret;
> +
> + unicam = kzalloc(sizeof(*unicam), GFP_KERNEL);
> + if (!unicam)
> + return -ENOMEM;
> +
> + kref_init(&unicam->kref);
> + unicam->dev = &pdev->dev;
> + platform_set_drvdata(pdev, unicam);
> +
> + unicam->base = devm_platform_ioremap_resource_byname(pdev, "unicam");
> + if (IS_ERR(unicam->base)) {
> + ret = PTR_ERR(unicam->base);
> + goto err_unicam_put;
> + }
> +
> + unicam->clk_gate_base = devm_platform_ioremap_resource_byname(pdev, "cmi");
> + if (IS_ERR(unicam->clk_gate_base)) {
> + ret = PTR_ERR(unicam->clk_gate_base);
> + goto err_unicam_put;
> + }
> +
> + unicam->clock = devm_clk_get(&pdev->dev, "lp");
> + if (IS_ERR(unicam->clock)) {
> + dev_err(unicam->dev, "Failed to get lp clock\n");
> + ret = PTR_ERR(unicam->clock);
> + goto err_unicam_put;
> + }
> +
> + unicam->vpu_clock = devm_clk_get(&pdev->dev, "vpu");
> + if (IS_ERR(unicam->vpu_clock)) {
> + dev_err(unicam->dev, "Failed to get vpu clock\n");
> + ret = PTR_ERR(unicam->vpu_clock);
> + goto err_unicam_put;
> + }
> +
> + ret = platform_get_irq(pdev, 0);
> + if (ret <= 0) {
> + dev_err(&pdev->dev, "No IRQ resource\n");
> + ret = -EINVAL;
> + goto err_unicam_put;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,
> + "unicam_capture0", unicam);
> + if (ret) {
> + dev_err(&pdev->dev, "Unable to request interrupt\n");
> + ret = -EINVAL;
> + goto err_unicam_put;
> + }
> +
> + /* Enable the block power domain. */
> + pm_runtime_enable(&pdev->dev);
> +
> + ret = unicam_media_init(unicam);
> + if (ret)
> + goto err_pm_runtime;
> +
> + ret = unicam_subdev_init(unicam);
> + if (ret)
> + goto err_media_unregister;
> +
> + ret = unicam_async_nf_init(unicam);
> + if (ret)
> + goto err_subdev_unregister;
> +
> + return 0;
> +
> +err_subdev_unregister:
> + unicam_subdev_cleanup(unicam);
> +err_media_unregister:
> + media_device_unregister(&unicam->mdev);
> +err_pm_runtime:
> + pm_runtime_disable(&pdev->dev);
> +err_unicam_put:
> + unicam_put(unicam);
> +
> + return ret;
> +}
> +
> +static int unicam_remove(struct platform_device *pdev)
> +{
> + struct unicam_device *unicam = platform_get_drvdata(pdev);
> +
> + unicam_unregister_nodes(unicam);
> + v4l2_device_unregister(&unicam->v4l2_dev);
> + media_device_unregister(&unicam->mdev);
> + v4l2_async_nf_unregister(&unicam->notifier);
> +
> + unicam_subdev_cleanup(unicam);
> +
> + unicam_put(unicam);
> +
> + pm_runtime_disable(&pdev->dev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id unicam_of_match[] = {
> + { .compatible = "brcm,bcm2835-unicam", },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, unicam_of_match);
> +
> +static struct platform_driver unicam_driver = {
> + .probe = unicam_probe,
> + .remove = unicam_remove,
> + .driver = {
> + .name = UNICAM_MODULE_NAME,
> + .pm = pm_ptr(&unicam_pm_ops),
> + .of_match_table = of_match_ptr(unicam_of_match),
> + },
> +};
> +
> +module_platform_driver(unicam_driver);
> +
> +MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com>");
> +MODULE_DESCRIPTION("BCM2835 Unicam driver");
> +MODULE_LICENSE("GPL");
--
Kind regards,
Sakari Ailus
^ permalink raw reply
* Re: [PATCH v6 1/2] driver core: Introduce device_link_wait_removal()
From: Greg Kroah-Hartman @ 2024-03-25 18:37 UTC (permalink / raw)
To: Herve Codina
Cc: Rafael J. Wysocki, Rob Herring, Frank Rowand, Saravana Kannan,
Lizhi Hou, Max Zhen, Sonal Santan, Stefano Stabellini,
Jonathan Cameron, linux-kernel, devicetree, Allan Nielsen,
Horatiu Vultur, Steen Hegelund, Luca Ceresoli, Nuno Sa,
Thomas Petazzoni, stable
In-Reply-To: <20240325152140.198219-2-herve.codina@bootlin.com>
On Mon, Mar 25, 2024 at 04:21:25PM +0100, Herve Codina wrote:
> The commit 80dd33cf72d1 ("drivers: base: Fix device link removal")
> introduces a workqueue to release the consumer and supplier devices used
> in the devlink.
> In the job queued, devices are release and in turn, when all the
> references to these devices are dropped, the release function of the
> device itself is called.
>
> Nothing is present to provide some synchronisation with this workqueue
> in order to ensure that all ongoing releasing operations are done and
> so, some other operations can be started safely.
>
> For instance, in the following sequence:
> 1) of_platform_depopulate()
> 2) of_overlay_remove()
>
> During the step 1, devices are released and related devlinks are removed
> (jobs pushed in the workqueue).
> During the step 2, OF nodes are destroyed but, without any
> synchronisation with devlink removal jobs, of_overlay_remove() can raise
> warnings related to missing of_node_put():
> ERROR: memory leak, expected refcount 1 instead of 2
>
> Indeed, the missing of_node_put() call is going to be done, too late,
> from the workqueue job execution.
>
> Introduce device_link_wait_removal() to offer a way to synchronize
> operations waiting for the end of devlink removals (i.e. end of
> workqueue jobs).
> Also, as a flushing operation is done on the workqueue, the workqueue
> used is moved from a system-wide workqueue to a local one.
>
> Cc: stable@vger.kernel.org
Why is this for stable? You are just adding a new api, no one is using
it.
Or if they are, you didn't send me that patch...
greg k-h
^ permalink raw reply
* Re: [PATCH v6 1/2] driver core: Introduce device_link_wait_removal()
From: Greg Kroah-Hartman @ 2024-03-25 18:38 UTC (permalink / raw)
To: Herve Codina
Cc: Rafael J. Wysocki, Rob Herring, Frank Rowand, Saravana Kannan,
Lizhi Hou, Max Zhen, Sonal Santan, Stefano Stabellini,
Jonathan Cameron, linux-kernel, devicetree, Allan Nielsen,
Horatiu Vultur, Steen Hegelund, Luca Ceresoli, Nuno Sa,
Thomas Petazzoni, stable
In-Reply-To: <20240325152140.198219-2-herve.codina@bootlin.com>
On Mon, Mar 25, 2024 at 04:21:25PM +0100, Herve Codina wrote:
> The commit 80dd33cf72d1 ("drivers: base: Fix device link removal")
> introduces a workqueue to release the consumer and supplier devices used
> in the devlink.
> In the job queued, devices are release and in turn, when all the
> references to these devices are dropped, the release function of the
> device itself is called.
>
> Nothing is present to provide some synchronisation with this workqueue
> in order to ensure that all ongoing releasing operations are done and
> so, some other operations can be started safely.
>
> For instance, in the following sequence:
> 1) of_platform_depopulate()
> 2) of_overlay_remove()
So this is only an issue for overlays? Why has no one noticed this in
the years since 80dd33cf72d1 was added? Why is this an issue now
suddenly?
thanks,
greg k-h
^ permalink raw reply
* Re: [PATCH v6 2/4] dt-bindings: media: add Maxim MAX96714 GMSL2 Deserializer
From: Conor Dooley @ 2024-03-25 18:41 UTC (permalink / raw)
To: Julien Massot
Cc: linux-media, devicetree, kernel, linux-kernel, mchehab, robh+dt,
krzysztof.kozlowski+dt, conor+dt, sakari.ailus
In-Reply-To: <20240325131634.165361-3-julien.massot@collabora.com>
[-- Attachment #1: Type: text/plain, Size: 411 bytes --]
On Mon, Mar 25, 2024 at 02:16:32PM +0100, Julien Massot wrote:
> Add DT bindings for Maxim MAX96714 GMSL2 Deserializer.
>
> Signed-off-by: Julien Massot <julien.massot@collabora.com>
> ---
> Change since v5:
> - Reverse the fallback MAX96714 can fallback to MAX96714F
> - Use const instead of enum for MAX96714F compatible
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: soc: mediatek: Add support for MT8188 VPPSYS
From: Conor Dooley @ 2024-03-25 18:55 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: linux-media, mchehab, robh, krzysztof.kozlowski+dt, conor+dt,
matthias.bgg, amergnat, moudy.ho, hverkuil-cisco,
sebastian.fricke, u.kleine-koenig, chunkuang.hu, p.zabel,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
kernel
In-Reply-To: <f90b2c8b-6eb3-46dc-abcc-600248218b4e@collabora.com>
[-- Attachment #1: Type: text/plain, Size: 1129 bytes --]
On Mon, Mar 25, 2024 at 09:23:58AM +0100, AngeloGioacchino Del Regno wrote:
> Il 22/03/24 18:42, Conor Dooley ha scritto:
> > On Fri, Mar 22, 2024 at 10:28:42AM +0100, AngeloGioacchino Del Regno wrote:
> > > Add compatible for MT8188 VPP mutex.
> > >
> > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >
> > You should at least mention the difference between this any anything
> > else.
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
>
> It's exactly always the same difference for MuteX blocks: different bits to
> activate mute for some IP ... but yeah, you're right, I'll shoot a word about
> this in the commit description on v2 (waiting a bit before doing that anyway).
Yah, I'm just pointing it out because it goes from an immediate ack to
having check the binding in-tree to see that this is an enum (although
that's due to the shitty looking diff that you can't avoid) and check
the driver patch to see that this is in fact a difference before
acking. I wouldn't bother sending a v2 if this was the only thing, seems
like a waste of your effort.
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^ permalink raw reply
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