* [PATCH v4 2/2] dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk
From: Christophe Roullier @ 2024-03-26 13:00 UTC (permalink / raw)
To: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Richard Cochran, Jose Abreu, Liam Girdwood,
Mark Brown, Christophe Roullier, Marek Vasut
Cc: netdev, devicetree, linux-stm32, linux-arm-kernel, linux-kernel
The Linux kernel dwmac-stm32 driver currently supports three DT
properties used to configure whether PHY clock are generated by
the MAC or supplied to the MAC from the PHY.
Originally there were two properties, st,eth-clk-sel and
st,eth-ref-clk-sel, each used to configure MAC clocking in
different bus mode and for different MAC clock frequency.
Since it is possible to determine the MAC 'eth-ck' clock
frequency from the clock subsystem and PHY bus mode from
the 'phy-mode' property, two disparate DT properties are
no longer required to configure MAC clocking.
Linux kernel commit 1bb694e20839 ("net: ethernet: stmmac: simplify phy modes management for stm32")
introduced a third, unified, property st,ext-phyclk. This property
covers both use cases of st,eth-clk-sel and st,eth-ref-clk-sel DT
properties, as well as a new use case for 25 MHz clock generated
by the MAC.
The third property st,ext-phyclk is so far undocumented,
document it.
Below table summarizes the clock requirement and clock sources for
supported PHY interface modes.
__________________________________________________________________________
|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125Mhz from PHY|
| | | 25MHz | 50MHz | |
---------------------------------------------------------------------------
| MII | - | eth-ck | n/a | n/a |
| | | st,ext-phyclk | | |
---------------------------------------------------------------------------
| GMII | - | eth-ck | n/a | n/a |
| | | st,ext-phyclk | | |
---------------------------------------------------------------------------
| RGMII | - | eth-ck | n/a | eth-ck |
| | | st,ext-phyclk | | st,eth-clk-sel or|
| | | | | st,ext-phyclk |
---------------------------------------------------------------------------
| RMII | - | eth-ck | eth-ck | n/a |
| | | st,ext-phyclk | st,eth-ref-clk-sel | |
| | | | or st,ext-phyclk | |
---------------------------------------------------------------------------
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index 80937b28fa046..529665d4fc911 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -85,6 +85,13 @@ properties:
phy-supply:
description: PHY regulator
+ st,ext-phyclk:
+ description:
+ set this property in RMII mode when you have PHY without crystal 50MHz and want to
+ select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
+ RCC clock instead of ETH_CLK125.
+ type: boolean
+
st,eth-clk-sel:
description:
set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
--
2.25.1
^ permalink raw reply related
* [PATCH v4 1/2] dt-bindings: net: add phy-supply property for stm32
From: Christophe Roullier @ 2024-03-26 12:58 UTC (permalink / raw)
To: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Richard Cochran, Jose Abreu, Liam Girdwood,
Mark Brown, Christophe Roullier, Marek Vasut
Cc: netdev, devicetree, linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20240326125849.226765-1-christophe.roullier@foss.st.com>
Phandle to a regulator that provides power to the PHY. This
regulator will be managed during the PHY power on/off sequence.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index fc8c96b08d7dc..80937b28fa046 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -82,6 +82,9 @@ properties:
Should be phandle/offset pair. The phandle to the syscon node which
encompases the glue register, and the offset of the control register
+ phy-supply:
+ description: PHY regulator
+
st,eth-clk-sel:
description:
set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
--
2.25.1
^ permalink raw reply related
* [PATCH v4 0/2] Add properties in dwmac-stm32 documentation
From: Christophe Roullier @ 2024-03-26 12:58 UTC (permalink / raw)
To: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Richard Cochran, Jose Abreu, Liam Girdwood,
Mark Brown, Christophe Roullier, Marek Vasut
Cc: netdev, devicetree, linux-stm32, linux-arm-kernel, linux-kernel
Introduce 2 new properties in dwmac-stm32 documentation
- phy-supply: to manage PHY regulator.
- st,ext-phyclk: is present since 2020 in driver so need to explain
it and avoid dtbs check issue : views/kernel/upstream/net-next/arch/arm/boot/dts/st/stm32mp157c-dk2.dtb:
ethernet@5800a000: Unevaluated properties are not allowed
('st,ext-phyclk' was unexpected)
Furthermore this property will be use in upstream of MP13 dwmac glue. (next step)
V2: - Drop deprecated: property for st,eth-clk-sel and st,eth-ref-clk-sel
V3: - Rework commit message
V4: - Fix syntax issue in commit message
Christophe Roullier (2):
dt-bindings: net: add phy-supply property for stm32
dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk
Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
--
2.25.1
^ permalink raw reply
* Re: [PATCH 2/3] dt-bindings: hsi: nokia-modem: convert to YAML
From: Sebastian Reichel @ 2024-03-26 13:00 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Tony Lindgren,
devicetree, linux-omap, linux-kernel
In-Reply-To: <58ec79cc-150e-4fef-bb4b-9d29901e9a04@linaro.org>
[-- Attachment #1: Type: text/plain, Size: 2161 bytes --]
Hi,
On Tue, Mar 26, 2024 at 08:21:05AM +0100, Krzysztof Kozlowski wrote:
> On 25/03/2024 22:45, Sebastian Reichel wrote:
> > Convert the legacy txt binding to modern YAML.
> > No semantic change.
> >
> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > ---
> > .../devicetree/bindings/hsi/nokia-modem.txt | 59 ------------
> > .../devicetree/bindings/hsi/nokia-modem.yaml | 101 +++++++++++++++++++++
> > 2 files changed, 101 insertions(+), 59 deletions(-)
> >
>
>
> > -};
> > diff --git a/Documentation/devicetree/bindings/hsi/nokia-modem.yaml b/Documentation/devicetree/bindings/hsi/nokia-modem.yaml
> > new file mode 100644
> > index 000000000000..c57cbcc7b722
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/hsi/nokia-modem.yaml
>
> Filename should match compatibles. nokia,n9-modem.yaml or nokia,modem.yaml
Ack, I will switch to nokia,modem.yaml in v2.
> > @@ -0,0 +1,101 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/hsi/nokia-modem.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Nokia modem
> > +
> > +maintainers:
> > + - Sebastian Reichel <sre@kernel.org>
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - nokia,n900-modem
> > + - nokia,n950-modem
> > + - nokia,n9-modem
> > +
>
> Aren't hsi-channel-ids related to hsi-channel-names? If so, they
> should be here with constraints.
Indeed. I forgot them, since they were not in the old binding :)
I will constraint them to min/max items 4 in v2.
> > + hsi-channel-names:
> > + items:
> > + - const: mcsaab-control
> > + - const: speech-control
> > + - const: speech-data
> > + - const: mcsaab-data
[...]
> > +examples:
> > + - |
> > + #include <dt-bindings/gpio/gpio.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + hsi-client {
>
> This should be "modem".
Ack.
>
> > + compatible = "nokia,n900-modem";
> > +
Thanks for the review,
-- Sebastian
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^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: hsi: hsi-client: convert to YAML
From: Krzysztof Kozlowski @ 2024-03-26 12:56 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Tony Lindgren,
devicetree, linux-omap, linux-kernel
In-Reply-To: <hz4fbdix5yaz2wtdkjkf23pc3m4kbeavynvjagundqvv3bisor@lc7dev4667i5>
On 26/03/2024 13:45, Sebastian Reichel wrote:
>
>> but more importantly: some properties are now excluding each
>> other.
>
> I think that requirement was already there.
Right.
...
>>> +
>>> +allOf:
>>> + - if:
>>> + required:
>>> + - hsi-mode
>>> + then:
>>> + properties:
>>> + hsi-rx-mode: false
>>> + hsi-tx-mode: false
>>
>> I don't understand what you are trying to achieve here and with anyOf.
>> It looks like just oneOf. OTOH, old binding did not exclude these
>> properties.
>
> So the anyOf ensures, that either hsi-mode or hsi-rx-mode +
> hsi-tx-mode are specified. Those properties were previously
Not entirely. anyOf should succeed also when none of them are present,
which is not what you want in such case.
> listed as required and they are indeed mandatory by the Linux
> kernel implementation.
>
> The old binding also has this:
>
> hsi-mode: May be used ***instead*** hsi-rx-mode and hsi-tx-mode
>
> So it's either hsi-rx-mode + hsi-tx-mode OR hsi-mode, but not
> all properties at the same time. That's what the allOf ensures:
> if hsi-mode is specified, then hsi-rx-mode and hsi-tx-mode may
> not be specified.
Then wouldn't this work for you:
https://elixir.bootlin.com/linux/v5.17-rc2/source/Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml#L91
?
But if you really want them to be optional but excluding, then simpler
syntax is:
https://lore.kernel.org/all/20230118163208.GA117919-robh@kernel.org/
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 4/4] virt: vmgenid: add support for devicetree bindings
From: Krzysztof Kozlowski @ 2024-03-26 12:53 UTC (permalink / raw)
To: kernel test robot, Sudan Landge, tytso, Jason, robh+dt,
krzysztof.kozlowski+dt, conor+dt, sathyanarayanan.kuppuswamy,
thomas.lendacky, dan.j.williams, devicetree, linux-kernel
Cc: oe-kbuild-all, graf, dwmw, bchalios, xmarcalx
In-Reply-To: <202403262047.aZVjmDY5-lkp@intel.com>
On 26/03/2024 13:48, kernel test robot wrote:
> Hi Sudan,
>
> kernel test robot noticed the following build errors:
...
> 134 ret = setup_vmgenid_state(state, remapped_ptr);
> 135 if (ret)
> 136 goto out;
> 137
> 138 state->irq = platform_get_irq(pdev, 0);
> 139 if (state->irq < 0) {
> 140 ret = state->irq;
> 141 goto out;
> 142 }
> 143 pdev->dev.driver_data = state;
> 144
> 145 ret = devm_request_irq(&pdev->dev, state->irq,
> 146 vmgenid_of_irq_handler,
> 147 IRQF_SHARED, "vmgenid", &pdev->dev);
> 148 if (ret)
> 149 pdev->dev.driver_data = NULL;
> 150
> 151 out:
> 152 return ret;
> 153 #else
> > 154 (void)dev;
So this code was not even built...
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 4/4] virt: vmgenid: add support for devicetree bindings
From: kernel test robot @ 2024-03-26 12:48 UTC (permalink / raw)
To: Sudan Landge, tytso, Jason, robh+dt, krzysztof.kozlowski+dt,
conor+dt, sathyanarayanan.kuppuswamy, thomas.lendacky,
dan.j.williams, devicetree, linux-kernel
Cc: oe-kbuild-all, graf, dwmw, bchalios, xmarcalx
In-Reply-To: <20240325195306.13133-5-sudanl@amazon.com>
Hi Sudan,
kernel test robot noticed the following build errors:
[auto build test ERROR on 8e938e39866920ddc266898e6ae1fffc5c8f51aa]
url: https://github.com/intel-lab-lkp/linux/commits/Sudan-Landge/virt-vmgenid-rearrange-code-to-make-review-easier/20240326-035657
base: 8e938e39866920ddc266898e6ae1fffc5c8f51aa
patch link: https://lore.kernel.org/r/20240325195306.13133-5-sudanl%40amazon.com
patch subject: [PATCH v3 4/4] virt: vmgenid: add support for devicetree bindings
config: x86_64-rhel-8.3-bpf (https://download.01.org/0day-ci/archive/20240326/202403262047.aZVjmDY5-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240326/202403262047.aZVjmDY5-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403262047.aZVjmDY5-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/virt/vmgenid.c: In function 'vmgenid_add_of':
>> drivers/virt/vmgenid.c:154:15: error: 'dev' undeclared (first use in this function); did you mean 'pdev'?
154 | (void)dev;
| ^~~
| pdev
drivers/virt/vmgenid.c:154:15: note: each undeclared identifier is reported only once for each function it appears in
vim +154 drivers/virt/vmgenid.c
121
122 static int vmgenid_add_of(struct platform_device *pdev, struct vmgenid_state *state)
123 {
124 #if IS_ENABLED(CONFIG_OF)
125 void __iomem *remapped_ptr;
126 int ret = 0;
127
128 remapped_ptr = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
129 if (IS_ERR(remapped_ptr)) {
130 ret = PTR_ERR(remapped_ptr);
131 goto out;
132 }
133
134 ret = setup_vmgenid_state(state, remapped_ptr);
135 if (ret)
136 goto out;
137
138 state->irq = platform_get_irq(pdev, 0);
139 if (state->irq < 0) {
140 ret = state->irq;
141 goto out;
142 }
143 pdev->dev.driver_data = state;
144
145 ret = devm_request_irq(&pdev->dev, state->irq,
146 vmgenid_of_irq_handler,
147 IRQF_SHARED, "vmgenid", &pdev->dev);
148 if (ret)
149 pdev->dev.driver_data = NULL;
150
151 out:
152 return ret;
153 #else
> 154 (void)dev;
155 (void)state;
156 return -EINVAL;
157 #endif
158 }
159
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: hsi: hsi-client: convert to YAML
From: Sebastian Reichel @ 2024-03-26 12:45 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Tony Lindgren,
devicetree, linux-omap, linux-kernel
In-Reply-To: <2905247d-03b0-45c1-add5-d3c2a986d87c@linaro.org>
[-- Attachment #1: Type: text/plain, Size: 4164 bytes --]
Hi,
On Tue, Mar 26, 2024 at 08:18:39AM +0100, Krzysztof Kozlowski wrote:
> On 25/03/2024 22:45, Sebastian Reichel wrote:
> > Convert the legacy txt binding to modern YAML and rename from
> > client-devices to hsi-client. No semantic change.
>
> There is semantic change: missing example (which is reasonable for
> shared schema)
Right, I should have mentioned that.
> but more importantly: some properties are now excluding each
> other.
I think that requirement was already there.
> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > ---
>
> ...
>
> > diff --git a/Documentation/devicetree/bindings/hsi/hsi-client.yaml b/Documentation/devicetree/bindings/hsi/hsi-client.yaml
> > new file mode 100644
> > index 000000000000..df6e1fdd2702
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/hsi/hsi-client.yaml
> > @@ -0,0 +1,84 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/hsi/hsi-client.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: HSI bus peripheral
> > +
> > +description:
> > + Each HSI port is supposed to have one child node, which
> > + symbols the remote device connected to the HSI port.
> > +
> > +maintainers:
> > + - Sebastian Reichel <sre@kernel.org>
> > +
> > +properties:
> > + $nodename:
> > + const: hsi-client
>
> Why? Does anything depend on this? It breaks generic-node-name rule. It
> seems you need it only to match the schema, but this just point to main
> problem - missing bus schema.
Ah, that's a good point. It makes a lot more sense to get the
nodename from the actual client. I will work this over.
> > +
> > + hsi-channel-ids:
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > + minItems: 1
> > + maxItems: 8
> > +
> > + hsi-channel-names:
> > + minItems: 1
> > + maxItems: 8
> > +
> > + hsi-rx-mode:
> > + enum: [stream, frame]
> > + description: Receiver Bit transmission mode
> > +
> > + hsi-tx-mode:
> > + enum: [stream, frame]
> > + description: Transmitter Bit transmission mode
> > +
> > + hsi-mode:
> > + enum: [stream, frame]
> > + description:
> > + May be used instead hsi-rx-mode and hsi-tx-mode if the
> > + transmission mode is the same for receiver and transmitter.
> > +
> > + hsi-speed-kbps:
> > + description: Max bit transmission speed in kbit/s
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + hsi-flow:
> > + enum: [synchronized, pipeline]
> > + description: RX flow type
> > +
> > + hsi-arb-mode:
> > + enum: [round-robin, priority]
> > + description: Arbitration mode for TX frame
> > +
> > +additionalProperties: true
> > +
> > +required:
> > + - compatible
> > + - hsi-channel-ids
> > + - hsi-speed-kbps
> > + - hsi-flow
> > + - hsi-arb-mode
> > +
> > +anyOf:
> > + - required:
> > + - hsi-mode
> > + - required:
> > + - hsi-rx-mode
> > + - hsi-tx-mode
> > +
> > +allOf:
> > + - if:
> > + required:
> > + - hsi-mode
> > + then:
> > + properties:
> > + hsi-rx-mode: false
> > + hsi-tx-mode: false
>
> I don't understand what you are trying to achieve here and with anyOf.
> It looks like just oneOf. OTOH, old binding did not exclude these
> properties.
So the anyOf ensures, that either hsi-mode or hsi-rx-mode +
hsi-tx-mode are specified. Those properties were previously
listed as required and they are indeed mandatory by the Linux
kernel implementation.
The old binding also has this:
hsi-mode: May be used ***instead*** hsi-rx-mode and hsi-tx-mode
So it's either hsi-rx-mode + hsi-tx-mode OR hsi-mode, but not
all properties at the same time. That's what the allOf ensures:
if hsi-mode is specified, then hsi-rx-mode and hsi-tx-mode may
not be specified.
> > + - if:
> > + required:
> > + - hsi-rx-mode
> > + then:
> > + properties:
> > + hsi-mode: false
> >
Thanks for the review,
-- Sebastian
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^ permalink raw reply
* Re: [PATCH v18 0/9] Add multiport support for DWC3 controllers
From: Johan Hovold @ 2024-03-26 12:37 UTC (permalink / raw)
To: Krishna Kurapati, Greg Kroah-Hartman
Cc: Krzysztof Kozlowski, Rob Herring, Bjorn Andersson, Wesley Cheng,
Konrad Dybcio, Conor Dooley, Thinh Nguyen, Felipe Balbi,
devicetree, linux-arm-msm, linux-usb, linux-kernel, quic_ppratap,
quic_jackp
In-Reply-To: <20240326113253.3010447-1-quic_kriskura@quicinc.com>
On Tue, Mar 26, 2024 at 05:02:44PM +0530, Krishna Kurapati wrote:
> Currently the DWC3 driver supports only single port controller which
> requires at most two PHYs ie HS and SS PHYs. There are SoCs that has
> DWC3 controller with multiple ports that can operate in host mode.
> Some of the port supports both SS+HS and other port supports only HS
> mode.
>
> This change primarily refactors the Phy logic in core driver to allow
> multiport support with Generic Phy's.
>
> Changes have been tested on QCOM SoC SA8295P which has 4 ports (2
> are HS+SS capable and 2 are HS only capable).
>
> This series depends on removal of ACPI from DWC3 QCOM wrapper [1].
> [1]: https://lore.kernel.org/all/20240305093216.3814787-1-quic_kriskura@quicinc.com/
Just to be clear, this dependency is already in 6.9-rc1 and this series
is ready to be merged.
> Krishna Kurapati (9):
> dt-bindings: usb: Add bindings for multiport properties on DWC3
> controller
> usb: dwc3: core: Access XHCI address space temporarily to read port
> info
> usb: dwc3: core: Skip setting event buffers for host only controllers
> usb: dwc3: core: Refactor PHY logic to support Multiport Controller
> dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport
> usb: dwc3: qcom: Add helper function to request wakeup interrupts
> usb: dwc3: qcom: Refactor IRQ handling in glue driver
> usb: dwc3: qcom: Enable wakeup for applicable ports of multiport
> usb: dwc3: qcom: Add multiport suspend/resume support for wrapper
Johan
^ permalink raw reply
* Re: [PATCH v3 2/3] clk: qcom: add IPQ9574 interconnect clocks support
From: Dmitry Baryshkov @ 2024-03-26 12:37 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
In-Reply-To: <20240326121312.1702701-3-quic_varada@quicinc.com>
On Tue, 26 Mar 2024 at 14:14, Varadarajan Narayanan
<quic_varada@quicinc.com> wrote:
>
> Unlike MSM platforms that manage NoC related clocks and scaling
> from RPM, IPQ SoCs dont involve RPM in managing NoC related
> clocks and there is no NoC scaling.
>
> However, there is a requirement to enable some NoC interface
> clocks for accessing the peripheral controllers present on
> these NoCs. Though exposing these as normal clocks would work,
> having a minimalistic interconnect driver to handle these clocks
> would make it consistent with other Qualcomm platforms resulting
> in common code paths. This is similar to msm8996-cbf's usage of
> icc-clk framework.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v3: Use indexed identifiers here to avoid confusion
> Fix error messages and move to common.c
> v2: Move DTS to separate patch
> Update commit log
> Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK to fix build error
> ---
> drivers/clk/qcom/Kconfig | 2 ++
> drivers/clk/qcom/common.c | 30 ++++++++++++++++
> drivers/clk/qcom/common.h | 2 ++
> drivers/clk/qcom/gcc-ipq9574.c | 64 +++++++++++++++++++++++++++++++++-
> 4 files changed, 97 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 8ab08e7b5b6c..af73a0b396eb 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -243,6 +243,8 @@ config IPQ_GCC_8074
>
> config IPQ_GCC_9574
> tristate "IPQ9574 Global Clock Controller"
> + select INTERCONNECT
> + select INTERCONNECT_CLK
> help
> Support for global clock controller on ipq9574 devices.
> Say Y if you want to use peripheral devices such as UART, SPI,
> diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
> index 75f09e6e057e..b18d38509de5 100644
> --- a/drivers/clk/qcom/common.c
> +++ b/drivers/clk/qcom/common.c
> @@ -8,6 +8,8 @@
> #include <linux/regmap.h>
> #include <linux/platform_device.h>
> #include <linux/clk-provider.h>
> +#include <linux/interconnect-clk.h>
> +#include <linux/interconnect-provider.h>
> #include <linux/reset-controller.h>
> #include <linux/of.h>
>
> @@ -337,4 +339,32 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
> }
> EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
>
> +int qcom_cc_icc_register(struct device *dev, struct clk_regmap *clks[],
> + int *noc_clks, int count, unsigned int first_id)
> +{
> + struct icc_provider *provider;
> + struct icc_clk_data *icd;
> + int i;
> +
> + icd = devm_kcalloc(dev, count, sizeof(*icd), GFP_KERNEL);
> + if (IS_ERR_OR_NULL(icd))
Can devm_kcalloc return ERR?
> + return dev_err_probe(dev, PTR_ERR(icd),
> + "malloc for clock data failed\n");
So, this becomes dev_err_prove(dev, 0, "..."). returning 0. Not the
expected result for the error case.
> +
> + for (i = 0; i < count; i++) {
> + icd[i].clk = clks[noc_clks[i]]->hw.clk;
> + if (IS_ERR_OR_NULL(icd[i].clk))
> + return dev_err_probe(dev, -ENOENT,
> + "%d clock not found\n", noc_clks[i]);
This is even better. Potential NULL pointer exception, then useless
ERR_OR_NULL and finally API abuse.
Please use clk_hw_get_clk(), it is there for you.
> + icd[i].name = clk_hw_get_name(&clks[noc_clks[i]]->hw);
> + }
> +
> + provider = icc_clk_register(dev, first_id, count, icd);
> + if (IS_ERR_OR_NULL(provider))
> + return dev_err_probe(dev, PTR_ERR(provider),
> + "icc_clk_register failed\n");
> +
> + return 0;
> +}
> +
> MODULE_LICENSE("GPL v2");
> diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
> index 9c8f7b798d9f..4fce5e229fc1 100644
> --- a/drivers/clk/qcom/common.h
> +++ b/drivers/clk/qcom/common.h
> @@ -65,5 +65,7 @@ extern int qcom_cc_probe(struct platform_device *pdev,
> const struct qcom_cc_desc *desc);
> extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
> const struct qcom_cc_desc *desc);
> +int qcom_cc_icc_register(struct device *dev, struct clk_regmap *clks[],
> + int *noc_clks, int count, unsigned int first_id);
Add this function to the qcom_cc_probe() call stream. Change it to
pass an array of clk_hw instead of passing indices.
>
> #endif
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> index 0a3f846695b8..c63c44b6740f 100644
> --- a/drivers/clk/qcom/gcc-ipq9574.c
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -12,6 +12,7 @@
>
> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> +#include <dt-bindings/interconnect/qcom,ipq9574.h>
>
> #include "clk-alpha-pll.h"
> #include "clk-branch.h"
> @@ -4301,6 +4302,56 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
> [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
> };
>
> +#define IPQ_APPS_ID 9574 /* some unique value */
> +
> +enum {
> + ICC_ANOC_PCIE0,
> + ICC_SNOC_PCIE0,
> + ICC_ANOC_PCIE1,
> + ICC_SNOC_PCIE1,
> + ICC_ANOC_PCIE2,
> + ICC_SNOC_PCIE2,
> + ICC_ANOC_PCIE3,
> + ICC_SNOC_PCIE3,
> + ICC_SNOC_USB,
> + ICC_ANOC_USB_AXI,
> + ICC_NSSNOC_NSSCC,
> + ICC_NSSNOC_SNOC_0,
> + ICC_NSSNOC_SNOC_1,
> + ICC_NSSNOC_PCNOC_1,
> + ICC_NSSNOC_QOSGEN_REF,
> + ICC_NSSNOC_TIMEOUT_REF,
> + ICC_NSSNOC_XO_DCD,
> + ICC_NSSNOC_ATB,
> + ICC_MEM_NOC_NSSNOC,
> + ICC_NSSNOC_MEMNOC,
> + ICC_NSSNOC_MEM_NOC_1,
> +};
> +
> +static int noc_clks[] = {
> + [ICC_ANOC_PCIE0] = GCC_ANOC_PCIE0_1LANE_M_CLK,
> + [ICC_SNOC_PCIE0] = GCC_SNOC_PCIE0_1LANE_S_CLK,
> + [ICC_ANOC_PCIE1] = GCC_ANOC_PCIE1_1LANE_M_CLK,
> + [ICC_SNOC_PCIE1] = GCC_SNOC_PCIE1_1LANE_S_CLK,
> + [ICC_ANOC_PCIE2] = GCC_ANOC_PCIE2_2LANE_M_CLK,
> + [ICC_SNOC_PCIE2] = GCC_SNOC_PCIE2_2LANE_S_CLK,
> + [ICC_ANOC_PCIE3] = GCC_ANOC_PCIE3_2LANE_M_CLK,
> + [ICC_SNOC_PCIE3] = GCC_SNOC_PCIE3_2LANE_S_CLK,
> + [ICC_SNOC_USB] = GCC_SNOC_USB_CLK,
> + [ICC_ANOC_USB_AXI] = GCC_ANOC_USB_AXI_CLK,
> + [ICC_NSSNOC_NSSCC] = GCC_NSSNOC_NSSCC_CLK,
> + [ICC_NSSNOC_SNOC_0] = GCC_NSSNOC_SNOC_CLK,
> + [ICC_NSSNOC_SNOC_1] = GCC_NSSNOC_SNOC_1_CLK,
> + [ICC_NSSNOC_PCNOC_1] = GCC_NSSNOC_PCNOC_1_CLK,
> + [ICC_NSSNOC_QOSGEN_REF] = GCC_NSSNOC_QOSGEN_REF_CLK,
> + [ICC_NSSNOC_TIMEOUT_REF] = GCC_NSSNOC_TIMEOUT_REF_CLK,
> + [ICC_NSSNOC_XO_DCD] = GCC_NSSNOC_XO_DCD_CLK,
> + [ICC_NSSNOC_ATB] = GCC_NSSNOC_ATB_CLK,
> + [ICC_MEM_NOC_NSSNOC] = GCC_MEM_NOC_NSSNOC_CLK,
> + [ICC_NSSNOC_MEMNOC] = GCC_NSSNOC_MEMNOC_CLK,
> + [ICC_NSSNOC_MEM_NOC_1] = GCC_NSSNOC_MEM_NOC_1_CLK,
> +};
> +
> static const struct of_device_id gcc_ipq9574_match_table[] = {
> { .compatible = "qcom,ipq9574-gcc" },
> { }
> @@ -4327,7 +4378,18 @@ static const struct qcom_cc_desc gcc_ipq9574_desc = {
>
> static int gcc_ipq9574_probe(struct platform_device *pdev)
> {
> - return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
> + int ret;
> +
> + ret = qcom_cc_probe(pdev, &gcc_ipq9574_desc);
> + if (ret)
> + return dev_err_probe(&pdev->dev, ret, "clock probe failed\n");
> +
> + ret = qcom_cc_icc_register(&pdev->dev, gcc_ipq9574_clks, noc_clks,
> + ARRAY_SIZE(noc_clks), IPQ_APPS_ID);
> + if (ret)
> + return dev_err_probe(&pdev->dev, ret, "interconnect register failed\n");
So, even if we had a useful message from the called function, it has
become overridden with the useless "failed" message. Please don't do
that.
> +
> + return 0;
> }
>
> static struct platform_driver gcc_ipq9574_driver = {
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH 2/4] arm64: dts: ti: k3-j721e-mcu: Add the MCU domain watchdog instances
From: Neha Malcom Francis @ 2024-03-26 12:27 UTC (permalink / raw)
To: robh, conor+dt, krzysztof.kozlowski+dt, vigneshr, nm
Cc: linux-arm-kernel, devicetree, linux-kernel, kristo, u-kumar1,
n-francis
In-Reply-To: <20240326122723.2329402-1-n-francis@ti.com>
There are 2 watchdog instances in the MCU domain. These instances are
coupled with the MCU domain R55 instances. Reserve them as they are not
used by A72.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
---
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index b0f41e9829cc..867f307909be 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -694,4 +694,30 @@ wkup_esm: esm@42080000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x42080000 0x00 0x1000>;
};
+
+ /*
+ * The 2 RTI instances are couple with MCU R5Fs so keeping them
+ * reserved as these will be used by their respective firmware
+ */
+ mcu_watchdog0: watchdog@40600000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x40600000 0x00 0x100>;
+ clocks = <&k3_clks 262 1>;
+ power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 262 1>;
+ assigned-clock-parents = <&k3_clks 262 5>;
+ /* reserved for MCU_R5F0_0 */
+ status = "reserved";
+ };
+
+ mcu_watchdog1: watchdog@40610000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x40610000 0x00 0x100>;
+ clocks = <&k3_clks 263 1>;
+ power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 263 1>;
+ assigned-clock-parents = <&k3_clks 263 5>;
+ /* reserved for MCU_R5F0_1 */
+ status = "reserved";
+ };
};
--
2.34.1
^ permalink raw reply related
* [PATCH 3/4] arm64: dts: ti: k3-j721e-main: Add the MAIN domain watchdog instances
From: Neha Malcom Francis @ 2024-03-26 12:27 UTC (permalink / raw)
To: robh, conor+dt, krzysztof.kozlowski+dt, vigneshr, nm
Cc: linux-arm-kernel, devicetree, linux-kernel, kristo, u-kumar1,
n-francis
In-Reply-To: <20240326122723.2329402-1-n-francis@ti.com>
There are 10 watchdog instances in the MAIN domain:
* one each for the 2 A72 cores
* one for the GPU core
* one for the C7x core
* one each for the 2 C66x cores
* one each for the 4 R5F cores
Currently, the devicetree only describes watchdog instances for the A72
cores and enables them. Describe the remaining but reserve them as they
will be used by their respective firmware.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 93 +++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index c7eafbc862f9..d8930b8ea8ec 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -2157,6 +2157,99 @@ watchdog1: watchdog@2210000 {
assigned-clock-parents = <&k3_clks 253 5>;
};
+ /*
+ * The following RTI instances are coupled with MCU R5Fs, c7x and
+ * GPU so keeping them reserved as these will be used by their
+ * respective firmware
+ */
+ watchdog2: watchdog@22f0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x22f0000 0x00 0x100>;
+ clocks = <&k3_clks 257 1>;
+ power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 257 1>;
+ assigned-clock-parents = <&k3_clks 257 5>;
+ /* reserved for GPU */
+ status = "reserved";
+ };
+
+ watchdog3: watchdog@2300000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2300000 0x00 0x100>;
+ clocks = <&k3_clks 256 1>;
+ power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 256 1>;
+ assigned-clock-parents = <&k3_clks 256 5>;
+ /* reserved for C7X */
+ status = "reserved";
+ };
+
+ watchdog4: watchdog@2380000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2380000 0x00 0x100>;
+ clocks = <&k3_clks 254 1>;
+ power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 254 1>;
+ assigned-clock-parents = <&k3_clks 254 5>;
+ /* reserved for C66X_0 */
+ status = "reserved";
+ };
+
+ watchdog5: watchdog@2390000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2390000 0x00 0x100>;
+ clocks = <&k3_clks 255 1>;
+ power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 255 1>;
+ assigned-clock-parents = <&k3_clks 255 5>;
+ /* reserved for C66X_1 */
+ status = "reserved";
+ };
+
+ watchdog6: watchdog@23c0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23c0000 0x00 0x100>;
+ clocks = <&k3_clks 258 1>;
+ power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 258 1>;
+ assigned-clock-parents = <&k3_clks 258 5>;
+ /* reserved for MAIN_R5F0_0 */
+ status = "reserved";
+ };
+
+ watchdog7: watchdog@23d0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23d0000 0x00 0x100>;
+ clocks = <&k3_clks 259 1>;
+ power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 259 1>;
+ assigned-clock-parents = <&k3_clks 259 5>;
+ /* reserved for MAIN_R5F0_1 */
+ status = "reserved";
+ };
+
+ watchdog8: watchdog@23e0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23e0000 0x00 0x100>;
+ clocks = <&k3_clks 260 1>;
+ power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 260 1>;
+ assigned-clock-parents = <&k3_clks 260 5>;
+ /* reserved for MAIN_R5F1_0 */
+ status = "reserved";
+ };
+
+ watchdog9: watchdog@23f0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23f0000 0x00 0x100>;
+ clocks = <&k3_clks 261 1>;
+ power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 261 1>;
+ assigned-clock-parents = <&k3_clks 261 5>;
+ /* reserved for MAIN_R5F1_1 */
+ status = "reserved";
+ };
+
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721e-r5fss";
ti,cluster-mode = <1>;
--
2.34.1
^ permalink raw reply related
* [PATCH 4/4] arm64: dts: ti: k3-j7200-main: Add the MAIN domain watchdog instances
From: Neha Malcom Francis @ 2024-03-26 12:27 UTC (permalink / raw)
To: robh, conor+dt, krzysztof.kozlowski+dt, vigneshr, nm
Cc: linux-arm-kernel, devicetree, linux-kernel, kristo, u-kumar1,
n-francis
In-Reply-To: <20240326122723.2329402-1-n-francis@ti.com>
There are 4 watchdog instances in the MAIN domain:
* one each for the 2 A72 cores
* one each for the 2 R5F cores
Currently, the devicetree only describes watchdog instances for the A72
cores and enables them. Describe the remaining but reserve them as they
will be used by their respective firmware.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 27 +++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 657f9cc9f4ea..c448c2218e23 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -1254,6 +1254,33 @@ watchdog1: watchdog@2210000 {
assigned-clock-parents = <&k3_clks 253 5>;
};
+ /*
+ * The following RTI instances are coupled with MCU R5Fs so
+ * keeping them reserved as these will be used by their respective
+ * firmware
+ */
+ watchdog2: watchdog@23c0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23c0000 0x00 0x100>;
+ clocks = <&k3_clks 258 1>;
+ power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 258 1>;
+ assigned-clock-parents = <&k3_clks 258 5>;
+ /* reserved for MAIN_R5F0_0 */
+ status = "reserved";
+ };
+
+ watchdog3: watchdog@23d0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23d0000 0x00 0x100>;
+ clocks = <&k3_clks 259 1>;
+ power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 259 1>;
+ assigned-clock-parents = <&k3_clks 259 5>;
+ /* reserved for MAIN_R5F0_1 */
+ status = "reserved";
+ };
+
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
--
2.34.1
^ permalink raw reply related
* [PATCH 0/4] arm64: dts: ti: k3-j7*: Add missing ESM and watchdog nodes
From: Neha Malcom Francis @ 2024-03-26 12:27 UTC (permalink / raw)
To: robh, conor+dt, krzysztof.kozlowski+dt, vigneshr, nm
Cc: linux-arm-kernel, devicetree, linux-kernel, kristo, u-kumar1,
n-francis
Add missing ESM and watchdog nodes for the sake of devicetree completion
of hardware description w.r.t Linux and ESM and WDT enablement on
U-Boot. This patch series adds the missing nodes for J721E and J7200.
Boot logs:
https://gist.github.com/nehamalcom/5dc94ab60f57df5d515d0a6d0da6e0d1
Neha Malcom Francis (4):
arm64: dts: ti: k3-j721e-mcu: Add the WKUP ESM instance
arm64: dts: ti: k3-j721e-mcu: Add the MCU domain watchdog instances
arm64: dts: ti: k3-j721e-main: Add the MAIN domain watchdog instances
arm64: dts: ti: k3-j7200-main: Add the MAIN domain watchdog instances
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 27 ++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 93 +++++++++++++++++++
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 31 +++++++
3 files changed, 151 insertions(+)
--
2.34.1
^ permalink raw reply
* [PATCH 1/4] arm64: dts: ti: k3-j721e-mcu: Add the WKUP ESM instance
From: Neha Malcom Francis @ 2024-03-26 12:27 UTC (permalink / raw)
To: robh, conor+dt, krzysztof.kozlowski+dt, vigneshr, nm
Cc: linux-arm-kernel, devicetree, linux-kernel, kristo, u-kumar1,
n-francis
In-Reply-To: <20240326122723.2329402-1-n-francis@ti.com>
Add the WKUP ESM instance for J721E. It has three instances in total,
one in the MAIN domain (main_esm) and two in the MCU-WKUP domain
(mcu_esm and wkup_esm).
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 4618b697fbc4..b0f41e9829cc 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -689,4 +689,9 @@ mcu_esm: esm@40800000 {
ti,esm-pins = <95>;
bootph-pre-ram;
};
+
+ wkup_esm: esm@42080000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x42080000 0x00 0x1000>;
+ };
};
--
2.34.1
^ permalink raw reply related
* Re: [PATCH] dt-bindings: ata: ahci-da850: Convert to dtschema
From: Damien Le Moal @ 2024-03-26 12:25 UTC (permalink / raw)
To: Animesh Agarwal
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-ide,
devicetree, linux-kernel
In-Reply-To: <20240326121735.11994-1-animeshagarwal28@gmail.com>
On 3/26/24 21:17, Animesh Agarwal wrote:
> Convert the ahci-da850 bindings to DT schema
Missing a period at the end of the sentence.
>
> Signed-off-by: Animesh Agarwal <animeshagarwal28@gmail.com>
> ---
> .../devicetree/bindings/ata/ahci-da850.txt | 18 ----------
> .../bindings/ata/ti,da850-ahci.yaml | 36 +++++++++++++++++++
> 2 files changed, 36 insertions(+), 18 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/ata/ahci-da850.txt
> create mode 100644 Documentation/devicetree/bindings/ata/ti,da850-ahci.yaml
>
> diff --git a/Documentation/devicetree/bindings/ata/ahci-da850.txt b/Documentation/devicetree/bindings/ata/ahci-da850.txt
> deleted file mode 100644
> index 5f8193417725..000000000000
> --- a/Documentation/devicetree/bindings/ata/ahci-da850.txt
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -Device tree binding for the TI DA850 AHCI SATA Controller
> ----------------------------------------------------------
> -
> -Required properties:
> - - compatible: must be "ti,da850-ahci"
> - - reg: physical base addresses and sizes of the two register regions
> - used by the controller: the register map as defined by the
> - AHCI 1.1 standard and the Power Down Control Register (PWRDN)
> - for enabling/disabling the SATA clock receiver
> - - interrupts: interrupt specifier (refer to the interrupt binding)
> -
> -Example:
> -
> - sata: sata@218000 {
> - compatible = "ti,da850-ahci";
> - reg = <0x218000 0x2000>, <0x22c018 0x4>;
> - interrupts = <67>;
> - };
> diff --git a/Documentation/devicetree/bindings/ata/ti,da850-ahci.yaml b/Documentation/devicetree/bindings/ata/ti,da850-ahci.yaml
> new file mode 100644
> index 000000000000..d54f58c12e78
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/ti,da850-ahci.yaml
> @@ -0,0 +1,36 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/ata/ti,da850-ahci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: TI DA850 AHCI SATA Controller
> +
> +maintainers:
> + - Animesh Agarwal <animeshagarwal28@gmail.com>
> +
> +properties:
> + compatible:
> + const: ti,da850-ahci
> +
> + reg:
> + minItems: 2
> + maxItems: 2
> +
> + interrupts:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + sata@218000 {
> + compatible = "ti,da850-ahci";
> + reg = <0x218000 0x2000>, <0x22c018 0x4>;
> + interrupts = <67>;
> + };
--
Damien Le Moal
Western Digital Research
^ permalink raw reply
* Re: [PATCH v5 1/3] dt-bindings: dmaengine: Add dmamux for CV18XX/SG200X series SoC
From: Inochi Amaoto @ 2024-03-26 12:19 UTC (permalink / raw)
To: Krzysztof Kozlowski, Inochi Amaoto, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chen Wang, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Jisheng Zhang, Liu Gui, Jingbao Qiu, dlan, dmaengine, devicetree,
linux-kernel, linux-riscv
In-Reply-To: <f7f6fcd8-5f49-4685-8488-9d51bb1210f5@linaro.org>
On Tue, Mar 26, 2024 at 01:14:12PM +0100, Krzysztof Kozlowski wrote:
> On 26/03/2024 13:06, Inochi Amaoto wrote:
> e.
> >>>> + regmap_set_bits(dmamux->regmap,
> >>>> + DMAMUX_CH_REG(chid),
> >>>> + DMAMUX_CH_SET(chid, devid));
> >>>> +
> >>>> + regmap_update_bits(dmamux->regmap, CV1800_SDMA_DMA_INT_MUX,
> >>>> + DMAMUX_INT_CH_MASK(chid, cpuid),
> >>>> + DMAMUX_INT_CH_BIT(chid, cpuid));
> >>>
> >>> I think this is.
> >>
> >> So where exactly? I don't see any define being used here.
> >> CV1800_SDMA_DMA_INT_MUX is not in your header. DMAMUX_ is not in your
> >> header. So what are you pointing?
> >>
> >> I don't understand this communication. Are you mocking me here or what?
> >> It's waste of my time.
> >>
> >
> > I apologize for my misunderstanding and your wasted time. I had
> > previously thought that hardware constants is also binding. This
> > leads to a weird communication between us. Since I agree and
> > understand this file is not a binding, I will remove this file in
> > the next version. Anyway, thanks for your kindly explanation.
>
> OK, no problem. When I asked where do you use header, it should make you
> think... remove the #include from the driver and everything still
> compiles, so obviously header is not being used.
>
> Best regards,
> Krzysztof
>
Thanks, I will think and do this for the future patch.
Regards,
Inochi
^ permalink raw reply
* [PATCH] dt-bindings: ata: ahci-da850: Convert to dtschema
From: Animesh Agarwal @ 2024-03-26 12:17 UTC (permalink / raw)
Cc: animeshagarwal28, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-ide, devicetree,
linux-kernel
Convert the ahci-da850 bindings to DT schema
Signed-off-by: Animesh Agarwal <animeshagarwal28@gmail.com>
---
.../devicetree/bindings/ata/ahci-da850.txt | 18 ----------
.../bindings/ata/ti,da850-ahci.yaml | 36 +++++++++++++++++++
2 files changed, 36 insertions(+), 18 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ata/ahci-da850.txt
create mode 100644 Documentation/devicetree/bindings/ata/ti,da850-ahci.yaml
diff --git a/Documentation/devicetree/bindings/ata/ahci-da850.txt b/Documentation/devicetree/bindings/ata/ahci-da850.txt
deleted file mode 100644
index 5f8193417725..000000000000
--- a/Documentation/devicetree/bindings/ata/ahci-da850.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Device tree binding for the TI DA850 AHCI SATA Controller
----------------------------------------------------------
-
-Required properties:
- - compatible: must be "ti,da850-ahci"
- - reg: physical base addresses and sizes of the two register regions
- used by the controller: the register map as defined by the
- AHCI 1.1 standard and the Power Down Control Register (PWRDN)
- for enabling/disabling the SATA clock receiver
- - interrupts: interrupt specifier (refer to the interrupt binding)
-
-Example:
-
- sata: sata@218000 {
- compatible = "ti,da850-ahci";
- reg = <0x218000 0x2000>, <0x22c018 0x4>;
- interrupts = <67>;
- };
diff --git a/Documentation/devicetree/bindings/ata/ti,da850-ahci.yaml b/Documentation/devicetree/bindings/ata/ti,da850-ahci.yaml
new file mode 100644
index 000000000000..d54f58c12e78
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ti,da850-ahci.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/ti,da850-ahci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI DA850 AHCI SATA Controller
+
+maintainers:
+ - Animesh Agarwal <animeshagarwal28@gmail.com>
+
+properties:
+ compatible:
+ const: ti,da850-ahci
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ sata@218000 {
+ compatible = "ti,da850-ahci";
+ reg = <0x218000 0x2000>, <0x22c018 0x4>;
+ interrupts = <67>;
+ };
--
2.44.0
^ permalink raw reply related
* Re: [PATCH v3 1/3] dt-bindings: interconnect: Add Qualcomm IPQ9574 support
From: Krzysztof Kozlowski @ 2024-03-26 12:14 UTC (permalink / raw)
To: Varadarajan Narayanan, andersson, konrad.dybcio, mturquette,
sboyd, robh, krzysztof.kozlowski+dt, conor+dt, djakov,
quic_anusha, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-pm
In-Reply-To: <20240326121312.1702701-2-quic_varada@quicinc.com>
On 26/03/2024 13:13, Varadarajan Narayanan wrote:
> Add interconnect-cells to clock provider so that it can be
> used as icc provider.
>
> Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
> interfaces. This will be used by the gcc-ipq9574 driver
> that will for providing interconnect services using the
> icc-clk framework.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v3:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 1/3] dt-bindings: dmaengine: Add dmamux for CV18XX/SG200X series SoC
From: Krzysztof Kozlowski @ 2024-03-26 12:14 UTC (permalink / raw)
To: Inochi Amaoto, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Jisheng Zhang, Liu Gui, Jingbao Qiu, dlan, dmaengine, devicetree,
linux-kernel, linux-riscv
In-Reply-To: <IA1PR20MB4953D3A70237A5395E61C170BB352@IA1PR20MB4953.namprd20.prod.outlook.com>
On 26/03/2024 13:06, Inochi Amaoto wrote:
e.
>>>> + regmap_set_bits(dmamux->regmap,
>>>> + DMAMUX_CH_REG(chid),
>>>> + DMAMUX_CH_SET(chid, devid));
>>>> +
>>>> + regmap_update_bits(dmamux->regmap, CV1800_SDMA_DMA_INT_MUX,
>>>> + DMAMUX_INT_CH_MASK(chid, cpuid),
>>>> + DMAMUX_INT_CH_BIT(chid, cpuid));
>>>
>>> I think this is.
>>
>> So where exactly? I don't see any define being used here.
>> CV1800_SDMA_DMA_INT_MUX is not in your header. DMAMUX_ is not in your
>> header. So what are you pointing?
>>
>> I don't understand this communication. Are you mocking me here or what?
>> It's waste of my time.
>>
>
> I apologize for my misunderstanding and your wasted time. I had
> previously thought that hardware constants is also binding. This
> leads to a weird communication between us. Since I agree and
> understand this file is not a binding, I will remove this file in
> the next version. Anyway, thanks for your kindly explanation.
OK, no problem. When I asked where do you use header, it should make you
think... remove the #include from the driver and everything still
compiles, so obviously header is not being used.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v3 3/3] arm64: dts: qcom: ipq9574: Add icc provider ability to gcc
From: Varadarajan Narayanan @ 2024-03-26 12:13 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan
In-Reply-To: <20240326121312.1702701-1-quic_varada@quicinc.com>
IPQ SoCs dont involve RPM in managing NoC related clocks and
there is no NoC scaling. Linux itself handles these clocks.
However, these should not be exposed as just clocks and align
with other Qualcomm SoCs that handle these clocks from a
interconnect provider.
Hence include icc provider capability to the gcc node so that
peripherals can use the interconnect facility to enable these
clocks.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Fix include file order
Move to separate patch
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 7f2e5cbf3bbb..5b3e69379b1f 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -306,6 +307,7 @@ gcc: clock-controller@1800000 {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ #interconnect-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v3 2/3] clk: qcom: add IPQ9574 interconnect clocks support
From: Varadarajan Narayanan @ 2024-03-26 12:13 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan
In-Reply-To: <20240326121312.1702701-1-quic_varada@quicinc.com>
Unlike MSM platforms that manage NoC related clocks and scaling
from RPM, IPQ SoCs dont involve RPM in managing NoC related
clocks and there is no NoC scaling.
However, there is a requirement to enable some NoC interface
clocks for accessing the peripheral controllers present on
these NoCs. Though exposing these as normal clocks would work,
having a minimalistic interconnect driver to handle these clocks
would make it consistent with other Qualcomm platforms resulting
in common code paths. This is similar to msm8996-cbf's usage of
icc-clk framework.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v3: Use indexed identifiers here to avoid confusion
Fix error messages and move to common.c
v2: Move DTS to separate patch
Update commit log
Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK to fix build error
---
drivers/clk/qcom/Kconfig | 2 ++
drivers/clk/qcom/common.c | 30 ++++++++++++++++
drivers/clk/qcom/common.h | 2 ++
drivers/clk/qcom/gcc-ipq9574.c | 64 +++++++++++++++++++++++++++++++++-
4 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8ab08e7b5b6c..af73a0b396eb 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -243,6 +243,8 @@ config IPQ_GCC_8074
config IPQ_GCC_9574
tristate "IPQ9574 Global Clock Controller"
+ select INTERCONNECT
+ select INTERCONNECT_CLK
help
Support for global clock controller on ipq9574 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 75f09e6e057e..b18d38509de5 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -8,6 +8,8 @@
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
+#include <linux/interconnect-clk.h>
+#include <linux/interconnect-provider.h>
#include <linux/reset-controller.h>
#include <linux/of.h>
@@ -337,4 +339,32 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
}
EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
+int qcom_cc_icc_register(struct device *dev, struct clk_regmap *clks[],
+ int *noc_clks, int count, unsigned int first_id)
+{
+ struct icc_provider *provider;
+ struct icc_clk_data *icd;
+ int i;
+
+ icd = devm_kcalloc(dev, count, sizeof(*icd), GFP_KERNEL);
+ if (IS_ERR_OR_NULL(icd))
+ return dev_err_probe(dev, PTR_ERR(icd),
+ "malloc for clock data failed\n");
+
+ for (i = 0; i < count; i++) {
+ icd[i].clk = clks[noc_clks[i]]->hw.clk;
+ if (IS_ERR_OR_NULL(icd[i].clk))
+ return dev_err_probe(dev, -ENOENT,
+ "%d clock not found\n", noc_clks[i]);
+ icd[i].name = clk_hw_get_name(&clks[noc_clks[i]]->hw);
+ }
+
+ provider = icc_clk_register(dev, first_id, count, icd);
+ if (IS_ERR_OR_NULL(provider))
+ return dev_err_probe(dev, PTR_ERR(provider),
+ "icc_clk_register failed\n");
+
+ return 0;
+}
+
MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 9c8f7b798d9f..4fce5e229fc1 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -65,5 +65,7 @@ extern int qcom_cc_probe(struct platform_device *pdev,
const struct qcom_cc_desc *desc);
extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
const struct qcom_cc_desc *desc);
+int qcom_cc_icc_register(struct device *dev, struct clk_regmap *clks[],
+ int *noc_clks, int count, unsigned int first_id);
#endif
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 0a3f846695b8..c63c44b6740f 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -12,6 +12,7 @@
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
@@ -4301,6 +4302,56 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
};
+#define IPQ_APPS_ID 9574 /* some unique value */
+
+enum {
+ ICC_ANOC_PCIE0,
+ ICC_SNOC_PCIE0,
+ ICC_ANOC_PCIE1,
+ ICC_SNOC_PCIE1,
+ ICC_ANOC_PCIE2,
+ ICC_SNOC_PCIE2,
+ ICC_ANOC_PCIE3,
+ ICC_SNOC_PCIE3,
+ ICC_SNOC_USB,
+ ICC_ANOC_USB_AXI,
+ ICC_NSSNOC_NSSCC,
+ ICC_NSSNOC_SNOC_0,
+ ICC_NSSNOC_SNOC_1,
+ ICC_NSSNOC_PCNOC_1,
+ ICC_NSSNOC_QOSGEN_REF,
+ ICC_NSSNOC_TIMEOUT_REF,
+ ICC_NSSNOC_XO_DCD,
+ ICC_NSSNOC_ATB,
+ ICC_MEM_NOC_NSSNOC,
+ ICC_NSSNOC_MEMNOC,
+ ICC_NSSNOC_MEM_NOC_1,
+};
+
+static int noc_clks[] = {
+ [ICC_ANOC_PCIE0] = GCC_ANOC_PCIE0_1LANE_M_CLK,
+ [ICC_SNOC_PCIE0] = GCC_SNOC_PCIE0_1LANE_S_CLK,
+ [ICC_ANOC_PCIE1] = GCC_ANOC_PCIE1_1LANE_M_CLK,
+ [ICC_SNOC_PCIE1] = GCC_SNOC_PCIE1_1LANE_S_CLK,
+ [ICC_ANOC_PCIE2] = GCC_ANOC_PCIE2_2LANE_M_CLK,
+ [ICC_SNOC_PCIE2] = GCC_SNOC_PCIE2_2LANE_S_CLK,
+ [ICC_ANOC_PCIE3] = GCC_ANOC_PCIE3_2LANE_M_CLK,
+ [ICC_SNOC_PCIE3] = GCC_SNOC_PCIE3_2LANE_S_CLK,
+ [ICC_SNOC_USB] = GCC_SNOC_USB_CLK,
+ [ICC_ANOC_USB_AXI] = GCC_ANOC_USB_AXI_CLK,
+ [ICC_NSSNOC_NSSCC] = GCC_NSSNOC_NSSCC_CLK,
+ [ICC_NSSNOC_SNOC_0] = GCC_NSSNOC_SNOC_CLK,
+ [ICC_NSSNOC_SNOC_1] = GCC_NSSNOC_SNOC_1_CLK,
+ [ICC_NSSNOC_PCNOC_1] = GCC_NSSNOC_PCNOC_1_CLK,
+ [ICC_NSSNOC_QOSGEN_REF] = GCC_NSSNOC_QOSGEN_REF_CLK,
+ [ICC_NSSNOC_TIMEOUT_REF] = GCC_NSSNOC_TIMEOUT_REF_CLK,
+ [ICC_NSSNOC_XO_DCD] = GCC_NSSNOC_XO_DCD_CLK,
+ [ICC_NSSNOC_ATB] = GCC_NSSNOC_ATB_CLK,
+ [ICC_MEM_NOC_NSSNOC] = GCC_MEM_NOC_NSSNOC_CLK,
+ [ICC_NSSNOC_MEMNOC] = GCC_NSSNOC_MEMNOC_CLK,
+ [ICC_NSSNOC_MEM_NOC_1] = GCC_NSSNOC_MEM_NOC_1_CLK,
+};
+
static const struct of_device_id gcc_ipq9574_match_table[] = {
{ .compatible = "qcom,ipq9574-gcc" },
{ }
@@ -4327,7 +4378,18 @@ static const struct qcom_cc_desc gcc_ipq9574_desc = {
static int gcc_ipq9574_probe(struct platform_device *pdev)
{
- return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
+ int ret;
+
+ ret = qcom_cc_probe(pdev, &gcc_ipq9574_desc);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "clock probe failed\n");
+
+ ret = qcom_cc_icc_register(&pdev->dev, gcc_ipq9574_clks, noc_clks,
+ ARRAY_SIZE(noc_clks), IPQ_APPS_ID);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "interconnect register failed\n");
+
+ return 0;
}
static struct platform_driver gcc_ipq9574_driver = {
--
2.34.1
^ permalink raw reply related
* [PATCH v3 1/3] dt-bindings: interconnect: Add Qualcomm IPQ9574 support
From: Varadarajan Narayanan @ 2024-03-26 12:13 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan
In-Reply-To: <20240326121312.1702701-1-quic_varada@quicinc.com>
Add interconnect-cells to clock provider so that it can be
used as icc provider.
Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
interfaces. This will be used by the gcc-ipq9574 driver
that will for providing interconnect services using the
icc-clk framework.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v3:
Squash Documentation/ and include/ changes into same patch
qcom,ipq9574.h
Move 'first id' to clock driver
---
.../bindings/clock/qcom,ipq9574-gcc.yaml | 3 +
.../dt-bindings/interconnect/qcom,ipq9574.h | 59 +++++++++++++++++++
2 files changed, 62 insertions(+)
create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
index 944a0ea79cd6..824781cbdf34 100644
--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
@@ -33,6 +33,9 @@ properties:
- description: PCIE30 PHY3 pipe clock source
- description: USB3 PHY pipe clock source
+ '#interconnect-cells':
+ const: 1
+
required:
- compatible
- clocks
diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
new file mode 100644
index 000000000000..9c95fbd5dc46
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef INTERCONNECT_QCOM_IPQ9574_H
+#define INTERCONNECT_QCOM_IPQ9574_H
+
+#define MASTER_ANOC_PCIE0_1 0
+#define SLAVE_ANOC_PCIE0_1 1
+#define MASTER_SNOC_PCIE0_1 2
+#define SLAVE_SNOC_PCIE0_1 3
+#define MASTER_ANOC_PCIE1_1 4
+#define SLAVE_ANOC_PCIE1_1 5
+#define MASTER_SNOC_PCIE1_1 6
+#define SLAVE_SNOC_PCIE1_1 7
+#define MASTER_ANOC_PCIE2_2 8
+#define SLAVE_ANOC_PCIE2_2 9
+#define MASTER_SNOC_PCIE2_2 10
+#define SLAVE_SNOC_PCIE2_2 11
+#define MASTER_ANOC_PCIE3_2 12
+#define SLAVE_ANOC_PCIE3_2 13
+#define MASTER_SNOC_PCIE3_2 14
+#define SLAVE_SNOC_PCIE3_2 15
+#define MASTER_USB 16
+#define SLAVE_USB 17
+#define MASTER_USB_AXI 18
+#define SLAVE_USB_AXI 19
+#define MASTER_NSSNOC_NSSCC 20
+#define SLAVE_NSSNOC_NSSCC 21
+#define MASTER_NSSNOC_SNOC 22
+#define SLAVE_NSSNOC_SNOC 23
+#define MASTER_NSSNOC_SNOC_1 24
+#define SLAVE_NSSNOC_SNOC_1 25
+#define MASTER_NSSNOC_PCNOC_1 26
+#define SLAVE_NSSNOC_PCNOC_1 27
+#define MASTER_NSSNOC_QOSGEN_REF 28
+#define SLAVE_NSSNOC_QOSGEN_REF 29
+#define MASTER_NSSNOC_TIMEOUT_REF 30
+#define SLAVE_NSSNOC_TIMEOUT_REF 31
+#define MASTER_NSSNOC_XO_DCD 32
+#define SLAVE_NSSNOC_XO_DCD 33
+#define MASTER_NSSNOC_ATB 34
+#define SLAVE_NSSNOC_ATB 35
+#define MASTER_MEM_NOC_NSSNOC 36
+#define SLAVE_MEM_NOC_NSSNOC 37
+#define MASTER_NSSNOC_MEMNOC 38
+#define SLAVE_NSSNOC_MEMNOC 39
+#define MASTER_NSSNOC_MEM_NOC_1 40
+#define SLAVE_NSSNOC_MEM_NOC_1 41
+
+#define MASTER_NSS_CC_NSSNOC_PPE 0
+#define SLAVE_NSS_CC_NSSNOC_PPE 1
+#define MASTER_NSS_CC_NSSNOC_PPE_CFG 2
+#define SLAVE_NSS_CC_NSSNOC_PPE_CFG 3
+#define MASTER_NSS_CC_NSSNOC_NSS_CSR 4
+#define SLAVE_NSS_CC_NSSNOC_NSS_CSR 5
+#define MASTER_NSS_CC_NSSNOC_IMEM_QSB 6
+#define SLAVE_NSS_CC_NSSNOC_IMEM_QSB 7
+#define MASTER_NSS_CC_NSSNOC_IMEM_AHB 8
+#define SLAVE_NSS_CC_NSSNOC_IMEM_AHB 9
+
+#endif /* INTERCONNECT_QCOM_IPQ9574_H */
--
2.34.1
^ permalink raw reply related
* [PATCH v3 0/3] Add interconnect driver for IPQ9574 SoC
From: Varadarajan Narayanan @ 2024-03-26 12:13 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan
MSM platforms manage NoC related clocks and scaling from RPM.
However, in IPQ SoCs, RPM is not involved in managing NoC
related clocks and there is no NoC scaling.
However, there is a requirement to enable some NoC interface
clocks for the accessing the peripherals present in the
system. Hence add a minimalistic interconnect driver that
establishes a path from the processor/memory to those peripherals
and vice versa.
---
v3:
qcom,ipq9574.h
Move 'first id' define to clock driver
gcc-ipq9574.c:
Use indexed identifiers here to avoid confusion
Fix error messages and move code to common.c as it can be
shared with future SoCs
v2:
qcom,ipq9574.h
Fix license identifier
Rename macros
qcom,ipq9574-gcc.yaml
Include interconnect-cells
gcc-ipq9574.c
Update commit log
Remove IS_ENABLED(CONFIG_INTERCONNECT) and auto select it from Kconfig
ipq9574.dtsi
Moved to separate patch
Include interconnect-cells to clock controller node
drivers/clk/qcom/Kconfig:
Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK
Varadarajan Narayanan (3):
dt-bindings: interconnect: Add Qualcomm IPQ9574 support
clk: qcom: add IPQ9574 interconnect clocks support
arm64: dts: qcom: ipq9574: Add icc provider ability to gcc
.../bindings/clock/qcom,ipq9574-gcc.yaml | 3 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 +
drivers/clk/qcom/Kconfig | 2 +
drivers/clk/qcom/common.c | 30 +++++++++
drivers/clk/qcom/common.h | 2 +
drivers/clk/qcom/gcc-ipq9574.c | 64 ++++++++++++++++++-
.../dt-bindings/interconnect/qcom,ipq9574.h | 59 +++++++++++++++++
7 files changed, 161 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
--
2.34.1
^ permalink raw reply
* [PATCH v2 2/2] ARM: dts: qcom: Add support for Motorola Moto G (2013)
From: Stanislav Jakubek @ 2024-03-26 12:11 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-arm-kernel, phone-devel,
linux-kernel
In-Reply-To: <32c507337ab80c550fb1df08f7014d1e31eb4c32.1711454680.git.stano.jakubek@gmail.com>
Add a device tree for the Motorola Moto G (2013) smartphone based
on the Qualcomm MSM8226 SoC.
Initially supported features:
- Buttons (Volume Down/Up, Power)
- eMMC
- Hall Effect Sensor
- SimpleFB display
- TMP108 temperature sensor
- Vibrator
Note: the dhob and shob reserved-memory regions are seemingly a part of some
Motorola specific (firmware?) mechanism, see [1].
[1] https://github.com/LineageOS/android_kernel_motorola_msm8226/blob/cm-14.1/Documentation/devicetree/bindings/misc/hob_ram.txt
Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com>
---
Changes in V2:
- split hob-ram reserved-memory region into dhob and shob
- add a note and a link to downstream documentation with more
information about these regions
arch/arm/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/msm8226-motorola-falcon.dts | 359 ++++++++++++++++++
2 files changed, 360 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts
diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile
index 6478a39b3be5..3eacbf5c0785 100644
--- a/arch/arm/boot/dts/qcom/Makefile
+++ b/arch/arm/boot/dts/qcom/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_QCOM) += \
+ msm8226-motorola-falcon.dtb \
qcom-apq8016-sbc.dtb \
qcom-apq8026-asus-sparrow.dtb \
qcom-apq8026-huawei-sturgeon.dtb \
diff --git a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts
new file mode 100644
index 000000000000..029e1b1659c9
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/dts-v1/;
+
+#include "qcom-msm8226.dtsi"
+#include "pm8226.dtsi"
+
+/delete-node/ &smem_region;
+
+/ {
+ model = "Motorola Moto G (2013)";
+ compatible = "motorola,falcon", "qcom,msm8226";
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &sdhc_1;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@3200000 {
+ compatible = "simple-framebuffer";
+ reg = <0x03200000 0x800000>;
+ width = <720>;
+ height = <1280>;
+ stride = <(720 * 3)>;
+ format = "r8g8b8";
+ vsp-supply = <®_lcd_pos>;
+ vsn-supply = <®_lcd_neg>;
+ vddio-supply = <&vddio_disp_vreg>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ event-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ };
+ };
+
+ vddio_disp_vreg: regulator-vddio-disp {
+ compatible = "regulator-fixed";
+ regulator-name = "vddio_disp";
+ gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&pm8226_l8>;
+ startup-delay-us = <300>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@3200000 {
+ reg = <0x03200000 0x800000>;
+ no-map;
+ };
+
+ dhob@f500000 {
+ reg = <0x0f500000 0x40000>;
+ no-map;
+ };
+
+ shob@f540000 {
+ reg = <0x0f540000 0x2000>;
+ no-map;
+ };
+
+ smem_region: smem@fa00000 {
+ reg = <0x0fa00000 0x100000>;
+ no-map;
+ };
+
+ /* Actually <0x0fa00000 0x500000>, but first 100000 is smem */
+ reserved@fb00000 {
+ reg = <0x0fb00000 0x400000>;
+ no-map;
+ };
+ };
+};
+
+&blsp1_i2c3 {
+ status = "okay";
+
+ regulator@3e {
+ compatible = "ti,tps65132";
+ reg = <0x3e>;
+ pinctrl-0 = <®_lcd_default>;
+ pinctrl-names = "default";
+
+ reg_lcd_pos: outp {
+ regulator-name = "outp";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ regulator-active-discharge = <1>;
+ regulator-boot-on;
+ enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_lcd_neg: outn {
+ regulator-name = "outn";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ regulator-active-discharge = <1>;
+ regulator-boot-on;
+ enable-gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ temperature-sensor@48 {
+ compatible = "ti,tmp108";
+ reg = <0x48>;
+ interrupts-extended = <&tlmm 13 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&temp_alert_default>;
+ pinctrl-names = "default";
+ #thermal-sensor-cells = <0>;
+ };
+};
+
+&pm8226_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&pm8226_vib {
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1337500>;
+ };
+
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ };
+
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ };
+
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ pm8226_lvs1: lvs1 {
+ regulator-always-on;
+ };
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ bus-width = <8>;
+ non-removable;
+
+ status = "okay";
+};
+
+&smbb {
+ qcom,fast-charge-safe-current = <2000000>;
+ qcom,fast-charge-current-limit = <1900000>;
+ qcom,fast-charge-safe-voltage = <4400000>;
+ qcom,minimum-input-voltage = <4300000>;
+
+ status = "okay";
+};
+
+&tlmm {
+ reg_lcd_default: reg-lcd-default-state {
+ pins = "gpio31", "gpio33";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+
+ reg_vddio_disp_default: reg-vddio-disp-default-state {
+ pins = "gpio34";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+
+ temp_alert_default: temp-alert-default-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-disable;
+ };
+};
+
+&usb {
+ extcon = <&smbb>;
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&smbb>;
+ v1p8-supply = <&pm8226_l10>;
+ v3p3-supply = <&pm8226_l20>;
+};
--
2.34.1
^ permalink raw reply related
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