* [PATCH v12 4/5] clk: sophgo: Add SG2042 clock driver
From: Chen Wang @ 2024-03-27 8:30 UTC (permalink / raw)
To: aou, chao.wei, conor, krzysztof.kozlowski+dt, mturquette, palmer,
paul.walmsley, richardcochran, robh+dt, sboyd, devicetree,
linux-clk, linux-kernel, linux-riscv, haijiao.liu, xiaoguang.xing,
guoren, jszhang, inochiama, samuel.holland
Cc: Chen Wang
In-Reply-To: <cover.1711527932.git.unicorn_wang@outlook.com>
From: Chen Wang <unicorn_wang@outlook.com>
Add a driver for the SOPHGO SG2042 clocks.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/sophgo/Kconfig | 7 +
drivers/clk/sophgo/Makefile | 2 +
drivers/clk/sophgo/clk-sophgo-sg2042.c | 1410 ++++++++++++++++++++++++
drivers/clk/sophgo/clk-sophgo-sg2042.h | 216 ++++
6 files changed, 1637 insertions(+)
create mode 100644 drivers/clk/sophgo/Kconfig
create mode 100644 drivers/clk/sophgo/Makefile
create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c
create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 50af5fc7f570..bc28502ec3c9 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -489,6 +489,7 @@ source "drivers/clk/rockchip/Kconfig"
source "drivers/clk/samsung/Kconfig"
source "drivers/clk/sifive/Kconfig"
source "drivers/clk/socfpga/Kconfig"
+source "drivers/clk/sophgo/Kconfig"
source "drivers/clk/sprd/Kconfig"
source "drivers/clk/starfive/Kconfig"
source "drivers/clk/sunxi/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 14fa8d4ecc1f..4abe16c8ccdf 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -118,6 +118,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
obj-$(CONFIG_CLK_SIFIVE) += sifive/
obj-y += socfpga/
+obj-y += sophgo/
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_ARCH_STI) += st/
diff --git a/drivers/clk/sophgo/Kconfig b/drivers/clk/sophgo/Kconfig
new file mode 100644
index 000000000000..2523818d64f9
--- /dev/null
+++ b/drivers/clk/sophgo/Kconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_SOPHGO_SG2042
+ bool "Sophgo SG2042 clock support"
+ depends on ARCH_SOPHGO || COMPILE_TEST
+ help
+ Say yes here to support the clock controller on the Sophgo SG2042 SoC.
diff --git a/drivers/clk/sophgo/Makefile b/drivers/clk/sophgo/Makefile
new file mode 100644
index 000000000000..13834cce260c
--- /dev/null
+++ b/drivers/clk/sophgo/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_SOPHGO_SG2042) += clk-sophgo-sg2042.o
diff --git a/drivers/clk/sophgo/clk-sophgo-sg2042.c b/drivers/clk/sophgo/clk-sophgo-sg2042.c
new file mode 100644
index 000000000000..a5648ff9f8d6
--- /dev/null
+++ b/drivers/clk/sophgo/clk-sophgo-sg2042.c
@@ -0,0 +1,1410 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Sophgo SG2042 Clock Generator Driver
+ *
+ * Copyright (C) 2024 Sophgo Technology Inc. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/iopoll.h>
+#include <linux/platform_device.h>
+
+/*
+ * The clock of SG2042 is composed of three parts.
+ * The registers of these three parts of the clock are scattered in three
+ * different memory address spaces:
+ * - pll clocks
+ * - gate clocks for RP subsystem
+ * - div/mux, and gate clocks working for other subsystem than RP subsystem
+ */
+#include <dt-bindings/clock/sophgo,sg2042-pll.h>
+#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
+#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
+
+#include "clk-sophgo-sg2042.h"
+
+#define KHZ 1000UL
+#define MHZ (KHZ * KHZ)
+
+#define REFDIV_MIN 1
+#define REFDIV_MAX 63
+#define FBDIV_MIN 16
+#define FBDIV_MAX 320
+
+#define PLL_FREF_SG2042 (25 * MHZ)
+
+#define PLL_FOUTPOSTDIV_MIN (16 * MHZ)
+#define PLL_FOUTPOSTDIV_MAX (3200 * MHZ)
+
+#define PLL_FOUTVCO_MIN (800 * MHZ)
+#define PLL_FOUTVCO_MAX (3200 * MHZ)
+
+struct sg2042_pll_ctrl {
+ unsigned long freq;
+ unsigned int fbdiv;
+ unsigned int postdiv1;
+ unsigned int postdiv2;
+ unsigned int refdiv;
+};
+
+#define PLLCTRL_FBDIV_SHIFT 16
+#define PLLCTRL_FBDIV_MASK (GENMASK(27, 16) >> PLLCTRL_FBDIV_SHIFT)
+#define PLLCTRL_POSTDIV2_SHIFT 12
+#define PLLCTRL_POSTDIV2_MASK (GENMASK(14, 12) >> PLLCTRL_POSTDIV2_SHIFT)
+#define PLLCTRL_POSTDIV1_SHIFT 8
+#define PLLCTRL_POSTDIV1_MASK (GENMASK(10, 8) >> PLLCTRL_POSTDIV1_SHIFT)
+#define PLLCTRL_REFDIV_SHIFT 0
+#define PLLCTRL_REFDIV_MASK (GENMASK(5, 0) >> PLLCTRL_REFDIV_SHIFT)
+
+static inline u32 sg2042_pll_ctrl_encode(struct sg2042_pll_ctrl *ctrl)
+{
+ return ((ctrl->fbdiv & PLLCTRL_FBDIV_MASK) << PLLCTRL_FBDIV_SHIFT) |
+ ((ctrl->postdiv2 & PLLCTRL_POSTDIV2_MASK) << PLLCTRL_POSTDIV2_SHIFT) |
+ ((ctrl->postdiv1 & PLLCTRL_POSTDIV1_MASK) << PLLCTRL_POSTDIV1_SHIFT) |
+ ((ctrl->refdiv & PLLCTRL_REFDIV_MASK) << PLLCTRL_REFDIV_SHIFT);
+}
+
+static inline void sg2042_pll_ctrl_decode(unsigned int reg_value,
+ struct sg2042_pll_ctrl *ctrl)
+{
+ ctrl->fbdiv = (reg_value >> PLLCTRL_FBDIV_SHIFT) & PLLCTRL_FBDIV_MASK;
+ ctrl->refdiv = (reg_value >> PLLCTRL_REFDIV_SHIFT) & PLLCTRL_REFDIV_MASK;
+ ctrl->postdiv1 = (reg_value >> PLLCTRL_POSTDIV1_SHIFT) & PLLCTRL_POSTDIV1_MASK;
+ ctrl->postdiv2 = (reg_value >> PLLCTRL_POSTDIV2_SHIFT) & PLLCTRL_POSTDIV2_MASK;
+}
+
+static inline int sg2042_pll_enable(struct sg2042_pll_clock *pll, bool en)
+{
+ unsigned int value = 0;
+
+ if (en) {
+ /* wait pll lock */
+ if (readl_poll_timeout_atomic(pll->base + pll->offset_status,
+ value,
+ ((value >> pll->shift_status_lock) & 0x1),
+ 0,
+ 100000))
+ pr_warn("%s not locked\n", pll->hw.init->name);
+
+ /* wait pll updating */
+ if (readl_poll_timeout_atomic(pll->base + pll->offset_status,
+ value,
+ !((value >> pll->shift_status_updating) & 0x1),
+ 0,
+ 100000))
+ pr_warn("%s still updating\n", pll->hw.init->name);
+
+ /* enable pll */
+ value = readl(pll->base + pll->offset_enable);
+ writel(value | (1 << pll->shift_enable), pll->base + pll->offset_enable);
+ } else {
+ /* disable pll */
+ value = readl(pll->base + pll->offset_enable);
+ writel(value & (~(1 << pll->shift_enable)), pll->base + pll->offset_enable);
+ }
+
+ return 0;
+}
+
+/*
+ * @reg_value: current register value
+ * @parent_rate: parent frequency
+ *
+ * This function is used to calculate below "rate" in equation
+ * rate = (parent_rate/REFDIV) x FBDIV/POSTDIV1/POSTDIV2
+ * = (parent_rate x FBDIV) / (REFDIV x POSTDIV1 x POSTDIV2)
+ */
+static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,
+ unsigned long parent_rate)
+{
+ struct sg2042_pll_ctrl ctrl_table;
+ u64 rate, numerator, denominator;
+
+ sg2042_pll_ctrl_decode(reg_value, &ctrl_table);
+
+ numerator = parent_rate * ctrl_table.fbdiv;
+ denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
+ do_div(numerator, denominator);
+ rate = numerator;
+
+ return rate;
+}
+
+/*
+ * Based on input rate/prate/fbdiv/refdiv, look up the postdiv1_2 table
+ * to get the closest postdiiv combination.
+ * postdiv1_2 contains all the possible combination lists of POSTDIV1 and POSTDIV2
+ * for example:
+ * postdiv1_2[0] = {2, 4, 8}, where div1 = 2, div2 = 4 , div1 * div2 = 8
+ *
+ * See TRM:
+ * FOUTPOSTDIV = FREF * FBDIV / REFDIV / (POSTDIV1 * POSTDIV2)
+ * So we get following formula to get POSTDIV1 and POSTDIV2:
+ * POSTDIV = (prate/REFDIV) x FBDIV/rate
+ * above POSTDIV = POSTDIV1*POSTDIV2
+ *
+ * @rate: FOUTPOSTDIV
+ * @prate: parent rate, i.e. FREF
+ * @fbdiv: FBDIV
+ * @refdiv: REFDIV
+ * @postdiv1: POSTDIV1, output
+ * @postdiv2: POSTDIV2, output
+ */
+static int sg2042_pll_get_postdiv_1_2(unsigned long rate,
+ unsigned long prate,
+ unsigned int fbdiv,
+ unsigned int refdiv,
+ unsigned int *postdiv1,
+ unsigned int *postdiv2)
+{
+ int index;
+ u64 tmp0;
+
+ /* POSTDIV_RESULT_INDEX point to 3rd element in the array postdiv1_2 */
+ #define POSTDIV_RESULT_INDEX 2
+
+ static int postdiv1_2[][3] = {
+ {2, 4, 8}, {3, 3, 9}, {2, 5, 10}, {2, 6, 12},
+ {2, 7, 14}, {3, 5, 15}, {4, 4, 16}, {3, 6, 18},
+ {4, 5, 20}, {3, 7, 21}, {4, 6, 24}, {5, 5, 25},
+ {4, 7, 28}, {5, 6, 30}, {5, 7, 35}, {6, 6, 36},
+ {6, 7, 42}, {7, 7, 49}
+ };
+
+ /* prate/REFDIV and result save to tmp0 */
+ tmp0 = prate;
+ do_div(tmp0, refdiv);
+
+ /* ((prate/REFDIV) x FBDIV) and result save to tmp0 */
+ tmp0 *= fbdiv;
+
+ /* ((prate/REFDIV) x FBDIV)/rate and result save to tmp0 */
+ do_div(tmp0, rate);
+
+ /* tmp0 is POSTDIV1*POSTDIV2, now we calculate div1 and div2 value */
+ if (tmp0 <= 7) {
+ /* (div1 * div2) <= 7, no need to use array search */
+ *postdiv1 = tmp0;
+ *postdiv2 = 1;
+ return 0;
+ }
+
+ /* (div1 * div2) > 7, use array search */
+ for (index = 0; index < ARRAY_SIZE(postdiv1_2); index++) {
+ if (tmp0 > postdiv1_2[index][POSTDIV_RESULT_INDEX]) {
+ continue;
+ } else {
+ /* found it */
+ *postdiv1 = postdiv1_2[index][1];
+ *postdiv2 = postdiv1_2[index][0];
+ return 0;
+ }
+ }
+ pr_warn("%s can not find in postdiv array!\n", __func__);
+ return -EINVAL;
+}
+
+/*
+ * Based on the given FOUTPISTDIV and the input FREF to calculate
+ * the REFDIV/FBDIV/PSTDIV1/POSTDIV2 combination for pllctrl register.
+ * @req_rate: expected output clock rate, i.e. FOUTPISTDIV
+ * @parent_rate: input parent clock rate, i.e. FREF
+ * @best: output to hold calculated combination of REFDIV/FBDIV/PSTDIV1/POSTDIV2
+ */
+static int sg2042_get_pll_ctl_setting(struct sg2042_pll_ctrl *best,
+ unsigned long req_rate,
+ unsigned long parent_rate)
+{
+ int ret;
+ unsigned int fbdiv, refdiv, postdiv1, postdiv2;
+ unsigned long foutpostdiv;
+ u64 tmp;
+ u64 foutvco;
+
+ if (parent_rate != PLL_FREF_SG2042) {
+ pr_err("INVALID FREF: %ld\n", parent_rate);
+ return -EINVAL;
+ }
+
+ if (req_rate < PLL_FOUTPOSTDIV_MIN || req_rate > PLL_FOUTPOSTDIV_MAX) {
+ pr_alert("INVALID FOUTPOSTDIV: %ld\n", req_rate);
+ return -EINVAL;
+ }
+
+ memset(best, 0, sizeof(struct sg2042_pll_ctrl));
+
+ for (refdiv = REFDIV_MIN; refdiv < REFDIV_MAX + 1; refdiv++) {
+ /* required by hardware: FREF/REFDIV must > 10 */
+ tmp = parent_rate;
+ do_div(tmp, refdiv);
+ if (tmp <= 10)
+ continue;
+
+ for (fbdiv = FBDIV_MIN; fbdiv < FBDIV_MAX + 1; fbdiv++) {
+ /*
+ * FOUTVCO = FREF*FBDIV/REFDIV validation
+ * required by hardware, FOUTVCO must [800MHz, 3200MHz]
+ */
+ foutvco = parent_rate * fbdiv;
+ do_div(foutvco, refdiv);
+ if (foutvco < PLL_FOUTVCO_MIN || foutvco > PLL_FOUTVCO_MAX)
+ continue;
+
+ ret = sg2042_pll_get_postdiv_1_2(req_rate, parent_rate,
+ fbdiv, refdiv,
+ &postdiv1, &postdiv2);
+ if (ret)
+ continue;
+
+ /*
+ * FOUTPOSTDIV = FREF*FBDIV/REFDIV/(POSTDIV1*POSTDIV2)
+ * = FOUTVCO/(POSTDIV1*POSTDIV2)
+ */
+ tmp = foutvco;
+ do_div(tmp, (postdiv1 * postdiv2));
+ foutpostdiv = (unsigned long)tmp;
+ /* Iterative to approach the expected value */
+ if (abs_diff(foutpostdiv, req_rate) < abs_diff(best->freq, req_rate)) {
+ best->freq = foutpostdiv;
+ best->refdiv = refdiv;
+ best->fbdiv = fbdiv;
+ best->postdiv1 = postdiv1;
+ best->postdiv2 = postdiv2;
+ if (foutpostdiv == req_rate)
+ return 0;
+ }
+ continue;
+ }
+ }
+
+ if (best->freq == 0)
+ return -EINVAL;
+ else
+ return 0;
+}
+
+/*
+ * @hw: ccf use to hook get sg2042_pll_clock
+ * @parent_rate: parent rate
+ *
+ * The is function will be called through clk_get_rate
+ * and return current rate after decoding reg value
+ */
+static unsigned long sg2042_clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ unsigned int value;
+ unsigned long rate;
+ struct sg2042_pll_clock *pll = to_sg2042_pll_clk(hw);
+
+ value = readl(pll->base + pll->offset_ctrl);
+ rate = sg2042_pll_recalc_rate(value, parent_rate);
+
+ pr_debug("--> %s: pll_recalc_rate: val = %ld\n",
+ clk_hw_get_name(hw), rate);
+ return rate;
+}
+
+static long sg2042_clk_pll_round_rate(struct clk_hw *hw,
+ unsigned long req_rate,
+ unsigned long *prate)
+{
+ unsigned int value;
+ struct sg2042_pll_ctrl pctrl_table;
+ long proper_rate;
+ int ret;
+
+ ret = sg2042_get_pll_ctl_setting(&pctrl_table, req_rate, *prate);
+ if (ret) {
+ proper_rate = 0;
+ goto out;
+ }
+
+ value = sg2042_pll_ctrl_encode(&pctrl_table);
+ proper_rate = (long)sg2042_pll_recalc_rate(value, *prate);
+
+out:
+ pr_debug("--> %s: pll_round_rate: val = %ld\n",
+ clk_hw_get_name(hw), proper_rate);
+ return proper_rate;
+}
+
+static int sg2042_clk_pll_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ req->rate = sg2042_clk_pll_round_rate(hw, min(req->rate, req->max_rate),
+ &req->best_parent_rate);
+ pr_debug("--> %s: pll_determine_rate: val = %ld\n",
+ clk_hw_get_name(hw), req->rate);
+ return 0;
+}
+
+static int sg2042_clk_pll_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ unsigned long flags;
+ unsigned int value;
+ int ret = 0;
+ struct sg2042_pll_ctrl pctrl_table;
+ struct sg2042_pll_clock *pll = to_sg2042_pll_clk(hw);
+
+ spin_lock_irqsave(pll->lock, flags);
+ if (sg2042_pll_enable(pll, 0)) {
+ pr_warn("Can't disable pll(%s), status error\n", pll->hw.init->name);
+ goto out;
+ }
+ ret = sg2042_get_pll_ctl_setting(&pctrl_table, rate, parent_rate);
+ if (ret) {
+ pr_warn("%s: Can't find a proper pll setting\n", pll->hw.init->name);
+ goto out2;
+ }
+
+ value = sg2042_pll_ctrl_encode(&pctrl_table);
+
+ /* write the value to top register */
+ writel(value, pll->base + pll->offset_ctrl);
+
+out2:
+ sg2042_pll_enable(pll, 1);
+out:
+ spin_unlock_irqrestore(pll->lock, flags);
+
+ pr_debug("--> %s: pll_set_rate: val = 0x%x\n",
+ clk_hw_get_name(hw), value);
+ return ret;
+}
+
+static const struct clk_ops sg2042_clk_pll_ops = {
+ .recalc_rate = sg2042_clk_pll_recalc_rate,
+ .round_rate = sg2042_clk_pll_round_rate,
+ .determine_rate = sg2042_clk_pll_determine_rate,
+ .set_rate = sg2042_clk_pll_set_rate,
+};
+
+static const struct clk_ops sg2042_clk_pll_ro_ops = {
+ .recalc_rate = sg2042_clk_pll_recalc_rate,
+ .round_rate = sg2042_clk_pll_round_rate,
+};
+
+static unsigned long sg2042_clk_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);
+ unsigned int val;
+ unsigned long ret_rate;
+
+ if (!(readl(divider->reg) & BIT(3))) {
+ val = (int)(divider->initval);
+ } else {
+ val = readl(divider->reg) >> divider->shift;
+ val &= clk_div_mask(divider->width);
+ }
+
+ ret_rate = divider_recalc_rate(hw, parent_rate, val, NULL,
+ divider->div_flags, divider->width);
+
+ pr_debug("--> %s: divider_recalc_rate: ret_rate = %ld\n",
+ clk_hw_get_name(hw), ret_rate);
+ return ret_rate;
+}
+
+static long sg2042_clk_divider_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
+{
+ int bestdiv;
+ unsigned long ret_rate;
+ struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);
+
+ /* if read only, just return current value */
+ if (divider->div_flags & CLK_DIVIDER_READ_ONLY) {
+ if (!(readl(divider->reg) & BIT(3))) {
+ bestdiv = (int)(divider->initval);
+ } else {
+ bestdiv = readl(divider->reg) >> divider->shift;
+ bestdiv &= clk_div_mask(divider->width);
+ }
+ ret_rate = DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
+ } else {
+ ret_rate = divider_round_rate(hw, rate, prate, NULL,
+ divider->width, divider->div_flags);
+ }
+
+ pr_debug("--> %s: divider_round_rate: val = %ld\n",
+ clk_hw_get_name(hw), ret_rate);
+ return ret_rate;
+}
+
+static int sg2042_clk_divider_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ unsigned int value;
+ unsigned int val, val2;
+ unsigned long flags = 0;
+ struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);
+
+ value = divider_get_val(rate, parent_rate, NULL,
+ divider->width, divider->div_flags);
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ /*
+ * The sequence of clock frequency modification is:
+ * Assert to reset divider.
+ * Modify the value of Clock Divide Factor (and High Wide if needed).
+ * De-assert to restore divided clock with new frequency.
+ */
+ val = readl(divider->reg);
+
+ /* assert */
+ val &= ~0x1;
+ writel(val, divider->reg);
+
+ if (divider->div_flags & CLK_DIVIDER_HIWORD_MASK) {
+ val = clk_div_mask(divider->width) << (divider->shift + 16);
+ } else {
+ val = readl(divider->reg);
+ val &= ~(clk_div_mask(divider->width) << divider->shift);
+ }
+ val |= value << divider->shift;
+ val |= 1 << 3;
+ writel(val, divider->reg);
+ val2 = val;
+
+ /* de-assert */
+ val |= 1;
+ writel(val, divider->reg);
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ pr_debug("--> %s: divider_set_rate: register val = 0x%x\n",
+ clk_hw_get_name(hw), val2);
+ return 0;
+}
+
+static const struct clk_ops sg2042_clk_divider_ops = {
+ .recalc_rate = sg2042_clk_divider_recalc_rate,
+ .round_rate = sg2042_clk_divider_round_rate,
+ .set_rate = sg2042_clk_divider_set_rate,
+};
+
+static const struct clk_ops sg2042_clk_divider_ro_ops = {
+ .recalc_rate = sg2042_clk_divider_recalc_rate,
+ .round_rate = sg2042_clk_divider_round_rate,
+};
+
+#define SG2042_PLL(_id, _name, _parent_name, _r_stat, _r_enable, _r_ctrl, _shift) \
+ { \
+ .hw.init = CLK_HW_INIT( \
+ _name, \
+ _parent_name, \
+ &sg2042_clk_pll_ops, \
+ CLK_GET_RATE_NOCACHE | CLK_GET_ACCURACY_NOCACHE),\
+ .id = _id, \
+ .offset_ctrl = _r_ctrl, \
+ .offset_status = _r_stat, \
+ .offset_enable = _r_enable, \
+ .shift_status_lock = 8 + (_shift), \
+ .shift_status_updating = _shift, \
+ .shift_enable = _shift, \
+ }
+
+#define SG2042_PLL_RO(_id, _name, _parent_name, _r_stat, _r_enable, _r_ctrl, _shift) \
+ { \
+ .hw.init = CLK_HW_INIT( \
+ _name, \
+ _parent_name, \
+ &sg2042_clk_pll_ro_ops, \
+ CLK_GET_RATE_NOCACHE | CLK_GET_ACCURACY_NOCACHE),\
+ .id = _id, \
+ .offset_ctrl = _r_ctrl, \
+ .offset_status = _r_stat, \
+ .offset_enable = _r_enable, \
+ .shift_status_lock = 8 + (_shift), \
+ .shift_status_updating = _shift, \
+ .shift_enable = _shift, \
+ }
+
+static struct sg2042_pll_clock sg2042_pll_clks[] = {
+ SG2042_PLL(MPLL_CLK, "mpll_clock", "cgi_main",
+ R_PLL_STAT, R_PLL_CLKEN_CONTROL, R_MPLL_CONTROL, 0),
+ SG2042_PLL_RO(FPLL_CLK, "fpll_clock", "cgi_main",
+ R_PLL_STAT, R_PLL_CLKEN_CONTROL, R_FPLL_CONTROL, 3),
+ SG2042_PLL_RO(DPLL0_CLK, "dpll0_clock", "cgi_dpll0",
+ R_PLL_STAT, R_PLL_CLKEN_CONTROL, R_DPLL0_CONTROL, 4),
+ SG2042_PLL_RO(DPLL1_CLK, "dpll1_clock", "cgi_dpll1",
+ R_PLL_STAT, R_PLL_CLKEN_CONTROL, R_DPLL1_CONTROL, 5),
+};
+
+#define SG2042_DIV(_id, _name, _parent_name, \
+ _r_ctrl, _shift, _width, \
+ _div_flag, _initval) { \
+ .hw.init = CLK_HW_INIT( \
+ _name, \
+ _parent_name, \
+ &sg2042_clk_divider_ops, \
+ 0), \
+ .id = _id, \
+ .offset_ctrl = _r_ctrl, \
+ .shift = _shift, \
+ .width = _width, \
+ .div_flags = _div_flag, \
+ .initval = _initval, \
+ }
+
+#define SG2042_DIV_RO(_id, _name, _parent_name, \
+ _r_ctrl, _shift, _width, \
+ _div_flag, _initval) { \
+ .hw.init = CLK_HW_INIT( \
+ _name, \
+ _parent_name, \
+ &sg2042_clk_divider_ro_ops, \
+ 0), \
+ .id = _id, \
+ .offset_ctrl = _r_ctrl, \
+ .shift = _shift, \
+ .width = _width, \
+ .div_flags = (_div_flag) | CLK_DIVIDER_READ_ONLY, \
+ .initval = _initval, \
+ }
+
+/*
+ * DIV items in the array are sorted according to the clock-tree diagram,
+ * from top to bottom, from upstream to downstream. Read TRM for details.
+ */
+#define DEF_DIVFLAG (CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO)
+static struct sg2042_divider_clock sg2042_div_clks[] = {
+ SG2042_DIV_RO(DIV_CLK_DPLL0_DDR01_0,
+ "clk_div_ddr01_0", "clk_gate_ddr01_div0",
+ R_CLKDIVREG27, 16, 5, DEF_DIVFLAG, 1),
+ SG2042_DIV_RO(DIV_CLK_FPLL_DDR01_1,
+ "clk_div_ddr01_1", "clk_gate_ddr01_div1",
+ R_CLKDIVREG28, 16, 5, DEF_DIVFLAG, 1),
+
+ SG2042_DIV_RO(DIV_CLK_DPLL1_DDR23_0,
+ "clk_div_ddr23_0", "clk_gate_ddr23_div0",
+ R_CLKDIVREG29, 16, 5, DEF_DIVFLAG, 1),
+ SG2042_DIV_RO(DIV_CLK_FPLL_DDR23_1,
+ "clk_div_ddr23_1", "clk_gate_ddr23_div1",
+ R_CLKDIVREG30, 16, 5, DEF_DIVFLAG, 1),
+
+ SG2042_DIV(DIV_CLK_MPLL_RP_CPU_NORMAL_0,
+ "clk_div_rp_cpu_normal_0", "clk_gate_rp_cpu_normal_div0",
+ R_CLKDIVREG0, 16, 5, DEF_DIVFLAG, 1),
+ SG2042_DIV(DIV_CLK_FPLL_RP_CPU_NORMAL_1,
+ "clk_div_rp_cpu_normal_1", "clk_gate_rp_cpu_normal_div1",
+ R_CLKDIVREG1, 16, 5, DEF_DIVFLAG, 1),
+
+ SG2042_DIV(DIV_CLK_MPLL_AXI_DDR_0,
+ "clk_div_axi_ddr_0", "clk_gate_axi_ddr_div0",
+ R_CLKDIVREG25, 16, 5, DEF_DIVFLAG, 2),
+ SG2042_DIV(DIV_CLK_FPLL_AXI_DDR_1,
+ "clk_div_axi_ddr_1", "clk_gate_axi_ddr_div1",
+ R_CLKDIVREG26, 16, 5, DEF_DIVFLAG, 1),
+
+ SG2042_DIV(DIV_CLK_FPLL_TOP_RP_CMN_DIV2,
+ "clk_div_top_rp_cmn_div2", "clk_mux_rp_cpu_normal",
+ R_CLKDIVREG3, 16, 16, DEF_DIVFLAG, 2),
+
+ SG2042_DIV(DIV_CLK_FPLL_50M_A53, "clk_div_50m_a53", "fpll_clock",
+ R_CLKDIVREG2, 16, 8, DEF_DIVFLAG, 20),
+ /* downstream of div_50m_a53 */
+ SG2042_DIV(DIV_CLK_FPLL_DIV_TIMER1, "clk_div_timer1", "clk_div_50m_a53",
+ R_CLKDIVREG6, 16, 16, DEF_DIVFLAG, 1),
+ SG2042_DIV(DIV_CLK_FPLL_DIV_TIMER2, "clk_div_timer2", "clk_div_50m_a53",
+ R_CLKDIVREG7, 16, 16, DEF_DIVFLAG, 1),
+ SG2042_DIV(DIV_CLK_FPLL_DIV_TIMER3, "clk_div_timer3", "clk_div_50m_a53",
+ R_CLKDIVREG8, 16, 16, DEF_DIVFLAG, 1),
+ SG2042_DIV(DIV_CLK_FPLL_DIV_TIMER4, "clk_div_timer4", "clk_div_50m_a53",
+ R_CLKDIVREG9, 16, 16, DEF_DIVFLAG, 1),
+ SG2042_DIV(DIV_CLK_FPLL_DIV_TIMER5, "clk_div_timer5", "clk_div_50m_a53",
+ R_CLKDIVREG10, 16, 16, DEF_DIVFLAG, 1),
+ SG2042_DIV(DIV_CLK_FPLL_DIV_TIMER6, "clk_div_timer6", "clk_div_50m_a53",
+ R_CLKDIVREG11, 16, 16, DEF_DIVFLAG, 1),
+ SG2042_DIV(DIV_CLK_FPLL_DIV_TIMER7, "clk_div_timer7", "clk_div_50m_a53",
+ R_CLKDIVREG12, 16, 16, DEF_DIVFLAG, 1),
+ SG2042_DIV(DIV_CLK_FPLL_DIV_TIMER8, "clk_div_timer8", "clk_div_50m_a53",
+ R_CLKDIVREG13, 16, 16, DEF_DIVFLAG, 1),
+
+ /*
+ * Set clk_div_uart_500m as RO, because the width of CLKDIVREG4 is too
+ * narrow for us to produce 115200. Use UART internal divider directly.
+ */
+ SG2042_DIV_RO(DIV_CLK_FPLL_UART_500M, "clk_div_uart_500m", "fpll_clock",
+ R_CLKDIVREG4, 16, 7, DEF_DIVFLAG, 2),
+ SG2042_DIV(DIV_CLK_FPLL_AHB_LPC, "clk_div_ahb_lpc", "fpll_clock",
+ R_CLKDIVREG5, 16, 16, DEF_DIVFLAG, 5),
+ SG2042_DIV(DIV_CLK_FPLL_EFUSE, "clk_div_efuse", "fpll_clock",
+ R_CLKDIVREG14, 16, 7, DEF_DIVFLAG, 40),
+ SG2042_DIV(DIV_CLK_FPLL_TX_ETH0, "clk_div_tx_eth0", "fpll_clock",
+ R_CLKDIVREG16, 16, 11, DEF_DIVFLAG, 8),
+ SG2042_DIV(DIV_CLK_FPLL_PTP_REF_I_ETH0,
+ "clk_div_ptp_ref_i_eth0", "fpll_clock",
+ R_CLKDIVREG17, 16, 8, DEF_DIVFLAG, 20),
+ SG2042_DIV(DIV_CLK_FPLL_REF_ETH0, "clk_div_ref_eth0", "fpll_clock",
+ R_CLKDIVREG18, 16, 8, DEF_DIVFLAG, 40),
+ SG2042_DIV(DIV_CLK_FPLL_EMMC, "clk_div_emmc", "fpll_clock",
+ R_CLKDIVREG19, 16, 5, DEF_DIVFLAG, 10),
+ SG2042_DIV(DIV_CLK_FPLL_SD, "clk_div_sd", "fpll_clock",
+ R_CLKDIVREG21, 16, 5, DEF_DIVFLAG, 10),
+
+ SG2042_DIV(DIV_CLK_FPLL_TOP_AXI0, "clk_div_top_axi0", "fpll_clock",
+ R_CLKDIVREG23, 16, 5, DEF_DIVFLAG, 10),
+ /* downstream of div_top_axi0 */
+ SG2042_DIV(DIV_CLK_FPLL_100K_EMMC, "clk_div_100k_emmc", "clk_div_top_axi0",
+ R_CLKDIVREG20, 16, 16, DEF_DIVFLAG, 1000),
+ SG2042_DIV(DIV_CLK_FPLL_100K_SD, "clk_div_100k_sd", "clk_div_top_axi0",
+ R_CLKDIVREG22, 16, 16, DEF_DIVFLAG, 1000),
+ SG2042_DIV(DIV_CLK_FPLL_GPIO_DB, "clk_div_gpio_db", "clk_div_top_axi0",
+ R_CLKDIVREG15, 16, 16, DEF_DIVFLAG, 1000),
+
+ SG2042_DIV(DIV_CLK_FPLL_TOP_AXI_HSPERI,
+ "clk_div_top_axi_hsperi", "fpll_clock",
+ R_CLKDIVREG24, 16, 5, DEF_DIVFLAG, 4),
+};
+
+#define SG2042_GATE(_id, _name, _parent_name, _flags, \
+ _r_enable, _bit_idx) { \
+ .hw.init = CLK_HW_INIT( \
+ _name, \
+ _parent_name, \
+ NULL, \
+ _flags), \
+ .id = _id, \
+ .offset_enable = _r_enable, \
+ .bit_idx = _bit_idx, \
+ }
+
+/*
+ * GATE items in the array are sorted according to the clock-tree diagram,
+ * from top to bottom, from upstream to downstream. Read TRM for details.
+ */
+
+/* Gate clocks which control registers are defined in CLOCK. */
+static const struct sg2042_gate_clock sg2042_gate_clks[] = {
+ SG2042_GATE(GATE_CLK_DDR01_DIV0, "clk_gate_ddr01_div0", "dpll0_clock",
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ R_CLKDIVREG27, 4),
+ SG2042_GATE(GATE_CLK_DDR01_DIV1, "clk_gate_ddr01_div1", "fpll_clock",
+ CLK_IS_CRITICAL,
+ R_CLKDIVREG28, 4),
+
+ SG2042_GATE(GATE_CLK_DDR23_DIV0, "clk_gate_ddr23_div0", "dpll1_clock",
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ R_CLKDIVREG29, 4),
+ SG2042_GATE(GATE_CLK_DDR23_DIV1, "clk_gate_ddr23_div1", "fpll_clock",
+ CLK_IS_CRITICAL,
+ R_CLKDIVREG30, 4),
+
+ SG2042_GATE(GATE_CLK_RP_CPU_NORMAL_DIV0, "clk_gate_rp_cpu_normal_div0", "mpll_clock",
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ R_CLKDIVREG0, 4),
+ SG2042_GATE(GATE_CLK_RP_CPU_NORMAL_DIV1,
+ "clk_gate_rp_cpu_normal_div1", "fpll_clock",
+ CLK_IS_CRITICAL,
+ R_CLKDIVREG1, 4),
+
+ SG2042_GATE(GATE_CLK_AXI_DDR_DIV0, "clk_gate_axi_ddr_div0", "mpll_clock",
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ R_CLKDIVREG25, 4),
+ SG2042_GATE(GATE_CLK_AXI_DDR_DIV1, "clk_gate_axi_ddr_div1", "fpll_clock",
+ CLK_IS_CRITICAL,
+ R_CLKDIVREG26, 4),
+
+ /* upon are gate clocks as input source for the muxes */
+
+ SG2042_GATE(GATE_CLK_DDR01, "clk_gate_ddr01", "clk_mux_ddr01",
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ R_CLKENREG1, 14),
+
+ SG2042_GATE(GATE_CLK_DDR23, "clk_gate_ddr23", "clk_mux_ddr23",
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ R_CLKENREG1, 15),
+
+ SG2042_GATE(GATE_CLK_RP_CPU_NORMAL,
+ "clk_gate_rp_cpu_normal", "clk_mux_rp_cpu_normal",
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ R_CLKENREG0, 0),
+
+ SG2042_GATE(GATE_CLK_AXI_DDR, "clk_gate_axi_ddr", "clk_mux_axi_ddr",
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ R_CLKENREG1, 13),
+
+ /* upon are gate clocks directly downstream of muxes */
+
+ /* downstream of clk_div_top_rp_cmn_div2 */
+ SG2042_GATE(GATE_CLK_TOP_RP_CMN_DIV2,
+ "clk_gate_top_rp_cmn_div2", "clk_div_top_rp_cmn_div2",
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, R_CLKENREG0, 2),
+ SG2042_GATE(GATE_CLK_HSDMA, "clk_gate_hsdma", "clk_gate_top_rp_cmn_div2",
+ CLK_SET_RATE_PARENT, R_CLKENREG1, 10),
+
+ /*
+ * downstream of clk_gate_rp_cpu_normal
+ *
+ * FIXME: there should be one 1/2 DIV between clk_gate_rp_cpu_normal
+ * and clk_gate_axi_pcie0/clk_gate_axi_pcie1.
+ * But the 1/2 DIV is fixed and no configurable register exported, so
+ * when reading from these two clocks, the rate value are still the
+ * same as that of clk_gate_rp_cpu_normal, it's not correct.
+ * This just affects the value read.
+ */
+ SG2042_GATE(GATE_CLK_AXI_PCIE0,
+ "clk_gate_axi_pcie0", "clk_gate_rp_cpu_normal",
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, R_CLKENREG1, 8),
+ SG2042_GATE(GATE_CLK_AXI_PCIE1,
+ "clk_gate_axi_pcie1", "clk_gate_rp_cpu_normal",
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, R_CLKENREG1, 9),
+
+ /* downstream of div_50m_a53 */
+ SG2042_GATE(GATE_CLK_A53_50M, "clk_gate_a53_50m", "clk_div_50m_a53",
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, R_CLKENREG0, 1),
+ SG2042_GATE(GATE_CLK_TIMER1, "clk_gate_timer1", "clk_div_timer1",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 12),
+ SG2042_GATE(GATE_CLK_TIMER2, "clk_gate_timer2", "clk_div_timer2",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 13),
+ SG2042_GATE(GATE_CLK_TIMER3, "clk_gate_timer3", "clk_div_timer3",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 14),
+ SG2042_GATE(GATE_CLK_TIMER4, "clk_gate_timer4", "clk_div_timer4",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 15),
+ SG2042_GATE(GATE_CLK_TIMER5, "clk_gate_timer5", "clk_div_timer5",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 16),
+ SG2042_GATE(GATE_CLK_TIMER6, "clk_gate_timer6", "clk_div_timer6",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 17),
+ SG2042_GATE(GATE_CLK_TIMER7, "clk_gate_timer7", "clk_div_timer7",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 18),
+ SG2042_GATE(GATE_CLK_TIMER8, "clk_gate_timer8", "clk_div_timer8",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 19),
+
+ /* gate clocks downstream from div clocks one-to-one */
+ SG2042_GATE(GATE_CLK_UART_500M, "clk_gate_uart_500m", "clk_div_uart_500m",
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, R_CLKENREG0, 4),
+ SG2042_GATE(GATE_CLK_AHB_LPC, "clk_gate_ahb_lpc", "clk_div_ahb_lpc",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 7),
+ SG2042_GATE(GATE_CLK_EFUSE, "clk_gate_efuse", "clk_div_efuse",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 20),
+ SG2042_GATE(GATE_CLK_TX_ETH0, "clk_gate_tx_eth0", "clk_div_tx_eth0",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 30),
+ SG2042_GATE(GATE_CLK_PTP_REF_I_ETH0,
+ "clk_gate_ptp_ref_i_eth0", "clk_div_ptp_ref_i_eth0",
+ CLK_SET_RATE_PARENT, R_CLKENREG1, 0),
+ SG2042_GATE(GATE_CLK_REF_ETH0, "clk_gate_ref_eth0", "clk_div_ref_eth0",
+ CLK_SET_RATE_PARENT, R_CLKENREG1, 1),
+ SG2042_GATE(GATE_CLK_EMMC_100M, "clk_gate_emmc", "clk_div_emmc",
+ CLK_SET_RATE_PARENT, R_CLKENREG1, 3),
+ SG2042_GATE(GATE_CLK_SD_100M, "clk_gate_sd", "clk_div_sd",
+ CLK_SET_RATE_PARENT, R_CLKENREG1, 6),
+
+ /* downstream of clk_div_top_axi0 */
+ SG2042_GATE(GATE_CLK_AHB_ROM, "clk_gate_ahb_rom", "clk_div_top_axi0",
+ 0, R_CLKENREG0, 8),
+ SG2042_GATE(GATE_CLK_AHB_SF, "clk_gate_ahb_sf", "clk_div_top_axi0",
+ 0, R_CLKENREG0, 9),
+ SG2042_GATE(GATE_CLK_AXI_SRAM, "clk_gate_axi_sram", "clk_div_top_axi0",
+ CLK_IGNORE_UNUSED, R_CLKENREG0, 10),
+ SG2042_GATE(GATE_CLK_APB_TIMER, "clk_gate_apb_timer", "clk_div_top_axi0",
+ CLK_IGNORE_UNUSED, R_CLKENREG0, 11),
+ SG2042_GATE(GATE_CLK_APB_EFUSE, "clk_gate_apb_efuse", "clk_div_top_axi0",
+ 0, R_CLKENREG0, 21),
+ SG2042_GATE(GATE_CLK_APB_GPIO, "clk_gate_apb_gpio", "clk_div_top_axi0",
+ 0, R_CLKENREG0, 22),
+ SG2042_GATE(GATE_CLK_APB_GPIO_INTR,
+ "clk_gate_apb_gpio_intr", "clk_div_top_axi0",
+ 0, R_CLKENREG0, 23),
+ SG2042_GATE(GATE_CLK_APB_I2C, "clk_gate_apb_i2c", "clk_div_top_axi0",
+ 0, R_CLKENREG0, 26),
+ SG2042_GATE(GATE_CLK_APB_WDT, "clk_gate_apb_wdt", "clk_div_top_axi0",
+ 0, R_CLKENREG0, 27),
+ SG2042_GATE(GATE_CLK_APB_PWM, "clk_gate_apb_pwm", "clk_div_top_axi0",
+ 0, R_CLKENREG0, 28),
+ SG2042_GATE(GATE_CLK_APB_RTC, "clk_gate_apb_rtc", "clk_div_top_axi0",
+ 0, R_CLKENREG0, 29),
+ SG2042_GATE(GATE_CLK_TOP_AXI0, "clk_gate_top_axi0", "clk_div_top_axi0",
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ R_CLKENREG1, 11),
+ /* downstream of DIV clocks which are sourced from clk_div_top_axi0 */
+ SG2042_GATE(GATE_CLK_GPIO_DB, "clk_gate_gpio_db", "clk_div_gpio_db",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 24),
+ SG2042_GATE(GATE_CLK_100K_EMMC, "clk_gate_100k_emmc", "clk_div_100k_emmc",
+ CLK_SET_RATE_PARENT, R_CLKENREG1, 4),
+ SG2042_GATE(GATE_CLK_100K_SD, "clk_gate_100k_sd", "clk_div_100k_sd",
+ CLK_SET_RATE_PARENT, R_CLKENREG1, 7),
+
+ /* downstream of clk_div_top_axi_hsperi */
+ SG2042_GATE(GATE_CLK_SYSDMA_AXI,
+ "clk_gate_sysdma_axi", "clk_div_top_axi_hsperi",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 3),
+ SG2042_GATE(GATE_CLK_APB_UART,
+ "clk_gate_apb_uart", "clk_div_top_axi_hsperi",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 5),
+ SG2042_GATE(GATE_CLK_AXI_DBG_I2C,
+ "clk_gate_axi_dbg_i2c", "clk_div_top_axi_hsperi",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 6),
+ SG2042_GATE(GATE_CLK_APB_SPI,
+ "clk_gate_apb_spi", "clk_div_top_axi_hsperi",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 25),
+ SG2042_GATE(GATE_CLK_AXI_ETH0,
+ "clk_gate_axi_eth0", "clk_div_top_axi_hsperi",
+ CLK_SET_RATE_PARENT, R_CLKENREG0, 31),
+ SG2042_GATE(GATE_CLK_AXI_EMMC,
+ "clk_gate_axi_emmc", "clk_div_top_axi_hsperi",
+ CLK_SET_RATE_PARENT, R_CLKENREG1, 2),
+ SG2042_GATE(GATE_CLK_AXI_SD,
+ "clk_gate_axi_sd", "clk_div_top_axi_hsperi",
+ CLK_SET_RATE_PARENT, R_CLKENREG1, 5),
+ SG2042_GATE(GATE_CLK_TOP_AXI_HSPERI,
+ "clk_gate_top_axi_hsperi", "clk_div_top_axi_hsperi",
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ R_CLKENREG1, 12),
+};
+
+/*
+ * Gate clocks for RP subsystem (including the MP subsystem), which control
+ * registers are defined in SYS_CTRL.
+ */
+static const struct sg2042_gate_clock sg2042_gate_rp[] = {
+ /* downstream of clk_gate_rp_cpu_normal about rxu */
+ SG2042_GATE(GATE_CLK_RXU0, "clk_gate_rxu0", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 0),
+ SG2042_GATE(GATE_CLK_RXU1, "clk_gate_rxu1", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 1),
+ SG2042_GATE(GATE_CLK_RXU2, "clk_gate_rxu2", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 2),
+ SG2042_GATE(GATE_CLK_RXU3, "clk_gate_rxu3", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 3),
+ SG2042_GATE(GATE_CLK_RXU4, "clk_gate_rxu4", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 4),
+ SG2042_GATE(GATE_CLK_RXU5, "clk_gate_rxu5", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 5),
+ SG2042_GATE(GATE_CLK_RXU6, "clk_gate_rxu6", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 6),
+ SG2042_GATE(GATE_CLK_RXU7, "clk_gate_rxu7", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 7),
+ SG2042_GATE(GATE_CLK_RXU8, "clk_gate_rxu8", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 8),
+ SG2042_GATE(GATE_CLK_RXU9, "clk_gate_rxu9", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 9),
+ SG2042_GATE(GATE_CLK_RXU10, "clk_gate_rxu10", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 10),
+ SG2042_GATE(GATE_CLK_RXU11, "clk_gate_rxu11", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 11),
+ SG2042_GATE(GATE_CLK_RXU12, "clk_gate_rxu12", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 12),
+ SG2042_GATE(GATE_CLK_RXU13, "clk_gate_rxu13", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 13),
+ SG2042_GATE(GATE_CLK_RXU14, "clk_gate_rxu14", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 14),
+ SG2042_GATE(GATE_CLK_RXU15, "clk_gate_rxu15", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 15),
+ SG2042_GATE(GATE_CLK_RXU16, "clk_gate_rxu16", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 16),
+ SG2042_GATE(GATE_CLK_RXU17, "clk_gate_rxu17", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 17),
+ SG2042_GATE(GATE_CLK_RXU18, "clk_gate_rxu18", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 18),
+ SG2042_GATE(GATE_CLK_RXU19, "clk_gate_rxu19", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 19),
+ SG2042_GATE(GATE_CLK_RXU20, "clk_gate_rxu20", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 20),
+ SG2042_GATE(GATE_CLK_RXU21, "clk_gate_rxu21", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 21),
+ SG2042_GATE(GATE_CLK_RXU22, "clk_gate_rxu22", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 22),
+ SG2042_GATE(GATE_CLK_RXU23, "clk_gate_rxu23", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 23),
+ SG2042_GATE(GATE_CLK_RXU24, "clk_gate_rxu24", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 24),
+ SG2042_GATE(GATE_CLK_RXU25, "clk_gate_rxu25", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 25),
+ SG2042_GATE(GATE_CLK_RXU26, "clk_gate_rxu26", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 26),
+ SG2042_GATE(GATE_CLK_RXU27, "clk_gate_rxu27", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 27),
+ SG2042_GATE(GATE_CLK_RXU28, "clk_gate_rxu28", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 28),
+ SG2042_GATE(GATE_CLK_RXU29, "clk_gate_rxu29", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 29),
+ SG2042_GATE(GATE_CLK_RXU30, "clk_gate_rxu30", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 30),
+ SG2042_GATE(GATE_CLK_RXU31, "clk_gate_rxu31", "clk_gate_rp_cpu_normal",
+ 0, R_RP_RXU_CLK_ENABLE, 31),
+
+ /* downstream of clk_gate_rp_cpu_normal about mp */
+ SG2042_GATE(GATE_CLK_MP0, "clk_gate_mp0", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP0_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP1, "clk_gate_mp1", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP1_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP2, "clk_gate_mp2", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP2_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP3, "clk_gate_mp3", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP3_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP4, "clk_gate_mp4", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP4_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP5, "clk_gate_mp5", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP5_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP6, "clk_gate_mp6", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP6_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP7, "clk_gate_mp7", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP7_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP8, "clk_gate_mp8", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP8_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP9, "clk_gate_mp9", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP9_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP10, "clk_gate_mp10", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP10_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP11, "clk_gate_mp11", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP11_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP12, "clk_gate_mp12", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP12_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP13, "clk_gate_mp13", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP13_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP14, "clk_gate_mp14", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP14_CONTROL_REG, 0),
+ SG2042_GATE(GATE_CLK_MP15, "clk_gate_mp15", "clk_gate_rp_cpu_normal",
+ CLK_IS_CRITICAL, R_MP15_CONTROL_REG, 0),
+};
+
+#define SG2042_MUX(_id, _name, _parent_names, _flags, _r_select, _shift, _width) { \
+ .hw.init = CLK_HW_INIT_PARENTS( \
+ _name, \
+ _parent_names, \
+ NULL, \
+ _flags), \
+ .id = _id, \
+ .offset_select = _r_select, \
+ .shift = _shift, \
+ .width = _width, \
+ }
+
+/*
+ * Note: regarding names for mux clock, "0/1" or "div0/div1" means the
+ * first/second parent input source, not the register value.
+ * For example:
+ * "clk_div_ddr01_0" is the name of Clock divider 0 control of DDR01, and
+ * "clk_gate_ddr01_div0" is the gate clock in front of the "clk_div_ddr01_0",
+ * they are both controlled by register CLKDIVREG27;
+ * "clk_div_ddr01_1" is the name of Clock divider 1 control of DDR01, and
+ * "clk_gate_ddr01_div1" is the gate clock in front of the "clk_div_ddr01_1",
+ * they are both controlled by register CLKDIVREG28;
+ * While for register value of mux selection, use Clock Select for DDR01’s clock
+ * as example, see CLKSELREG0, bit[2].
+ * 1: Select in_dpll0_clk as clock source, correspondng to the parent input
+ * source from "clk_div_ddr01_0".
+ * 0: Select in_fpll_clk as clock source, corresponding to the parent input
+ * source from "clk_div_ddr01_1".
+ * So we need a table to define the array of register values corresponding to
+ * the parent index and tell CCF about this when registering mux clock.
+ */
+static const u32 sg2042_mux_table[] = {1, 0};
+
+static const char *const clk_mux_ddr01_p[] = {
+ "clk_div_ddr01_0", "clk_div_ddr01_1"};
+static const char *const clk_mux_ddr23_p[] = {
+ "clk_div_ddr23_0", "clk_div_ddr23_1"};
+static const char *const clk_mux_rp_cpu_normal_p[] = {
+ "clk_div_rp_cpu_normal_0", "clk_div_rp_cpu_normal_1"};
+static const char *const clk_mux_axi_ddr_p[] = {
+ "clk_div_axi_ddr_0", "clk_div_axi_ddr_1"};
+
+static struct sg2042_mux_clock sg2042_mux_clks[] = {
+ SG2042_MUX(MUX_CLK_DDR01, "clk_mux_ddr01", clk_mux_ddr01_p,
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT | CLK_MUX_READ_ONLY,
+ R_CLKSELREG0, 2, 1),
+ SG2042_MUX(MUX_CLK_DDR23, "clk_mux_ddr23", clk_mux_ddr23_p,
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT | CLK_MUX_READ_ONLY,
+ R_CLKSELREG0, 3, 1),
+ SG2042_MUX(MUX_CLK_RP_CPU_NORMAL, "clk_mux_rp_cpu_normal", clk_mux_rp_cpu_normal_p,
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ R_CLKSELREG0, 0, 1),
+ SG2042_MUX(MUX_CLK_AXI_DDR, "clk_mux_axi_ddr", clk_mux_axi_ddr_p,
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ R_CLKSELREG0, 1, 1),
+};
+
+static DEFINE_SPINLOCK(sg2042_clk_lock);
+
+static int sg2042_clk_register_plls(struct sg2042_clk_data *clk_data,
+ struct sg2042_pll_clock pll_clks[],
+ int num_pll_clks)
+{
+ struct clk_hw *hw;
+ struct sg2042_pll_clock *pll;
+ int i, ret = 0;
+
+ for (i = 0; i < num_pll_clks; i++) {
+ pll = &pll_clks[i];
+ /* assign these for ops usage during registration */
+ pll->base = clk_data->iobase;
+ pll->lock = &sg2042_clk_lock;
+
+ hw = &pll->hw;
+ ret = clk_hw_register(NULL, hw);
+ if (ret) {
+ pr_err("failed to register clock %s\n", pll->hw.init->name);
+ break;
+ }
+
+ clk_data->onecell_data.hws[pll->id] = hw;
+ }
+
+ /* leave unregister to outside if failed */
+ return ret;
+}
+
+static int sg2042_clk_register_divs(struct sg2042_clk_data *clk_data,
+ struct sg2042_divider_clock div_clks[],
+ int num_div_clks)
+{
+ struct clk_hw *hw;
+ struct sg2042_divider_clock *div;
+ int i, ret = 0;
+
+ for (i = 0; i < num_div_clks; i++) {
+ div = &div_clks[i];
+
+ if (div->div_flags & CLK_DIVIDER_HIWORD_MASK) {
+ if (div->width + div->shift > 16) {
+ pr_warn("divider value exceeds LOWORD field\n");
+ ret = -EINVAL;
+ break;
+ }
+ }
+
+ div->reg = clk_data->iobase + div->offset_ctrl;
+ div->lock = &sg2042_clk_lock;
+
+ hw = &div->hw;
+ ret = clk_hw_register(NULL, hw);
+ if (ret) {
+ pr_err("failed to register clock %s\n", div->hw.init->name);
+ break;
+ }
+
+ clk_data->onecell_data.hws[div->id] = hw;
+ }
+
+ /* leave unregister to outside if failed */
+ return ret;
+}
+
+static int sg2042_clk_register_gates(struct sg2042_clk_data *clk_data,
+ const struct sg2042_gate_clock gate_clks[],
+ int num_gate_clks)
+{
+ struct clk_hw *hw;
+ const struct sg2042_gate_clock *gate;
+ int i, ret = 0;
+
+ for (i = 0; i < num_gate_clks; i++) {
+ gate = &gate_clks[i];
+ hw = clk_hw_register_gate(NULL,
+ gate->hw.init->name,
+ gate->hw.init->parent_names[0],
+ gate->hw.init->flags,
+ clk_data->iobase + gate->offset_enable,
+ gate->bit_idx,
+ 0,
+ &sg2042_clk_lock);
+ if (IS_ERR(hw)) {
+ pr_err("failed to register clock %s\n", gate->hw.init->name);
+ ret = PTR_ERR(hw);
+ break;
+ }
+
+ clk_data->onecell_data.hws[gate->id] = hw;
+ }
+
+ /* leave unregister to outside if failed */
+ return ret;
+}
+
+static int sg2042_mux_notifier_cb(struct notifier_block *nb,
+ unsigned long event,
+ void *data)
+{
+ int ret = 0;
+ struct clk_notifier_data *ndata = data;
+ struct clk_hw *hw = __clk_get_hw(ndata->clk);
+ const struct clk_ops *ops = &clk_mux_ops;
+ struct sg2042_mux_clock *mux = to_sg2042_mux_nb(nb);
+
+ /* To switch to fpll before changing rate and restore after that */
+ if (event == PRE_RATE_CHANGE) {
+ mux->original_index = ops->get_parent(hw);
+
+ /*
+ * "1" is the array index of the second parent input source of
+ * mux. For SG2042, it's fpll for all mux clocks.
+ * "0" is the array index of the frist parent input source of
+ * mux, For SG2042, it's mpll.
+ * FIXME, any good idea to avoid magic number?
+ */
+ if (mux->original_index == 0)
+ ret = ops->set_parent(hw, 1);
+ } else if (event == POST_RATE_CHANGE) {
+ ret = ops->set_parent(hw, mux->original_index);
+ }
+
+ return notifier_from_errno(ret);
+}
+
+static int sg2042_clk_register_muxs(struct sg2042_clk_data *clk_data,
+ struct sg2042_mux_clock mux_clks[],
+ int num_mux_clks)
+{
+ struct clk_hw *hw;
+ struct sg2042_mux_clock *mux;
+ int i, ret = 0;
+
+ for (i = 0; i < num_mux_clks; i++) {
+ mux = &mux_clks[i];
+
+ hw = clk_hw_register_mux_table(NULL,
+ mux->hw.init->name,
+ mux->hw.init->parent_names,
+ mux->hw.init->num_parents,
+ mux->hw.init->flags,
+ clk_data->iobase + mux->offset_select,
+ mux->shift,
+ BIT(mux->width) - 1,
+ 0,
+ sg2042_mux_table,
+ &sg2042_clk_lock);
+ if (IS_ERR(hw)) {
+ pr_err("failed to register clock %s\n", mux->hw.init->name);
+ ret = PTR_ERR(hw);
+ break;
+ }
+
+ clk_data->onecell_data.hws[mux->id] = hw;
+
+ /*
+ * FIXME: Theoretically, we should set parent for the
+ * mux, but seems hardware has done this for us with
+ * default value, so we don't set parent again here.
+ */
+
+ if (!(mux->hw.init->flags & CLK_MUX_READ_ONLY)) {
+ mux->clk_nb.notifier_call = sg2042_mux_notifier_cb;
+ ret = clk_notifier_register(hw->clk, &mux->clk_nb);
+ if (ret) {
+ pr_err("failed to register clock notifier for %s\n",
+ mux->hw.init->name);
+ goto error_cleanup;
+ }
+ }
+ }
+
+ return 0;
+
+error_cleanup:
+ /* unregister notifier and release the memory allocated */
+ for (i = 0; i < num_mux_clks; i++) {
+ mux = &mux_clks[i];
+
+ hw = clk_data->onecell_data.hws[mux->id];
+
+ if (hw)
+ clk_notifier_unregister(hw->clk, &mux->clk_nb);
+ }
+
+ /* leave clk unregister to outside if failed */
+ return ret;
+}
+
+static int sg2042_init_clkdata(struct platform_device *pdev,
+ int num_clks,
+ struct sg2042_clk_data **pp_clk_data)
+{
+ struct sg2042_clk_data *clk_data = NULL;
+
+ clk_data = devm_kzalloc(&pdev->dev,
+ struct_size(clk_data, onecell_data.hws, num_clks),
+ GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ clk_data->iobase = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
+ if (WARN_ON(IS_ERR(clk_data->iobase)))
+ return PTR_ERR(clk_data->iobase);
+
+ clk_data->onecell_data.num = num_clks;
+
+ *pp_clk_data = clk_data;
+
+ return 0;
+}
+
+static int sg2042_clkgen_probe(struct platform_device *pdev)
+{
+ struct sg2042_clk_data *clk_data = NULL;
+ int i, ret = 0;
+ int num_clks = 0;
+
+ num_clks = ARRAY_SIZE(sg2042_div_clks) +
+ ARRAY_SIZE(sg2042_gate_clks) +
+ ARRAY_SIZE(sg2042_mux_clks);
+ if (num_clks == 0) {
+ ret = -EINVAL;
+ goto error_out;
+ }
+
+ ret = sg2042_init_clkdata(pdev, num_clks, &clk_data);
+ if (ret < 0)
+ goto error_out;
+
+ ret = sg2042_clk_register_divs(clk_data, sg2042_div_clks,
+ ARRAY_SIZE(sg2042_div_clks));
+ if (ret)
+ goto cleanup;
+
+ ret = sg2042_clk_register_gates(clk_data, sg2042_gate_clks,
+ ARRAY_SIZE(sg2042_gate_clks));
+ if (ret)
+ goto cleanup;
+
+ ret = sg2042_clk_register_muxs(clk_data, sg2042_mux_clks,
+ ARRAY_SIZE(sg2042_mux_clks));
+ if (ret)
+ goto cleanup;
+
+ return devm_of_clk_add_hw_provider(&pdev->dev,
+ of_clk_hw_onecell_get,
+ &clk_data->onecell_data);
+
+cleanup:
+ for (i = 0; i < num_clks; i++) {
+ if (clk_data->onecell_data.hws[i])
+ clk_hw_unregister(clk_data->onecell_data.hws[i]);
+ }
+
+error_out:
+ pr_err("%s failed error number %d\n", __func__, ret);
+ return ret;
+}
+
+static int sg2042_rpgate_probe(struct platform_device *pdev)
+{
+ struct sg2042_clk_data *clk_data = NULL;
+ int i, ret = 0;
+ int num_clks = 0;
+
+ num_clks = ARRAY_SIZE(sg2042_gate_rp);
+ if (num_clks == 0) {
+ ret = -EINVAL;
+ goto error_out;
+ }
+
+ ret = sg2042_init_clkdata(pdev, num_clks, &clk_data);
+ if (ret < 0)
+ goto error_out;
+
+ ret = sg2042_clk_register_gates(clk_data, sg2042_gate_rp,
+ ARRAY_SIZE(sg2042_gate_rp));
+ if (ret)
+ goto cleanup;
+
+ return devm_of_clk_add_hw_provider(&pdev->dev,
+ of_clk_hw_onecell_get,
+ &clk_data->onecell_data);
+
+cleanup:
+ for (i = 0; i < num_clks; i++) {
+ if (clk_data->onecell_data.hws[i])
+ clk_hw_unregister(clk_data->onecell_data.hws[i]);
+ }
+
+error_out:
+ pr_err("%s failed error number %d\n", __func__, ret);
+ return ret;
+}
+
+static int sg2042_pll_probe(struct platform_device *pdev)
+{
+ struct sg2042_clk_data *clk_data = NULL;
+ int i, ret = 0;
+ int num_clks = 0;
+
+ num_clks = ARRAY_SIZE(sg2042_pll_clks);
+ if (num_clks == 0) {
+ ret = -EINVAL;
+ goto error_out;
+ }
+
+ ret = sg2042_init_clkdata(pdev, num_clks, &clk_data);
+ if (ret < 0)
+ goto error_out;
+
+ ret = sg2042_clk_register_plls(clk_data, sg2042_pll_clks,
+ ARRAY_SIZE(sg2042_pll_clks));
+ if (ret)
+ goto cleanup;
+
+ return devm_of_clk_add_hw_provider(&pdev->dev,
+ of_clk_hw_onecell_get,
+ &clk_data->onecell_data);
+
+cleanup:
+ for (i = 0; i < num_clks; i++) {
+ if (clk_data->onecell_data.hws[i])
+ clk_hw_unregister(clk_data->onecell_data.hws[i]);
+ }
+
+error_out:
+ pr_err("%s failed error number %d\n", __func__, ret);
+ return ret;
+}
+
+static const struct of_device_id sg2042_clkgen_match[] = {
+ { .compatible = "sophgo,sg2042-clkgen" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver sg2042_clkgen_driver = {
+ .probe = sg2042_clkgen_probe,
+ .driver = {
+ .name = "clk-sophgo-sg2042-clkgen",
+ .of_match_table = sg2042_clkgen_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver(sg2042_clkgen_driver);
+
+static const struct of_device_id sg2042_rpgate_match[] = {
+ { .compatible = "sophgo,sg2042-rpgate" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver sg2042_rpgate_driver = {
+ .probe = sg2042_rpgate_probe,
+ .driver = {
+ .name = "clk-sophgo-sg2042-rpgate",
+ .of_match_table = sg2042_rpgate_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver(sg2042_rpgate_driver);
+
+static const struct of_device_id sg2042_pll_match[] = {
+ { .compatible = "sophgo,sg2042-pll" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver sg2042_pll_driver = {
+ .probe = sg2042_pll_probe,
+ .driver = {
+ .name = "clk-sophgo-sg2042-pll",
+ .of_match_table = sg2042_pll_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver(sg2042_pll_driver);
diff --git a/drivers/clk/sophgo/clk-sophgo-sg2042.h b/drivers/clk/sophgo/clk-sophgo-sg2042.h
new file mode 100644
index 000000000000..407fec6f3f02
--- /dev/null
+++ b/drivers/clk/sophgo/clk-sophgo-sg2042.h
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __CLK_SOPHGO_SG2042_H
+#define __CLK_SOPHGO_SG2042_H
+
+/* Registers defined in SYS_CTRL */
+#define R_PLL_BEGIN 0xC0
+#define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
+#define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
+#define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
+#define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
+#define R_DPLL0_CONTROL (0xF8 - R_PLL_BEGIN)
+#define R_DPLL1_CONTROL (0xFC - R_PLL_BEGIN)
+
+#define R_SYSGATE_BEGIN 0x0368
+#define R_RP_RXU_CLK_ENABLE (0x0368 - R_SYSGATE_BEGIN)
+#define R_MP0_STATUS_REG (0x0380 - R_SYSGATE_BEGIN)
+#define R_MP0_CONTROL_REG (0x0384 - R_SYSGATE_BEGIN)
+#define R_MP1_STATUS_REG (0x0388 - R_SYSGATE_BEGIN)
+#define R_MP1_CONTROL_REG (0x038C - R_SYSGATE_BEGIN)
+#define R_MP2_STATUS_REG (0x0390 - R_SYSGATE_BEGIN)
+#define R_MP2_CONTROL_REG (0x0394 - R_SYSGATE_BEGIN)
+#define R_MP3_STATUS_REG (0x0398 - R_SYSGATE_BEGIN)
+#define R_MP3_CONTROL_REG (0x039C - R_SYSGATE_BEGIN)
+#define R_MP4_STATUS_REG (0x03A0 - R_SYSGATE_BEGIN)
+#define R_MP4_CONTROL_REG (0x03A4 - R_SYSGATE_BEGIN)
+#define R_MP5_STATUS_REG (0x03A8 - R_SYSGATE_BEGIN)
+#define R_MP5_CONTROL_REG (0x03AC - R_SYSGATE_BEGIN)
+#define R_MP6_STATUS_REG (0x03B0 - R_SYSGATE_BEGIN)
+#define R_MP6_CONTROL_REG (0x03B4 - R_SYSGATE_BEGIN)
+#define R_MP7_STATUS_REG (0x03B8 - R_SYSGATE_BEGIN)
+#define R_MP7_CONTROL_REG (0x03BC - R_SYSGATE_BEGIN)
+#define R_MP8_STATUS_REG (0x03C0 - R_SYSGATE_BEGIN)
+#define R_MP8_CONTROL_REG (0x03C4 - R_SYSGATE_BEGIN)
+#define R_MP9_STATUS_REG (0x03C8 - R_SYSGATE_BEGIN)
+#define R_MP9_CONTROL_REG (0x03CC - R_SYSGATE_BEGIN)
+#define R_MP10_STATUS_REG (0x03D0 - R_SYSGATE_BEGIN)
+#define R_MP10_CONTROL_REG (0x03D4 - R_SYSGATE_BEGIN)
+#define R_MP11_STATUS_REG (0x03D8 - R_SYSGATE_BEGIN)
+#define R_MP11_CONTROL_REG (0x03DC - R_SYSGATE_BEGIN)
+#define R_MP12_STATUS_REG (0x03E0 - R_SYSGATE_BEGIN)
+#define R_MP12_CONTROL_REG (0x03E4 - R_SYSGATE_BEGIN)
+#define R_MP13_STATUS_REG (0x03E8 - R_SYSGATE_BEGIN)
+#define R_MP13_CONTROL_REG (0x03EC - R_SYSGATE_BEGIN)
+#define R_MP14_STATUS_REG (0x03F0 - R_SYSGATE_BEGIN)
+#define R_MP14_CONTROL_REG (0x03F4 - R_SYSGATE_BEGIN)
+#define R_MP15_STATUS_REG (0x03F8 - R_SYSGATE_BEGIN)
+#define R_MP15_CONTROL_REG (0x03FC - R_SYSGATE_BEGIN)
+
+/* Registers defined in CLOCK */
+#define R_CLKENREG0 0x00
+#define R_CLKENREG1 0x04
+#define R_CLKSELREG0 0x20
+#define R_CLKDIVREG0 0x40
+#define R_CLKDIVREG1 0x44
+#define R_CLKDIVREG2 0x48
+#define R_CLKDIVREG3 0x4C
+#define R_CLKDIVREG4 0x50
+#define R_CLKDIVREG5 0x54
+#define R_CLKDIVREG6 0x58
+#define R_CLKDIVREG7 0x5C
+#define R_CLKDIVREG8 0x60
+#define R_CLKDIVREG9 0x64
+#define R_CLKDIVREG10 0x68
+#define R_CLKDIVREG11 0x6C
+#define R_CLKDIVREG12 0x70
+#define R_CLKDIVREG13 0x74
+#define R_CLKDIVREG14 0x78
+#define R_CLKDIVREG15 0x7C
+#define R_CLKDIVREG16 0x80
+#define R_CLKDIVREG17 0x84
+#define R_CLKDIVREG18 0x88
+#define R_CLKDIVREG19 0x8C
+#define R_CLKDIVREG20 0x90
+#define R_CLKDIVREG21 0x94
+#define R_CLKDIVREG22 0x98
+#define R_CLKDIVREG23 0x9C
+#define R_CLKDIVREG24 0xA0
+#define R_CLKDIVREG25 0xA4
+#define R_CLKDIVREG26 0xA8
+#define R_CLKDIVREG27 0xAC
+#define R_CLKDIVREG28 0xB0
+#define R_CLKDIVREG29 0xB4
+#define R_CLKDIVREG30 0xB8
+
+/*
+ * Common data of clock-controller
+ * Note: this structure will be used both by clkgen & sysclk.
+ * @iobase: base address of clock-controller
+ * @onecell_data: used for adding providers.
+ */
+struct sg2042_clk_data {
+ void __iomem *iobase;
+ struct clk_hw_onecell_data onecell_data;
+};
+
+/*
+ * PLL clock
+ * @hw: clk_hw for initialization
+ * @id: used to map clk_onecell_data
+ * @base: used for readl/writel.
+ * **NOTE**: PLL registers are all in SYS_CTRL!
+ * @lock: spinlock to protect register access, modification
+ * of frequency can only be served one at the time.
+ * @offset_status: offset of pll status registers
+ * @offset_enable: offset of pll enable registers
+ * @offset_ctrl: offset of pll control registers
+ * @shift_status_lock: shift of XXX_LOCK in pll status register
+ * @shift_status_updating: shift of UPDATING_XXX in pll status register
+ * @shift_enable: shift of XXX_CLK_EN in pll enable register
+ */
+struct sg2042_pll_clock {
+ struct clk_hw hw;
+
+ unsigned int id;
+ void __iomem *base;
+ /* protect register access */
+ spinlock_t *lock;
+
+ u32 offset_status;
+ u32 offset_enable;
+ u32 offset_ctrl;
+ u8 shift_status_lock;
+ u8 shift_status_updating;
+ u8 shift_enable;
+};
+
+#define to_sg2042_pll_clk(_hw) container_of(_hw, struct sg2042_pll_clock, hw)
+
+/*
+ * Divider clock
+ * @hw: clk_hw for initialization
+ * @id: used to map clk_onecell_data
+ * @reg: used for readl/writel.
+ * **NOTE**: DIV registers are ALL in CLOCK!
+ * @lock: spinlock to protect register access, modification of
+ * frequency can only be served one at the time
+ * @offset_ctrl: offset of divider control registers
+ * @shift: shift of "Clock Divider Factor" in divider control register
+ * @width: width of "Clock Divider Factor" in divider control register
+ * @div_flags: private flags for this clock, not for framework-specific
+ * @initval: In the divider control register, we can configure whether
+ * to use the value of "Clock Divider Factor" or just use
+ * the initial value pre-configured by IC. BIT[3] controls
+ * this and by default (value is 0), means initial value
+ * is used.
+ * **NOTE** that we cannot read the initial value (default
+ * value when poweron) and default value of "Clock Divider
+ * Factor" is zero, which I think is a hardware design flaw
+ * and should be sync-ed with the initial value. So in
+ * software we have to add a configuration item (initval)
+ * to manually configure this value and use it when BIT[3]
+ * is zero.
+ */
+struct sg2042_divider_clock {
+ struct clk_hw hw;
+
+ unsigned int id;
+
+ void __iomem *reg;
+ /* protect register access */
+ spinlock_t *lock;
+
+ unsigned long offset_ctrl;
+ u8 shift;
+ u8 width;
+ u8 div_flags;
+ u32 initval;
+};
+
+#define to_sg2042_clk_divider(_hw) \
+ container_of(_hw, struct sg2042_divider_clock, hw)
+
+/*
+ * Gate clock
+ * @hw: clk_hw for initialization
+ * @id: used to map clk_onecell_data
+ * @offset_enable: offset of gate enable registers
+ * @bit_idx: which bit in the register controls gating of this clock
+ */
+struct sg2042_gate_clock {
+ struct clk_hw hw;
+
+ unsigned int id;
+
+ unsigned long offset_enable;
+ u8 bit_idx;
+};
+
+/*
+ * Mux clock
+ * @hw: clk_hw for initialization
+ * @id: used to map clk_onecell_data
+ * @offset_select: offset of mux selection registers
+ * **NOTE**: MUX registers are ALL in CLOCK!
+ * @shift: shift of "Clock Select" in mux selection register
+ * @width: width of "Clock Select" in mux selection register
+ * @clk_nb: used for notification
+ * @original_index: set by notifier callback
+ */
+struct sg2042_mux_clock {
+ struct clk_hw hw;
+
+ unsigned int id;
+
+ unsigned long offset_select;
+ u8 shift;
+ u8 width;
+
+ struct notifier_block clk_nb;
+ u8 original_index;
+};
+
+#define to_sg2042_mux_nb(_nb) container_of(_nb, struct sg2042_mux_clock, clk_nb)
+
+#endif /* __CLK_SOPHGO_SG2042_H */
--
2.25.1
^ permalink raw reply related
* [PATCH v12 3/5] dt-bindings: clock: sophgo: add clkgen for SG2042
From: Chen Wang @ 2024-03-27 8:30 UTC (permalink / raw)
To: aou, chao.wei, conor, krzysztof.kozlowski+dt, mturquette, palmer,
paul.walmsley, richardcochran, robh+dt, sboyd, devicetree,
linux-clk, linux-kernel, linux-riscv, haijiao.liu, xiaoguang.xing,
guoren, jszhang, inochiama, samuel.holland
Cc: Chen Wang, Rob Herring
In-Reply-To: <cover.1711527932.git.unicorn_wang@outlook.com>
From: Chen Wang <unicorn_wang@outlook.com>
Add bindings for the clock generator of divider/mux and gates working
for other subsystem than RP subsystem for Sophgo SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/clock/sophgo,sg2042-clkgen.yaml | 49 ++++++++
.../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++++++++++++++++++
2 files changed, 160 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h
diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
new file mode 100644
index 000000000000..e31dece67215
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Clock Generator for divider/mux/gate
+
+maintainers:
+ - Chen Wang <unicorn_wang@outlook.com>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-clkgen
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main PLL
+ - description: Fixed PLL
+ - description: DDR PLL 0
+ - description: DDR PLL 1
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@30012000 {
+ compatible = "sophgo,sg2042-clkgen";
+ reg = <0x30012000 0x1000>;
+ clocks = <&pllclk 0>,
+ <&pllclk 1>,
+ <&pllclk 2>,
+ <&pllclk 3>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/sophgo,sg2042-clkgen.h b/include/dt-bindings/clock/sophgo,sg2042-clkgen.h
new file mode 100644
index 000000000000..84f7857317a2
--- /dev/null
+++ b/include/dt-bindings/clock/sophgo,sg2042-clkgen.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__
+#define __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__
+
+#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0
+#define DIV_CLK_MPLL_AXI_DDR_0 1
+#define DIV_CLK_FPLL_DDR01_1 2
+#define DIV_CLK_FPLL_DDR23_1 3
+#define DIV_CLK_FPLL_RP_CPU_NORMAL_1 4
+#define DIV_CLK_FPLL_50M_A53 5
+#define DIV_CLK_FPLL_TOP_RP_CMN_DIV2 6
+#define DIV_CLK_FPLL_UART_500M 7
+#define DIV_CLK_FPLL_AHB_LPC 8
+#define DIV_CLK_FPLL_EFUSE 9
+#define DIV_CLK_FPLL_TX_ETH0 10
+#define DIV_CLK_FPLL_PTP_REF_I_ETH0 11
+#define DIV_CLK_FPLL_REF_ETH0 12
+#define DIV_CLK_FPLL_EMMC 13
+#define DIV_CLK_FPLL_SD 14
+#define DIV_CLK_FPLL_TOP_AXI0 15
+#define DIV_CLK_FPLL_TOP_AXI_HSPERI 16
+#define DIV_CLK_FPLL_AXI_DDR_1 17
+#define DIV_CLK_FPLL_DIV_TIMER1 18
+#define DIV_CLK_FPLL_DIV_TIMER2 19
+#define DIV_CLK_FPLL_DIV_TIMER3 20
+#define DIV_CLK_FPLL_DIV_TIMER4 21
+#define DIV_CLK_FPLL_DIV_TIMER5 22
+#define DIV_CLK_FPLL_DIV_TIMER6 23
+#define DIV_CLK_FPLL_DIV_TIMER7 24
+#define DIV_CLK_FPLL_DIV_TIMER8 25
+#define DIV_CLK_FPLL_100K_EMMC 26
+#define DIV_CLK_FPLL_100K_SD 27
+#define DIV_CLK_FPLL_GPIO_DB 28
+#define DIV_CLK_DPLL0_DDR01_0 29
+#define DIV_CLK_DPLL1_DDR23_0 30
+
+#define GATE_CLK_RP_CPU_NORMAL_DIV0 31
+#define GATE_CLK_AXI_DDR_DIV0 32
+
+#define GATE_CLK_RP_CPU_NORMAL_DIV1 33
+#define GATE_CLK_A53_50M 34
+#define GATE_CLK_TOP_RP_CMN_DIV2 35
+#define GATE_CLK_HSDMA 36
+#define GATE_CLK_EMMC_100M 37
+#define GATE_CLK_SD_100M 38
+#define GATE_CLK_TX_ETH0 39
+#define GATE_CLK_PTP_REF_I_ETH0 40
+#define GATE_CLK_REF_ETH0 41
+#define GATE_CLK_UART_500M 42
+#define GATE_CLK_EFUSE 43
+
+#define GATE_CLK_AHB_LPC 44
+#define GATE_CLK_AHB_ROM 45
+#define GATE_CLK_AHB_SF 46
+
+#define GATE_CLK_APB_UART 47
+#define GATE_CLK_APB_TIMER 48
+#define GATE_CLK_APB_EFUSE 49
+#define GATE_CLK_APB_GPIO 50
+#define GATE_CLK_APB_GPIO_INTR 51
+#define GATE_CLK_APB_SPI 52
+#define GATE_CLK_APB_I2C 53
+#define GATE_CLK_APB_WDT 54
+#define GATE_CLK_APB_PWM 55
+#define GATE_CLK_APB_RTC 56
+
+#define GATE_CLK_AXI_PCIE0 57
+#define GATE_CLK_AXI_PCIE1 58
+#define GATE_CLK_SYSDMA_AXI 59
+#define GATE_CLK_AXI_DBG_I2C 60
+#define GATE_CLK_AXI_SRAM 61
+#define GATE_CLK_AXI_ETH0 62
+#define GATE_CLK_AXI_EMMC 63
+#define GATE_CLK_AXI_SD 64
+#define GATE_CLK_TOP_AXI0 65
+#define GATE_CLK_TOP_AXI_HSPERI 66
+
+#define GATE_CLK_TIMER1 67
+#define GATE_CLK_TIMER2 68
+#define GATE_CLK_TIMER3 69
+#define GATE_CLK_TIMER4 70
+#define GATE_CLK_TIMER5 71
+#define GATE_CLK_TIMER6 72
+#define GATE_CLK_TIMER7 73
+#define GATE_CLK_TIMER8 74
+#define GATE_CLK_100K_EMMC 75
+#define GATE_CLK_100K_SD 76
+#define GATE_CLK_GPIO_DB 77
+
+#define GATE_CLK_AXI_DDR_DIV1 78
+#define GATE_CLK_DDR01_DIV1 79
+#define GATE_CLK_DDR23_DIV1 80
+
+#define GATE_CLK_DDR01_DIV0 81
+#define GATE_CLK_DDR23_DIV0 82
+
+#define GATE_CLK_DDR01 83
+#define GATE_CLK_DDR23 84
+#define GATE_CLK_RP_CPU_NORMAL 85
+#define GATE_CLK_AXI_DDR 86
+
+#define MUX_CLK_DDR01 87
+#define MUX_CLK_DDR23 88
+#define MUX_CLK_RP_CPU_NORMAL 89
+#define MUX_CLK_AXI_DDR 90
+
+#endif /* __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ */
--
2.25.1
^ permalink raw reply related
* RE: [PATCH v2 6/6] misc: pci_endpoint_test: Add Device ID for R-Car V4H PCIe controller
From: Yoshihiro Shimoda @ 2024-03-27 8:30 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Frank Li, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org,
bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, mani@kernel.org,
marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Geert Uytterhoeven
In-Reply-To: <CAMuHMdU+5=r5Wa9cy0XDRnygumjMsC6mH0Tg-OVgbBkQjk1+0g@mail.gmail.com>
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, March 27, 2024 5:12 PM
>
> Hi Shimoda-san,
>
> On Tue, Mar 26, 2024 at 6:47 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > From: Frank Li, Sent: Tuesday, March 26, 2024 12:21 PM
> > > On Tue, Mar 26, 2024 at 11:45:40AM +0900, Yoshihiro Shimoda wrote:
> > > > Add Renesas R8A779G0 in pci_device_id table so that pci-epf-test
> > > > can be used for testing PCIe EP on R-Car V4H.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > ---
> > > > drivers/misc/pci_endpoint_test.c | 4 ++++
> > > > 1 file changed, 4 insertions(+)
> > > >
> > > > diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
> > > > index c38a6083f0a7..2fa3c6473c7d 100644
> > > > --- a/drivers/misc/pci_endpoint_test.c
> > > > +++ b/drivers/misc/pci_endpoint_test.c
> > > > @@ -83,6 +83,7 @@
> > > > #define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
> > > > #define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
> > > > #define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031
> > > > +#define PCI_DEVICE_ID_RENESAS_R8A779G0 0x0030
> > > >
> > > > static DEFINE_IDA(pci_endpoint_test_ida);
> > > >
> > > > @@ -1005,6 +1006,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
> > > > { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0),
> > > > .driver_data = (kernel_ulong_t)&default_data,
> > > > },
> > > > + { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779G0),
> > > > + .driver_data = (kernel_ulong_t)&default_data,
> > > > + },
> > >
> > > You use default_data, why need new device_id? I think you can use 0x0031
> > > to do test.
> >
> > I thought we can add a new device_id freely like other devices.
> > Since the PCIe controller's endpoint mode can configure the device id,
> > I can use 0x0031 to do test though.
>
> Can it?
Yes, the following function can write the device id in endpoint mode.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-designware-ep.c?h=v6.9-rc1#n108
> The documentation for the PCICONF0Fi register states both the
> DEVICE_ID and VENDOR_ID bits are read-only.
You're correct. The documentation (R-Car V4H hardware manual) said these bits are read-only.
However, actual hardware IP seems to allow writing this register if the write protect is disabled in endpoint mode.
Best regards,
Yoshihiro Shimoda
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply
* [PATCH v12 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042
From: Chen Wang @ 2024-03-27 8:30 UTC (permalink / raw)
To: aou, chao.wei, conor, krzysztof.kozlowski+dt, mturquette, palmer,
paul.walmsley, richardcochran, robh+dt, sboyd, devicetree,
linux-clk, linux-kernel, linux-riscv, haijiao.liu, xiaoguang.xing,
guoren, jszhang, inochiama, samuel.holland
Cc: Chen Wang, Rob Herring
In-Reply-To: <cover.1711527932.git.unicorn_wang@outlook.com>
From: Chen Wang <unicorn_wang@outlook.com>
Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/clock/sophgo,sg2042-rpgate.yaml | 43 ++++++++++++++
.../dt-bindings/clock/sophgo,sg2042-rpgate.h | 58 +++++++++++++++++++
2 files changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml
create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h
diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml
new file mode 100644
index 000000000000..9a58038b3182
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem
+
+maintainers:
+ - Chen Wang <unicorn_wang@outlook.com>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-rpgate
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Gate clock for RP subsystem
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@20000000 {
+ compatible = "sophgo,sg2042-rpgate";
+ reg = <0x20000000 0x10000>;
+ clocks = <&clkgen 85>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/sophgo,sg2042-rpgate.h b/include/dt-bindings/clock/sophgo,sg2042-rpgate.h
new file mode 100644
index 000000000000..8b4522d5f559
--- /dev/null
+++ b/include/dt-bindings/clock/sophgo,sg2042-rpgate.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__
+#define __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__
+
+#define GATE_CLK_RXU0 0
+#define GATE_CLK_RXU1 1
+#define GATE_CLK_RXU2 2
+#define GATE_CLK_RXU3 3
+#define GATE_CLK_RXU4 4
+#define GATE_CLK_RXU5 5
+#define GATE_CLK_RXU6 6
+#define GATE_CLK_RXU7 7
+#define GATE_CLK_RXU8 8
+#define GATE_CLK_RXU9 9
+#define GATE_CLK_RXU10 10
+#define GATE_CLK_RXU11 11
+#define GATE_CLK_RXU12 12
+#define GATE_CLK_RXU13 13
+#define GATE_CLK_RXU14 14
+#define GATE_CLK_RXU15 15
+#define GATE_CLK_RXU16 16
+#define GATE_CLK_RXU17 17
+#define GATE_CLK_RXU18 18
+#define GATE_CLK_RXU19 19
+#define GATE_CLK_RXU20 20
+#define GATE_CLK_RXU21 21
+#define GATE_CLK_RXU22 22
+#define GATE_CLK_RXU23 23
+#define GATE_CLK_RXU24 24
+#define GATE_CLK_RXU25 25
+#define GATE_CLK_RXU26 26
+#define GATE_CLK_RXU27 27
+#define GATE_CLK_RXU28 28
+#define GATE_CLK_RXU29 29
+#define GATE_CLK_RXU30 30
+#define GATE_CLK_RXU31 31
+#define GATE_CLK_MP0 32
+#define GATE_CLK_MP1 33
+#define GATE_CLK_MP2 34
+#define GATE_CLK_MP3 35
+#define GATE_CLK_MP4 36
+#define GATE_CLK_MP5 37
+#define GATE_CLK_MP6 38
+#define GATE_CLK_MP7 39
+#define GATE_CLK_MP8 40
+#define GATE_CLK_MP9 41
+#define GATE_CLK_MP10 42
+#define GATE_CLK_MP11 43
+#define GATE_CLK_MP12 44
+#define GATE_CLK_MP13 45
+#define GATE_CLK_MP14 46
+#define GATE_CLK_MP15 47
+
+#endif /* __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__ */
--
2.25.1
^ permalink raw reply related
* [PATCH v12 1/5] dt-bindings: clock: sophgo: add pll clocks for SG2042
From: Chen Wang @ 2024-03-27 8:29 UTC (permalink / raw)
To: aou, chao.wei, conor, krzysztof.kozlowski+dt, mturquette, palmer,
paul.walmsley, richardcochran, robh+dt, sboyd, devicetree,
linux-clk, linux-kernel, linux-riscv, haijiao.liu, xiaoguang.xing,
guoren, jszhang, inochiama, samuel.holland
Cc: Chen Wang, Rob Herring
In-Reply-To: <cover.1711527932.git.unicorn_wang@outlook.com>
From: Chen Wang <unicorn_wang@outlook.com>
Add bindings for the pll clocks for Sophgo SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
.../bindings/clock/sophgo,sg2042-pll.yaml | 45 +++++++++++++++++++
include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 ++++++
2 files changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml
create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h
diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml
new file mode 100644
index 000000000000..b9af733e8a73
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 PLL Clock Generator
+
+maintainers:
+ - Chen Wang <unicorn_wang@outlook.com>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-pll
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
+ - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
+ - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@10000000 {
+ compatible = "sophgo,sg2042-pll";
+ reg = <0x10000000 0x10000>;
+ clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/sophgo,sg2042-pll.h b/include/dt-bindings/clock/sophgo,sg2042-pll.h
new file mode 100644
index 000000000000..2d519b3bf51c
--- /dev/null
+++ b/include/dt-bindings/clock/sophgo,sg2042-pll.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__
+#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__
+
+#define MPLL_CLK 0
+#define FPLL_CLK 1
+#define DPLL0_CLK 2
+#define DPLL1_CLK 3
+
+#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */
--
2.25.1
^ permalink raw reply related
* [PATCH v12 0/5] riscv: sophgo: add clock support for sg2042
From: Chen Wang @ 2024-03-27 8:29 UTC (permalink / raw)
To: aou, chao.wei, conor, krzysztof.kozlowski+dt, mturquette, palmer,
paul.walmsley, richardcochran, robh+dt, sboyd, devicetree,
linux-clk, linux-kernel, linux-riscv, haijiao.liu, xiaoguang.xing,
guoren, jszhang, inochiama, samuel.holland
Cc: Chen Wang
From: Chen Wang <unicorn_wang@outlook.com>
This series adds clock controller support for sophgo sg2042.
Thanks,
Chen
---
Changes in v12:
The patch series is based on v6.9-rc1.
Improved the dirvier code as per review comments from Stephen Boyd.
- Remove default y for CLK_SOPHGO_SG2042.
- Optimize sg2042_pll_get_postdiv_1_2, move postdiv1_2 to the function.
scope and add more explaniation.
- Optimize sg2042_get_pll_ctl_setting.
- Switch to platform driver.
- Use clk_hw for initialization of struct clks.
- Don't use ignore_unused when using critical.
- Other code cleanup as per input form the reviewers.
Changes in v11:
The patch series is based on v6.8-rc5. You can simply review or test the
patches at the link [12].
Quick fixed some dt_binding_check errors reported by Rob.
Changes in v10:
The patch series is based on v6.8-rc4. You can simply review or test the
patches at the link [11].
Add input clocks for rpgate & clkgen.
Changes in v9:
The patch series is based on v6.8-rc2. You can simply review or test the
patches at the link [10].
From this version, drop the system-controller node due to there is no actual
device corresponding to it in IC design. SYS_CTRL is just a registers segment
defined on TRM for misc functions. Now three clock-controllers are defined for
SG2042, the control registers of the three clock-controllers are scattered in
different memory address spaces:
- the first one is for pll clocks;
- the second one is for gate clocks for RP subsystem;
- the third one is for div/mux, and gate clocks working for other subsystem
than RP subsystem.
Changes in v8:
The patch series is based on v6.7. You can simply review or test the
patches at the link [9].
In this version, the main change is to split one clock provider into two.
Strictly follow the hardware instructions, in the memoymap, the control
registers of some clocks are defined in the SYS_CTRL segment, and the
control registers of other clocks are defined in the CLOCK segment.
Therefore, the new design defines two clock controllers, one as a child
node of the system control and the other as an independent clock controller
node.
This modification involves a major modification to the binding files, so
the reviewed-by tags has been deleted.
Changes in v7:
The patch series is based on v6.7. You can simply review or test the
patches at the link [8].
- fixed initval issue.
- fixed pll clk crash issue.
- fixed warning reported by <lkp@intel.com>
- code optimization as per review comments.
- code cleanup and style improvements as per review comments and checkpatch
with "--strict"
Changes in v6:
The patch series is based on v6.7-rc1. You can simply review or test the
patches at the link [7].
- fixed some warnings/errors reported by kernel test robot <lkp@intel.com>.
Changes in v5:
The patch series is based on v6.7-rc1. You can simply review or test the
patches at the link [6].
- dt-bindings: improved yaml, such as:
- add vendor prefix for system-ctrl property for clock generator.
- Add explanation for system-ctrl property.
- move sophgo,sg2042-clkgen.yaml to directly under clock folder.
- fixed bugs for driver Makefile/Kconfig
- continue cleaning-up debug print for driver code.
Changes in v4:
The patch series is based on v6.7-rc1. You can simply review or test the
patches at the link [5].
- dt-bindings: fixed a dt_binding_check error.
Changes in v3:
The patch series is based on v6.7-rc1. You can simply review or test the
patches at the link [3].
- DTS: don't use syscon but define sg2042 specific system control node. More
background info can read [4].
- Updating minor issues in dt-bindings as per input from reviews.
Changes in v2:
The patch series is based on v6.7-rc1. You can simply review or test the
patches at the link [2].
- Squashed the patch adding clock definitions with the patch adding the
binding for the clock controller.
- Updating dt-binding for syscon, remove oneOf for property compatible;
define clock controller as child of syscon.
- DTS changes: merge sg2042-clock.dtsi into sg2042.dtsi; move clock-frequency
property of osc to board devicethree due to the oscillator is outside the
SoC.
- Fixed some bugs in driver code during testing, including removing warnings
for rv32_defconfig.
- Updated MAINTAINERS info.
Changes in v1:
The patch series is based on v6.7-rc1. You can simply review or test the
patches at the link [1].
Link: https://lore.kernel.org/linux-riscv/cover.1699879741.git.unicorn_wang@outlook.com/ [1]
Link: https://lore.kernel.org/linux-riscv/cover.1701044106.git.unicorn_wang@outlook.com/ [2]
Link: https://lore.kernel.org/linux-riscv/cover.1701691923.git.unicorn_wang@outlook.com/ [3]
Link: https://lore.kernel.org/linux-riscv/MA0P287MB03329AE180378E1A2E034374FE82A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM/ [4]
Link: https://lore.kernel.org/linux-riscv/cover.1701734442.git.unicorn_wang@outlook.com/ [5]
Link: https://lore.kernel.org/linux-riscv/cover.1701938395.git.unicorn_wang@outlook.com/ [6]
Link: https://lore.kernel.org/linux-riscv/cover.1701997033.git.unicorn_wang@outlook.com/ [7]
Link: https://lore.kernel.org/linux-riscv/cover.1704694903.git.unicorn_wang@outlook.com/ [8]
Link: https://lore.kernel.org/linux-riscv/cover.1705388518.git.unicorn_wang@outlook.com/ [9]
Link: https://lore.kernel.org/linux-riscv/cover.1706854074.git.unicorn_wang@outlook.com/ [10]
Link: https://lore.kernel.org/linux-riscv/cover.1708223519.git.unicorn_wang@outlook.com/ [11]
Link: https://lore.kernel.org/linux-riscv/cover.1708397315.git.unicorn_wang@outlook.com/ [12]
---
Chen Wang (5):
dt-bindings: clock: sophgo: add pll clocks for SG2042
dt-bindings: clock: sophgo: add RP gate clocks for SG2042
dt-bindings: clock: sophgo: add clkgen for SG2042
clk: sophgo: Add SG2042 clock driver
riscv: dts: add clock generator for Sophgo SG2042 SoC
.../bindings/clock/sophgo,sg2042-clkgen.yaml | 49 +
.../bindings/clock/sophgo,sg2042-pll.yaml | 45 +
.../bindings/clock/sophgo,sg2042-rpgate.yaml | 43 +
.../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 +
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 49 +-
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/sophgo/Kconfig | 7 +
drivers/clk/sophgo/Makefile | 2 +
drivers/clk/sophgo/clk-sophgo-sg2042.c | 1410 +++++++++++++++++
drivers/clk/sophgo/clk-sophgo-sg2042.h | 216 +++
.../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++
include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 +
.../dt-bindings/clock/sophgo,sg2042-rpgate.h | 58 +
14 files changed, 2017 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml
create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml
create mode 100644 drivers/clk/sophgo/Kconfig
create mode 100644 drivers/clk/sophgo/Makefile
create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c
create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h
create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h
create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h
create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h
base-commit: 4cece764965020c22cff7665b18a012006359095
--
2.25.1
^ permalink raw reply
* Re: [PATCH v3 2/3] clk: qcom: add IPQ9574 interconnect clocks support
From: Varadarajan Narayanan @ 2024-03-27 8:21 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
In-Reply-To: <CAA8EJpq5ng2K_Y481FbsjSXCaGM5_2+xkwWqFzfzXv2ZOBpMgw@mail.gmail.com>
Dmitry,
On Tue, Mar 26, 2024 at 02:37:20PM +0200, Dmitry Baryshkov wrote:
> On Tue, 26 Mar 2024 at 14:14, Varadarajan Narayanan
> <quic_varada@quicinc.com> wrote:
> >
> > Unlike MSM platforms that manage NoC related clocks and scaling
> > from RPM, IPQ SoCs dont involve RPM in managing NoC related
> > clocks and there is no NoC scaling.
> >
> > However, there is a requirement to enable some NoC interface
> > clocks for accessing the peripheral controllers present on
> > these NoCs. Though exposing these as normal clocks would work,
> > having a minimalistic interconnect driver to handle these clocks
> > would make it consistent with other Qualcomm platforms resulting
> > in common code paths. This is similar to msm8996-cbf's usage of
> > icc-clk framework.
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Have posted the next version addressing your comments.
Please review.
Thanks
Varada
^ permalink raw reply
* [PATCH v4 3/3] arm64: dts: qcom: ipq9574: Add icc provider ability to gcc
From: Varadarajan Narayanan @ 2024-03-27 8:18 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan
In-Reply-To: <20240327081850.2924870-1-quic_varada@quicinc.com>
IPQ SoCs dont involve RPM in managing NoC related clocks and
there is no NoC scaling. Linux itself handles these clocks.
However, these should not be exposed as just clocks and align
with other Qualcomm SoCs that handle these clocks from a
interconnect provider.
Hence include icc provider capability to the gcc node so that
peripherals can use the interconnect facility to enable these
clocks.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Fix include file order
Move to separate patch
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 7f2e5cbf3bbb..5b3e69379b1f 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -306,6 +307,7 @@ gcc: clock-controller@1800000 {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ #interconnect-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v4 2/3] clk: qcom: add IPQ9574 interconnect clocks support
From: Varadarajan Narayanan @ 2024-03-27 8:18 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan
In-Reply-To: <20240327081850.2924870-1-quic_varada@quicinc.com>
Unlike MSM platforms that manage NoC related clocks and scaling
from RPM, IPQ SoCs dont involve RPM in managing NoC related
clocks and there is no NoC scaling.
However, there is a requirement to enable some NoC interface
clocks for accessing the peripheral controllers present on
these NoCs. Though exposing these as normal clocks would work,
having a minimalistic interconnect driver to handle these clocks
would make it consistent with other Qualcomm platforms resulting
in common code paths. This is similar to msm8996-cbf's usage of
icc-clk framework.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v4: Use clk_hw instead of indices
Do icc register in qcom_cc_probe() call stream
Add icc clock info to qcom_cc_desc structure
v3: Use indexed identifiers here to avoid confusion
Fix error messages and move to common.c
v2: Move DTS to separate patch
Update commit log
Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK to fix build error
---
drivers/clk/qcom/Kconfig | 2 ++
drivers/clk/qcom/common.c | 34 ++++++++++++++++++++-
drivers/clk/qcom/common.h | 4 ++-
drivers/clk/qcom/gcc-ipq9574.c | 54 ++++++++++++++++++++++++++++++++++
4 files changed, 92 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8ab08e7b5b6c..af73a0b396eb 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -243,6 +243,8 @@ config IPQ_GCC_8074
config IPQ_GCC_9574
tristate "IPQ9574 Global Clock Controller"
+ select INTERCONNECT
+ select INTERCONNECT_CLK
help
Support for global clock controller on ipq9574 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 75f09e6e057e..523d30d0ccbc 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -8,6 +8,8 @@
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
+#include <linux/interconnect-clk.h>
+#include <linux/interconnect-provider.h>
#include <linux/reset-controller.h>
#include <linux/of.h>
@@ -234,6 +236,36 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
}
+static int qcom_cc_icc_register(struct device *dev,
+ const struct qcom_cc_desc *desc)
+{
+#if IS_ENABLED(CONFIG_INTERCONNECT_CLK)
+ struct icc_provider *provider;
+ struct icc_clk_data *icd;
+ int i;
+
+ if (!desc->icc_hws)
+ return 0;
+
+ icd = devm_kcalloc(dev, desc->num_icc_hws, sizeof(*icd), GFP_KERNEL);
+ if (!icd)
+ return dev_err_probe(dev, -ENOMEM, "malloc for icc clock data failed\n");
+
+ for (i = 0; i < desc->num_icc_hws; i++) {
+ icd[i].clk = devm_clk_hw_get_clk(dev, desc->icc_hws[i], "");
+ if (IS_ERR_OR_NULL(icd[i].clk))
+ return dev_err_probe(dev, -ENOENT, "icc clock not found\n");
+ icd[i].name = clk_hw_get_name(desc->icc_hws[i]);
+ }
+
+ provider = icc_clk_register(dev, desc->first_id, desc->num_icc_hws, icd);
+ if (IS_ERR_OR_NULL(provider))
+ return dev_err_probe(dev, PTR_ERR(provider),
+ "icc_clk_register failed\n");
+#endif
+ return 0;
+}
+
int qcom_cc_really_probe(struct platform_device *pdev,
const struct qcom_cc_desc *desc, struct regmap *regmap)
{
@@ -303,7 +335,7 @@ int qcom_cc_really_probe(struct platform_device *pdev,
if (ret)
return ret;
- return 0;
+ return qcom_cc_icc_register(dev, desc);
}
EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 9c8f7b798d9f..3c3a07f6dcb9 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -29,6 +29,9 @@ struct qcom_cc_desc {
size_t num_gdscs;
struct clk_hw **clk_hws;
size_t num_clk_hws;
+ struct clk_hw **icc_hws;
+ size_t num_icc_hws;
+ unsigned int first_id;
};
/**
@@ -65,5 +68,4 @@ extern int qcom_cc_probe(struct platform_device *pdev,
const struct qcom_cc_desc *desc);
extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
const struct qcom_cc_desc *desc);
-
#endif
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 0a3f846695b8..187fd9dcdf49 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -12,6 +12,7 @@
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
@@ -4301,6 +4302,56 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
};
+#define IPQ_APPS_ID 9574 /* some unique value */
+
+enum {
+ ICC_ANOC_PCIE0,
+ ICC_SNOC_PCIE0,
+ ICC_ANOC_PCIE1,
+ ICC_SNOC_PCIE1,
+ ICC_ANOC_PCIE2,
+ ICC_SNOC_PCIE2,
+ ICC_ANOC_PCIE3,
+ ICC_SNOC_PCIE3,
+ ICC_SNOC_USB,
+ ICC_ANOC_USB_AXI,
+ ICC_NSSNOC_NSSCC,
+ ICC_NSSNOC_SNOC_0,
+ ICC_NSSNOC_SNOC_1,
+ ICC_NSSNOC_PCNOC_1,
+ ICC_NSSNOC_QOSGEN_REF,
+ ICC_NSSNOC_TIMEOUT_REF,
+ ICC_NSSNOC_XO_DCD,
+ ICC_NSSNOC_ATB,
+ ICC_MEM_NOC_NSSNOC,
+ ICC_NSSNOC_MEMNOC,
+ ICC_NSSNOC_MEM_NOC_1,
+};
+
+static struct clk_hw *icc_ipq9574_hws[] = {
+ [ICC_ANOC_PCIE0] = &gcc_anoc_pcie0_1lane_m_clk.clkr.hw,
+ [ICC_SNOC_PCIE0] = &gcc_anoc_pcie1_1lane_m_clk.clkr.hw,
+ [ICC_ANOC_PCIE1] = &gcc_anoc_pcie2_2lane_m_clk.clkr.hw,
+ [ICC_SNOC_PCIE1] = &gcc_anoc_pcie3_2lane_m_clk.clkr.hw,
+ [ICC_ANOC_PCIE2] = &gcc_snoc_pcie0_1lane_s_clk.clkr.hw,
+ [ICC_SNOC_PCIE2] = &gcc_snoc_pcie1_1lane_s_clk.clkr.hw,
+ [ICC_ANOC_PCIE3] = &gcc_snoc_pcie2_2lane_s_clk.clkr.hw,
+ [ICC_SNOC_PCIE3] = &gcc_snoc_pcie3_2lane_s_clk.clkr.hw,
+ [ICC_SNOC_USB] = &gcc_snoc_usb_clk.clkr.hw,
+ [ICC_ANOC_USB_AXI] = &gcc_anoc_usb_axi_clk.clkr.hw,
+ [ICC_NSSNOC_NSSCC] = &gcc_nssnoc_nsscc_clk.clkr.hw,
+ [ICC_NSSNOC_SNOC_0] = &gcc_nssnoc_snoc_clk.clkr.hw,
+ [ICC_NSSNOC_SNOC_1] = &gcc_nssnoc_snoc_1_clk.clkr.hw,
+ [ICC_NSSNOC_PCNOC_1] = &gcc_nssnoc_pcnoc_1_clk.clkr.hw,
+ [ICC_NSSNOC_QOSGEN_REF] = &gcc_nssnoc_qosgen_ref_clk.clkr.hw,
+ [ICC_NSSNOC_TIMEOUT_REF] = &gcc_nssnoc_timeout_ref_clk.clkr.hw,
+ [ICC_NSSNOC_XO_DCD] = &gcc_nssnoc_xo_dcd_clk.clkr.hw,
+ [ICC_NSSNOC_ATB] = &gcc_nssnoc_atb_clk.clkr.hw,
+ [ICC_MEM_NOC_NSSNOC] = &gcc_mem_noc_nssnoc_clk.clkr.hw,
+ [ICC_NSSNOC_MEMNOC] = &gcc_nssnoc_memnoc_clk.clkr.hw,
+ [ICC_NSSNOC_MEM_NOC_1] = &gcc_nssnoc_mem_noc_1_clk.clkr.hw,
+};
+
static const struct of_device_id gcc_ipq9574_match_table[] = {
{ .compatible = "qcom,ipq9574-gcc" },
{ }
@@ -4323,6 +4374,9 @@ static const struct qcom_cc_desc gcc_ipq9574_desc = {
.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
.clk_hws = gcc_ipq9574_hws,
.num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
+ .icc_hws = icc_ipq9574_hws,
+ .num_icc_hws = ARRAY_SIZE(icc_ipq9574_hws),
+ .first_id = IPQ_APPS_ID,
};
static int gcc_ipq9574_probe(struct platform_device *pdev)
--
2.34.1
^ permalink raw reply related
* [PATCH v4 1/3] dt-bindings: interconnect: Add Qualcomm IPQ9574 support
From: Varadarajan Narayanan @ 2024-03-27 8:18 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan, Krzysztof Kozlowski
In-Reply-To: <20240327081850.2924870-1-quic_varada@quicinc.com>
Add interconnect-cells to clock provider so that it can be
used as icc provider.
Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
interfaces. This will be used by the gcc-ipq9574 driver
that will for providing interconnect services using the
icc-clk framework.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v3:
Squash Documentation/ and include/ changes into same patch
qcom,ipq9574.h
Move 'first id' to clock driver
---
.../bindings/clock/qcom,ipq9574-gcc.yaml | 3 +
.../dt-bindings/interconnect/qcom,ipq9574.h | 59 +++++++++++++++++++
2 files changed, 62 insertions(+)
create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
index 944a0ea79cd6..824781cbdf34 100644
--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
@@ -33,6 +33,9 @@ properties:
- description: PCIE30 PHY3 pipe clock source
- description: USB3 PHY pipe clock source
+ '#interconnect-cells':
+ const: 1
+
required:
- compatible
- clocks
diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
new file mode 100644
index 000000000000..9c95fbd5dc46
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef INTERCONNECT_QCOM_IPQ9574_H
+#define INTERCONNECT_QCOM_IPQ9574_H
+
+#define MASTER_ANOC_PCIE0_1 0
+#define SLAVE_ANOC_PCIE0_1 1
+#define MASTER_SNOC_PCIE0_1 2
+#define SLAVE_SNOC_PCIE0_1 3
+#define MASTER_ANOC_PCIE1_1 4
+#define SLAVE_ANOC_PCIE1_1 5
+#define MASTER_SNOC_PCIE1_1 6
+#define SLAVE_SNOC_PCIE1_1 7
+#define MASTER_ANOC_PCIE2_2 8
+#define SLAVE_ANOC_PCIE2_2 9
+#define MASTER_SNOC_PCIE2_2 10
+#define SLAVE_SNOC_PCIE2_2 11
+#define MASTER_ANOC_PCIE3_2 12
+#define SLAVE_ANOC_PCIE3_2 13
+#define MASTER_SNOC_PCIE3_2 14
+#define SLAVE_SNOC_PCIE3_2 15
+#define MASTER_USB 16
+#define SLAVE_USB 17
+#define MASTER_USB_AXI 18
+#define SLAVE_USB_AXI 19
+#define MASTER_NSSNOC_NSSCC 20
+#define SLAVE_NSSNOC_NSSCC 21
+#define MASTER_NSSNOC_SNOC 22
+#define SLAVE_NSSNOC_SNOC 23
+#define MASTER_NSSNOC_SNOC_1 24
+#define SLAVE_NSSNOC_SNOC_1 25
+#define MASTER_NSSNOC_PCNOC_1 26
+#define SLAVE_NSSNOC_PCNOC_1 27
+#define MASTER_NSSNOC_QOSGEN_REF 28
+#define SLAVE_NSSNOC_QOSGEN_REF 29
+#define MASTER_NSSNOC_TIMEOUT_REF 30
+#define SLAVE_NSSNOC_TIMEOUT_REF 31
+#define MASTER_NSSNOC_XO_DCD 32
+#define SLAVE_NSSNOC_XO_DCD 33
+#define MASTER_NSSNOC_ATB 34
+#define SLAVE_NSSNOC_ATB 35
+#define MASTER_MEM_NOC_NSSNOC 36
+#define SLAVE_MEM_NOC_NSSNOC 37
+#define MASTER_NSSNOC_MEMNOC 38
+#define SLAVE_NSSNOC_MEMNOC 39
+#define MASTER_NSSNOC_MEM_NOC_1 40
+#define SLAVE_NSSNOC_MEM_NOC_1 41
+
+#define MASTER_NSS_CC_NSSNOC_PPE 0
+#define SLAVE_NSS_CC_NSSNOC_PPE 1
+#define MASTER_NSS_CC_NSSNOC_PPE_CFG 2
+#define SLAVE_NSS_CC_NSSNOC_PPE_CFG 3
+#define MASTER_NSS_CC_NSSNOC_NSS_CSR 4
+#define SLAVE_NSS_CC_NSSNOC_NSS_CSR 5
+#define MASTER_NSS_CC_NSSNOC_IMEM_QSB 6
+#define SLAVE_NSS_CC_NSSNOC_IMEM_QSB 7
+#define MASTER_NSS_CC_NSSNOC_IMEM_AHB 8
+#define SLAVE_NSS_CC_NSSNOC_IMEM_AHB 9
+
+#endif /* INTERCONNECT_QCOM_IPQ9574_H */
--
2.34.1
^ permalink raw reply related
* [PATCH v3 0/3] Add interconnect driver for IPQ9574 SoC
From: Varadarajan Narayanan @ 2024-03-27 8:18 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan
MSM platforms manage NoC related clocks and scaling from RPM.
However, in IPQ SoCs, RPM is not involved in managing NoC
related clocks and there is no NoC scaling.
However, there is a requirement to enable some NoC interface
clocks for the accessing the peripherals present in the
system. Hence add a minimalistic interconnect driver that
establishes a path from the processor/memory to those peripherals
and vice versa.
---
v4:
gcc-ipq9574.c
Use clk_hw instead of indices
common.c
Do icc register in qcom_cc_probe() call stream
common.h
Add icc clock info to qcom_cc_desc structure
v3:
qcom,ipq9574.h
Move 'first id' define to clock driver
gcc-ipq9574.c:
Use indexed identifiers here to avoid confusion
Fix error messages and move code to common.c as it can be
shared with future SoCs
v2:
qcom,ipq9574.h
Fix license identifier
Rename macros
qcom,ipq9574-gcc.yaml
Include interconnect-cells
gcc-ipq9574.c
Update commit log
Remove IS_ENABLED(CONFIG_INTERCONNECT) and auto select it from Kconfig
ipq9574.dtsi
Moved to separate patch
Include interconnect-cells to clock controller node
drivers/clk/qcom/Kconfig:
Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK
Varadarajan Narayanan (3):
dt-bindings: interconnect: Add Qualcomm IPQ9574 support
clk: qcom: add IPQ9574 interconnect clocks support
arm64: dts: qcom: ipq9574: Add icc provider ability to gcc
.../bindings/clock/qcom,ipq9574-gcc.yaml | 3 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 +
drivers/clk/qcom/Kconfig | 2 +
drivers/clk/qcom/common.c | 34 ++++++++++-
drivers/clk/qcom/common.h | 4 +-
drivers/clk/qcom/gcc-ipq9574.c | 54 +++++++++++++++++
.../dt-bindings/interconnect/qcom,ipq9574.h | 59 +++++++++++++++++++
7 files changed, 156 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
--
2.34.1
^ permalink raw reply
* Re: [RFC PATCH 07/13] pinctrl: renesas: pinctrl-rzg2l: Validate power registers for SD and ETH
From: Lad, Prabhakar @ 2024-03-27 8:13 UTC (permalink / raw)
To: Dan Carpenter
Cc: Geert Uytterhoeven, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-renesas-soc,
linux-gpio, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
In-Reply-To: <a0d7e6f4-5f4d-4601-857a-c485cceffe3b@moroto.mountain>
Hi Dan,
Thank you for the review.
On Wed, Mar 27, 2024 at 7:58 AM Dan Carpenter <dan.carpenter@linaro.org> wrote:
>
> On Tue, Mar 26, 2024 at 10:28:38PM +0000, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist,
> > resulting in invalid register offsets. Ensure that the register offsets
> > are valid before any read/write operations are performed. If the power
> ^^^^^^^^^^^^
> > registers are not available, both SD and ETH will be set to -EINVAL.
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> Where does this happen? It doesn't seem to be a part of this patchset.
> -EINVAL seems weird here, but it's hard to judge without actually seeing
> it.
>
Good catch, in patch 13/13 it should be below instead of sd_ch and
eth_poc assigned to 0.
+static const struct rzg2l_hwcfg rzv2h_hwcfg = {
+ .regs = {
+ .pwpr = 0x3c04,
+ .sd_ch = -EINVAL,
+ .eth_poc = -EINVAL,
+ },
+};
Cheers,
Prabhakar
^ permalink raw reply
* Re: [PATCH v2 6/6] misc: pci_endpoint_test: Add Device ID for R-Car V4H PCIe controller
From: Geert Uytterhoeven @ 2024-03-27 8:11 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Frank Li, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org,
bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, mani@kernel.org,
marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Geert Uytterhoeven
In-Reply-To: <TYCPR01MB1104072DA4D6B3DF120A10D0AD8352@TYCPR01MB11040.jpnprd01.prod.outlook.com>
Hi Shimoda-san,
On Tue, Mar 26, 2024 at 6:47 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Frank Li, Sent: Tuesday, March 26, 2024 12:21 PM
> > On Tue, Mar 26, 2024 at 11:45:40AM +0900, Yoshihiro Shimoda wrote:
> > > Add Renesas R8A779G0 in pci_device_id table so that pci-epf-test
> > > can be used for testing PCIe EP on R-Car V4H.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > ---
> > > drivers/misc/pci_endpoint_test.c | 4 ++++
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
> > > index c38a6083f0a7..2fa3c6473c7d 100644
> > > --- a/drivers/misc/pci_endpoint_test.c
> > > +++ b/drivers/misc/pci_endpoint_test.c
> > > @@ -83,6 +83,7 @@
> > > #define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
> > > #define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
> > > #define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031
> > > +#define PCI_DEVICE_ID_RENESAS_R8A779G0 0x0030
> > >
> > > static DEFINE_IDA(pci_endpoint_test_ida);
> > >
> > > @@ -1005,6 +1006,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
> > > { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0),
> > > .driver_data = (kernel_ulong_t)&default_data,
> > > },
> > > + { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779G0),
> > > + .driver_data = (kernel_ulong_t)&default_data,
> > > + },
> >
> > You use default_data, why need new device_id? I think you can use 0x0031
> > to do test.
>
> I thought we can add a new device_id freely like other devices.
> Since the PCIe controller's endpoint mode can configure the device id,
> I can use 0x0031 to do test though.
Can it? The documentation for the PCICONF0Fi register states both the
DEVICE_ID and VENDOR_ID bits are read-only.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 2/4] dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIH0108 and PMD8028 support
From: Krzysztof Kozlowski @ 2024-03-27 8:10 UTC (permalink / raw)
To: Anjelique Melendez, andersson, konrad.dybcio, linus.walleij,
robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: linux-arm-msm, linux-gpio, devicetree, linux-kernel,
quic_subbaram, quic_collinsd, quic_jprakash
In-Reply-To: <20240326220628.2392802-3-quic_amelende@quicinc.com>
On 26/03/2024 23:06, Anjelique Melendez wrote:
> Update the Qualcomm Technologies, Inc. PMIC GPIO binding documentation
> to include compatible strings for PMIH0108 and PMD8028 PMICs.
>
> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 4/4] dt-bindings: arm: keystone: Remove ti,system-reboot-controller property
From: Krzysztof Kozlowski @ 2024-03-27 8:08 UTC (permalink / raw)
To: Andrew Davis, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Santosh Shilimkar, Nishanth Menon, Vignesh Raghavendra
Cc: devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20240326223730.54639-5-afd@ti.com>
On 26/03/2024 23:37, Andrew Davis wrote:
> This property was only ever used in one device. It is no longer needed as
> what it signaled is now default. Remove this unneeded/unused property.
>
> Signed-off-by: Andrew Davis <afd@ti.com>
> ---
> Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml | 5 -----
> 1 file changed, 5 deletions(-)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH] media: dt-bindings: ovti,ov2680: Document clock/data-lanes
From: Krzysztof Kozlowski @ 2024-03-27 8:07 UTC (permalink / raw)
To: Fabio Estevam, sakari.ailus
Cc: rmfrfs, robh, krzysztof.kozlowski+dt, conor+dt, linux-media,
devicetree, Fabio Estevam
In-Reply-To: <20240326231033.2048193-1-festevam@gmail.com>
On 27/03/2024 00:10, Fabio Estevam wrote:
> + properties:
> + endpoint:
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + const: 0
> +
> + data-lanes:
> + const: 1
>
> required:
> - compatible
> @@ -65,7 +78,7 @@ required:
> - reset-gpios
> - port
>
> -additionalProperties: false
> +unevaluatedProperties: false
This looks like unrelated change and it needs its own explanation.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [RFC PATCH 07/13] pinctrl: renesas: pinctrl-rzg2l: Validate power registers for SD and ETH
From: Dan Carpenter @ 2024-03-27 7:58 UTC (permalink / raw)
To: Prabhakar
Cc: Geert Uytterhoeven, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-renesas-soc,
linux-gpio, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
In-Reply-To: <20240326222844.1422948-8-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Tue, Mar 26, 2024 at 10:28:38PM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist,
> resulting in invalid register offsets. Ensure that the register offsets
> are valid before any read/write operations are performed. If the power
^^^^^^^^^^^^
> registers are not available, both SD and ETH will be set to -EINVAL.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Where does this happen? It doesn't seem to be a part of this patchset.
-EINVAL seems weird here, but it's hard to judge without actually seeing
it.
regards,
dan carpenter
^ permalink raw reply
* [PATCH v5 0/2] ASoC: nau8325: Modify driver code and dtschema.
From: Seven Lee @ 2024-03-27 7:57 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, alsa-devel, devicetree, linux-sound,
krzysztof.kozlowski+dt, linux-kernel, robh+dt, conor+dt, perex,
tiwai, YHCHuang, KCHSU0, CTLIN0, SJLIN0, wtli, scott6986,
supercraig0719, dardar923
Revise properties description and use standard units in dtschema.
The unit conversion driver based on the attribute must also be
changed accordingly.
Change:
V1 -> V2:
- Revise the driver description part for the C++ comment.
- In the nau8325_clkdet_put function, modify the max variable to hard code.
- Removed "Clock Detection" switch control.
- modify the "ALC Enable" switch name.
- Revise the dtschema for "nuvoton,dac-vref".
V2 -> V3:
- Properties use standard unit suffixes.
- Modify the enum definition.
- Driver code should be used dev_dbg().
V3 -> V4:
- Properties use standard unit suffixes.
- Modify the enum definition.
V4->V5:
- Properties use standard unit suffixes for vref-impedance and dac-vref.
- Revise the enum definition.
- Modify the code related to properties usage in the NAU8325 codec driver.
- Re-arrange header files in alphabetical order.
Seven Lee (2):
ASoC: dt-bindings: Added schema for "nuvoton,nau8325"
ASoC: nau8325: new driver
.../bindings/sound/nuvoton,nau8325.yaml | 80 ++
sound/soc/codecs/nau8325.c | 893 ++++++++++++++++++
sound/soc/codecs/nau8325.h | 391 ++++++++
3 files changed, 1364 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/nuvoton,nau8325.yaml
create mode 100644 sound/soc/codecs/nau8325.c
create mode 100644 sound/soc/codecs/nau8325.h
--
2.25.1
^ permalink raw reply
* [PATCH v5 2/2] ASoC: nau8325: new driver
From: Seven Lee @ 2024-03-27 7:57 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, alsa-devel, devicetree, linux-sound,
krzysztof.kozlowski+dt, linux-kernel, robh+dt, conor+dt, perex,
tiwai, YHCHuang, KCHSU0, CTLIN0, SJLIN0, wtli, scott6986,
supercraig0719, dardar923
In-Reply-To: <20240327075755.3410381-1-wtli@nuvoton.com>
The driver is for amplifiers NAU8325 of Nuvoton Technology Corporation.
The NAU8325 is a stereo high efficiency filter-free Class-D audio
amplifier, which is capable of driving a 4ohm load with up to 3W output
power.
Signed-off-by: Seven Lee <wtli@nuvoton.com>
---
sound/soc/codecs/nau8325.c | 893 +++++++++++++++++++++++++++++++++++++
sound/soc/codecs/nau8325.h | 391 ++++++++++++++++
2 files changed, 1284 insertions(+)
create mode 100644 sound/soc/codecs/nau8325.c
create mode 100644 sound/soc/codecs/nau8325.h
diff --git a/sound/soc/codecs/nau8325.c b/sound/soc/codecs/nau8325.c
new file mode 100644
index 000000000000..a00a30364c89
--- /dev/null
+++ b/sound/soc/codecs/nau8325.c
@@ -0,0 +1,893 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// nau8325.c -- Nuvoton NAU8325 audio codec driver
+//
+// Copyright 2023 Nuvoton Technology Crop.
+// Author: Seven Lee <WTLI@nuvoton.com>
+// David Lin <CTLIN0@nuvoton.com>
+//
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+#include "nau8325.h"
+
+/* Range of Master Clock MCLK (Hz) */
+#define MASTER_CLK_MAX 49152000
+#define MASTER_CLK_MIN 2048000
+
+/* scaling for MCLK source */
+#define CLK_PROC_BYPASS (-1)
+
+/* the maximum CLK_DAC */
+#define CLK_DA_AD_MAX 6144000
+
+/* from MCLK input */
+#define MCLK_SRC 4
+
+static const struct nau8325_src_attr mclk_n1_div[] = {
+ { 1, 0x0 },
+ { 2, 0x1 },
+ { 3, 0x2 },
+};
+
+/* over sampling rate */
+static const struct nau8325_osr_attr osr_dac_sel[] = {
+ { 64, 2 }, /* OSR 64, SRC 1/4 */
+ { 256, 0 }, /* OSR 256, SRC 1 */
+ { 128, 1 }, /* OSR 128, SRC 1/2 */
+ { 0, 0 },
+ { 32, 3 }, /* OSR 32, SRC 1/8 */
+};
+
+static const struct nau8325_src_attr mclk_n2_div[] = {
+ { 0, 0x0 },
+ { 1, 0x1 },
+ { 2, 0x2 },
+ { 3, 0x3 },
+ { 4, 0x4 },
+};
+
+static const struct nau8325_src_attr mclk_n3_mult[] = {
+ { 0, 0x1 },
+ { 1, 0x2 },
+ { 2, 0x3 },
+ { 3, 0x4 },
+};
+
+/* Sample Rate and MCLK_SRC selections */
+static const struct nau8325_srate_attr target_srate_table[] = {
+ /* { FS, range, max, { MCLK source }} */
+ { 48000, 2, true, { 12288000, 19200000, 24000000 } },
+ { 16000, 1, false, { 4096000, 6400000, 8000000 } },
+ { 8000, 0, false, { 2048000, 3200000, 4000000 }},
+ { 44100, 2, true, { 11289600, 17640000, 22050000 }},
+ { 64000, 3, false, { 16384000, 25600000, 32000000 } },
+ { 96000, 3, true, { 24576000, 38400000, 48000000 } },
+ { 12000, 0, true, { 3072000, 4800000, 6000000 } },
+ { 24000, 1, true, { 6144000, 9600000, 12000000 } },
+ { 32000, 2, false, { 8192000, 12800000, 16000000 } },
+};
+
+static const struct reg_default nau8325_reg_defaults[] = {
+ { NAU8325_R00_HARDWARE_RST, 0x0000 },
+ { NAU8325_R01_SOFTWARE_RST, 0x0000 },
+ { NAU8325_R03_CLK_CTRL, 0x0000 },
+ { NAU8325_R04_ENA_CTRL, 0x0000 },
+ { NAU8325_R05_INTERRUPT_CTRL, 0x007f },
+ { NAU8325_R09_IRQOUT, 0x0000 },
+ { NAU8325_R0A_IO_CTRL, 0x0000 },
+ { NAU8325_R0B_PDM_CTRL, 0x0000 },
+ { NAU8325_R0C_TDM_CTRL, 0x0000 },
+ { NAU8325_R0D_I2S_PCM_CTRL1, 0x000a },
+ { NAU8325_R0E_I2S_PCM_CTRL2, 0x0000 },
+ { NAU8325_R0F_L_TIME_SLOT, 0x0000 },
+ { NAU8325_R10_R_TIME_SLOT, 0x0000 },
+ { NAU8325_R11_HPF_CTRL, 0x0000 },
+ { NAU8325_R12_MUTE_CTRL, 0x0000 },
+ { NAU8325_R13_DAC_VOLUME, 0xf3f3 },
+ { NAU8325_R29_DAC_CTRL1, 0x0081 },
+ { NAU8325_R2A_DAC_CTRL2, 0x0000 },
+ { NAU8325_R2C_ALC_CTRL1, 0x000e },
+ { NAU8325_R2D_ALC_CTRL2, 0x8400 },
+ { NAU8325_R2E_ALC_CTRL3, 0x0000 },
+ { NAU8325_R2F_ALC_CTRL4, 0x003f },
+ { NAU8325_R40_CLK_DET_CTRL, 0xa801 },
+ { NAU8325_R50_MIXER_CTRL, 0x0000 },
+ { NAU8325_R55_MISC_CTRL, 0x0000 },
+ { NAU8325_R60_BIAS_ADJ, 0x0000 },
+ { NAU8325_R61_ANALOG_CONTROL_1, 0x0000 },
+ { NAU8325_R62_ANALOG_CONTROL_2, 0x0000 },
+ { NAU8325_R63_ANALOG_CONTROL_3, 0x0000 },
+ { NAU8325_R64_ANALOG_CONTROL_4, 0x0000 },
+ { NAU8325_R65_ANALOG_CONTROL_5, 0x0000 },
+ { NAU8325_R66_ANALOG_CONTROL_6, 0x0000 },
+ { NAU8325_R69_CLIP_CTRL, 0x0000 },
+ { NAU8325_R73_RDAC, 0x0008 },
+};
+
+static bool nau8325_readable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case NAU8325_R02_DEVICE_ID ... NAU8325_R06_INT_CLR_STATUS:
+ case NAU8325_R09_IRQOUT ... NAU8325_R13_DAC_VOLUME:
+ case NAU8325_R1D_DEBUG_READ1:
+ case NAU8325_R1F_DEBUG_READ2:
+ case NAU8325_R22_DEBUG_READ3:
+ case NAU8325_R29_DAC_CTRL1 ... NAU8325_R2A_DAC_CTRL2:
+ case NAU8325_R2C_ALC_CTRL1 ... NAU8325_R2F_ALC_CTRL4:
+ case NAU8325_R40_CLK_DET_CTRL:
+ case NAU8325_R49_TEST_STATUS ... NAU8325_R4A_ANALOG_READ:
+ case NAU8325_R50_MIXER_CTRL:
+ case NAU8325_R55_MISC_CTRL:
+ case NAU8325_R60_BIAS_ADJ ... NAU8325_R66_ANALOG_CONTROL_6:
+ case NAU8325_R69_CLIP_CTRL:
+ case NAU8325_R73_RDAC:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool nau8325_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case NAU8325_R00_HARDWARE_RST:
+ case NAU8325_R03_CLK_CTRL ... NAU8325_R06_INT_CLR_STATUS:
+ case NAU8325_R09_IRQOUT ... NAU8325_R13_DAC_VOLUME:
+ case NAU8325_R29_DAC_CTRL1 ... NAU8325_R2A_DAC_CTRL2:
+ case NAU8325_R2C_ALC_CTRL1 ... NAU8325_R2F_ALC_CTRL4:
+ case NAU8325_R40_CLK_DET_CTRL:
+ case NAU8325_R50_MIXER_CTRL:
+ case NAU8325_R55_MISC_CTRL:
+ case NAU8325_R60_BIAS_ADJ ... NAU8325_R66_ANALOG_CONTROL_6:
+ case NAU8325_R69_CLIP_CTRL:
+ case NAU8325_R73_RDAC:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool nau8325_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case NAU8325_R00_HARDWARE_RST ... NAU8325_R02_DEVICE_ID:
+ case NAU8325_R06_INT_CLR_STATUS:
+ case NAU8325_R1D_DEBUG_READ1:
+ case NAU8325_R1F_DEBUG_READ2:
+ case NAU8325_R22_DEBUG_READ3:
+ case NAU8325_R4A_ANALOG_READ:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static const char * const nau8325_dac_oversampl[] = {
+ "64", "256", "128", "", "32" };
+
+static const struct soc_enum nau8325_dac_oversampl_enum =
+ SOC_ENUM_SINGLE(NAU8325_R29_DAC_CTRL1, NAU8325_DAC_OVERSAMPLE_SFT,
+ ARRAY_SIZE(nau8325_dac_oversampl),
+ nau8325_dac_oversampl);
+
+static const DECLARE_TLV_DB_MINMAX_MUTE(dac_vol_tlv, -8000, 600);
+
+static const struct snd_kcontrol_new nau8325_snd_controls[] = {
+ SOC_ENUM("DAC Oversampling Rate", nau8325_dac_oversampl_enum),
+ SOC_DOUBLE_TLV("Speaker Volume", NAU8325_R13_DAC_VOLUME,
+ NAU8325_DAC_VOLUME_L_SFT, NAU8325_DAC_VOLUME_R_SFT,
+ NAU8325_DAC_VOLUME_R_EN, 0, dac_vol_tlv),
+ SOC_SINGLE("ALC Max Gain", NAU8325_R2C_ALC_CTRL1,
+ NAU8325_ALC_MAXGAIN_SFT, NAU8325_ALC_MAXGAIN_MAX, 0),
+ SOC_SINGLE("ALC Min Gain", NAU8325_R2C_ALC_CTRL1,
+ NAU8325_ALC_MINGAIN_SFT, NAU8325_ALC_MINGAIN_MAX, 0),
+ SOC_SINGLE("ALC Decay Timer", NAU8325_R2D_ALC_CTRL2,
+ NAU8325_ALC_DCY_SFT, NAU8325_ALC_DCY_MAX, 0),
+ SOC_SINGLE("ALC Attack Timer", NAU8325_R2D_ALC_CTRL2,
+ NAU8325_ALC_ATK_SFT, NAU8325_ALC_ATK_MAX, 0),
+ SOC_SINGLE("ALC Hold Time", NAU8325_R2D_ALC_CTRL2,
+ NAU8325_ALC_HLD_SFT, NAU8325_ALC_HLD_MAX, 0),
+ SOC_SINGLE("ALC Target Level", NAU8325_R2D_ALC_CTRL2,
+ NAU8325_ALC_LVL_SFT, NAU8325_ALC_LVL_MAX, 0),
+ SOC_SINGLE("ALC Enable Switch", NAU8325_R2E_ALC_CTRL3,
+ NAU8325_ALC_EN_SFT, 1, 0),
+};
+
+static int nau8325_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_component *component =
+ snd_soc_dapm_to_component(w->dapm);
+ struct nau8325 *nau8325 = snd_soc_component_get_drvdata(component);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ regmap_update_bits(nau8325->regmap, NAU8325_R12_MUTE_CTRL,
+ NAU8325_SOFT_MUTE, 0);
+ msleep(30);
+ break;
+ case SND_SOC_DAPM_PRE_PMD:
+ /* Soft mute the output to prevent the pop noise. */
+ regmap_update_bits(nau8325->regmap, NAU8325_R12_MUTE_CTRL,
+ NAU8325_SOFT_MUTE, NAU8325_SOFT_MUTE);
+ msleep(30);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int nau8325_powerup_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_component *component =
+ snd_soc_dapm_to_component(w->dapm);
+ struct nau8325 *nau8325 = snd_soc_component_get_drvdata(component);
+
+ if (nau8325->clock_detection)
+ return 0;
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ regmap_update_bits(nau8325->regmap, NAU8325_R40_CLK_DET_CTRL,
+ NAU8325_PWRUP_DFT, NAU8325_PWRUP_DFT);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ regmap_update_bits(nau8325->regmap, NAU8325_R40_CLK_DET_CTRL,
+ NAU8325_PWRUP_DFT, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget nau8325_dapm_widgets[] = {
+ SND_SOC_DAPM_SUPPLY("Power Up", SND_SOC_NOPM, 0, 0,
+ nau8325_powerup_event, SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_DAC_E("DACL", NULL, NAU8325_R04_ENA_CTRL,
+ NAU8325_DAC_LEFT_CH_EN_SFT, 0, nau8325_dac_event,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+ SND_SOC_DAPM_DAC_E("DACR", NULL, NAU8325_R04_ENA_CTRL,
+ NAU8325_DAC_RIGHT_CH_EN_SFT, 0, nau8325_dac_event,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+ SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
+
+ SND_SOC_DAPM_OUTPUT("SPKL"),
+ SND_SOC_DAPM_OUTPUT("SPKR"),
+};
+
+static const struct snd_soc_dapm_route nau8325_dapm_routes[] = {
+ { "DACL", NULL, "Power Up" },
+ { "DACR", NULL, "Power Up" },
+
+ { "DACL", NULL, "AIFRX" },
+ { "DACR", NULL, "AIFRX" },
+ { "SPKL", NULL, "DACL" },
+ { "SPKR", NULL, "DACR" },
+};
+
+static int nau8325_srate_clk_apply(struct nau8325 *nau8325,
+ const struct nau8325_srate_attr *srate_table,
+ int n1_sel, int mclk_mult_sel, int n2_sel)
+{
+ if (!srate_table || n2_sel < 0 || n2_sel >= ARRAY_SIZE(mclk_n2_div) ||
+ n1_sel < 0 || n1_sel >= ARRAY_SIZE(mclk_n1_div)) {
+ dev_dbg(nau8325->dev, "The CLK isn't supported.");
+ return -EINVAL;
+ }
+
+ regmap_update_bits(nau8325->regmap, NAU8325_R40_CLK_DET_CTRL,
+ NAU8325_REG_SRATE_MASK | NAU8325_REG_DIV_MAX,
+ (srate_table->range << NAU8325_REG_SRATE_SFT) |
+ (srate_table->max ? NAU8325_REG_DIV_MAX : 0));
+ regmap_update_bits(nau8325->regmap, NAU8325_R03_CLK_CTRL,
+ NAU8325_MCLK_SRC_MASK, mclk_n2_div[n2_sel].val);
+ regmap_update_bits(nau8325->regmap, NAU8325_R03_CLK_CTRL,
+ NAU8325_CLK_MUL_SRC_MASK,
+ mclk_n1_div[n1_sel].val << NAU8325_CLK_MUL_SRC_SFT);
+
+ if (mclk_mult_sel != CLK_PROC_BYPASS) {
+ regmap_update_bits(nau8325->regmap, NAU8325_R03_CLK_CTRL,
+ NAU8325_MCLK_SEL_MASK,
+ mclk_n3_mult[mclk_mult_sel].val <<
+ NAU8325_MCLK_SEL_SFT);
+ } else {
+ regmap_update_bits(nau8325->regmap, NAU8325_R03_CLK_CTRL,
+ NAU8325_MCLK_SEL_MASK, 0);
+ }
+
+ switch (mclk_mult_sel) {
+ case 2:
+ regmap_update_bits(nau8325->regmap, NAU8325_R65_ANALOG_CONTROL_5,
+ NAU8325_MCLK4XEN_EN, NAU8325_MCLK4XEN_EN);
+ break;
+ case 3:
+ regmap_update_bits(nau8325->regmap, NAU8325_R65_ANALOG_CONTROL_5,
+ NAU8325_MCLK4XEN_EN | NAU8325_MCLK8XEN_EN,
+ NAU8325_MCLK4XEN_EN | NAU8325_MCLK8XEN_EN);
+ break;
+ default:
+ regmap_update_bits(nau8325->regmap, NAU8325_R65_ANALOG_CONTROL_5,
+ NAU8325_MCLK4XEN_EN | NAU8325_MCLK8XEN_EN, 0);
+ break;
+ }
+
+ return 0;
+}
+
+static int nau8325_clksrc_n2(struct nau8325 *nau8325,
+ const struct nau8325_srate_attr *srate_table,
+ int mclk, int *n2_sel)
+{
+ int i, mclk_src, ratio;
+
+ ratio = NAU8325_MCLK_FS_RATIO_NUM;
+ for (i = 0; i < ARRAY_SIZE(mclk_n2_div); i++) {
+ mclk_src = mclk >> mclk_n2_div[i].param;
+ if (srate_table->mclk_src[NAU8325_MCLK_FS_RATIO_256] == mclk_src) {
+ ratio = NAU8325_MCLK_FS_RATIO_256;
+ break;
+ } else if (srate_table->mclk_src[NAU8325_MCLK_FS_RATIO_400] == mclk_src) {
+ ratio = NAU8325_MCLK_FS_RATIO_400;
+ break;
+ } else if (srate_table->mclk_src[NAU8325_MCLK_FS_RATIO_500] == mclk_src) {
+ ratio = NAU8325_MCLK_FS_RATIO_500;
+ break;
+ }
+ }
+ if (ratio != NAU8325_MCLK_FS_RATIO_NUM)
+ *n2_sel = i;
+
+ return ratio;
+}
+
+static const struct nau8325_srate_attr *target_srate_attribute(int srate)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(target_srate_table); i++)
+ if (target_srate_table[i].fs == srate)
+ break;
+
+ if (i == ARRAY_SIZE(target_srate_table))
+ goto proc_err;
+
+ return &target_srate_table[i];
+
+proc_err:
+ return NULL;
+}
+
+static int nau8325_clksrc_choose(struct nau8325 *nau8325,
+ const struct nau8325_srate_attr **srate_table,
+ int *n1_sel, int *mult_sel, int *n2_sel)
+{
+ int i, j, mclk, mclk_max, ratio, ratio_sel, n2_max;
+
+ if (!nau8325->mclk || !nau8325->fs)
+ goto proc_err;
+
+ /* select sampling rate and MCLK_SRC */
+ *srate_table = target_srate_attribute(nau8325->fs);
+ if (!*srate_table)
+ goto proc_err;
+
+ /* First check clock from MCLK directly, decide N2 for MCLK_SRC.
+ * If not good, consider 1/N1 and Multiplier.
+ */
+ ratio = nau8325_clksrc_n2(nau8325, *srate_table, nau8325->mclk, n2_sel);
+ if (ratio != NAU8325_MCLK_FS_RATIO_NUM) {
+ *n1_sel = 0;
+ *mult_sel = CLK_PROC_BYPASS;
+ *n2_sel = MCLK_SRC;
+ goto proc_done;
+ }
+
+ /* Get MCLK_SRC through 1/N, Multiplier, and then 1/N2. */
+ mclk_max = 0;
+ for (i = 0; i < ARRAY_SIZE(mclk_n1_div); i++) {
+ for (j = 0; j < ARRAY_SIZE(mclk_n3_mult); j++) {
+ mclk = nau8325->mclk << mclk_n3_mult[j].param;
+ mclk = mclk / mclk_n1_div[i].param;
+ ratio = nau8325_clksrc_n2(nau8325,
+ *srate_table, mclk, n2_sel);
+ if (ratio != NAU8325_MCLK_FS_RATIO_NUM &&
+ (mclk_max < mclk || i > *n1_sel)) {
+ mclk_max = mclk;
+ n2_max = *n2_sel;
+ *n1_sel = i;
+ *mult_sel = j;
+ ratio_sel = ratio;
+ goto proc_done;
+ }
+ }
+ }
+ if (mclk_max) {
+ *n2_sel = n2_max;
+ ratio = ratio_sel;
+ goto proc_done;
+ }
+
+proc_err:
+ dev_dbg(nau8325->dev, "The MCLK %d is invalid. It can't get MCLK_SRC of 256/400/500 FS (%d)",
+ nau8325->mclk, nau8325->fs);
+ return -EINVAL;
+proc_done:
+ dev_dbg(nau8325->dev, "nau8325->fs=%d,range=0x%x, %s, (n1,mu,n2,dmu):(%d,%d,%d), MCLK_SRC=%uHz (%d)",
+ nau8325->fs, (*srate_table)->range,
+ (*srate_table)->max ? "MAX" : "MIN",
+ *n1_sel == CLK_PROC_BYPASS ?
+ CLK_PROC_BYPASS : mclk_n1_div[*n1_sel].param,
+ *mult_sel == CLK_PROC_BYPASS ?
+ CLK_PROC_BYPASS : 1 << mclk_n3_mult[*mult_sel].param,
+ 1 << mclk_n2_div[*n2_sel].param,
+ (*srate_table)->mclk_src[ratio],
+ (*srate_table)->mclk_src[ratio] / nau8325->fs);
+
+ return 0;
+}
+
+static int nau8325_clock_config(struct nau8325 *nau8325)
+{
+ const struct nau8325_srate_attr *srate_table;
+ int ret, n1_sel, mult_sel, n2_sel;
+
+ ret = nau8325_clksrc_choose(nau8325, &srate_table,
+ &n1_sel, &mult_sel, &n2_sel);
+ if (ret)
+ goto err;
+
+ ret = nau8325_srate_clk_apply(nau8325, srate_table,
+ n1_sel, mult_sel, n2_sel);
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ return ret;
+}
+
+static const struct nau8325_osr_attr *nau8325_get_osr(struct nau8325 *nau8325)
+{
+ unsigned int osr;
+
+ regmap_read(nau8325->regmap, NAU8325_R29_DAC_CTRL1, &osr);
+ osr &= NAU8325_DAC_OVERSAMPLE_MASK;
+ if (osr >= ARRAY_SIZE(osr_dac_sel))
+ return NULL;
+
+ return &osr_dac_sel[osr];
+}
+
+static int nau8325_dai_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_component *component = dai->component;
+ struct nau8325 *nau8325 = snd_soc_component_get_drvdata(component);
+ const struct nau8325_osr_attr *osr;
+
+ osr = nau8325_get_osr(nau8325);
+ if (!osr || !osr->osr)
+ return -EINVAL;
+
+ return snd_pcm_hw_constraint_minmax(substream->runtime,
+ SNDRV_PCM_HW_PARAM_RATE,
+ 0, CLK_DA_AD_MAX / osr->osr);
+}
+
+static int nau8325_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_component *component = dai->component;
+ struct nau8325 *nau8325 = snd_soc_component_get_drvdata(component);
+ unsigned int val_len = 0;
+ const struct nau8325_osr_attr *osr;
+ int ret;
+
+ nau8325->fs = params_rate(params);
+ osr = nau8325_get_osr(nau8325);
+ if (!osr || !osr->osr || nau8325->fs * osr->osr > CLK_DA_AD_MAX) {
+ ret = -EINVAL;
+ goto err;
+ }
+ regmap_update_bits(nau8325->regmap, NAU8325_R03_CLK_CTRL,
+ NAU8325_CLK_DAC_SRC_MASK,
+ osr->clk_src << NAU8325_CLK_DAC_SRC_SFT);
+
+ ret = nau8325_clock_config(nau8325);
+ if (ret)
+ goto err;
+
+ switch (params_width(params)) {
+ case 16:
+ val_len |= NAU8325_I2S_DL_16;
+ break;
+ case 20:
+ val_len |= NAU8325_I2S_DL_20;
+ break;
+ case 24:
+ val_len |= NAU8325_I2S_DL_24;
+ break;
+ case 32:
+ val_len |= NAU8325_I2S_DL_32;
+ break;
+ default:
+ ret = -EINVAL;
+ goto err;
+ }
+
+ regmap_update_bits(nau8325->regmap, NAU8325_R0D_I2S_PCM_CTRL1,
+ NAU8325_I2S_DL_MASK, val_len);
+
+ return 0;
+
+err:
+ return ret;
+}
+
+static int nau8325_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct snd_soc_component *component = dai->component;
+ struct nau8325 *nau8325 = snd_soc_component_get_drvdata(component);
+ unsigned int ctrl1_val = 0;
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBC_CFC:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ ctrl1_val |= NAU8325_I2S_BP_INV;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ ctrl1_val |= NAU8325_I2S_DF_I2S;
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ ctrl1_val |= NAU8325_I2S_DF_LEFT;
+ break;
+ case SND_SOC_DAIFMT_RIGHT_J:
+ ctrl1_val |= NAU8325_I2S_DF_RIGTH;
+ break;
+ case SND_SOC_DAIFMT_DSP_A:
+ ctrl1_val |= NAU8325_I2S_DF_PCM_AB;
+ break;
+ case SND_SOC_DAIFMT_DSP_B:
+ ctrl1_val |= NAU8325_I2S_DF_PCM_AB;
+ ctrl1_val |= NAU8325_I2S_PCMB_EN;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(nau8325->regmap, NAU8325_R0D_I2S_PCM_CTRL1,
+ NAU8325_I2S_DF_MASK | NAU8325_I2S_BP_MASK |
+ NAU8325_I2S_PCMB_EN, ctrl1_val);
+
+ return 0;
+}
+
+static int nau8325_set_sysclk(struct snd_soc_component *component, int clk_id,
+ int source, unsigned int freq, int dir)
+{
+ struct nau8325 *nau8325 = snd_soc_component_get_drvdata(component);
+
+ if (freq < MASTER_CLK_MIN || freq > MASTER_CLK_MAX) {
+ dev_dbg(nau8325->dev, "MCLK exceeds the range, MCLK:%d", freq);
+ return -EINVAL;
+ }
+
+ nau8325->mclk = freq;
+ dev_dbg(nau8325->dev, "MCLK %dHz", nau8325->mclk);
+
+ return 0;
+}
+
+static const struct snd_soc_component_driver nau8325_component_driver = {
+ .set_sysclk = nau8325_set_sysclk,
+ .suspend_bias_off = true,
+ .controls = nau8325_snd_controls,
+ .num_controls = ARRAY_SIZE(nau8325_snd_controls),
+ .dapm_widgets = nau8325_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(nau8325_dapm_widgets),
+ .dapm_routes = nau8325_dapm_routes,
+ .num_dapm_routes = ARRAY_SIZE(nau8325_dapm_routes),
+};
+
+static const struct snd_soc_dai_ops nau8325_dai_ops = {
+ .startup = nau8325_dai_startup,
+ .hw_params = nau8325_hw_params,
+ .set_fmt = nau8325_set_fmt,
+};
+
+#define NAU8325_RATES SNDRV_PCM_RATE_8000_96000
+#define NAU8325_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
+ | SNDRV_PCM_FMTBIT_S24_3LE)
+
+static struct snd_soc_dai_driver nau8325_dai = {
+ .name = NAU8325_CODEC_DAI,
+ .playback = {
+ .stream_name = "Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = NAU8325_RATES,
+ .formats = NAU8325_FORMATS,
+ },
+ .ops = &nau8325_dai_ops,
+};
+
+static const struct regmap_config nau8325_regmap_config = {
+ .reg_bits = NAU8325_REG_ADDR_LEN,
+ .val_bits = NAU8325_REG_DATA_LEN,
+
+ .max_register = NAU8325_REG_MAX,
+ .readable_reg = nau8325_readable_reg,
+ .writeable_reg = nau8325_writeable_reg,
+ .volatile_reg = nau8325_volatile_reg,
+
+ .cache_type = REGCACHE_RBTREE,
+ .reg_defaults = nau8325_reg_defaults,
+ .num_reg_defaults = ARRAY_SIZE(nau8325_reg_defaults),
+};
+
+static void nau8325_reset_chip(struct regmap *regmap)
+{
+ regmap_write(regmap, NAU8325_R00_HARDWARE_RST, 0x0001);
+ regmap_write(regmap, NAU8325_R00_HARDWARE_RST, 0x0000);
+}
+
+static void nau8325_init_regs(struct nau8325 *nau8325)
+{
+ struct regmap *regmap = nau8325->regmap;
+ struct device *dev = nau8325->dev;
+
+ /* set ALC parameters */
+ regmap_update_bits(regmap, NAU8325_R2C_ALC_CTRL1,
+ NAU8325_ALC_MAXGAIN_MASK,
+ 0x7 << NAU8325_ALC_MAXGAIN_SFT);
+ regmap_update_bits(regmap, NAU8325_R2D_ALC_CTRL2,
+ NAU8325_ALC_DCY_MASK | NAU8325_ALC_ATK_MASK |
+ NAU8325_ALC_HLD_MASK, (0x5 << NAU8325_ALC_DCY_SFT) |
+ (0x3 << NAU8325_ALC_ATK_SFT) |
+ (0x5 << NAU8325_ALC_HLD_SFT));
+ /* Enable ALC to avoid signal distortion when battery low. */
+ if (nau8325->alc_enable)
+ regmap_update_bits(regmap, NAU8325_R2E_ALC_CTRL3,
+ NAU8325_ALC_EN, NAU8325_ALC_EN);
+ if (nau8325->clock_detection)
+ regmap_update_bits(regmap, NAU8325_R40_CLK_DET_CTRL,
+ NAU8325_CLKPWRUP_DIS |
+ NAU8325_PWRUP_DFT, 0);
+ else
+ regmap_update_bits(regmap, NAU8325_R40_CLK_DET_CTRL,
+ NAU8325_CLKPWRUP_DIS | NAU8325_PWRUP_DFT,
+ NAU8325_CLKPWRUP_DIS);
+ if (nau8325->clock_det_data)
+ regmap_update_bits(regmap, NAU8325_R40_CLK_DET_CTRL,
+ NAU8325_APWRUP_EN, NAU8325_APWRUP_EN);
+ else
+ regmap_update_bits(regmap, NAU8325_R40_CLK_DET_CTRL,
+ NAU8325_APWRUP_EN, 0);
+
+ /* DAC Reference Voltage Setting */
+ switch (nau8325->dac_vref_microvolt) {
+ case 1800000:
+ regmap_update_bits(regmap, NAU8325_R73_RDAC,
+ NAU8325_DACVREFSEL_MASK, 0 << NAU8325_DACVREFSEL_SFT);
+ break;
+ case 2700000:
+ regmap_update_bits(regmap, NAU8325_R73_RDAC,
+ NAU8325_DACVREFSEL_MASK, 1 << NAU8325_DACVREFSEL_SFT);
+ break;
+ case 2880000:
+ regmap_update_bits(regmap, NAU8325_R73_RDAC,
+ NAU8325_DACVREFSEL_MASK, 2 << NAU8325_DACVREFSEL_SFT);
+ break;
+ case 3060000:
+ regmap_update_bits(regmap, NAU8325_R73_RDAC,
+ NAU8325_DACVREFSEL_MASK, 3 << NAU8325_DACVREFSEL_SFT);
+ break;
+ default:
+ dev_dbg(dev, "Invalid dac-vref-microvolt %d", nau8325->dac_vref_microvolt);
+
+ }
+
+ /* DAC Reference Voltage Decoupling Capacitors. */
+ regmap_update_bits(regmap, NAU8325_R63_ANALOG_CONTROL_3,
+ NAU8325_CLASSD_COARSE_GAIN_MASK, 0x4);
+ /* Auto-Att Min Gain 0dB, Class-D N Driver Slew Rate -25%. */
+ regmap_update_bits(regmap, NAU8325_R64_ANALOG_CONTROL_4,
+ NAU8325_CLASSD_SLEWN_MASK, 0x7);
+
+ /* VMID Tieoff (VMID Resistor Selection) */
+ switch (nau8325->vref_impedance_ohms) {
+ case 0:
+ regmap_update_bits(regmap, NAU8325_R60_BIAS_ADJ,
+ NAU8325_BIAS_VMID_SEL_MASK, 0 << NAU8325_BIAS_VMID_SEL_SFT);
+ break;
+ case 25000:
+ regmap_update_bits(regmap, NAU8325_R60_BIAS_ADJ,
+ NAU8325_BIAS_VMID_SEL_MASK, 1 << NAU8325_BIAS_VMID_SEL_SFT);
+ break;
+ case 125000:
+ regmap_update_bits(regmap, NAU8325_R60_BIAS_ADJ,
+ NAU8325_BIAS_VMID_SEL_MASK, 2 << NAU8325_BIAS_VMID_SEL_SFT);
+ break;
+ case 2500:
+ regmap_update_bits(regmap, NAU8325_R60_BIAS_ADJ,
+ NAU8325_BIAS_VMID_SEL_MASK, 3 << NAU8325_BIAS_VMID_SEL_SFT);
+ break;
+ default:
+ dev_dbg(dev, "Invalid vref-impedance-ohms %d", nau8325->vref_impedance_ohms);
+ }
+
+
+ /* enable VMID, BIAS, DAC, DCA CLOCK, Voltage/Current Amps
+ */
+ regmap_update_bits(regmap, NAU8325_R61_ANALOG_CONTROL_1,
+ NAU8325_DACEN_MASK | NAU8325_DACCLKEN_MASK |
+ NAU8325_DACEN_R_MASK | NAU8325_DACCLKEN_R_MASK |
+ NAU8325_CLASSDEN_MASK | NAU8325_VMDFSTENB_MASK |
+ NAU8325_BIASEN_MASK | NAU8325_VMIDEN_MASK,
+ (0x1 << NAU8325_DACEN_SFT) |
+ (0x1 << NAU8325_DACCLKEN_SFT) |
+ (0x1 << NAU8325_DACEN_R_SFT) |
+ (0x1 << NAU8325_DACCLKEN_R_SFT) |
+ (0x1 << NAU8325_CLASSDEN_SFT) |
+ (0x1 << NAU8325_VMDFSTENB_SFT) |
+ (0x1 << NAU8325_BIASEN_SFT) | 0x3);
+
+ /* Enable ALC to avoid signal distortion when battery low. */
+ if (nau8325->alc_enable)
+ regmap_update_bits(regmap, NAU8325_R2E_ALC_CTRL3,
+ NAU8325_ALC_EN, NAU8325_ALC_EN);
+ if (nau8325->clock_det_data)
+ regmap_update_bits(regmap, NAU8325_R40_CLK_DET_CTRL,
+ NAU8325_APWRUP_EN, NAU8325_APWRUP_EN);
+ else
+ regmap_update_bits(regmap, NAU8325_R40_CLK_DET_CTRL,
+ NAU8325_APWRUP_EN, 0);
+ if (nau8325->clock_detection)
+ regmap_update_bits(regmap, NAU8325_R40_CLK_DET_CTRL,
+ NAU8325_CLKPWRUP_DIS |
+ NAU8325_PWRUP_DFT, 0);
+ else
+ regmap_update_bits(regmap, NAU8325_R40_CLK_DET_CTRL,
+ NAU8325_CLKPWRUP_DIS | NAU8325_PWRUP_DFT,
+ NAU8325_CLKPWRUP_DIS);
+ regmap_update_bits(regmap, NAU8325_R29_DAC_CTRL1,
+ NAU8325_DAC_OVERSAMPLE_MASK,
+ NAU8325_DAC_OVERSAMPLE_128);
+}
+
+static void nau8325_print_device_properties(struct nau8325 *nau8325)
+{
+ struct device *dev = nau8325->dev;
+
+ dev_dbg(dev, "vref-impedance-ohms: %d", nau8325->vref_impedance_ohms);
+ dev_dbg(dev, "dac-vref-microvolt: %d", nau8325->dac_vref_microvolt);
+ dev_dbg(dev, "alc-enable: %d", nau8325->alc_enable);
+ dev_dbg(dev, "clock-det-data: %d", nau8325->clock_det_data);
+ dev_dbg(dev, "clock-detection-disable: %d", nau8325->clock_detection);
+}
+
+static int nau8325_read_device_properties(struct device *dev,
+ struct nau8325 *nau8325)
+{
+ int ret;
+
+ nau8325->alc_enable =
+ device_property_read_bool(dev, "nuvoton,alc-enable");
+ nau8325->clock_det_data =
+ device_property_read_bool(dev, "nuvoton,clock-det-data");
+ nau8325->clock_detection =
+ !device_property_read_bool(dev, "nuvoton,clock-detection-disable");
+
+ ret = device_property_read_u32(dev, "nuvoton,vref-impedance-ohms",
+ &nau8325->vref_impedance_ohms);
+ if (ret)
+ nau8325->vref_impedance_ohms = 125000;
+ ret = device_property_read_u32(dev, "nuvoton,dac-vref-microvolt",
+ &nau8325->dac_vref_microvolt);
+ if (ret)
+ nau8325->dac_vref_microvolt = 2880000;
+
+ return 0;
+}
+
+static int nau8325_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+{
+ struct device *dev = &i2c->dev;
+ struct nau8325 *nau8325 = dev_get_platdata(dev);
+ int ret, value;
+
+ if (!nau8325) {
+ nau8325 = devm_kzalloc(dev, sizeof(*nau8325), GFP_KERNEL);
+ if (!nau8325) {
+ ret = -ENOMEM;
+ goto err;
+ }
+ ret = nau8325_read_device_properties(dev, nau8325);
+ if (ret)
+ goto err;
+ }
+ i2c_set_clientdata(i2c, nau8325);
+
+ nau8325->regmap = devm_regmap_init_i2c(i2c, &nau8325_regmap_config);
+ if (IS_ERR(nau8325->regmap)) {
+ ret = PTR_ERR(nau8325->regmap);
+ goto err;
+ }
+ nau8325->dev = dev;
+ nau8325_print_device_properties(nau8325);
+
+ nau8325_reset_chip(nau8325->regmap);
+ ret = regmap_read(nau8325->regmap, NAU8325_R02_DEVICE_ID, &value);
+ if (ret) {
+ dev_dbg(dev, "Failed to read device id (%d)", ret);
+ goto err;
+ }
+ nau8325_init_regs(nau8325);
+
+ ret = devm_snd_soc_register_component(dev, &nau8325_component_driver,
+ &nau8325_dai, 1);
+err:
+ return ret;
+}
+
+static const struct i2c_device_id nau8325_i2c_ids[] = {
+ { "nau8325", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, nau8325_i2c_ids);
+
+#ifdef CONFIG_OF
+static const struct of_device_id nau8325_of_ids[] = {
+ { .compatible = "nuvoton,nau8325", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, nau8325_of_ids);
+#endif
+
+static struct i2c_driver nau8325_i2c_driver = {
+ .driver = {
+ .name = "nau8325",
+ .of_match_table = of_match_ptr(nau8325_of_ids),
+ },
+ .probe = nau8325_i2c_probe,
+ .id_table = nau8325_i2c_ids,
+};
+module_i2c_driver(nau8325_i2c_driver);
+
+MODULE_DESCRIPTION("ASoC NAU8325 driver");
+MODULE_AUTHOR("Seven Lee <WTLI@nuvoton.com>");
+MODULE_AUTHOR("David Lin <CTLIN0@nuvoton.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/nau8325.h b/sound/soc/codecs/nau8325.h
new file mode 100644
index 000000000000..0d173b66a4d4
--- /dev/null
+++ b/sound/soc/codecs/nau8325.h
@@ -0,0 +1,391 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * nau8325.h -- Nuvoton NAU8325 audio codec driver
+ *
+ * Copyright 2023 Nuvoton Technology Crop.
+ * Author: Seven Lee <WTLI@nuvoton.com>
+ * David Lin <CTLIN0@nuvoton.com>
+ */
+
+#ifndef __NAU8325_H__
+#define __NAU8325_H__
+
+#define NAU8325_R00_HARDWARE_RST 0x00
+#define NAU8325_R01_SOFTWARE_RST 0x01
+#define NAU8325_R02_DEVICE_ID 0x02
+#define NAU8325_R03_CLK_CTRL 0x03
+#define NAU8325_R04_ENA_CTRL 0x04
+#define NAU8325_R05_INTERRUPT_CTRL 0x05
+#define NAU8325_R06_INT_CLR_STATUS 0x06
+#define NAU8325_R09_IRQOUT 0x09
+#define NAU8325_R0A_IO_CTRL 0x0a
+#define NAU8325_R0B_PDM_CTRL 0x0b
+#define NAU8325_R0C_TDM_CTRL 0x0c
+#define NAU8325_R0D_I2S_PCM_CTRL1 0x0d
+#define NAU8325_R0E_I2S_PCM_CTRL2 0x0e
+#define NAU8325_R0F_L_TIME_SLOT 0x0f
+#define NAU8325_R10_R_TIME_SLOT 0x10
+#define NAU8325_R11_HPF_CTRL 0x11
+#define NAU8325_R12_MUTE_CTRL 0x12
+#define NAU8325_R13_DAC_VOLUME 0x13
+#define NAU8325_R1D_DEBUG_READ1 0x1d
+#define NAU8325_R1F_DEBUG_READ2 0x1f
+#define NAU8325_R22_DEBUG_READ3 0x22
+#define NAU8325_R29_DAC_CTRL1 0x29
+#define NAU8325_R2A_DAC_CTRL2 0x2a
+#define NAU8325_R2C_ALC_CTRL1 0x2c
+#define NAU8325_R2D_ALC_CTRL2 0x2d
+#define NAU8325_R2E_ALC_CTRL3 0x2e
+#define NAU8325_R2F_ALC_CTRL4 0x2f
+#define NAU8325_R40_CLK_DET_CTRL 0x40
+#define NAU8325_R49_TEST_STATUS 0x49
+#define NAU8325_R4A_ANALOG_READ 0x4a
+#define NAU8325_R50_MIXER_CTRL 0x50
+#define NAU8325_R55_MISC_CTRL 0x55
+#define NAU8325_R60_BIAS_ADJ 0x60
+#define NAU8325_R61_ANALOG_CONTROL_1 0x61
+#define NAU8325_R62_ANALOG_CONTROL_2 0x62
+#define NAU8325_R63_ANALOG_CONTROL_3 0x63
+#define NAU8325_R64_ANALOG_CONTROL_4 0x64
+#define NAU8325_R65_ANALOG_CONTROL_5 0x65
+#define NAU8325_R66_ANALOG_CONTROL_6 0x66
+#define NAU8325_R69_CLIP_CTRL 0x69
+#define NAU8325_R73_RDAC 0x73
+#define NAU8325_REG_MAX NAU8325_R73_RDAC
+
+/* 16-bit control register address, and 16-bits control register data */
+#define NAU8325_REG_ADDR_LEN 16
+#define NAU8325_REG_DATA_LEN 16
+
+/* CLK_CTRL (0x03) */
+#define NAU8325_CLK_DAC_SRC_SFT 12
+#define NAU8325_CLK_DAC_SRC_MASK (0x3 << NAU8325_CLK_DAC_SRC_SFT)
+#define NAU8325_CLK_MUL_SRC_SFT 6
+#define NAU8325_CLK_MUL_SRC_MASK (0x3 << NAU8325_CLK_MUL_SRC_SFT)
+#define NAU8325_MCLK_SEL_SFT 3
+#define NAU8325_MCLK_SEL_MASK (0x7 << NAU8325_MCLK_SEL_SFT)
+#define NAU8325_MCLK_SRC_MASK 0x7
+
+/* ENA_CTRL (0x04) */
+#define NAU8325_DAC_LEFT_CH_EN_SFT 3
+#define NAU8325_DAC_LEFT_CH_EN (0x1 << NAU8325_DAC_LEFT_CH_EN_SFT)
+#define NAU8325_DAC_RIGHT_CH_EN_SFT 2
+#define NAU8325_DAC_RIGHT_CH_EN (0x1 << NAU8325_DAC_RIGHT_CH_EN_SFT)
+
+/* INTERRUPT_CTRL (0x05) */
+#define NAU8325_ARP_DWN_INT_SFT 12
+#define NAU8325_ARP_DWN_INT_MASK (0x1 << NAU8325_ARP_DWN_INT_SFT)
+#define NAU8325_CLIP_INT_SFT 11
+#define NAU8325_CLIP_INT_MASK (0x1 << NAU8325_CLIP_INT_SFT)
+#define NAU8325_LVD_INT_SFT 10
+#define NAU8325_LVD_INT_MASK (0x1 << NAU8325_LVD_INT_SFT)
+#define NAU8325_PWR_INT_DIS_SFT 8
+#define NAU8325_PWR_INT_DIS (0x1 << NAU8325_PWR_INT_DIS_SFT)
+#define NAU8325_OCP_OTP_SHTDWN_INT_SFT 4
+#define NAU8325_OCP_OTP_SHTDWN_INT_MASK (0x1 << NAU8325_OCP_OTP_SHTDWN_INT_SFT)
+#define NAU8325_CLIP_INT_DIS_SFT 3
+#define NAU8325_CLIP_INT_DIS (0x1 << NAU8325_CLIP_INT_DIS_SFT)
+#define NAU8325_LVD_INT_DIS_SFT 2
+#define NAU8325_LVD_INT_DIS (0x1 << NAU8325_LVD_INT_DIS_SFT)
+#define NAU8325_PWR_INT_MASK 0x1
+
+/* INT_CLR_STATUS (0x06) */
+#define NAU8325_INT_STATUS_MASK 0x7f
+
+/* IRQOUT (0x9) */
+#define NAU8325_IRQOUT_SEL_SEF 12
+#define NAU8325_IRQOUT_SEL_MASK (0xf << NAU8325_IRQOUT_SEL_SEF)
+#define NAU8325_DEM_DITH_SFT 7
+#define NAU8325_DEM_DITH_EN (0x1 << NAU8325_DEM_DITH_SFT)
+#define NAU8325_GAINZI3_SFT 5
+#define NAU8325_GAINZI3_MASK (0x1 << NAU8325_GAINZI3_SFT)
+#define NAU8325_GAINZI2_MASK 0x1f
+
+/* IO_CTRL (0x0a) */
+#define NAU8325_IRQ_PL_SFT 15
+#define NAU8325_IRQ_PL_ACT_HIGH (0x1 << NAU8325_IRQ_PL_SFT)
+#define NAU8325_IRQ_PS_SFT 14
+#define NAU8325_IRQ_PS_UP (0x1 << NAU8325_IRQ_PS_SFT)
+#define NAU8325_IRQ_PE_SFT 13
+#define NAU8325_IRQ_PE_EN (0x1 << NAU8325_IRQ_PE_SFT)
+#define NAU8325_IRQ_DS_SFT 12
+#define NAU8325_IRQ_DS_HIGH (0x1 << NAU8325_IRQ_DS_SFT)
+#define NAU8325_IRQ_OUTPUT_SFT 11
+#define NAU8325_IRQ_OUTPUT_EN (0x1 << NAU8325_IRQ_OUTPUT_SFT)
+#define NAU8325_IRQ_PIN_DEBUG_SFT 10
+#define NAU8325_IRQ_PIN_DEBUG_EN (0x1 << NAU8325_IRQ_PIN_DEBUG_SFT)
+
+/* PDM_CTRL (0x0b) */
+#define NAU8325_PDM_LCH_EDGE_SFT 1
+#define NAU8325_PDM_LCH_EDGE__MASK (0x1 << NAU8325_PDM_LCH_EDGE_SFT)
+#define NAU8325_PDM_MODE_EN 0x1
+
+/* TDM_CTRL (0x0c) */
+#define NAU8325_TDM_SFT 15
+#define NAU8325_TDM_EN (0x1 << NAU8325_TDM_SFT)
+#define NAU8325_PCM_OFFSET_CTRL_SFT 14
+#define NAU8325_PCM_OFFSET_CTRL_EN (0x1 << NAU8325_PCM_OFFSET_CTRL_SFT)
+#define NAU8325_DAC_LEFT_SFT 6
+#define NAU8325_NAU8325_DAC_LEFT_MASK (0x7 << NAU8325_DAC_LEFT_SFT)
+#define NAU8325_DAC_RIGHT_SFT 3
+#define NAU8325_DAC_RIGHT_MASK (0x7 << NAU8325_DAC_RIGHT_SFT)
+
+/* I2S_PCM_CTRL1 (0x0d) */
+#define NAU8325_DACCM_CTL_SFT 14
+#define NAU8325_DACCM_CTL_MASK (0x3 << NAU8325_DACCM_CTL_SFT)
+#define NAU8325_CMB8_0_SFT 10
+#define NAU8325_CMB8_0_MASK (0x1 << NAU8325_CMB8_0_SFT)
+#define NAU8325_UA_OFFSET_SFT 9
+#define NAU8325_UA_OFFSET_MASK (0x1 << NAU8325_UA_OFFSET_SFT)
+#define NAU8325_I2S_BP_SFT 7
+#define NAU8325_I2S_BP_MASK (0x1 << NAU8325_I2S_BP_SFT)
+#define NAU8325_I2S_BP_INV (0x1 << NAU8325_I2S_BP_SFT)
+#define NAU8325_I2S_PCMB_SFT 6
+#define NAU8325_I2S_PCMB_EN (0x1 << NAU8325_I2S_PCMB_SFT)
+#define NAU8325_I2S_DACPSHS0_SFT 5
+#define NAU8325_I2S_DACPSHS0_MASK (0x1 << NAU8325_I2S_DACPSHS0_SFT)
+#define NAU8325_I2S_DL_SFT 2
+#define NAU8325_I2S_DL_MASK (0x3 << NAU8325_I2S_DL_SFT)
+#define NAU8325_I2S_DL_32 (0x3 << NAU8325_I2S_DL_SFT)
+#define NAU8325_I2S_DL_24 (0x2 << NAU8325_I2S_DL_SFT)
+#define NAU8325_I2S_DL_20 (0x1 << NAU8325_I2S_DL_SFT)
+#define NAU8325_I2S_DL_16 (0x0 << NAU8325_I2S_DL_SFT)
+#define NAU8325_I2S_DF_MASK 0x3
+#define NAU8325_I2S_DF_RIGTH 0x0
+#define NAU8325_I2S_DF_LEFT 0x1
+#define NAU8325_I2S_DF_I2S 0x2
+#define NAU8325_I2S_DF_PCM_AB 0x3
+
+/* I2S_PCM_CTRL2 (0x0e) */
+#define NAU8325_PCM_TS_SFT 10
+#define NAU8325_PCM_TS_EN (0x1 << NAU8325_PCM_TS_SFT)
+#define NAU8325_PCM8BIT0_SFT 8
+#define NAU8325_PCM8BIT0_MASK (0x1 << NAU8325_PCM8BIT0_SFT)
+
+/* L_TIME_SLOT (0x0f)*/
+#define NAU8325_SHORT_FS_DET_SFT 13
+#define NAU8325_SHORT_FS_DET_DIS (0x1 << NAU8325_SHORT_FS_DET_SFT)
+#define NAU8325_TSLOT_L0_MASK 0x3ff
+
+/* R_TIME_SLOT (0x10)*/
+#define NAU8325_TSLOT_R0_MASK 0x3ff
+
+/* HPF_CTRL (0x11)*/
+#define NAU8325_DAC_HPF_SFT 15
+#define NAU8325_DAC_HPF_EN (0x1 << NAU8325_DAC_HPF_SFT)
+#define NAU8325_DAC_HPF_APP_SFT 14
+#define NAU8325_DAC_HPF_APP_MASK (0x1 << NAU8325_DAC_HPF_APP_SFT)
+#define NAU8325_DAC_HPF_FCUT_SFT 11
+#define NAU8325_DAC_HPF_FCUT_MASK (0x7 << NAU8325_DAC_HPF_FCUT_SFT)
+
+/* MUTE_CTRL (0x12)*/
+#define NAU8325_SOFT_MUTE_SFT 15
+#define NAU8325_SOFT_MUTE (0x1 << NAU8325_SOFT_MUTE_SFT)
+#define NAU8325_DAC_ZC_SFT 8
+#define NAU8325_DAC_ZC_EN (0x1 << NAU8325_DAC_ZC_SFT)
+#define NAU8325_UNMUTE_CTL_SFT 6
+#define NAU8325_UNMUTE_CTL_MASK (0x3 << NAU8325_UNMUTE_CTL_SFT)
+#define NAU8325_ANA_MUTE_SFT 4
+#define NAU8325_ANA_MUTE_MASK (0x3 << NAU8325_ANA_MUTE_SFT)
+#define NAU8325_AUTO_MUTE_SFT 3
+#define NAU8325_AUTO_MUTE_DIS (0x1 << NAU8325_AUTO_MUTE_SFT)
+
+/* DAC_VOLUME (0x13) */
+#define NAU8325_DAC_VOLUME_L_SFT 8
+#define NAU8325_DAC_VOLUME_L_EN (0xff << NAU8325_DAC_VOLUME_L_SFT)
+#define NAU8325_DAC_VOLUME_R_SFT 0
+#define NAU8325_DAC_VOLUME_R_EN (0xff << NAU8325_DAC_VOLUME_R_SFT)
+#define NAU8325_DAC_VOL_MAX 0xff
+
+/* DEBUG_READ1 (0x1d)*/
+#define NAU8325_OSR100_MASK (0x1 << 6)
+#define NAU8325_MIPS500_MASK (0x1 << 5)
+#define NAU8325_SHUTDWNDRVR_R_MASK (0x1 << 4)
+#define NAU8325_SHUTDWNDRVR_L_MASK (0x1 << 3)
+#define NAU8325_MUTEB_MASK (0x1 << 2)
+#define NAU8325_PDOSCB_MASK (0x1 << 1)
+#define NAU8325_POWERDOWN1B_D_MASK 0x1
+
+/* DEBUG_READ2 (0x1f)*/
+#define NAU8325_R_CHANNEL_Vol_SFT 8
+#define NAU8325_R_CHANNEL_Vol_MASK (0xff << NAU8325_R_CHANNEL_Vol_SFT)
+#define NAU8325_L_CHANNEL_Vol_MASK 0xff
+
+/* DEBUG_READ3(0x22)*/
+#define NAU8325_PGAL_GAIN_MASK (0x3f << 7)
+#define NAU8325_CLIP_MASK (0x1 << 6)
+#define NAU8325_SCAN_MODE_MASK (0x1 << 5)
+#define NAU8325_SDB_MASK (0x1 << 4)
+#define NAU8325_TALARM_MASK (0x1 << 3)
+#define NAU8325_SHORTR_MASK (0x1 << 2)
+#define NAU8325_SHORTL_MASK (0x1 << 1)
+#define NAU8325_TMDET_MASK 0x1
+
+/* DAC_CTRL1 (0x29) */
+#define NAU8325_DAC_OVERSAMPLE_SFT 0
+#define NAU8325_DAC_OVERSAMPLE_MASK 0x7
+#define NAU8325_DAC_OVERSAMPLE_256 1
+#define NAU8325_DAC_OVERSAMPLE_128 2
+#define NAU8325_DAC_OVERSAMPLE_64 0
+#define NAU8325_DAC_OVERSAMPLE_32 4
+
+/* ALC_CTRL1 (0x2c) */
+#define NAU8325_ALC_MAXGAIN_SFT 5
+#define NAU8325_ALC_MAXGAIN_MAX 0x7
+#define NAU8325_ALC_MAXGAIN_MASK (0x7 << NAU8325_ALC_MAXGAIN_SFT)
+#define NAU8325_ALC_MINGAIN_MAX 4
+#define NAU8325_ALC_MINGAIN_SFT 1
+#define NAU8325_ALC_MINGAIN_MASK (0x7 << NAU8325_ALC_MINGAIN_SFT)
+
+/* ALC_CTRL2 (0x2d) */
+#define NAU8325_ALC_DCY_SFT 12
+#define NAU8325_ALC_DCY_MAX 0xb
+#define NAU8325_ALC_DCY_MASK (0xf << NAU8325_ALC_DCY_SFT)
+#define NAU8325_ALC_ATK_SFT 8
+#define NAU8325_ALC_ATK_MAX 0xb
+#define NAU8325_ALC_ATK_MASK (0xf << NAU8325_ALC_ATK_SFT)
+#define NAU8325_ALC_HLD_SFT 4
+#define NAU8325_ALC_HLD_MAX 0xa
+#define NAU8325_ALC_HLD_MASK (0xf << NAU8325_ALC_HLD_SFT)
+#define NAU8325_ALC_LVL_SFT 0
+#define NAU8325_ALC_LVL_MAX 0xf
+#define NAU8325_ALC_LVL_MASK 0xf
+
+/* ALC_CTRL3 (0x2e) */
+#define NAU8325_ALC_EN_SFT 15
+#define NAU8325_ALC_EN (0x1 << NAU8325_ALC_EN_SFT)
+
+/* TEMP_COMP_CTRL (0x30) */
+#define NAU8325_TEMP_COMP_ACT2_MASK 0xff
+
+/* LPF_CTRL (0x33) */
+#define NAU8325_LPF_IN1_EN_SFT 15
+#define NAU8325_LPF_IN1_EN (0x1 << NAU8325_LPF_IN1_EN_SFT)
+#define NAU8325_LPF_IN1_TC_SFT 11
+#define NAU8325_LPF_IN1_TC_MASK (0xf << NAU8325_LPF_IN1_TC_SFT)
+#define NAU8325_LPF_IN2_EN_SFT 10
+#define NAU8325_LPF_IN2_EN (0x1 << NAU8325_LPF_IN2_EN_SFT)
+#define NAU8325_LPF_IN2_TC_SFT 6
+#define NAU8325_LPF_IN2_TC_MASK (0xf << NAU8325_LPF_IN2_TC_SFT)
+
+/* CLK_DET_CTRL (0x40) */
+#define NAU8325_APWRUP_SFT 15
+#define NAU8325_APWRUP_EN (0x1 << NAU8325_APWRUP_SFT)
+#define NAU8325_CLKPWRUP_SFT 14
+#define NAU8325_CLKPWRUP_DIS (0x1 << NAU8325_CLKPWRUP_SFT)
+#define NAU8325_PWRUP_DFT_SFT 13
+#define NAU8325_PWRUP_DFT (0x1 << NAU8325_PWRUP_DFT_SFT)
+#define NAU8325_REG_SRATE_SFT 10
+#define NAU8325_REG_SRATE_MASK (0x7 << NAU8325_REG_SRATE_SFT)
+#define NAU8325_REG_ALT_SRATE_SFT 9
+#define NAU8325_REG_ALT_SRATE_EN (0x1 << NAU8325_REG_ALT_SRATE_SFT)
+#define NAU8325_REG_DIV_MAX 0x1
+
+/* BIAS_ADJ (0x60) */
+#define NAU8325_BIAS_VMID_SEL_SFT 4
+#define NAU8325_BIAS_VMID_SEL_MASK (0x3 << NAU8325_BIAS_VMID_SEL_SFT)
+
+/* ANALOG_CONTROL_1 (0x61) */
+#define NAU8325_VMDFSTENB_SFT 14
+#define NAU8325_VMDFSTENB_MASK (0x3 << NAU8325_VMDFSTENB_SFT)
+#define NAU8325_CLASSDEN_SFT 12
+#define NAU8325_CLASSDEN_MASK (0x3 << NAU8325_CLASSDEN_SFT)
+#define NAU8325_DACCLKEN_R_SFT 10
+#define NAU8325_DACCLKEN_R_MASK (0x3 << NAU8325_DACCLKEN_R_SFT)
+#define NAU8325_DACEN_R_SFT 8
+#define NAU8325_DACEN_R_MASK (0x3 << NAU8325_DACEN_R_SFT)
+#define NAU8325_DACCLKEN_SFT 6
+#define NAU8325_DACCLKEN_MASK (0x3 << NAU8325_DACCLKEN_SFT)
+#define NAU8325_DACEN_SFT 4
+#define NAU8325_DACEN_MASK (0x3 << NAU8325_DACEN_SFT)
+#define NAU8325_BIASEN_SFT 2
+#define NAU8325_BIASEN_MASK (0x3 << NAU8325_BIASEN_SFT)
+#define NAU8325_VMIDEN_MASK 0x3
+
+/* ANALOG_CONTROL_2 (0x62) */
+#define NAU8325_PWMMOD_SFT 14
+#define NAU8325_PWMMOD_MASK (0x1 << NAU8325_PWMMOD_SFT)
+#define NAU8325_DACTEST_SFT 6
+#define NAU8325_DACTEST_MASK (0x3 << NAU8325_DACTEST_SFT)
+#define NAU8325_DACREFCAP_SFT 4
+#define NAU8325_DACREFCAP_MASK (0x3 << NAU8325_DACREFCAP_SFT)
+
+/* ANALOG_CONTROL_3 (0x63) */
+#define NAU8325_POWER_DOWN_L_SFT 12
+#define NAU8325_POWER_DOWN_L_MASK (0x3 << NAU8325_POWER_DOWN_L_SFT)
+#define NAU8325_POWER_DOWN_R_SFT 11
+#define NAU8325_POWER_DOWN_R_MASK (0x3 << NAU8325_DACREFCAP_SFT)
+#define NAU8325_CLASSD_FINE_SFT 5
+#define NAU8325_CLASSD_FINE_MASK (0x3 << NAU8325_CLASSD_FINE_SFT)
+#define NAU8325_CLASSD_COARSE_GAIN_MASK 0xf
+
+/* ANALOG_CONTROL_4 (0x64) */
+#define NAU8325_CLASSD_OCPN_SFT 12
+#define NAU8325_CLASSD_OCPN_MASK (0xf << NAU8325_CLASSD_OCPN_SFT)
+#define NAU8325_CLASSD_OCPP_SFT 8
+#define NAU8325_CLASSD_OCPP_MASK (0xf << NAU8325_CLASSD_OCPP_SFT)
+#define NAU8325_CLASSD_SLEWN_MASK 0xff
+
+/* ANALOG_CONTROL_5 (0x65) */
+#define NAU8325_MCLK_RANGE_SFT 2
+#define NAU8325_MCLK_RANGE_EN (0x1 << NAU8325_MCLK_RANGE_SFT)
+#define NAU8325_MCLK8XEN_SFT 1
+#define NAU8325_MCLK8XEN_EN (0x1 << NAU8325_MCLK8XEN_SFT)
+#define NAU8325_MCLK4XEN_EN 0x1
+
+/* ANALOG_CONTROL_6 (0x66) */
+#define NAU8325_VBATLOW_SFT 4
+#define NAU8325_VBATLOW_MASK (0x1 << NAU8325_VBATLOW_SFT)
+#define NAU8325_VDDSPK_LIM_SFT 3
+#define NAU8325_VDDSPK_LIM_EN (0x1 << NAU8325_VDDSPK_LIM_SFT)
+#define NAU8325_VDDSPK_LIM_MASK 0x7
+
+/* CLIP_CTRL (0x69)*/
+#define NAU8325_ANTI_CLIP_SFT 4
+#define NAU8325_ANTI_CLIP_EN (0x1 << NAU8325_ANTI_CLIP_SFT)
+
+/* RDAC (0x73) */
+#define NAU8325_CLK_DAC_DELAY_SFT 4
+#define NAU8325_CLK_DAC_DELAY_EN (0x7 << NAU8325_CLK_DAC_DELAY_SFT)
+#define NAU8325_DACVREFSEL_SFT 2
+#define NAU8325_DACVREFSEL_MASK (0x3 << NAU8325_DACVREFSEL_SFT)
+
+#define NAU8325_CODEC_DAI "nau8325-hifi"
+
+struct nau8325 {
+ struct device *dev;
+ struct regmap *regmap;
+ int mclk;
+ int fs;
+ int vref_impedance_ohms;
+ int dac_vref_microvolt;
+ int clock_detection;
+ int clock_det_data;
+ int alc_enable;
+};
+
+struct nau8325_src_attr {
+ int param;
+ unsigned int val;
+};
+
+enum {
+ NAU8325_MCLK_FS_RATIO_256,
+ NAU8325_MCLK_FS_RATIO_400,
+ NAU8325_MCLK_FS_RATIO_500,
+ NAU8325_MCLK_FS_RATIO_NUM,
+};
+
+struct nau8325_srate_attr {
+ int fs;
+ int range;
+ bool max;
+ unsigned int mclk_src[NAU8325_MCLK_FS_RATIO_NUM];
+};
+
+struct nau8325_osr_attr {
+ unsigned int osr;
+ unsigned int clk_src;
+};
+
+#endif /* __NAU8325_H__ */
--
2.25.1
^ permalink raw reply related
* [PATCH v5 1/2] ASoC: dt-bindings: Added schema for "nuvoton,nau8325"
From: Seven Lee @ 2024-03-27 7:57 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, alsa-devel, devicetree, linux-sound,
krzysztof.kozlowski+dt, linux-kernel, robh+dt, conor+dt, perex,
tiwai, YHCHuang, KCHSU0, CTLIN0, SJLIN0, wtli, scott6986,
supercraig0719, dardar923
In-Reply-To: <20240327075755.3410381-1-wtli@nuvoton.com>
Add a DT schema for describing nau8325 audio amplifiers. The key features
are as follows:
- Low SPK_VDD Quiescent Current
- Gain Setting with 2-wire interface
- Powerful Stereo Class-D Amplifier
- Low Output Noise
- Low Current Shutdown Mode
- Click-and Pop Suppression
More resources :
https://www.nuvoton.com/products/smart-home-audio/audio-amplifiers/class-d-series/nau8325yg/
Signed-off-by: Seven Lee <wtli@nuvoton.com>
---
.../bindings/sound/nuvoton,nau8325.yaml | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/nuvoton,nau8325.yaml
diff --git a/Documentation/devicetree/bindings/sound/nuvoton,nau8325.yaml b/Documentation/devicetree/bindings/sound/nuvoton,nau8325.yaml
new file mode 100644
index 000000000000..979be0d336da
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/nuvoton,nau8325.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nuvoton,nau8325.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NAU8325 audio Amplifier
+
+maintainers:
+ - Seven Lee <WTLI@nuvoton.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: nuvoton,nau8325
+
+ reg:
+ maxItems: 1
+
+ nuvoton,vref-impedance-ohms:
+ description:
+ The vref impedance to be used in ohms. Middle of voltage enables
+ Tie-Off selection options. Due to the high impedance of the VREF
+ pin, it is important to use a low-leakage capacitor.
+
+ enum: [0, 25000, 125000, 2500]
+
+ nuvoton,dac-vref-microvolt:
+ description:
+ The DAC vref to be used in voltage. DAC reference voltage setting. Can
+ be used for minor tuning of the output level. Since the VDDA is range
+ between 1.62 to 1.98 voltage, the typical value for design is 1.8V. After
+ the minor tuning, the final microvolt are as the below.
+
+ enum: [1800000, 2700000, 2880000, 3060000]
+
+ nuvoton,alc-enable:
+ description:
+ Enable digital automatic level control (ALC) function.
+ type: boolean
+
+ nuvoton,clock-detection-disable:
+ description:
+ When clock detection is enabled, it will detect whether MCLK
+ and FS are within the range. MCLK range is from 2.048MHz to 24.576MHz.
+ FS range is from 8kHz to 96kHz. And also needs to detect the ratio
+ MCLK_SRC/LRCK of 256, 400 or 500, and needs to detect the BCLK
+ to make sure data is present. There needs to be at least 8 BCLK
+ cycles per Frame Sync.
+ type: boolean
+
+ nuvoton,clock-det-data:
+ description:
+ Request clock detection to require 2048 non-zero samples before enabling
+ the audio paths. If set then non-zero samples is required, otherwise it
+ doesn't matter.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec@21 {
+ compatible = "nuvoton,nau8325";
+ reg = <0x21>;
+ nuvoton,vref-impedance-ohms = <125000>;
+ nuvoton,dac-vref-microvolt = <2880000>;
+ nuvoton,alc-enable;
+ nuvoton,clock-det-data;
+ };
+ };
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v2 1/2] dt-bindings: dma: snps,dw-axi-dmac: Add JH8100 support
From: Conor Dooley @ 2024-03-27 7:57 UTC (permalink / raw)
To: Tan Chun Hau
Cc: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Ley Foon Tan, Jee Heng Sia, dmaengine, devicetree,
linux-kernel
In-Reply-To: <20240327025126.229475-2-chunhau.tan@starfivetech.com>
[-- Attachment #1: Type: text/plain, Size: 449 bytes --]
On Tue, Mar 26, 2024 at 07:51:25PM -0700, Tan Chun Hau wrote:
> Add support for StarFive JH8100 SoC in Sysnopsys Designware AXI DMA
> controller.
>
> Both JH8100 and JH7110 require reset operation in device probe.
> However, JH8100 doesn't need to apply different configuration on
> CH_CFG registers.
>
> Signed-off-by: Tan Chun Hau <chunhau.tan@starfivetech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v5 1/1] dt-bindings: net: starfive,jh7110-dwmac: Add StarFive JH8100 support
From: Krzysztof Kozlowski @ 2024-03-27 7:54 UTC (permalink / raw)
To: Tan Chun Hau, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Simon Horman, Bartosz Golaszewski,
Andrew Halaney, Jisheng Zhang, Uwe Kleine-König,
Russell King
Cc: Ley Foon Tan, Jee Heng Sia, netdev, devicetree, linux-kernel,
linux-stm32, linux-arm-kernel, linux-riscv
In-Reply-To: <20240327015750.226349-2-chunhau.tan@starfivetech.com>
On 27/03/2024 02:57, Tan Chun Hau wrote:
> Add StarFive JH8100 dwmac support.
> The JH8100 dwmac shares the same driver code as the JH7110 dwmac
> and has only one reset signal.
>
> Please refer to below:
>
> JH8100: reset-names = "stmmaceth";
> JH7110: reset-names = "stmmaceth", "ahb";
> JH7100: reset-names = "ahb";
>
> Example usage of JH8100 in the device tree:
>
> gmac0: ethernet@16030000 {
> compatible = "starfive,jh8100-dwmac",
> "starfive,jh7110-dwmac",
> "snps,dwmac-5.20";
> ...
> };
>
> Signed-off-by: Tan Chun Hau <chunhau.tan@starfivetech.com>
> ---
> .../devicetree/bindings/net/snps,dwmac.yaml | 1 +
> .../bindings/net/starfive,jh7110-dwmac.yaml | 29 +++++++++++++++----
> 2 files changed, 25 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> index 6b0341a8e0ea..a6d596b7dcf4 100644
> --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> @@ -97,6 +97,7 @@ properties:
> - snps,dwxgmac-2.10
> - starfive,jh7100-dwmac
> - starfive,jh7110-dwmac
> + - starfive,jh8100-dwmac
I think that's not needed. You have there already your fallback.
>
> reg:
> minItems: 1
> diff --git a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
> index 0d1962980f57..5805a58c55d1 100644
> --- a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
> @@ -18,6 +18,7 @@ select:
> enum:
> - starfive,jh7100-dwmac
> - starfive,jh7110-dwmac
> + - starfive,jh8100-dwmac
Same here, even more obvious.
> required:
> - compatible
>
> @@ -30,6 +31,10 @@ properties:
> - items:
> - const: starfive,jh7110-dwmac
> - const: snps,dwmac-5.20
> + - items:
> + - const: starfive,jh8100-dwmac
> + - const: starfive,jh7110-dwmac
> + - const: snps,dwmac-5.20
>
> reg:
> maxItems: 1
> @@ -116,11 +121,25 @@ allOf:
> minItems: 3
> maxItems: 3
>
> - resets:
> - minItems: 2
> -
> - reset-names:
> - minItems: 2
> + if:
I would personally avoid nesting if within if. It gets unreadable.
Although Rob did not comment on this one, so I guess it is fine.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: dma: snps,dw-axi-dmac: Add JH8100 support
From: Krzysztof Kozlowski @ 2024-03-27 7:49 UTC (permalink / raw)
To: Tan Chun Hau, Eugeniy Paltsev, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Ley Foon Tan, Jee Heng Sia, dmaengine, devicetree, linux-kernel
In-Reply-To: <20240327025126.229475-2-chunhau.tan@starfivetech.com>
On 27/03/2024 03:51, Tan Chun Hau wrote:
> Add support for StarFive JH8100 SoC in Sysnopsys Designware AXI DMA
> controller.
>
> Both JH8100 and JH7110 require reset operation in device probe.
> However, JH8100 doesn't need to apply different configuration on
> CH_CFG registers.
This is a friendly reminder during the review process.
It looks like you received a tag and forgot to add it.
If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions, under or above your Signed-off-by tag. Tag is "received", when
provided in a message replied to you on the mailing list. Tools like b4
can help here. However, there's no need to repost patches *only* to add
the tags. The upstream maintainer will do that for tags received on the
version they apply.
https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
If a tag was not added on purpose, please state why and what changed.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v1 1/4] dt-bindings: input: Add Himax HX83102J touchscreen
From: Allen Lin @ 2024-03-27 7:48 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, Rob Herring, dmitry.torokhov,
krzysztof.kozlowski+dt, conor+dt, jikos, benjamin.tissoires,
linux-input, devicetree, linux-kernel
In-Reply-To: <20240326-granite-snipping-7c8b04480b2e@spud>
Conor Dooley <conor@kernel.org> 於 2024年3月27日 週三 上午3:28寫道：
>
> On Tue, Mar 26, 2024 at 06:40:28PM +0800, Allen Lin wrote:
> > Conor Dooley <conor.dooley@microchip.com> 於 2024年3月26日 週二 下午4:48寫道：
> > >
> > > On Tue, Mar 26, 2024 at 01:46:56PM +0800, Allen Lin wrote:
> > > > Conor Dooley <conor@kernel.org> 於 2024年3月23日 週六 上午2:34寫道：
> > > > >
> > > > > On Fri, Mar 22, 2024 at 01:30:09PM -0500, Rob Herring wrote:
> > > > > > On Fri, Mar 22, 2024 at 05:54:08PM +0000, Conor Dooley wrote:
> > > > > > > On Fri, Mar 22, 2024 at 04:56:03PM +0800, Allen_Lin wrote:
> > > > > > > > Add the HX83102j touchscreen device tree bindings documents.
> > > > > > > > HX83102j is a Himax TDDI touchscreen controller.
> > > > > > > > It's power sequence should be bound with a lcm driver, thus it
> > > > > > > > needs to be a panel follower. Others are the same as normal SPI
> > > > > > > > touchscreen controller.
> > > > > > > >
> > > > > > > > Signed-off-by: Allen_Lin <allencl_lin@hotmail.com>
> > > > > > >
> > > > > > > note to self/Krzysztof/Rob:
> > > > > > > There was a previous attempt at this kind of device. This version looks
> > > > > > > better but might be incomplete given there's a bunch more properties in
> > > > > > > that patchset:
> > > > > > > https://lore.kernel.org/all/20231017091900.801989-1-tylor_yang@himax.corp-partner.google.com/
> > > > > >
> > > > > > Those don't look like properties we want coming back.
> > > > >
> > > > > Oh, I don't want most of them coming back either. There are some
> > > > > supplies in there though that I think we would like to come back, no?
> > > > > Maybe this particular device doesn't have any supplies, but that doesn't
> > > > > really seem credible.
> > > >
> > > > We will use Firmware-name in Device Tree.
> > >
> > > > For power supply settings, because there may be other device using
> > > > same regulator.
> > >
> > > If there are other devices using the same regulator is it more
> > > important that you document it so that it doesn't get disabled by the
> > > other users.
> > >
> > > > We plan to define it as an optional property for user to control in
> > > > next release.
> > >
> > > I don't see how the regulator would not be required, the device doesn't
> > > function without power.
> > >
> > > Thanks,
> > > Conor.
> >
> > I will set power supply as required.
> > The description of power supply as below,
> >
> > properties:
> > vccd-supply:
> > description: A phandle for the regualtor supplying IO power. Should be own
> > by TPIC only.
>
> What does "owned by TPIC" only mean? Why would the vccd supply not be
> allowed to be shared with another device?
>
> > This works for TP digital IO only, main power is
> > given by display part VSP/VSN power source which is controlled
> > by lcm driver.
>
> What drivers control things doesn't really matter here, we're just
> describing the hardware. If there's another supply to the controller,
> then document it too please.
>
Below is IC power sequence introduction.
https://github.com/HimaxSoftware/Doc/tree/main/Himax_Chipset_Power_Sequence
TDDI IC, which means Touch and Display Driver is integrated in one IC,
So some power supplies will be controlled by Display driver.
In yaml Document, can we just list power supplies controlled by touch driver?
Thanks,
Allen
^ permalink raw reply
* Re: [PATCH RFC] riscv: dts: sophgo: add sdcard support for milkv duo
From: Inochi Amaoto @ 2024-03-27 7:44 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Adrian Hunter, Jisheng Zhang
Cc: Inochi Amaoto, linux-mmc, devicetree, linux-kernel, linux-riscv
In-Reply-To: <20240217144826.3944-1-jszhang@kernel.org>
On Sat, 17 Feb 2024 22:48:26 +0800, Jisheng Zhang wrote:
> Add sdhci dt node in SoC dtsi and enable it in milkv duo dts.
>
>
Applied to sophgo/for-next, thanks!
[1/1] riscv: dts: sophgo: add sdcard support for milkv duo
https://github.com/sophgo/linux/commit/89a7056ed4f771e689729f7992ef5351e64e26c6
Thanks,
Inochi
^ permalink raw reply
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