* Re: [PATCH v2 2/2] mfd: rohm-bd71828: Add power off functionality
From: Andreas Kemnade @ 2024-03-27 13:04 UTC (permalink / raw)
To: Matti Vaittinen
Cc: lee, robh+dt, krzysztof.kozlowski+dt, conor+dt, devicetree,
linux-kernel
In-Reply-To: <815e1cdc-145e-4880-96a0-d9c21308b9b3@gmail.com>
Hi,
On Wed, 27 Mar 2024 09:32:29 +0200
Matti Vaittinen <mazziesaccount@gmail.com> wrote:
> It's worth noting that there is another PMIC, BD71879, which, from the
> driver software point of view, should be (almost?) identical to the
> BD71828. I believe the BD71828 drivers should work with it as well - if
> not out of the box, at least with very minor modifications.
> Unfortunately I don't know products where the BD71879 is used or if it
> is sold via distributors - so I don't know if adding a DT
> compatible/chip type define for it would be beneficial.
yes, you already told we thet the BD71828 drivers are compatible with
the BD71879 and I am using the latter.
But that at least should be commented somewhere, so that
people do not raise questions, like: Do I have some strange board revision,
etc?
The most terse form to comment it is a separate dt compatible so we are
prepare any "almost identical" surprises.
Regards,
Andreas
^ permalink raw reply
* Re: [PATCH 3/4] arm64: dts: rockchip: Add VEPU121 to rk3588
From: Sebastian Reichel @ 2024-03-27 13:09 UTC (permalink / raw)
To: Link Mauve
Cc: Krzysztof Kozlowski, linux-kernel, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Joerg Roedel, Will Deacon,
Robin Murphy, Cristian Ciocaltea, Dragan Simic, Shreeya Patel,
Chris Morgan, Andy Yan, Nicolas Frattaroli, linux-media,
linux-rockchip, devicetree, linux-arm-kernel, iommu
In-Reply-To: <ZgQTrwOUtdZ1nRs0@desktop>
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Hi,
On Wed, Mar 27, 2024 at 01:40:15PM +0100, Link Mauve wrote:
> On Thu, Mar 21, 2024 at 09:15:38AM +0100, Krzysztof Kozlowski wrote:
> > On 20/03/2024 18:37, Emmanuel Gil Peyrot wrote:
> > > The TRM (version 1.0 page 385) lists five VEPU121 cores, but only four
> > > interrupts are listed (on page 24), so I’ve only enabled four of them
> > > for now.
> > >
> > > Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
> > > ---
> > > arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++++++
> > > 1 file changed, 80 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> > > index 2a23b4dc36e4..fe77b56ac9a0 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> > > @@ -2488,6 +2488,86 @@ gpio4: gpio@fec50000 {
> > > };
> > > };
> > >
> > > + jpeg_enc0: video-codec@fdba0000 {
> > > + compatible = "rockchip,rk3588-vepu121";
> > > + reg = <0x0 0xfdba0000 0x0 0x800>;
> > > + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
> > > + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
> > > + clock-names = "aclk", "hclk";
> > > + iommus = <&jpeg_enc0_mmu>;
> > > + power-domains = <&power RK3588_PD_VDPU>;
> > > + };
> > > +
> > > + jpeg_enc0_mmu: iommu@fdba0800 {
> > > + compatible = "rockchip,rk3588-iommu";
> >
> > It does not look like you tested the DTS against bindings. Please run
> > `make dtbs_check W=1` (see
> > Documentation/devicetree/bindings/writing-schema.rst or
> > https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
> > for instructions).
>
> Even on master I get an exception about this unresolvable file:
> referencing.exceptions.Unresolvable: cache-controller.yaml#
>
> Yet it seems to be present in only three files, all of them unrelated to
> the rockchip board I’m interested in (it seems), so I’m not sure what to
> do about that.
The trace looked like you tried using dt-schema with jsonschema
version 4.18+, which is known broken:
https://github.com/devicetree-org/dt-schema/issues/109
Greetings,
-- Sebastian
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^ permalink raw reply
* Re: [PATCH v4 1/2] of: create of_root if no dtb provided
From: Rob Herring @ 2024-03-27 13:11 UTC (permalink / raw)
To: Guenter Roeck
Cc: Stephen Boyd, Frank Rowand, Clément Léger, devicetree,
linux-kernel, Lizhi Hou, Allan Nielsen, Horatiu Vultur,
Steen Hegelund, Thomas Petazzoni
In-Reply-To: <23ed5bbb-7616-424b-96ee-3fe1c6d8ca89@roeck-us.net>
On Wed, Mar 20, 2024 at 3:06 PM Guenter Roeck <linux@roeck-us.net> wrote:
>
> On 3/20/24 12:14, Rob Herring wrote:
> > On Mon, Mar 18, 2024 at 4:31 PM Guenter Roeck <linux@roeck-us.net> wrote:
> >>
> >> On 3/18/24 12:26, Rob Herring wrote:
> >>> +Stephen
> >>>
> >>> On Mon, Mar 18, 2024 at 12:09 PM Guenter Roeck <linux@roeck-us.net> wrote:
> >>>>
> >>>> Hi,
> >>>>
> >>>> On Fri, Mar 17, 2023 at 12:34:14AM -0500, Frank Rowand wrote:
> >>>>> When enabling CONFIG_OF on a platform where of_root is not populated by
> >>>>> firmware, we end up without a root node. In order to apply overlays and
> >>>>> create subnodes of the root node, we need one. Create this root node
> >>>>> by unflattening an empty builtin dtb.
> >>>>>
> >>>>> If firmware provides a flattened device tree (FDT) then the FDT is
> >>>>> unflattened via setup_arch(). Otherwise setup_of(), which is called
> >>>>> immediately after setup_arch(), will create the default root node
> >>>>> if it does not exist.
> >>>>>
> >>>>> Signed-off-by: Frank Rowand <frowand.list@gmail.com>
> >>>>
> >>>> This patch results in a crash on nios2.
> >>>
> >>> This patch was never applied. I assume you meant a later version of it
> >>> that did get applied.
> >>>
> >>>>
> >>>> Building nios2:10m50-ghrd:10m50_defconfig:10m50_devboard.dts ... running ...R failed (crashed)
> >>>
> >>> Booting with DT?
> >>>
> >>>> ------------
> >>>> qemu log:
> >>>> earlycon: uart8250 at MMIO32 0x18001600 (options '')
> >>>> printk: legacy bootconsole [uart8250] enabled
> >>>> Linux version 6.8.0-11409-gf6cef5f8c37f (groeck@desktop) (nios2-linux-gcc (GCC) 11.4.0, GNU ld (GNU Binutils) 2.40) #1 Sun Mar 17 23:38:59 PDT 2024
> >>>> Kernel panic - not syncing: early_init_dt_alloc_memory_arch: Failed to allocate 72 bytes align=0x40
> >>>> ---[ end Kernel panic - not syncing: early_init_dt_alloc_memory_arch: Failed to allocate 72 bytes align=0x40 ]---
> >>>
> >>> nios2 looks utterly broken to me. This change should be a nop unless
> >>> initial_boot_params is NULL. It looks like it is possible for r6 (dtb
> >>> address) to be 0 depending on kconfig options, but that would have
> >>> skipped copying and unflattening which would then panic in
> >>> setup_cpuinfo(). If initial_boot_params is not NULL, then the same
> >>> early_init_dt_alloc_memory_arch() calls should fail when copying the
> >>> DT. So I don't see how nios2 booting with DT ever worked.
> >>>
> >>
> >> For nios2, in early_init_devtree():
> >>
> >> void __init early_init_devtree(void *params)
> >> {
> >> __be32 *dtb = (u32 *)__dtb_start;
> >> ...
> >> if (be32_to_cpu((__be32) *dtb) == OF_DT_HEADER)
> >> params = (void *)__dtb_start;
> >>
> >> That worked fine until this patch. Starting with this patch, __dtb_start
> >> always points to a valid empty devicetree blob, which overrides the
> >> devicetree blob passed to early_init_devtree(). This causes the problem.
> >
> > With an external DTB, it doesn't boot with or without this patch. It
> > just dies in different spots. Before it just skipped any memory
>
> No, that is incorrect.
Well, I can tell you it doesn't boot for me. So I must be doing
something different from your setup.
> Up to this patch it booted just fine with an
> external dtb using the "-initrd" command line argument, and I explained
> to you above why this is the case.
What does -initrd have to do with anything? Does that shift where the
external dtb is placed or something?
I think I see the issue. __dtb_start points to the start of *all*
built-in DTBs, not a specific one. In this case, arc, csky, loongarch,
mips, openrisc, riscv, sh, and xtensa may all be broken too (if one
picks the magic combination of booting modes and kconfig options). I
would expect all these cases have been broken forever if the DT
unittest is enabled as it too adds a built-in dtb. But I would also
expect that arch code gets linked first and link order would save us
here.
Rob
^ permalink raw reply
* [PATCH v2 1/2] media: dt-binding: media: Document rk3588’s VEPU121
From: Emmanuel Gil Peyrot @ 2024-03-27 13:41 UTC (permalink / raw)
To: linux-kernel
Cc: Emmanuel Gil Peyrot, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Joerg Roedel, Will Deacon,
Robin Murphy, Sebastian Reichel, Cristian Ciocaltea, Dragan Simic,
Shreeya Patel, Chris Morgan, Andy Yan, Nicolas Frattaroli,
linux-media, linux-rockchip, devicetree, linux-arm-kernel, iommu
In-Reply-To: <20240327134115.424846-1-linkmauve@linkmauve.fr>
This encoder-only device is present four times on this SoC, and should
support everything the rk3568 vepu supports (so JPEG, H.264 and VP8
encoding).
According to the TRM[1], there is also the VEPU580 encoder which
supports H.264 and H.265, and various VDPU* decoders, of which only the
VDPU981 is currently supported. This patch describes only the VEPU121.
[1] https://github.com/FanX-Tek/rk3588-TRM-and-Datasheet
Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
---
.../devicetree/bindings/media/rockchip,rk3568-vepu.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
index 9d90d8d0565a..4c6cb21da041 100644
--- a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
@@ -15,8 +15,12 @@ description:
properties:
compatible:
- enum:
- - rockchip,rk3568-vepu
+ oneOf:
+ - const: rockchip,rk3568-vepu
+ - items:
+ - enum:
+ - rockchip,rk3588-vepu121
+ - const: rockchip,rk3568-vepu
reg:
maxItems: 1
--
2.44.0
^ permalink raw reply related
* [PATCH v2 0/2] Enable JPEG encoding on rk3588
From: Emmanuel Gil Peyrot @ 2024-03-27 13:41 UTC (permalink / raw)
To: linux-kernel
Cc: Emmanuel Gil Peyrot, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Joerg Roedel, Will Deacon,
Robin Murphy, Sebastian Reichel, Cristian Ciocaltea, Dragan Simic,
Shreeya Patel, Chris Morgan, Andy Yan, Nicolas Frattaroli,
linux-media, linux-rockchip, devicetree, linux-arm-kernel, iommu
Only the JPEG encoder is available for now, although there are patches
for the undocumented VP8 encoder floating around[0].
This has been tested on a rock-5b, resulting in four /dev/video*
encoders. The userspace program I’ve been using to test them is
Onix[1], using the jpeg-encoder example, it will pick one of these four
at random (but displays the one it picked):
% ffmpeg -i <input image> -pix_fmt yuvj420p temp.yuv
% jpeg-encoder temp.yuv <width> <height> NV12 <quality> output.jpeg
[0] https://patchwork.kernel.org/project/linux-rockchip/list/?series=789885
[1] https://crates.io/crates/onix
Changes since v1:
- Dropped patches 1 and 4.
- Use the proper compatible form, since this device should be fully
compatible with the VEPU of rk356x.
- Describe where the VEPU121 name comes from, and list other encoders
and decoders present in this SoC.
- Properly test the device tree changes, I previously couldn’t since I
was using a too recent version of python-jsonschema…
Emmanuel Gil Peyrot (2):
media: dt-binding: media: Document rk3588’s VEPU121
arm64: dts: rockchip: Add VEPU121 to rk3588
.../bindings/media/rockchip,rk3568-vepu.yaml | 8 +-
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++
2 files changed, 86 insertions(+), 2 deletions(-)
--
2.44.0
^ permalink raw reply
* [PATCH v2 2/2] arm64: dts: rockchip: Add VEPU121 to rk3588
From: Emmanuel Gil Peyrot @ 2024-03-27 13:41 UTC (permalink / raw)
To: linux-kernel
Cc: Emmanuel Gil Peyrot, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Joerg Roedel, Will Deacon,
Robin Murphy, Sebastian Reichel, Cristian Ciocaltea, Dragan Simic,
Shreeya Patel, Chris Morgan, Andy Yan, Nicolas Frattaroli,
linux-media, linux-rockchip, devicetree, linux-arm-kernel, iommu
In-Reply-To: <20240327134115.424846-1-linkmauve@linkmauve.fr>
The TRM (version 1.0 page 385) lists five VEPU121 cores, but only four
interrupts are listed (on page 24), so I’ve only enabled four of them
for now.
Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 87b83c87bd55..510ed3db9d01 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2488,6 +2488,86 @@ gpio4: gpio@fec50000 {
};
};
+ jpeg_enc0: video-codec@fdba0000 {
+ compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu";
+ reg = <0x0 0xfdba0000 0x0 0x800>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
+ clock-names = "aclk", "hclk";
+ iommus = <&jpeg_enc0_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ jpeg_enc0_mmu: iommu@fdba0800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba0800 0x0 0x40>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ jpeg_enc1: video-codec@fdba4000 {
+ compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu";
+ reg = <0x0 0xfdba4000 0x0 0x800>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
+ clock-names = "aclk", "hclk";
+ iommus = <&jpeg_enc1_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ jpeg_enc1_mmu: iommu@fdba4800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba4800 0x0 0x40>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ jpeg_enc2: video-codec@fdba8000 {
+ compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu";
+ reg = <0x0 0xfdba8000 0x0 0x800>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
+ clock-names = "aclk", "hclk";
+ iommus = <&jpeg_enc2_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ jpeg_enc2_mmu: iommu@fdba8800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba8800 0x0 0x40>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ jpeg_enc3: video-codec@fdbac000 {
+ compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu";
+ reg = <0x0 0xfdbac000 0x0 0x800>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
+ clock-names = "aclk", "hclk";
+ iommus = <&jpeg_enc3_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ jpeg_enc3_mmu: iommu@fdbac800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdbac800 0x0 0x40>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
av1d: video-codec@fdc70000 {
compatible = "rockchip,rk3588-av1-vpu";
reg = <0x0 0xfdc70000 0x0 0x800>;
--
2.44.0
^ permalink raw reply related
* Re: [PATCH v2 2/2] mfd: rohm-bd71828: Add power off functionality
From: Matti Vaittinen @ 2024-03-27 14:11 UTC (permalink / raw)
To: Andreas Kemnade
Cc: lee, robh+dt, krzysztof.kozlowski+dt, conor+dt, devicetree,
linux-kernel
In-Reply-To: <20240327140451.65ff8e18@aktux>
On 3/27/24 15:04, Andreas Kemnade wrote:
> Hi,
>
> On Wed, 27 Mar 2024 09:32:29 +0200
> Matti Vaittinen <mazziesaccount@gmail.com> wrote:
>
>> It's worth noting that there is another PMIC, BD71879, which, from the
>> driver software point of view, should be (almost?) identical to the
>> BD71828. I believe the BD71828 drivers should work with it as well - if
>> not out of the box, at least with very minor modifications.
>> Unfortunately I don't know products where the BD71879 is used or if it
>> is sold via distributors - so I don't know if adding a DT
>> compatible/chip type define for it would be beneficial.
>
> yes, you already told we thet the BD71828 drivers are compatible with
> the BD71879 and I am using the latter.
> But that at least should be commented somewhere, so that
> people do not raise questions, like: Do I have some strange board revision,
> etc?
> The most terse form to comment it is a separate dt compatible so we are
> prepare any "almost identical" surprises.
I agree. Reason why I haven't done this already is that I don't always
(like in this case) know which of the variant are eventually sold. So,
it's balancing dance between adding compatibles for ICs that will never
been seen by large audience, and missing compatibles for some of the
variants.
This is also why I was interested in knowing which variant you had, and
where was it used.
But yes, I think that as the BD71879 has obviously been found by a
community linux kernel user - it would make sense to add a compatible
for it!
Do you feel like adding the compatible 'rohm,bd71879' in
rohm,bd71828-pmic.yaml as part of this series(?)
Yours,
-- Matti
--
Matti Vaittinen
Linux kernel developer at ROHM Semiconductors
Oulu Finland
~~ When things go utterly wrong vim users can always type :help! ~~
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: ufs: qcom: document SC8180X UFS
From: Rob Herring @ 2024-03-27 14:31 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Krzysztof Kozlowski,
Conor Dooley, Andy Gross, linux-arm-msm, linux-scsi, devicetree,
linux-kernel
In-Reply-To: <20240326174632.209745-1-krzysztof.kozlowski@linaro.org>
On Tue, Mar 26, 2024 at 06:46:30PM +0100, Krzysztof Kozlowski wrote:
> Document already upstreamed and used Qualcomm SC8180x UFS host
> controller to fix dtbs_check warnings like:
>
> sc8180x-primus.dtb: ufshc@1d84000: compatible:0: 'qcom,sc8180x-ufshc' is not one of ['qcom,msm8994-ufshc', ... ]
> sc8180x-primus.dtb: ufshc@1d84000: Unevaluated properties are not allowed ('compatible' was unexpected)
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
>
> Rob, considering limbo status of this binding, maybe you can take it
> directly? Would be the fastest.
Applied for 6.9, thanks.
Rob
^ permalink raw reply
* Re: [PATCH v4 1/2] of: create of_root if no dtb provided
From: Guenter Roeck @ 2024-03-27 14:40 UTC (permalink / raw)
To: Rob Herring
Cc: Stephen Boyd, Frank Rowand, Clément Léger, devicetree,
linux-kernel, Lizhi Hou, Allan Nielsen, Horatiu Vultur,
Steen Hegelund, Thomas Petazzoni
In-Reply-To: <CAL_JsqJd-upC4TgOwP5-DMXKL+x=X7sGC7qqiy2PTjD6pnSV7Q@mail.gmail.com>
On 3/27/24 06:11, Rob Herring wrote:
> On Wed, Mar 20, 2024 at 3:06 PM Guenter Roeck <linux@roeck-us.net> wrote:
>>
>> On 3/20/24 12:14, Rob Herring wrote:
>>> On Mon, Mar 18, 2024 at 4:31 PM Guenter Roeck <linux@roeck-us.net> wrote:
>>>>
>>>> On 3/18/24 12:26, Rob Herring wrote:
>>>>> +Stephen
>>>>>
>>>>> On Mon, Mar 18, 2024 at 12:09 PM Guenter Roeck <linux@roeck-us.net> wrote:
>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> On Fri, Mar 17, 2023 at 12:34:14AM -0500, Frank Rowand wrote:
>>>>>>> When enabling CONFIG_OF on a platform where of_root is not populated by
>>>>>>> firmware, we end up without a root node. In order to apply overlays and
>>>>>>> create subnodes of the root node, we need one. Create this root node
>>>>>>> by unflattening an empty builtin dtb.
>>>>>>>
>>>>>>> If firmware provides a flattened device tree (FDT) then the FDT is
>>>>>>> unflattened via setup_arch(). Otherwise setup_of(), which is called
>>>>>>> immediately after setup_arch(), will create the default root node
>>>>>>> if it does not exist.
>>>>>>>
>>>>>>> Signed-off-by: Frank Rowand <frowand.list@gmail.com>
>>>>>>
>>>>>> This patch results in a crash on nios2.
>>>>>
>>>>> This patch was never applied. I assume you meant a later version of it
>>>>> that did get applied.
>>>>>
>>>>>>
>>>>>> Building nios2:10m50-ghrd:10m50_defconfig:10m50_devboard.dts ... running ...R failed (crashed)
>>>>>
>>>>> Booting with DT?
>>>>>
>>>>>> ------------
>>>>>> qemu log:
>>>>>> earlycon: uart8250 at MMIO32 0x18001600 (options '')
>>>>>> printk: legacy bootconsole [uart8250] enabled
>>>>>> Linux version 6.8.0-11409-gf6cef5f8c37f (groeck@desktop) (nios2-linux-gcc (GCC) 11.4.0, GNU ld (GNU Binutils) 2.40) #1 Sun Mar 17 23:38:59 PDT 2024
>>>>>> Kernel panic - not syncing: early_init_dt_alloc_memory_arch: Failed to allocate 72 bytes align=0x40
>>>>>> ---[ end Kernel panic - not syncing: early_init_dt_alloc_memory_arch: Failed to allocate 72 bytes align=0x40 ]---
>>>>>
>>>>> nios2 looks utterly broken to me. This change should be a nop unless
>>>>> initial_boot_params is NULL. It looks like it is possible for r6 (dtb
>>>>> address) to be 0 depending on kconfig options, but that would have
>>>>> skipped copying and unflattening which would then panic in
>>>>> setup_cpuinfo(). If initial_boot_params is not NULL, then the same
>>>>> early_init_dt_alloc_memory_arch() calls should fail when copying the
>>>>> DT. So I don't see how nios2 booting with DT ever worked.
>>>>>
>>>>
>>>> For nios2, in early_init_devtree():
>>>>
>>>> void __init early_init_devtree(void *params)
>>>> {
>>>> __be32 *dtb = (u32 *)__dtb_start;
>>>> ...
>>>> if (be32_to_cpu((__be32) *dtb) == OF_DT_HEADER)
>>>> params = (void *)__dtb_start;
>>>>
>>>> That worked fine until this patch. Starting with this patch, __dtb_start
>>>> always points to a valid empty devicetree blob, which overrides the
>>>> devicetree blob passed to early_init_devtree(). This causes the problem.
>>>
>>> With an external DTB, it doesn't boot with or without this patch. It
>>> just dies in different spots. Before it just skipped any memory
>>
>> No, that is incorrect.
>
> Well, I can tell you it doesn't boot for me. So I must be doing
> something different from your setup.
>
Maybe you have OF_UNITTEST enabled and it indeed results in the
problem you mention below. I don't have it enabled because it produces
various backtraces which would hide real problems.
>> Up to this patch it booted just fine with an
>> external dtb using the "-initrd" command line argument, and I explained
>> to you above why this is the case.
>
> What does -initrd have to do with anything? Does that shift where the
> external dtb is placed or something?
>
Nothing. I meant to say -dtb.
> I think I see the issue. __dtb_start points to the start of *all*
> built-in DTBs, not a specific one. In this case, arc, csky, loongarch,
> mips, openrisc, riscv, sh, and xtensa may all be broken too (if one
> picks the magic combination of booting modes and kconfig options). I
No.
- arc only picks the internal dtb if use_embedded_dtb is true. This flag
is only set if there is no external dtb, or if the external dtb does
not provide a valid machine description.
- openrisc only picks the internal dtb if no external dtb is provided.
- riscv only picks the internal dtb if CONFIG_BUILTIN_DTB is enabled.
- sh only used the internal dtb if CONFIG_USE_BUILTIN_DTB is enabled.
- xtensa only picks the internal dtb if there is no external dtb.
However, nios2 picks the internal dtb _even if_ an external dtb
is provided if there is an internal dtb. In other words, it prefers
the internal dtb over the external dtb. All other architectures
prefer the external dtb over the internal dtb.
> would expect all these cases have been broken forever if the DT
> unittest is enabled as it too adds a built-in dtb. But I would also
Even if that is correct for nios2, that hardly seems to be an argument
to break nios2 boot with external dtb unconditionally.
Thanks,
Guenter
^ permalink raw reply
* Re: [PATCH v8 05/10] ARM: dts: bcm2835-rpi: Move firmware-clocks from bcm2711 to bcm2835
From: Dave Stevenson @ 2024-03-27 14:46 UTC (permalink / raw)
To: Laurent Pinchart
Cc: linux-media, David Plowman, Jean-Michel Hautbois, Hans Verkuil,
Naushir Patuck, Sakari Ailus, kernel-list, linux-rpi-kernel,
Florian Fainelli, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Conor Dooley, Krzysztof Kozlowski,
Rob Herring, devicetree, Phil Elwell
In-Reply-To: <20240327000510.2541-6-laurent.pinchart@ideasonboard.com>
Hi Laurent
On Wed, 27 Mar 2024 at 00:05, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>
> The Raspberry Pi firmware handles clocks on all BCM2835-derived SoCs,
> not just on the BCM2711. Move the corresponding DT node from
> bcm2711-rpi.dtsi to bcm2835-rpi.dtsi.
It's already present in bcm2835-rpi-common.dtsi [1]. That is included
for all Pi0-3 platforms, but not bcm2711 / Pi4.
I don't see any reason why it needs to be defined separately for the
bcm283x vs bcm2711 (I suspect it's just evolution), but having it
defined twice on the bcm283x platforms isn't that great.
Drop the firmware_clocks node from bcm2835-rpi-common.dtsi as well, and it gets:
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
[1] https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi#L10-L15
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi | 5 -----
> arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi | 5 +++++
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi
> index d233a191c139..86188eabeb24 100644
> --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi
> @@ -20,11 +20,6 @@ aliases {
> };
>
> &firmware {
> - firmware_clocks: clocks {
> - compatible = "raspberrypi,firmware-clocks";
> - #clock-cells = <1>;
> - };
> -
> expgpio: gpio {
> compatible = "raspberrypi,firmware-gpio";
> gpio-controller;
> diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi
> index 761a9da97bd0..6e6dc109f0c2 100644
> --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi
> @@ -5,6 +5,11 @@ soc {
> firmware: firmware {
> compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
> mboxes = <&mailbox>;
> +
> + firmware_clocks: clocks {
> + compatible = "raspberrypi,firmware-clocks";
> + #clock-cells = <1>;
> + };
> };
>
> power: power {
> --
> Regards,
>
> Laurent Pinchart
>
^ permalink raw reply
* Re: [PATCH 04/25] clk: meson: a1: add the audio clock controller driver
From: Jerome Brunet @ 2024-03-27 12:57 UTC (permalink / raw)
To: Jan Dakinevich
Cc: Jerome Brunet, Neil Armstrong, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Kevin Hilman, Martin Blumenstingl, Liam Girdwood, Mark Brown,
Linus Walleij, Jaroslav Kysela, Takashi Iwai, linux-amlogic,
linux-clk, devicetree, linux-kernel, linux-arm-kernel, alsa-devel,
linux-sound, linux-gpio, kernel
In-Reply-To: <dc4ed700-623d-4823-9a41-de9be78afa64@salutedevices.com>
On Tue 26 Mar 2024 at 21:44, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
> On 3/26/24 18:26, Jerome Brunet wrote:
>>
>> On Sat 23 Mar 2024 at 21:02, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
>>
>>> Jerome, I have reworked my driver reusing axg-audio code as most as I
>>> could and now I have one more question. Lets see on this definition from
>>> axg-audio:
>>>
>>> #define AUD_MST_MUX(_name, _reg, _flag) \
>>> AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
>>> mst_mux_parent_data, 0)
>>>
>>> #define AUD_MST_MCLK_MUX(_name, _reg) \
>>> AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
>>>
>>> CLK_SET_RATE_PARENT is not set here. But why? It means, that topmost pll
>>> clock will not be reconfigured at runtime to satisfy the rate that was
>>> requested from axg-tdm.
>>>
>>
>> Yes, that is by design. It is another area where mainline audio differs
>> greatly from AML vendor code. The PLLs are expected be to fixed and the
>> audio master clock will reparent to the most adequate PLL source
>> depending on the use case.
>>
>> This is how we manage to satisfy all audio interfaces with a very
>> limited number of PLLs
>>
>> On AXG/G12 there is at most 6 concurrent interfaces (3 FRDDR/TODDR) - 8
>> on sm1 - and we can satisfy on that with 3 PLLs. That would not be
>> possible if interfaces were having their way with the PLLs, reseting it
>> everytime a stream is started.
>> > The PLL rate should be carefully chosen so it can be derived easily. On
>> AXG/G12/SM1 that is:
>> * one PLL per rate family, to maximize clock precision
>> * x24 x32: to handle different sample sizes
>> * x2 until we reach the PLL limits to allow higher rates such as 384kHz
>> or even higher
>>
>
> Thank you. Now it has become much clearer.
>
>> If you have less PLLs on A1, you'll have to make compromises, like a less
>> precise clock to support multiple family with one PLL.
>> This is why the PLLs are set for each platform in DT because that choice
>> may depend on the platform use case.
>>
>
> Unfortunately, on A1 we have only one PLL.
>
That where compromises comes in. Pick a rate known as 'audio friendly'
which match some rates and appromixate others, or use codec clock master.
> Yes, for us it would be better to have hifi_pll with predefined rate.
> For instance it will allow to avoid that ugly workaround in PDM (sysrate
> property, etc).
That is another problem entirely.
Krzysztof and I already covered what you should do for this.
The exact rate the PDM system clock does not matter at all because the
driver queries the actual rate of the clocks and adapts.
You have problems here only because you added CLK_SET_RATE_PARENT and
you are triggering the concurrent usage problem I explain below.
>
> But what whould be preferred for upstream? I can imagine a scenario
> where samples with different rate should be played, PDM attached to
> fclk_divN and there are no conflicts with TDM.
You are considering only PDM and 1 TDM. The SoC has 2 TDMs which could
be active concurrently a different rates.
> In this case
> reconfiguration of hifi_pll on demand could better satisfy somebody's
> requirements.
No this is not possible. Doing so does not allow all the interfaces to be
used concurrently.
* If the PLL is not protected, existing streams get broken by new
starting stream when the PLL is reconfigured
* If the PLL is protected, new stream effectively starve because no
clock may provide a 'good enough' rate for them
This is why the reference rate must carefully chosen, something CCF
cannot do for you.
For example, a source of 12.288MHz (and its powers of 2) allows to match
48 and 32kHz sample rates and approximate 44.1kHz rates with an
acceptable drift.
>
>>>
>>> On 3/19/24 11:30, Jerome Brunet wrote:
>>>>
>>>> On Tue 19 Mar 2024 at 04:47, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
>>>>
>>>>> Let's start from the end:
>>>>>
>>>>>> No - Looks to me you just have two clock controllers you are trying
>>>>> force into one.
>>>>>
>>>>>> Again, this shows 2 devices. The one related to your 'map0' should
>>>>> request AUD2_CLKID_AUDIOTOP as input and enable it right away.
>>>>>
>>>>> Most of fishy workarounds that you commented is caused the fact the mmio
>>>>> of this clock controller is divided into two parts. Compare it with
>>>>> axg-audio driver, things that was part of contigous memory region (like
>>>>> pdm) here are moved to second region. Is this enough to make a guess
>>>>> that these are two devices?
>>>>
>>>> I see obsolutely no reason to think it is a single device nor to add all the quirks
>>>> you have the way you did. So yes, in that case, 2 zones, 2 devices.
>>>>
>>>>>
>>>>> Concerning AUD2_CLKID_AUDIOTOP clock, as it turned out, it must be
>>>>> enabled before enabling of clocks from second region too. That is
>>>>> AUD2_CLKID_AUDIOTOP clock feeds both parts of this clock controller.
>>>>>
>>>>
>>>> Yes. I understood the first time around and already commented on that.
>>>>
>>>>>
>>>>> On 3/15/24 12:20, Jerome Brunet wrote:
>>>>>>
>>>>>> On Fri 15 Mar 2024 at 02:21, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
>>>>>>
>>>>>>> This controller provides clocks and reset functionality for audio
>>>>>>> peripherals on Amlogic A1 SoC family.
>>>>>>>
>>>>>>> The driver is almost identical to 'axg-audio', however it would be better
>>>>>>> to keep it separate due to following reasons:
>>>>>>>
>>>>>>> - significant amount of bits has another definition. I will bring there
>>>>>>> a mess of new defines with A1_ suffixes.
>>>>>>>
>>>>>>> - registers of this controller are located in two separate regions. It
>>>>>>> will give a lot of complications for 'axg-audio' to support this.
>>>>>>>
>>>>>>> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>>>>>>> ---
>>>>>>> drivers/clk/meson/Kconfig | 13 +
>>>>>>> drivers/clk/meson/Makefile | 1 +
>>>>>>> drivers/clk/meson/a1-audio.c | 556 +++++++++++++++++++++++++++++++++++
>>>>>>> drivers/clk/meson/a1-audio.h | 58 ++++
>>>>>>> 4 files changed, 628 insertions(+)
>>>>>>> create mode 100644 drivers/clk/meson/a1-audio.c
>>>>>>> create mode 100644 drivers/clk/meson/a1-audio.h
>>>>>>>
>>>>>>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>>>>>>> index d6a2fa5f7e88..80c4a18c83d2 100644
>>>>>>> --- a/drivers/clk/meson/Kconfig
>>>>>>> +++ b/drivers/clk/meson/Kconfig
>>>>>>> @@ -133,6 +133,19 @@ config COMMON_CLK_A1_PERIPHERALS
>>>>>>> device, A1 SoC Family. Say Y if you want A1 Peripherals clock
>>>>>>> controller to work.
>>>>>>>
>>>>>>> +config COMMON_CLK_A1_AUDIO
>>>>>>> + tristate "Amlogic A1 SoC Audio clock controller support"
>>>>>>> + depends on ARM64
>>>>>>> + select COMMON_CLK_MESON_REGMAP
>>>>>>> + select COMMON_CLK_MESON_CLKC_UTILS
>>>>>>> + select COMMON_CLK_MESON_PHASE
>>>>>>> + select COMMON_CLK_MESON_SCLK_DIV
>>>>>>> + select COMMON_CLK_MESON_AUDIO_RSTC
>>>>>>> + help
>>>>>>> + Support for the Audio clock controller on Amlogic A113L based
>>>>>>> + device, A1 SoC Family. Say Y if you want A1 Audio clock controller
>>>>>>> + to work.
>>>>>>> +
>>>>>>> config COMMON_CLK_G12A
>>>>>>> tristate "G12 and SM1 SoC clock controllers support"
>>>>>>> depends on ARM64
>>>>>>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>>>>>>> index 88d94921a4dc..4968fc7ad555 100644
>>>>>>> --- a/drivers/clk/meson/Makefile
>>>>>>> +++ b/drivers/clk/meson/Makefile
>>>>>>> @@ -20,6 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
>>>>>>> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
>>>>>>> obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
>>>>>>> obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
>>>>>>> +obj-$(CONFIG_COMMON_CLK_A1_AUDIO) += a1-audio.o
>>>>>>> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
>>>>>>> obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
>>>>>>> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
>>>>>>> diff --git a/drivers/clk/meson/a1-audio.c b/drivers/clk/meson/a1-audio.c
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..6039116c93ba
>>>>>>> --- /dev/null
>>>>>>> +++ b/drivers/clk/meson/a1-audio.c
>>>>>>> @@ -0,0 +1,556 @@
>>>>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>>>>> +/*
>>>>>>> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
>>>>>>> + *
>>>>>>> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>>>>>>> + */
>>>>>>> +
>>>>>>> +#include <linux/clk.h>
>>>>>>> +#include <linux/clk-provider.h>
>>>>>>> +#include <linux/init.h>
>>>>>>> +#include <linux/of_device.h>
>>>>>>> +#include <linux/module.h>
>>>>>>> +#include <linux/platform_device.h>
>>>>>>> +#include <linux/regmap.h>
>>>>>>> +#include <linux/reset.h>
>>>>>>> +#include <linux/reset-controller.h>
>>>>>>> +#include <linux/slab.h>
>>>>>>> +
>>>>>>> +#include "meson-clkc-utils.h"
>>>>>>> +#include "meson-audio-rstc.h"
>>>>>>> +#include "clk-regmap.h"
>>>>>>> +#include "clk-phase.h"
>>>>>>> +#include "sclk-div.h"
>>>>>>> +#include "a1-audio.h"
>>>>>>> +
>>>>>>> +#define AUDIO_PDATA(_name) \
>>>>>>> + ((const struct clk_parent_data[]) { { .hw = &(_name).hw } })
>>>>>>
>>>>>> Not a fan - yet another level of macro.
>>>>>>
>>>>>>> +
>>>>>>> +#define AUDIO_MUX(_name, _reg, _mask, _shift, _pdata) \
>>>>>>> +static struct clk_regmap _name = { \
>>>>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>>>>> + .data = &(struct clk_regmap_mux_data){ \
>>>>>>> + .offset = AUDIO_REG_OFFSET(_reg), \
>>>>>>> + .mask = (_mask), \
>>>>>>> + .shift = (_shift), \
>>>>>>> + }, \
>>>>>>> + .hw.init = &(struct clk_init_data) { \
>>>>>>> + .name = #_name, \
>>>>>>> + .ops = &clk_regmap_mux_ops, \
>>>>>>> + .parent_data = (_pdata), \
>>>>>>> + .num_parents = ARRAY_SIZE(_pdata), \
>>>>>>> + .flags = CLK_SET_RATE_PARENT, \
>>>>>>> + }, \
>>>>>>> +}
>>>>>>> +
>>>>>>> +#define AUDIO_DIV(_name, _reg, _shift, _width, _pdata) \
>>>>>>> +static struct clk_regmap _name = { \
>>>>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>>>>> + .data = &(struct clk_regmap_div_data){ \
>>>>>>> + .offset = AUDIO_REG_OFFSET(_reg), \
>>>>>>> + .shift = (_shift), \
>>>>>>> + .width = (_width), \
>>>>>>> + }, \
>>>>>>> + .hw.init = &(struct clk_init_data) { \
>>>>>>> + .name = #_name, \
>>>>>>> + .ops = &clk_regmap_divider_ops, \
>>>>>>> + .parent_data = (_pdata), \
>>>>>>> + .num_parents = 1, \
>>>>>>> + .flags = CLK_SET_RATE_PARENT, \
>>>>>>> + }, \
>>>>>>> +}
>>>>>>> +
>>>>>>> +#define AUDIO_GATE(_name, _reg, _bit, _pdata) \
>>>>>>> +static struct clk_regmap _name = { \
>>>>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>>>>> + .data = &(struct clk_regmap_gate_data){ \
>>>>>>> + .offset = AUDIO_REG_OFFSET(_reg), \
>>>>>>> + .bit_idx = (_bit), \
>>>>>>> + }, \
>>>>>>> + .hw.init = &(struct clk_init_data) { \
>>>>>>> + .name = #_name, \
>>>>>>> + .ops = &clk_regmap_gate_ops, \
>>>>>>> + .parent_data = (_pdata), \
>>>>>>> + .num_parents = 1, \
>>>>>>> + .flags = CLK_SET_RATE_PARENT, \
>>>>>>> + }, \
>>>>>>> +}
>>>>>>> +
>>>>>>> +#define AUDIO_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
>>>>>>> + _hi_shift, _hi_width, _pdata, _set_rate_parent) \
>>>>>>> +static struct clk_regmap _name = { \
>>>>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>>>>> + .data = &(struct meson_sclk_div_data) { \
>>>>>>> + .div = { \
>>>>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>>>>> + .shift = (_div_shift), \
>>>>>>> + .width = (_div_width), \
>>>>>>> + }, \
>>>>>>> + .hi = { \
>>>>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>>>>> + .shift = (_hi_shift), \
>>>>>>> + .width = (_hi_width), \
>>>>>>> + }, \
>>>>>>> + }, \
>>>>>>> + .hw.init = &(struct clk_init_data) { \
>>>>>>> + .name = #_name, \
>>>>>>> + .ops = &meson_sclk_div_ops, \
>>>>>>> + .parent_data = (_pdata), \
>>>>>>> + .num_parents = 1, \
>>>>>>> + .flags = (_set_rate_parent) ? CLK_SET_RATE_PARENT : 0, \
>>>>>>
>>>>>> Does not help readeability. Just pass the flag as axg-audio does.
>>>>>>
>>>>>>> + }, \
>>>>>>> +}
>>>>>>> +
>>>>>>> +#define AUDIO_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
>>>>>>> + _pdata) \
>>>>>>> +static struct clk_regmap _name = { \
>>>>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>>>>> + .data = &(struct meson_clk_triphase_data) { \
>>>>>>> + .ph0 = { \
>>>>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>>>>> + .shift = (_shift0), \
>>>>>>> + .width = (_width), \
>>>>>>> + }, \
>>>>>>> + .ph1 = { \
>>>>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>>>>> + .shift = (_shift1), \
>>>>>>> + .width = (_width), \
>>>>>>> + }, \
>>>>>>> + .ph2 = { \
>>>>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>>>>> + .shift = (_shift2), \
>>>>>>> + .width = (_width), \
>>>>>>> + }, \
>>>>>>> + }, \
>>>>>>> + .hw.init = &(struct clk_init_data) { \
>>>>>>> + .name = #_name, \
>>>>>>> + .ops = &meson_clk_triphase_ops, \
>>>>>>> + .parent_data = (_pdata), \
>>>>>>> + .num_parents = 1, \
>>>>>>> + .flags = CLK_SET_RATE_PARENT | CLK_DUTY_CYCLE_PARENT, \
>>>>>>> + }, \
>>>>>>> +}
>>>>>>> +
>>>>>>> +#define AUDIO_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, \
>>>>>>> + _pdata) \
>>>>>>> +static struct clk_regmap _name = { \
>>>>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>>>>> + .data = &(struct meson_sclk_ws_inv_data) { \
>>>>>>> + .ph = { \
>>>>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>>>>> + .shift = (_shift_ph), \
>>>>>>> + .width = (_width), \
>>>>>>> + }, \
>>>>>>> + .ws = { \
>>>>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>>>>> + .shift = (_shift_ws), \
>>>>>>> + .width = (_width), \
>>>>>>> + }, \
>>>>>>> + }, \
>>>>>>> + .hw.init = &(struct clk_init_data) { \
>>>>>>> + .name = #_name, \
>>>>>>> + .ops = &meson_sclk_ws_inv_ops, \
>>>>>>> + .parent_data = (_pdata), \
>>>>>>> + .num_parents = 1, \
>>>>>>> + .flags = CLK_SET_RATE_PARENT | CLK_DUTY_CYCLE_PARENT, \
>>>>>>> + }, \
>>>>>>> +}
>>>>>>
>>>>>> All the above does essentially the same things as the macro of
>>>>>> axg-audio, to some minor differences. Yet it is another set to maintain.
>>>>>>
>>>>>
>>>>> Except one thing... Here I keep memory identifier to which this clock
>>>>> belongs:
>>>>>
>>>>> .map = AUDIO_REG_MAP(_reg),
>>>>>
>>>>> It is workaround, but ->map the only common field in clk_regmap that
>>>>> could be used for this purpose.
>>>>>
>>>>>
>>>>>> I'd much prefer if you put the axg-audio macro in a header a re-used
>>>>>> those. There would a single set to maintain. You may then specialize the
>>>>>> included in the driver C file, to avoid redundant parameters
>>>>>>
>>>>>> Rework axg-audio to use clk_parent_data if you must, but not in the same
>>>>>> series please.
>>>>>>
>>>>>>> +
>>>>>>> +static const struct clk_parent_data a1_pclk_pdata[] = {
>>>>>>> + { .fw_name = "pclk", },
>>>>>>> +};
>>>>>>> +
>>>>>>> +AUDIO_GATE(audio_ddr_arb, AUDIO_CLK_GATE_EN0, 0, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_tdmin_a, AUDIO_CLK_GATE_EN0, 1, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_tdmin_b, AUDIO_CLK_GATE_EN0, 2, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_tdmin_lb, AUDIO_CLK_GATE_EN0, 3, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_loopback, AUDIO_CLK_GATE_EN0, 4, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_tdmout_a, AUDIO_CLK_GATE_EN0, 5, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_tdmout_b, AUDIO_CLK_GATE_EN0, 6, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_frddr_a, AUDIO_CLK_GATE_EN0, 7, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_frddr_b, AUDIO_CLK_GATE_EN0, 8, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_toddr_a, AUDIO_CLK_GATE_EN0, 9, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_toddr_b, AUDIO_CLK_GATE_EN0, 10, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_spdifin, AUDIO_CLK_GATE_EN0, 11, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_resample, AUDIO_CLK_GATE_EN0, 12, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_eqdrc, AUDIO_CLK_GATE_EN0, 13, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio_audiolocker, AUDIO_CLK_GATE_EN0, 14, a1_pclk_pdata);
>>>>>> This is what I mean by redundant parameter ^
>>>>>>
>>>>>
>>>>> Yep. I could define something like AUDIO_PCLK_GATE().
>>>>>
>>>>>>> +
>>>>>>> +AUDIO_GATE(audio2_ddr_arb, AUDIO2_CLK_GATE_EN0, 0, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio2_pdm, AUDIO2_CLK_GATE_EN0, 1, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio2_tdmin_vad, AUDIO2_CLK_GATE_EN0, 2, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio2_toddr_vad, AUDIO2_CLK_GATE_EN0, 3, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio2_vad, AUDIO2_CLK_GATE_EN0, 4, a1_pclk_pdata);
>>>>>>> +AUDIO_GATE(audio2_audiotop, AUDIO2_CLK_GATE_EN0, 7, a1_pclk_pdata);
>>>>>>> +
>>>>>>> +static const struct clk_parent_data a1_mst_pdata[] = {
>>>>>>> + { .fw_name = "dds_in" },
>>>>>>> + { .fw_name = "fclk_div2" },
>>>>>>> + { .fw_name = "fclk_div3" },
>>>>>>> + { .fw_name = "hifi_pll" },
>>>>>>> + { .fw_name = "xtal" },
>>>>>>> +};
>>>>>>> +
>>>>>>> +#define AUDIO_MST_MCLK(_name, _reg) \
>>>>>>> + AUDIO_MUX(_name##_mux, (_reg), 0x7, 24, a1_mst_pdata); \
>>>>>>> + AUDIO_DIV(_name##_div, (_reg), 0, 16, \
>>>>>>> + AUDIO_PDATA(_name##_mux)); \
>>>>>>> + AUDIO_GATE(_name, (_reg), 31, AUDIO_PDATA(_name##_div))
>>>>>>> +
>>>>>>> +AUDIO_MST_MCLK(audio_mst_a_mclk, AUDIO_MCLK_A_CTRL);
>>>>>>> +AUDIO_MST_MCLK(audio_mst_b_mclk, AUDIO_MCLK_B_CTRL);
>>>>>>> +AUDIO_MST_MCLK(audio_mst_c_mclk, AUDIO_MCLK_C_CTRL);
>>>>>>> +AUDIO_MST_MCLK(audio_mst_d_mclk, AUDIO_MCLK_D_CTRL);
>>>>>>> +AUDIO_MST_MCLK(audio_spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
>>>>>>> +AUDIO_MST_MCLK(audio_eqdrc_clk, AUDIO_CLK_EQDRC_CTRL);
>>>>>>> +
>>>>>>> +AUDIO_MUX(audio_resample_clk_mux, AUDIO_CLK_RESAMPLE_CTRL, 0xf, 24,
>>>>>>> + a1_mst_pdata);
>>>>>>> +AUDIO_DIV(audio_resample_clk_div, AUDIO_CLK_RESAMPLE_CTRL, 0, 8,
>>>>>>> + AUDIO_PDATA(audio_resample_clk_mux));
>>>>>>> +AUDIO_GATE(audio_resample_clk, AUDIO_CLK_RESAMPLE_CTRL, 31,
>>>>>>> + AUDIO_PDATA(audio_resample_clk_div));
>>>>>>> +
>>>>>>> +AUDIO_MUX(audio_locker_in_clk_mux, AUDIO_CLK_LOCKER_CTRL, 0xf, 8,
>>>>>>> + a1_mst_pdata);
>>>>>>> +AUDIO_DIV(audio_locker_in_clk_div, AUDIO_CLK_LOCKER_CTRL, 0, 8,
>>>>>>> + AUDIO_PDATA(audio_locker_in_clk_mux));
>>>>>>> +AUDIO_GATE(audio_locker_in_clk, AUDIO_CLK_LOCKER_CTRL, 15,
>>>>>>> + AUDIO_PDATA(audio_locker_in_clk_div));
>>>>>>> +
>>>>>>> +AUDIO_MUX(audio_locker_out_clk_mux, AUDIO_CLK_LOCKER_CTRL, 0xf, 24,
>>>>>>> + a1_mst_pdata);
>>>>>>> +AUDIO_DIV(audio_locker_out_clk_div, AUDIO_CLK_LOCKER_CTRL, 16, 8,
>>>>>>> + AUDIO_PDATA(audio_locker_out_clk_mux));
>>>>>>> +AUDIO_GATE(audio_locker_out_clk, AUDIO_CLK_LOCKER_CTRL, 31,
>>>>>>> + AUDIO_PDATA(audio_locker_out_clk_div));
>>>>>>> +
>>>>>>> +AUDIO_MST_MCLK(audio2_vad_mclk, AUDIO2_MCLK_VAD_CTRL);
>>>>>>> +AUDIO_MST_MCLK(audio2_vad_clk, AUDIO2_CLK_VAD_CTRL);
>>>>>>> +AUDIO_MST_MCLK(audio2_pdm_dclk, AUDIO2_CLK_PDMIN_CTRL0);
>>>>>>> +AUDIO_MST_MCLK(audio2_pdm_sysclk, AUDIO2_CLK_PDMIN_CTRL1);
>>>>>>> +
>>>>>>> +#define AUDIO_MST_SCLK(_name, _reg0, _reg1, _pdata) \
>>>>>>> + AUDIO_GATE(_name##_pre_en, (_reg0), 31, (_pdata)); \
>>>>>>> + AUDIO_SCLK_DIV(_name##_div, (_reg0), 20, 10, 0, 0, \
>>>>>>> + AUDIO_PDATA(_name##_pre_en), true); \
>>>>>>> + AUDIO_GATE(_name##_post_en, (_reg0), 30, \
>>>>>>> + AUDIO_PDATA(_name##_div)); \
>>>>>>> + AUDIO_TRIPHASE(_name, (_reg1), 1, 0, 2, 4, \
>>>>>>> + AUDIO_PDATA(_name##_post_en))
>>>>>>> +
>>>>>>
>>>>>> Again, I'm not a fan of this many levels of macro. I can live with it
>>>>>> but certainly don't want the burden of reviewing and maintaining for
>>>>>> clock driver. AXG / G12 and A1 are obviously closely related, so make it common.
>>>>>>
>>>>>>> +#define AUDIO_MST_LRCLK(_name, _reg0, _reg1, _pdata) \
>>>>>>> + AUDIO_SCLK_DIV(_name##_div, (_reg0), 0, 10, 10, 10, \
>>>>>>> + (_pdata), false); \
>>>>>>> + AUDIO_TRIPHASE(_name, (_reg1), 1, 1, 3, 5, \
>>>>>>> + AUDIO_PDATA(_name##_div))
>>>>>>> +
>>>>>>> +AUDIO_MST_SCLK(audio_mst_a_sclk, AUDIO_MST_A_SCLK_CTRL0, AUDIO_MST_A_SCLK_CTRL1,
>>>>>>> + AUDIO_PDATA(audio_mst_a_mclk));
>>>>>>> +AUDIO_MST_SCLK(audio_mst_b_sclk, AUDIO_MST_B_SCLK_CTRL0, AUDIO_MST_B_SCLK_CTRL1,
>>>>>>> + AUDIO_PDATA(audio_mst_b_mclk));
>>>>>>> +AUDIO_MST_SCLK(audio_mst_c_sclk, AUDIO_MST_C_SCLK_CTRL0, AUDIO_MST_C_SCLK_CTRL1,
>>>>>>> + AUDIO_PDATA(audio_mst_c_mclk));
>>>>>>> +AUDIO_MST_SCLK(audio_mst_d_sclk, AUDIO_MST_D_SCLK_CTRL0, AUDIO_MST_D_SCLK_CTRL1,
>>>>>>> + AUDIO_PDATA(audio_mst_d_mclk));
>>>>>>> +
>>>>>>> +AUDIO_MST_LRCLK(audio_mst_a_lrclk, AUDIO_MST_A_SCLK_CTRL0, AUDIO_MST_A_SCLK_CTRL1,
>>>>>>> + AUDIO_PDATA(audio_mst_a_sclk_post_en));
>>>>>>> +AUDIO_MST_LRCLK(audio_mst_b_lrclk, AUDIO_MST_B_SCLK_CTRL0, AUDIO_MST_B_SCLK_CTRL1,
>>>>>>> + AUDIO_PDATA(audio_mst_b_sclk_post_en));
>>>>>>> +AUDIO_MST_LRCLK(audio_mst_c_lrclk, AUDIO_MST_C_SCLK_CTRL0, AUDIO_MST_C_SCLK_CTRL1,
>>>>>>> + AUDIO_PDATA(audio_mst_c_sclk_post_en));
>>>>>>> +AUDIO_MST_LRCLK(audio_mst_d_lrclk, AUDIO_MST_D_SCLK_CTRL0, AUDIO_MST_D_SCLK_CTRL1,
>>>>>>> + AUDIO_PDATA(audio_mst_d_sclk_post_en));
>>>>>>> +
>>>>>>> +static const struct clk_parent_data a1_mst_sclk_pdata[] = {
>>>>>>> + { .hw = &audio_mst_a_sclk.hw },
>>>>>>> + { .hw = &audio_mst_b_sclk.hw },
>>>>>>> + { .hw = &audio_mst_c_sclk.hw },
>>>>>>> + { .hw = &audio_mst_d_sclk.hw },
>>>>>>> + { .fw_name = "slv_sclk0" },
>>>>>>> + { .fw_name = "slv_sclk1" },
>>>>>>> + { .fw_name = "slv_sclk2" },
>>>>>>> + { .fw_name = "slv_sclk3" },
>>>>>>> + { .fw_name = "slv_sclk4" },
>>>>>>> + { .fw_name = "slv_sclk5" },
>>>>>>> + { .fw_name = "slv_sclk6" },
>>>>>>> + { .fw_name = "slv_sclk7" },
>>>>>>> + { .fw_name = "slv_sclk8" },
>>>>>>> + { .fw_name = "slv_sclk9" },
>>>>>>> +};
>>>>>>> +
>>>>>>> +static const struct clk_parent_data a1_mst_lrclk_pdata[] = {
>>>>>>> + { .hw = &audio_mst_a_lrclk.hw },
>>>>>>> + { .hw = &audio_mst_b_lrclk.hw },
>>>>>>> + { .hw = &audio_mst_c_lrclk.hw },
>>>>>>> + { .hw = &audio_mst_d_lrclk.hw },
>>>>>>> + { .fw_name = "slv_lrclk0" },
>>>>>>> + { .fw_name = "slv_lrclk1" },
>>>>>>> + { .fw_name = "slv_lrclk2" },
>>>>>>> + { .fw_name = "slv_lrclk3" },
>>>>>>> + { .fw_name = "slv_lrclk4" },
>>>>>>> + { .fw_name = "slv_lrclk5" },
>>>>>>> + { .fw_name = "slv_lrclk6" },
>>>>>>> + { .fw_name = "slv_lrclk7" },
>>>>>>> + { .fw_name = "slv_lrclk8" },
>>>>>>> + { .fw_name = "slv_lrclk9" },
>>>>>>> +};
>>>>>>> +
>>>>>>> +#define AUDIO_TDM_SCLK(_name, _reg) \
>>>>>>> + AUDIO_MUX(_name##_mux, (_reg), 0xf, 24, a1_mst_sclk_pdata); \
>>>>>>> + AUDIO_GATE(_name##_pre_en, (_reg), 31, \
>>>>>>> + AUDIO_PDATA(_name##_mux)); \
>>>>>>> + AUDIO_GATE(_name##_post_en, (_reg), 30, \
>>>>>>> + AUDIO_PDATA(_name##_pre_en)); \
>>>>>>> + AUDIO_SCLK_WS(_name, (_reg), 1, 29, 28, \
>>>>>>> + AUDIO_PDATA(_name##_post_en))
>>>>>>> +
>>>>>>> +#define AUDIO_TDM_LRCLK(_name, _reg) \
>>>>>>> + AUDIO_MUX(_name, (_reg), 0xf, 20, a1_mst_lrclk_pdata)
>>>>>>> +
>>>>>>> +AUDIO_TDM_SCLK(audio_tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL);
>>>>>>> +AUDIO_TDM_SCLK(audio_tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL);
>>>>>>> +AUDIO_TDM_SCLK(audio_tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL);
>>>>>>> +AUDIO_TDM_SCLK(audio_tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL);
>>>>>>> +AUDIO_TDM_SCLK(audio_tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL);
>>>>>>> +
>>>>>>> +AUDIO_TDM_LRCLK(audio_tdmin_a_lrclk, AUDIO_CLK_TDMIN_A_CTRL);
>>>>>>> +AUDIO_TDM_LRCLK(audio_tdmin_b_lrclk, AUDIO_CLK_TDMIN_B_CTRL);
>>>>>>> +AUDIO_TDM_LRCLK(audio_tdmin_lb_lrclk, AUDIO_CLK_TDMIN_LB_CTRL);
>>>>>>> +AUDIO_TDM_LRCLK(audio_tdmout_a_lrclk, AUDIO_CLK_TDMOUT_A_CTRL);
>>>>>>> +AUDIO_TDM_LRCLK(audio_tdmout_b_lrclk, AUDIO_CLK_TDMOUT_B_CTRL);
>>>>>>> +
>>>>>>> +static struct clk_hw *a1_audio_hw_clks[] = {
>>>>>>> + [AUD_CLKID_DDR_ARB] = &audio_ddr_arb.hw,
>>>>>>> + [AUD_CLKID_TDMIN_A] = &audio_tdmin_a.hw,
>>>>>>> + [AUD_CLKID_TDMIN_B] = &audio_tdmin_b.hw,
>>>>>>> + [AUD_CLKID_TDMIN_LB] = &audio_tdmin_lb.hw,
>>>>>>> + [AUD_CLKID_LOOPBACK] = &audio_loopback.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_A] = &audio_tdmout_a.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_B] = &audio_tdmout_b.hw,
>>>>>>> + [AUD_CLKID_FRDDR_A] = &audio_frddr_a.hw,
>>>>>>> + [AUD_CLKID_FRDDR_B] = &audio_frddr_b.hw,
>>>>>>> + [AUD_CLKID_TODDR_A] = &audio_toddr_a.hw,
>>>>>>> + [AUD_CLKID_TODDR_B] = &audio_toddr_b.hw,
>>>>>>> + [AUD_CLKID_SPDIFIN] = &audio_spdifin.hw,
>>>>>>> + [AUD_CLKID_RESAMPLE] = &audio_resample.hw,
>>>>>>> + [AUD_CLKID_EQDRC] = &audio_eqdrc.hw,
>>>>>>> + [AUD_CLKID_LOCKER] = &audio_audiolocker.hw,
>>>>>>> + [AUD_CLKID_MST_A_MCLK_SEL] = &audio_mst_a_mclk_mux.hw,
>>>>>>> + [AUD_CLKID_MST_A_MCLK_DIV] = &audio_mst_a_mclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_A_MCLK] = &audio_mst_a_mclk.hw,
>>>>>>> + [AUD_CLKID_MST_B_MCLK_SEL] = &audio_mst_b_mclk_mux.hw,
>>>>>>> + [AUD_CLKID_MST_B_MCLK_DIV] = &audio_mst_b_mclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_B_MCLK] = &audio_mst_b_mclk.hw,
>>>>>>> + [AUD_CLKID_MST_C_MCLK_SEL] = &audio_mst_c_mclk_mux.hw,
>>>>>>> + [AUD_CLKID_MST_C_MCLK_DIV] = &audio_mst_c_mclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_C_MCLK] = &audio_mst_c_mclk.hw,
>>>>>>> + [AUD_CLKID_MST_D_MCLK_SEL] = &audio_mst_d_mclk_mux.hw,
>>>>>>> + [AUD_CLKID_MST_D_MCLK_DIV] = &audio_mst_d_mclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_D_MCLK] = &audio_mst_d_mclk.hw,
>>>>>>> + [AUD_CLKID_RESAMPLE_CLK_SEL] = &audio_resample_clk_mux.hw,
>>>>>>> + [AUD_CLKID_RESAMPLE_CLK_DIV] = &audio_resample_clk_div.hw,
>>>>>>> + [AUD_CLKID_RESAMPLE_CLK] = &audio_resample_clk.hw,
>>>>>>> + [AUD_CLKID_LOCKER_IN_CLK_SEL] = &audio_locker_in_clk_mux.hw,
>>>>>>> + [AUD_CLKID_LOCKER_IN_CLK_DIV] = &audio_locker_in_clk_div.hw,
>>>>>>> + [AUD_CLKID_LOCKER_IN_CLK] = &audio_locker_in_clk.hw,
>>>>>>> + [AUD_CLKID_LOCKER_OUT_CLK_SEL] = &audio_locker_out_clk_mux.hw,
>>>>>>> + [AUD_CLKID_LOCKER_OUT_CLK_DIV] = &audio_locker_out_clk_div.hw,
>>>>>>> + [AUD_CLKID_LOCKER_OUT_CLK] = &audio_locker_out_clk.hw,
>>>>>>> + [AUD_CLKID_SPDIFIN_CLK_SEL] = &audio_spdifin_clk_mux.hw,
>>>>>>> + [AUD_CLKID_SPDIFIN_CLK_DIV] = &audio_spdifin_clk_div.hw,
>>>>>>> + [AUD_CLKID_SPDIFIN_CLK] = &audio_spdifin_clk.hw,
>>>>>>> + [AUD_CLKID_EQDRC_CLK_SEL] = &audio_eqdrc_clk_mux.hw,
>>>>>>> + [AUD_CLKID_EQDRC_CLK_DIV] = &audio_eqdrc_clk_div.hw,
>>>>>>> + [AUD_CLKID_EQDRC_CLK] = &audio_eqdrc_clk.hw,
>>>>>>> + [AUD_CLKID_MST_A_SCLK_PRE_EN] = &audio_mst_a_sclk_pre_en.hw,
>>>>>>> + [AUD_CLKID_MST_A_SCLK_DIV] = &audio_mst_a_sclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_A_SCLK_POST_EN] = &audio_mst_a_sclk_post_en.hw,
>>>>>>> + [AUD_CLKID_MST_A_SCLK] = &audio_mst_a_sclk.hw,
>>>>>>> + [AUD_CLKID_MST_B_SCLK_PRE_EN] = &audio_mst_b_sclk_pre_en.hw,
>>>>>>> + [AUD_CLKID_MST_B_SCLK_DIV] = &audio_mst_b_sclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_B_SCLK_POST_EN] = &audio_mst_b_sclk_post_en.hw,
>>>>>>> + [AUD_CLKID_MST_B_SCLK] = &audio_mst_b_sclk.hw,
>>>>>>> + [AUD_CLKID_MST_C_SCLK_PRE_EN] = &audio_mst_c_sclk_pre_en.hw,
>>>>>>> + [AUD_CLKID_MST_C_SCLK_DIV] = &audio_mst_c_sclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_C_SCLK_POST_EN] = &audio_mst_c_sclk_post_en.hw,
>>>>>>> + [AUD_CLKID_MST_C_SCLK] = &audio_mst_c_sclk.hw,
>>>>>>> + [AUD_CLKID_MST_D_SCLK_PRE_EN] = &audio_mst_d_sclk_pre_en.hw,
>>>>>>> + [AUD_CLKID_MST_D_SCLK_DIV] = &audio_mst_d_sclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_D_SCLK_POST_EN] = &audio_mst_d_sclk_post_en.hw,
>>>>>>> + [AUD_CLKID_MST_D_SCLK] = &audio_mst_d_sclk.hw,
>>>>>>> + [AUD_CLKID_MST_A_LRCLK_DIV] = &audio_mst_a_lrclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_A_LRCLK] = &audio_mst_a_lrclk.hw,
>>>>>>> + [AUD_CLKID_MST_B_LRCLK_DIV] = &audio_mst_b_lrclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_B_LRCLK] = &audio_mst_b_lrclk.hw,
>>>>>>> + [AUD_CLKID_MST_C_LRCLK_DIV] = &audio_mst_c_lrclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_C_LRCLK] = &audio_mst_c_lrclk.hw,
>>>>>>> + [AUD_CLKID_MST_D_LRCLK_DIV] = &audio_mst_d_lrclk_div.hw,
>>>>>>> + [AUD_CLKID_MST_D_LRCLK] = &audio_mst_d_lrclk.hw,
>>>>>>> + [AUD_CLKID_TDMIN_A_SCLK_SEL] = &audio_tdmin_a_sclk_mux.hw,
>>>>>>> + [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &audio_tdmin_a_sclk_pre_en.hw,
>>>>>>> + [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &audio_tdmin_a_sclk_post_en.hw,
>>>>>>> + [AUD_CLKID_TDMIN_A_SCLK] = &audio_tdmin_a_sclk.hw,
>>>>>>> + [AUD_CLKID_TDMIN_A_LRCLK] = &audio_tdmin_a_lrclk.hw,
>>>>>>> + [AUD_CLKID_TDMIN_B_SCLK_SEL] = &audio_tdmin_b_sclk_mux.hw,
>>>>>>> + [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &audio_tdmin_b_sclk_pre_en.hw,
>>>>>>> + [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &audio_tdmin_b_sclk_post_en.hw,
>>>>>>> + [AUD_CLKID_TDMIN_B_SCLK] = &audio_tdmin_b_sclk.hw,
>>>>>>> + [AUD_CLKID_TDMIN_B_LRCLK] = &audio_tdmin_b_lrclk.hw,
>>>>>>> + [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &audio_tdmin_lb_sclk_mux.hw,
>>>>>>> + [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &audio_tdmin_lb_sclk_pre_en.hw,
>>>>>>> + [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &audio_tdmin_lb_sclk_post_en.hw,
>>>>>>> + [AUD_CLKID_TDMIN_LB_SCLK] = &audio_tdmin_lb_sclk.hw,
>>>>>>> + [AUD_CLKID_TDMIN_LB_LRCLK] = &audio_tdmin_lb_lrclk.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &audio_tdmout_a_sclk_mux.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &audio_tdmout_a_sclk_pre_en.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &audio_tdmout_a_sclk_post_en.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_A_SCLK] = &audio_tdmout_a_sclk.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_A_LRCLK] = &audio_tdmout_a_lrclk.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &audio_tdmout_b_sclk_mux.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &audio_tdmout_b_sclk_pre_en.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &audio_tdmout_b_sclk_post_en.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_B_SCLK] = &audio_tdmout_b_sclk.hw,
>>>>>>> + [AUD_CLKID_TDMOUT_B_LRCLK] = &audio_tdmout_b_lrclk.hw,
>>>>>>> +
>>>>>>> + [AUD2_CLKID_DDR_ARB] = &audio2_ddr_arb.hw,
>>>>>>> + [AUD2_CLKID_PDM] = &audio2_pdm.hw,
>>>>>>> + [AUD2_CLKID_TDMIN_VAD] = &audio2_tdmin_vad.hw,
>>>>>>> + [AUD2_CLKID_TODDR_VAD] = &audio2_toddr_vad.hw,
>>>>>>> + [AUD2_CLKID_VAD] = &audio2_vad.hw,
>>>>>>> + [AUD2_CLKID_AUDIOTOP] = &audio2_audiotop.hw,
>>>>>>> + [AUD2_CLKID_VAD_MCLK_SEL] = &audio2_vad_mclk_mux.hw,
>>>>>>> + [AUD2_CLKID_VAD_MCLK_DIV] = &audio2_vad_mclk_div.hw,
>>>>>>> + [AUD2_CLKID_VAD_MCLK] = &audio2_vad_mclk.hw,
>>>>>>> + [AUD2_CLKID_VAD_CLK_SEL] = &audio2_vad_clk_mux.hw,
>>>>>>> + [AUD2_CLKID_VAD_CLK_DIV] = &audio2_vad_clk_div.hw,
>>>>>>> + [AUD2_CLKID_VAD_CLK] = &audio2_vad_clk.hw,
>>>>>>> + [AUD2_CLKID_PDM_DCLK_SEL] = &audio2_pdm_dclk_mux.hw,
>>>>>>> + [AUD2_CLKID_PDM_DCLK_DIV] = &audio2_pdm_dclk_div.hw,
>>>>>>> + [AUD2_CLKID_PDM_DCLK] = &audio2_pdm_dclk.hw,
>>>>>>> + [AUD2_CLKID_PDM_SYSCLK_SEL] = &audio2_pdm_sysclk_mux.hw,
>>>>>>> + [AUD2_CLKID_PDM_SYSCLK_DIV] = &audio2_pdm_sysclk_div.hw,
>>>>>>> + [AUD2_CLKID_PDM_SYSCLK] = &audio2_pdm_sysclk.hw,
>>>>>>> +};
>>>>>>> +
>>>>>>> +static struct meson_clk_hw_data a1_audio_clks = {
>>>>>>> + .hws = a1_audio_hw_clks,
>>>>>>> + .num = ARRAY_SIZE(a1_audio_hw_clks),
>>>>>>> +};
>>>>>>> +
>>>>>>> +static struct regmap *a1_audio_map(struct platform_device *pdev,
>>>>>>> + unsigned int index)
>>>>>>> +{
>>>>>>> + char name[32];
>>>>>>> + const struct regmap_config cfg = {
>>>>>>> + .reg_bits = 32,
>>>>>>> + .val_bits = 32,
>>>>>>> + .reg_stride = 4,
>>>>>>> + .name = name,
>>>>>>
>>>>>> Not necessary
>>>>>>
>>>>>
>>>>> This implementation uses two regmaps, and this field allow to avoid
>>>>> errors like this:
>>>>>
>>>>> [ 0.145530] debugfs: Directory 'fe050000.audio-clock-controller' with
>>>>> parent 'regmap' already present!
>>>>>
>>>>>>> + };
>>>>>>> + void __iomem *base;
>>>>>>> +
>>>>>>> + base = devm_platform_ioremap_resource(pdev, index);
>>>>>>> + if (IS_ERR(base))
>>>>>>> + return base;
>>>>>>> +
>>>>>>> + scnprintf(name, sizeof(name), "%d", index);
>>>>>>> + return devm_regmap_init_mmio(&pdev->dev, base, &cfg);
>>>>>>> +}
>>>>>>
>>>>>> That is overengineered. Please keep it simple. Declare the regmap_config
>>>>>> as static const global, and do it like axg-audio please.
>>>>>>
>>>>>
>>>>> This only reason why it is not "static const" because I need to set
>>>>> unique name for each regmap.
>>>>>
>>>>>>> +
>>>>>>> +static int a1_register_clk(struct platform_device *pdev,
>>>>>>> + struct regmap *map0, struct regmap *map1,
>>>>>>> + struct clk_hw *hw)
>>>>>>> +{
>>>>>>> + struct clk_regmap *clk = container_of(hw, struct clk_regmap, hw);
>>>>>>> +
>>>>>>> + if (!hw)
>>>>>>> + return 0;
>>>>>>> +
>>>>>>> + switch ((unsigned long)clk->map) {
>>>>>>> + case AUDIO_RANGE_0:
>>>>>>> + clk->map = map0;
>>>>>>> + break;
>>>>>>> + case AUDIO_RANGE_1:
>>>>>>> + clk->map = map1;
>>>>>>> + break;
>>>>>>
>>>>>> ... fishy
>>>>>>
>>>>>>> + default:
>>>>>>> + WARN_ON(1);
>>>>>>> + return -EINVAL;
>>>>>>> + }
>>>>>>> +
>>>>>>> + return devm_clk_hw_register(&pdev->dev, hw);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int a1_audio_clkc_probe(struct platform_device *pdev)
>>>>>>> +{
>>>>>>> + struct regmap *map0, *map1;
>>>>>>> + struct clk *clk;
>>>>>>> + unsigned int i;
>>>>>>> + int ret;
>>>>>>> +
>>>>>>> + clk = devm_clk_get_enabled(&pdev->dev, "pclk");
>>>>>>> + if (WARN_ON(IS_ERR(clk)))
>>>>>>> + return PTR_ERR(clk);
>>>>>>> +
>>>>>>> + map0 = a1_audio_map(pdev, 0);
>>>>>>> + if (IS_ERR(map0))
>>>>>>> + return PTR_ERR(map0);
>>>>>>> +
>>>>>>> + map1 = a1_audio_map(pdev, 1);
>>>>>>> + if (IS_ERR(map1))
>>>>>>> + return PTR_ERR(map1);
>>>>>>
>>>>>> No - Looks to me you just have two clock controllers you are trying
>>>>>> force into one.
>>>>>>
>>>>>
>>>>> See the begining.
>>>>>
>>>>>>> +
>>>>>>> + /*
>>>>>>> + * Register and enable AUD2_CLKID_AUDIOTOP clock first. Unless
>>>>>>> + * it is enabled any read/write to 'map0' hangs the CPU.
>>>>>>> + */
>>>>>>> +
>>>>>>> + ret = a1_register_clk(pdev, map0, map1,
>>>>>>> + a1_audio_clks.hws[AUD2_CLKID_AUDIOTOP]);
>>>>>>> + if (ret)
>>>>>>> + return ret;
>>>>>>> +
>>>>>>> + ret = clk_prepare_enable(a1_audio_clks.hws[AUD2_CLKID_AUDIOTOP]->clk);
>>>>>>> + if (ret)
>>>>>>> + return ret;
>>>>>>
>>>>>> Again, this shows 2 devices. The one related to your 'map0' should
>>>>>> request AUD2_CLKID_AUDIOTOP as input and enable it right away.
>>>>>>
>>>>>
>>>>> See the begining.
>>>>>
>>>>>>> +
>>>>>>> + for (i = 0; i < a1_audio_clks.num; i++) {
>>>>>>> + if (i == AUD2_CLKID_AUDIOTOP)
>>>>>>> + continue;
>>>>>>> +
>>>>>>> + ret = a1_register_clk(pdev, map0, map1, a1_audio_clks.hws[i]);
>>>>>>> + if (ret)
>>>>>>> + return ret;
>>>>>>> + }
>>>>>>> +
>>>>>>> + ret = devm_of_clk_add_hw_provider(&pdev->dev, meson_clk_hw_get,
>>>>>>> + &a1_audio_clks);
>>>>>>> + if (ret)
>>>>>>> + return ret;
>>>>>>> +
>>>>>>> + BUILD_BUG_ON((unsigned long)AUDIO_REG_MAP(AUDIO_SW_RESET0) !=
>>>>>>> + AUDIO_RANGE_0);
>>>>>>
>>>>>> Why is that necessary ?
>>>>>>
>>>>>
>>>>> A little paranoia. Here AUDIO_SW_RESET0 is handled as map0's register,
>>>>> and I want to assert it.
>>>>>
>>>>>>> + return meson_audio_rstc_register(&pdev->dev, map0,
>>>>>>> + AUDIO_REG_OFFSET(AUDIO_SW_RESET0), 32);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static const struct of_device_id a1_audio_clkc_match_table[] = {
>>>>>>> + { .compatible = "amlogic,a1-audio-clkc", },
>>>>>>> + {}
>>>>>>> +};
>>>>>>> +MODULE_DEVICE_TABLE(of, a1_audio_clkc_match_table);
>>>>>>> +
>>>>>>> +static struct platform_driver a1_audio_clkc_driver = {
>>>>>>> + .probe = a1_audio_clkc_probe,
>>>>>>> + .driver = {
>>>>>>> + .name = "a1-audio-clkc",
>>>>>>> + .of_match_table = a1_audio_clkc_match_table,
>>>>>>> + },
>>>>>>> +};
>>>>>>> +module_platform_driver(a1_audio_clkc_driver);
>>>>>>> +
>>>>>>> +MODULE_DESCRIPTION("Amlogic A1 Audio Clock driver");
>>>>>>> +MODULE_AUTHOR("Jan Dakinevich <jan.dakinevich@salutedevices.com>");
>>>>>>> +MODULE_LICENSE("GPL");
>>>>>>> diff --git a/drivers/clk/meson/a1-audio.h b/drivers/clk/meson/a1-audio.h
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..f994e87276cd
>>>>>>> --- /dev/null
>>>>>>> +++ b/drivers/clk/meson/a1-audio.h
>>>>>>> @@ -0,0 +1,58 @@
>>>>>>> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
>>>>>>> +/*
>>>>>>> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
>>>>>>> + *
>>>>>>> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>>>>>>> + */
>>>>>>> +
>>>>>>> +#ifndef __A1_AUDIO_H
>>>>>>> +#define __A1_AUDIO_H
>>>>>>> +
>>>>>>> +#define AUDIO_RANGE_0 0xa
>>>>>>> +#define AUDIO_RANGE_1 0xb
>>>>>>> +#define AUDIO_RANGE_SHIFT 16
>>>>>>> +
>>>>>>> +#define AUDIO_REG(_range, _offset) \
>>>>>>> + (((_range) << AUDIO_RANGE_SHIFT) + (_offset))
>>>>>>> +
>>>>>>> +#define AUDIO_REG_OFFSET(_reg) \
>>>>>>> + ((_reg) & ((1 << AUDIO_RANGE_SHIFT) - 1))
>>>>>>> +
>>>>>>> +#define AUDIO_REG_MAP(_reg) \
>>>>>>> + ((void *)((_reg) >> AUDIO_RANGE_SHIFT))
>>>>>>
>>>>>> That is seriouly overengineered.
>>>>>> The following are offset. Just write what they are.
>>>>>>
>>>>>
>>>>> This is all in order to keep range's identifier together with offset and
>>>>> then use it to store the identifier in clk_regmaps.
>>>>>
>>>>>> There is not reason to put that into a header. It is only going to be
>>>>>> used by a single driver.
>>>>>>>> +
>>>>>>> +#define AUDIO_CLK_GATE_EN0 AUDIO_REG(AUDIO_RANGE_0, 0x000)
>>>>>>> +#define AUDIO_MCLK_A_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x008)
>>>>>>> +#define AUDIO_MCLK_B_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x00c)
>>>>>>> +#define AUDIO_MCLK_C_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x010)
>>>>>>> +#define AUDIO_MCLK_D_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x014)
>>>>>>> +#define AUDIO_MCLK_E_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x018)
>>>>>>> +#define AUDIO_MCLK_F_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x01c)
>>>>>>> +#define AUDIO_SW_RESET0 AUDIO_REG(AUDIO_RANGE_0, 0x028)
>>>>>>> +#define AUDIO_MST_A_SCLK_CTRL0 AUDIO_REG(AUDIO_RANGE_0, 0x040)
>>>>>>> +#define AUDIO_MST_A_SCLK_CTRL1 AUDIO_REG(AUDIO_RANGE_0, 0x044)
>>>>>>> +#define AUDIO_MST_B_SCLK_CTRL0 AUDIO_REG(AUDIO_RANGE_0, 0x048)
>>>>>>> +#define AUDIO_MST_B_SCLK_CTRL1 AUDIO_REG(AUDIO_RANGE_0, 0x04c)
>>>>>>> +#define AUDIO_MST_C_SCLK_CTRL0 AUDIO_REG(AUDIO_RANGE_0, 0x050)
>>>>>>> +#define AUDIO_MST_C_SCLK_CTRL1 AUDIO_REG(AUDIO_RANGE_0, 0x054)
>>>>>>> +#define AUDIO_MST_D_SCLK_CTRL0 AUDIO_REG(AUDIO_RANGE_0, 0x058)
>>>>>>> +#define AUDIO_MST_D_SCLK_CTRL1 AUDIO_REG(AUDIO_RANGE_0, 0x05c)
>>>>>>> +#define AUDIO_CLK_TDMIN_A_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x080)
>>>>>>> +#define AUDIO_CLK_TDMIN_B_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x084)
>>>>>>> +#define AUDIO_CLK_TDMIN_LB_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x08c)
>>>>>>> +#define AUDIO_CLK_TDMOUT_A_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x090)
>>>>>>> +#define AUDIO_CLK_TDMOUT_B_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x094)
>>>>>>> +#define AUDIO_CLK_SPDIFIN_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x09c)
>>>>>>> +#define AUDIO_CLK_RESAMPLE_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x0a4)
>>>>>>> +#define AUDIO_CLK_LOCKER_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x0a8)
>>>>>>> +#define AUDIO_CLK_EQDRC_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x0c0)
>>>>>>> +
>>>>>>> +#define AUDIO2_CLK_GATE_EN0 AUDIO_REG(AUDIO_RANGE_1, 0x00c)
>>>>>>> +#define AUDIO2_MCLK_VAD_CTRL AUDIO_REG(AUDIO_RANGE_1, 0x040)
>>>>>>> +#define AUDIO2_CLK_VAD_CTRL AUDIO_REG(AUDIO_RANGE_1, 0x044)
>>>>>>> +#define AUDIO2_CLK_PDMIN_CTRL0 AUDIO_REG(AUDIO_RANGE_1, 0x058)
>>>>>>> +#define AUDIO2_CLK_PDMIN_CTRL1 AUDIO_REG(AUDIO_RANGE_1, 0x05c)
>>>>>>> +
>>>>>>> +#include <dt-bindings/clock/amlogic,a1-audio-clkc.h>
>>>>>>> +
>>>>>>> +#endif /* __A1_AUDIO_H */
>>>>>>
>>>>>>
>>>>
>>>>
>>
>>
--
Jerome
^ permalink raw reply
* Re: [PATCH v8 09/10] ARM: dts: bcm2711-rpi-4-b: Add CAM1 regulator
From: Dave Stevenson @ 2024-03-27 14:49 UTC (permalink / raw)
To: Laurent Pinchart
Cc: linux-media, David Plowman, Jean-Michel Hautbois, Hans Verkuil,
Naushir Patuck, Sakari Ailus, kernel-list, linux-rpi-kernel,
Florian Fainelli, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Conor Dooley, Krzysztof Kozlowski,
Rob Herring, devicetree
In-Reply-To: <20240327000510.2541-10-laurent.pinchart@ideasonboard.com>
Hi Laurent
On Wed, 27 Mar 2024 at 00:05, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>
> Add a fixed regulator to model the power supply to the camera connector.
As with the I2C0 mux stuff, this ideally wants to be generic rather
than 2711 only, but I'm happy to get it merged for Pi4 first and then
add the others.
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts
> index d5f8823230db..cfc8cb5e10ba 100644
> --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts
> +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts
> @@ -15,6 +15,13 @@ chosen {
> stdout-path = "serial1:115200n8";
> };
>
> + cam1_reg: regulator-cam1 {
> + compatible = "regulator-fixed";
> + regulator-name = "cam1-reg";
> + enable-active-high;
> + gpio = <&expgpio 5 GPIO_ACTIVE_HIGH>;
> + };
> +
> sd_io_1v8_reg: regulator-sd-io-1v8 {
> compatible = "regulator-gpio";
> regulator-name = "vdd-sd-io";
> --
> Regards,
>
> Laurent Pinchart
>
^ permalink raw reply
* Re: [PATCH] media: dt-bindings: ovti,ov2680: Document clock/data-lanes
From: Fabio Estevam @ 2024-03-27 14:50 UTC (permalink / raw)
To: Sakari Ailus
Cc: rmfrfs, robh, krzysztof.kozlowski+dt, conor+dt, linux-media,
devicetree, Fabio Estevam
In-Reply-To: <ZgPtolH796HER4cP@kekkonen.localdomain>
Hi Sakari,
On Wed, Mar 27, 2024 at 6:58 AM Sakari Ailus
<sakari.ailus@linux.intel.com> wrote:
> If there's a single possible configuration only, is this needed? There's no
> information here which the driver would need.
Good point.
In this case, the correct fix would be to remove 'clock-lanes' and
'data-lanes' from imx7s-warp.dts.
^ permalink raw reply
* Re: [PATCH v8 00/10] media: Add driver for the Raspberry Pi <5 CSI-2 receiver
From: Dave Stevenson @ 2024-03-27 14:54 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Florian Fainelli, linux-media, David Plowman,
Jean-Michel Hautbois, Hans Verkuil, Naushir Patuck, Sakari Ailus,
kernel-list, linux-rpi-kernel, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Conor Dooley, Krzysztof Kozlowski,
Rob Herring, devicetree
In-Reply-To: <20240327001220.GA26859@pendragon.ideasonboard.com>
Hi Laurent
On Wed, 27 Mar 2024 at 00:12, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>
> Hi Florian,
>
> I think patches 04/10 ("ARM: dts: bcm2835-rpi: Move firmware-clocks from
> bcm2711 to bcm2835"), 07/10 ("ARM: dts: bcm2711-rpi: Add pinctrl-based
> multiplexing for I2C0"a), 08/10 ("ARM: dts: bcm2711-rpi-cm4-io: Add RTC on
> I2C0") and 09/10 ("ARM: dts: bcm2711-rpi-4-b: Add CAM1 regulator") are
> ready for you to merge. This would help reducing further iterations of
> this series.
>
> A review from Dave would be nice for 05/10 and 09/10 though.
Done.
Please do nudge me if there are patches you specifically want me to
review. I'm not directly involved in the camera side at present, so
only keeping a passing eye on these patchsets.
Dave
> On Wed, Mar 27, 2024 at 02:04:58AM +0200, Laurent Pinchart wrote:
> > Hello everybody,
> >
> > This patch series adds a new driver for the BCM2835 (and derivative)
> > CCP2/CSI2 camera interface named Unicam. This IP core is found in the
> > VC4-based Raspberry Pi, namely the Pi Zero, Pi 3 and Pi 4.
> >
> > Camera support for Raspberry Pi 4 currently relies on a downstream
> > Unicam driver that live in the Raspberry Pi kernel tree ([1]). The
> > driver uses the V4L2 API, but works around the lack of features in V4L2
> > to properly support sensor embedded data. Since the Unicam driver
> > development by Raspberry Pi, some of those features have been merged in
> > the kernel (namely the V4L2 streams API) or are being developed (namely
> > generic metadata formats and subdev internal pads), with patches posted
> > for review on the linux-media mailing list ([2]).
> >
> > This new upstream driver is based on the downstream code, extensively
> > reworked to use the new V4L2 APIs.
> >
> > The series is based on a merge of
> >
> > - v8 of the generic metadata and internal pads, rebased on v6.9-rc1 ([3])
> > - the downstream ISP driver ported to mainline ([4])
> >
> > with a set of patches for the imx219 driver applied on top. For
> > convenience, it can be found in [5]. Note that the ISP driver is getting
> > upstreamed separately.
> >
> > Compared to v7, I have left the imx219 patches out, as they don't need
> > to be bundled with the Unicam driver for review. They will be
> > resubmitted separately.
> >
> > The series starts with four patches that add the Unicam driver (04/10),
> > with new V4L2 pixel formats (01/10 and 02/10) and DT bindings (03/10).
> > The remaining patches cover DT integration (05/10 to 09/10) with a
> > sample DT overlay for the IMX219 camera module (10/10).
> >
> > The patches have been tested on a Raspberry Pi 4 using an IMX219 camera
> > module (the Raspberry Pi camera v2), with libcamera. Updates are needed
> > to libcamera to use the new V4L2 APIs, patches have been posted to [6].
> > For manual testing with media-ctl, corresponding API updates to
> > v4l-utils are available at [7].
> >
> > While more work is needed to be able to merge the generic metadata API
> > (namely implementing support for the latest API version in media-ctl and
> > v4l2-compliance), I'm happy with the unicam implementation, and I
> > believe we're really nearing completion. This series, along with the
> > libcamera support, help validating the new kernel APIs. We have reached
> > a point where we can start converting other sensor drivers from the
> > downstream Raspberry Pi kernel to the standard APIs for embedded data,
> > as well as integrating the APIs in the Raspberry Pi 5 CFE driver.
> >
> > [1] https://github.com/raspberrypi/linux/tree/rpi-6.1.y/drivers/media/platform/bcm2835
> > [2] https://lore.kernel.org/linux-media/20240313072516.241106-1-sakari.ailus@linux.intel.com/
> > [3] https://git.kernel.org/pub/scm/linux/kernel/git/pinchartl/linux.git/log/?h=rpi/v6.9/metadata/v8
> > [4] https://git.kernel.org/pub/scm/linux/kernel/git/pinchartl/linux.git/log/?h=rpi/v6.9/isp/v2
> > [5] https://git.kernel.org/pub/scm/linux/kernel/git/pinchartl/linux.git/log/?h=rpi/v6.9/unicam/next
> > [6] https://lists.libcamera.org/pipermail/libcamera-devel/2024-March/040711.html
> > [7] https://git.linuxtv.org/pinchartl/v4l-utils.git/log/?h=metadata
> >
> > Dave Stevenson (2):
> > dt-bindings: media: Add bindings for bcm2835-unicam
> > media: bcm2835-unicam: Add support for CCP2/CSI2 camera interface
> >
> > Jean-Michel Hautbois (3):
> > media: v4l: Add V4L2-PIX-FMT-Y12P format
> > media: v4l: Add V4L2-PIX-FMT-Y14P format
> > ARM: dts: bcm2835: Add Unicam CSI nodes
> >
> > Laurent Pinchart (3):
> > ARM: dts: bcm2835-rpi: Move firmware-clocks from bcm2711 to bcm2835
> > ARM: dts: bcm2711-rpi-4-b: Add CAM1 regulator
> > [DNI] arm64: dts: broadcom: Add overlay for Raspberry Pi 4B IMX219
> > camera
> >
> > Uwe Kleine-König (2):
> > ARM: dts: bcm2711-rpi: Add pinctrl-based multiplexing for I2C0
> > ARM: dts: bcm2711-rpi-cm4-io: Add RTC on I2C0
> >
> > .../bindings/media/brcm,bcm2835-unicam.yaml | 127 +
> > .../media/v4l/pixfmt-yuv-luma.rst | 48 +
> > MAINTAINERS | 7 +
> > .../arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts | 7 +
> > .../boot/dts/broadcom/bcm2711-rpi-cm4-io.dts | 9 +
> > arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi | 34 +-
> > arch/arm/boot/dts/broadcom/bcm2711.dtsi | 8 +
> > arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi | 19 +
> > arch/arm/boot/dts/broadcom/bcm283x.dtsi | 24 +
> > arch/arm64/boot/dts/broadcom/Makefile | 4 +
> > .../dts/broadcom/bcm2711-rpi-4-b-imx219.dtso | 65 +
> > drivers/media/platform/Kconfig | 1 +
> > drivers/media/platform/Makefile | 1 +
> > drivers/media/platform/broadcom/Kconfig | 23 +
> > drivers/media/platform/broadcom/Makefile | 3 +
> > .../platform/broadcom/bcm2835-unicam-regs.h | 246 ++
> > .../media/platform/broadcom/bcm2835-unicam.c | 2671 +++++++++++++++++
> > drivers/media/v4l2-core/v4l2-ioctl.c | 2 +
> > include/uapi/linux/videodev2.h | 2 +
> > 19 files changed, 3296 insertions(+), 5 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
> > create mode 100644 arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b-imx219.dtso
> > create mode 100644 drivers/media/platform/broadcom/Kconfig
> > create mode 100644 drivers/media/platform/broadcom/Makefile
> > create mode 100644 drivers/media/platform/broadcom/bcm2835-unicam-regs.h
> > create mode 100644 drivers/media/platform/broadcom/bcm2835-unicam.c
> >
> >
> > base-commit: 37a950b8e140e3bd97d22943ba860542111d64fe
>
> --
> Regards,
>
> Laurent Pinchart
^ permalink raw reply
* Re: [PATCH v4 0/3] arm64: dts: qcom: apq8016: Add Schneider HMIBSC board DTS
From: Rob Herring @ 2024-03-27 15:41 UTC (permalink / raw)
To: Sumit Garg
Cc: krzysztof.kozlowski+dt, robh+dt, benjamin.missey, konrad.dybcio,
dmitry.baryshkov, neil.armstrong, pascal.eberhard, devicetree,
andersson, daniel.thompson, jimmy.lalande, conor+dt, stephan,
linux-arm-msm, caleb.connolly, abdou.saker, linux-kernel,
laetitia.mariottini
In-Reply-To: <20240327063734.3236117-1-sumit.garg@linaro.org>
On Wed, 27 Mar 2024 12:07:31 +0530, Sumit Garg wrote:
> Add Schneider Electric HMIBSC board DTS. The HMIBSC board is an IIoT Edge
> Box Core board based on the Qualcomm APQ8016E SoC. For more information
> refer to the product page [1].
>
> One of the major difference from db410c is serial port where HMIBSC board
> uses UART1 as the debug console with a default RS232 mode (UART1 mode mux
> configured via gpio99 and gpio100).
>
> Support for Schneider Electric HMIBSC. Features:
> - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
> - 1GiB RAM
> - 8GiB eMMC, SD slot
> - WiFi and Bluetooth
> - 2x Host, 1x Device USB port
> - HDMI
> - Discrete TPM2 chip over SPI
> - USB ethernet adaptors (soldered)
>
> This series is a v2 since v1 of this DTS file has been reviewed on the
> U-Boot mailing list [2].
>
> Changes in v4:
> - Dropped IRQ_TYPE_EDGE_FALLING for pm8916_resin given the expectations
> of Linux kernel driver. Instead depend on systemd workaround suggested
> by Caleb to get expected HMIBSC reset behaviour.
> - Incorporated further DT coding style comments from Stephen.
> - Warnings reported by Rob's DT check bot aren't related to HMIBSC
> board DTS but rather they are due to msm8916.dtsi or extcon-usb-gpio.txt
> still not converted to YAML format.
>
> Changes in v3:
> - Picked up tags.
> - Fixed further DT schema warnings.
> - Configure resin/power button interrupt as falling edge.
> - Incorporate DTS coding style comments from Krzysztof and Konrad.
>
> Changes in v2:
> - Fix DT schema warnings.
> - Incorporate suggestions from Stephan.
> - Document UART1 mode GPIOs based mux.
>
> [1] https://www.se.com/us/en/product/HMIBSCEA53D1L0T/iiot-edge-box-core-harmony-ipc-emmc-dc-linux-tpm/
> [2] https://patchwork.ozlabs.org/project/uboot/patch/20240311111027.44577-6-sumit.garg@linaro.org/
>
> Sumit Garg (3):
> dt-bindings: vendor-prefixes: Add Schneider Electric
> dt-bindings: arm: qcom: Add Schneider Electric HMIBSC board
> arm64: dts: qcom: apq8016: Add Schneider HMIBSC board DTS
>
> .../devicetree/bindings/arm/qcom.yaml | 1 +
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../dts/qcom/apq8016-schneider-hmibsc.dts | 490 ++++++++++++++++++
> 4 files changed, 494 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts
>
> --
> 2.34.1
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y qcom/apq8016-schneider-hmibsc.dtb' for 20240327063734.3236117-1-sumit.garg@linaro.org:
arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dtb: /soc@0/audio-codec@771c000: failed to match any schema with compatible: ['qcom,msm8916-wcd-digital-codec']
arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dtb: /soc@0/power-manager@b088000: failed to match any schema with compatible: ['qcom,msm8916-acc']
arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dtb: /soc@0/power-manager@b098000: failed to match any schema with compatible: ['qcom,msm8916-acc']
arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dtb: /soc@0/power-manager@b0a8000: failed to match any schema with compatible: ['qcom,msm8916-acc']
arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dtb: /soc@0/power-manager@b0b8000: failed to match any schema with compatible: ['qcom,msm8916-acc']
arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dtb: /usb-id: failed to match any schema with compatible: ['linux,extcon-usb-gpio']
^ permalink raw reply
* Re: [PATCH 0/7] regulator: mcp16502: Update the names from buck regulators
From: Rob Herring @ 2024-03-27 15:41 UTC (permalink / raw)
To: Mihai Sain
Cc: alexandre.belloni, devicetree, lgirdwood, linux-arm-kernel,
krzysztof.kozlowski+dt, linux-kernel, broonie, andrei.simion,
nicolas.ferre, conor+dt, claudiu.beznea
In-Reply-To: <20240327101724.2982-1-mihai.sain@microchip.com>
On Wed, 27 Mar 2024 12:17:17 +0200, Mihai Sain wrote:
> Use generic names for buck regulators to avoid any confusion.
> Update the names from buck regulators in order to match
> the datasheet block diagram for the buck regulators.
> Using BUCK1-4 as node names is consistent with the node naming rules.
>
> Link: https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP16502-Data-Sheet-DS20006275.pdf
>
> Mihai Sain (7):
> ARM: dts: microchip: sama5d27_wlsom1: Update the node names from pmic-regulators
> ARM: dts: microchip: sama5d29_curiosity: Update the node names from pmic-regulators
> ARM: dts: microchip: sama5d2_icp: Update the node names from pmic-regulators
> ARM: dts: microchip: sama7g54_curiosity: Update the node names from pmic-regulators
> ARM: dts: microchip: sama7g5ek: Update the node names from pmic-regulators
> regulator: dt-bindings: microchip,mcp16502: Update the node names from buck regulators
> regulator: mcp16502: Update the names from buck regulators
>
> .../bindings/regulator/microchip,mcp16502.yaml | 10 +++++-----
> arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi | 8 ++++----
> .../arm/boot/dts/microchip/at91-sama5d29_curiosity.dts | 8 ++++----
> arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts | 8 ++++----
> .../arm/boot/dts/microchip/at91-sama7g54_curiosity.dts | 8 ++++----
> arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 8 ++++----
> drivers/regulator/mcp16502.c | 8 ++++----
> 7 files changed, 29 insertions(+), 29 deletions(-)
>
> --
> 2.44.0
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y microchip/at91-sama5d29_curiosity.dtb microchip/at91-sama5d2_icp.dtb microchip/at91-sama7g54_curiosity.dtb microchip/at91-sama7g5ek.dtb' for 20240327101724.2982-1-mihai.sain@microchip.com:
arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dtb: ahb: apb: {'compatible': ['simple-bus'], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': True, 'hlcdc@f0000000': {'compatible': ['atmel,sama5d2-hlcdc'], 'reg': [[4026531840, 8192]], 'interrupts': [[45, 4, 0]], 'clocks': [[3, 2, 45], [3, 1, 3], [16]], 'clock-names': ['periph_clk', 'sys_clk', 'slow_clk'], 'status': ['disabled'], 'phandle': [[52]], 'hlcdc-display-controller': {'compatible': ['atmel,hlcdc-display-controller'], '#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'#address-cells': [[1]], '#size-cells': [[0]], 'reg': [[0]]}}, 'hlcdc-pwm': {'compatible': ['atmel,hlcdc-pwm'], '#pwm-cells': [[3]], 'phandle': [[53]]}}, 'isc@f0008000': {'compatible': ['atmel,sama5d2-isc'], 'reg': [[4026564608, 16384]], 'interrupts': [[46, 4, 5]], 'clocks': [[3, 2, 46], [3, 1, 18], [3, 3, 46]], 'clock-names': ['hclock', 'iscck', 'gck'], '#clock-cells': [[0]], 'clock-output-names': ['isc-mck'], 'status': ['disabled'], 'phandle': [[54]]}, 'ramc@f000c000': {'compatible': ['atmel,sama5d3-ddramc'], 'reg': [[4026580992, 512]], 'clocks': [[3, 1, 2], [3, 2, 13]], 'clock-names': ['ddrck', 'mpddr'], 'phandle': [[55]]}, 'dma-controller@f0010000': {'compatible': ['atmel,sama5d4-dma'], 'reg': [[4026597376, 4096]], 'interrupts': [[6, 4, 0]], '#dma-cells': [[1]], 'clocks': [[3, 2, 6]], 'clock-names': ['dma_clk'], 'phandle': [[19]]}, 'dma-controller@f0004000': {'compatible': ['atmel,sama5d4-dma'], 'reg': [[4026548224, 4096]], 'interrupts': [[7, 4, 0]], '#dma-cells': [[1]], 'clocks': [[3, 2, 7]], 'clock-names': ['dma_clk'], 'phandle': [[31]]}, 'clock-controller@f0014000': {'compatible': ['atmel,sama5d2-pmc', 'syscon'], 'reg': [[4026613760, 352]], 'interrupts': [[74, 4, 7]], '#clock-cells': [[2]], 'clocks': [[16], [17]], 'clock-names': ['slow_clk', 'main_xtal'], 'phandle': [[3]]}, 'spi@f0020000': {'compatible': ['atmel,sama5d2-qspi'], 'reg': [[4026662912, 256], [3489660928, 134217728]], 'reg-names': ['qspi_base', 'qspi_mmap'], 'interrupts': [[52, 4, 7]], 'clocks': [[3, 2, 52]], 'clock-names': ['pclk'], '#address-cells': [[1]], '#size-cells': [[0]], 'status': ['disabled'], 'phandle': [[56]]}, 'spi@f0024000': {'compatible': ['atmel,sama5d2-qspi'], 'reg': [[4026679296, 256], [3623878656, 134217728]], 'reg-names': ['qspi_base', 'qspi_mmap'], 'interrupts': [[53, 4, 7]], 'clocks': [[3, 2, 53]], 'clock-names': ['pclk'], '#address-cells': [[1]], '#size-cells': [[0]], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[18]], 'phandle': [[57]], 'flash@0': {'#address-cells': [[1]], '#size-cells': [[1]], 'compatible': ['jedec,spi-nor'], 'reg': [[0]], 'spi-max-frequency': [[80000000]], 'spi-tx-bus-width': [[4]], 'spi-rx-bus-width': [[4]], 'm25p,fast-read': True, 'label': ['atmel_qspi1'], 'status': ['okay'], 'at91bootstrap@0': {'label': ['at91bootstrap'], 'reg': [[0, 262144]]}, 'bootloader@40000': {'label': ['bootloader'], 'reg': [[262144, 786432]]}, 'bootloaderenvred@100000': {'label': ['bootloader env redundant'], 'reg': [[1048576, 262144]]}, 'bootloaderenv@140000': {'label': ['bootloader env'], 'reg': [[1310720, 262144]]}, 'dtb@180000': {'label': ['device tree'], 'reg': [[1572864, 524288]]}, 'kernel@200000': {'label': ['kernel'], 'reg': [[2097152, 6291456]]}}}, 'crypto@f0028000': {'compatible': ['atmel,at91sam9g46-sha'], 'reg': [[4026695680, 256]], 'interrupts': [[12, 4, 0]], 'dmas': [[19, 503332864]], 'dma-names': ['tx'], 'clocks': [[3, 2, 12]], 'clock-names': ['sha_clk'], 'phandle': [[58]]}, 'crypto@f002c000': {'compatible': ['atmel,at91sam9g46-aes'], 'reg': [[4026712064, 256]], 'interrupts': [[9, 4, 0]], 'dmas': [[19, 436224000], [19, 453001216]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 9]], 'clock-names': ['aes_clk'], 'phandle': [[59]]}, 'spi@f8000000': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[4160749568, 256]], 'interrupts': [[33, 4, 7]], 'dmas': [[19, 100679680], [19, 117456896]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 33]], 'clock-names': ['spi_clk'], 'atmel,fifo-size': [[16]], '#address-cells': [[1]], '#size-cells': [[0]], 'status': ['disabled'], 'phandle': [[60]]}, 'ssc@f8004000': {'compatible': ['atmel,at91sam9g45-ssc'], 'reg': [[4160765952, 16384]], 'interrupts': [[43, 4, 4]], 'dmas': [[19, 352337920], [19, 369115136]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 43]], 'clock-names': ['pclk'], 'status': ['disabled'], 'phandle': [[61]]}, 'ethernet@f8008000': {'compatible': ['atmel,sama5d29-gem'], 'reg': [[4160782336, 4096]], 'interrupts': [[5, 4, 3], [66, 4, 3], [67, 4, 3]], 'clocks': [[3, 2, 5], [3, 2, 5]], 'clock-names': ['hclk', 'pclk'], 'status': ['disabled'], 'phandle': [[62]]}, 'timer@f800c000': {'compatible': ['atmel,sama5d2-tcb', 'simple-mfd', 'syscon'], '#address-cells': [[1]], '#size-cells': [[0]], 'reg': [[4160798720, 256]], 'interrupts': [[35, 4, 0]], 'clocks': [[3, 2, 35], [3, 3, 35], [16]], 'clock-names': ['t0_clk', 'gclk', 'slow_clk'], 'phandle': [[63]], 'timer@0': {'compatible': ['atmel,tcb-timer'], 'reg': [[0]], 'phandle': [[64]]}, 'timer@1': {'compatible': ['atmel,tcb-timer'], 'reg': [[1]], 'phandle': [[65]]}}, 'timer@f8010000': {'compatible': ['atmel,sama5d2-tcb', 'simple-mfd', 'syscon'], '#address-cells': [[1]], '#size-cells': [[0]], 'reg': [[4160815104, 256]], 'interrupts': [[36, 4, 0]], 'clocks': [[3, 2, 36], [3, 3, 36], [16]], 'clock-names': ['t0_clk', 'gclk', 'slow_clk'], 'phandle': [[66]]}, 'hsmc@f8014000': {'compatible': ['atmel,sama5d2-smc', 'syscon', 'simple-mfd'], 'reg': [[4160831488, 4096]], 'interrupts': [[17, 4, 6]], 'clocks': [[3, 2, 17]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': True, 'phandle': [[10]], 'ecc-engine@f8014070': {'compatible': ['atmel,sama5d2-pmecc'], 'reg': [[4160831600, 1168], [4160832768, 512]], 'phandle': [[13]]}}, 'pdmic@f8018000': {'compatible': ['atmel,sama5d2-pdmic'], 'reg': [[4160847872, 292]], 'interrupts': [[48, 4, 7]], 'dmas': [[19, 838877184]], 'dma-names': ['rx'], 'clocks': [[3, 2, 48], [3, 3, 48]], 'clock-names': ['pclk', 'gclk'], 'status': ['disabled'], 'phandle': [[67]]}, 'serial@f801c000': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[4160864256, 256]], 'atmel,usart-mode': [[0]], 'interrupts': [[24, 4, 7]], 'dmas': [[19, 587218944], [19, 603996160]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 24]], 'clock-names': ['usart'], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[20]], 'atmel,use-dma-rx': True, 'atmel,use-dma-tx': True, 'phandle': [[68]]}, 'serial@f8020000': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[4160880640, 256]], 'atmel,usart-mode': [[0]], 'interrupts': [[25, 4, 7]], 'dmas': [[19, 620773376], [19, 637550592]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 25]], 'clock-names': ['usart'], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[21]], 'atmel,use-dma-rx': True, 'atmel,use-dma-tx': True, 'phandle': [[69]]}, 'serial@f8024000': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[4160897024, 256]], 'atmel,usart-mode': [[0]], 'interrupts': [[26, 4, 7]], 'dmas': [[19, 654327808], [19, 671105024]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 26]], 'clock-names': ['usart'], 'status': ['disabled'], 'phandle': [[70]]}, 'i2c@f8028000': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[4160913408, 256]], 'interrupts': [[29, 4, 7]], 'dmas': [[0], [0]], 'dma-names': ['tx', 'rx'], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 29]], 'atmel,fifo-size': [[16]], 'status': ['okay'], 'pinctrl-names': ['default', 'gpio'], 'pinctrl-0': [[22]], 'pinctrl-1': [[23]], 'sda-gpios': [[7, 63, 0]], 'scl-gpios': [[7, 64, 6]], 'i2c-sda-hold-time-ns': [[350]], 'phandle': [[71]], 'mcp16502@5b': {'compatible': ['microchip,mcp16502'], 'reg': [[91]], 'status': ['okay'], 'lpm-gpios': [[24, 0, 1]], 'regulators': {'BUCK1': {'regulator-name': ['VDD_IO'], 'regulator-min-microvolt': [[3300000]], 'regulator-max-microvolt': [[3300000]], 'regulator-initial-mode': [[2]], 'regulator-allowed-modes': [[2, 4]], 'regulator-always-on': True, 'phandle': [[37]], 'regulator-state-standby': {'regulator-on-in-suspend': True, 'regulator-mode': [[4]]}, 'regulator-state-mem': {'regulator-off-in-suspend': True, 'regulator-mode': [[4]]}}, 'BUCK2': {'regulator-name': ['VDD_DDR'], 'regulator-min-microvolt': [[1200000]], 'regulator-max-microvolt': [[1200000]], 'regulator-initial-mode': [[2]], 'regulator-allowed-modes': [[2, 4]], 'regulator-always-on': True, 'phandle': [[72]], 'regulator-state-standby': {'regulator-on-in-suspend': True, 'regulator-suspend-microvolt': [[1200000]], 'regulator-changeable-in-suspend': True, 'regulator-mode': [[4]]}, 'regulator-state-mem': {'regulator-on-in-suspend': True, 'regulator-suspend-microvolt': [[1200000]], 'regulator-changeable-in-suspend': True, 'regulator-mode': [[4]]}}, 'BUCK3': {'regulator-name': ['VDD_CORE'], 'regulator-min-microvolt': [[1250000]], 'regulator-max-microvolt': [[1250000]], 'regulator-initial-mode': [[2]], 'regulator-allowed-modes': [[2, 4]], 'regulator-always-on': True, 'phandle': [[73]], 'regulator-state-standby': {'regulator-on-in-suspend': True, 'regulator-mode': [[4]]}, 'regulator-state-mem': {'regulator-off-in-suspend': True, 'regulator-mode': [[4]]}}, 'BUCK4': {'regulator-name': ['VDD_OTHER'], 'regulator-min-microvolt': [[1800000]], 'regulator-max-microvolt': [[1800000]], 'regulator-initial-mode': [[2]], 'regulator-allowed-modes': [[2, 4]], 'regulator-always-on': True, 'phandle': [[74]], 'regulator-state-standby': {'regulator-on-in-suspend': True, 'regulator-suspend-microvolt': [[1800000]], 'regulator-changeable-in-suspend': True, 'regulator-mode': [[4]]}, 'regulator-state-mem': {'regulator-on-in-suspend': True, 'regulator-suspend-microvolt': [[1800000]], 'regulator-changeable-in-suspend': True, 'regulator-mode': [[4]]}}, 'LDO1': {'regulator-name': ['LDO1'], 'regulator-min-microvolt': [[2500000]], 'regulator-max-microvolt': [[2500000]], 'regulator-always-on': True, 'regulator-state-standby': {'regulator-on-in-suspend': True}, 'regulator-state-mem': {'regulator-off-in-suspend': True}}, 'LDO2': {'regulator-name': ['LDO2'], 'regulator-min-microvolt': [[3300000]], 'regulator-max-microvolt': [[3300000]], 'regulator-always-on': True, 'regulator-state-standby': {'regulator-on-in-suspend': True}, 'regulator-state-mem': {'regulator-off-in-suspend': True}}}}}, 'pwm@f802c000': {'compatible': ['atmel,sama5d2-pwm'], 'reg': [[4160929792, 16384]], 'interrupts': [[38, 4, 7]], '#pwm-cells': [[3]], 'clocks': [[3, 2, 38]], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[25, 26]], 'phandle': [[75]]}, 'sfr@f8030000': {'compatible': ['atmel,sama5d2-sfr', 'syscon'], 'reg': [[4160946176, 152]], 'phandle': [[76]]}, 'flexcom@f8034000': {'compatible': ['atmel,sama5d2-flexcom'], 'reg': [[4160962560, 512]], 'clocks': [[3, 2, 19]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': [[0, 4160962560, 2048]], 'status': ['disabled'], 'phandle': [[77]], 'serial@200': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[512, 512]], 'atmel,usart-mode': [[0]], 'interrupts': [[19, 4, 7]], 'clocks': [[3, 2, 19]], 'clock-names': ['usart'], 'dmas': [[19, 184565760], [19, 201342976]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[32]], 'status': ['disabled'], 'phandle': [[78]]}, 'spi@400': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[1024, 512]], 'interrupts': [[19, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 19]], 'clock-names': ['spi_clk'], 'dmas': [[19, 184565760], [19, 201342976]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[79]]}, 'i2c@600': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[1536, 512]], 'interrupts': [[19, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 19]], 'dmas': [[19, 184565760], [19, 201342976]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[80]]}}, 'flexcom@f8038000': {'compatible': ['atmel,sama5d2-flexcom'], 'reg': [[4160978944, 512]], 'clocks': [[3, 2, 20]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': [[0, 4160978944, 2048]], 'status': ['okay'], 'atmel,flexcom-mode': [[1]], 'phandle': [[81]], 'serial@200': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[512, 512]], 'atmel,usart-mode': [[0]], 'interrupts': [[20, 4, 7]], 'clocks': [[3, 2, 20]], 'clock-names': ['usart'], 'dmas': [[19, 218120192], [19, 234897408]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[32]], 'status': ['okay'], 'pinctrl-0': [[27]], 'pinctrl-names': ['default'], 'atmel,use-dma-rx': True, 'atmel,use-dma-tx': True, 'phandle': [[82]]}, 'spi@400': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[1024, 512]], 'interrupts': [[20, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 20]], 'clock-names': ['spi_clk'], 'dmas': [[19, 218120192], [19, 234897408]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[83]]}, 'i2c@600': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[1536, 512]], 'interrupts': [[20, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 20]], 'dmas': [[19, 218120192], [19, 234897408]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[84]]}}, 'sram@f8044000': {'compatible': ['atmel,sama5d2-securam', 'mmio-sram'], 'reg': [[4161028096, 5152]], 'clocks': [[3, 2, 51]], '#address-cells': [[1]], '#size-cells': [[1]], 'no-memory-wc': True, 'ranges': [[0, 4161028096, 5152]], 'phandle': [[85]]}, 'reset-controller@f8048000': {'compatible': ['atmel,sama5d3-rstc'], 'reg': [[4161044480, 16]], 'clocks': [[16]], 'phandle': [[86]]}, 'poweroff@f8048010': {'compatible': ['atmel,sama5d2-shdwc'], 'reg': [[4161044496, 16]], 'clocks': [[16]], '#address-cells': [[1]], '#size-cells': [[0]], 'atmel,wakeup-rtc-timer': True, 'debounce-delay-us': [[976]], 'phandle': [[87]], 'input@0': {'reg': [[0]]}}, 'timer@f8048030': {'compatible': ['atmel,at91sam9260-pit'], 'reg': [[4161044528, 16]], 'interrupts': [[3, 4, 5]], 'clocks': [[3, 0, 4]], 'phandle': [[88]]}, 'watchdog@f8048040': {'compatible': ['atmel,sama5d4-wdt'], 'reg': [[4161044544, 16]], 'interrupts': [[4, 4, 7]], 'clocks': [[16]], 'status': ['okay'], 'phandle': [[89]]}, 'clock-controller@f8048050': {'compatible': ['atmel,sama5d4-sckc'], 'reg': [[4161044560, 4]], 'clocks': [[28]], '#clock-cells': [[0]], 'phandle': [[16]]}, 'rtc@f80480b0': {'compatible': ['atmel,sama5d2-rtc'], 'reg': [[4161044656, 48]], 'interrupts': [[74, 4, 7]], 'clocks': [[16]], 'phandle': [[90]]}, 'i2s@f8050000': {'compatible': ['atmel,sama5d2-i2s'], 'reg': [[4161077248, 256]], 'interrupts': [[54, 4, 7]], 'dmas': [[19, 520110080], [19, 536887296]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 54], [3, 3, 54]], 'clock-names': ['pclk', 'gclk'], 'assigned-clocks': [[3, 0, 5]], 'assigned-clock-parents': [[3, 3, 54]], 'status': ['disabled'], 'phandle': [[91]]}, 'can@f8054000': {'compatible': ['bosch,m_can'], 'reg': [[4161093632, 16384], [2162688, 7168]], 'reg-names': ['m_can', 'message_ram'], 'interrupts': [[56, 4, 7], [64, 4, 7]], 'interrupt-names': ['int0', 'int1'], 'clocks': [[3, 2, 56], [3, 3, 56]], 'clock-names': ['hclk', 'cclk'], 'assigned-clocks': [[3, 3, 56]], 'assigned-clock-parents': [[3, 0, 2]], 'assigned-clock-rates': [[40000000]], 'bosch,mram-cfg': [[0, 0, 0, 64, 0, 0, 32, 32]], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[29]], 'phandle': [[92]]}, 'spi@fc000000': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[4227858432, 256]], 'interrupts': [[34, 4, 7]], 'dmas': [[19, 134234112], [19, 151011328]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 34]], 'clock-names': ['spi_clk'], 'atmel,fifo-size': [[16]], '#address-cells': [[1]], '#size-cells': [[0]], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[30]], 'phandle': [[93]]}, 'serial@fc008000': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[4227891200, 256]], 'atmel,usart-mode': [[0]], 'interrupts': [[27, 4, 7]], 'dmas': [[31, 687882240], [31, 704659456]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 27]], 'clock-names': ['usart'], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[32]], 'atmel,use-dma-rx': True, 'atmel,use-dma-tx': True, 'phandle': [[94]]}, 'serial@fc00c000': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[4227907584, 256]], 'atmel,usart-mode': [[0]], 'dmas': [[19, 721436672], [19, 738213888]], 'dma-names': ['tx', 'rx'], 'interrupts': [[28, 4, 7]], 'clocks': [[3, 2, 28]], 'clock-names': ['usart'], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[33]], 'atmel,use-dma-rx': True, 'atmel,use-dma-tx': True, 'phandle': [[95]]}, 'flexcom@fc010000': {'compatible': ['atmel,sama5d2-flexcom'], 'reg': [[4227923968, 512]], 'clocks': [[3, 2, 21]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': [[0, 4227923968, 2048]], 'status': ['disabled'], 'phandle': [[96]], 'serial@200': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[512, 512]], 'atmel,usart-mode': [[0]], 'interrupts': [[21, 4, 7]], 'clocks': [[3, 2, 21]], 'clock-names': ['usart'], 'dmas': [[19, 251674624], [19, 268451840]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[32]], 'status': ['disabled'], 'phandle': [[97]]}, 'spi@400': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[1024, 512]], 'interrupts': [[21, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 21]], 'clock-names': ['spi_clk'], 'dmas': [[19, 251674624], [19, 268451840]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[98]]}, 'i2c@600': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[1536, 512]], 'interrupts': [[21, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 21]], 'dmas': [[19, 251674624], [19, 268451840]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[99]]}}, 'flexcom@fc014000': {'compatible': ['atmel,sama5d2-flexcom'], 'reg': [[4227940352, 512]], 'clocks': [[3, 2, 22]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': [[0, 4227940352, 2048]], 'status': ['disabled'], 'phandle': [[100]], 'serial@200': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[512, 512]], 'atmel,usart-mode': [[0]], 'interrupts': [[22, 4, 7]], 'clocks': [[3, 2, 22]], 'clock-names': ['usart'], 'dmas': [[19, 285229056], [19, 302006272]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[32]], 'status': ['disabled'], 'phandle': [[101]]}, 'spi@400': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[1024, 512]], 'interrupts': [[22, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 22]], 'clock-names': ['spi_clk'], 'dmas': [[19, 285229056], [19, 302006272]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[102]]}, 'i2c@600': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[1536, 512]], 'interrupts': [[22, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 22]], 'dmas': [[19, 285229056], [19, 302006272]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[103]]}}, 'flexcom@fc018000': {'compatible': ['atmel,sama5d2-flexcom'], 'reg': [[4227956736, 512]], 'clocks': [[3, 2, 23]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': [[0, 4227956736, 2048]], 'status': ['okay'], 'atmel,flexcom-mode': [[2]], 'phandle': [[104]], 'serial@200': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[512, 512]], 'atmel,usart-mode': [[0]], 'interrupts': [[23, 4, 7]], 'clocks': [[3, 2, 23]], 'clock-names': ['usart'], 'dmas': [[19, 318783488], [19, 335560704]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[32]], 'status': ['disabled'], 'phandle': [[105]]}, 'spi@400': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[1024, 512]], 'interrupts': [[23, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 23]], 'clock-names': ['spi_clk'], 'dmas': [[0], [0]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[34]], 'phandle': [[106]]}, 'i2c@600': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[1536, 512]], 'interrupts': [[23, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 23]], 'dmas': [[19, 318783488], [19, 335560704]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[107]]}}, 'trng@fc01c000': {'compatible': ['atmel,at91sam9g45-trng'], 'reg': [[4227973120, 256]], 'interrupts': [[47, 4, 0]], 'clocks': [[3, 2, 47]]}, 'interrupt-controller@fc020000': {'#interrupt-cells': [[3]], 'compatible': ['atmel,sama5d2-aic'], 'interrupt-controller': True, 'reg': [[4227989504, 512]], 'atmel,external-irqs': [[49]], 'phandle': [[1]]}, 'i2c@fc028000': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[4228022272, 256]], 'interrupts': [[30, 4, 7]], 'dmas': [[0], [0]], 'dma-names': ['tx', 'rx'], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 30]], 'atmel,fifo-size': [[16]], 'status': ['okay'], 'pinctrl-names': ['default', 'gpio'], 'pinctrl-0': [[35]], 'pinctrl-1': [[36]], 'i2c-analog-filter': True, 'i2c-digital-filter': True, 'i2c-digital-filter-width-ns': [[35]], 'sda-gpios': [[7, 100, 0]], 'scl-gpios': [[7, 101, 6]], 'phandle': [[108]]}, 'adc@fc030000': {'compatible': ['atmel,sama5d2-adc'], 'reg': [[4228055040, 256]], 'interrupts': [[40, 4, 7]], 'clocks': [[3, 2, 40]], 'clock-names': ['adc_clk'], 'dmas': [[19, 419446784]], 'dma-names': ['rx'], 'atmel,min-sample-rate-hz': [[200000]], 'atmel,max-sample-rate-hz': [[20000000]], 'atmel,startup-time-ms': [[4]], 'atmel,trigger-edge-type': [[1]], '#io-channel-cells': [[1]], 'status': ['okay'], 'vddana-supply': [[37]], 'vref-supply': [[37]], 'pinctrl-names': ['default'], 'pinctrl-0': [[38, 39]], 'phandle': [[6]]}, 'pinctrl@fc038000': {'compatible': ['atmel,sama5d2-pinctrl'], 'reg': [[4228087808, 1536]], 'interrupts': [[18, 4, 7], [68, 4, 7], [69, 4, 7], [70, 4, 7]], 'interrupt-controller': True, '#interrupt-cells': [[2]], 'gpio-controller': True, '#gpio-cells': [[2]], 'clocks': [[3, 2, 18]], 'phandle': [[7]], 'adc-default': {'pinmux': [[121, 122]], 'bias-disable': True, 'phandle': [[38]]}, 'adtrg-default': {'pinmux': [[1114239]], 'bias-pull-up': True, 'phandle': [[39]]}, 'can0-default': {'pinmux': [[2424906, 2424907]], 'bias-disable': True, 'phandle': [[29]]}, 'can1-default': {'pinmux': [[1310810, 1310811]], 'bias-disable': True, 'phandle': [[40]]}, 'debug-uart': {'pinmux': [[1245242, 1245243]], 'bias-disable': True, 'phandle': [[20]]}, 'flx1-default': {'pinmux': [[1114136, 1114135, 1114137, 1114138]], 'bias-disable': True, 'phandle': [[27]]}, 'i2c0-default': {'pinmux': [[1310783, 1310784]], 'bias-disable': True, 'phandle': [[22]]}, 'i2c0-gpio-default': {'pinmux': [[63, 64]], 'bias-disable': True, 'phandle': [[23]]}, 'i2c1-default': {'pinmux': [[2162788, 2162789]], 'bias-disable': True, 'phandle': [[35]]}, 'i2c1-gpio-default': {'pinmux': [[100, 101]], 'bias-disable': True, 'phandle': [[36]]}, 'key-gpio-default': {'pinmux': [[17]], 'bias-pull-up': True, 'phandle': [[41]]}, 'led-gpio-default': {'pinmux': [[7, 8, 9]], 'bias-pull-up': True, 'phandle': [[42]]}, 'mikrobus1-pwm': {'pinmux': [[1310751]], 'bias-disable': True, 'phandle': [[25]]}, 'mikrobus2-pwm': {'pinmux': [[1310752]], 'bias-disable': True, 'phandle': [[26]]}, 'mikrobus1-uart': {'pinmux': [[1114147, 1114148]], 'bias-disable': True, 'phandle': [[33]]}, 'mikrobus2-uart': {'pinmux': [[3342379, 3342380]], 'bias-disable': True, 'phandle': [[32]]}, 'qspi1-default': {'pinmux': [[2359333, 2359334, 2359335, 2359336, 2359337, 2359338]], 'bias-disable': True, 'phandle': [[18]]}, 'rpi-spi': {'pinmux': [[2228332, 2228333, 2228334, 2228335, 2228336]], 'bias-disable': True, 'phandle': [[34]]}, 'rpi-uart': {'pinmux': [[1114210, 1114211]], 'bias-disable': True, 'phandle': [[21]]}, 'sdmmc0-default': {'pinmux': [[1114112, 1114113, 1114114, 1114115, 1114116, 1114117, 1114123, 1114125]], 'bias-disable': True, 'phandle': [[14]]}, 'sdmmc1-default': {'pinmux': [[1376274, 1376275, 1376276, 1376277, 1376278, 1376284, 1376286]], 'bias-disable': True, 'phandle': [[15]]}, 'spi1-default': {'pinmux': [[1310785, 1310786, 1310787, 1310788, 1310789, 1310790, 1310791]], 'bias-disable': True, 'phandle': [[30]]}, 'usb-default': {'pinmux': [[6]], 'bias-disable': True, 'phandle': [[9]]}, 'usba-vbus': {'pinmux': [[45]], 'bias-disable': True, 'phandle': [[8]]}}, 'secumod@fc040000': {'compatible': ['atmel,sama5d2-secumod', 'syscon'], 'reg': [[4228120576, 256]], 'gpio-controller': True, '#gpio-cells': [[2]], 'phandle': [[24]]}, 'crypto@fc044000': {'compatible': ['atmel,at91sam9g46-tdes'], 'reg': [[4228136960, 256]], 'interrupts': [[11, 4, 0]], 'dmas': [[19, 469778432], [19, 486555648]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 11]], 'clock-names': ['tdes_clk'], 'phandle': [[109]]}, 'classd@fc048000': {'compatible': ['atmel,sama5d2-classd'], 'reg': [[4228153344, 256]], 'interrupts': [[59, 4, 7]], 'dmas': [[19, 788545536]], 'dma-names': ['tx'], 'clocks': [[3, 2, 59], [3, 3, 59]], 'clock-names': ['pclk', 'gclk'], 'status': ['disabled'], 'phandle': [[110]]}, 'i2s@fc04c000': {'compatible': ['atmel,sama5d2-i2s'], 'reg': [[4228169728, 256]], 'interrupts': [[55, 4, 7]], 'dmas': [[19, 553664512], [19, 570441728]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 55], [3, 3, 55]], 'clock-names': ['pclk', 'gclk'], 'assigned-clocks': [[3, 0, 6]], 'assigned-clock-parents': [[3, 3, 55]], 'status': ['disabled'], 'phandle': [[111]]}, 'can@fc050000': {'compatible': ['bosch,m_can'], 'reg': [[4228186112, 16384], [2162688, 14336]], 'reg-names': ['m_can', 'message_ram'], 'interrupts': [[57, 4, 7], [65, 4, 7]], 'interrupt-names': ['int0', 'int1'], 'clocks': [[3, 2, 57], [3, 3, 57]], 'clock-names': ['hclk', 'cclk'], 'assigned-clocks': [[3, 3, 57]], 'assigned-clock-parents': [[3, 0, 2]], 'assigned-clock-rates': [[40000000]], 'bosch,mram-cfg': [[7168, 0, 0, 64, 0, 0, 32, 32]], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[40]], 'phandle': [[112]]}, 'sfr@fc05c000': {'compatible': ['atmel,sama5d2-sfrbu', 'syscon'], 'reg': [[4228235264, 32]], 'phandle': [[113]]}, 'chipid@fc069000': {'compatible': ['atmel,sama5d2-chipid'], 'reg': [[4228288512, 8]]}} should not be valid under {'type': 'object'}
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
arch/arm/boot/dts/microchip/at91-sama5d2_icp.dtb: ahb: apb: {'compatible': ['simple-bus'], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': True, 'hlcdc@f0000000': {'compatible': ['atmel,sama5d2-hlcdc'], 'reg': [[4026531840, 8192]], 'interrupts': [[45, 4, 0]], 'clocks': [[3, 2, 45], [3, 1, 3], [15]], 'clock-names': ['periph_clk', 'sys_clk', 'slow_clk'], 'status': ['disabled'], 'phandle': [[58]], 'hlcdc-display-controller': {'compatible': ['atmel,hlcdc-display-controller'], '#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'#address-cells': [[1]], '#size-cells': [[0]], 'reg': [[0]]}}, 'hlcdc-pwm': {'compatible': ['atmel,hlcdc-pwm'], '#pwm-cells': [[3]], 'phandle': [[59]]}}, 'isc@f0008000': {'compatible': ['atmel,sama5d2-isc'], 'reg': [[4026564608, 16384]], 'interrupts': [[46, 4, 5]], 'clocks': [[3, 2, 46], [3, 1, 18], [3, 3, 46]], 'clock-names': ['hclock', 'iscck', 'gck'], '#clock-cells': [[0]], 'clock-output-names': ['isc-mck'], 'status': ['disabled'], 'phandle': [[60]]}, 'ramc@f000c000': {'compatible': ['atmel,sama5d3-ddramc'], 'reg': [[4026580992, 512]], 'clocks': [[3, 1, 2], [3, 2, 13]], 'clock-names': ['ddrck', 'mpddr'], 'phandle': [[61]]}, 'dma-controller@f0010000': {'compatible': ['atmel,sama5d4-dma'], 'reg': [[4026597376, 4096]], 'interrupts': [[6, 4, 0]], '#dma-cells': [[1]], 'clocks': [[3, 2, 6]], 'clock-names': ['dma_clk'], 'phandle': [[18]]}, 'dma-controller@f0004000': {'compatible': ['atmel,sama5d4-dma'], 'reg': [[4026548224, 4096]], 'interrupts': [[7, 4, 0]], '#dma-cells': [[1]], 'clocks': [[3, 2, 7]], 'clock-names': ['dma_clk'], 'phandle': [[34]]}, 'clock-controller@f0014000': {'compatible': ['atmel,sama5d2-pmc', 'syscon'], 'reg': [[4026613760, 352]], 'interrupts': [[74, 4, 7]], '#clock-cells': [[2]], 'clocks': [[15], [16]], 'clock-names': ['slow_clk', 'main_xtal'], 'phandle': [[3]]}, 'spi@f0020000': {'compatible': ['atmel,sama5d2-qspi'], 'reg': [[4026662912, 256], [3489660928, 134217728]], 'reg-names': ['qspi_base', 'qspi_mmap'], 'interrupts': [[52, 4, 7]], 'clocks': [[3, 2, 52]], 'clock-names': ['pclk'], '#address-cells': [[1]], '#size-cells': [[0]], 'status': ['disabled'], 'phandle': [[62]]}, 'spi@f0024000': {'compatible': ['atmel,sama5d2-qspi'], 'reg': [[4026679296, 256], [3623878656, 134217728]], 'reg-names': ['qspi_base', 'qspi_mmap'], 'interrupts': [[53, 4, 7]], 'clocks': [[3, 2, 53]], 'clock-names': ['pclk'], '#address-cells': [[1]], '#size-cells': [[0]], 'status': ['disabled'], 'pinctrl-names': ['default'], 'pinctrl-0': [[17]], 'phandle': [[63]], 'flash@0': {'#address-cells': [[1]], '#size-cells': [[1]], 'compatible': ['jedec,spi-nor'], 'reg': [[0]], 'spi-max-frequency': [[104000000]], 'spi-cs-setup-ns': [[7]], 'spi-tx-bus-width': [[4]], 'spi-rx-bus-width': [[4]], 'm25p,fast-read': True, 'at91bootstrap@0': {'label': ['qspi: at91bootstrap'], 'reg': [[0, 262144]]}, 'bootloader@40000': {'label': ['qspi: bootloader'], 'reg': [[262144, 786432]]}, 'bootloaderenvred@100000': {'label': ['qspi: bootloader env redundant'], 'reg': [[1048576, 262144]]}, 'bootloaderenv@140000': {'label': ['qspi: bootloader env'], 'reg': [[1310720, 262144]]}, 'dtb@180000': {'label': ['qspi: device tree'], 'reg': [[1572864, 524288]]}, 'kernel@200000': {'label': ['qspi: kernel'], 'reg': [[2097152, 6291456]]}}}, 'crypto@f0028000': {'compatible': ['atmel,at91sam9g46-sha'], 'reg': [[4026695680, 256]], 'interrupts': [[12, 4, 0]], 'dmas': [[18, 503332864]], 'dma-names': ['tx'], 'clocks': [[3, 2, 12]], 'clock-names': ['sha_clk'], 'phandle': [[64]]}, 'crypto@f002c000': {'compatible': ['atmel,at91sam9g46-aes'], 'reg': [[4026712064, 256]], 'interrupts': [[9, 4, 0]], 'dmas': [[18, 436224000], [18, 453001216]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 9]], 'clock-names': ['aes_clk'], 'phandle': [[65]]}, 'spi@f8000000': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[4160749568, 256]], 'interrupts': [[33, 4, 7]], 'dmas': [[18, 100679680], [18, 117456896]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 33]], 'clock-names': ['spi_clk'], 'atmel,fifo-size': [[16]], '#address-cells': [[1]], '#size-cells': [[0]], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[19, 20]], 'phandle': [[66]]}, 'ssc@f8004000': {'compatible': ['atmel,at91sam9g45-ssc'], 'reg': [[4160765952, 16384]], 'interrupts': [[43, 4, 4]], 'dmas': [[18, 352337920], [18, 369115136]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 43]], 'clock-names': ['pclk'], 'status': ['disabled'], 'phandle': [[67]]}, 'ethernet@f8008000': {'compatible': ['atmel,sama5d2-gem'], 'reg': [[4160782336, 4096]], 'interrupts': [[5, 4, 3], [66, 4, 3], [67, 4, 3]], 'clocks': [[3, 2, 5], [3, 2, 5]], 'clock-names': ['hclk', 'pclk'], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[21, 22, 23]], 'phy-mode': ['mii'], 'phandle': [[31]], 'fixed-link': {'speed': [[100]], 'full-duplex': True}}, 'timer@f800c000': {'compatible': ['atmel,sama5d2-tcb', 'simple-mfd', 'syscon'], '#address-cells': [[1]], '#size-cells': [[0]], 'reg': [[4160798720, 256]], 'interrupts': [[35, 4, 0]], 'clocks': [[3, 2, 35], [3, 3, 35], [15]], 'clock-names': ['t0_clk', 'gclk', 'slow_clk'], 'phandle': [[68]], 'timer@0': {'compatible': ['atmel,tcb-timer'], 'reg': [[0]], 'phandle': [[69]]}, 'timer@1': {'compatible': ['atmel,tcb-timer'], 'reg': [[1]], 'phandle': [[70]]}}, 'timer@f8010000': {'compatible': ['atmel,sama5d2-tcb', 'simple-mfd', 'syscon'], '#address-cells': [[1]], '#size-cells': [[0]], 'reg': [[4160815104, 256]], 'interrupts': [[36, 4, 0]], 'clocks': [[3, 2, 36], [3, 3, 36], [15]], 'clock-names': ['t0_clk', 'gclk', 'slow_clk'], 'phandle': [[71]]}, 'hsmc@f8014000': {'compatible': ['atmel,sama5d2-smc', 'syscon', 'simple-mfd'], 'reg': [[4160831488, 4096]], 'interrupts': [[17, 4, 6]], 'clocks': [[3, 2, 17]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': True, 'phandle': [[10]], 'ecc-engine@f8014070': {'compatible': ['atmel,sama5d2-pmecc'], 'reg': [[4160831600, 1168], [4160832768, 512]], 'phandle': [[13]]}}, 'pdmic@f8018000': {'compatible': ['atmel,sama5d2-pdmic'], 'reg': [[4160847872, 292]], 'interrupts': [[48, 4, 7]], 'dmas': [[18, 838877184]], 'dma-names': ['rx'], 'clocks': [[3, 2, 48], [3, 3, 48]], 'clock-names': ['pclk', 'gclk'], 'status': ['disabled'], 'phandle': [[72]]}, 'serial@f801c000': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[4160864256, 256]], 'atmel,usart-mode': [[0]], 'interrupts': [[24, 4, 7]], 'dmas': [[18, 587218944], [18, 603996160]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 24]], 'clock-names': ['usart'], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[24]], 'atmel,use-dma-rx': True, 'atmel,use-dma-tx': True, 'phandle': [[73]]}, 'serial@f8020000': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[4160880640, 256]], 'atmel,usart-mode': [[0]], 'interrupts': [[25, 4, 7]], 'dmas': [[18, 620773376], [18, 637550592]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 25]], 'clock-names': ['usart'], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[25]], 'atmel,use-dma-rx': True, 'atmel,use-dma-tx': True, 'phandle': [[74]]}, 'serial@f8024000': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[4160897024, 256]], 'atmel,usart-mode': [[0]], 'interrupts': [[26, 4, 7]], 'dmas': [[18, 654327808], [18, 671105024]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 26]], 'clock-names': ['usart'], 'status': ['disabled'], 'phandle': [[75]]}, 'i2c@f8028000': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[4160913408, 256]], 'interrupts': [[29, 4, 7]], 'dmas': [[18, 16384], [18, 16793600]], 'dma-names': ['tx', 'rx'], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 29]], 'atmel,fifo-size': [[16]], 'status': ['okay'], 'pinctrl-names': ['default', 'gpio'], 'pinctrl-0': [[26]], 'pinctrl-1': [[27]], 'sda-gpios': [[7, 117, 0]], 'scl-gpios': [[7, 118, 6]], 'i2c-digital-filter': True, 'i2c-digital-filter-width-ns': [[35]], 'phandle': [[76]]}, 'pwm@f802c000': {'compatible': ['atmel,sama5d2-pwm'], 'reg': [[4160929792, 16384]], 'interrupts': [[38, 4, 7]], '#pwm-cells': [[3]], 'clocks': [[3, 2, 38]], 'status': ['disabled'], 'pinctrl-names': ['default'], 'pinctrl-0': [[28]], 'phandle': [[77]]}, 'sfr@f8030000': {'compatible': ['atmel,sama5d2-sfr', 'syscon'], 'reg': [[4160946176, 152]], 'phandle': [[78]]}, 'flexcom@f8034000': {'compatible': ['atmel,sama5d2-flexcom'], 'reg': [[4160962560, 512]], 'clocks': [[3, 2, 19]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': [[0, 4160962560, 2048]], 'status': ['okay'], 'atmel,flexcom-mode': [[2]], 'phandle': [[79]], 'serial@200': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[512, 512]], 'atmel,usart-mode': [[0]], 'interrupts': [[19, 4, 7]], 'clocks': [[3, 2, 19]], 'clock-names': ['usart'], 'dmas': [[18, 184565760], [18, 201342976]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[32]], 'status': ['disabled'], 'phandle': [[80]]}, 'spi@400': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[1024, 512]], 'interrupts': [[19, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 19]], 'clock-names': ['spi_clk'], 'dmas': [[0], [0]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['okay'], 'cs-gpios': [[7, 64, 1]], 'pinctrl-names': ['default'], 'pinctrl-0': [[29, 30]], 'phandle': [[81]], 'ksz8563@0': {'compatible': ['microchip,ksz8563'], 'reg': [[0]], 'reset-gpios': [[7, 100, 1]], 'spi-max-frequency': [[500000]], 'spi-cpha': True, 'spi-cpol': True, 'phandle': [[82]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'label': ['lan1']}, 'port@1': {'reg': [[1]], 'label': ['lan2']}, 'port@2': {'reg': [[2]], 'label': ['cpu'], 'ethernet': [[31]], 'phy-mode': ['mii'], 'fixed-link': {'speed': [[100]], 'full-duplex': True}}}}}, 'i2c@600': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[1536, 512]], 'interrupts': [[19, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 19]], 'dmas': [[18, 184565760], [18, 201342976]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[83]]}}, 'flexcom@f8038000': {'compatible': ['atmel,sama5d2-flexcom'], 'reg': [[4160978944, 512]], 'clocks': [[3, 2, 20]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': [[0, 4160978944, 2048]], 'status': ['disabled'], 'phandle': [[84]], 'serial@200': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[512, 512]], 'atmel,usart-mode': [[0]], 'interrupts': [[20, 4, 7]], 'clocks': [[3, 2, 20]], 'clock-names': ['usart'], 'dmas': [[18, 218120192], [18, 234897408]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[32]], 'status': ['disabled'], 'phandle': [[85]]}, 'spi@400': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[1024, 512]], 'interrupts': [[20, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 20]], 'clock-names': ['spi_clk'], 'dmas': [[18, 218120192], [18, 234897408]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[86]]}, 'i2c@600': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[1536, 512]], 'interrupts': [[20, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 20]], 'dmas': [[18, 218120192], [18, 234897408]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[87]]}}, 'sram@f8044000': {'compatible': ['atmel,sama5d2-securam', 'mmio-sram'], 'reg': [[4161028096, 5152]], 'clocks': [[3, 2, 51]], '#address-cells': [[1]], '#size-cells': [[1]], 'no-memory-wc': True, 'ranges': [[0, 4161028096, 5152]], 'phandle': [[88]]}, 'reset-controller@f8048000': {'compatible': ['atmel,sama5d3-rstc'], 'reg': [[4161044480, 16]], 'clocks': [[15]], 'phandle': [[89]]}, 'poweroff@f8048010': {'compatible': ['atmel,sama5d2-shdwc'], 'reg': [[4161044496, 16]], 'clocks': [[15]], '#address-cells': [[1]], '#size-cells': [[0]], 'atmel,wakeup-rtc-timer': True, 'debounce-delay-us': [[976]], 'phandle': [[90]], 'input@0': {'reg': [[0]]}}, 'timer@f8048030': {'compatible': ['atmel,at91sam9260-pit'], 'reg': [[4161044528, 16]], 'interrupts': [[3, 4, 5]], 'clocks': [[3, 0, 4]], 'phandle': [[91]]}, 'watchdog@f8048040': {'compatible': ['atmel,sama5d4-wdt'], 'reg': [[4161044544, 16]], 'interrupts': [[4, 4, 7]], 'clocks': [[15]], 'status': ['okay'], 'phandle': [[92]]}, 'clock-controller@f8048050': {'compatible': ['atmel,sama5d4-sckc'], 'reg': [[4161044560, 4]], 'clocks': [[32]], '#clock-cells': [[0]], 'phandle': [[15]]}, 'rtc@f80480b0': {'compatible': ['atmel,sama5d2-rtc'], 'reg': [[4161044656, 48]], 'interrupts': [[74, 4, 7]], 'clocks': [[15]], 'phandle': [[93]]}, 'i2s@f8050000': {'compatible': ['atmel,sama5d2-i2s'], 'reg': [[4161077248, 256]], 'interrupts': [[54, 4, 7]], 'dmas': [[18, 520110080], [18, 536887296]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 54], [3, 3, 54]], 'clock-names': ['pclk', 'gclk'], 'assigned-clocks': [[3, 0, 5]], 'assigned-clock-parents': [[3, 3, 54]], 'status': ['disabled'], 'phandle': [[94]]}, 'can@f8054000': {'compatible': ['bosch,m_can'], 'reg': [[4161093632, 16384], [2162688, 7168]], 'reg-names': ['m_can', 'message_ram'], 'interrupts': [[56, 4, 7], [64, 4, 7]], 'interrupt-names': ['int0', 'int1'], 'clocks': [[3, 2, 56], [3, 3, 56]], 'clock-names': ['hclk', 'cclk'], 'assigned-clocks': [[3, 3, 56]], 'assigned-clock-parents': [[3, 0, 2]], 'assigned-clock-rates': [[40000000]], 'bosch,mram-cfg': [[0, 0, 0, 64, 0, 0, 32, 32]], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[33]], 'phandle': [[95]]}, 'spi@fc000000': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[4227858432, 256]], 'interrupts': [[34, 4, 7]], 'dmas': [[18, 134234112], [18, 151011328]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 34]], 'clock-names': ['spi_clk'], 'atmel,fifo-size': [[16]], '#address-cells': [[1]], '#size-cells': [[0]], 'status': ['disabled'], 'phandle': [[96]]}, 'serial@fc008000': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[4227891200, 256]], 'atmel,usart-mode': [[0]], 'interrupts': [[27, 4, 7]], 'dmas': [[34, 687882240], [34, 704659456]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 27]], 'clock-names': ['usart'], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[35]], 'atmel,use-dma-rx': True, 'atmel,use-dma-tx': True, 'phandle': [[97]]}, 'serial@fc00c000': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[4227907584, 256]], 'atmel,usart-mode': [[0]], 'dmas': [[18, 721436672], [18, 738213888]], 'dma-names': ['tx', 'rx'], 'interrupts': [[28, 4, 7]], 'clocks': [[3, 2, 28]], 'clock-names': ['usart'], 'status': ['disabled'], 'phandle': [[98]]}, 'flexcom@fc010000': {'compatible': ['atmel,sama5d2-flexcom'], 'reg': [[4227923968, 512]], 'clocks': [[3, 2, 21]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': [[0, 4227923968, 2048]], 'status': ['okay'], 'atmel,flexcom-mode': [[1]], 'phandle': [[99]], 'serial@200': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[512, 512]], 'atmel,usart-mode': [[0]], 'interrupts': [[21, 4, 7]], 'clocks': [[3, 2, 21]], 'clock-names': ['usart'], 'dmas': [[18, 251674624], [18, 268451840]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[32]], 'status': ['okay'], 'pinctrl-0': [[36]], 'pinctrl-names': ['default'], 'atmel,use-dma-rx': True, 'atmel,use-dma-tx': True, 'phandle': [[100]]}, 'spi@400': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[1024, 512]], 'interrupts': [[21, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 21]], 'clock-names': ['spi_clk'], 'dmas': [[18, 251674624], [18, 268451840]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[101]]}, 'i2c@600': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[1536, 512]], 'interrupts': [[21, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 21]], 'dmas': [[18, 251674624], [18, 268451840]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[102]]}}, 'flexcom@fc014000': {'compatible': ['atmel,sama5d2-flexcom'], 'reg': [[4227940352, 512]], 'clocks': [[3, 2, 22]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': [[0, 4227940352, 2048]], 'status': ['okay'], 'atmel,flexcom-mode': [[2]], 'phandle': [[103]], 'serial@200': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[512, 512]], 'atmel,usart-mode': [[0]], 'interrupts': [[22, 4, 7]], 'clocks': [[3, 2, 22]], 'clock-names': ['usart'], 'dmas': [[18, 285229056], [18, 302006272]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[32]], 'status': ['disabled'], 'phandle': [[104]]}, 'spi@400': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[1024, 512]], 'interrupts': [[22, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 22]], 'clock-names': ['spi_clk'], 'dmas': [[0], [0]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[37, 38]], 'phandle': [[105]]}, 'i2c@600': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[1536, 512]], 'interrupts': [[22, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 22]], 'dmas': [[18, 285229056], [18, 302006272]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[106]]}}, 'flexcom@fc018000': {'compatible': ['atmel,sama5d2-flexcom'], 'reg': [[4227956736, 512]], 'clocks': [[3, 2, 23]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': [[0, 4227956736, 2048]], 'status': ['okay'], 'atmel,flexcom-mode': [[3]], 'phandle': [[107]], 'serial@200': {'compatible': ['atmel,at91sam9260-usart'], 'reg': [[512, 512]], 'atmel,usart-mode': [[0]], 'interrupts': [[23, 4, 7]], 'clocks': [[3, 2, 23]], 'clock-names': ['usart'], 'dmas': [[18, 318783488], [18, 335560704]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[32]], 'status': ['disabled'], 'phandle': [[108]]}, 'spi@400': {'compatible': ['atmel,at91rm9200-spi'], 'reg': [[1024, 512]], 'interrupts': [[23, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 23]], 'clock-names': ['spi_clk'], 'dmas': [[18, 318783488], [18, 335560704]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['disabled'], 'phandle': [[109]]}, 'i2c@600': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[1536, 512]], 'interrupts': [[23, 4, 7]], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 23]], 'dmas': [[0], [0]], 'dma-names': ['tx', 'rx'], 'atmel,fifo-size': [[16]], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[39]], 'i2c-digital-filter': True, 'i2c-digital-filter-width-ns': [[35]], 'phandle': [[110]], 'mcp16502@5b': {'compatible': ['microchip,mcp16502'], 'reg': [[91]], 'status': ['okay'], 'lpm-gpios': [[40, 7, 1]], 'regulators': {'BUCK1': {'regulator-name': ['VDD_IO'], 'regulator-min-microvolt': [[3300000]], 'regulator-max-microvolt': [[3300000]], 'regulator-initial-mode': [[2]], 'regulator-allowed-modes': [[2, 4]], 'regulator-always-on': True, 'phandle': [[43]], 'regulator-state-standby': {'regulator-on-in-suspend': True, 'regulator-mode': [[4]]}, 'regulator-state-mem': {'regulator-off-in-suspend': True, 'regulator-mode': [[4]]}}, 'BUCK2': {'regulator-name': ['VDD_DDR'], 'regulator-min-microvolt': [[1350000]], 'regulator-max-microvolt': [[1350000]], 'regulator-initial-mode': [[2]], 'regulator-allowed-modes': [[2, 4]], 'regulator-always-on': True, 'regulator-state-standby': {'regulator-on-in-suspend': True, 'regulator-mode': [[4]]}, 'regulator-state-mem': {'regulator-on-in-suspend': True, 'regulator-mode': [[4]]}}, 'BUCK3': {'regulator-name': ['VDD_CORE'], 'regulator-min-microvolt': [[1250000]], 'regulator-max-microvolt': [[1250000]], 'regulator-initial-mode': [[2]], 'regulator-allowed-modes': [[2, 4]], 'regulator-always-on': True, 'regulator-state-standby': {'regulator-on-in-suspend': True, 'regulator-mode': [[4]]}, 'regulator-state-mem': {'regulator-off-in-suspend': True, 'regulator-mode': [[4]]}}, 'BUCK4': {'regulator-name': ['VDD_OTHER'], 'regulator-min-microvolt': [[600000]], 'regulator-max-microvolt': [[1850000]], 'regulator-initial-mode': [[2]], 'regulator-allowed-modes': [[2, 4]], 'regulator-state-standby': {'regulator-on-in-suspend': True, 'regulator-mode': [[4]]}, 'regulator-state-mem': {'regulator-off-in-suspend': True, 'regulator-mode': [[4]]}}, 'LDO1': {'regulator-name': ['LDO1'], 'regulator-min-microvolt': [[2500000]], 'regulator-max-microvolt': [[2500000]], 'regulator-always-on': True, 'regulator-state-standby': {'regulator-on-in-suspend': True}, 'regulator-state-mem': {'regulator-off-in-suspend': True}}, 'LDO2': {'regulator-name': ['LDO2'], 'regulator-min-microvolt': [[3300000]], 'regulator-max-microvolt': [[3300000]], 'regulator-always-on': True, 'regulator-state-standby': {'regulator-on-in-suspend': True}, 'regulator-state-mem': {'regulator-off-in-suspend': True}}}}}}, 'trng@fc01c000': {'compatible': ['atmel,at91sam9g45-trng'], 'reg': [[4227973120, 256]], 'interrupts': [[47, 4, 0]], 'clocks': [[3, 2, 47]]}, 'interrupt-controller@fc020000': {'#interrupt-cells': [[3]], 'compatible': ['atmel,sama5d2-aic'], 'interrupt-controller': True, 'reg': [[4227989504, 512]], 'atmel,external-irqs': [[49]], 'phandle': [[1]]}, 'i2c@fc028000': {'compatible': ['atmel,sama5d2-i2c'], 'reg': [[4228022272, 256]], 'interrupts': [[30, 4, 7]], 'dmas': [[0], [0]], 'dma-names': ['tx', 'rx'], '#address-cells': [[1]], '#size-cells': [[0]], 'clocks': [[3, 2, 30]], 'atmel,fifo-size': [[16]], 'status': ['okay'], 'pinctrl-names': ['default', 'gpio'], 'pinctrl-0': [[41]], 'pinctrl-1': [[42]], 'sda-gpios': [[7, 115, 0]], 'scl-gpios': [[7, 116, 6]], 'i2c-digital-filter': True, 'i2c-digital-filter-width-ns': [[35]], 'phandle': [[111]], 'eeprom@50': {'compatible': ['atmel,24c02'], 'reg': [[80]], 'pagesize': [[16]], 'status': ['okay']}, 'eeprom@52': {'compatible': ['atmel,24c02'], 'reg': [[82]], 'pagesize': [[16]], 'status': ['disabled']}, 'eeprom@53': {'compatible': ['atmel,24c02'], 'reg': [[83]], 'pagesize': [[16]], 'status': ['disabled']}}, 'adc@fc030000': {'compatible': ['atmel,sama5d2-adc'], 'reg': [[4228055040, 256]], 'interrupts': [[40, 4, 7]], 'clocks': [[3, 2, 40]], 'clock-names': ['adc_clk'], 'dmas': [[18, 419446784]], 'dma-names': ['rx'], 'atmel,min-sample-rate-hz': [[200000]], 'atmel,max-sample-rate-hz': [[20000000]], 'atmel,startup-time-ms': [[4]], 'atmel,trigger-edge-type': [[1]], '#io-channel-cells': [[1]], 'status': ['okay'], 'vddana-supply': [[43]], 'vref-supply': [[43]], 'pinctrl-names': ['default'], 'pinctrl-0': [[44, 45]], 'phandle': [[6]]}, 'pinctrl@fc038000': {'compatible': ['atmel,sama5d2-pinctrl'], 'reg': [[4228087808, 1536]], 'interrupts': [[18, 4, 7], [68, 4, 7], [69, 4, 7], [70, 4, 7]], 'interrupt-controller': True, '#interrupt-cells': [[2]], 'gpio-controller': True, '#gpio-cells': [[2]], 'clocks': [[3, 2, 18]], 'phandle': [[7]], 'adc_default': {'pinmux': [[120, 121, 122]], 'bias-disable': True, 'phandle': [[44]]}, 'adtrg_default': {'pinmux': [[1114239]], 'bias-pull-up': True, 'phandle': [[45]]}, 'flx4_default': {'pinmux': [[1179740, 1179741]], 'bias-disable': True, 'phandle': [[39]]}, 'can0_default': {'pinmux': [[2424906, 2424907]], 'bias-disable': True, 'phandle': [[33]]}, 'can1_default': {'pinmux': [[1310810, 1310811]], 'bias-disable': True, 'phandle': [[46]]}, 'i2c1_default': {'pinmux': [[3276915, 3276916]], 'bias-disable': True, 'phandle': [[41]]}, 'i2c1_gpio': {'pinmux': [[115, 116]], 'bias-disable': True, 'phandle': [[42]]}, 'key_gpio_default': {'pinmux': [[96]], 'bias-pull-up': True, 'phandle': [[47]]}, 'led_gpio_default': {'pinmux': [[32, 33, 31]], 'bias-pull-up': True, 'phandle': [[48]]}, 'qspi1_default': {'pinmux': [[1179654, 1179655, 1179656, 1179657, 1179658, 1179659]], 'bias-disable': True, 'phandle': [[17]]}, 'sdmmc0_default': {'phandle': [[14]], 'cmd_data': {'pinmux': [[1114113, 1114114, 1114115, 1114116, 1114117]], 'bias-disable': True}, 'ck_cd': {'pinmux': [[1114112, 1114125]], 'bias-disable': True}}, 'sdmmc1_default': {'phandle': [[112]], 'cmd_data': {'pinmux': [[1376274, 1376275, 1376276, 1376277]], 'bias-disable': True}, 'ck_cd': {'pinmux': [[1376278, 1376284]], 'bias-disable': True}}, 'mikrobus_i2c': {'pinmux': [[4325494, 4325493]], 'bias-disable': True, 'phandle': [[26]]}, 'i2c0_gpio': {'pinmux': [[117, 118]], 'bias-disable': True, 'phandle': [[27]]}, 'mikrobus1_an': {'pinmux': [[122]], 'bias-disable': True, 'phandle': [[113]]}, 'mikrobus1_rst': {'pinmux': [[69]], 'bias-disable': True, 'phandle': [[114]]}, 'mikrobus1_spi_cs': {'pinmux': [[2424917]], 'bias-disable': True, 'phandle': [[38]]}, 'mikrobus1_spi': {'pinmux': [[2424916, 2424915, 2424914]], 'bias-disable': True, 'phandle': [[37]]}, 'mikrobus1_pwm': {'pinmux': [[1245252]], 'bias-disable': True, 'phandle': [[115]]}, 'mikrobus1_int': {'pinmux': [[67]], 'bias-disable': True, 'phandle': [[116]]}, 'mikrobus1_uart': {'pinmux': [[1245242, 1245243]], 'bias-disable': True, 'phandle': [[24]]}, 'mikrobus2_an': {'pinmux': [[121]], 'bias-disable': True, 'phandle': [[117]]}, 'mikrobus2_rst': {'pinmux': [[56]], 'bias-disable': True, 'phandle': [[118]]}, 'mikrobus2_spi_cs': {'pinmux': [[1245247]], 'bias-disable': True, 'phandle': [[119]]}, 'mikrobus2_spi': {'pinmux': [[1245244, 1245245, 1245246]], 'bias-disable': True, 'phandle': [[29]]}, 'ksz_spi_cs': {'pinmux': [[64]], 'bias-disable': True, 'phandle': [[30]]}, 'mikrobus2_pwm': {'pinmux': [[2359351]], 'bias-disable': True, 'phandle': [[120]]}, 'mikrobus2_int': {'pinmux': [[54]], 'bias-disable': True, 'phandle': [[121]]}, 'mikrobus2_uart': {'pinmux': [[1310796, 1310797]], 'bias-disable': True, 'phandle': [[35]]}, 'mikrobus3_an': {'pinmux': [[120]], 'bias-disable': True, 'phandle': [[122]]}, 'mikrobus3_rst': {'pinmux': [[53]], 'bias-disable': True, 'phandle': [[123]]}, 'mikrobus3_spi_cs': {'pinmux': [[1114129]], 'bias-disable': True, 'phandle': [[20]]}, 'mikrobus3_spi': {'pinmux': [[1114126, 1114128, 1114127]], 'bias-disable': True, 'phandle': [[19]]}, 'mikrobus3_pwm': {'pinmux': [[2359348]], 'bias-disable': True, 'phandle': [[124]]}, 'mikrobus3_int': {'pinmux': [[50]], 'bias-disable': True, 'phandle': [[125]]}, 'mikrobus3_uart': {'pinmux': [[2424903, 2424904]], 'bias-disable': True, 'phandle': [[25]]}, 'usb_default': {'pinmux': [[81]], 'bias-disable': True, 'phandle': [[9]]}, 'usba_vbus': {'pinmux': [[119]], 'bias-disable': True, 'phandle': [[8]]}, 'pwm0_pwm2_default': {'pinmux': [[1245221, 1245222]], 'bias-pull-up': True, 'phandle': [[28]]}, 'macb0_default': {'pinmux': [[2359393, 2359394, 2359397, 2359398, 2359399, 2359400, 2359401, 2359402, 2359403, 2359404, 2359405, 2359406, 2359407, 2359408, 2359409, 2359410]], 'bias-disable': True, 'phandle': [[21]]}, 'macb0_phy_irq': {'pinmux': [[99]], 'bias-disable': True, 'phandle': [[22]]}, 'macb0_sw_rst': {'pinmux': [[100]], 'bias-disable': True, 'phandle': [[23]]}, 'flx2_default': {'pinmux': [[1376262, 1376263, 1376265, 1376266]], 'bias-disable': True, 'phandle': [[36]]}}, 'secumod@fc040000': {'compatible': ['atmel,sama5d2-secumod', 'syscon'], 'reg': [[4228120576, 256]], 'gpio-controller': True, '#gpio-cells': [[2]], 'phandle': [[40]]}, 'crypto@fc044000': {'compatible': ['atmel,at91sam9g46-tdes'], 'reg': [[4228136960, 256]], 'interrupts': [[11, 4, 0]], 'dmas': [[18, 469778432], [18, 486555648]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 11]], 'clock-names': ['tdes_clk'], 'phandle': [[126]]}, 'classd@fc048000': {'compatible': ['atmel,sama5d2-classd'], 'reg': [[4228153344, 256]], 'interrupts': [[59, 4, 7]], 'dmas': [[18, 788545536]], 'dma-names': ['tx'], 'clocks': [[3, 2, 59], [3, 3, 59]], 'clock-names': ['pclk', 'gclk'], 'status': ['disabled'], 'phandle': [[127]]}, 'i2s@fc04c000': {'compatible': ['atmel,sama5d2-i2s'], 'reg': [[4228169728, 256]], 'interrupts': [[55, 4, 7]], 'dmas': [[18, 553664512], [18, 570441728]], 'dma-names': ['tx', 'rx'], 'clocks': [[3, 2, 55], [3, 3, 55]], 'clock-names': ['pclk', 'gclk'], 'assigned-clocks': [[3, 0, 6]], 'assigned-clock-parents': [[3, 3, 55]], 'status': ['disabled'], 'phandle': [[128]]}, 'can@fc050000': {'compatible': ['bosch,m_can'], 'reg': [[4228186112, 16384], [2162688, 14336]], 'reg-names': ['m_can', 'message_ram'], 'interrupts': [[57, 4, 7], [65, 4, 7]], 'interrupt-names': ['int0', 'int1'], 'clocks': [[3, 2, 57], [3, 3, 57]], 'clock-names': ['hclk', 'cclk'], 'assigned-clocks': [[3, 3, 57]], 'assigned-clock-parents': [[3, 0, 2]], 'assigned-clock-rates': [[40000000]], 'bosch,mram-cfg': [[7168, 0, 0, 64, 0, 0, 32, 32]], 'status': ['okay'], 'pinctrl-names': ['default'], 'pinctrl-0': [[46]], 'phandle': [[129]]}, 'sfr@fc05c000': {'compatible': ['atmel,sama5d2-sfrbu', 'syscon'], 'reg': [[4228235264, 32]], 'phandle': [[130]]}, 'chipid@fc069000': {'compatible': ['atmel,sama5d2-chipid'], 'reg': [[4228288512, 8]]}} should not be valid under {'type': 'object'}
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: mcp16502@5b: regulators:BUCK3:regulator-state-standby: 'regulator-suspend-voltage' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/regulator/microchip,mcp16502.yaml#
arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: mcp16502@5b: regulators:BUCK4:regulator-state-standby: 'regulator-suspend-voltage' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/regulator/microchip,mcp16502.yaml#
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: pmic@5b: regulators:BUCK3:regulator-state-standby: 'regulator-suspend-voltage' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/regulator/microchip,mcp16502.yaml#
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: pmic@5b: regulators:BUCK4:regulator-state-standby: 'regulator-suspend-voltage' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/regulator/microchip,mcp16502.yaml#
^ permalink raw reply
* Re: [PATCH 2/2] dt-bindings: qcom: Document samsung,fortuna
From: Rob Herring @ 2024-03-27 15:43 UTC (permalink / raw)
To: Raymond Hackley
Cc: linux-kernel, Bjorn Andersson, Konrad Dybcio, Krzysztof Kozlowski,
Conor Dooley, Stephan Gerhold, Nikita Travkin, linux-arm-msm,
devicetree, ~postmarketos/upstreaming
In-Reply-To: <20240326141222.200452-3-raymondhackley@protonmail.com>
On Tue, Mar 26, 2024 at 02:12:58PM +0000, Raymond Hackley wrote:
> Document common binding samsung,fortuna used by the following
> Samsung Galaxy Grand Prime devices below:
> - SM-G530FZ (msm8916-samsung-grandprimelte)
> - SM-G530H (msm8216-samsung-fortuna3g)
> - SM-G530W (msm8916-gprimeltecan)
Commit messages should answer "why?". Why do you need this?
Please test this binding change against your dts changes. I think you
will find it fails.
>
> Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 66beaac60e1d..2db776d78d22 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -204,6 +204,7 @@ properties:
> - samsung,a5u-eur
> - samsung,e5
> - samsung,e7
> + - samsung,fortuna
> - samsung,fortuna3g
> - samsung,gprimeltecan
> - samsung,grandmax
> --
> 2.39.2
>
>
^ permalink raw reply
* Re: [PATCH v4 4/4] drivers: watchdog: ast2500 and ast2600 support bootstatus
From: Guenter Roeck @ 2024-03-27 15:47 UTC (permalink / raw)
To: Peter Yin, patrick, Wim Van Sebroeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240327085330.3281697-5-peteryin.openbmc@gmail.com>
On 3/27/24 01:53, Peter Yin wrote:
> Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2600
>
> Regarding the AST2600 specification, the WDTn Timeout Status Register
> (WDT10) has bit 1 reserved. Bit 1 of the status register indicates
> on ast2500 if the boot was from the second boot source.
> It does not indicate that the most recent reset was triggered by
> the watchdog. The code should just be changed to set WDIOF_CARDRESET
> if bit 0 of the status register is set.
>
> Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or
> ast2500 SCU3C when bit1 is set.
>
> Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
> ---
> drivers/watchdog/aspeed_wdt.c | 60 +++++++++++++++++++++++++----------
> 1 file changed, 44 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
> index b4773a6aaf8c..29e9afdee619 100644
> --- a/drivers/watchdog/aspeed_wdt.c
> +++ b/drivers/watchdog/aspeed_wdt.c
> @@ -11,10 +11,12 @@
> #include <linux/io.h>
> #include <linux/kernel.h>
> #include <linux/kstrtox.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
> +#include <linux/regmap.h>
> #include <linux/watchdog.h>
>
> static bool nowayout = WATCHDOG_NOWAYOUT;
> @@ -65,23 +67,32 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
> #define WDT_RELOAD_VALUE 0x04
> #define WDT_RESTART 0x08
> #define WDT_CTRL 0x0C
> -#define WDT_CTRL_BOOT_SECONDARY BIT(7)
> -#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
> -#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
> -#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
> -#define WDT_CTRL_1MHZ_CLK BIT(4)
> -#define WDT_CTRL_WDT_EXT BIT(3)
> -#define WDT_CTRL_WDT_INTR BIT(2)
> -#define WDT_CTRL_RESET_SYSTEM BIT(1)
> -#define WDT_CTRL_ENABLE BIT(0)
> +#define WDT_CTRL_BOOT_SECONDARY BIT(7)
> +#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
> +#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
> +#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
> +#define WDT_CTRL_1MHZ_CLK BIT(4)
> +#define WDT_CTRL_WDT_EXT BIT(3)
> +#define WDT_CTRL_WDT_INTR BIT(2)
> +#define WDT_CTRL_RESET_SYSTEM BIT(1)
> +#define WDT_CTRL_ENABLE BIT(0)
> #define WDT_TIMEOUT_STATUS 0x10
> -#define WDT_TIMEOUT_STATUS_IRQ BIT(2)
> -#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
> +#define WDT_TIMEOUT_STATUS_IRQ BIT(2)
> +#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
> +#define WDT_TIMEOUT_STATUS_EVENT BIT(0)
> #define WDT_CLEAR_TIMEOUT_STATUS 0x14
> -#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
> +#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
> #define WDT_RESET_MASK1 0x1c
> #define WDT_RESET_MASK2 0x20
>
The above bit value defines were indented to show what is
registers and what is register bit values. Why are you
changing that other than for personal preference ?
Guenter
^ permalink raw reply
* Re: [PATCH v4 4/4] drivers: watchdog: ast2500 and ast2600 support bootstatus
From: Chia Hsing Yin @ 2024-03-27 16:07 UTC (permalink / raw)
To: Guenter Roeck
Cc: patrick, Wim Van Sebroeck, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery, linux-watchdog,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
In-Reply-To: <f0b03c0b-eb54-420e-a4f7-8286e20b9df6@roeck-us.net>
On Wed, Mar 27, 2024 at 11:47 PM Guenter Roeck <linux@roeck-us.net> wrote:
>
> On 3/27/24 01:53, Peter Yin wrote:
> > Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2600
> >
> > Regarding the AST2600 specification, the WDTn Timeout Status Register
> > (WDT10) has bit 1 reserved. Bit 1 of the status register indicates
> > on ast2500 if the boot was from the second boot source.
> > It does not indicate that the most recent reset was triggered by
> > the watchdog. The code should just be changed to set WDIOF_CARDRESET
> > if bit 0 of the status register is set.
> >
> > Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or
> > ast2500 SCU3C when bit1 is set.
> >
> > Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
> > ---
> > drivers/watchdog/aspeed_wdt.c | 60 +++++++++++++++++++++++++----------
> > 1 file changed, 44 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
> > index b4773a6aaf8c..29e9afdee619 100644
> > --- a/drivers/watchdog/aspeed_wdt.c
> > +++ b/drivers/watchdog/aspeed_wdt.c
> > @@ -11,10 +11,12 @@
> > #include <linux/io.h>
> > #include <linux/kernel.h>
> > #include <linux/kstrtox.h>
> > +#include <linux/mfd/syscon.h>
> > #include <linux/module.h>
> > #include <linux/of.h>
> > #include <linux/of_irq.h>
> > #include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > #include <linux/watchdog.h>
> >
> > static bool nowayout = WATCHDOG_NOWAYOUT;
> > @@ -65,23 +67,32 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
> > #define WDT_RELOAD_VALUE 0x04
> > #define WDT_RESTART 0x08
> > #define WDT_CTRL 0x0C
> > -#define WDT_CTRL_BOOT_SECONDARY BIT(7)
> > -#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
> > -#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
> > -#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
> > -#define WDT_CTRL_1MHZ_CLK BIT(4)
> > -#define WDT_CTRL_WDT_EXT BIT(3)
> > -#define WDT_CTRL_WDT_INTR BIT(2)
> > -#define WDT_CTRL_RESET_SYSTEM BIT(1)
> > -#define WDT_CTRL_ENABLE BIT(0)
> > +#define WDT_CTRL_BOOT_SECONDARY BIT(7)
> > +#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
> > +#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
> > +#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
> > +#define WDT_CTRL_1MHZ_CLK BIT(4)
> > +#define WDT_CTRL_WDT_EXT BIT(3)
> > +#define WDT_CTRL_WDT_INTR BIT(2)
> > +#define WDT_CTRL_RESET_SYSTEM BIT(1)
> > +#define WDT_CTRL_ENABLE BIT(0)
> > #define WDT_TIMEOUT_STATUS 0x10
> > -#define WDT_TIMEOUT_STATUS_IRQ BIT(2)
> > -#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
> > +#define WDT_TIMEOUT_STATUS_IRQ BIT(2)
> > +#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
> > +#define WDT_TIMEOUT_STATUS_EVENT BIT(0)
> > #define WDT_CLEAR_TIMEOUT_STATUS 0x14
> > -#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
> > +#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
> > #define WDT_RESET_MASK1 0x1c
> > #define WDT_RESET_MASK2 0x20
> >
>
> The above bit value defines were indented to show what is
> registers and what is register bit values. Why are you
> changing that other than for personal preference ?
>
> Guenter
>
Oh! I'm sorry, I didn't realize this was a rule. I thought it was just
an alignment issue. I will revert it in the next version. Thank you
for explaining.
^ permalink raw reply
* Re: [PATCH 4/4] drm/bridge: hotplug-bridge: add driver to support hot-pluggable DSI bridges
From: Luca Ceresoli @ 2024-03-27 16:08 UTC (permalink / raw)
To: Maxime Ripard
Cc: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, David Airlie, Daniel Vetter,
Maarten Lankhorst, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Kocialkowski,
Hervé Codina, Thomas Petazzoni, dri-devel, devicetree,
linux-kernel, Paul Kocialkowski
In-Reply-To: <20240327-radiant-cherry-myna-25afc4@houat>
Hi Maxime,
On Wed, 27 Mar 2024 13:42:40 +0100
Maxime Ripard <mripard@kernel.org> wrote:
> On Tue, Mar 26, 2024 at 05:28:14PM +0100, Luca Ceresoli wrote:
> > This driver implements the point of a DRM pipeline where a connector allows
> > removal of all the following bridges up to the panel.
> >
> > The DRM subsystem currently allows hotplug of the monitor but not preceding
> > components. However there are embedded devices where the "tail" of the DRM
> > pipeline, including one or more bridges, can be physically removed:
> >
> > .------------------------.
> > | DISPLAY CONTROLLER |
> > | .---------. .------. |
> > | | ENCODER |<--| CRTC | |
> > | '---------' '------' |
> > '------|-----------------'
> > |
> > | HOTPLUG
> > V CONNECTOR
> > .---------. .--. .-. .---------. .-------.
> > | 0 to N | | _| _| | | 1 to N | | |
> > | BRIDGES |--DSI-->||_ |_ |--DSI-->| BRIDGES |--LVDS-->| PANEL |
> > | | | | | | | | | |
> > '---------' '--' '-' '---------' '-------'
> >
> > [--- fixed components --] [----------- removable add-on -----------]
> >
> > This driver supports such devices, where the final segment of a MIPI DSI
> > bus, including one or more bridges, can be physically disconnected and
> > reconnected at runtime, possibly with a different model.
> >
> > This implementation supports a MIPI DSI bus only, but it is designed to be
> > as far as possible generic and extendable to other busses that have no
> > native hotplug and model ID discovery.
> >
> > This driver does not provide facilities to add and remove the hot-pluggable
> > components from the kernel: this needs to be done by other means
> > (e.g. device tree overlay runtime insertion and removal). The
> > hotplug-bridge gets notified of hot-plugging by the DRM bridge notifier
> > callbacks after they get added or before they get removed.
> >
> > The hotplug-bridge role is to implement the "hot-pluggable connector" in
> > the bridge chain. In this position, what the hotplug-bridge should ideally
> > do is:
> >
> > * communicate with the previous component (bridge or encoder) so that it
> > believes it always has a connected bridge following it and the DRM card
> > is always present
> > * be notified of the addition and removal of the following bridge and
> > attach/detach to/from it
> > * communicate with the following bridge so that it will attach and detach
> > using the normal procedure (as if the entire pipeline were being created
> > or destroyed, not only the tail)
> > * expose the "add-on connected/disconnected" status via the DRM connector
> > connected/disconnected status, so that users of the DRM pipeline know
> > when they can render output on the display
> >
> > However some aspects make it a bit more complex than that. Most notably:
> >
> > * the next bridge can be probed and removed at any moment and all probing
> > sequences need to be handled
> > * the DSI host/device registration process, which adds to the DRM bridge
> > attach process, makes the initial card registration tricky
> > * the need to register and deregister the following bridges at runtime
> > without tearing down the whole DRM card prevents using the functions
> > that are normally recommended
> > * the automatic mechanism to call the appropriate .get_modes operation
> > (typically provided by the panel bridge) cannot work as the panel can
> > disappear and reappear as a different model, so an ad-hoc lookup is
> > needed
>
> There's several additional hurdles there:
>
> - You mentioned the connector in your ideal scenario. But as soon as
> you remove the last bridge, the connector will probably go away too.
> There's two scenarii here then:
>
> - The driver is ok, and it will stay there until the last user its to
> the main DRM device. Which means that if you create a new one,
> you'll have the old one and the new one together, but you can't
> tell which one you're supposed to use.
>
> - If the driver isn't ok, the connector will be freed immediately.
> There's plenty of lingering pointers in the framework, and
> especially the states though, leading to use-after-free errors.
>
> - So far, we told everyone that the graphics pipeline wasn't going to
> change. How do you expect applications to deal with a connector going
> away without any regression? I guess the natural thing here would be
> to emit a uevent just like we do when the connection status change,
> but the thing is: we're doing that for the connector, and the
> connector is gone.
Thanks for your feedback. I probably should have discussed this aspect
in my cover letter, sorry about that, let me amend now.
I think there are two possible approaches.
The first approach is based on removing the drm_connector. My laptop
uses the i915 driver, and I have observed that attaching/removing a
USB-C dock with an HDMI connector connected to a monitor, a new
drm_connector appears/disappears for the card. User space gets notified
and the external monitor is enabled/disabled, just the way a desktop
user would expect, so this is possible. I had a look at the driver but
how this magic happens was not clear to me honestly.
The second approach is simpler and based on keeping the drm_connector
always instantiated, and it is what this driver does. The drm_connector
is added by the hotplug-bridge driver in the drm_bridge_funcs.attach op,
which happens initially, and only removed by drm_bridge_funcs.detach,
so it is never removed when detaching the _following_ part of the
pipeline (which the card is unaware of). So the encoder always has a
drm_connector.
Note when attaching to the downstream bridge we pass the
DRM_BRIDGE_ATTACH_NO_CONNECTOR flag, which _should_ prevent creation of a
second connector. I'd expect some drivers to not honour that flag, but
they can be fixed if needed.
When the tail of the pipeline is connected/removed, the
hpb->next_bridge pointer becomes valid/NULL. And
hotplug_bridge_detect() looks at exactly that pointer to return a
connected or disconnected status.
The result is that when the add-on is connected, 'modetest -c' shows:
Connectors:
id encoder status name size (mm) modes encoders
37 0 connected DSI-1 293x165 1 36
modes:
index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
#0 1920x1080 60.00 1920 1978 2020 2108 1080 1088 1102 1116 141140 flags: ; type: preferred, driver
props:
...
and when it is disconnected, it shows:
Connectors:
id encoder status name size (mm) modes encoders
37 0 disconnected DSI-1 0x0 0 36
props:
...
weston detects the HPD events from the connector and starts/stops using
the removable display correctly.
Does this clarify the approach?
I could be missing some aspects of course, especially in case of more
complex hardware setups than the one I have. However the code in this
series has been tested for a long time and no memory-safety issue has
appeared.
> Between the userspace expectations and the memory-safety issue plaguing
> way too many drivers, I'm not sure this approach can work.
>
> I guess one way to somewhat achieve what you're trying to do would be to
> introduce the connection status at the bridge level, reflect the
> aggregate connection status of all bridges on the connector, and make
> each bridge driver probe its device in the connect hook through DCS or
> I2C.
I think you mean: keeping all the bridge drivers instantiated, even
when the physical chip is removed.
This is of course another possible approach. However it would be more
invasive, forcing bridge drivers to change their current behaviour. And
it would violate the design that a driver is probed when a device is
there, and removed when the hardware goes away.
The approach I took firstly allows to have zero modifications to
existing bridge drivers -- not necessarily the right thing to do, but I
didn't find any good reason to require that.
Additionally, it is designed to allow removing an add-on having bridge
XYZ and then plugging in another add-on with bridge ABC, having a
different driver. Keeping alive the XYZ driver on unplug would not make
sense in such a case. This is not a tested scenario as I have no
hardware allowing that, but it is part of the design goals and I see no
obvious reason it wouldn't work with this patch as is, since the
downstream bridge driver is removed on disconnect and probed on connect
for whatever bridge will be connected.
Best regards,
Luca
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: display: bridge: add the Hot-plug MIPI DSI connector
From: Rob Herring @ 2024-03-27 16:09 UTC (permalink / raw)
To: Luca Ceresoli
Cc: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, David Airlie, Daniel Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Krzysztof Kozlowski, Conor Dooley, Paul Kocialkowski,
Hervé Codina, Thomas Petazzoni, dri-devel, devicetree,
linux-kernel, Paul Kocialkowski
In-Reply-To: <20240326-hotplug-drm-bridge-v1-1-4b51b5eb75d5@bootlin.com>
On Tue, Mar 26, 2024 at 05:28:11PM +0100, Luca Ceresoli wrote:
> Add bindings for a physical, hot-pluggable connector allowing the far end
> of a MIPI DSI bus to be connected and disconnected at runtime.
>
> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> ---
> .../bridge/hotplug-video-connector-dsi.yaml | 87 ++++++++++++++++++++++
> MAINTAINERS | 5 ++
> 2 files changed, 92 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/hotplug-video-connector-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/hotplug-video-connector-dsi.yaml
> new file mode 100644
> index 000000000000..05beb8aa9ab4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/hotplug-video-connector-dsi.yaml
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/hotplug-video-connector-dsi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Hot-pluggable connector on a MIPI DSI bus
> +
> +maintainers:
> + - Luca Ceresoli <luca.ceresoli@bootlin.com>
> +
> +description:
> + A bridge representing a physical, hot-pluggable connector on a MIPI DSI
> + video bus. The connector splits the video pipeline in a fixed part and a
> + removable part.
> +
> + The fixed part of the video pipeline includes all components up to the
> + display controller and 0 or more bridges. The removable part includes one
> + or more bridges and any other components up to the panel.
> +
> + The removable part of the pipeline can be physically disconnected at any
> + moment, making all of its components not usable anymore. The same or a
> + different removable part of the pipeline can be reconnected later on.
> +
> + Note that the hotplug-video-connector does not describe video busses
> + having native hotplug capabilities in the hardware, such as HDMI.
> +
> +properties:
> + compatible:
> + const: hotplug-video-connector-dsi
Got a spec for this connector? How do I know if I have one or not?
The problem here is what else is on this connector? GPIO controls,
power rails, etc.?
If this is some kind of standard connector, then we need to be able to
remap everything on the connector not just DSI signals. And for that,
it's not just DSI signals, so I'd say we would need some sort of generic
graph remapping that the core graph code handles transparently.
If it is not standard, then you don't need any remapping and can just
use an overlay that connects the ports directly.
Rob
^ permalink raw reply
* Re: [PATCH v6 12/16] PCI/pwrctl: add PCI power control core code
From: Simon Horman @ 2024-03-27 16:16 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Marcel Holtmann, Luiz Augusto von Dentz, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kalle Valo, Bjorn Andersson,
Konrad Dybcio, Liam Girdwood, Mark Brown, Catalin Marinas,
Will Deacon, Bjorn Helgaas, Saravana Kannan, Geert Uytterhoeven,
Arnd Bergmann, Neil Armstrong, Marek Szyprowski, Alex Elder,
Srini Kandagatla, Greg Kroah-Hartman, Abel Vesa,
Manivannan Sadhasivam, Lukas Wunner, Dmitry Baryshkov,
linux-bluetooth, netdev, devicetree, linux-kernel, linux-wireless,
linux-arm-msm, linux-arm-kernel, linux-pci, linux-pm,
Bartosz Golaszewski
In-Reply-To: <20240325131624.26023-13-brgl@bgdev.pl>
On Mon, Mar 25, 2024 at 02:16:20PM +0100, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>
> Some PCI devices must be powered-on before they can be detected on the
> bus. Introduce a simple framework reusing the existing PCI OF
> infrastructure.
>
> The way this works is: a DT node representing a PCI device connected to
> the port can be matched against its power control platform driver. If
> the match succeeds, the driver is responsible for powering-up the device
> and calling pcie_pwrctl_device_set_ready() which will trigger a PCI bus
> rescan as well as subscribe to PCI bus notifications.
>
> When the device is detected and created, we'll make it consume the same
> DT node that the platform device did. When the device is bound, we'll
> create a device link between it and the parent power control device.
>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Hi Bartosz,
some minor Kernel doc nits from my side.
...
> diff --git a/drivers/pci/pwrctl/core.c b/drivers/pci/pwrctl/core.c
...
> +/**
> + * devm_pci_pwrctl_device_set_ready - Managed variant of
> + * pci_pwrctl_device_set_ready().
> + *
nit: @dev should be documented here
> + * @pwrctl: PCI power control data
> + *
> + * Returns:
> + * 0 on success, negative error number on error.
> + */
> +int devm_pci_pwrctl_device_set_ready(struct device *dev,
> + struct pci_pwrctl *pwrctl)
> +{
> + int ret;
> +
> + ret = pci_pwrctl_device_set_ready(pwrctl);
> + if (ret)
> + return ret;
> +
> + return devm_add_action_or_reset(dev,
> + devm_pci_pwrctl_device_unset_ready,
> + pwrctl);
> +}
> +EXPORT_SYMBOL_GPL(devm_pci_pwrctl_device_set_ready);
> +
> +MODULE_AUTHOR("Bartosz Golaszewski <bartosz.golaszewski@linaro.org>");
> +MODULE_DESCRIPTION("PCI Device Power Control core driver");
> +MODULE_LICENSE("GPL");
> diff --git a/include/linux/pci-pwrctl.h b/include/linux/pci-pwrctl.h
> new file mode 100644
> index 000000000000..ae8324ea7eeb
> --- /dev/null
> +++ b/include/linux/pci-pwrctl.h
> @@ -0,0 +1,51 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2024 Linaro Ltd.
> + */
> +
> +#ifndef __PCI_PWRCTL_H__
> +#define __PCI_PWRCTL_H__
> +
> +#include <linux/notifier.h>
> +
> +struct device;
> +struct device_link;
> +
> +/*
> + * This is a simple framework for solving the issue of PCI devices that require
> + * certain resources (regulators, GPIOs, clocks) to be enabled before the
> + * device can actually be detected on the PCI bus.
> + *
> + * The idea is to reuse the platform bus to populate OF nodes describing the
> + * PCI device and its resources, let these platform devices probe and enable
> + * relevant resources and then trigger a rescan of the PCI bus allowing for the
> + * same device (with a second associated struct device) to be registered with
> + * the PCI subsystem.
> + *
> + * To preserve a correct hierarchy for PCI power management and device reset,
> + * we create a device link between the power control platform device (parent)
> + * and the supplied PCI device (child).
> + */
> +
> +/**
> + * struct pci_pwrctl - PCI device power control context.
> + * @dev - Address of the power controlling device.
nit: I think this should be "@dev: " rather than "@dev - "
As is, "./scripts/kernel-doc -none" complains.
> + *
> + * An object of this type must be allocated by the PCI power control device and
> + * passed to the pwrctl subsystem to trigger a bus rescan and setup a device
> + * link with the device once it's up.
> + */
> +struct pci_pwrctl {
> + struct device *dev;
> +
> + /* Private, don't use. */
I think Private needs to be followed by a ':' rather than a ',' to keep
kernel-doc happy.
> + struct notifier_block nb;
> + struct device_link *link;
> +};
> +
> +int pci_pwrctl_device_set_ready(struct pci_pwrctl *pwrctl);
> +void pci_pwrctl_device_unset_ready(struct pci_pwrctl *pwrctl);
> +int devm_pci_pwrctl_device_set_ready(struct device *dev,
> + struct pci_pwrctl *pwrctl);
> +
> +#endif /* __PCI_PWRCTL_H__ */
> --
> 2.40.1
>
>
^ permalink raw reply
* Re: [PATCH v6 1/3] dt-bindings: mtd: Add Loongson-1 NAND Controller
From: Conor Dooley @ 2024-03-27 16:23 UTC (permalink / raw)
To: keguang.zhang
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-mtd,
linux-kernel, linux-mips, devicetree
In-Reply-To: <20240327-loongson1-nand-v6-1-7f9311cef020@gmail.com>
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On Wed, Mar 27, 2024 at 06:43:59PM +0800, Keguang Zhang via B4 Relay wrote:
> From: Keguang Zhang <keguang.zhang@gmail.com>
>
> Add devicetree binding document for Loongson-1 NAND Controller.
>
> Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
> ---
> Changes in v6:
> - A newly added patch
> ---
> .../devicetree/bindings/mtd/loongson,ls1x-nfc.yaml | 66 ++++++++++++++++++++++
> 1 file changed, 66 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mtd/loongson,ls1x-nfc.yaml b/Documentation/devicetree/bindings/mtd/loongson,ls1x-nfc.yaml
> new file mode 100644
> index 000000000000..2494c7b3b506
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/loongson,ls1x-nfc.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/loongson,ls1x-nfc.yaml#
Please make the filename match the compatible.
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson-1 NAND Controller
> +
> +maintainers:
> + - Keguang Zhang <keguang.zhang@gmail.com>
> +
> +allOf:
> + - $ref: nand-controller.yaml
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: loongson,ls1b-nfc
> + - items:
> + - enum:
> + - loongson,ls1a-nfc
> + - loongson,ls1c-nfc
> + - const: loongson,ls1b-nfc
> +
> + reg:
> + maxItems: 1
> +
> + dmas:
> + maxItems: 1
> +
> + dma-names:
> + const: rxtx
If you only have one dma, why do you need a dma-names entry for it?
Looks fine to me otherwise though,
COnor.
> +
> +patternProperties:
> + "^nand@[0-3]$":
> + type: object
> + $ref: raw-nand-chip.yaml
> +
> + unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - dmas
> + - dma-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + nand-controller@1fe78000 {
> + compatible = "loongson,ls1b-nfc";
> + reg = <0x1fe78000 0x40>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dmas = <&dma 0>;
> + dma-names = "rxtx";
> +
> + nand@0 {
> + reg = <0>;
> + nand-use-soft-ecc-engine;
> + nand-ecc-algo = "hamming";
> + };
> + };
>
> --
> 2.40.1
>
>
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^ permalink raw reply
* Re: [PATCH 7/7] regulator: mcp16502: Update the names from buck regulators
From: Conor Dooley @ 2024-03-27 16:28 UTC (permalink / raw)
To: Mihai Sain
Cc: robh, krzysztof.kozlowski+dt, conor+dt, nicolas.ferre,
alexandre.belloni, claudiu.beznea, lgirdwood, broonie,
andrei.simion, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20240327101724.2982-8-mihai.sain@microchip.com>
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On Wed, Mar 27, 2024 at 12:17:24PM +0200, Mihai Sain wrote:
> Use generic names for buck regulators to avoid any confusion.
> Update the names from buck regulators in order to match
> the datasheet block diagram for the buck regulators.
>
> Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
I know the regulator core will create dummy regulators when they are not
provided in the devicetree, so I am not 100% on how backwards
compatibility works here.
You'll end up with a bunch of dummies and therefore the regulator-names
and constraints on the regulator will be lost, no?
Can you explain how is this backwards compatible with the old
devicetrees?
Thanks,
Conor.
> ---
> drivers/regulator/mcp16502.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/regulator/mcp16502.c b/drivers/regulator/mcp16502.c
> index 0c15a19fe83a..d6fc9f1afaef 100644
> --- a/drivers/regulator/mcp16502.c
> +++ b/drivers/regulator/mcp16502.c
> @@ -468,13 +468,13 @@ static const struct linear_range b234_ranges[] = {
>
> static const struct regulator_desc mcp16502_desc[] = {
> /* MCP16502_REGULATOR(_name, _id, ranges, regulator_ops, ramp_table) */
> - MCP16502_REGULATOR("VDD_IO", BUCK1, b1l12_ranges, mcp16502_buck_ops,
> + MCP16502_REGULATOR("BUCK1", BUCK1, b1l12_ranges, mcp16502_buck_ops,
> mcp16502_ramp_b1l12),
> - MCP16502_REGULATOR("VDD_DDR", BUCK2, b234_ranges, mcp16502_buck_ops,
> + MCP16502_REGULATOR("BUCK2", BUCK2, b234_ranges, mcp16502_buck_ops,
> mcp16502_ramp_b234),
> - MCP16502_REGULATOR("VDD_CORE", BUCK3, b234_ranges, mcp16502_buck_ops,
> + MCP16502_REGULATOR("BUCK3", BUCK3, b234_ranges, mcp16502_buck_ops,
> mcp16502_ramp_b234),
> - MCP16502_REGULATOR("VDD_OTHER", BUCK4, b234_ranges, mcp16502_buck_ops,
> + MCP16502_REGULATOR("BUCK4", BUCK4, b234_ranges, mcp16502_buck_ops,
> mcp16502_ramp_b234),
> MCP16502_REGULATOR("LDO1", LDO1, b1l12_ranges, mcp16502_ldo_ops,
> mcp16502_ramp_b1l12),
> --
> 2.44.0
>
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^ permalink raw reply
* Re: [PATCH 1/3] phy: rockchip: emmc: Enable pulldown for strobe line
From: Folker Schwesinger @ 2024-03-27 16:21 UTC (permalink / raw)
To: Dragan Simic, Conor Dooley
Cc: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Chris Ruehl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christopher Obbard, Alban Browaeys, Doug Anderson, Brian Norris,
Jensen Huang, linux-phy, linux-arm-kernel, linux-rockchip,
linux-kernel, devicetree
In-Reply-To: <436f78a981ecba441a0636912ddd1cf2@manjaro.org>
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Hi Conor and Dragan,
thanks for your feedback!
On Tue Mar 26, 2024 at 8:55 PM CET, Dragan Simic wrote:
> On 2024-03-26 20:46, Conor Dooley wrote:
> > On Tue, Mar 26, 2024 at 07:54:35PM +0100, Folker Schwesinger via B4
> > Relay wrote:
> >> From: Folker Schwesinger <dev@folker-schwesinger.de>
> >>
> >> Restore the behavior of the Rockchip kernel that undconditionally
> >> enables the internal strobe pulldown.
> >
> > What do you mean "restore the behaviour of the rockchip kernel"? Did
> > mainline behave the same as the rockchip kernel previously? If not,
> > using "restore" here is misleading. "Unconditionally" is also
> > incorrect,
> > because you have a property that disables it.
Apologizes for the misleading commit message. Prior to 5.11 the Linux
kernel did not touch the pull-down registers. However, it seems the
register's (factory?) default was set to enable the pull-down. As it
was mentioned elsewhere that was the configuration recommended by
Rockchip. The 4.4 vendor (Rockchip) kernel reflects that by enabling the
pull-down in its kernel.
Of course, this has nothing to do with the Linux kernel, so "restore"
was a bad choice here.
I previously had split the driver patch into two separate patches, one
for changing the default (unconditionally at that point), the other for
adding the disable property. As both changes were minimal I decided to
squash the commits. I updated the cover letter, but forgot to update the
commit message. Sorry.
> >> Fixes: 8b5c2b45b8f0 ("phy: rockchip: set pulldown for strobe line in
> >> dts")
> >> Signed-off-by: Folker Schwesinger <dev@folker-schwesinger.de>
> >> ---
> >> drivers/phy/rockchip/phy-rockchip-emmc.c | 6 +++---
> >> 1 file changed, 3 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/phy/rockchip/phy-rockchip-emmc.c
> >> b/drivers/phy/rockchip/phy-rockchip-emmc.c
> >> index 20023f6eb994..6e637f3e1b19 100644
> >> --- a/drivers/phy/rockchip/phy-rockchip-emmc.c
> >> +++ b/drivers/phy/rockchip/phy-rockchip-emmc.c
> >> @@ -376,14 +376,14 @@ static int rockchip_emmc_phy_probe(struct
> >> platform_device *pdev)
> >> rk_phy->reg_offset = reg_offset;
> >> rk_phy->reg_base = grf;
> >> rk_phy->drive_impedance = PHYCTRL_DR_50OHM;
> >> - rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_DISABLE;
> >> + rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_ENABLE;
> >> rk_phy->output_tapdelay_select = PHYCTRL_OTAPDLYSEL_DEFAULT;
> >>
> >> if (!of_property_read_u32(dev->of_node, "drive-impedance-ohm",
> >> &val))
> >> rk_phy->drive_impedance = convert_drive_impedance_ohm(pdev, val);
> >>
> >> - if (of_property_read_bool(dev->of_node,
> >> "rockchip,enable-strobe-pulldown"))
> >> - rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_ENABLE;
> >> + if (of_property_read_bool(dev->of_node,
> >> "rockchip,disable-strobe-pulldown"))
> >> + rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_DISABLE;
> >
> > Unfortunately you cannot do this.
> > Previously no property at all meant disabled and a property was
> > required
> > to enable it. With this change the absence of a property means that it
> > will be enabled.
> > An old devicetree is that wanted this to be disabled would have no
> > property and will now end up with it enabled. This is an ABI break and
> > is
> > clearly not backwards compatible, that's a NAK unless it is
> > demonstrable
> > that noone actually wants to disable it at all.
> >
>
> Moreover, as I already explained some time ago, [1] some boards and
> devices are unfortunately miswired, and we don't want to enable the
> DATA STROBE pull-down on such boards.
>
> [1]
> https://lore.kernel.org/linux-rockchip/ca5b7cad01f645c7c559ab26a8db8085@manjaro.org/#t
>
> > If this patch fixes a problem on a board that you have, I would suggest
> > that you add the property to enable it, as the binding tells you to.
I agree, I'll post the patches later.
Best regards
Folker
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