* Re: [PATCH v2 2/2] mfd: rohm-bd71828: Add power off functionality
From: Matti Vaittinen @ 2024-03-28 5:15 UTC (permalink / raw)
To: Andreas Kemnade
Cc: lee, robh+dt, krzysztof.kozlowski+dt, conor+dt, devicetree,
linux-kernel
In-Reply-To: <20240327230252.0535e895@aktux>
Morning Andreas,
On 3/28/24 00:02, Andreas Kemnade wrote:
> Hi Matti,
>
> On Wed, 27 Mar 2024 16:11:36 +0200
> Matti Vaittinen <mazziesaccount@gmail.com> wrote:
>
>> On 3/27/24 15:04, Andreas Kemnade wrote:
>>> Hi,
>>>
>>> On Wed, 27 Mar 2024 09:32:29 +0200
>>> Matti Vaittinen <mazziesaccount@gmail.com> wrote:
>>>
>>>> It's worth noting that there is another PMIC, BD71879, which, from the
>>>> driver software point of view, should be (almost?) identical to the
>>>> BD71828. I believe the BD71828 drivers should work with it as well - if
>>>> not out of the box, at least with very minor modifications.
>>>> Unfortunately I don't know products where the BD71879 is used or if it
>>>> is sold via distributors - so I don't know if adding a DT
>>>> compatible/chip type define for it would be beneficial.
>>>
>>> yes, you already told we thet the BD71828 drivers are compatible with
>>> the BD71879 and I am using the latter.
>>> But that at least should be commented somewhere, so that
>>> people do not raise questions, like: Do I have some strange board revision,
>>> etc?
>>> The most terse form to comment it is a separate dt compatible so we are
>>> prepare any "almost identical" surprises.
>>
>> I agree. Reason why I haven't done this already is that I don't always
>> (like in this case) know which of the variant are eventually sold. So,
>> it's balancing dance between adding compatibles for ICs that will never
>> been seen by large audience, and missing compatibles for some of the
>> variants.
>>
>> This is also why I was interested in knowing which variant you had, and
>> where was it used.
>>
> I have found it in the Kobo Clara 2E ebook reader.
> Kobo seems to switch from RC5T619 to BD71879.
> The Kobo Nia rev C also has that one.
> Kobo Libra 2 has several hardware revs out in the wild, some of them
> with the BD71879.
Thanks for the info :) It's a shame we so rarely know where things we
work for are used. I always find news like this interesting.
>> But yes, I think that as the BD71879 has obviously been found by a
>> community linux kernel user - it would make sense to add a compatible
>> for it!
>>
>> Do you feel like adding the compatible 'rohm,bd71879' in
>> rohm,bd71828-pmic.yaml as part of this series(?)
>
> Do we want a separate chip_type now? Or do we want to add it later if
> we ever see a difference. My personal opinion is to wait until there is
> really a need.
Using the BD71828 chip_id for BD71879 in the MFD driver is fine to me. A
comment saying they seem "functionally equivalent" can be added to
explain this choice.
> If we do not need it, then it is a different series I think but sure
> I will produce such a patch.
Great, thanks! I think it's clearer to have it as own patch, but I think
it fits in the same series - what suits you best. (Don't know if Lee or
DT peeps have different opinion.)
Yours,
-- Matti
--
Matti Vaittinen
Linux kernel developer at ROHM Semiconductors
Oulu Finland
~~ When things go utterly wrong vim users can always type :help! ~~
^ permalink raw reply
* Re: [PATCH v9 08/38] dt-bindings: dma: Add Cirrus EP93xx
From: Vinod Koul @ 2024-03-28 4:26 UTC (permalink / raw)
To: nikita.shubin
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Alexander Sverdlin, dmaengine, devicetree, linux-kernel,
Arnd Bergmann, Krzysztof Kozlowski
In-Reply-To: <20240326-ep93xx-v9-8-156e2ae5dfc8@maquefel.me>
On 26-03-24, 12:18, Nikita Shubin via B4 Relay wrote:
> From: Nikita Shubin <nikita.shubin@maquefel.me>
>
> Add YAML bindings for ep93xx SoC DMA.
Acked-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply
* Re: [PATCH 2/3] dt-bindings: ufs: qcom: document SC7180 UFS
From: Manivannan Sadhasivam @ 2024-03-28 3:59 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Konrad Dybcio, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, linux-arm-msm, linux-scsi, devicetree, linux-kernel
In-Reply-To: <20240326174632.209745-2-krzysztof.kozlowski@linaro.org>
On Tue, Mar 26, 2024 at 06:46:31PM +0100, Krzysztof Kozlowski wrote:
> Document already upstreamed and used Qualcomm SC7180 UFS host controller
> to fix dtbs_check warnings like:
>
> sc7180-idp.dtb: ufshc@1d84000: compatible:0: 'qcom,sc7180-ufshc' is not one of ...
> sc7180-idp.dtb: ufshc@1d84000: clocks: [[39, 99], [39, 7], [39, 98], [39, 107], [36, 0], [39, 106], [39, 105]] is too short
> sc7180-idp.dtb: ufshc@1d84000: clock-names: ['core_clk', 'bus_aggr_clk', 'iface_clk', 'core_clk_unipro', ...] is too short
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../devicetree/bindings/ufs/qcom,ufs.yaml | 34 ++++++++++++++++---
> 1 file changed, 30 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> index 1ab3d16917ac..7e6d442545ad 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> @@ -27,6 +27,7 @@ properties:
> - qcom,msm8996-ufshc
> - qcom,msm8998-ufshc
> - qcom,sa8775p-ufshc
> + - qcom,sc7180-ufshc
> - qcom,sc7280-ufshc
> - qcom,sc8180x-ufshc
> - qcom,sc8280xp-ufshc
> @@ -43,11 +44,11 @@ properties:
> - const: jedec,ufs-2.0
>
> clocks:
> - minItems: 8
> + minItems: 7
> maxItems: 11
>
> clock-names:
> - minItems: 8
> + minItems: 7
> maxItems: 11
>
> dma-coherent: true
> @@ -113,6 +114,31 @@ required:
> allOf:
> - $ref: ufs-common.yaml
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc7180-ufshc
> + then:
> + properties:
> + clocks:
> + minItems: 7
> + maxItems: 7
> + clock-names:
> + items:
> + - const: core_clk
> + - const: bus_aggr_clk
> + - const: iface_clk
> + - const: core_clk_unipro
> + - const: ref_clk
> + - const: tx_lane0_sync_clk
> + - const: rx_lane0_sync_clk
> + reg:
> + maxItems: 1
> + reg-names:
> + maxItems: 1
> +
> - if:
> properties:
> compatible:
> @@ -250,7 +276,7 @@ allOf:
> reg:
> maxItems: 1
> clocks:
> - minItems: 8
> + minItems: 7
> maxItems: 8
> else:
> properties:
> @@ -258,7 +284,7 @@ allOf:
> minItems: 1
> maxItems: 2
> clocks:
> - minItems: 8
> + minItems: 7
I'm getting confused by the clock requirements for qcom,ice. Why does specifying
the qcom,ice phandle require these clocks? These are the UFSHC clocks and
already defined above.
- Mani
> maxItems: 11
>
> unevaluatedProperties: false
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* Re: [PATCH v5 4/4] drivers: watchdog: ast2500 and ast2600 support bootstatus
From: PeterYin @ 2024-03-28 3:17 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240328013303.3609385-5-peteryin.openbmc@gmail.com>
Peter Yin 於 3/28/24 09:33 寫道:
> Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2600
>
> Regarding the AST2600 specification, the WDTn Timeout Status Register
> (WDT10) has bit 1 reserved. Bit 1 of the status register indicates
> on ast2500 if the boot was from the second boot source.
> It does not indicate that the most recent reset was triggered by
> the watchdog. The code should just be changed to set WDIOF_CARDRESET
> if bit 0 of the status register is set.
>
> Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or
> ast2500 SCU3C when bit1 is set.
>
> Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
> ---
> drivers/watchdog/aspeed_wdt.c | 34 ++++++++++++++++++++++++++++++----
> 1 file changed, 30 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
> index b4773a6aaf8c..c3c8098c035d 100644
> --- a/drivers/watchdog/aspeed_wdt.c
> +++ b/drivers/watchdog/aspeed_wdt.c
> @@ -11,10 +11,12 @@
> #include <linux/io.h>
> #include <linux/kernel.h>
> #include <linux/kstrtox.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
> +#include <linux/regmap.h>
> #include <linux/watchdog.h>
>
> static bool nowayout = WATCHDOG_NOWAYOUT;
> @@ -82,6 +84,13 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
> #define WDT_RESET_MASK1 0x1c
> #define WDT_RESET_MASK2 0x20
>
> +/*
> + * Ast2600 SCU74 bit1 is External reset flag
> + * Ast2500 SCU3C bit1 is External reset flag
> + */
> +#define AST2500_SYSTEM_RESET_EVENT 0x3C
> +#define AST2600_SYSTEM_RESET_EVENT 0x74
> +#define EXTERN_RESET_FLAG BIT(1)
> /*
> * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
> * enabled), specifically:
> @@ -330,6 +339,11 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
> if (IS_ERR(wdt->base))
> return PTR_ERR(wdt->base);
>
> + struct regmap *scu_base = syscon_regmap_lookup_by_phandle(dev->of_node,
> + "aspeed,scu");
> + if (IS_ERR(scu_base))
> + return PTR_ERR(scu_base);
> +
> wdt->wdd.info = &aspeed_wdt_info;
>
> if (wdt->cfg->irq_mask) {
> @@ -459,14 +473,26 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
> }
>
> status = readl(wdt->base + WDT_TIMEOUT_STATUS);
> - if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
> + if (status & WDT_TIMEOUT_STATUS_EVENT)
> wdt->wdd.bootstatus = WDIOF_CARDRESET;
>
> - if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
> - of_device_is_compatible(np, "aspeed,ast2500-wdt"))
> - wdt->wdd.groups = bswitch_groups;
> + if (of_device_is_compatible(np, "aspeed,ast2600-wdt")) {
> + ret = regmap_read(scu_base,
> + AST2600_SYSTEM_RESET_EVENT,
> + &status);
> + } else {
> + ret = regmap_read(scu_base,
> + AST2500_SYSTEM_RESET_EVENT,
> + &status);
> + wdt->wdd.groups = bswitch_groups;
> }
>
> + /*
> + * Reset cause by Extern Reset
> + */
> + if (status & EXTERN_RESET_FLAG && !ret)
> + wdt->wdd.bootstatus |= WDIOF_EXTERN1;
> +
> dev_set_drvdata(dev, wdt);
>
> return devm_watchdog_register_device(dev, &wdt->wdd);
Please ignore this version, as I lost the definition for
WDT_TIMEOUT_STATUS_EVENT.
Thanks.
^ permalink raw reply
* Re: [PATCH v2 2/6] arm64: dts: qcom: qcs6490-rb3gen2: Add DP output
From: Bjorn Andersson @ 2024-03-28 3:07 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, cros-qcom-dts-watchers, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, linux-arm-msm, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <CAA8EJpoe7A94608V1GdQ-oU9UXagHPm0mVBUe4Yxi=HF2pMd7w@mail.gmail.com>
On Thu, Mar 28, 2024 at 03:51:54AM +0200, Dmitry Baryshkov wrote:
> On Wed, 27 Mar 2024 at 04:04, Bjorn Andersson <quic_bjorande@quicinc.com> wrote:
> >
> > The RB3Gen2 board comes with a mini DP connector, describe this, enable
> > MDSS, DP controller and the PHY that drives this.
> >
> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> > ---
> > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 40 ++++++++++++++++++++++++++++
> > 1 file changed, 40 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> > index 63ebe0774f1d..f90bf3518e98 100644
> > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> > @@ -39,6 +39,20 @@ chosen {
> > stdout-path = "serial0:115200n8";
> > };
> >
> > + dp-connector {
> > + compatible = "dp-connector";
> > + label = "DP";
> > + type = "mini";
> > +
> > + hpd-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
>
> Is it the standard hpd gpio? If so, is there any reason for using it
> through dp-connector rather than as a native HPD signal?
>
I added it because you asked for it. That said, I do like having it
clearly defined in the devicetree.
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller
From: Bjorn Andersson @ 2024-03-28 2:29 UTC (permalink / raw)
To: Maximilian Luz
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vinod Koul, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240328022224.336938-1-luzmaximilian@gmail.com>
On Thu, Mar 28, 2024 at 03:21:57AM +0100, Maximilian Luz wrote:
> The ACPI DSDT of the Surface Pro X (SQ2) specifies the interrupts for
> the secondary UBS controller as
>
> Name (_CRS, ResourceTemplate ()
> {
> Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
> {
> 0x000000AA,
> }
> Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, )
> {
> 0x000000A7, // hs_phy_irq: &intc GIC_SPI 136
> }
> Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, )
> {
> 0x00000228, // ss_phy_irq: &pdc 40
> }
> Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, )
> {
> 0x0000020A, // dm_hs_phy_irq: &pdc 10
> }
> Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, )
> {
> 0x0000020B, // dp_hs_phy_irq: &pdc 11
> }
> })
>
> Generally, the interrupts above 0x200 map to the PDC interrupts (as used
> in the devicetree) as ACPI_NUMBER - 0x200. Note that this lines up with
> dm_hs_phy_irq and dp_hs_phy_irq (as well as the interrupts for the
> primary USB controller).
>
> Based on the snippet above, ss_phy_irq should therefore be PDC 40 (=
> 0x28) and not PDC 7. The latter is according to ACPI instead used as
> ss_phy_irq for port 0 of the multiport USB controller). Fix this by
> setting ss_phy_irq to '&pdc 40'.
>
> Fixes: b080f53a8f44 ("arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes")
> Signed-off-by: Maximilian Luz <luzmaximilian@gmail.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Regards,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> index 32afc78d5b769..053f7861c3cec 100644
> --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> @@ -2701,7 +2701,7 @@ usb_sec: usb@a8f8800 {
> resets = <&gcc GCC_USB30_SEC_BCR>;
> power-domains = <&gcc USB30_SEC_GDSC>;
> interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> - <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
> <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
> <&pdc 11 IRQ_TYPE_EDGE_BOTH>;
> interrupt-names = "hs_phy_irq", "ss_phy_irq",
> --
> 2.44.0
>
^ permalink raw reply
* [PATCH v6 4/4] drivers: watchdog: ast2500 and ast2600 support bootstatus
From: Peter Yin @ 2024-03-28 2:22 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240328022231.3649741-1-peteryin.openbmc@gmail.com>
Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2600
Regarding the AST2600 specification, the WDTn Timeout Status Register
(WDT10) has bit 1 reserved. Bit 1 of the status register indicates
on ast2500 if the boot was from the second boot source.
It does not indicate that the most recent reset was triggered by
the watchdog. The code should just be changed to set WDIOF_CARDRESET
if bit 0 of the status register is set.
Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or
ast2500 SCU3C when bit1 is set.
Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
---
drivers/watchdog/aspeed_wdt.c | 35 +++++++++++++++++++++++++++++++----
1 file changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
index b4773a6aaf8c..0e7ef860cbdc 100644
--- a/drivers/watchdog/aspeed_wdt.c
+++ b/drivers/watchdog/aspeed_wdt.c
@@ -11,10 +11,12 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/kstrtox.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/watchdog.h>
static bool nowayout = WATCHDOG_NOWAYOUT;
@@ -77,11 +79,19 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
#define WDT_TIMEOUT_STATUS 0x10
#define WDT_TIMEOUT_STATUS_IRQ BIT(2)
#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
+#define WDT_TIMEOUT_STATUS_EVENT BIT(0)
#define WDT_CLEAR_TIMEOUT_STATUS 0x14
#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
#define WDT_RESET_MASK1 0x1c
#define WDT_RESET_MASK2 0x20
+/*
+ * Ast2600 SCU74 bit1 is External reset flag
+ * Ast2500 SCU3C bit1 is External reset flag
+ */
+#define AST2500_SYSTEM_RESET_EVENT 0x3C
+#define AST2600_SYSTEM_RESET_EVENT 0x74
+#define EXTERN_RESET_FLAG BIT(1)
/*
* WDT_RESET_WIDTH controls the characteristics of the external pulse (if
* enabled), specifically:
@@ -330,6 +340,11 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
if (IS_ERR(wdt->base))
return PTR_ERR(wdt->base);
+ struct regmap *scu_base = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "aspeed,scu");
+ if (IS_ERR(scu_base))
+ return PTR_ERR(scu_base);
+
wdt->wdd.info = &aspeed_wdt_info;
if (wdt->cfg->irq_mask) {
@@ -459,14 +474,26 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
}
status = readl(wdt->base + WDT_TIMEOUT_STATUS);
- if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
+ if (status & WDT_TIMEOUT_STATUS_EVENT)
wdt->wdd.bootstatus = WDIOF_CARDRESET;
- if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
- of_device_is_compatible(np, "aspeed,ast2500-wdt"))
- wdt->wdd.groups = bswitch_groups;
+ if (of_device_is_compatible(np, "aspeed,ast2600-wdt")) {
+ ret = regmap_read(scu_base,
+ AST2600_SYSTEM_RESET_EVENT,
+ &status);
+ } else {
+ ret = regmap_read(scu_base,
+ AST2500_SYSTEM_RESET_EVENT,
+ &status);
+ wdt->wdd.groups = bswitch_groups;
}
+ /*
+ * Reset cause by Extern Reset
+ */
+ if (status & EXTERN_RESET_FLAG && !ret)
+ wdt->wdd.bootstatus |= WDIOF_EXTERN1;
+
dev_set_drvdata(dev, wdt);
return devm_watchdog_register_device(dev, &wdt->wdd);
--
2.25.1
^ permalink raw reply related
* [PATCH v6 3/4] dt-bindings: watchdog: aspeed-wdt: Add aspeed,scu
From: Peter Yin @ 2024-03-28 2:22 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240328022231.3649741-1-peteryin.openbmc@gmail.com>
To use the SCU register to obtain reset flags for supporting
bootstatus.
Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
---
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
index 3208adb3e52e..80a1f58b5a2e 100644
--- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
@@ -8,6 +8,8 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped
region
+ - aspeed,scu: a reference to the System Control Unit node of the Aspeed
+ SOC.
Optional properties:
@@ -62,6 +64,7 @@ Examples:
reg = <0x1e785000 0x1c>;
aspeed,reset-type = "system";
aspeed,external-signal;
+ aspeed,scu = <&syscon>;
};
#include <dt-bindings/watchdog/aspeed-wdt.h>
@@ -70,4 +73,5 @@ Examples:
reg = <0x1e785040 0x40>;
aspeed,reset-mask = <AST2600_WDT_RESET1_DEFAULT
(AST2600_WDT_RESET2_DEFAULT & ~AST2600_WDT_RESET2_LPC)>;
+ aspeed,scu = <&syscon>;
};
--
2.25.1
^ permalink raw reply related
* [PATCH v6 2/4] ARM: dts: aspeed: Add the AST2600 WDT with SCU register
From: Peter Yin @ 2024-03-28 2:22 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240328022231.3649741-1-peteryin.openbmc@gmail.com>
The AST2600 Watchdog Timer (WDT) references
the System Control Unit (SCU) register for its operation.
Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
---
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
index ead835fca657..b47850f0dca0 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
@@ -557,23 +557,27 @@ uart5: serial@1e784000 {
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785000 0x40>;
+ aspeed,scu = <&syscon>;
};
wdt2: watchdog@1e785040 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785040 0x40>;
+ aspeed,scu = <&syscon>;
status = "disabled";
};
wdt3: watchdog@1e785080 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785080 0x40>;
+ aspeed,scu = <&syscon>;
status = "disabled";
};
wdt4: watchdog@1e7850c0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
+ aspeed,scu = <&syscon>;
status = "disabled";
};
--
2.25.1
^ permalink raw reply related
* [PATCH v6 1/4] ARM: dts: aspeed: Add the AST2500 WDT with SCU register
From: Peter Yin @ 2024-03-28 2:22 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240328022231.3649741-1-peteryin.openbmc@gmail.com>
The AST2500 WDT references the System Control Unit
register for its operation.
Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
---
arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi
index 04f98d1dbb97..5fd12c057c31 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi
@@ -410,12 +410,14 @@ wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785000 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
+ aspeed,scu = <&syscon>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785020 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
+ aspeed,scu = <&syscon>;
};
wdt3: watchdog@1e785040 {
@@ -423,6 +425,7 @@ wdt3: watchdog@1e785040 {
reg = <0x1e785040 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
status = "disabled";
+ aspeed,scu = <&syscon>;
};
pwm_tacho: pwm-tacho-controller@1e786000 {
--
2.25.1
^ permalink raw reply related
* [PATCH v6 0/4] drivers: watchdog: ast2500 and ast2600 support bootstatus
From: Peter Yin @ 2024-03-28 2:22 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2500/ast2600
Regarding the AST2600 specification, the WDTn Timeout Status Register
(WDT10) has bit 1 reserved. Bit 1 of the status register indicates
on ast2500 if the boot was from the second boot source.
It does not indicate that the most recent reset was triggered by
the watchdog. The code should just be changed to set WDIOF_CARDRESET
if bit 0 of the status register is set.
Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or
ast2500 SCU3C when bit1 is set.
Change Log:
v5 -> v6
- Fixed missing WDT_TIMEOUT_STATUS_EVENT.
v4 -> v5
- Revert indentation.
v3 -> v4
- Add error handling for syscon_regmap_lookup_by_phandle and
regmap_read.
v2 -> v3
- Fixed WDIOF_CARDRESET status bit check and added support
for WDIOF_EXTERN1 on ast2500 and ast2600.
v1 -> v2
- Add comment and support WDIOF_CARDRESET in ast2600
v1
- Patch 0001 - Add WDIOF_EXTERN1 bootstatus
---
Peter Yin (4):
ARM: dts: aspeed: Add the AST2500 WDT with SCU register
ARM: dts: aspeed: Add the AST2600 WDT with SCU register
dt-bindings: watchdog: aspeed-wdt: Add aspeed,scu
drivers: watchdog: ast2500 and ast2600 support bootstatus
.../bindings/watchdog/aspeed-wdt.txt | 4 +++
arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 3 ++
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 +++
drivers/watchdog/aspeed_wdt.c | 35 ++++++++++++++++---
4 files changed, 42 insertions(+), 4 deletions(-)
--
2.25.1
^ permalink raw reply
* [PATCH] arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller
From: Maximilian Luz @ 2024-03-28 2:21 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Maximilian Luz, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, linux-arm-msm, devicetree, linux-kernel
The ACPI DSDT of the Surface Pro X (SQ2) specifies the interrupts for
the secondary UBS controller as
Name (_CRS, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
{
0x000000AA,
}
Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, )
{
0x000000A7, // hs_phy_irq: &intc GIC_SPI 136
}
Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, )
{
0x00000228, // ss_phy_irq: &pdc 40
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, )
{
0x0000020A, // dm_hs_phy_irq: &pdc 10
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, )
{
0x0000020B, // dp_hs_phy_irq: &pdc 11
}
})
Generally, the interrupts above 0x200 map to the PDC interrupts (as used
in the devicetree) as ACPI_NUMBER - 0x200. Note that this lines up with
dm_hs_phy_irq and dp_hs_phy_irq (as well as the interrupts for the
primary USB controller).
Based on the snippet above, ss_phy_irq should therefore be PDC 40 (=
0x28) and not PDC 7. The latter is according to ACPI instead used as
ss_phy_irq for port 0 of the multiport USB controller). Fix this by
setting ss_phy_irq to '&pdc 40'.
Fixes: b080f53a8f44 ("arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes")
Signed-off-by: Maximilian Luz <luzmaximilian@gmail.com>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 32afc78d5b769..053f7861c3cec 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -2701,7 +2701,7 @@ usb_sec: usb@a8f8800 {
resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc USB30_SEC_GDSC>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
--
2.44.0
^ permalink raw reply related
* Re: [PATCH v2 5/6] arm64: dts: qcom: qcs6490-rb3gen2: Enable USB Type-C display
From: Dmitry Baryshkov @ 2024-03-28 2:04 UTC (permalink / raw)
To: Bjorn Andersson
Cc: cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, linux-arm-msm, devicetree, linux-kernel,
linux-arm-kernel, Neil Armstrong, Krishna Kurapati PSSNV
In-Reply-To: <20240326-rb3gen2-dp-connector-v2-5-a9f1bc32ecaf@quicinc.com>
On Wed, 27 Mar 2024 at 04:04, Bjorn Andersson <quic_bjorande@quicinc.com> wrote:
>
> With the ADSP remoteproc loaded pmic_glink can be introduced and
> together with the redriver wired up to provide role and orientation
> switching signals as well as USB Type-C display on the RB3gen2.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Tested-By: Krishna Kurapati PSSNV <quic_kriskura@quicinc.com>
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 107 ++++++++++++++++++++++++++-
> 1 file changed, 106 insertions(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH v2] arm64: dts: qcom: qcs6490-rb3gen2: Enable UFS
From: Bjorn Andersson @ 2024-03-28 2:01 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Bjorn Andersson
The rb3gen2 has UFS memory, adjust the necessary supply voltage and add
the controller and phy nodes to enable this.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---
Changes in v2:
- Added missing regulator-allow-set-load and regulator-allowed-modes
- Dropped max-voltage for vreg_l9b_1p2 to it's expected value
- Link to v1: https://lore.kernel.org/r/20240326-rb3gen2-ufs-v1-1-8c5c2dae1e64@quicinc.com
---
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 28 +++++++++++++++++++++++++---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 63ebe0774f1d..79d7c8932bff 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -221,8 +221,8 @@ vreg_l6b_1p2: ldo6 {
vreg_l7b_2p952: ldo7 {
regulator-name = "vreg_l7b_2p952";
- regulator-min-microvolt = <2400000>;
- regulator-max-microvolt = <3544000>;
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <2952000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
@@ -236,8 +236,11 @@ vreg_l8b_0p904: ldo8 {
vreg_l9b_1p2: ldo9 {
regulator-name = "vreg_l9b_1p2";
regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1304000>;
+ regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11b_1p504: ldo11 {
@@ -508,6 +511,25 @@ &usb_1_qmpphy {
status = "okay";
};
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l7b_2p952>;
+ vcc-max-microamp = <800000>;
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <900000>;
+ vccq2-supply = <&vreg_l9b_1p2>;
+ vccq2-max-microamp = <900000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
&wifi {
memory-region = <&wlan_fw_mem>;
};
---
base-commit: 084c8e315db34b59d38d06e684b1a0dd07d30287
change-id: 20240326-rb3gen2-ufs-7ddb07157556
Best regards,
--
Bjorn Andersson <quic_bjorande@quicinc.com>
^ permalink raw reply related
* Re: [RISC-V] [tech-j-ext] [RFC PATCH 5/9] riscv: Split per-CPU and per-thread envcfg bits
From: Deepak Gupta @ 2024-03-28 1:58 UTC (permalink / raw)
To: Samuel Holland
Cc: Palmer Dabbelt, linux-riscv, devicetree, Catalin Marinas,
linux-kernel, tech-j-ext, Conor Dooley, kasan-dev,
Evgenii Stepanov, Krzysztof Kozlowski, Rob Herring, Andrew Jones,
Guo Ren, Heiko Stuebner, Paul Walmsley
In-Reply-To: <40ab1ce5-8700-4a63-b182-1e864f6c9225@sifive.com>
On Tue, Mar 19, 2024 at 7:21 PM Samuel Holland
<samuel.holland@sifive.com> wrote:
>
> > else
> > regs->status |= SR_UXL_64;
> > #endif
> > + current->thread_info.envcfg = ENVCFG_BASE;
> > }
> >
> > And instead of context switching in `_switch_to`,
> > In `entry.S` pick up `envcfg` from `thread_info` and write it into CSR.
>
> The immediate reason is that writing envcfg in ret_from_exception() adds cycles
> to every IRQ and system call exit, even though most of them will not change the
> envcfg value. This is especially the case when returning from an IRQ/exception
> back to S-mode, since envcfg has zero effect there.
>
A quick observation:
So I tried this on my setup. When I put `senvcfg` writes in
`__switch_to ` path, qemu suddenly
just tanks and takes a lot of time to boot up as opposed to when
`senvcfg` was in trap return path.
In my case entire userspace (all processes) have cfi enabled for them
via `senvcfg` and it gets
context switched. Not sure it's specific to my setup. I don't think it
should be an issue on actual
hardware.
Still debugging why it slows down my qemu drastically when same writes
to same CSR
are moved from `ret_from_exception` to `switch_to`
^ permalink raw reply
* Re: [PATCH v2 3/6] arm64: dts: qcom: qcs6490-rb3gen2: Enable adsp and cdsp
From: Dmitry Baryshkov @ 2024-03-28 1:54 UTC (permalink / raw)
To: Bjorn Andersson
Cc: cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, linux-arm-msm, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20240326-rb3gen2-dp-connector-v2-3-a9f1bc32ecaf@quicinc.com>
On Wed, 27 Mar 2024 at 04:04, Bjorn Andersson <quic_bjorande@quicinc.com> wrote:
>
> Define firmware paths and enable the ADSP and CDSP remoteprocs.
>
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 2/6] arm64: dts: qcom: qcs6490-rb3gen2: Add DP output
From: Dmitry Baryshkov @ 2024-03-28 1:51 UTC (permalink / raw)
To: Bjorn Andersson
Cc: cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, linux-arm-msm, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20240326-rb3gen2-dp-connector-v2-2-a9f1bc32ecaf@quicinc.com>
On Wed, 27 Mar 2024 at 04:04, Bjorn Andersson <quic_bjorande@quicinc.com> wrote:
>
> The RB3Gen2 board comes with a mini DP connector, describe this, enable
> MDSS, DP controller and the PHY that drives this.
>
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 40 ++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> index 63ebe0774f1d..f90bf3518e98 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> @@ -39,6 +39,20 @@ chosen {
> stdout-path = "serial0:115200n8";
> };
>
> + dp-connector {
> + compatible = "dp-connector";
> + label = "DP";
> + type = "mini";
> +
> + hpd-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
Is it the standard hpd gpio? If so, is there any reason for using it
through dp-connector rather than as a native HPD signal?
> +
> + port {
> + dp_connector_in: endpoint {
> + remote-endpoint = <&mdss_edp_out>;
> + };
> + };
> + };
> +
> reserved-memory {
> xbl_mem: xbl@80700000 {
> reg = <0x0 0x80700000 0x0 0x100000>;
> @@ -471,6 +485,25 @@ &gcc {
> <GCC_WPSS_RSCP_CLK>;
> };
>
> +&mdss {
> + status = "okay";
> +};
> +
> +&mdss_edp {
> + status = "okay";
> +};
> +
> +&mdss_edp_out {
> + data-lanes = <0 1 2 3>;
> + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
> +
> + remote-endpoint = <&dp_connector_in>;
> +};
> +
> +&mdss_edp_phy {
> + status = "okay";
> +};
> +
> &qupv3_id_0 {
> status = "okay";
> };
> @@ -511,3 +544,10 @@ &usb_1_qmpphy {
> &wifi {
> memory-region = <&wlan_fw_mem>;
> };
> +
> +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
> +
> +&edp_hot_plug_det {
> + function = "gpio";
> + bias-disable;
> +};
>
> --
> 2.25.1
>
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH] dt-bindings: ti,pcm1681: Convert to dtschema
From: Animesh Agarwal @ 2024-03-28 1:40 UTC (permalink / raw)
Cc: animeshagarwal28, Shenghao Ding, Kevin Lu, Baojun Xu,
Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, alsa-devel, devicetree, linux-kernel
Convert the Texas Instruments PCM1681 bindings to DT schema.
Signed-off-by: Animesh Agarwal <animeshagarwal28@gmail.com>
---
.../devicetree/bindings/sound/ti,pcm1681.txt | 15 --------
.../devicetree/bindings/sound/ti,pcm1681.yaml | 35 +++++++++++++++++++
2 files changed, 35 insertions(+), 15 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/ti,pcm1681.txt
create mode 100644 Documentation/devicetree/bindings/sound/ti,pcm1681.yaml
diff --git a/Documentation/devicetree/bindings/sound/ti,pcm1681.txt b/Documentation/devicetree/bindings/sound/ti,pcm1681.txt
deleted file mode 100644
index 4df17185ab80..000000000000
--- a/Documentation/devicetree/bindings/sound/ti,pcm1681.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Texas Instruments PCM1681 8-channel PWM Processor
-
-Required properties:
-
- - compatible: Should contain "ti,pcm1681".
- - reg: The i2c address. Should contain <0x4c>.
-
-Examples:
-
- i2c_bus {
- pcm1681@4c {
- compatible = "ti,pcm1681";
- reg = <0x4c>;
- };
- };
diff --git a/Documentation/devicetree/bindings/sound/ti,pcm1681.yaml b/Documentation/devicetree/bindings/sound/ti,pcm1681.yaml
new file mode 100644
index 000000000000..4093d0ff654d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ti,pcm1681.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,pcm1681.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments PCM1681 8-channel PWM Processor
+
+maintainers:
+ - Animesh Agarwal <animeshagarwal28@gmail.com>
+
+properties:
+ compatible:
+ const: ti,pcm1681
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcm1681@4c {
+ compatible = "ti,pcm1681";
+ reg = <0x4c>;
+ };
+ };
--
2.44.0
^ permalink raw reply related
* Re: [PATCH v3] dt-bindings: ata: ahci-da850: Convert to dtschema
From: Animesh Agarwal @ 2024-03-28 1:35 UTC (permalink / raw)
To: Conor Dooley
Cc: Damien Le Moal, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-ide, devicetree, linux-kernel
In-Reply-To: <20240327-dumpster-capital-fcb7d205b294@spud>
On Wed, Mar 27, 2024 at 10:16 PM Conor Dooley <conor@kernel.org> wrote:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks Conor.
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: crypto: ti,omap-sham: Convert to dtschema
From: Animesh Agarwal @ 2024-03-28 1:34 UTC (permalink / raw)
To: Conor Dooley
Cc: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-crypto, devicetree, linux-kernel
In-Reply-To: <20240327-attribute-stubbly-d09613567e0d@spud>
On Wed, Mar 27, 2024 at 10:22 PM Conor Dooley <conor@kernel.org> wrote:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for the review, Conor.
Regards,
Animesh Agarwal.
^ permalink raw reply
* [PATCH v5 4/4] drivers: watchdog: ast2500 and ast2600 support bootstatus
From: Peter Yin @ 2024-03-28 1:33 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240328013303.3609385-1-peteryin.openbmc@gmail.com>
Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2600
Regarding the AST2600 specification, the WDTn Timeout Status Register
(WDT10) has bit 1 reserved. Bit 1 of the status register indicates
on ast2500 if the boot was from the second boot source.
It does not indicate that the most recent reset was triggered by
the watchdog. The code should just be changed to set WDIOF_CARDRESET
if bit 0 of the status register is set.
Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or
ast2500 SCU3C when bit1 is set.
Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
---
drivers/watchdog/aspeed_wdt.c | 34 ++++++++++++++++++++++++++++++----
1 file changed, 30 insertions(+), 4 deletions(-)
diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
index b4773a6aaf8c..c3c8098c035d 100644
--- a/drivers/watchdog/aspeed_wdt.c
+++ b/drivers/watchdog/aspeed_wdt.c
@@ -11,10 +11,12 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/kstrtox.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/watchdog.h>
static bool nowayout = WATCHDOG_NOWAYOUT;
@@ -82,6 +84,13 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
#define WDT_RESET_MASK1 0x1c
#define WDT_RESET_MASK2 0x20
+/*
+ * Ast2600 SCU74 bit1 is External reset flag
+ * Ast2500 SCU3C bit1 is External reset flag
+ */
+#define AST2500_SYSTEM_RESET_EVENT 0x3C
+#define AST2600_SYSTEM_RESET_EVENT 0x74
+#define EXTERN_RESET_FLAG BIT(1)
/*
* WDT_RESET_WIDTH controls the characteristics of the external pulse (if
* enabled), specifically:
@@ -330,6 +339,11 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
if (IS_ERR(wdt->base))
return PTR_ERR(wdt->base);
+ struct regmap *scu_base = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "aspeed,scu");
+ if (IS_ERR(scu_base))
+ return PTR_ERR(scu_base);
+
wdt->wdd.info = &aspeed_wdt_info;
if (wdt->cfg->irq_mask) {
@@ -459,14 +473,26 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
}
status = readl(wdt->base + WDT_TIMEOUT_STATUS);
- if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
+ if (status & WDT_TIMEOUT_STATUS_EVENT)
wdt->wdd.bootstatus = WDIOF_CARDRESET;
- if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
- of_device_is_compatible(np, "aspeed,ast2500-wdt"))
- wdt->wdd.groups = bswitch_groups;
+ if (of_device_is_compatible(np, "aspeed,ast2600-wdt")) {
+ ret = regmap_read(scu_base,
+ AST2600_SYSTEM_RESET_EVENT,
+ &status);
+ } else {
+ ret = regmap_read(scu_base,
+ AST2500_SYSTEM_RESET_EVENT,
+ &status);
+ wdt->wdd.groups = bswitch_groups;
}
+ /*
+ * Reset cause by Extern Reset
+ */
+ if (status & EXTERN_RESET_FLAG && !ret)
+ wdt->wdd.bootstatus |= WDIOF_EXTERN1;
+
dev_set_drvdata(dev, wdt);
return devm_watchdog_register_device(dev, &wdt->wdd);
--
2.25.1
^ permalink raw reply related
* [PATCH v5 3/4] dt-bindings: watchdog: aspeed-wdt: Add aspeed,scu
From: Peter Yin @ 2024-03-28 1:33 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240328013303.3609385-1-peteryin.openbmc@gmail.com>
To use the SCU register to obtain reset flags for supporting
bootstatus.
Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
---
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
index 3208adb3e52e..80a1f58b5a2e 100644
--- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
@@ -8,6 +8,8 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped
region
+ - aspeed,scu: a reference to the System Control Unit node of the Aspeed
+ SOC.
Optional properties:
@@ -62,6 +64,7 @@ Examples:
reg = <0x1e785000 0x1c>;
aspeed,reset-type = "system";
aspeed,external-signal;
+ aspeed,scu = <&syscon>;
};
#include <dt-bindings/watchdog/aspeed-wdt.h>
@@ -70,4 +73,5 @@ Examples:
reg = <0x1e785040 0x40>;
aspeed,reset-mask = <AST2600_WDT_RESET1_DEFAULT
(AST2600_WDT_RESET2_DEFAULT & ~AST2600_WDT_RESET2_LPC)>;
+ aspeed,scu = <&syscon>;
};
--
2.25.1
^ permalink raw reply related
* [PATCH v5 2/4] ARM: dts: aspeed: Add the AST2600 WDT with SCU register
From: Peter Yin @ 2024-03-28 1:33 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240328013303.3609385-1-peteryin.openbmc@gmail.com>
The AST2600 Watchdog Timer (WDT) references
the System Control Unit (SCU) register for its operation.
Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
---
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
index ead835fca657..b47850f0dca0 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
@@ -557,23 +557,27 @@ uart5: serial@1e784000 {
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785000 0x40>;
+ aspeed,scu = <&syscon>;
};
wdt2: watchdog@1e785040 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785040 0x40>;
+ aspeed,scu = <&syscon>;
status = "disabled";
};
wdt3: watchdog@1e785080 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e785080 0x40>;
+ aspeed,scu = <&syscon>;
status = "disabled";
};
wdt4: watchdog@1e7850c0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
+ aspeed,scu = <&syscon>;
status = "disabled";
};
--
2.25.1
^ permalink raw reply related
* [PATCH v5 1/4] ARM: dts: aspeed: Add the AST2500 WDT with SCU register
From: Peter Yin @ 2024-03-28 1:32 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240328013303.3609385-1-peteryin.openbmc@gmail.com>
The AST2500 WDT references the System Control Unit
register for its operation.
Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
---
arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi
index 04f98d1dbb97..5fd12c057c31 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi
@@ -410,12 +410,14 @@ wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785000 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
+ aspeed,scu = <&syscon>;
};
wdt2: watchdog@1e785020 {
compatible = "aspeed,ast2500-wdt";
reg = <0x1e785020 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
+ aspeed,scu = <&syscon>;
};
wdt3: watchdog@1e785040 {
@@ -423,6 +425,7 @@ wdt3: watchdog@1e785040 {
reg = <0x1e785040 0x20>;
clocks = <&syscon ASPEED_CLK_APB>;
status = "disabled";
+ aspeed,scu = <&syscon>;
};
pwm_tacho: pwm-tacho-controller@1e786000 {
--
2.25.1
^ permalink raw reply related
* [PATCH v5 0/4] drivers: watchdog: ast2500 and ast2600 support bootstatus
From: Peter Yin @ 2024-03-28 1:32 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2500/ast2600
Regarding the AST2600 specification, the WDTn Timeout Status Register
(WDT10) has bit 1 reserved. Bit 1 of the status register indicates
on ast2500 if the boot was from the second boot source.
It does not indicate that the most recent reset was triggered by
the watchdog. The code should just be changed to set WDIOF_CARDRESET
if bit 0 of the status register is set.
Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or
ast2500 SCU3C when bit1 is set.
v4 -> v5
- Revert indentation.
v3 -> v4
- Add error handling for syscon_regmap_lookup_by_phandle and
regmap_read.
v2 -> v3
- Fixed WDIOF_CARDRESET status bit check and added support
for WDIOF_EXTERN1 on ast2500 and ast2600.
v1 -> v2
- Add comment and support WDIOF_CARDRESET in ast2600
v1
- Patch 0001 - Add WDIOF_EXTERN1 bootstatus
---
Peter Yin (4):
ARM: dts: aspeed: Add the AST2500 WDT with SCU register
ARM: dts: aspeed: Add the AST2600 WDT with SCU register
dt-bindings: watchdog: aspeed-wdt: Add aspeed,scu
drivers: watchdog: ast2500 and ast2600 support bootstatus
.../bindings/watchdog/aspeed-wdt.txt | 4 +++
arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 3 ++
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 +++
drivers/watchdog/aspeed_wdt.c | 34 ++++++++++++++++---
4 files changed, 41 insertions(+), 4 deletions(-)
--
2.25.1
^ permalink raw reply
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