* Re: [PATCH v5 1/1] dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk
From: Christophe ROULLIER @ 2024-03-28 15:07 UTC (permalink / raw)
To: Marek Vasut, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue, Richard Cochran, Jose Abreu,
Liam Girdwood, Mark Brown
Cc: netdev, devicetree, linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <480d4064-b553-4005-ad98-499a862703ff@denx.de>
On 3/28/24 15:19, Marek Vasut wrote:
> On 3/28/24 3:08 PM, Christophe Roullier wrote:
>
> [...]
>
>> | RMII | - | eth-ck | eth-ck | n/a |
>> | | | st,ext-phyclk | st,eth-ref-clk-sel
>> | |
>> | | | | or st,ext-phyclk
>> | |
>>
>> ---------------------------------------------------------------------------
>>
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
>> ---
>> Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>> b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>> index fc8c96b08d7dc..b35eae80ed6ac 100644
>> --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>> +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>> @@ -82,6 +82,13 @@ properties:
>> Should be phandle/offset pair. The phandle to the syscon node
>> which
>> encompases the glue register, and the offset of the control
>> register
>> +st,ext-phyclk:
>
> Don't you need two spaces in front of the 'st,' here ?
Sorry, that's right.
>
>> + description:
>> + set this property in RMII mode when you have PHY without
>> crystal 50MHz and want to
>> + select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when
>> you want to select
>> + RCC clock instead of ETH_CLK125.
>> + type: boolean
>> +
>
> With that fixed:
>
> Reviewed-by: Marek Vasut <marex@denx.de>
^ permalink raw reply
* Re: [PATCH 1/1] arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif[0,1] and sai[4,5]
From: Frank Li @ 2024-03-28 14:57 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
In-Reply-To: <ZgV6a7ZMwM4aR7f+@dragon>
On Thu, Mar 28, 2024 at 10:10:51PM +0800, Shawn Guo wrote:
> On Mon, Feb 26, 2024 at 02:21:29PM -0500, Frank Li wrote:
> > Add asrc[0,1], esai0, spdif[0,1], sai[4,5] and related lpcg node for
> > imx8 audio subsystem.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > .../boot/dts/freescale/imx8-ss-audio.dtsi | 306 ++++++++++++++++++
> > 1 file changed, 306 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> > index 07afeb78ed564..6d78d6c0d9002 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> > @@ -6,6 +6,7 @@
> >
> > #include <dt-bindings/clock/imx8-clock.h>
> > #include <dt-bindings/clock/imx8-lpcg.h>
> > +#include <dt-bindings/dma/fsl-edma.h>
> > #include <dt-bindings/firmware/imx/rsrc.h>
> >
> > audio_ipg_clk: clock-audio-ipg {
> > @@ -481,4 +482,309 @@ acm: acm@59e00000 {
> > "sai3_rx_bclk",
> > "sai4_rx_bclk";
> > };
> > +
> > + asrc0: asrc@59000000 {
>
> We want to sort nodes in unit-address, right?
Actually it is fixed at v2. I just send out v8, which include extra space
fix and wrong clock index fixes.
https://lore.kernel.org/imx/20240328-asrc_8qxp-v8-0-801cd6bb5be2@nxp.com/T/#t
Also need below patches to make board level audio work.
https://lore.kernel.org/imx/20240305-m4_lpuart-v3-0-592463ef1d22@nxp.com/
Frank
>
> > + compatible = "fsl,imx8qm-asrc";
> > + reg = <0x59000000 0x10000>;
> > + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&asrc0_lpcg 0>,
> > + <&asrc0_lpcg 0>,
> > + <&aud_pll_div0_lpcg 0>,
> > + <&aud_pll_div1_lpcg 0>,
> > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
> > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>;
> > + clock-names = "ipg", "mem",
> > + "asrck_0", "asrck_1", "asrck_2", "asrck_3",
> > + "asrck_4", "asrck_5", "asrck_6", "asrck_7",
> > + "asrck_8", "asrck_9", "asrck_a", "asrck_b",
> > + "asrck_c", "asrck_d", "asrck_e", "asrck_f",
> > + "spba";
> > + dmas = <&edma0 0 0 0>,
> > + <&edma0 1 0 0>,
> > + <&edma0 2 0 0>,
> > + <&edma0 3 0 FSL_EDMA_RX>,
> > + <&edma0 4 0 FSL_EDMA_RX>,
> > + <&edma0 5 0 FSL_EDMA_RX>;
> > + /* tx* is output channel of asrc, it is rx channel for eDMA */
> > + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
> > + fsl,asrc-rate = <8000>;
>
> One space around =
>
> > + fsl,asrc-width = <16>;
> > + fsl,asrc-clk-map = <0>;
> > + power-domains = <&pd IMX_SC_R_ASRC_0>;
> > + status = "disabled";
> > + };
> > +
> > + esai0: esai@59010000 {
> > + compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai";
> > + reg = <0x59010000 0x10000>;
> > + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&clk_dummy>;
> > + clock-names = "core", "extal", "fsys", "spba";
> > + dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>;
> > + dma-names = "rx", "tx";
> > + power-domains = <&pd IMX_SC_R_ESAI_0>;
> > + status = "disabled";
> > + };
> > +
> > + spdif0: spdif@59020000 {
> > + compatible = "fsl,imx8qm-spdif";
> > + reg = <0x59020000 0x10000>;
> > + interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
>
> Ditto
>
> > + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
> > + clocks = <&spdif0_lpcg 1>, /* core */
> > + <&clk_dummy>, /* rxtx0 */
> > + <&spdif0_lpcg 0>, /* rxtx1 */
> > + <&clk_dummy>, /* rxtx2 */
> > + <&clk_dummy>, /* rxtx3 */
> > + <&clk_dummy>, /* rxtx4 */
> > + <&audio_ipg_clk>, /* rxtx5 */
> > + <&clk_dummy>, /* rxtx6 */
> > + <&clk_dummy>, /* rxtx7 */
> > + <&clk_dummy>; /* spba */
> > + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
> > + "rxtx5", "rxtx6", "rxtx7", "spba";
> > + dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
> > + <&edma0 9 0 FSL_EDMA_MULTI_FIFO>;
> > + dma-names = "rx", "tx";
> > + power-domains = <&pd IMX_SC_R_SPDIF_0>;
> > + status = "disabled";
> > + };
> > +
> > + spdif1: spdif@59030000 {
> > + compatible = "fsl,imx8qm-spdif";
> > + reg = <0x59030000 0x10000>;
> > + interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */
>
> Ditto
>
> Shawn
>
> > + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */
> > + clocks = <&spdif1_lpcg 1>, /* core */
> > + <&clk_dummy>, /* rxtx0 */
> > + <&spdif1_lpcg 0>, /* rxtx1 */
> > + <&clk_dummy>, /* rxtx2 */
> > + <&clk_dummy>, /* rxtx3 */
> > + <&clk_dummy>, /* rxtx4 */
> > + <&audio_ipg_clk>, /* rxtx5 */
> > + <&clk_dummy>, /* rxtx6 */
> > + <&clk_dummy>, /* rxtx7 */
> > + <&clk_dummy>; /* spba */
> > + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
> > + "rxtx5", "rxtx6", "rxtx7", "spba";
> > + dmas = <&edma0 10 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
> > + <&edma0 11 0 FSL_EDMA_MULTI_FIFO>;
> > + dma-names = "rx", "tx";
> > + power-domains = <&pd IMX_SC_R_SPDIF_1>;
> > + status = "disabled";
> > + };
> > +
> > + asrc1: asrc@59800000 {
> > + compatible = "fsl,imx8qm-asrc";
> > + reg = <0x59800000 0x10000>;
> > + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&asrc1_lpcg 0>,
> > + <&asrc1_lpcg 0>,
> > + <&aud_pll_div0_lpcg 0>,
> > + <&aud_pll_div1_lpcg 0>,
> > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
> > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>,
> > + <&clk_dummy>;
> > + clock-names = "ipg", "mem",
> > + "asrck_0", "asrck_1", "asrck_2", "asrck_3",
> > + "asrck_4", "asrck_5", "asrck_6", "asrck_7",
> > + "asrck_8", "asrck_9", "asrck_a", "asrck_b",
> > + "asrck_c", "asrck_d", "asrck_e", "asrck_f",
> > + "spba";
> > + dmas = <&edma1 0 0 0>,
> > + <&edma1 1 0 0>,
> > + <&edma1 2 0 0>,
> > + <&edma1 3 0 FSL_EDMA_RX>,
> > + <&edma1 4 0 FSL_EDMA_RX>,
> > + <&edma1 5 0 FSL_EDMA_RX>;
> > + /* tx* is output channel of asrc, it is rx channel for eDMA */
> > + dma-names = "txa", "txb", "txc", "rxa", "rxb", "rxc";
> > + fsl,asrc-rate = <8000>;
> > + fsl,asrc-width = <16>;
> > + fsl,asrc-clk-map = <1>;
> > + power-domains = <&pd IMX_SC_R_ASRC_1>;
> > + status = "disabled";
> > + };
> > +
> > + sai4: sai@59820000 {
> > + compatible = "fsl,imx8qm-sai";
> > + reg = <0x59820000 0x10000>;
> > + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&sai4_lpcg 1>,
> > + <&clk_dummy>,
> > + <&sai4_lpcg 0>,
> > + <&clk_dummy>,
> > + <&clk_dummy>;
> > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
> > + dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>;
> > + dma-names = "rx", "tx";
> > + power-domains = <&pd IMX_SC_R_SAI_4>;
> > + status = "disabled";
> > + };
> > +
> > + sai5: sai@59830000 {
> > + compatible = "fsl,imx8qm-sai";
> > + reg = <0x59830000 0x10000>;
> > + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&sai5_lpcg 1>,
> > + <&clk_dummy>,
> > + <&sai5_lpcg 0>,
> > + <&clk_dummy>,
> > + <&clk_dummy>;
> > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
> > + dmas = <&edma1 10 0 0>;
> > + dma-names = "tx";
> > + power-domains = <&pd IMX_SC_R_SAI_5>;
> > + status = "disabled";
> > + };
> > +
> > + amix: amix@59840000 {
> > + compatible = "fsl,imx8qm-audmix";
> > + reg = <0x59840000 0x10000>;
> > + clocks = <&amix_lpcg 0>;
> > + clock-names = "ipg";
> > + power-domains = <&pd IMX_SC_R_AMIX>;
> > + dais = <&sai4>, <&sai5>;
> > + status = "disabled";
> > + };
> > +
> > + mqs: mqs@59850000 {
> > + compatible = "fsl,imx8qm-mqs";
> > + reg = <0x59850000 0x10000>;
> > + clocks = <&mqs0_lpcg 1>,
> > + <&mqs0_lpcg 0>;
> > + clock-names = "core", "mclk";
> > + power-domains = <&pd IMX_SC_R_MQS_0>;
> > + status = "disabled";
> > + };
> > +
> > + asrc0_lpcg: clock-controller@59400000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x59400000 0x10000>;
> > + #clock-cells = <1>;
> > + clocks = <&audio_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_4>;
> > + clock-output-names = "asrc0_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_ASRC_0>;
> > + };
> > +
> > + esai0_lpcg: clock-controller@59410000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x59410000 0x10000>;
> > + #clock-cells = <1>;
> > + clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
> > + <&audio_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > + clock-output-names = "esai0_lpcg_extal_clk",
> > + "esai0_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_ESAI_0>;
> > + };
> > +
> > + spdif0_lpcg: clock-controller@59420000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x59420000 0x10000>;
> > + #clock-cells = <1>;
> > + clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>,
> > + <&audio_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > + clock-output-names = "spdif0_lpcg_tx_clk",
> > + "spdif0_lpcg_gclkw";
> > + power-domains = <&pd IMX_SC_R_SPDIF_0>;
> > + };
> > +
> > + spdif1_lpcg: clock-controller@59430000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x59430000 0x10000>;
> > + #clock-cells = <1>;
> > + clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>,
> > + <&audio_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > + clock-output-names = "spdif1_lpcg_tx_clk",
> > + "spdif1_lpcg_gclkw";
> > + power-domains = <&pd IMX_SC_R_SPDIF_1>;
> > + status = "disabled";
> > + };
> > +
> > + asrc1_lpcg: clock-controller@59c00000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x59c00000 0x10000>;
> > + #clock-cells = <1>;
> > + clocks = <&audio_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_4>;
> > + clock-output-names = "asrc1_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_ASRC_1>;
> > + };
> > +
> > + sai4_lpcg: clock-controller@59c20000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x59c20000 0x10000>;
> > + #clock-cells = <1>;
> > + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
> > + <&audio_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > + clock-output-names = "sai4_lpcg_mclk",
> > + "sai4_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_SAI_4>;
> > + };
> > +
> > + sai5_lpcg: clock-controller@59c30000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x59c30000 0x10000>;
> > + #clock-cells = <1>;
> > + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
> > + <&audio_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > + clock-output-names = "sai5_lpcg_mclk",
> > + "sai5_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_SAI_5>;
> > + };
> > +
> > + amix_lpcg: clock-controller@59c40000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x59c40000 0x10000>;
> > + #clock-cells = <1>;
> > + clocks = <&audio_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>;
> > + clock-output-names = "amix_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_AMIX>;
> > + };
> > +
> > + mqs0_lpcg: clock-controller@59c50000 {
> > + compatible = "fsl,imx8qxp-lpcg";
> > + reg = <0x59c50000 0x10000>;
> > + #clock-cells = <1>;
> > + clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>,
> > + <&audio_ipg_clk>;
> > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > + clock-output-names = "mqs0_lpcg_mclk",
> > + "mqs0_lpcg_ipg_clk";
> > + power-domains = <&pd IMX_SC_R_MQS_0>;
> > + };
> > };
> > --
> > 2.34.1
> >
>
^ permalink raw reply
* [PATCH] arm64: dts: qcom: Add support for Samsung Galaxy Z Fold5
From: Alexandru Marc Serdeliuc via B4 Relay @ 2024-03-28 14:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Alexandru Marc Serdeliuc
From: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
Add support for Samsung Galaxy Z Fold5 (q5q) foldable phone
Currently working features:
- Framebuffer
- UFS
- i2c
- Buttons
Signed-off-by: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 616 ++++++++++++++++++++++++
2 files changed, 617 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 7d40ec5e7d21..a7503fd35b6c 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -241,6 +241,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8550-samsung-q5q.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
new file mode 100644
index 000000000000..ac8392022a7f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
@@ -0,0 +1,616 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
+ * Copyright (c) 2024, David Wronek <david@mainlining.org>
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/ {
+ model = "Samsung Galaxy Z Fold5";
+ compatible = "samsung,q5q", "qcom,sm8550";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ bootargs = "console=tty0 clk_ignore_unused pd_ignore_unused";
+
+ framebuffer: framebuffer@b8000000 {
+ compatible = "simple-framebuffer";
+ reg = <0x0 0xb8000000 0x0 0x2b00000>;
+ width = <2176>;
+ height = <1812>;
+ stride = <(2176 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reserved-memory {
+ chipinfo_region@81cf4000 {
+ reg = <0x0 0x81cf4000 0x0 0x1000>;
+ no-map;
+ };
+
+ kaslr_region@b01ff000 {
+ reg = <0x0 0xb01ff000 0x0 0x1000>;
+ no-map;
+ };
+
+ uh_guest_region {
+ reg = <0x0 0xb1000000 0x0 0x3000000>;
+ no-map;
+ };
+
+ uh_heap_region {
+ reg = <0x0 0xb0200000 0x0 0x40000>;
+ no-map;
+ };
+
+/*
+ * The bootloader will only keep display hardware enabled
+ * if this memory region is named exactly 'splash_region'
+ */
+ splash_region {
+ reg = <0x0 0xb8000000 0x0 0x2b00000>;
+ no-map;
+ };
+ }; // end reserved-memory
+}; // end /
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ }; // end regulators-0
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vreg_l3c_0p91: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ }; // end regulators-1
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ }; // end regulators-2
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vreg_s4e_0p9: smps4 {
+ regulator-name = "vreg_s4e_0p9";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p1: smps5 {
+ regulator-name = "vreg_s5e_1p1";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ }; // end regulators-3
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p91: ldo3 {
+ regulator-name = "vreg_l3f_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ }; // end regulators-4
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vreg_s1g_1p2: smps1 {
+ regulator-name = "vreg_s1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p8: smps2 {
+ regulator-name = "vreg_s2g_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p7: smps3 {
+ regulator-name = "vreg_s3g_0p7";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p3: smps4 {
+ regulator-name = "vreg_s4g_1p3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p8: smps5 {
+ regulator-name = "vreg_s5g_0p8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p8: smps6 {
+ regulator-name = "vreg_s6g_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2g_1p2: ldo2 {
+ regulator-name = "vreg_l2g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ }; // end regulators-5
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vreg_l1m_1p056: ldo1 {
+ regulator-name = "vreg_l1m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_1p8: ldo6 {
+ regulator-name = "vreg_l6m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p9: ldo7 {
+ regulator-name = "vreg_l7m_2p9";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ }; // end regulators-6
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "n";
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p1: ldo2 {
+ regulator-name = "vreg_l2n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_2p8: ldo3 {
+ regulator-name = "vreg_l3n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_2p8: ldo4 {
+ regulator-name = "vreg_l4n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_1p8: ldo5 {
+ regulator-name = "vreg_l5n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_3p3: ldo6 {
+ regulator-name = "vreg_l6n_3p3";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_2p96: ldo7 {
+ regulator-name = "vreg_l7n_2p96";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ }; // end regulators-7
+}; // end apps_rsc
+
+&gpu {
+ status = "disabled";
+ zap-shader {
+ firmware-name = "qcom/sm8550/a740_zap.mbn";
+ };
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&mdss {
+ status = "disabled";
+};
+
+&pcie_1_phy_aux_clk {
+ clock-frequency = <1000>;
+};
+
+&pcie0 {
+ status = "okay";
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
+};
+
+&pcie0_phy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+};
+
+&pcie1 {
+ status = "okay";
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3c_0p91>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ status = "okay";
+ firmware-name = "qcom/sm8550/adsp.mbn",
+ "qcom/sm8550/adsp_dtb.mbn";
+};
+
+&remoteproc_cdsp {
+ status = "okay";
+ firmware-name = "qcom/sm8550/cdsp.mbn",
+ "qcom/sm8550/cdsp_dtb.mbn";
+};
+
+&remoteproc_mpss {
+ status = "okay";
+ firmware-name = "qcom/sm8550/modem.mbn",
+ "qcom/sm8550/modem_dtb.mbn";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <36 4>, <50 2>;
+};
+
+&ufs_mem_hc {
+ status = "okay";
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+};
+
+&ufs_mem_phy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
+
+&dispcc {
+ status = "disabled";
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEDOWN>;
+};
---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240328-arm64-dts-add-support-for-samsung-galaxy-zfold5-3ae7f1cd0cf4
Best regards,
--
Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
^ permalink raw reply related
* [PATCH v8 5/5] arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]
From: Frank Li @ 2024-03-28 14:51 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shengjiu Wang
Cc: linux-sound, devicetree, imx, linux-arm-kernel, linux-kernel,
Frank Li
In-Reply-To: <20240328-asrc_8qxp-v8-0-801cd6bb5be2@nxp.com>
Add asrc[0,1], esai0, spdif0, sai[4,5] and related lpcg node for
imx8 audio subsystem.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 269 +++++++++++++++++++++++
1 file changed, 269 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
index d8bbe53320bce..897cbb7b67422 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/clock/imx8-lpcg.h>
+#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/firmware/imx/rsrc.h>
audio_ipg_clk: clock-audio-ipg {
@@ -119,6 +120,89 @@ audio_subsys: bus@59000000 {
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x1000000>;
+ asrc0: asrc@59000000 {
+ compatible = "fsl,imx8qm-asrc";
+ reg = <0x59000000 0x10000>;
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>,
+ <&asrc0_lpcg IMX_LPCG_CLK_0>,
+ <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>,
+ <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>,
+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "mem", "ipg",
+ "asrck_0", "asrck_1", "asrck_2", "asrck_3",
+ "asrck_4", "asrck_5", "asrck_6", "asrck_7",
+ "asrck_8", "asrck_9", "asrck_a", "asrck_b",
+ "asrck_c", "asrck_d", "asrck_e", "asrck_f",
+ "spba";
+ dmas = <&edma0 0 0 0>,
+ <&edma0 1 0 0>,
+ <&edma0 2 0 0>,
+ <&edma0 3 0 FSL_EDMA_RX>,
+ <&edma0 4 0 FSL_EDMA_RX>,
+ <&edma0 5 0 FSL_EDMA_RX>;
+ /* tx* is output channel of asrc, it is rx channel for eDMA */
+ dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
+ fsl,asrc-rate = <8000>;
+ fsl,asrc-width = <16>;
+ fsl,asrc-clk-map = <0>;
+ power-domains = <&pd IMX_SC_R_ASRC_0>;
+ status = "disabled";
+ };
+
+ esai0: esai@59010000 {
+ compatible = "fsl,imx8qm-esai";
+ reg = <0x59010000 0x10000>;
+ interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&esai0_lpcg IMX_LPCG_CLK_4>,
+ <&esai0_lpcg IMX_LPCG_CLK_0>,
+ <&esai0_lpcg IMX_LPCG_CLK_4>,
+ <&clk_dummy>;
+ clock-names = "core", "extal", "fsys", "spba";
+ dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd IMX_SC_R_ESAI_0>;
+ status = "disabled";
+ };
+
+ spdif0: spdif@59020000 {
+ compatible = "fsl,imx8qm-spdif";
+ reg = <0x59020000 0x10000>;
+ interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+ clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */
+ <&clk_dummy>, /* rxtx0 */
+ <&spdif0_lpcg IMX_LPCG_CLK_0>, /* rxtx1 */
+ <&clk_dummy>, /* rxtx2 */
+ <&clk_dummy>, /* rxtx3 */
+ <&clk_dummy>, /* rxtx4 */
+ <&audio_ipg_clk>, /* rxtx5 */
+ <&clk_dummy>, /* rxtx6 */
+ <&clk_dummy>, /* rxtx7 */
+ <&clk_dummy>; /* spba */
+ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6", "rxtx7", "spba";
+ dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
+ <&edma0 9 0 FSL_EDMA_MULTI_FIFO>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd IMX_SC_R_SPDIF_0>;
+ status = "disabled";
+ };
+
sai0: sai@59040000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59040000 0x10000>;
@@ -239,6 +323,40 @@ edma0: dma-controller@591f0000 {
<&pd IMX_SC_R_DMA_0_CH23>;
};
+ asrc0_lpcg: clock-controller@59400000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "asrc0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ASRC_0>;
+ };
+
+ esai0_lpcg: clock-controller@59410000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "esai0_lpcg_extal_clk",
+ "esai0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ESAI_0>;
+ };
+
+ spdif0_lpcg: clock-controller@59420000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59420000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spdif0_lpcg_tx_clk",
+ "spdif0_lpcg_gclkw";
+ power-domains = <&pd IMX_SC_R_SPDIF_0>;
+ };
+
sai0_lpcg: clock-controller@59440000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59440000 0x10000>;
@@ -333,6 +451,101 @@ dsp: dsp@596e8000 {
status = "disabled";
};
+ asrc1: asrc@59800000 {
+ compatible = "fsl,imx8qm-asrc";
+ reg = <0x59800000 0x10000>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&asrc1_lpcg IMX_LPCG_CLK_4>,
+ <&asrc1_lpcg IMX_LPCG_CLK_4>,
+ <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
+ <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "mem", "ipg",
+ "asrck_0", "asrck_1", "asrck_2", "asrck_3",
+ "asrck_4", "asrck_5", "asrck_6", "asrck_7",
+ "asrck_8", "asrck_9", "asrck_a", "asrck_b",
+ "asrck_c", "asrck_d", "asrck_e", "asrck_f",
+ "spba";
+ dmas = <&edma1 0 0 0>,
+ <&edma1 1 0 0>,
+ <&edma1 2 0 0>,
+ <&edma1 3 0 FSL_EDMA_RX>,
+ <&edma1 4 0 FSL_EDMA_RX>,
+ <&edma1 5 0 FSL_EDMA_RX>;
+ /* tx* is output channel of asrc, it is rx channel for eDMA */
+ dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
+ fsl,asrc-rate = <8000>;
+ fsl,asrc-width = <16>;
+ fsl,asrc-clk-map = <1>;
+ power-domains = <&pd IMX_SC_R_ASRC_1>;
+ status = "disabled";
+ };
+
+ sai4: sai@59820000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59820000 0x10000>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai4_lpcg IMX_LPCG_CLK_4>,
+ <&clk_dummy>,
+ <&sai4_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd IMX_SC_R_SAI_4>;
+ status = "disabled";
+ };
+
+ sai5: sai@59830000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59830000 0x10000>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai5_lpcg IMX_LPCG_CLK_4>,
+ <&clk_dummy>,
+ <&sai5_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&edma1 10 0 0>;
+ dma-names = "tx";
+ power-domains = <&pd IMX_SC_R_SAI_5>;
+ status = "disabled";
+ };
+
+ amix: amix@59840000 {
+ compatible = "fsl,imx8qm-audmix";
+ reg = <0x59840000 0x10000>;
+ clocks = <&amix_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_AMIX>;
+ dais = <&sai4>, <&sai5>;
+ status = "disabled";
+ };
+
+ mqs: mqs@59850000 {
+ compatible = "fsl,imx8qm-mqs";
+ reg = <0x59850000 0x10000>;
+ clocks = <&mqs0_lpcg IMX_LPCG_CLK_4>, <&mqs0_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "mclk", "core";
+ power-domains = <&pd IMX_SC_R_MQS_0>;
+ status = "disabled";
+ };
+
edma1: dma-controller@599f0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x599f0000 0xc0000>;
@@ -481,4 +694,60 @@ acm: acm@59e00000 {
"sai3_rx_bclk",
"sai4_rx_bclk";
};
+
+ asrc1_lpcg: clock-controller@59c00000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c00000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "asrc1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ASRC_1>;
+ };
+
+ sai4_lpcg: clock-controller@59c20000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "sai4_lpcg_mclk",
+ "sai4_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_4>;
+ };
+
+ sai5_lpcg: clock-controller@59c30000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "sai5_lpcg_mclk",
+ "sai5_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_5>;
+ };
+
+ amix_lpcg: clock-controller@59c40000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c40000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "amix_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_AMIX>;
+ };
+
+ mqs0_lpcg: clock-controller@59c50000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c50000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "mqs0_lpcg_mclk",
+ "mqs0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MQS_0>;
+ };
};
--
2.34.1
^ permalink raw reply related
* [PATCH v8 4/5] arm64: dts: imx8: fix audio lpcg index
From: Frank Li @ 2024-03-28 14:51 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shengjiu Wang
Cc: linux-sound, devicetree, imx, linux-arm-kernel, linux-kernel,
Frank Li
In-Reply-To: <20240328-asrc_8qxp-v8-0-801cd6bb5be2@nxp.com>
lpcg cell0 should be clock's 'indices' instead of 'index'.
imx_lpcg_of_clk_src_get(struct of_phandle_args *clkspec, void *data)
{
struct clk_hw_onecell_data *hw_data = data;
unsigned int idx = clkspec->args[0] / 4;
....
}
<@sai0_lpcg 1> will be the same as <@sai_lpcg 0>.
Replace 0 with IMX_LPCG_CLK_0 and replace 1 with IMX_LPCG_CLK_4.
It can work at iMX8QXP because IMX_LPCG_CLK_4 is ipg clock, which already
enabled. But for iMX8QM IMX_LPCG_CLK_4 is mclk, which trigger issue.
Fixes: 0a9279e9ae88 ("arm64: dts: imx8qxp: Add audio SAI nodes")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
index 07afeb78ed564..d8bbe53320bce 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
@@ -123,9 +123,9 @@ sai0: sai@59040000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59040000 0x10000>;
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sai0_lpcg 1>,
+ clocks = <&sai0_lpcg IMX_LPCG_CLK_4>,
<&clk_dummy>,
- <&sai0_lpcg 0>,
+ <&sai0_lpcg IMX_LPCG_CLK_0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
@@ -139,9 +139,9 @@ sai1: sai@59050000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59050000 0x10000>;
interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sai1_lpcg 1>,
+ clocks = <&sai1_lpcg IMX_LPCG_CLK_4>,
<&clk_dummy>,
- <&sai1_lpcg 0>,
+ <&sai1_lpcg IMX_LPCG_CLK_0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
@@ -155,9 +155,9 @@ sai2: sai@59060000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59060000 0x10000>;
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sai2_lpcg 1>,
+ clocks = <&sai2_lpcg IMX_LPCG_CLK_4>,
<&clk_dummy>,
- <&sai2_lpcg 0>,
+ <&sai2_lpcg IMX_LPCG_CLK_0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
@@ -171,9 +171,9 @@ sai3: sai@59070000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59070000 0x10000>;
interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sai3_lpcg 1>,
+ clocks = <&sai3_lpcg IMX_LPCG_CLK_4>,
<&clk_dummy>,
- <&sai3_lpcg 0>,
+ <&sai3_lpcg IMX_LPCG_CLK_0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
--
2.34.1
^ permalink raw reply related
* [PATCH v8 3/5] ASoC: dt-bindings: fsl-sai: allow only one dma-names
From: Frank Li @ 2024-03-28 14:51 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shengjiu Wang
Cc: linux-sound, devicetree, imx, linux-arm-kernel, linux-kernel,
Frank Li
In-Reply-To: <20240328-asrc_8qxp-v8-0-801cd6bb5be2@nxp.com>
Some sai only connect one direction dma (rx/tx) in SOC. For example:
imx8qxp sai5 only connect tx dma channel. So allow only one "rx" or "tx"
for dma-names.
Remove description under dmas because no user use index to get dma channel.
All user use 'dma-names' to get correct dma channel. dma-names already in
'required' list.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Documentation/devicetree/bindings/sound/fsl,sai.yaml | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl,sai.yaml b/Documentation/devicetree/bindings/sound/fsl,sai.yaml
index 2456d958adeef..a5d9c246cc476 100644
--- a/Documentation/devicetree/bindings/sound/fsl,sai.yaml
+++ b/Documentation/devicetree/bindings/sound/fsl,sai.yaml
@@ -81,14 +81,12 @@ properties:
dmas:
minItems: 1
- items:
- - description: DMA controller phandle and request line for RX
- - description: DMA controller phandle and request line for TX
+ maxItems: 2
dma-names:
minItems: 1
items:
- - const: rx
+ - enum: [ rx, tx ]
- const: tx
interrupts:
--
2.34.1
^ permalink raw reply related
* [PATCH v8 2/5] ASoC: dt-bindings: fsl,imx-asrc: update max interrupt numbers
From: Frank Li @ 2024-03-28 14:51 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shengjiu Wang
Cc: linux-sound, devicetree, imx, linux-arm-kernel, linux-kernel,
Frank Li
In-Reply-To: <20240328-asrc_8qxp-v8-0-801cd6bb5be2@nxp.com>
fsl,imx8qxp-spdif and fsl,imx8qm-spdif have 2 interrupts. Other platforms
have 1 interrupt.
Increase max interrupt number to 2 and add restriction for platforms except
i.MX8QXP and i.MX8QM.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../devicetree/bindings/sound/fsl,spdif.yaml | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml
index 56f8c0c8afdea..204f361cea27a 100644
--- a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml
@@ -31,7 +31,10 @@ properties:
maxItems: 1
interrupts:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: Combined or receive interrupt
+ - description: Transmit interrupt
dmas:
items:
@@ -101,6 +104,21 @@ required:
additionalProperties: false
allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-spdif
+ - fsl,imx8qxp-spdif
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
- if:
properties:
compatible:
--
2.34.1
^ permalink raw reply related
* [PATCH v8 1/5] ASoC: dt-bindings: fsl,imx-asrc/spdif: Add power-domains property
From: Frank Li @ 2024-03-28 14:51 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shengjiu Wang
Cc: linux-sound, devicetree, imx, linux-arm-kernel, linux-kernel,
Frank Li, Conor Dooley
In-Reply-To: <20240328-asrc_8qxp-v8-0-801cd6bb5be2@nxp.com>
Add power-domains property for asrc and spdif since fsl,imx8qm-asrc/spdif
and fsl,imx8qxp-asrc/spdif require 'power-domains'.
Set 'power-domains' as required property for compatible string
fsl,imx8qm-asrc/spdif and fsl,imx8qxp-asrc/spdif.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml | 14 ++++++++++++++
Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 15 +++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml
index bfef2fcb75b14..76aa1f2484883 100644
--- a/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml
+++ b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml
@@ -74,6 +74,9 @@ properties:
- const: asrck_f
- const: spba
+ power-domains:
+ maxItems: 1
+
fsl,asrc-rate:
$ref: /schemas/types.yaml#/definitions/uint32
description: The mutual sample rate used by DPCM Back Ends
@@ -131,6 +134,17 @@ allOf:
properties:
fsl,asrc-clk-map: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qm-asrc
+ - fsl,imx8qxp-asrc
+ then:
+ required:
+ - power-domains
+
additionalProperties: false
examples:
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml
index 1d64e8337aa4b..56f8c0c8afdea 100644
--- a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml
@@ -86,6 +86,9 @@ properties:
registers. Set this flag for HCDs with big endian descriptors and big
endian registers.
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -97,6 +100,18 @@ required:
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qm-spdif
+ - fsl,imx8qxp-spdif
+ then:
+ required:
+ - power-domains
+
examples:
- |
spdif@2004000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v8 0/5] arm64: dts: imx8qxp add asrc and sai
From: Frank Li @ 2024-03-28 14:51 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shengjiu Wang
Cc: linux-sound, devicetree, imx, linux-arm-kernel, linux-kernel,
Frank Li, Conor Dooley
Update binding doc to avoid warning.
Change from v1 to v2
- Fixed dts DTB_CHECK warning
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Changes in v8:
binding:
- Add rob's review tag
dts:
- Add fixed patch to fix sai0 lpcg index
- Update other node lpcg index
- Remove extra space after =
- Link to v7: https://lore.kernel.org/r/20240318-asrc_8qxp-v7-0-01ce5264a761@nxp.com
Changes in v7:
- Using rob method for dma-names
- Drop conor acked tag form dma-names and interrupt patches
- Fixed warning for interrupts
- Pass dt_bindng check
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,sai.yaml
LINT Documentation/devicetree/bindings
DTEX Documentation/devicetree/bindings/sound/fsl,sai.example.dts
CHKDT Documentation/devicetree/bindings/processed-schema.json
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC_CHK Documentation/devicetree/bindings/sound/fsl,sai.example.dtb
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,spdif.yaml
LINT Documentation/devicetree/bindings
DTEX Documentation/devicetree/bindings/sound/fsl,spdif.example.dts
CHKDT Documentation/devicetree/bindings/processed-schema.json
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC_CHK Documentation/devicetree/bindings/sound/fsl,spdif.example.dtb
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,imx-asrc.yaml
LINT Documentation/devicetree/bindings
DTEX Documentation/devicetree/bindings/sound/fsl,imx-asrc.example.dts
CHKDT Documentation/devicetree/bindings/processed-schema.json
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC_CHK Documentation/devicetree/bindings/sound/fsl,imx-asrc.example.dtb
- Pass DTB_CHECK, below warning exist because binding doc still be txt.
from schema $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
arch/arm64/boot/dts/freescale/imx8dxl-evk.dtb: /bus@59000000/amix@59840000: failed to match any schema with compatible: ['fsl,imx8qm-audmix']
- Link to v6: https://lore.kernel.org/r/20240308-asrc_8qxp-v6-0-e08f6d030e09@nxp.com
Changes in v6:
- Add interrupt description in binding doc according to rob suggestion
- Link to v5: https://lore.kernel.org/r/20240307-asrc_8qxp-v5-0-db363740368d@nxp.com
Changes in v5:
- using rob's suggest logic after fix maxItems.
- sort dts nodes.
- remove spdif1. Add later when do 8qm upstream
- Link to v4: https://lore.kernel.org/r/20240305-asrc_8qxp-v4-0-c61b98046591@nxp.com
Changes in v4:
Combine comments' from v2 and v3. I hope I address everythings.
- Krzysztof's comments
- add reson about why change
- rob's comments
using rob's suggest logic to restrict interrupt number
but for dma-names, still need use oneOf to cover 3 case
- [rx, tx]
- [rx]
- [tx]
oneOf
- items:
- tx
- rx
- enums: [rx, tx]
- Conor's comments
- add power-domains required for imx8qxp and imx8qm
- remove dmas descript, not allow use index to get dma-channel. Current
no user using this method.
- Link to v3: https://lore.kernel.org/r/20240228-asrc_8qxp-v3-0-d4d5935fd3aa@nxp.com
Changes in v3:
- Fixed dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/sound/fsl,spdif.example.dtb: spdif@2004000: interrupts: [[0, 52, 4]] is too short
from schema $id: http://devicetree.org/schemas/sound/fsl,spdif.yaml#
- Link to v2: https://lore.kernel.org/r/20240227-asrc_8qxp-v2-0-521bcc7eb1c0@nxp.com
---
Frank Li (5):
ASoC: dt-bindings: fsl,imx-asrc/spdif: Add power-domains property
ASoC: dt-bindings: fsl,imx-asrc: update max interrupt numbers
ASoC: dt-bindings: fsl-sai: allow only one dma-names
arm64: dts: imx8: fix audio lpcg index
arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]
.../devicetree/bindings/sound/fsl,imx-asrc.yaml | 14 +
.../devicetree/bindings/sound/fsl,sai.yaml | 6 +-
.../devicetree/bindings/sound/fsl,spdif.yaml | 35 ++-
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 285 ++++++++++++++++++++-
4 files changed, 327 insertions(+), 13 deletions(-)
---
base-commit: 8552c902efe7ef670b6961fb8885b67961aeb629
change-id: 20240227-asrc_8qxp-25aa6783840f
Best regards,
---
Frank Li <Frank.Li@nxp.com>
^ permalink raw reply
* Re: [PATCH] dt-bindings: arm: qcom: Add Samsung Galaxy Z Fold5
From: Konrad Dybcio @ 2024-03-28 14:47 UTC (permalink / raw)
To: Alexandru Serdeliuc, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <33e23d1c-5b6f-4111-9631-0f8db1100d0c@yahoo.com>
On 28.03.2024 3:42 PM, Alexandru Serdeliuc wrote:
> Hi Konrad,
>
>
> Thanks, yes, I am new to b4 and sending patches, in a few minutes I will add the second patch.
>
> That actually add the device tree, but without the previous patch it showed me a warning, and with both patches provided another warning that i need to split them in two.
Oh no, you should send them together! Could you please paste the warning so that
we can work out the issue?
Konrad
^ permalink raw reply
* Re: [PATCH] dt-bindings: arm: qcom: Add Samsung Galaxy Z Fold5
From: Alexandru Serdeliuc @ 2024-03-28 14:42 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <ca4ed5e3-32ea-451a-82ca-25fba07877dc@linaro.org>
Hi Konrad,
Thanks, yes, I am new to b4 and sending patches, in a few minutes I will
add the second patch.
That actually add the device tree, but without the previous patch it
showed me a warning, and with both patches provided another warning
that i need to split them in two.
Best regards,
Marc
On 28/3/24 15:39, Konrad Dybcio wrote:
> On 28.03.2024 3:31 PM, Alexandru Marc Serdeliuc via B4 Relay wrote:
>> From: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
>>
>> This documents Samsung Galaxy Z Fold5 (samsung,q5q)
>> which is a foldable phone by Samsung based on the sm8550 SoC.
>>
>> Signed-off-by: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
>> ---
>> This documents Samsung Galaxy Z Fold5 (samsung,q5q)
>> which is a foldable phone by Samsung based on the sm8550 SoC.
>> ---
> That's very welcome, but are you going to submit a devicetree for it?
>
> Konrad
^ permalink raw reply
* Re: [PATCH] dt-bindings: arm: qcom: Add Samsung Galaxy Z Fold5
From: Konrad Dybcio @ 2024-03-28 14:39 UTC (permalink / raw)
To: serdeliuk, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240328-dt-bindings-arm-qcom-add-support-for-samsung-galaxy-zfold5-v1-1-cb612e3ade18@yahoo.com>
On 28.03.2024 3:31 PM, Alexandru Marc Serdeliuc via B4 Relay wrote:
> From: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
>
> This documents Samsung Galaxy Z Fold5 (samsung,q5q)
> which is a foldable phone by Samsung based on the sm8550 SoC.
>
> Signed-off-by: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
> ---
> This documents Samsung Galaxy Z Fold5 (samsung,q5q)
> which is a foldable phone by Samsung based on the sm8550 SoC.
> ---
That's very welcome, but are you going to submit a devicetree for it?
Konrad
^ permalink raw reply
* Re: [PATCH 01/10] iio: buffer: add helper for setting direction
From: Jonathan Cameron @ 2024-03-28 14:36 UTC (permalink / raw)
To: Nuno Sa via B4 Relay
Cc: nuno.sa, linux-iio, devicetree, Dragos Bogdan, Lars-Peter Clausen,
Michael Hennerich, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Olivier Moysan
In-Reply-To: <20240328-iio-backend-axi-dac-v1-1-afc808b3fde3@analog.com>
On Thu, 28 Mar 2024 14:22:25 +0100
Nuno Sa via B4 Relay <devnull+nuno.sa.analog.com@kernel.org> wrote:
> From: Nuno Sa <nuno.sa@analog.com>
>
> Simple helper for setting the buffer direction when it's allocated using
> iio_dmaengine_buffer_alloc().
>
> Signed-off-by: Nuno Sa <nuno.sa@analog.com>
I wonder if we should align with the approach for triggered-buffers with and _ext
form of the registration function that takes a direction. It seems odd to allocate
one then change the direction.
Jonathan
> ---
> drivers/iio/industrialio-buffer.c | 7 +++++++
> include/linux/iio/buffer.h | 3 +++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/iio/industrialio-buffer.c b/drivers/iio/industrialio-buffer.c
> index 1d950a3e153b..4b1ca6ad86ee 100644
> --- a/drivers/iio/industrialio-buffer.c
> +++ b/drivers/iio/industrialio-buffer.c
> @@ -1956,6 +1956,13 @@ void iio_buffer_put(struct iio_buffer *buffer)
> }
> EXPORT_SYMBOL_GPL(iio_buffer_put);
>
> +void iio_buffer_set_dir(struct iio_buffer *buffer,
> + enum iio_buffer_direction dir)
> +{
> + buffer->direction = dir;
> +}
> +EXPORT_SYMBOL_GPL(iio_buffer_set_dir);
> +
> /**
> * iio_device_attach_buffer - Attach a buffer to a IIO device
> * @indio_dev: The device the buffer should be attached to
> diff --git a/include/linux/iio/buffer.h b/include/linux/iio/buffer.h
> index 418b1307d3f2..7e70bb5adc01 100644
> --- a/include/linux/iio/buffer.h
> +++ b/include/linux/iio/buffer.h
> @@ -55,4 +55,7 @@ bool iio_validate_scan_mask_onehot(struct iio_dev *indio_dev,
> int iio_device_attach_buffer(struct iio_dev *indio_dev,
> struct iio_buffer *buffer);
>
> +void iio_buffer_set_dir(struct iio_buffer *buffer,
> + enum iio_buffer_direction dir);
> +
> #endif /* _IIO_BUFFER_GENERIC_H_ */
>
^ permalink raw reply
* [PATCH] dt-bindings: arm: qcom: Add Samsung Galaxy Z Fold5
From: Alexandru Marc Serdeliuc via B4 Relay @ 2024-03-28 14:31 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Alexandru Marc Serdeliuc
From: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
This documents Samsung Galaxy Z Fold5 (samsung,q5q)
which is a foldable phone by Samsung based on the sm8550 SoC.
Signed-off-by: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
---
This documents Samsung Galaxy Z Fold5 (samsung,q5q)
which is a foldable phone by Samsung based on the sm8550 SoC.
---
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 66beaac60e1d..dea2a23b8fc2 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1003,6 +1003,7 @@ properties:
- qcom,sm8550-hdk
- qcom,sm8550-mtp
- qcom,sm8550-qrd
+ - samsung,q5q
- const: qcom,sm8550
- items:
---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240328-dt-bindings-arm-qcom-add-support-for-samsung-galaxy-zfold5-0994c09c202b
Best regards,
--
Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
^ permalink raw reply related
* Re: [PATCH v1 1/2] dt-bindings: thermal: amlogic: add support for A1 thermal sensor
From: Dmitry Rokosov @ 2024-03-28 14:29 UTC (permalink / raw)
To: neil.armstrong
Cc: jbrunet, mturquette, khilman, martin.blumenstingl, glaroque,
rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh+dt,
krzysztof.kozlowski+dt, conor+dt, kernel, rockosov, linux-amlogic,
linux-pm, linux-kernel, devicetree, linux-arm-kernel
In-Reply-To: <19897482-2fa1-4688-aeec-855123558374@linaro.org>
Hello Neil,
Thank you for quick feedback.
On Thu, Mar 28, 2024 at 03:07:52PM +0100, neil.armstrong@linaro.org wrote:
> Hi,
>
> On 28/03/2024 14:37, Dmitry Rokosov wrote:
> > Provide right compatible properties for Amlogic A1 Thermal Sensor
> > controller. A1 family supports only one thermal node - CPU thermal
> > sensor.
> >
> > Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
> > ---
> > .../bindings/thermal/amlogic,thermal.yaml | 14 +++++++++-----
> > 1 file changed, 9 insertions(+), 5 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
> > index 20f8f9b3b971..0e7f6568d385 100644
> > --- a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
> > +++ b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
> > @@ -13,11 +13,15 @@ description: Binding for Amlogic Thermal
> > properties:
> > compatible:
> > - items:
> > - - enum:
> > - - amlogic,g12a-cpu-thermal
> > - - amlogic,g12a-ddr-thermal
> > - - const: amlogic,g12a-thermal
> > + oneOf:
> > + - items:
> > + - enum:
> > + - amlogic,g12a-cpu-thermal
> > + - amlogic,g12a-ddr-thermal
> > + - const: amlogic,g12a-thermal
> > + - items:
> > + - const: amlogic,a1-cpu-thermal
> > + - const: amlogic,a1-thermal
>
> In this case you can just use "amlogic,a1-cpu-thermal" or "amlogic,a1-thermal", no need for a fallback.
Okay, I will send v2 with only one compatible w/o fallback.
--
Thank you,
Dmitry
^ permalink raw reply
* Re: [PATCH net-next v6 11/17] dt-bindings: net: pse-pd: Add another way of describing several PSE PIs
From: Kory Maincent @ 2024-03-28 14:23 UTC (permalink / raw)
To: Andrew Lunn
Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Oleksij Rempel, Mark Brown,
Frank Rowand, Heiner Kallweit, Russell King, Thomas Petazzoni,
netdev, linux-kernel, linux-doc, devicetree, Dent Project
In-Reply-To: <2d325acb-fc35-4ca3-80f2-ac88359578fd@lunn.ch>
On Thu, 28 Mar 2024 13:31:06 +0100
Andrew Lunn <andrew@lunn.ch> wrote:
> > + pairsets:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description:
> > + List of phandles, each pointing to the power supply for the
> > + corresponding pairset named in 'pairset-names'. This property
> > + aligns with IEEE 802.3-2022, Section 33.2.3 and 145.2.4.
> > + PSE Pinout Alternatives (as per IEEE 802.3-2022 Table
> > 145\u20133)
> > +
> > |-----------|---------------|---------------|---------------|---------------|
> > + | Conductor | Alternative A | Alternative A | Alternative B
> > | Alternative B |
> > + | | (MDI-X) | (MDI) | (X)
> > | (S) |
> > +
> > |-----------|---------------|---------------|---------------|---------------|
> > + | 1 | Negative VPSE | Positive VPSE | \u2014
> > | \u2014 |
> > + | 2 | Negative VPSE | Positive VPSE | \u2014
> > | \u2014 |
> > + | 3 | Positive VPSE | Negative VPSE | \u2014
> > | \u2014 |
> > + | 4 | \u2014 | \u2014 |
> > Negative VPSE | Positive VPSE |
> > + | 5 | \u2014 | \u2014 |
> > Negative VPSE | Positive VPSE |
> > + | 6 | Positive VPSE | Negative VPSE | \u2014
> > | \u2014 |
> > + | 7 | \u2014 | \u2014 |
> > Positive VPSE | Negative VPSE |
> > + | 8 | \u2014 | \u2014 |
> > Positive VPSE | Negative VPSE |
>
> Is it possible to avoid \u encoding? Ideally this documentation should
> be understandable without having to render it using a toolset. I just
> want to use less(1).
>
> Or is this a email problem? Has something converted your UTF-8 file to
> this \u notation?
It seems to come from the documentation I copied pasted from Oleksij mail.
Will fix it.
Regards,
--
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH net-next v6 11/17] dt-bindings: net: pse-pd: Add another way of describing several PSE PIs
From: Kory Maincent @ 2024-03-28 14:20 UTC (permalink / raw)
To: Andrew Lunn
Cc: Rob Herring, devicetree, Thomas Petazzoni, Dent Project,
Rafael J. Wysocki, Jonathan Corbet, Rob Herring, Russell King,
Conor Dooley, Jakub Kicinski, Frank Rowand, Krzysztof Kozlowski,
Heiner Kallweit, Russ Weight, David S. Miller, Greg Kroah-Hartman,
Oleksij Rempel, Paolo Abeni, Mark Brown, netdev, linux-doc,
Eric Dumazet, Luis Chamberlain, linux-kernel
In-Reply-To: <5230d786-44a8-45a0-ab0d-e1aa4ab6a836@lunn.ch>
On Thu, 28 Mar 2024 13:32:09 +0100
Andrew Lunn <andrew@lunn.ch> wrote:
> On Tue, Mar 26, 2024 at 10:39:28AM -0500, Rob Herring wrote:
> >
> > On Tue, 26 Mar 2024 15:04:48 +0100, Kory Maincent wrote:
> > > From: Kory Maincent (Dent Project) <kory.maincent@bootlin.com>
> > >
> > > PSE PI setup may encompass multiple PSE controllers or auxiliary circuits
> > > that collectively manage power delivery to one Ethernet port.
> > > Such configurations might support a range of PoE standards and require
> > > the capability to dynamically configure power delivery based on the
> > > operational mode (e.g., PoE2 versus PoE4) or specific requirements of
> > > connected devices. In these instances, a dedicated PSE PI node becomes
> > > essential for accurately documenting the system architecture. This node
> > > would serve to detail the interactions between different PSE controllers,
> > > the support for various PoE modes, and any additional logic required to
> > > coordinate power delivery across the network infrastructure.
> > >
> > > The old usage of "#pse-cells" is unsuficient as it carries only the PSE PI
> > > index information.
> > >
> > > Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
> > > ---
> > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> >
> > yamllint warnings/errors:
> >
> > dtschema/dtc warnings/errors:
> >
> >
> > doc reference errors (make refcheckdocs):
> > Warning: Documentation/devicetree/bindings/net/pse-pd/pse-controller.yaml
> > references a file that doesn't exist:
> > Documentation/networking/pse-pd/pse-pi.rst
> > Documentation/devicetree/bindings/net/pse-pd/pse-controller.yaml:
> > Documentation/networking/pse-pd/pse-pi.rst
>
> Is this a false positive?
I suppose so as the file is added in the patch 10.
Regards,
--
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH v5 1/1] dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk
From: Marek Vasut @ 2024-03-28 14:19 UTC (permalink / raw)
To: Christophe Roullier, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maxime Coquelin, Alexandre Torgue, Richard Cochran,
Jose Abreu, Liam Girdwood, Mark Brown
Cc: netdev, devicetree, linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20240328140803.324141-2-christophe.roullier@foss.st.com>
On 3/28/24 3:08 PM, Christophe Roullier wrote:
[...]
> | RMII | - | eth-ck | eth-ck | n/a |
> | | | st,ext-phyclk | st,eth-ref-clk-sel | |
> | | | | or st,ext-phyclk | |
>
> ---------------------------------------------------------------------------
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
> ---
> Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> index fc8c96b08d7dc..b35eae80ed6ac 100644
> --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> @@ -82,6 +82,13 @@ properties:
> Should be phandle/offset pair. The phandle to the syscon node which
> encompases the glue register, and the offset of the control register
>
> +st,ext-phyclk:
Don't you need two spaces in front of the 'st,' here ?
> + description:
> + set this property in RMII mode when you have PHY without crystal 50MHz and want to
> + select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
> + RCC clock instead of ETH_CLK125.
> + type: boolean
> +
With that fixed:
Reviewed-by: Marek Vasut <marex@denx.de>
^ permalink raw reply
* Re: [RFC PATCH 06/13] pinctrl: renesas: pinctrl-rzg2l: Make cfg to u64 in struct rzg2l_variable_pin_cfg
From: Geert Uytterhoeven @ 2024-03-28 14:13 UTC (permalink / raw)
To: Prabhakar
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Magnus Damm, linux-renesas-soc, linux-gpio, devicetree,
linux-kernel, Fabrizio Castro, Lad Prabhakar
In-Reply-To: <20240326222844.1422948-7-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Tue, Mar 26, 2024 at 11:30 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Now that we have updated the macro PIN_CFG_MASK to allow for the maximum
> configuration bits, update the size of 'cfg' to 'u64' in the
> 'struct rzg2l_variable_pin_cfg'.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -241,7 +241,7 @@ struct rzg2l_dedicated_configs {
> * @pin: port pin
> */
> struct rzg2l_variable_pin_cfg {
> - u32 cfg:20;
> + u64 cfg:46;
> u32 port:5;
> u32 pin:3;
Doesn't this store the 46 cfg bits in a 64-bit word, and the 8 port
and pin bits in a different 32-bit word? Worse, you'll get 4 bytes
of padding at the end of the structure.
Changing the port and pin to u64 should make sure everything is
stored together in a single 64-bit word.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH net-next v6 10/17] net: pse-pd: Add support for PSE PIs
From: Kory Maincent @ 2024-03-28 14:12 UTC (permalink / raw)
To: Simon Horman
Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Oleksij Rempel, Mark Brown,
Frank Rowand, Andrew Lunn, Heiner Kallweit, Russell King,
Thomas Petazzoni, netdev, linux-kernel, linux-doc, devicetree,
Dent Project
In-Reply-To: <20240328104011.GY403975@kernel.org>
On Thu, 28 Mar 2024 10:40:11 +0000
Simon Horman <horms@kernel.org> wrote:
> On Thu, Mar 28, 2024 at 10:33:22AM +0000, Simon Horman wrote:
> > On Tue, Mar 26, 2024 at 03:04:47PM +0100, Kory Maincent wrote:
> > > From: Kory Maincent (Dent Project) <kory.maincent@bootlin.com>
>
> ...
>
> > > diff --git a/include/linux/pse-pd/pse.h b/include/linux/pse-pd/pse.h
> >
> > ...
> >
> > > @@ -73,11 +103,11 @@ struct pse_control;
> > > * @pse_control_head: head of internal list of requested PSE controls
> > > * @dev: corresponding driver model device struct
> > > * @of_pse_n_cells: number of cells in PSE line specifiers
> > > - * @of_xlate: translation function to translate from specifier as found
> > > in the
> > > - * device tree to id as given to the PSE control ops
> > > * @nr_lines: number of PSE controls in this controller device
> > > * @lock: Mutex for serialization access to the PSE controller
> > > * @types: types of the PSE controller
> > > + * @pi: table of PSE PIs described in this controller device
> > > + * @of_legacy: flag set if the pse_pis devicetree node is not used
> >
> > nit: it looks line the documentation didn't keep up with the
> > structure during development: @no_of_pse_pi should be
> > documented instead of @of_legacy.
>
> There seem to be some similar minor problems in
> [PATCH net-next v6 13/17] net: pse-pd: Use regulator framework within PSE
> framework
>
> ./scripts/kernel-doc -none is your friend here.
Oh didn't know about it, thanks!
Regards,
--
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH 1/1] arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif[0,1] and sai[4,5]
From: Shawn Guo @ 2024-03-28 14:10 UTC (permalink / raw)
To: Frank Li
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
In-Reply-To: <20240226192130.259288-1-Frank.Li@nxp.com>
On Mon, Feb 26, 2024 at 02:21:29PM -0500, Frank Li wrote:
> Add asrc[0,1], esai0, spdif[0,1], sai[4,5] and related lpcg node for
> imx8 audio subsystem.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> .../boot/dts/freescale/imx8-ss-audio.dtsi | 306 ++++++++++++++++++
> 1 file changed, 306 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> index 07afeb78ed564..6d78d6c0d9002 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> @@ -6,6 +6,7 @@
>
> #include <dt-bindings/clock/imx8-clock.h>
> #include <dt-bindings/clock/imx8-lpcg.h>
> +#include <dt-bindings/dma/fsl-edma.h>
> #include <dt-bindings/firmware/imx/rsrc.h>
>
> audio_ipg_clk: clock-audio-ipg {
> @@ -481,4 +482,309 @@ acm: acm@59e00000 {
> "sai3_rx_bclk",
> "sai4_rx_bclk";
> };
> +
> + asrc0: asrc@59000000 {
We want to sort nodes in unit-address, right?
> + compatible = "fsl,imx8qm-asrc";
> + reg = <0x59000000 0x10000>;
> + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&asrc0_lpcg 0>,
> + <&asrc0_lpcg 0>,
> + <&aud_pll_div0_lpcg 0>,
> + <&aud_pll_div1_lpcg 0>,
> + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
> + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>;
> + clock-names = "ipg", "mem",
> + "asrck_0", "asrck_1", "asrck_2", "asrck_3",
> + "asrck_4", "asrck_5", "asrck_6", "asrck_7",
> + "asrck_8", "asrck_9", "asrck_a", "asrck_b",
> + "asrck_c", "asrck_d", "asrck_e", "asrck_f",
> + "spba";
> + dmas = <&edma0 0 0 0>,
> + <&edma0 1 0 0>,
> + <&edma0 2 0 0>,
> + <&edma0 3 0 FSL_EDMA_RX>,
> + <&edma0 4 0 FSL_EDMA_RX>,
> + <&edma0 5 0 FSL_EDMA_RX>;
> + /* tx* is output channel of asrc, it is rx channel for eDMA */
> + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
> + fsl,asrc-rate = <8000>;
One space around =
> + fsl,asrc-width = <16>;
> + fsl,asrc-clk-map = <0>;
> + power-domains = <&pd IMX_SC_R_ASRC_0>;
> + status = "disabled";
> + };
> +
> + esai0: esai@59010000 {
> + compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai";
> + reg = <0x59010000 0x10000>;
> + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&clk_dummy>;
> + clock-names = "core", "extal", "fsys", "spba";
> + dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>;
> + dma-names = "rx", "tx";
> + power-domains = <&pd IMX_SC_R_ESAI_0>;
> + status = "disabled";
> + };
> +
> + spdif0: spdif@59020000 {
> + compatible = "fsl,imx8qm-spdif";
> + reg = <0x59020000 0x10000>;
> + interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
Ditto
> + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
> + clocks = <&spdif0_lpcg 1>, /* core */
> + <&clk_dummy>, /* rxtx0 */
> + <&spdif0_lpcg 0>, /* rxtx1 */
> + <&clk_dummy>, /* rxtx2 */
> + <&clk_dummy>, /* rxtx3 */
> + <&clk_dummy>, /* rxtx4 */
> + <&audio_ipg_clk>, /* rxtx5 */
> + <&clk_dummy>, /* rxtx6 */
> + <&clk_dummy>, /* rxtx7 */
> + <&clk_dummy>; /* spba */
> + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
> + "rxtx5", "rxtx6", "rxtx7", "spba";
> + dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
> + <&edma0 9 0 FSL_EDMA_MULTI_FIFO>;
> + dma-names = "rx", "tx";
> + power-domains = <&pd IMX_SC_R_SPDIF_0>;
> + status = "disabled";
> + };
> +
> + spdif1: spdif@59030000 {
> + compatible = "fsl,imx8qm-spdif";
> + reg = <0x59030000 0x10000>;
> + interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */
Ditto
Shawn
> + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */
> + clocks = <&spdif1_lpcg 1>, /* core */
> + <&clk_dummy>, /* rxtx0 */
> + <&spdif1_lpcg 0>, /* rxtx1 */
> + <&clk_dummy>, /* rxtx2 */
> + <&clk_dummy>, /* rxtx3 */
> + <&clk_dummy>, /* rxtx4 */
> + <&audio_ipg_clk>, /* rxtx5 */
> + <&clk_dummy>, /* rxtx6 */
> + <&clk_dummy>, /* rxtx7 */
> + <&clk_dummy>; /* spba */
> + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
> + "rxtx5", "rxtx6", "rxtx7", "spba";
> + dmas = <&edma0 10 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
> + <&edma0 11 0 FSL_EDMA_MULTI_FIFO>;
> + dma-names = "rx", "tx";
> + power-domains = <&pd IMX_SC_R_SPDIF_1>;
> + status = "disabled";
> + };
> +
> + asrc1: asrc@59800000 {
> + compatible = "fsl,imx8qm-asrc";
> + reg = <0x59800000 0x10000>;
> + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&asrc1_lpcg 0>,
> + <&asrc1_lpcg 0>,
> + <&aud_pll_div0_lpcg 0>,
> + <&aud_pll_div1_lpcg 0>,
> + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
> + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>,
> + <&clk_dummy>;
> + clock-names = "ipg", "mem",
> + "asrck_0", "asrck_1", "asrck_2", "asrck_3",
> + "asrck_4", "asrck_5", "asrck_6", "asrck_7",
> + "asrck_8", "asrck_9", "asrck_a", "asrck_b",
> + "asrck_c", "asrck_d", "asrck_e", "asrck_f",
> + "spba";
> + dmas = <&edma1 0 0 0>,
> + <&edma1 1 0 0>,
> + <&edma1 2 0 0>,
> + <&edma1 3 0 FSL_EDMA_RX>,
> + <&edma1 4 0 FSL_EDMA_RX>,
> + <&edma1 5 0 FSL_EDMA_RX>;
> + /* tx* is output channel of asrc, it is rx channel for eDMA */
> + dma-names = "txa", "txb", "txc", "rxa", "rxb", "rxc";
> + fsl,asrc-rate = <8000>;
> + fsl,asrc-width = <16>;
> + fsl,asrc-clk-map = <1>;
> + power-domains = <&pd IMX_SC_R_ASRC_1>;
> + status = "disabled";
> + };
> +
> + sai4: sai@59820000 {
> + compatible = "fsl,imx8qm-sai";
> + reg = <0x59820000 0x10000>;
> + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&sai4_lpcg 1>,
> + <&clk_dummy>,
> + <&sai4_lpcg 0>,
> + <&clk_dummy>,
> + <&clk_dummy>;
> + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
> + dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>;
> + dma-names = "rx", "tx";
> + power-domains = <&pd IMX_SC_R_SAI_4>;
> + status = "disabled";
> + };
> +
> + sai5: sai@59830000 {
> + compatible = "fsl,imx8qm-sai";
> + reg = <0x59830000 0x10000>;
> + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&sai5_lpcg 1>,
> + <&clk_dummy>,
> + <&sai5_lpcg 0>,
> + <&clk_dummy>,
> + <&clk_dummy>;
> + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
> + dmas = <&edma1 10 0 0>;
> + dma-names = "tx";
> + power-domains = <&pd IMX_SC_R_SAI_5>;
> + status = "disabled";
> + };
> +
> + amix: amix@59840000 {
> + compatible = "fsl,imx8qm-audmix";
> + reg = <0x59840000 0x10000>;
> + clocks = <&amix_lpcg 0>;
> + clock-names = "ipg";
> + power-domains = <&pd IMX_SC_R_AMIX>;
> + dais = <&sai4>, <&sai5>;
> + status = "disabled";
> + };
> +
> + mqs: mqs@59850000 {
> + compatible = "fsl,imx8qm-mqs";
> + reg = <0x59850000 0x10000>;
> + clocks = <&mqs0_lpcg 1>,
> + <&mqs0_lpcg 0>;
> + clock-names = "core", "mclk";
> + power-domains = <&pd IMX_SC_R_MQS_0>;
> + status = "disabled";
> + };
> +
> + asrc0_lpcg: clock-controller@59400000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x59400000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&audio_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_4>;
> + clock-output-names = "asrc0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_ASRC_0>;
> + };
> +
> + esai0_lpcg: clock-controller@59410000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x59410000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
> + <&audio_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "esai0_lpcg_extal_clk",
> + "esai0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_ESAI_0>;
> + };
> +
> + spdif0_lpcg: clock-controller@59420000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x59420000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>,
> + <&audio_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "spdif0_lpcg_tx_clk",
> + "spdif0_lpcg_gclkw";
> + power-domains = <&pd IMX_SC_R_SPDIF_0>;
> + };
> +
> + spdif1_lpcg: clock-controller@59430000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x59430000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>,
> + <&audio_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "spdif1_lpcg_tx_clk",
> + "spdif1_lpcg_gclkw";
> + power-domains = <&pd IMX_SC_R_SPDIF_1>;
> + status = "disabled";
> + };
> +
> + asrc1_lpcg: clock-controller@59c00000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x59c00000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&audio_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_4>;
> + clock-output-names = "asrc1_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_ASRC_1>;
> + };
> +
> + sai4_lpcg: clock-controller@59c20000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x59c20000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
> + <&audio_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "sai4_lpcg_mclk",
> + "sai4_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_SAI_4>;
> + };
> +
> + sai5_lpcg: clock-controller@59c30000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x59c30000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
> + <&audio_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "sai5_lpcg_mclk",
> + "sai5_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_SAI_5>;
> + };
> +
> + amix_lpcg: clock-controller@59c40000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x59c40000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&audio_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "amix_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_AMIX>;
> + };
> +
> + mqs0_lpcg: clock-controller@59c50000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x59c50000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>,
> + <&audio_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "mqs0_lpcg_mclk",
> + "mqs0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MQS_0>;
> + };
> };
> --
> 2.34.1
>
^ permalink raw reply
* [PATCH v5 0/1] Add property in dwmac-stm32 documentation
From: Christophe Roullier @ 2024-03-28 14:08 UTC (permalink / raw)
To: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Richard Cochran, Jose Abreu, Liam Girdwood,
Mark Brown, Christophe Roullier, Marek Vasut
Cc: netdev, devicetree, linux-stm32, linux-arm-kernel, linux-kernel
Introduce property in dwmac-stm32 documentation
- st,ext-phyclk: is present since 2020 in driver so need to explain
it and avoid dtbs check issue : views/kernel/upstream/net-next/arch/arm/boot/dts/st/stm32mp157c-dk2.dtb:
ethernet@5800a000: Unevaluated properties are not allowed
('st,ext-phyclk' was unexpected)
Furthermore this property will be use in upstream of MP13 dwmac glue. (next step)
V2: - Drop deprecated: property for st,eth-clk-sel and st,eth-ref-clk-sel
V3: - Rework commit message
V4: - Fix syntax issue in commit message
V5: - Remark from Andrew Lunn (remove documentation of PHY regulator, it will come in next step (with
implementation))
Christophe Roullier (1):
dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk
Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 7 +++++++
1 file changed, 7 insertions(+)
--
2.25.1
^ permalink raw reply
* [PATCH v5 1/1] dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk
From: Christophe Roullier @ 2024-03-28 14:08 UTC (permalink / raw)
To: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Richard Cochran, Jose Abreu, Liam Girdwood,
Mark Brown, Christophe Roullier, Marek Vasut
Cc: netdev, devicetree, linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20240328140803.324141-1-christophe.roullier@foss.st.com>
The Linux kernel dwmac-stm32 driver currently supports three DT
properties used to configure whether PHY clock are generated by
the MAC or supplied to the MAC from the PHY.
Originally there were two properties, st,eth-clk-sel and
st,eth-ref-clk-sel, each used to configure MAC clocking in
different bus mode and for different MAC clock frequency.
Since it is possible to determine the MAC 'eth-ck' clock
frequency from the clock subsystem and PHY bus mode from
the 'phy-mode' property, two disparate DT properties are
no longer required to configure MAC clocking.
Linux kernel commit 1bb694e20839 ("net: ethernet: stmmac: simplify phy modes management for stm32")
introduced a third, unified, property st,ext-phyclk. This property
covers both use cases of st,eth-clk-sel and st,eth-ref-clk-sel DT
properties, as well as a new use case for 25 MHz clock generated
by the MAC.
The third property st,ext-phyclk is so far undocumented,
document it.
Below table summarizes the clock requirement and clock sources for
supported PHY interface modes.
__________________________________________________________________________
|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125Mhz from PHY|
| | | 25MHz | 50MHz | |
---------------------------------------------------------------------------
| MII | - | eth-ck | n/a | n/a |
| | | st,ext-phyclk | | |
---------------------------------------------------------------------------
| GMII | - | eth-ck | n/a | n/a |
| | | st,ext-phyclk | | |
---------------------------------------------------------------------------
| RGMII | - | eth-ck | n/a | eth-ck |
| | | st,ext-phyclk | | st,eth-clk-sel or|
| | | | | st,ext-phyclk |
---------------------------------------------------------------------------
| RMII | - | eth-ck | eth-ck | n/a |
| | | st,ext-phyclk | st,eth-ref-clk-sel | |
| | | | or st,ext-phyclk | |
---------------------------------------------------------------------------
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index fc8c96b08d7dc..b35eae80ed6ac 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -82,6 +82,13 @@ properties:
Should be phandle/offset pair. The phandle to the syscon node which
encompases the glue register, and the offset of the control register
+st,ext-phyclk:
+ description:
+ set this property in RMII mode when you have PHY without crystal 50MHz and want to
+ select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
+ RCC clock instead of ETH_CLK125.
+ type: boolean
+
st,eth-clk-sel:
description:
set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v1 1/3] arm64: dts: amlogic: a1: add cooling-cells for DVFS feature
From: neil.armstrong @ 2024-03-28 14:08 UTC (permalink / raw)
To: Dmitry Rokosov, jbrunet, mturquette, khilman, martin.blumenstingl,
glaroque, rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: kernel, rockosov, linux-amlogic, linux-pm, linux-kernel,
devicetree, linux-arm-kernel
In-Reply-To: <20240328134459.18446-2-ddrokosov@salutedevices.com>
On 28/03/2024 14:44, Dmitry Rokosov wrote:
> It's used for CPU with DVFS feature to specify minimum and maximum
> cooling state used in the reference.
> Without these values DVFS will not work and dtbs_check will raise the
> error.
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index fbee986421f1..f65d4a77ee52 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -32,6 +32,7 @@ cpu0: cpu@0 {
> reg = <0x0 0x0>;
> enable-method = "psci";
> next-level-cache = <&l2>;
> + #cooling-cells = <2>;
> };
>
> cpu1: cpu@1 {
> @@ -40,6 +41,7 @@ cpu1: cpu@1 {
> reg = <0x0 0x1>;
> enable-method = "psci";
> next-level-cache = <&l2>;
> + #cooling-cells = <2>;
> };
>
> l2: l2-cache0 {
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply
* Re: [PATCH v1 2/2] thermal: amlogic: support A1 SoC family Thermal Sensor controller
From: neil.armstrong @ 2024-03-28 14:08 UTC (permalink / raw)
To: Dmitry Rokosov, jbrunet, mturquette, khilman, martin.blumenstingl,
glaroque, rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: kernel, rockosov, linux-amlogic, linux-pm, linux-kernel,
devicetree, linux-arm-kernel
In-Reply-To: <20240328133802.15651-3-ddrokosov@salutedevices.com>
On 28/03/2024 14:37, Dmitry Rokosov wrote:
> In comparison to other Amlogic chips, there is one key difference.
> The offset for the sec_ao base, also known as u_efuse_off, is special,
> while other aspects remain the same.
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
> ---
> drivers/thermal/amlogic_thermal.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/thermal/amlogic_thermal.c b/drivers/thermal/amlogic_thermal.c
> index 5877cde25b79..1d23afd32013 100644
> --- a/drivers/thermal/amlogic_thermal.c
> +++ b/drivers/thermal/amlogic_thermal.c
> @@ -222,6 +222,12 @@ static const struct amlogic_thermal_data amlogic_thermal_g12a_ddr_param = {
> .regmap_config = &amlogic_thermal_regmap_config_g12a,
> };
>
> +static const struct amlogic_thermal_data amlogic_thermal_a1_cpu_param = {
> + .u_efuse_off = 0x114,
> + .calibration_parameters = &amlogic_thermal_g12a,
> + .regmap_config = &amlogic_thermal_regmap_config_g12a,
> +};
> +
> static const struct of_device_id of_amlogic_thermal_match[] = {
> {
> .compatible = "amlogic,g12a-ddr-thermal",
> @@ -231,6 +237,10 @@ static const struct of_device_id of_amlogic_thermal_match[] = {
> .compatible = "amlogic,g12a-cpu-thermal",
> .data = &amlogic_thermal_g12a_cpu_param,
> },
> + {
> + .compatible = "amlogic,a1-cpu-thermal",
> + .data = &amlogic_thermal_a1_cpu_param,
> + },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, of_amlogic_thermal_match);
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Keep it even it you change the compatible,
Thanks,
Neil
^ permalink raw reply
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