* Re: [PATCH] ARM: dts: imx7s-warp: Pass OV2680 link-frequencies
From: Rob Herring @ 2024-03-28 21:01 UTC (permalink / raw)
To: Fabio Estevam
Cc: Fabio Estevam, linux-arm-kernel, sakari.ailus, stable, hdegoede,
devicetree, shawnguo, conor+dt, krzysztof.kozlowski+dt
In-Reply-To: <20240328151954.2517368-1-festevam@gmail.com>
On Thu, 28 Mar 2024 12:19:54 -0300, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
>
> Since commit 63b0cd30b78e ("media: ov2680: Add bus-cfg / endpoint
> property verification") the ov2680 no longer probes on a imx7s-warp7:
>
> ov2680 1-0036: error -EINVAL: supported link freq 330000000 not found
> ov2680 1-0036: probe with driver ov2680 failed with error -22
>
> Fix it by passing the required 'link-frequencies' property as
> recommended by:
>
> https://www.kernel.org/doc/html/v6.9-rc1/driver-api/media/camera-sensor.html#handling-clocks
>
> Cc: stable@vger.kernel.org
> Fixes: 63b0cd30b78e ("media: ov2680: Add bus-cfg / endpoint property verification")
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> ---
> arch/arm/boot/dts/nxp/imx/imx7s-warp.dts | 1 +
> 1 file changed, 1 insertion(+)
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y nxp/imx/imx7s-warp.dtb' for 20240328151954.2517368-1-festevam@gmail.com:
arch/arm/boot/dts/nxp/imx/imx7s-warp.dtb: camera@36: port:endpoint: Unevaluated properties are not allowed ('clock-lanes', 'data-lanes', 'link-frequencies' were unexpected)
from schema $id: http://devicetree.org/schemas/media/i2c/ovti,ov2680.yaml#
^ permalink raw reply
* Re: [PATCH 1/5] dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings
From: Rob Herring @ 2024-03-28 20:54 UTC (permalink / raw)
To: Sibi Sankar
Cc: sudeep.holla, cristian.marussi, andersson, konrad.dybcio,
jassisinghbrar, krzysztof.kozlowski+dt, linux-kernel,
linux-arm-msm, devicetree, quic_rgottimu, quic_kshivnan, conor+dt,
quic_gkohli, quic_nkela, quic_psodagud
In-Reply-To: <20240328095044.2926125-2-quic_sibis@quicinc.com>
On Thu, Mar 28, 2024 at 03:20:40PM +0530, Sibi Sankar wrote:
> Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox
> controller.
>
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---
>
> rfc:
rfc is not a version, but a "state of the patch" tag. This should be v2.
> * Use x1e80100 as the fallback for future SoCs using the cpucp-mbox
> controller. [Krzysztoff/Konrad/Rob]
>
> .../bindings/mailbox/qcom,cpucp-mbox.yaml | 49 +++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 2/3] dt-bindings: display: msm: sm6350-mdss: document DP controller subnode
From: Rob Herring @ 2024-03-28 20:52 UTC (permalink / raw)
To: Luca Weiss
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Daniel Vetter,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh,
Krishna Manikandan, Bjorn Andersson, Konrad Dybcio,
~postmarketos/upstreaming, phone-devel, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel
In-Reply-To: <20240328-sm6350-dp-v1-2-215ca2b81c35@fairphone.com>
On Thu, Mar 28, 2024 at 10:42:45AM +0100, Luca Weiss wrote:
> Document the displayport controller subnode of the SM6350 MDSS.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> .../devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
> index c9ba1fae8042..d91b8eca6aba 100644
> --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
> @@ -53,6 +53,16 @@ patternProperties:
> compatible:
> const: qcom,sm6350-dpu
>
> + "^displayport-controller@[0-9a-f]+$":
> + type: object
> + additionalProperties: true
> +
> + properties:
> + compatible:
> + items:
> + - const: qcom,sm6350-dp
> + - const: qcom,sm8350-dp
Just use 'contains' here with qcom,sm6350-dp. The full schema will check
the order.
Rob
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: display: msm: dp-controller: document SM8250 compatible
From: Rob Herring @ 2024-03-28 20:51 UTC (permalink / raw)
To: Luca Weiss
Cc: Konrad Dybcio, Krishna Manikandan, David Airlie, devicetree,
Dmitry Baryshkov, linux-arm-msm, Bjorn Andersson, Sean Paul,
Daniel Vetter, ~postmarketos/upstreaming, Rob Clark,
Maxime Ripard, dri-devel, Thomas Zimmermann, Abhinav Kumar,
Maarten Lankhorst, Krzysztof Kozlowski, Marijn Suijten,
Conor Dooley, linux-kernel, freedreno, Kuogee Hsieh, phone-devel
In-Reply-To: <20240328-sm6350-dp-v1-1-215ca2b81c35@fairphone.com>
On Thu, 28 Mar 2024 10:42:44 +0100, Luca Weiss wrote:
> Add the compatible string for the DisplayPort controller on SM6350 which
> is compatible with the one on SM8350.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 22/23] drivers: media: i2c: imx258: Add support for powerdown gpio
From: Rob Herring @ 2024-03-28 20:48 UTC (permalink / raw)
To: git
Cc: linux-media, dave.stevenson, jacopo.mondi, mchehab,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, Ondrej Jirman
In-Reply-To: <20240327231710.53188-23-git@luigi311.com>
On Wed, Mar 27, 2024 at 05:17:08PM -0600, git@luigi311.com wrote:
> From: Luigi311 <git@luigi311.com>
>
> On some boards powerdown signal needs to be deasserted for this
> sensor to be enabled.
>
> Signed-off-by: Ondrej Jirman <megi@xff.cz>
> ---
> .../devicetree/bindings/media/i2c/sony,imx258.yaml | 4 ++++
Bindings should be a separate patch.
> drivers/media/i2c/imx258.c | 13 +++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> index c7856de15ba3..0414085bf22f 100644
> --- a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> @@ -35,6 +35,10 @@ properties:
> reg:
> maxItems: 1
>
> + powerdown-gpios:
> + description: |-
Don't need '|-' if no formatting.
> + Reference to the GPIO connected to the PWDN pin, if any.
> +
> reset-gpios:
> description: |-
> Reference to the GPIO connected to the XCLR pin, if any.
^ permalink raw reply
* Re: [PATCH 18/23] dt-bindings: media: imx258: Add alternate compatible strings
From: Rob Herring @ 2024-03-28 20:46 UTC (permalink / raw)
To: Luigi311
Cc: linux-media, dave.stevenson, jacopo.mondi, mchehab,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel
In-Reply-To: <76f999a7-55e0-4676-aa75-8fcd466e046b@luigi311.com>
On Thu, Mar 28, 2024 at 01:16:22PM -0600, Luigi311 wrote:
> On 3/28/24 12:55, Rob Herring wrote:
> > On Wed, Mar 27, 2024 at 05:17:04PM -0600, git@luigi311.com wrote:
> >> From: Dave Stevenson <dave.stevenson@raspberrypi.com>
> >>
> >> There are a number of variants of the imx258 modules that can not
> >> be differentiated at runtime, so add compatible strings for them.
> >> But you are only adding 1 variant.
>
> I can not speak for Dave but as to why this was added here but looking
> at the imx296 yaml that has something similar where there are multiple
> variants that may not be detectable at run time but does not include
> similar verbiage in the main description. Should I drop this from the
> description so it matches the imx296?
Just change "add compatible strings for them" to "add compatible string
for the PDAF variant" or something.
>
> >
> >>
> >> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> >> Signed-off-by: Luigi311 <git@luigi311.com>
> >> ---
> >> .../devicetree/bindings/media/i2c/sony,imx258.yaml | 6 +++++-
> >> 1 file changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> >> index bee61a443b23..c7856de15ba3 100644
> >> --- a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> >> +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> >> @@ -14,10 +14,14 @@ description: |-
> >> type stacked image sensor with a square pixel array of size 4208 x 3120. It
> >> is programmable through I2C interface. Image data is sent through MIPI
> >> CSI-2.
> >> + There are a number of variants of the sensor which cannot be detected at
> >> + runtime, so multiple compatible strings are required to differentiate these.
> >
> > That's more reasoning/why for the patch than description of the h/w.
> >
> >> properties:
> >> compatible:
> >> - const: sony,imx258
> >> + - enum:
> >> + - sony,imx258
> >> + - sony,imx258-pdaf
> >
> > How do I know which one to use? Please define what PDAF means somewhere
> > as well as perhaps what the original/default variant is or isn't.
>
> Would it make sense to change the properties to include a description like so
>
> properties:
> compatible:
> enum:
> - sony,imx258
> - sony,imx258-pdaf
> description:
> The IMX258 sensor exists in two different models, a standard variant
> (IMX258) and a variant with phase detection autofocus (IMX258-PDAF).
> The camera module does not expose the model through registers, so the
> exact model needs to be specified.
Looks fine, but I'd move this to the top-level 'description'.
Rob
^ permalink raw reply
* Re: [PATCH 3/3] arm64: dts: freescale: Add device tree for Emcraft Systems NavQ+ Kit
From: Andrew Lunn @ 2024-03-28 20:42 UTC (permalink / raw)
To: Gilles Talis
Cc: devicetree, imx, linux-arm-kernel, conor+dt,
krzysztof.kozlowski+dt, robh, shawnguo, festevam, alex
In-Reply-To: <20240328202320.187596-4-gilles.talis@gmail.com>
> +&eqos {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_eqos>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> + status = "okay";
> +
> + mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <1000>;
> + reset-deassert-us = <10000>;
> + qca,disable-smarteee;
> + qca,disable-hibernation-mode;
> + vddio-supply = <&vddio>;
> +
> + vddio: vddio-regulator {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
Please could you explain what this last node is doing.
Andrew
^ permalink raw reply
* Re: [PATCH v5 1/1] dt-bindings: net: starfive,jh7110-dwmac: Add StarFive JH8100 support
From: Rob Herring @ 2024-03-28 20:42 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Tan Chun Hau, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Emil Renner Berthing, Krzysztof Kozlowski,
Conor Dooley, Maxime Coquelin, Alexandre Torgue, Simon Horman,
Bartosz Golaszewski, Andrew Halaney, Jisheng Zhang,
Uwe Kleine-König, Russell King, Ley Foon Tan, Jee Heng Sia,
netdev, devicetree, linux-kernel, linux-stm32, linux-arm-kernel,
linux-riscv
In-Reply-To: <31ac366d-bfa6-4c99-a04d-ab9fb029da7e@linaro.org>
On Wed, Mar 27, 2024 at 08:54:30AM +0100, Krzysztof Kozlowski wrote:
> On 27/03/2024 02:57, Tan Chun Hau wrote:
> > Add StarFive JH8100 dwmac support.
> > The JH8100 dwmac shares the same driver code as the JH7110 dwmac
> > and has only one reset signal.
> >
> > Please refer to below:
> >
> > JH8100: reset-names = "stmmaceth";
> > JH7110: reset-names = "stmmaceth", "ahb";
> > JH7100: reset-names = "ahb";
> >
> > Example usage of JH8100 in the device tree:
> >
> > gmac0: ethernet@16030000 {
> > compatible = "starfive,jh8100-dwmac",
> > "starfive,jh7110-dwmac",
> > "snps,dwmac-5.20";
> > ...
> > };
> >
> > Signed-off-by: Tan Chun Hau <chunhau.tan@starfivetech.com>
> > ---
> > .../devicetree/bindings/net/snps,dwmac.yaml | 1 +
> > .../bindings/net/starfive,jh7110-dwmac.yaml | 29 +++++++++++++++----
> > 2 files changed, 25 insertions(+), 5 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> > index 6b0341a8e0ea..a6d596b7dcf4 100644
> > --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> > +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
> > @@ -97,6 +97,7 @@ properties:
> > - snps,dwxgmac-2.10
> > - starfive,jh7100-dwmac
> > - starfive,jh7110-dwmac
> > + - starfive,jh8100-dwmac
>
> I think that's not needed. You have there already your fallback.
>
> >
> > reg:
> > minItems: 1
> > diff --git a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
> > index 0d1962980f57..5805a58c55d1 100644
> > --- a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
> > +++ b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
> > @@ -18,6 +18,7 @@ select:
> > enum:
> > - starfive,jh7100-dwmac
> > - starfive,jh7110-dwmac
> > + - starfive,jh8100-dwmac
>
> Same here, even more obvious.
Agreed.
>
> > required:
> > - compatible
> >
> > @@ -30,6 +31,10 @@ properties:
> > - items:
> > - const: starfive,jh7110-dwmac
> > - const: snps,dwmac-5.20
> > + - items:
> > + - const: starfive,jh8100-dwmac
> > + - const: starfive,jh7110-dwmac
> > + - const: snps,dwmac-5.20
> >
> > reg:
> > maxItems: 1
> > @@ -116,11 +121,25 @@ allOf:
> > minItems: 3
> > maxItems: 3
> >
> > - resets:
> > - minItems: 2
> > -
> > - reset-names:
> > - minItems: 2
> > + if:
>
> I would personally avoid nesting if within if. It gets unreadable.
> Although Rob did not comment on this one, so I guess it is fine.
I normally agree, but here I suggested it as it looked to be the
simplest option.
With the 2 other comments addressed,
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v10 2/2] dt-bindings: mtd: fixed-partition: Add binman compatibles
From: Rob Herring @ 2024-03-28 20:37 UTC (permalink / raw)
To: Simon Glass
Cc: Michael Walle, Conor Dooley, Vignesh Raghavendra, devicetree,
Krzysztof Kozlowski, U-Boot Mailing List, Rafał Miłecki,
linux-mtd, Miquel Raynal, Richard Weinberger, linux-kernel,
Tom Rini
In-Reply-To: <20240326200645.1182803-2-sjg@chromium.org>
On Tue, 26 Mar 2024 14:06:45 -0600, Simon Glass wrote:
> Add two compatibles for binman entries, as a starting point for the
> schema.
>
> Note that, after discussion on v2, we decided to keep the existing
> meaning of label so as not to require changes to existing userspace
> software when moving to use binman nodes to specify the firmware
> layout.
>
> Note also that, after discussion on v6, we decided to use the same
> 'fixed-partition' schema for the binman features, so this version
> adds a new 'binman.yaml' file providing the new compatibles to the
> existing partition.yaml binding.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v10:
> - Drop binman,entry since it is likely not necessary
> - Put the description back
>
> Changes in v8:
> - Switch the patch ordering so the partition change comes first
>
> Changes in v7:
> - Adjust MAINTAINERS entry
> - Put compatible strings into the 'fixed-partition' binding
>
> Changes in v5:
> - Add mention of why 'binman' is the vendor
> - Drop 'select: false'
> - Tidy up the compatible setings
> - Use 'tfa-bl31' instead of 'atf-bl31'
>
> Changes in v4:
> - Correct selection of multiple compatible strings
>
> Changes in v3:
> - Drop fixed-partitions from the example
> - Use compatible instead of label
>
> Changes in v2:
> - Use plain partition@xxx for the node name
>
> .../bindings/mtd/partitions/binman.yaml | 53 +++++++++++++++++++
> .../bindings/mtd/partitions/partition.yaml | 21 ++++++++
> MAINTAINERS | 5 ++
> 3 files changed, 79 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/partitions/binman.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v3 2/2] phy: add driver for MediaTek XFI T-PHY
From: Daniel Golle @ 2024-03-28 20:12 UTC (permalink / raw)
To: Vinod Koul
Cc: Bc-bocun Chen, Steven Liu, John Crispin, Chunfeng Yun,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Qingfang Deng, SkyLake Huang, Philipp Zabel, linux-arm-kernel,
linux-mediatek, linux-phy, devicetree, linux-kernel, netdev
In-Reply-To: <ZgW8f1Rshi28YcvA@matsya>
Hi Vinod,
thank you for taking your time to review my submission!
On Fri, Mar 29, 2024 at 12:22:47AM +0530, Vinod Koul wrote:
> On 10-02-24, 02:10, Daniel Golle wrote:
> > Add driver for MediaTek's XFI T-PHY which can be found in the MT7988
>
> What does XFI mean?
https://en.wikipedia.org/wiki/XFP_transceiver#XFI
I chose this name because names of functions dealing with the phy in
the vendor driver are prefixed "xfi_pextp_".
The register space used by the phy is called "pextp", which could be
read as "_P_CI _ex_press _T_-_P_hy", and that is quite misleading as
this phy isn't used for anything related to PCIe, so I wanted to find
a better name.
XFI is still somehow related (as in: you would find the relevant
places using grep in the vendor driver when looking for that) and
seemed to at least somehow be aligned with the function of that phy:
Dealing with (up to) 10 Gbit/s Ethernet SerDes signals.
MediaTek calls phys with more than one potential use T-PHY or X-PHY:
The capital letter 'T' graphically connects 3 points, two of them
being on the upper side representing the internal components and one
on the lower side representing the single external interface.
Other vendors (like Marvell) call such things "combo phys".
Anyway, if anyone has better ideas regarding the naming, now is the
moment to speak up ;)
>
> > SoC. The XFI T-PHY is a 10 Gigabit/s Ethernet SerDes PHY with muxes on
> > the internal side to be used with either USXGMII PCS or LynxI PCS,
> > depending on the selected PHY interface mode.
> >
> > The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
> > PHY_INTERFACE_MODE_* corresponding to the supported modes:
> >
> > * USXGMII \
> > * 10GBase-R }- USXGMII PCS - XGDM \
> > * 5GBase-R / \
> > }- Ethernet MAC
> > * 2500Base-X \ /
> > * 1000Base-X }- LynxI PCS - GDM /
> > * Cisco SGMII (MAC side) /
> >
> > In order to work-around a performance issue present on the first of
> > two XFI T-PHYs present in MT7988, special tuning is applied which can be
> > selected by adding the 'mediatek,usxgmii-performance-errata' property to
> > the device tree node.
> >
> > There is no documentation for most registers used for the
> > analog/tuning part, however, most of the registers have been partially
> > reverse-engineered from MediaTek's SDK implementation (an opaque
> > sequence of 32-bit register writes) and descriptions for all relevant
> > digital registers and bits such as resets and muxes have been supplied
> > by MediaTek.
> >
> > Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > ---
> > v3: no changes
> > v2:
> > * use IO helpers from mtk-io.h instead of rolling my own
> > * use devm_clk_bulk_get()
> > * yse devm_platform_ioremap_resource()
> > * unify name and description everywhere
> > * invert bool is_xgmii into bool use_lynxi_pcs and add comments
> > describing the meaning of each of the stack variables
> > * not much we can do about remaining magic values unless MTK provides
> > definitions for them
> >
> >
> > MAINTAINERS | 1 +
> > drivers/phy/mediatek/Kconfig | 12 +
> > drivers/phy/mediatek/Makefile | 1 +
> > drivers/phy/mediatek/phy-mtk-xfi-tphy.c | 360 ++++++++++++++++++++++++
> > 4 files changed, 374 insertions(+)
> > create mode 100644 drivers/phy/mediatek/phy-mtk-xfi-tphy.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 4be2fd097f261..616b86e3e62fd 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -13776,6 +13776,7 @@ L: netdev@vger.kernel.org
> > S: Maintained
> > F: drivers/net/phy/mediatek-ge-soc.c
> > F: drivers/net/phy/mediatek-ge.c
> > +F: drivers/phy/mediatek/phy-mtk-xfi-tphy.c
> >
> > MEDIATEK I2C CONTROLLER DRIVER
> > M: Qii Wang <qii.wang@mediatek.com>
> > diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
> > index 3849b7c87d287..117d0e84c7360 100644
> > --- a/drivers/phy/mediatek/Kconfig
> > +++ b/drivers/phy/mediatek/Kconfig
> > @@ -13,6 +13,18 @@ config PHY_MTK_PCIE
> > callback for PCIe GEN3 port, it supports software efuse
> > initialization.
> >
> > +config PHY_MTK_XFI_TPHY
> > + tristate "MediaTek 10GE SerDes XFI T-PHY driver"
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
> > + depends on OF && OF_ADDRESS
>
> why both, is OF not enough?
As we are already also depending on HAS_IOMEM what is left there is
basically just a !SPARC dependency.
And that is probably a historic left-over and (according to commit
5ab5fc7e35705c from 2010...) should be re-evaluated. I'm happy to drop
OF_ADDRESS and keep only HAS_IOMEM, and we shall see if any of the
COMPILE_TESTs actually fails, given that everyone is fine with that.
>
> > + depends on HAS_IOMEM
> > + select GENERIC_PHY
> > + help
> > + Say 'Y' here to add support for MediaTek XFI T-PHY driver.
> > + The driver provides access to the Ethernet SerDes T-PHY supporting
> > + 1GE and 2.5GE modes via the LynxI PCS, and 5GE and 10GE modes
> > + via the USXGMII PCS found in MediaTek SoCs with 10G Ethernet.
> > +
> > config PHY_MTK_TPHY
> > tristate "MediaTek T-PHY Driver"
> > depends on ARCH_MEDIATEK || COMPILE_TEST
> > diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
> > index f6e24a47e0815..1b8088df71e84 100644
> > --- a/drivers/phy/mediatek/Makefile
> > +++ b/drivers/phy/mediatek/Makefile
> > @@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
> > obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
> > obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
> > obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
> > +obj-$(CONFIG_PHY_MTK_XFI_TPHY) += phy-mtk-xfi-tphy.o
> >
> > phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
> > phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
> > diff --git a/drivers/phy/mediatek/phy-mtk-xfi-tphy.c b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
> > new file mode 100644
> > index 0000000000000..551d6cee33f94
> > --- /dev/null
> > +++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
> > @@ -0,0 +1,360 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/* MediaTek 10GE SerDes XFI T-PHY driver
> > + *
> > + * Copyright (c) 2024 Daniel Golle <daniel@makrotopia.org>
> > + * Bc-bocun Chen <bc-bocun.chen@mediatek.com>
> > + * based on mtk_usxgmii.c and mtk_sgmii.c found in MediaTek's SDK (GPL-2.0)
> > + * Copyright (c) 2022 MediaTek Inc.
> > + * Author: Henry Yen <henry.yen@mediatek.com>
> > + */
> > +
> > +#include <linux/module.h>
> > +#include <linux/device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/of.h>
> > +#include <linux/io.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/phy.h>
> > +#include <linux/phy/phy.h>
> > +
> > +#include "phy-mtk-io.h"
> > +
> > +#define MTK_XFI_TPHY_NUM_CLOCKS 2
> > +
> > +#define REG_DIG_GLB_70 0x0070
> > +#define XTP_PCS_RX_EQ_IN_PROGRESS(x) FIELD_PREP(GENMASK(25, 24), (x))
> > +#define XTP_PCS_MODE_MASK GENMASK(17, 16)
> > +#define XTP_PCS_MODE(x) FIELD_PREP(GENMASK(17, 16), (x))
> > +#define XTP_PCS_RST_B BIT(15)
> > +#define XTP_FRC_PCS_RST_B BIT(14)
> > +#define XTP_PCS_PWD_SYNC_MASK GENMASK(13, 12)
> > +#define XTP_PCS_PWD_SYNC(x) FIELD_PREP(XTP_PCS_PWD_SYNC_MASK, (x))
> > +#define XTP_PCS_PWD_ASYNC_MASK GENMASK(11, 10)
> > +#define XTP_PCS_PWD_ASYNC(x) FIELD_PREP(XTP_PCS_PWD_ASYNC_MASK, (x))
> > +#define XTP_FRC_PCS_PWD_ASYNC BIT(8)
> > +#define XTP_PCS_UPDT BIT(4)
> > +#define XTP_PCS_IN_FR_RG BIT(0)
> > +
> > +#define REG_DIG_GLB_F4 0x00f4
> > +#define XFI_DPHY_PCS_SEL BIT(0)
> > +#define XFI_DPHY_PCS_SEL_SGMII FIELD_PREP(XFI_DPHY_PCS_SEL, 1)
> > +#define XFI_DPHY_PCS_SEL_USXGMII FIELD_PREP(XFI_DPHY_PCS_SEL, 0)
> > +#define XFI_DPHY_AD_SGDT_FRC_EN BIT(5)
> > +
> > +#define REG_DIG_LN_TRX_40 0x3040
> > +#define XTP_LN_FRC_TX_DATA_EN BIT(29)
> > +#define XTP_LN_TX_DATA_EN BIT(28)
> > +
> > +#define REG_DIG_LN_TRX_B0 0x30b0
> > +#define XTP_LN_FRC_TX_MACCK_EN BIT(5)
> > +#define XTP_LN_TX_MACCK_EN BIT(4)
> > +
> > +#define REG_ANA_GLB_D0 0x90d0
> > +#define XTP_GLB_USXGMII_SEL_MASK GENMASK(3, 1)
> > +#define XTP_GLB_USXGMII_SEL(x) FIELD_PREP(GENMASK(3, 1), (x))
> > +#define XTP_GLB_USXGMII_EN BIT(0)
> > +
> > +struct mtk_xfi_tphy {
> > + void __iomem *base;
> > + struct device *dev;
> > + struct reset_control *reset;
> > + struct clk_bulk_data clocks[MTK_XFI_TPHY_NUM_CLOCKS];
> > + bool da_war;
> > +};
> > +
> > +static void mtk_xfi_tphy_setup(struct mtk_xfi_tphy *xfi_tphy,
> > + phy_interface_t interface)
> > +{
> > + /* Override 10GBase-R tuning value if work-around is selected */
> > + bool da_war = (xfi_tphy->da_war && (interface == PHY_INTERFACE_MODE_10GBASER));
>
> why do you need braces around this?
Just for readability. They can safely be removed.
>
> > + /* Bools to make setting up values for specific PHY speeds easier */
> > + bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
> > + bool is_1g = (interface == PHY_INTERFACE_MODE_1000BASEX ||
> > + interface == PHY_INTERFACE_MODE_SGMII);
> > + bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
> > + interface == PHY_INTERFACE_MODE_USXGMII);
> > + bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
> > + /* Bool to configure input mux to either
> > + * - USXGMII PCS (64b/66b coding) for 5G/10G
> > + * - LynxI PCS (8b/10b coding) for 1G/2.5G
> > + */
> > + bool use_lynxi_pcs = (is_1g || is_2p5g);
>
> This is quite terrible to read, how about declaring variables first and
> then doing the initialization?
Ack.
>
> > +
> > + dev_dbg(xfi_tphy->dev, "setting up for mode %s\n", phy_modes(interface));
> > +
> > + /* Setup PLL setting */
> > + mtk_phy_update_bits(xfi_tphy->base + 0x9024, 0x100000, is_10g ? 0x0 : 0x100000);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x2020, 0x202000, is_5g ? 0x202000 : 0x0);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x2030, 0x500, is_1g ? 0x0 : 0x500);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x2034, 0xa00, is_1g ? 0x0 : 0xa00);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x2040, 0x340000, is_1g ? 0x200000 : 0x140000);
>
> magic numbers?
Yes, and not much we can do about them. According to MTK engineers (in
Cc) they also don't know what those numbers really mean in detail and
have only been given sequences of magic register writes for each
interface mode ([1], [2], [3], [4], [5]) by the upstream IP supplier
of the PHY. I then compared those write sequences with each others,
and observed the behavior of each register (as in: read their value
before and after the write operation; all of them read back the value
written to them) and rewrote the initialization as one function only
changing the bits actually needed (instead of always writing the complete
32-bit value). I've made sure that everything still works and Bc-bocun
Chen of MediaTek (also in Cc) then helped to label at least some of
the registers and bits there in as far as they are understood by
MediaTek.
[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/refs/heads/master/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c#172
[2]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/refs/heads/master/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_sgmii.c#284
[3]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/refs/heads/master/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_usxgmii.c#132
[4]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/refs/heads/master/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_usxgmii.c#246
[5]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/refs/heads/master/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_usxgmii.c#360
>
> > +
> > + /* Setup RXFE BW setting */
> > + mtk_phy_update_bits(xfi_tphy->base + 0x50f0, 0xc10, is_1g ? 0x410 : is_5g ? 0x800 : 0x400);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x50e0, 0x4000, is_5g ? 0x0 : 0x4000);
> > +
> > + /* Setup RX CDR setting */
> > + mtk_phy_update_bits(xfi_tphy->base + 0x506c, 0x30000, is_5g ? 0x0 : 0x30000);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x5070, 0x670000, is_5g ? 0x620000 : 0x50000);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x5074, 0x180000, is_5g ? 0x180000 : 0x0);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x5078, 0xf000400, is_5g ? 0x8000000 :
> > + 0x7000400);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x507c, 0x5000500, is_5g ? 0x4000400 :
> > + 0x1000100);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x5080, 0x1410, is_1g ? 0x400 : is_5g ? 0x1010 : 0x0);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x5084, 0x30300, is_1g ? 0x30300 :
> > + is_5g ? 0x30100 :
> > + 0x100);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x5088, 0x60200, is_1g ? 0x20200 :
> > + is_5g ? 0x40000 :
> > + 0x20000);
> > +
> > + /* Setting RXFE adaptation range setting */
> > + mtk_phy_update_bits(xfi_tphy->base + 0x50e4, 0xc0000, is_5g ? 0x0 : 0xc0000);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x50e8, 0x40000, is_5g ? 0x0 : 0x40000);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x50ec, 0xa00, is_1g ? 0x200 : 0x800);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x50a8, 0xee0000, is_5g ? 0x800000 :
> > + 0x6e0000);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x6004, 0x190000, is_5g ? 0x0 : 0x190000);
> > +
> > + if (is_10g)
> > + writel(0x01423342, xfi_tphy->base + 0x00f8);
> > + else if (is_5g)
> > + writel(0x00a132a1, xfi_tphy->base + 0x00f8);
> > + else if (is_2p5g)
> > + writel(0x009c329c, xfi_tphy->base + 0x00f8);
> > + else
> > + writel(0x00fa32fa, xfi_tphy->base + 0x00f8);
> > +
> > + /* Force SGDT_OUT off and select PCS */
> > + mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_F4,
> > + XFI_DPHY_AD_SGDT_FRC_EN | XFI_DPHY_PCS_SEL,
> > + XFI_DPHY_AD_SGDT_FRC_EN |
> > + (use_lynxi_pcs ? XFI_DPHY_PCS_SEL_SGMII :
> > + XFI_DPHY_PCS_SEL_USXGMII));
> > +
> > + /* Force GLB_CKDET_OUT */
> > + mtk_phy_set_bits(xfi_tphy->base + 0x0030, 0xc00);
> > +
> > + /* Force AEQ on */
> > + writel(XTP_PCS_RX_EQ_IN_PROGRESS(2) | XTP_PCS_PWD_SYNC(2) | XTP_PCS_PWD_ASYNC(2),
> > + xfi_tphy->base + REG_DIG_GLB_70);
> > +
> > + usleep_range(1, 5);
> > +
> > + /* Setup TX DA default value */
> > + mtk_phy_update_bits(xfi_tphy->base + 0x30b0, 0x30, 0x20);
> > + writel(0x00008a01, xfi_tphy->base + 0x3028);
> > + writel(0x0000a884, xfi_tphy->base + 0x302c);
> > + writel(0x00083002, xfi_tphy->base + 0x3024);
> > +
> > + /* Setup RG default value */
> > + if (use_lynxi_pcs) {
> > + writel(0x00011110, xfi_tphy->base + 0x3010);
> > + writel(0x40704000, xfi_tphy->base + 0x3048);
> > + } else {
> > + writel(0x00022220, xfi_tphy->base + 0x3010);
> > + writel(0x0f020a01, xfi_tphy->base + 0x5064);
> > + writel(0x06100600, xfi_tphy->base + 0x50b4);
> > + if (interface == PHY_INTERFACE_MODE_USXGMII)
> > + writel(0x40704000, xfi_tphy->base + 0x3048);
> > + else
> > + writel(0x47684100, xfi_tphy->base + 0x3048);
> > + }
> > +
> > + if (is_1g)
> > + writel(0x0000c000, xfi_tphy->base + 0x3064);
> > +
> > + /* Setup RX EQ initial value */
> > + mtk_phy_update_bits(xfi_tphy->base + 0x3050, 0xa8000000,
> > + (interface != PHY_INTERFACE_MODE_10GBASER) ? 0xa8000000 : 0x0);
> > + mtk_phy_update_bits(xfi_tphy->base + 0x3054, 0xaa,
> > + (interface != PHY_INTERFACE_MODE_10GBASER) ? 0xaa : 0x0);
> > +
> > + if (!use_lynxi_pcs)
> > + writel(0x00000f00, xfi_tphy->base + 0x306c);
> > + else if (is_2p5g)
> > + writel(0x22000f00, xfi_tphy->base + 0x306c);
> > + else
> > + writel(0x20200f00, xfi_tphy->base + 0x306c);
> > +
> > + mtk_phy_update_bits(xfi_tphy->base + 0xa008, 0x10000, da_war ? 0x10000 : 0x0);
> > +
> > + mtk_phy_update_bits(xfi_tphy->base + 0xa060, 0x50000, use_lynxi_pcs ? 0x50000 : 0x40000);
> > +
> > + /* Setup PHYA speed */
> > + mtk_phy_update_bits(xfi_tphy->base + REG_ANA_GLB_D0,
> > + XTP_GLB_USXGMII_SEL_MASK | XTP_GLB_USXGMII_EN,
> > + is_10g ? XTP_GLB_USXGMII_SEL(0) :
> > + is_5g ? XTP_GLB_USXGMII_SEL(1) :
> > + is_2p5g ? XTP_GLB_USXGMII_SEL(2) :
> > + XTP_GLB_USXGMII_SEL(3));
> > + mtk_phy_set_bits(xfi_tphy->base + REG_ANA_GLB_D0, XTP_GLB_USXGMII_EN);
> > +
> > + /* Release reset */
> > + mtk_phy_set_bits(xfi_tphy->base + REG_DIG_GLB_70,
> > + XTP_PCS_RST_B | XTP_FRC_PCS_RST_B);
> > + usleep_range(150, 500);
> > +
> > + /* Switch to P0 */
> > + mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70,
> > + XTP_PCS_IN_FR_RG |
> > + XTP_FRC_PCS_PWD_ASYNC |
> > + XTP_PCS_PWD_ASYNC_MASK |
> > + XTP_PCS_PWD_SYNC_MASK |
> > + XTP_PCS_UPDT,
> > + XTP_PCS_IN_FR_RG |
> > + XTP_FRC_PCS_PWD_ASYNC |
> > + XTP_PCS_UPDT);
> > + usleep_range(1, 5);
> > +
> > + mtk_phy_clear_bits(xfi_tphy->base + REG_DIG_GLB_70, XTP_PCS_UPDT);
> > + usleep_range(15, 50);
> > +
> > + if (use_lynxi_pcs) {
> > + /* Switch to Gen2 */
> > + mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70,
> > + XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
> > + XTP_PCS_MODE(1) | XTP_PCS_UPDT);
> > + } else {
> > + /* Switch to Gen3 */
> > + mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70,
> > + XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
> > + XTP_PCS_MODE(2) | XTP_PCS_UPDT);
> > + }
> > + usleep_range(1, 5);
> > +
> > + mtk_phy_clear_bits(xfi_tphy->base + REG_DIG_GLB_70, XTP_PCS_UPDT);
> > +
> > + usleep_range(100, 500);
> > +
> > + /* Enable MAC CK */
> > + mtk_phy_set_bits(xfi_tphy->base + REG_DIG_LN_TRX_B0, XTP_LN_TX_MACCK_EN);
> > + mtk_phy_clear_bits(xfi_tphy->base + REG_DIG_GLB_F4, XFI_DPHY_AD_SGDT_FRC_EN);
> > +
> > + /* Enable TX data */
> > + mtk_phy_set_bits(xfi_tphy->base + REG_DIG_LN_TRX_40,
> > + XTP_LN_FRC_TX_DATA_EN | XTP_LN_TX_DATA_EN);
> > + usleep_range(400, 1000);
> > +}
> > +
> > +static int mtk_xfi_tphy_set_mode(struct phy *phy, enum phy_mode mode, int
> > + submode)
> > +{
> > + struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
> > +
> > + if (mode != PHY_MODE_ETHERNET)
> > + return -EINVAL;
> > +
> > + switch (submode) {
> > + case PHY_INTERFACE_MODE_1000BASEX:
> > + case PHY_INTERFACE_MODE_2500BASEX:
> > + case PHY_INTERFACE_MODE_SGMII:
> > + case PHY_INTERFACE_MODE_5GBASER:
> > + case PHY_INTERFACE_MODE_10GBASER:
> > + case PHY_INTERFACE_MODE_USXGMII:
> > + mtk_xfi_tphy_setup(xfi_tphy, submode);
> > + return 0;
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +
> > +static int mtk_xfi_tphy_reset(struct phy *phy)
> > +{
> > + struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
> > +
> > + reset_control_assert(xfi_tphy->reset);
> > + usleep_range(100, 500);
> > + reset_control_deassert(xfi_tphy->reset);
> > + usleep_range(1, 10);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_xfi_tphy_power_on(struct phy *phy)
> > +{
> > + struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
> > +
> > + return clk_bulk_prepare_enable(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
> > +}
> > +
> > +static int mtk_xfi_tphy_power_off(struct phy *phy)
> > +{
> > + struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
> > +
> > + clk_bulk_disable_unprepare(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct phy_ops mtk_xfi_tphy_ops = {
> > + .power_on = mtk_xfi_tphy_power_on,
> > + .power_off = mtk_xfi_tphy_power_off,
> > + .set_mode = mtk_xfi_tphy_set_mode,
> > + .reset = mtk_xfi_tphy_reset,
> > + .owner = THIS_MODULE,
> > +};
> > +
> > +static int mtk_xfi_tphy_probe(struct platform_device *pdev)
> > +{
> > + struct device_node *np = pdev->dev.of_node;
> > + struct phy_provider *phy_provider;
> > + struct mtk_xfi_tphy *xfi_tphy;
> > + struct phy *phy;
> > + int ret;
> > +
> > + if (!np)
> > + return -ENODEV;
> > +
> > + xfi_tphy = devm_kzalloc(&pdev->dev, sizeof(*xfi_tphy), GFP_KERNEL);
> > + if (!xfi_tphy)
> > + return -ENOMEM;
> > +
> > + xfi_tphy->base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(xfi_tphy->base))
> > + return PTR_ERR(xfi_tphy->base);
> > +
> > + xfi_tphy->dev = &pdev->dev;
> > + xfi_tphy->clocks[0].id = "topxtal";
> > + xfi_tphy->clocks[1].id = "xfipll";
> > + ret = devm_clk_bulk_get(&pdev->dev, MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
> > + if (ret)
> > + return ret;
> > +
> > + xfi_tphy->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > + if (IS_ERR(xfi_tphy->reset))
> > + return PTR_ERR(xfi_tphy->reset);
> > +
> > + xfi_tphy->da_war = of_property_read_bool(np, "mediatek,usxgmii-performance-errata");
> > +
> > + phy = devm_phy_create(&pdev->dev, NULL, &mtk_xfi_tphy_ops);
> > + if (IS_ERR(phy))
> > + return PTR_ERR(phy);
> > +
> > + phy_set_drvdata(phy, xfi_tphy);
> > + phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
> > +
> > + return PTR_ERR_OR_ZERO(phy_provider);
> > +}
> > +
> > +static const struct of_device_id mtk_xfi_tphy_match[] = {
> > + { .compatible = "mediatek,mt7988-xfi-tphy", },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_xfi_tphy_match);
> > +
> > +static struct platform_driver mtk_xfi_tphy_driver = {
> > + .probe = mtk_xfi_tphy_probe,
> > + .driver = {
> > + .name = "mtk-xfi-tphy",
> > + .of_match_table = mtk_xfi_tphy_match,
> > + },
> > +};
> > +module_platform_driver(mtk_xfi_tphy_driver);
> > +
> > +MODULE_DESCRIPTION("MediaTek 10GE SerDes XFI T-PHY driver");
> > +MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
> > +MODULE_AUTHOR("Bc-bocun Chen <bc-bocun.chen@mediatek.com>");
> > +MODULE_LICENSE("GPL");
> > --
> > 2.43.0
>
> --
> ~Vinod
^ permalink raw reply
* [PATCH 3/3] arm64: dts: freescale: Add device tree for Emcraft Systems NavQ+ Kit
From: Gilles Talis @ 2024-03-28 20:23 UTC (permalink / raw)
To: devicetree, imx, linux-arm-kernel
Cc: conor+dt, krzysztof.kozlowski+dt, robh, shawnguo, festevam, alex,
Gilles Talis
In-Reply-To: <20240328202320.187596-1-gilles.talis@gmail.com>
The Emcraft Systems NavQ+ kit is a mobile robotics platform
based on NXP i.MX8 MPlus SoC.
The following interfaces and devices are enabled:
- eMMC
- Gigabit Ethernet
- RTC
- SD-Card
- UART console
Signed-off-by: Gilles Talis <gilles.talis@gmail.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../arm64/boot/dts/freescale/imx8mp-navqp.dts | 435 ++++++++++++++++++
2 files changed, 436 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 045250d0a040..bf99864c0bc4 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
new file mode 100644
index 000000000000..8182e71008f8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
@@ -0,0 +1,435 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Emcraft Systems
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mp.dtsi"
+
+/ {
+ model = "Emcraft Systems i.MX8MPlus NavQ+ Kit";
+ compatible = "emcraft,imx8mp-navqp", "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ status {
+ label = "status";
+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <10000>;
+ qca,disable-smarteee;
+ qca,disable-hibernation-mode;
+ vddio-supply = <&vddio>;
+
+ vddio: vddio-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK5 {
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ };
+};
+
+&uart2 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* SD Card */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x110
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c6: i2c6grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x400001c3
+ MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--
2.39.2
^ permalink raw reply related
* [PATCH 2/3] dt-bindings: arm: Add Emcraft Systems i.MX8M Plus NavQ+ Kit
From: Gilles Talis @ 2024-03-28 20:23 UTC (permalink / raw)
To: devicetree, imx, linux-arm-kernel
Cc: conor+dt, krzysztof.kozlowski+dt, robh, shawnguo, festevam, alex,
Gilles Talis
In-Reply-To: <20240328202320.187596-1-gilles.talis@gmail.com>
Add DT compatible string for Emcraft NavQ+ kit based on
the i.MX8M Plus SoC from NXP
Signed-off-by: Gilles Talis <gilles.talis@gmail.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 0027201e19f8..cec1b31d0792 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1050,6 +1050,7 @@ properties:
- enum:
- beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit
- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
+ - emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit
- fsl,imx8mp-evk # i.MX8MP EVK Board
- gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
--
2.39.2
^ permalink raw reply related
* [PATCH 1/3] dt-bindings: vendor-prefixes: Add Emcraft Systems
From: Gilles Talis @ 2024-03-28 20:23 UTC (permalink / raw)
To: devicetree, imx, linux-arm-kernel
Cc: conor+dt, krzysztof.kozlowski+dt, robh, shawnguo, festevam, alex,
Gilles Talis
In-Reply-To: <20240328202320.187596-1-gilles.talis@gmail.com>
Add an entry for Emcraft Systems (https://www.emcraft.com/)
Signed-off-by: Gilles Talis <gilles.talis@gmail.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index b97d298b3eb6..8b978c6f1dfd 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -438,6 +438,8 @@ patternProperties:
description: Dongguan EmbedFire Electronic Technology Co., Ltd.
"^embest,.*":
description: Shenzhen Embest Technology Co., Ltd.
+ "^emcraft,.*":
+ description: Emcraft Systems
"^emlid,.*":
description: Emlid, Ltd.
"^emmicro,.*":
--
2.39.2
^ permalink raw reply related
* [PATCH 0/3] Add support for Emcraft Systems NavQ+ kit
From: Gilles Talis @ 2024-03-28 20:23 UTC (permalink / raw)
To: devicetree, imx, linux-arm-kernel
Cc: conor+dt, krzysztof.kozlowski+dt, robh, shawnguo, festevam, alex,
Gilles Talis
Hello
This series adds a device tree file for the Emcraft Systems NavQ+ kit [1]
The first patch adds a new vendor prefix for Emcraft Systems
The second one adds the board to the arm/fsl.yaml DT bindings.
Last patch adds device tree file for the kit.
[1] https://www.emcraft.com/products/1222
Gilles Talis (3):
dt-bindings: vendor-prefixes: Add Emcraft Systems
dt-bindings: arm: Add Emcraft Systems i.MX8M Plus NavQ+ Kit
arm64: dts: freescale: Add device tree for Emcraft Systems NavQ+ Kit
.../devicetree/bindings/arm/fsl.yaml | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../arm64/boot/dts/freescale/imx8mp-navqp.dts | 435 ++++++++++++++++++
4 files changed, 439 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
base-commit: 4cece764965020c22cff7665b18a012006359095
--
2.39.2
^ permalink raw reply
* Re: [PATCH 18/23] dt-bindings: media: imx258: Add alternate compatible strings
From: kernel test robot @ 2024-03-28 20:05 UTC (permalink / raw)
To: git, linux-media
Cc: oe-kbuild-all, dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, Luigi311
In-Reply-To: <20240327231710.53188-19-git@luigi311.com>
Hi,
kernel test robot noticed the following build warnings:
[auto build test WARNING on media-tree/master]
[also build test WARNING on linuxtv-media-stage/master linus/master v6.9-rc1 next-20240328]
[cannot apply to sailus-media-tree/streams]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/git-luigi311-com/media-i2c-imx258-Remove-unused-defines/20240328-072629
base: git://linuxtv.org/media_tree.git master
patch link: https://lore.kernel.org/r/20240327231710.53188-19-git%40luigi311.com
patch subject: [PATCH 18/23] dt-bindings: media: imx258: Add alternate compatible strings
compiler: loongarch64-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240329/202403290352.sV38QfhQ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403290352.sV38QfhQ-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml: properties:compatible: [{'enum': ['sony,imx258', 'sony,imx258-pdaf']}] is not of type 'object', 'boolean'
from schema $id: http://json-schema.org/draft-07/schema#
>> Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml: properties:compatible: [{'enum': ['sony,imx258', 'sony,imx258-pdaf']}] is not of type 'object', 'boolean'
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
--
>> Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml: ignoring, error in schema: properties: compatible
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v5 09/11] regulator: tps6594-regulator: Add TI TPS65224 PMIC regulators
From: Mark Brown @ 2024-03-28 19:55 UTC (permalink / raw)
To: Bhargav Raviprakash
Cc: linux-kernel, m.nirmaladevi, lee, robh+dt, krzysztof.kozlowski+dt,
conor+dt, jpanis, devicetree, arnd, gregkh, lgirdwood,
linus.walleij, linux-gpio, linux-arm-kernel, nm, vigneshr, kristo,
eblanc
In-Reply-To: <20240328124016.161959-10-bhargav.r@ltts.com>
[-- Attachment #1: Type: text/plain, Size: 503 bytes --]
On Thu, Mar 28, 2024 at 06:10:14PM +0530, Bhargav Raviprakash wrote:
> From: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com>
>
> Add support for TPS65224 regulators (bucks and LDOs) to TPS6594 driver as
> they have significant functional overlap. TPS65224 PMIC has 4 buck
> regulators and 3 LDOs. BUCK12 can operate in dual phase.
> The output voltages are configurable and are meant to supply power to the
> main processor and other components.
Reviewed-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [RFC PATCH 06/13] pinctrl: renesas: pinctrl-rzg2l: Make cfg to u64 in struct rzg2l_variable_pin_cfg
From: Lad, Prabhakar @ 2024-03-28 19:53 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Magnus Damm, linux-renesas-soc, linux-gpio, devicetree,
linux-kernel, Fabrizio Castro, Lad Prabhakar
In-Reply-To: <CAMuHMdWdaiSer10agMytpv9h_gb4bEpEHjThDwRkMShXkKMxzA@mail.gmail.com>
Hi Geert,
Thank you for the review.
On Thu, Mar 28, 2024 at 2:14 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, Mar 26, 2024 at 11:30 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Now that we have updated the macro PIN_CFG_MASK to allow for the maximum
> > configuration bits, update the size of 'cfg' to 'u64' in the
> > 'struct rzg2l_variable_pin_cfg'.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > @@ -241,7 +241,7 @@ struct rzg2l_dedicated_configs {
> > * @pin: port pin
> > */
> > struct rzg2l_variable_pin_cfg {
> > - u32 cfg:20;
> > + u64 cfg:46;
> > u32 port:5;
> > u32 pin:3;
>
> Doesn't this store the 46 cfg bits in a 64-bit word, and the 8 port
> and pin bits in a different 32-bit word? Worse, you'll get 4 bytes
> of padding at the end of the structure.
Agreed.
> Changing the port and pin to u64 should make sure everything is
> stored together in a single 64-bit word.
>
I'll change the port and pin to u64 .
Cheers,
Prabhakar
^ permalink raw reply
* Re: [RFC PATCH 13/13] pinctrl: renesas: pinctrl-rzg2l: Add support for RZ/V2H SoC
From: Lad, Prabhakar @ 2024-03-28 19:51 UTC (permalink / raw)
To: claudiu beznea
Cc: Geert Uytterhoeven, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-renesas-soc,
linux-gpio, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
In-Reply-To: <25bc9ceb-c5cb-40a2-8c3d-d9666b88546c@tuxon.dev>
Hi Claudiu,
Thank you for the review.
On Thu, Mar 28, 2024 at 8:04 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
>
> Hi, Prabhakar,
>
> On 27.03.2024 00:28, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add pinctrl driver support for RZ/V2H(P) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 483 +++++++++++++++++++++++-
> > 1 file changed, 481 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > index 6f0c85bb97a8..716c11ca5a8f 100644
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > @@ -59,6 +59,13 @@
> > #define PIN_CFG_OEN BIT(15)
> > #define PIN_CFG_VARIABLE BIT(16)
> > #define PIN_CFG_NOGPIO_INT BIT(17)
> > +#define PIN_CFG_OPEN_DRAIN BIT(18)
> > +#define PIN_CFG_SCHMIT_CTRL BIT(19)
> > +#define PIN_CFG_ELC BIT(20)
> > +#define PIN_CFG_IOLH_1 BIT(21)
> > +#define PIN_CFG_IOLH_2 BIT(22)
> > +#define PIN_CFG_IOLH_3 BIT(23)
> > +#define PIN_CFG_IOLH_4 BIT(24)
> >
> > #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
> > (PIN_CFG_IOLH_##group | \
> > @@ -70,6 +77,10 @@
> > #define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
> > PIN_CFG_SR)
> >
> > +#define RZV2H_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
> > + PIN_CFG_OPEN_DRAIN | \
> > + PIN_CFG_SR)
> > +
> > #define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
> > PIN_CFG_SOFT_PS)
> >
> > @@ -133,6 +144,8 @@
> >
> > #define PWPR_B0WI BIT(7) /* Bit Write Disable */
> > #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
> > +#define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable */
> > +#define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable */
> >
> > #define PM_MASK 0x03
> > #define PFC_MASK 0x07
> > @@ -149,6 +162,19 @@
> > #define RZG2L_TINT_IRQ_START_INDEX 9
> > #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
> >
> > +/* Custom pinconf parameters */
> > +#define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1)
> > +
> > +static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = {
> > + { "renesas-rzv2h,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },
> > +};
> > +
> > +#ifdef CONFIG_DEBUG_FS
> > +static const struct pin_config_item renesas_rzv2h_conf_items[] = {
> > + PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true),
> > +};
> > +#endif
> > +
> > /* Read/write 8 bits register */
> > #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \
> > do { \
> > @@ -324,6 +350,8 @@ struct rzg2l_pinctrl {
> > spinlock_t lock; /* lock read/write registers */
> > struct mutex mutex; /* serialize adding groups and functions */
> >
> > + raw_spinlock_t pwpr_lock; /* serialize PWPR register access */
> > +
> > struct rzg2l_pinctrl_pin_settings *settings;
> > struct rzg2l_pinctrl_reg_cache *cache;
> > struct rzg2l_pinctrl_reg_cache *dedicated_cache;
> > @@ -348,6 +376,79 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
> > return 0;
> > }
> >
> > +static const struct rzg2l_variable_pin_cfg r9a09g057_variable_pin_cfg[] = {
> > + {
> > + .port = 9,
> > + .pin = 0,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL,
> > + },
> > + {
> > + .port = 9,
> > + .pin = 1,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL,
> > + },
> > + {
> > + .port = 9,
> > + .pin = 2,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL,
> > + },
> > + {
> > + .port = 9,
> > + .pin = 3,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL,
> > + },
> > + {
> > + .port = 9,
> > + .pin = 4,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL,
> > + },
> > + {
> > + .port = 9,
> > + .pin = 5,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL,
> > + },
> > + {
> > + .port = 9,
> > + .pin = 6,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL,
> > + },
> > + {
> > + .port = 9,
> > + .pin = 7,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL,
> > + },
> > + {
> > + .port = 11,
> > + .pin = 0,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL,
> > + },
> > + {
> > + .port = 11,
> > + .pin = 1,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL | PIN_CFG_IEN,
> > + },
> > + {
> > + .port = 11,
> > + .pin = 2,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL | PIN_CFG_IEN,
> > + },
> > + {
> > + .port = 11,
> > + .pin = 3,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL | PIN_CFG_IEN,
> > + },
> > + {
> > + .port = 11,
> > + .pin = 4,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL | PIN_CFG_IEN,
> > + },
> > + {
> > + .port = 11,
> > + .pin = 5,
> > + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL | PIN_CFG_IEN,
> > + },
> > +};
> > +
> > #ifdef CONFIG_RISCV
> > static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = {
> > {
> > @@ -474,6 +575,19 @@ static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, void __iomem *
> > writeb(val, addr);
> > }
> >
> > +static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, void __iomem *addr)
> > +{
> > + const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
> > + u8 pwpr;
> > +
> > + raw_spin_lock(&pctrl->pwpr_lock);
> > + pwpr = readb(pctrl->base + regs->pwpr);
> > + writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr);
>
> What about having a device specific function that locks/unlocks the PWPR,
> this part ^ being the lock.
>
>
OK, ill have SoC specific function to lock/unlock.
>
> > + writeb(val, addr);
>
> And this starting here:
>
> > + writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
> > + raw_spin_unlock(&pctrl->pwpr_lock);
>
> ending here: the unlock function. It should generate les diffs at least in
> this patch.
>
> And you can add, were needed:
>
> if (pctrl->pwpr_lock_function)
> pctrl->pwpr_lock_function();
>
> write(val, addr);
>
> if (pctrl->pwpr_unlock_function)
> pctrl->pwpr_unlock_function();
>
>
> With this you can avoid adding rzv2h_pinctrl_set_pfc_mode() which is alomst
> identical w/ rzg2l_pinctrl_set_pfc_mode(), or adding
> rzv2h_pinctrl_pm_setup_pfc() almost identical with
> rzg2l_pinctrl_pm_setup_pfc().
>
Agreed.
> > +}
> > +
> > static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
> > u8 pin, u8 off, u8 func)
> > {
> > @@ -512,6 +626,47 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
> > spin_unlock_irqrestore(&pctrl->lock, flags);
> > };
> >
> > +static void rzv2h_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
> > + u8 pin, u8 off, u8 func)
> > +{
> > + const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
> > + unsigned long flags;
> > + u32 reg;
> > + u8 pwpr;
> > +
> > + spin_lock_irqsave(&pctrl->lock, flags);
> > +
> > + /* Set pin to 'Non-use (Hi-Z input protection)' */
> > + reg = readw(pctrl->base + PM(off));
> > + reg &= ~(PM_MASK << (pin * 2));
> > + writew(reg, pctrl->base + PM(off));
> > +
> > + /* Set the PWPR register to allow PFC and PMC register to write */
> > + raw_spin_lock(&pctrl->pwpr_lock);
> > + pwpr = readb(pctrl->base + regs->pwpr);
> > + writeb(PWPR_PFCWE | pwpr, pctrl->base + regs->pwpr);
> > +
> > + /* Temporarily switch to GPIO mode with PMC register */
> > + reg = readb(pctrl->base + PMC(off));
> > + writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
> > +
> > + /* Select Pin function mode with PFC register */
> > + reg = readl(pctrl->base + PFC(off));
> > + reg &= ~(PFC_MASK << (pin * 4));
> > + writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
> > +
> > + /* Switch to Peripheral pin function with PMC register */
> > + reg = readb(pctrl->base + PMC(off));
> > + writeb(reg | BIT(pin), pctrl->base + PMC(off));
> > +
> > + /* Set the PWPR register to be write-protected */
> > + pwpr = readb(pctrl->base + regs->pwpr);
> > + writeb(pwpr & ~PWPR_PFCWE, pctrl->base + regs->pwpr);
> > + raw_spin_unlock(&pctrl->pwpr_lock);
> > +
> > + spin_unlock_irqrestore(&pctrl->lock, flags);
> > +};
> > +
> > static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
> > unsigned int func_selector,
> > unsigned int group_selector)
> > @@ -1087,14 +1242,26 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8
> > return 0;
> > }
> >
> > +static u32 rzv2h_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
> > +{
> > + /* stub */
> > + return 0;
> > +}
> > +
> > +static int rzv2h_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
> > +{
> > + /* stub */
> > + return -EINVAL;
> > +}
> > +
>
> What about chekcing:
> if (pctrl->data->read_oen)
> ret = pctrl->data->read_oen()
>
> if (pctrl->data->write_oen)
> ret = pctrl->data->write_oen()
>
> Accross the driver. This will avoid adding stubs each time suppor for a new
> IP is added.
>
I plan to fill this up in a non-rfc series.
> > static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
> > unsigned int _pin,
> > unsigned long *config)
> > {
> > struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> > - enum pin_config_param param = pinconf_to_config_param(*config);
> > const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
> > const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
> > + u32 param = pinconf_to_config_param(*config);
> > u64 *pin_data = pin->drv_data;
> > unsigned int arg = 0;
> > u32 off, cfg;
> > @@ -1180,6 +1347,30 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
> > break;
> > }
> >
> > + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: {
> > + u8 val;
> > +
> > + if (!(cfg & (PIN_CFG_IOLH_1 | PIN_CFG_IOLH_2 | PIN_CFG_IOLH_3 | PIN_CFG_IOLH_4)))
> > + return -EINVAL;
> > +
> > + val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
> > + switch (val) {
> > + case 0:
> > + arg = 1;
> > + break;
> > + case 1:
> > + arg = 2;
> > + break;
> > + case 2:
> > + arg = 4;
> > + break;
> > + default:
> > + arg = 6;
> > + break;
> > + }
> > + break;
> > + }
> > +
> > default:
> > return -ENOTSUPP;
> > }
> > @@ -1199,9 +1390,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
> > const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
> > struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
> > u64 *pin_data = pin->drv_data;
> > - enum pin_config_param param;
> > unsigned int i, arg, index;
> > u32 cfg, off;
> > + u32 param;
> > int ret;
> > u8 bit;
> >
> > @@ -1283,6 +1474,32 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
> > rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
> > break;
> >
> > + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
> > + arg = pinconf_to_config_argument(_configs[i]);
> > +
> > + if (!(cfg & (PIN_CFG_IOLH_1 | PIN_CFG_IOLH_2 |
> > + PIN_CFG_IOLH_3 | PIN_CFG_IOLH_4)))
> > + return -EINVAL;
> > +
> > + switch (arg) {
> > + case 1:
> > + index = 0;
> > + break;
> > + case 2:
> > + index = 1;
> > + break;
> > + case 4:
> > + index = 2;
> > + break;
> > + case 6:
> > + index = 3;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > + rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
> > + break;
> > +
> > default:
> > return -EOPNOTSUPP;
> > }
> > @@ -1730,6 +1947,38 @@ static const u64 r9a08g045_gpio_configs[] = {
> > RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
> > };
> >
> > +static const char * const rzv2h_gpio_names[] = {
> > + "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
> > + "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
> > + "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
> > + "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
> > + "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
> > + "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
> > + "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
> > + "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
> > + "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
> > + "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97",
> > + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
> > + "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
> > +};
> > +
> > +static const u64 r9a09g057_gpio_configs[] = {
> > + RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P0 */
> > + RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P1 */
> > + RZG2L_GPIO_PORT_PACK(2, 0x22, RZV2H_MPXED_PIN_FUNCS(4)), /* P2 */
> > + RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P3 */
> > + RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P4 */
> > + RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P5 */
> > + RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL |
> > + PIN_CFG_ELC), /* P6 */
> > + RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P7 */
> > + RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL |
> > + PIN_CFG_ELC), /* P8 */
> > + RZG2L_GPIO_PORT_PACK(8, 0x29, PIN_CFG_VARIABLE), /* P9 */
> > + RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* PA */
> > + RZG2L_GPIO_PORT_PACK(6, 0x2b, PIN_CFG_VARIABLE), /* PB */
> > +};
> > +
> > static const struct {
> > struct rzg2l_dedicated_configs common[35];
> > struct rzg2l_dedicated_configs rzg2l_pins[7];
> > @@ -1856,6 +2105,139 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
> > PIN_CFG_IO_VMC_SD1)) },
> > };
> >
> > +static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
> > + { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
> > + PIN_CFG_FILCLKSEL)) },
> > + { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_1 | PIN_CFG_SR |
> > + PIN_CFG_IEN)) },
> > + { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_1 | PIN_CFG_SR)) },
> > + { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_1 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_1 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_1 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_1 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD | PIN_CFG_OEN)) },
> > + { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD | PIN_CFG_OEN)) },
> > + { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_1 | PIN_CFG_SR |
> > + PIN_CFG_PUPD | PIN_CFG_OEN)) },
> > + { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_1 | PIN_CFG_SR |
> > + PIN_CFG_PUPD | PIN_CFG_OEN)) },
> > + { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
> > + { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
> > + { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
> > + { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR)) },
> > + { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR)) },
> > + { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IOLH_2 | PIN_CFG_PUPD)) },
> > + { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR)) },
> > + { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD1_DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD1_DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD1_DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "SD1_DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_1 | PIN_CFG_SR)) },
> > + { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_1 | PIN_CFG_SR)) },
> > + { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_IEN | PIN_CFG_PUPD)) },
> > + { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
> > + { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
> > + { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
> > + { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD | PIN_CFG_OEN)) },
> > + { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
> > + { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
> > + { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
> > + { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
> > + { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
> > + { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
> > + { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_SR | PIN_CFG_IEN |
> > + PIN_CFG_PUPD)) },
> > + { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
> > + { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
> > + { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
> > + { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD | PIN_CFG_OEN)) },
> > + { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
> > + { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
> > + { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR |
> > + PIN_CFG_PUPD)) },
> > + { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
> > + { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
> > + { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
> > + { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
> > +};
> > +
> > static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
> > {
> > const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
> > @@ -2380,6 +2762,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
> > BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
> > ARRAY_SIZE(rzg2l_gpio_names));
> >
> > + BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
> > + ARRAY_SIZE(rzv2h_gpio_names));
> > +
> > pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
> > if (!pctrl)
> > return -ENOMEM;
> > @@ -2402,6 +2787,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
> >
> > spin_lock_init(&pctrl->lock);
> > spin_lock_init(&pctrl->bitmap_lock);
> > + raw_spin_lock_init(&pctrl->pwpr_lock);
> > mutex_init(&pctrl->mutex);
> > atomic_set(&pctrl->wakeup_path, 0);
> >
> > @@ -2578,6 +2964,65 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
> > writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
> > }
> >
> > +static void rzv2h_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
>
> Have you managed to test this?
>
No S2R isn't tested and is just added for completeness, I wonder if we
should have a SoC specific flag "pm_supported" for this, as apart from
RZ/G3S nothing has been tested I believe?
Cheers,
Prabhakar
^ permalink raw reply
* Re: [RFC PATCH 08/13] pinctrl: renesas: pinctrl-rzg2l: Add function pointers for writing to PFC
From: Lad, Prabhakar @ 2024-03-28 19:45 UTC (permalink / raw)
To: claudiu beznea
Cc: Geert Uytterhoeven, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-renesas-soc,
linux-gpio, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
In-Reply-To: <3d3a651e-2853-4b5b-bc8a-6f494250d9c7@tuxon.dev>
Hi Claudiu,
Thank you for the review.
On Thu, Mar 28, 2024 at 8:13 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
>
>
>
> On 28.03.2024 10:02, claudiu beznea wrote:
> > Hi, Prabhakar,
> >
> > On 27.03.2024 00:28, Prabhakar wrote:
> >> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>
> >> On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers.
> >> However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls
> >> writing to both PFC and PMC registers. To accommodate these differences
> >> across SoC variants, introduce set_pfc_mode() and pm_set_pfc() function
> >> pointers.
> >
> > I think the overall code can be simplified if you add 1 function that does
> > the lock/unlock for PWPR. See patch 13.
>
> I meant to say one function for lock and one for unlock.
>
I agree, let me remodel it that way.
Cheers,
Prabhakar
^ permalink raw reply
* Re: [RFC PATCH v2 3/5] dt-bindings: clock: meson: document A1 SoC audio clock controller driver
From: Jan Dakinevich @ 2024-03-28 19:43 UTC (permalink / raw)
To: Krzysztof Kozlowski, Neil Armstrong, Jerome Brunet,
Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kevin Hilman, Martin Blumenstingl, Philipp Zabel,
linux-amlogic, linux-clk, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <cff5e036-7f7c-4270-be0c-f49b196a502b@linaro.org>
On 3/28/24 12:01, Krzysztof Kozlowski wrote:
> On 28/03/2024 02:08, Jan Dakinevich wrote:
>> Add device tree bindings for A1 SoC audio clock and reset controllers.
>>
>> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> ---
>
>> +title: Amlogic A1 Audio Clock Control Unit and Reset Controller
>> +
>> +maintainers:
>> + - Neil Armstrong <neil.armstrong@linaro.org>
>> + - Jerome Brunet <jbrunet@baylibre.com>
>> + - Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - amlogic,a1-audio-clkc
>> + - amlogic,a1-audio2-clkc
>
> What is "2"?
>
This is the second clock controller. I couldn't think of a better name.
> If there is going to be any new version/resend:
Definitely, this is not the final version. Thank you for comments!
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> + '#reset-cells':
>> + const: 1
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + minItems: 6
>> + maxItems: 7
>> +
>> + clock-names:
>> + minItems: 6
>> + maxItems: 7
>> +
>> +required:
>> + - compatible
>> + - '#clock-cells'
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - amlogic,a1-audio-clkc
>> + then:
>> + properties:
>> + clocks:
>> + items:
>> + - description: input core clock
>> + - description: input main peripheral bus clock
>> + - description: input dds_in
>> + - description: input fixed pll div2
>> + - description: input fixed pll div3
>> + - description: input hifi_pll
>> + - description: input oscillator (usually at 24MHz)
>> + clocks-names:
>> + items:
>> + - const: core
>> + - const: pclk
>> + - const: dds_in
>> + - const: fclk_div2
>> + - const: fclk_div3
>> + - const: hifi_pll
>> + - const: xtal
>> + required:
>> + - '#reset-cells'
>> + else:
>> + properties:
>> + clocks:
>> + items:
>> + - description: input main peripheral bus clock
>> + - description: input dds_in
>> + - description: input fixed pll div2
>> + - description: input fixed pll div3
>> + - description: input hifi_pll
>> + - description: input oscillator (usually at 24MHz)
>> + clock-names:
>> + items:
>> + - const: pclk
>> + - const: dds_in
>> + - const: fclk_div2
>> + - const: fclk_div3
>> + - const: hifi_pll
>> + - const: xtal
>
> #reset-cells: false
>
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
>> + #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
>> + #include <dt-bindings/clock/amlogic,a1-audio-clkc.h>
>> + audio {
>
> If there is going to be any new version/resend:
> soc {
>
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + clkc_audio: audio-clock-controller@fe050000 {
>
> Node names should be generic. See also an explanation and list of
> examples (not exhaustive) in DT specification:
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> So: clock-controller
>
>> + compatible = "amlogic,a1-audio-clkc";
>> + reg = <0x0 0xfe050000 0x0 0xb0>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + clocks = <&clkc_audio2 AUD2_CLKID_AUDIOTOP>,
>> + <&clkc_periphs CLKID_AUDIO>,
>> + <&clkc_periphs CLKID_DDS_IN>,
>> + <&clkc_pll CLKID_FCLK_DIV2>,
>> + <&clkc_pll CLKID_FCLK_DIV3>,
>> + <&clkc_pll CLKID_HIFI_PLL>,
>> + <&xtal>;
>> + clock-names = "core",
>> + "pclk",
>> + "dds_in",
>> + "fclk_div2",
>> + "fclk_div3",
>> + "hifi_pll",
>> + "xtal";
>> + };
>> +
>> + clkc_audio2: audio-clock-controller@fe054800 {
>
> clock-controller
> (so I expect resend)
>
>> + compatible = "amlogic,a1-audio2-clkc";
>> + reg = <0x0 0xfe054800 0x0 0x20>;
>> + #clock-cells = <1>;
>> + clocks = <&clkc_periphs CLKID_AUDIO>,
>> + <&clkc_periphs CLKID_DDS_IN>,
>> + <&clkc_pll CLKID_FCLK_DIV2>,
>> + <&clkc_pll CLKID_FCLK_DIV3>,
>> + <&clkc_pll CLKID_HIFI_PLL>,
>> + <&xtal>;
>> + clock-names = "pclk",
>> + "dds_in",
>> + "fclk_div2",
>> + "fclk_div3",
>> + "hifi_pll",
>> + "xtal";
>> + };
>> + };
>> diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
>> new file mode 100644
>> index 000000000000..b30df3b1ae08
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
>> @@ -0,0 +1,122 @@
>> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
>> +/*
>> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
>> + *
>> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> + */
>> +
>> +#ifndef __A1_AUDIO_CLKC_BINDINGS_H
>> +#define __A1_AUDIO_CLKC_BINDINGS_H
>> +
>> +#define AUD_CLKID_DDR_ARB 1
>> +#define AUD_CLKID_TDMIN_A 2
>> +#define AUD_CLKID_TDMIN_B 3
>> +#define AUD_CLKID_TDMIN_LB 4
>
> Why both clock controllers have the same clocks? This is confusing. It
> seems you split same block into two!
>
> Best regards,
> Krzysztof
>
--
Best regards
Jan Dakinevich
^ permalink raw reply
* Re: [RFC PATCH 07/13] pinctrl: renesas: pinctrl-rzg2l: Validate power registers for SD and ETH
From: Lad, Prabhakar @ 2024-03-28 19:40 UTC (permalink / raw)
To: claudiu beznea
Cc: Geert Uytterhoeven, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-renesas-soc,
linux-gpio, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
In-Reply-To: <c200e87e-1c65-4926-9307-16229e90594e@tuxon.dev>
Hi Claudiu,
Thank you for the review.
On Thu, Mar 28, 2024 at 8:01 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
>
> Hi, Prabhakar,
>
> On 27.03.2024 00:28, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist,
> > resulting in invalid register offsets. Ensure that the register offsets
> > are valid before any read/write operations are performed. If the power
> > registers are not available, both SD and ETH will be set to -EINVAL.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 16 ++++++++++------
> > 1 file changed, 10 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > index 348fdccaff72..705372faaeff 100644
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > @@ -184,8 +184,8 @@
> > */
> > struct rzg2l_register_offsets {
> > u16 pwpr;
> > - u16 sd_ch;
> > - u16 eth_poc;
> > + int sd_ch;
> > + int eth_poc;
> > };
> >
> > /**
> > @@ -2567,8 +2567,10 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
> > rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true);
> >
> > for (u8 i = 0; i < 2; i++) {
> > - cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i));
> > - cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));
> > + if (regs->sd_ch != -EINVAL)
>
> As of my knowledge, the current users of this driver uses SD and ETH
> offsets different from zero. To avoid populating these values for all the
> SoCs and avoid increasing the size of these fields I think you can add
> checks like these:
>
> if (regs->sd_ch)
> // set sd_ch
>
Agreed.
>
> Same for the rest.
>
OK.
Cheers,
Prabhakar
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: ti: Add k3-j722s-beagley-ai
From: Robert Nelson @ 2024-03-28 19:37 UTC (permalink / raw)
To: Jason Kridner
Cc: linux-arm-kernel, linux-kernel, devicetree, Nishanth Menon,
Jared McArthur, Deepak Khatri
In-Reply-To: <5C54919E-EBD5-4A16-821F-5146659CCD1D@beagleboard.org>
On Thu, Mar 28, 2024 at 2:26 PM Jason Kridner <jkridner@beagleboard.org> wrote:
>
>
>
> > On Mar 28, 2024, at 9:16 AM, Robert Nelson <robertcnelson@gmail.com> wrote:
> >
> > On Thu, Mar 28, 2024 at 2:12 PM Robert Nelson <robertcnelson@gmail.com> wrote:
> >>
> >> BeagleBoard.org BeagleY-AI is an easy to use, affordable open source
> >> hardware single board computer based on the Texas Instruments AM67A,
> >> which features a quad-core 64-bit Arm CPU subsystem, 2 general-purpose
> >> digital-signal-processors (DSP) and matrix-multiply-accelerators (MMA),
> >> GPU, vision and deep learning accelerators, and multiple Arm Cortex-R5
> >> cores for low-power, low-latency GPIO control.
> >>
> >> https://beagley-ai.org/
> >> https://openbeagle.org/beagley-ai/beagley-ai
> >
> > @Jason Kridner we need this to become public when you are ready ^ ;)
> >
>
> Did I mess up? Should already be public. We should make a github.com mirror though for up-time/visibility/bandwidth.
Thanks Jason, it seems to work in incognito mode now, so we are good!
Regards,
--
Robert Nelson
https://rcn-ee.com/
^ permalink raw reply
* Re: [RISC-V] [tech-j-ext] [RFC PATCH 5/9] riscv: Split per-CPU and per-thread envcfg bits
From: Deepak Gupta @ 2024-03-28 19:34 UTC (permalink / raw)
To: Samuel Holland, Palmer Dabbelt, linux-riscv, devicetree,
Catalin Marinas, linux-kernel, tech-j-ext, Conor Dooley,
kasan-dev, Evgenii Stepanov, Krzysztof Kozlowski, Rob Herring,
Andrew Jones, Guo Ren, Heiko Stuebner, Paul Walmsley
In-Reply-To: <17C0CB122DBB0EAE.6770@lists.riscv.org>
On Wed, Mar 27, 2024 at 06:58:45PM -0700, Deepak Gupta via lists.riscv.org wrote:
>On Tue, Mar 19, 2024 at 7:21 PM Samuel Holland
><samuel.holland@sifive.com> wrote:
>>
>> > else
>> > regs->status |= SR_UXL_64;
>> > #endif
>> > + current->thread_info.envcfg = ENVCFG_BASE;
>> > }
>> >
>> > And instead of context switching in `_switch_to`,
>> > In `entry.S` pick up `envcfg` from `thread_info` and write it into CSR.
>>
>> The immediate reason is that writing envcfg in ret_from_exception() adds cycles
>> to every IRQ and system call exit, even though most of them will not change the
>> envcfg value. This is especially the case when returning from an IRQ/exception
>> back to S-mode, since envcfg has zero effect there.
>>
>
>A quick observation:
>So I tried this on my setup. When I put `senvcfg` writes in
>`__switch_to ` path, qemu suddenly
>just tanks and takes a lot of time to boot up as opposed to when
>`senvcfg` was in trap return path.
>In my case entire userspace (all processes) have cfi enabled for them
>via `senvcfg` and it gets
>context switched. Not sure it's specific to my setup. I don't think it
>should be an issue on actual
>hardware.
>
>Still debugging why it slows down my qemu drastically when same writes
>to same CSR
>are moved from `ret_from_exception` to `switch_to`
Nevermind and sorry for the bother. An issue on my setup.
>
>
>-=-=-=-=-=-=-=-=-=-=-=-
>Links: You receive all messages sent to this group.
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>Mute This Topic: https://lists.riscv.org/mt/105033914/7300952
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>-=-=-=-=-=-=-=-=-=-=-=-
>
>
^ permalink raw reply
* [PATCH v2 3/3] arm64: dts: amlogic: ad402: setup thermal-zones
From: Dmitry Rokosov @ 2024-03-28 19:26 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, khilman, martin.blumenstingl,
glaroque, rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: kernel, rockosov, linux-amlogic, linux-pm, linux-kernel,
devicetree, linux-arm-kernel, Dmitry Rokosov
In-Reply-To: <20240328192645.20914-1-ddrokosov@salutedevices.com>
There is one thermal zone with 3 trip points: soc_passive, soc_hot, and
soc_critical, as well as two cooling maps.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
---
.../arm64/boot/dts/amlogic/meson-a1-ad402.dts | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts b/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts
index 6c02301840ff..2d22e8b45c6d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "meson-a1.dtsi"
+#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/gpio/gpio.h>
@@ -177,6 +178,50 @@ codec {
};
};
};
+
+ thermal-zones {
+ soc_thermal: soc_thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ sustainable-power = <130>;
+
+ thermal-sensors = <&cpu_temp>;
+
+ trips {
+ soc_passive: soc-passive {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ soc_hot: soc-hot {
+ temperature = <85000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ soc_critical: soc-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ soc_cooling_maps: cooling-maps {
+ map0 {
+ trip = <&soc_passive>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&soc_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
};
/* Bluetooth HCI H4 */
--
2.43.0
^ permalink raw reply related
* [PATCH v2 2/3] arm64: dts: amlogic: a1: introduce cpu temperature sensor
From: Dmitry Rokosov @ 2024-03-28 19:26 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, khilman, martin.blumenstingl,
glaroque, rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: kernel, rockosov, linux-amlogic, linux-pm, linux-kernel,
devicetree, linux-arm-kernel, Dmitry Rokosov
In-Reply-To: <20240328192645.20914-1-ddrokosov@salutedevices.com>
The A1 SoC family has only one thermal sensor for CPU temperature
measurement. It is required to set the TS clock rate to 500kHz to make
it workable.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index f65d4a77ee52..de77eb53d1dc 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -854,6 +854,17 @@ usb2_phy1: phy@4000 {
power-domains = <&pwrc PWRC_USB_ID>;
};
+ cpu_temp: temperature-sensor@4c00 {
+ compatible = "amlogic,a1-cpu-thermal";
+ reg = <0x0 0x4c00 0x0 0x50>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc_periphs CLKID_TS>;
+ assigned-clocks = <&clkc_periphs CLKID_TS>;
+ assigned-clock-rates = <500000>;
+ #thermal-sensor-cells = <0>;
+ amlogic,ao-secure = <&sec_AO>;
+ };
+
hwrng: rng@5118 {
compatible = "amlogic,meson-rng";
reg = <0x0 0x5118 0x0 0x4>;
--
2.43.0
^ permalink raw reply related
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