* Re: [PATCH 0/4] Add USB Support on Qualcomm's QDU/QRU1000 Platform
From: Komal Bajaj @ 2024-03-29 11:28 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Wesley Cheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb
In-Reply-To: <2024032637-sessions-outcast-888a@gregkh>
On 3/26/2024 2:00 PM, Greg Kroah-Hartman wrote:
> On Tue, Mar 19, 2024 at 02:37:24PM +0530, Komal Bajaj wrote:
>> This series adds support of USB3 PHY support for Qualcomm's QDU/QRU1000 Platform.
>>
>> ---------
>> Changes in v2:
>> * Dropped extra lines
>> * Sorted the tables alphabetically
>> * Link to v1: https://lore.kernel.org/linux-arm-msm/20240311120215.16845-1-quic_kbajaj@quicinc.com/
>>
>> Komal Bajaj (4):
>> dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000
>> dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY
>> dt-bindings: usb: dwc3: Add QDU1000 compatible
>> phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000
>>
>> .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 2 +
>> .../bindings/phy/qcom,usb-snps-femto-v2.yaml | 1 +
>> .../devicetree/bindings/usb/qcom,dwc3.yaml | 3 ++
>> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 49 +++++++++++++++++++
>> 4 files changed, 55 insertions(+)
>>
>> --
>> 2.42.0
>>
>>
>
> The subject line here does not say v2, so I'm confused as to which one
> is which :(
>
> Please fix up and send a v3.
Apologies, forgot to mark patches as v2.
Will soon send v3 series with proper marking.
Thanks
Komal
>
> thanks,
>
> greg k-h
^ permalink raw reply
* [PATCH v7 2/2] dmaengine: Loongson1: Add Loongson-1 APB DMA driver
From: Keguang Zhang via B4 Relay @ 2024-03-29 11:26 UTC (permalink / raw)
To: Keguang Zhang, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Huacai Chen
Cc: linux-mips, dmaengine, devicetree, linux-kernel
In-Reply-To: <20240329-loongson1-dma-v7-0-37db58608de5@gmail.com>
From: Keguang Zhang <keguang.zhang@gmail.com>
This patch adds APB DMA driver for Loongson-1 SoCs.
Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
---
Changes in v7:
- Change the comptible to 'loongson,ls1*-apbdma'
- Update Kconfig and Makefile accordingly
- Rename the file to loongson1-apb-dma.c to keep the consistency
Changes in v6:
- Implement .device_prep_dma_cyclic for Loongson1 audio driver,
- as well as .device_pause and .device_resume.
- Set the limitation LS1X_DMA_MAX_DESC and put all descriptors
- into one page to save memory
- Move dma_pool_zalloc() into ls1x_dma_alloc_desc()
- Drop dma_slave_config structure
- Use .remove_new instead of .remove
- Use KBUILD_MODNAME for the driver name
- Improve the debug information
Changes in v5:
- Add DT support
- Use DT data instead of platform data
- Use chan_id of struct dma_chan instead of own id
- Use of_dma_xlate_by_chan_id() instead of ls1x_dma_filter()
- Update the author information to my official name
Changes in v4:
- Use dma_slave_map to find the proper channel.
- Explicitly call devm_request_irq() and tasklet_kill().
- Fix namespace issue.
- Some minor fixes and cleanups.
Changes in v3:
- Rename ls1x_dma_filter_fn to ls1x_dma_filter.
Changes in v2:
- Change the config from 'DMA_LOONGSON1' to 'LOONGSON1_DMA',
- and rearrange it in alphabetical order in Kconfig and Makefile.
- Fix comment style.
---
drivers/dma/Kconfig | 9 +
drivers/dma/Makefile | 1 +
drivers/dma/loongson1-apb-dma.c | 665 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 675 insertions(+)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 002a5ec80620..f7b06c4cdf3f 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -369,6 +369,15 @@ config K3_DMA
Support the DMA engine for Hisilicon K3 platform
devices.
+config LOONGSON1_APB_DMA
+ tristate "Loongson1 APB DMA support"
+ depends on MACH_LOONGSON32 || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ This selects support for the APB DMA controller in Loongson1 SoCs,
+ which is required by Loongson1 NAND and audio support.
+
config LPC18XX_DMAMUX
bool "NXP LPC18xx/43xx DMA MUX for PL080"
depends on ARCH_LPC18XX || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index dfd40d14e408..b26f6677978a 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_INTEL_IDMA64) += idma64.o
obj-$(CONFIG_INTEL_IOATDMA) += ioat/
obj-y += idxd/
obj-$(CONFIG_K3_DMA) += k3dma.o
+obj-$(CONFIG_LOONGSON1_APB_DMA) += loongson1-apb-dma.o
obj-$(CONFIG_LPC18XX_DMAMUX) += lpc18xx-dmamux.o
obj-$(CONFIG_LS2X_APB_DMA) += ls2x-apb-dma.o
obj-$(CONFIG_MILBEAUT_HDMAC) += milbeaut-hdmac.o
diff --git a/drivers/dma/loongson1-apb-dma.c b/drivers/dma/loongson1-apb-dma.c
new file mode 100644
index 000000000000..d474a2601e6e
--- /dev/null
+++ b/drivers/dma/loongson1-apb-dma.c
@@ -0,0 +1,665 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for Loongson-1 APB DMA Controller
+ *
+ * Copyright (C) 2015-2024 Keguang Zhang <keguang.zhang@gmail.com>
+ */
+
+#include <linux/dmapool.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "dmaengine.h"
+#include "virt-dma.h"
+
+/* Loongson-1 DMA Control Register */
+#define DMA_CTRL 0x0
+
+/* DMA Control Register Bits */
+#define DMA_STOP BIT(4)
+#define DMA_START BIT(3)
+#define DMA_ASK_VALID BIT(2)
+
+#define DMA_ADDR_MASK GENMASK(31, 6)
+
+/* DMA Next Field Bits */
+#define DMA_NEXT_VALID BIT(0)
+
+/* DMA Command Field Bits */
+#define DMA_RAM2DEV BIT(12)
+#define DMA_INT BIT(1)
+#define DMA_INT_MASK BIT(0)
+
+#define LS1X_DMA_MAX_CHANNELS 3
+
+/* Size of allocations for hardware descriptors */
+#define LS1X_DMA_DESCS_SIZE PAGE_SIZE
+#define LS1X_DMA_MAX_DESC \
+ (LS1X_DMA_DESCS_SIZE / sizeof(struct ls1x_dma_hwdesc))
+
+struct ls1x_dma_hwdesc {
+ u32 next; /* next descriptor address */
+ u32 saddr; /* memory DMA address */
+ u32 daddr; /* device DMA address */
+ u32 length;
+ u32 stride;
+ u32 cycles;
+ u32 cmd;
+ u32 stats;
+};
+
+struct ls1x_dma_desc {
+ struct virt_dma_desc vdesc;
+ enum dma_transfer_direction dir;
+ enum dma_transaction_type type;
+ unsigned int bus_width;
+
+ unsigned int nr_descs; /* number of descriptors */
+
+ struct ls1x_dma_hwdesc *hwdesc;
+ dma_addr_t hwdesc_phys;
+};
+
+struct ls1x_dma_chan {
+ struct virt_dma_chan vchan;
+ struct dma_pool *desc_pool;
+ phys_addr_t src_addr;
+ phys_addr_t dst_addr;
+ enum dma_slave_buswidth src_addr_width;
+ enum dma_slave_buswidth dst_addr_width;
+
+ void __iomem *reg_base;
+ int irq;
+
+ struct ls1x_dma_desc *desc;
+
+ struct ls1x_dma_hwdesc *curr_hwdesc;
+ dma_addr_t curr_hwdesc_phys;
+};
+
+struct ls1x_dma {
+ struct dma_device ddev;
+ void __iomem *reg_base;
+
+ unsigned int nr_chans;
+ struct ls1x_dma_chan chan[];
+};
+
+#define to_ls1x_dma_chan(dchan) \
+ container_of(dchan, struct ls1x_dma_chan, vchan.chan)
+
+#define to_ls1x_dma_desc(vd) \
+ container_of(vd, struct ls1x_dma_desc, vdesc)
+
+/* macros for registers read/write */
+#define chan_readl(chan, off) \
+ readl((chan)->reg_base + (off))
+
+#define chan_writel(chan, off, val) \
+ writel((val), (chan)->reg_base + (off))
+
+static inline struct device *chan2dev(struct dma_chan *chan)
+{
+ return &chan->dev->device;
+}
+
+static inline int ls1x_dma_query(struct ls1x_dma_chan *chan,
+ dma_addr_t *hwdesc_phys)
+{
+ struct dma_chan *dchan = &chan->vchan.chan;
+ int val, ret;
+
+ val = *hwdesc_phys & DMA_ADDR_MASK;
+ val |= DMA_ASK_VALID;
+ val |= dchan->chan_id;
+ chan_writel(chan, DMA_CTRL, val);
+ ret = readl_poll_timeout_atomic(chan->reg_base + DMA_CTRL, val,
+ !(val & DMA_ASK_VALID), 0, 3000);
+ if (ret)
+ dev_err(chan2dev(dchan), "failed to query DMA\n");
+
+ return ret;
+}
+
+static inline int ls1x_dma_start(struct ls1x_dma_chan *chan,
+ dma_addr_t *hwdesc_phys)
+{
+ struct dma_chan *dchan = &chan->vchan.chan;
+ int val, ret;
+
+ dev_dbg(chan2dev(dchan), "cookie=%d, starting hwdesc=%x\n",
+ dchan->cookie, *hwdesc_phys);
+
+ val = *hwdesc_phys & DMA_ADDR_MASK;
+ val |= DMA_START;
+ val |= dchan->chan_id;
+ chan_writel(chan, DMA_CTRL, val);
+ ret = readl_poll_timeout(chan->reg_base + DMA_CTRL, val,
+ !(val & DMA_START), 0, 3000);
+ if (ret)
+ dev_err(chan2dev(dchan), "failed to start DMA\n");
+
+ return ret;
+}
+
+static inline void ls1x_dma_stop(struct ls1x_dma_chan *chan)
+{
+ chan_writel(chan, DMA_CTRL, chan_readl(chan, DMA_CTRL) | DMA_STOP);
+}
+
+static void ls1x_dma_free_chan_resources(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+
+ dma_free_coherent(chan2dev(dchan), sizeof(struct ls1x_dma_hwdesc),
+ chan->curr_hwdesc, chan->curr_hwdesc_phys);
+ vchan_free_chan_resources(&chan->vchan);
+ dma_pool_destroy(chan->desc_pool);
+ chan->desc_pool = NULL;
+}
+
+static int ls1x_dma_alloc_chan_resources(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+
+ chan->desc_pool = dma_pool_create(dma_chan_name(dchan),
+ chan2dev(dchan),
+ sizeof(struct ls1x_dma_hwdesc),
+ __alignof__(struct ls1x_dma_hwdesc),
+ 0);
+ if (!chan->desc_pool)
+ return -ENOMEM;
+
+ /* allocate memory for querying current HW descriptor */
+ dma_set_coherent_mask(chan2dev(dchan), DMA_BIT_MASK(32));
+ chan->curr_hwdesc = dma_alloc_coherent(chan2dev(dchan),
+ sizeof(struct ls1x_dma_hwdesc),
+ &chan->curr_hwdesc_phys,
+ GFP_KERNEL);
+ if (!chan->curr_hwdesc)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void ls1x_dma_free_desc(struct virt_dma_desc *vdesc)
+{
+ struct ls1x_dma_desc *desc = to_ls1x_dma_desc(vdesc);
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(vdesc->tx.chan);
+
+ dma_pool_free(chan->desc_pool, desc->hwdesc, desc->hwdesc_phys);
+ chan->desc = NULL;
+ kfree(desc);
+}
+
+static struct ls1x_dma_desc *
+ls1x_dma_alloc_desc(struct dma_chan *dchan, int sg_len,
+ enum dma_transfer_direction direction,
+ enum dma_transaction_type type)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ struct ls1x_dma_desc *desc;
+
+ if (sg_len > LS1X_DMA_MAX_DESC) {
+ dev_err(chan2dev(dchan), "sg_len %u exceeds limit %lu",
+ sg_len, LS1X_DMA_MAX_DESC);
+ return NULL;
+ }
+
+ desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
+ if (!desc)
+ return NULL;
+
+ /* allocate HW descriptors */
+ desc->hwdesc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT,
+ &desc->hwdesc_phys);
+ if (!desc->hwdesc) {
+ dev_err(chan2dev(dchan), "failed to alloc HW descriptors\n");
+ ls1x_dma_free_desc(&desc->vdesc);
+ return NULL;
+ }
+
+ desc->dir = direction;
+ desc->type = type;
+ desc->nr_descs = sg_len;
+
+ return desc;
+}
+
+static int ls1x_dma_setup_hwdescs(struct dma_chan *dchan,
+ struct ls1x_dma_desc *desc,
+ struct scatterlist *sgl, unsigned int sg_len)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ dma_addr_t next_hwdesc_phys = desc->hwdesc_phys;
+
+ struct scatterlist *sg;
+ unsigned int dev_addr, cmd, i;
+
+ switch (desc->dir) {
+ case DMA_MEM_TO_DEV:
+ dev_addr = chan->dst_addr;
+ desc->bus_width = chan->dst_addr_width;
+ cmd = DMA_RAM2DEV | DMA_INT;
+ break;
+ case DMA_DEV_TO_MEM:
+ dev_addr = chan->src_addr;
+ desc->bus_width = chan->src_addr_width;
+ cmd = DMA_INT;
+ break;
+ default:
+ dev_err(chan2dev(dchan), "unsupported DMA direction: %s\n",
+ dmaengine_get_direction_text(desc->dir));
+ return -EINVAL;
+ }
+
+ /* setup HW descriptors */
+ for_each_sg(sgl, sg, sg_len, i) {
+ dma_addr_t buf_addr = sg_dma_address(sg);
+ size_t buf_len = sg_dma_len(sg);
+ struct ls1x_dma_hwdesc *hwdesc = &desc->hwdesc[i];
+
+ if (!is_dma_copy_aligned(dchan->device, buf_addr, 0, buf_len)) {
+ dev_err(chan2dev(dchan), "buffer is not aligned!\n");
+ return -EINVAL;
+ }
+
+ hwdesc->saddr = buf_addr;
+ hwdesc->daddr = dev_addr;
+ hwdesc->length = buf_len / desc->bus_width;
+ hwdesc->stride = 0;
+ hwdesc->cycles = 1;
+ hwdesc->cmd = cmd;
+
+ if (i) {
+ next_hwdesc_phys += sizeof(*hwdesc);
+ desc->hwdesc[i - 1].next = next_hwdesc_phys
+ | DMA_NEXT_VALID;
+ }
+ }
+
+ if (desc->type == DMA_CYCLIC)
+ desc->hwdesc[i - 1].next = desc->hwdesc_phys | DMA_NEXT_VALID;
+
+ for_each_sg(sgl, sg, sg_len, i) {
+ struct ls1x_dma_hwdesc *hwdesc = &desc->hwdesc[i];
+
+ print_hex_dump_debug("HW DESC: ", DUMP_PREFIX_OFFSET, 16, 4,
+ hwdesc, sizeof(*hwdesc), false);
+ }
+
+ return 0;
+}
+
+static struct dma_async_tx_descriptor *
+ls1x_dma_prep_slave_sg(struct dma_chan *dchan,
+ struct scatterlist *sgl, unsigned int sg_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ struct ls1x_dma_desc *desc;
+
+ dev_dbg(chan2dev(dchan), "sg_len=%u flags=0x%lx dir=%s\n",
+ sg_len, flags, dmaengine_get_direction_text(direction));
+
+ desc = ls1x_dma_alloc_desc(dchan, sg_len, direction, DMA_SLAVE);
+ if (!desc)
+ return NULL;
+
+ if (ls1x_dma_setup_hwdescs(dchan, desc, sgl, sg_len)) {
+ ls1x_dma_free_desc(&desc->vdesc);
+ return NULL;
+ }
+
+ return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
+}
+
+static struct dma_async_tx_descriptor *
+ls1x_dma_prep_dma_cyclic(struct dma_chan *dchan,
+ dma_addr_t buf_addr, size_t buf_len, size_t period_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ struct ls1x_dma_desc *desc;
+ struct scatterlist *sgl;
+ unsigned int sg_len;
+ unsigned int i;
+
+ dev_dbg(chan2dev(dchan),
+ "buf_len=%d period_len=%zu flags=0x%lx dir=%s\n", buf_len,
+ period_len, flags, dmaengine_get_direction_text(direction));
+
+ sg_len = buf_len / period_len;
+ desc = ls1x_dma_alloc_desc(dchan, sg_len, direction, DMA_CYCLIC);
+ if (!desc)
+ return NULL;
+
+ /* allocate the scatterlist */
+ sgl = kmalloc_array(sg_len, sizeof(*sgl), GFP_NOWAIT);
+ if (!sgl)
+ return NULL;
+
+ sg_init_table(sgl, sg_len);
+ for (i = 0; i < sg_len; ++i) {
+ sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(buf_addr)),
+ period_len, offset_in_page(buf_addr));
+ sg_dma_address(&sgl[i]) = buf_addr;
+ sg_dma_len(&sgl[i]) = period_len;
+ buf_addr += period_len;
+ }
+
+ if (ls1x_dma_setup_hwdescs(dchan, desc, sgl, sg_len)) {
+ ls1x_dma_free_desc(&desc->vdesc);
+ return NULL;
+ }
+
+ kfree(sgl);
+
+ return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
+}
+
+static int ls1x_dma_slave_config(struct dma_chan *dchan,
+ struct dma_slave_config *config)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+
+ chan->src_addr = config->src_addr;
+ chan->src_addr_width = config->src_addr_width;
+ chan->dst_addr = config->dst_addr;
+ chan->dst_addr_width = config->dst_addr_width;
+
+ return 0;
+}
+
+static int ls1x_dma_pause(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ ret = ls1x_dma_query(chan, &chan->curr_hwdesc_phys);
+ if (!ret)
+ ls1x_dma_stop(chan);
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+ return ret;
+}
+
+static int ls1x_dma_resume(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ ret = ls1x_dma_start(chan, &chan->curr_hwdesc_phys);
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+ return ret;
+}
+
+static int ls1x_dma_terminate_all(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ unsigned long flags;
+ LIST_HEAD(head);
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ ls1x_dma_stop(chan);
+ vchan_get_all_descriptors(&chan->vchan, &head);
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+ vchan_dma_desc_free_list(&chan->vchan, &head);
+
+ return 0;
+}
+
+static enum dma_status ls1x_dma_tx_status(struct dma_chan *dchan,
+ dma_cookie_t cookie,
+ struct dma_tx_state *state)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ struct virt_dma_desc *vdesc;
+ enum dma_status status;
+ size_t bytes = 0;
+ unsigned long flags;
+
+ status = dma_cookie_status(dchan, cookie, state);
+ if (status == DMA_COMPLETE)
+ return status;
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ vdesc = vchan_find_desc(&chan->vchan, cookie);
+ if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) {
+ struct ls1x_dma_desc *desc = chan->desc;
+ int i;
+
+ if (ls1x_dma_query(chan, &chan->curr_hwdesc_phys))
+ return status;
+
+ /* locate the current HW descriptor */
+ for (i = 0; i < desc->nr_descs; i++)
+ if (desc->hwdesc[i].next == chan->curr_hwdesc->next)
+ break;
+
+ /* count the residues */
+ for (; i < desc->nr_descs; i++)
+ bytes += desc->hwdesc[i].length * desc->bus_width;
+
+ dma_set_residue(state, bytes);
+ }
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+ return status;
+}
+
+static void ls1x_dma_issue_pending(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ struct virt_dma_desc *vdesc;
+ unsigned long flags;
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
+ vdesc = vchan_next_desc(&chan->vchan);
+ if (!vdesc) {
+ chan->desc = NULL;
+ return;
+ }
+ chan->desc = to_ls1x_dma_desc(vdesc);
+ ls1x_dma_start(chan, &chan->desc->hwdesc_phys);
+ }
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+}
+
+static irqreturn_t ls1x_dma_irq_handler(int irq, void *data)
+{
+ struct ls1x_dma_chan *chan = data;
+ struct ls1x_dma_desc *desc = chan->desc;
+ struct dma_chan *dchan = &chan->vchan.chan;
+
+ if (!desc) {
+ dev_warn(chan2dev(dchan),
+ "IRQ %d with no active descriptor on channel %d\n",
+ irq, dchan->chan_id);
+ return IRQ_NONE;
+ }
+
+ dev_dbg(chan2dev(dchan), "DMA IRQ %d on channel %d\n", irq,
+ dchan->chan_id);
+
+ spin_lock(&chan->vchan.lock);
+
+ if (desc->type == DMA_CYCLIC) {
+ vchan_cyclic_callback(&desc->vdesc);
+ } else {
+ list_del(&desc->vdesc.node);
+ vchan_cookie_complete(&desc->vdesc);
+ chan->desc = NULL;
+ }
+
+ spin_unlock(&chan->vchan.lock);
+ return IRQ_HANDLED;
+}
+
+static int ls1x_dma_chan_probe(struct platform_device *pdev,
+ struct ls1x_dma *dma, int chan_id)
+{
+ struct device *dev = &pdev->dev;
+ struct ls1x_dma_chan *chan = &dma->chan[chan_id];
+ char pdev_irqname[4];
+ char *irqname;
+ int ret;
+
+ sprintf(pdev_irqname, "ch%u", chan_id);
+ chan->irq = platform_get_irq_byname(pdev, pdev_irqname);
+ if (chan->irq < 0)
+ return -ENODEV;
+
+ irqname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
+ dev_name(dev), pdev_irqname);
+ if (!irqname)
+ return -ENOMEM;
+
+ ret = devm_request_irq(dev, chan->irq, ls1x_dma_irq_handler,
+ IRQF_SHARED, irqname, chan);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to request IRQ %u!\n", chan->irq);
+
+ chan->reg_base = dma->reg_base;
+ chan->vchan.desc_free = ls1x_dma_free_desc;
+ vchan_init(&chan->vchan, &dma->ddev);
+ dev_info(dev, "%s (irq %d) initialized\n", pdev_irqname, chan->irq);
+
+ return 0;
+}
+
+static void ls1x_dma_chan_remove(struct ls1x_dma *dma, int chan_id)
+{
+ struct device *dev = dma->ddev.dev;
+ struct ls1x_dma_chan *chan = &dma->chan[chan_id];
+
+ devm_free_irq(dev, chan->irq, chan);
+ list_del(&chan->vchan.chan.device_node);
+ tasklet_kill(&chan->vchan.task);
+}
+
+static int ls1x_dma_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct dma_device *ddev;
+ struct ls1x_dma *dma;
+ int nr_chans, ret, i;
+
+ nr_chans = platform_irq_count(pdev);
+ if (nr_chans <= 0)
+ return nr_chans;
+ if (nr_chans > LS1X_DMA_MAX_CHANNELS)
+ return dev_err_probe(dev, -EINVAL,
+ "nr_chans=%d exceeds the maximum\n",
+ nr_chans);
+
+ dma = devm_kzalloc(dev, struct_size(dma, chan, nr_chans), GFP_KERNEL);
+ if (!dma)
+ return -ENOMEM;
+
+ /* initialize DMA device */
+ dma->reg_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(dma->reg_base))
+ return PTR_ERR(dma->reg_base);
+
+ ddev = &dma->ddev;
+ ddev->dev = dev;
+ ddev->copy_align = DMAENGINE_ALIGN_4_BYTES;
+ ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+ ddev->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+ ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+ ddev->max_sg_burst = LS1X_DMA_MAX_DESC;
+ ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+ ddev->device_alloc_chan_resources = ls1x_dma_alloc_chan_resources;
+ ddev->device_free_chan_resources = ls1x_dma_free_chan_resources;
+ ddev->device_prep_slave_sg = ls1x_dma_prep_slave_sg;
+ ddev->device_prep_dma_cyclic = ls1x_dma_prep_dma_cyclic;
+ ddev->device_config = ls1x_dma_slave_config;
+ ddev->device_pause = ls1x_dma_pause;
+ ddev->device_resume = ls1x_dma_resume;
+ ddev->device_terminate_all = ls1x_dma_terminate_all;
+ ddev->device_tx_status = ls1x_dma_tx_status;
+ ddev->device_issue_pending = ls1x_dma_issue_pending;
+
+ dma_cap_set(DMA_SLAVE, ddev->cap_mask);
+ INIT_LIST_HEAD(&ddev->channels);
+
+ /* initialize DMA channels */
+ for (i = 0; i < nr_chans; i++) {
+ ret = ls1x_dma_chan_probe(pdev, dma, i);
+ if (ret)
+ return ret;
+ }
+ dma->nr_chans = nr_chans;
+
+ ret = dmaenginem_async_device_register(ddev);
+ if (ret) {
+ dev_err(dev, "failed to register DMA device! %d\n", ret);
+ return ret;
+ }
+
+ ret =
+ of_dma_controller_register(dev->of_node, of_dma_xlate_by_chan_id,
+ ddev);
+ if (ret) {
+ dev_err(dev, "failed to register DMA controller! %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, dma);
+ dev_info(dev, "Loongson1 DMA driver registered\n");
+
+ return 0;
+}
+
+static void ls1x_dma_remove(struct platform_device *pdev)
+{
+ struct ls1x_dma *dma = platform_get_drvdata(pdev);
+ int i;
+
+ of_dma_controller_free(pdev->dev.of_node);
+
+ for (i = 0; i < dma->nr_chans; i++)
+ ls1x_dma_chan_remove(dma, i);
+}
+
+static const struct of_device_id ls1x_dma_match[] = {
+ { .compatible = "loongson,ls1b-apbdma" },
+ { .compatible = "loongson,ls1c-apbdma" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ls1x_dma_match);
+
+static struct platform_driver ls1x_dma_driver = {
+ .probe = ls1x_dma_probe,
+ .remove_new = ls1x_dma_remove,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = ls1x_dma_match,
+ },
+};
+
+module_platform_driver(ls1x_dma_driver);
+
+MODULE_AUTHOR("Keguang Zhang <keguang.zhang@gmail.com>");
+MODULE_DESCRIPTION("Loongson-1 APB DMA Controller driver");
+MODULE_LICENSE("GPL");
--
2.40.1
^ permalink raw reply related
* [PATCH v7 0/2] Add support for Loongson1 APB DMA
From: Keguang Zhang via B4 Relay @ 2024-03-29 11:26 UTC (permalink / raw)
To: Keguang Zhang, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Huacai Chen
Cc: linux-mips, dmaengine, devicetree, linux-kernel
Add the driver and dt-binding document for Loongson1 APB DMA.
Changes in v7:
- Change the comptible to 'loongson,ls1*-apbdma' (suggested by Huacai Chen)
- Update the title and description part accordingly
- Rename the file to loongson,ls1b-apbdma.yaml
- Add a compatible string for LS1A
- Delete minItems of 'interrupts'
- Change patterns of 'interrupt-names' to const
- Rename the file to loongson1-apb-dma.c to keep the consistency
- Update Kconfig and Makefile accordingly
- Link to v6: https://lore.kernel.org/r/20240316-loongson1-dma-v6-0-90de2c3cc928@gmail.com
Changes in v6:
- Change the compatible to the fallback
- Implement .device_prep_dma_cyclic for Loongson1 sound driver,
- as well as .device_pause and .device_resume.
- Set the limitation LS1X_DMA_MAX_DESC and put all descriptors
- into one page to save memory
- Move dma_pool_zalloc() into ls1x_dma_alloc_desc()
- Drop dma_slave_config structure
- Use .remove_new instead of .remove
- Use KBUILD_MODNAME for the driver name
- Improve the debug information
- Some minor fixes
-
Changes in v5:
- Add the dt-binding document
- Add DT support
- Use DT information instead of platform data
- Use chan_id of struct dma_chan instead of own id
- Use of_dma_xlate_by_chan_id() instead of ls1x_dma_filter()
- Update the author information to my official name
-
Changes in v4:
- Use dma_slave_map to find the proper channel.
- Explicitly call devm_request_irq() and tasklet_kill().
- Fix namespace issue.
- Some minor fixes and cleanups.
-
Changes in v3:
- Rename ls1x_dma_filter_fn to ls1x_dma_filter.
-
Changes in v2:
- Change the config from 'DMA_LOONGSON1' to 'LOONGSON1_DMA',
- and rearrange it in alphabetical order in Kconfig and Makefile.
- Fix comment style.
---
Keguang Zhang (2):
dt-bindings: dma: Add Loongson-1 APB DMA
dmaengine: Loongson1: Add Loongson-1 APB DMA driver
.../bindings/dma/loongson,ls1b-apbdma.yaml | 65 ++
drivers/dma/Kconfig | 9 +
drivers/dma/Makefile | 1 +
drivers/dma/loongson1-apb-dma.c | 665 +++++++++++++++++++++
4 files changed, 740 insertions(+)
---
base-commit: a6bd6c9333397f5a0e2667d4d82fef8c970108f2
change-id: 20231120-loongson1-dma-163afe5708b9
Best regards,
--
Keguang Zhang <keguang.zhang@gmail.com>
^ permalink raw reply
* [PATCH v7 1/2] dt-bindings: dma: Add Loongson-1 APB DMA
From: Keguang Zhang via B4 Relay @ 2024-03-29 11:26 UTC (permalink / raw)
To: Keguang Zhang, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Huacai Chen
Cc: linux-mips, dmaengine, devicetree, linux-kernel
In-Reply-To: <20240329-loongson1-dma-v7-0-37db58608de5@gmail.com>
From: Keguang Zhang <keguang.zhang@gmail.com>
Add devicetree binding document for Loongson-1 APB DMA.
Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
---
Changes in v7:
- Change the comptible to 'loongson,ls1*-apbdma' (suggested by Huacai Chen)
- Update the title and description part accordingly
- Rename the file to loongson,ls1b-apbdma.yaml
- Add a compatible string for LS1A
- Delete minItems of 'interrupts'
- Change patterns of 'interrupt-names' to const
Changes in v6:
- Change the compatible to the fallback
- Some minor fixes
Changes in v5:
- A newly added patch
---
.../bindings/dma/loongson,ls1b-apbdma.yaml | 65 ++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml b/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml
new file mode 100644
index 000000000000..449da9fc2de1
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/loongson,ls1b-apbdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson-1 APB DMA Controller
+
+maintainers:
+ - Keguang Zhang <keguang.zhang@gmail.com>
+
+description:
+ Loongson-1 APB DMA controller provides 3 independent channels for
+ peripherals such as NAND, audio playback and capture.
+
+properties:
+ compatible:
+ oneOf:
+ - const: loongson,ls1b-apbdma
+ - items:
+ - enum:
+ - loongson,ls1a-apbdma
+ - loongson,ls1c-apbdma
+ - const: loongson,ls1b-apbdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: Each channel has a dedicated interrupt line.
+ maxItems: 3
+
+ interrupt-names:
+ items:
+ - const: ch0
+ - const: ch1
+ - const: ch2
+
+ '#dma-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - '#dma-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ dma-controller@1fd01160 {
+ compatible = "loongson,ls1b-apbdma";
+ reg = <0x1fd01160 0x4>;
+
+ interrupt-parent = <&intc0>;
+ interrupts = <13 IRQ_TYPE_EDGE_RISING>,
+ <14 IRQ_TYPE_EDGE_RISING>,
+ <15 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ch0", "ch1", "ch2";
+
+ #dma-cells = <1>;
+ };
--
2.40.1
^ permalink raw reply related
* Re: [PATCH 2/2] phy: qcom-qmp-ufs: Add SM8475 support
From: Konrad Dybcio @ 2024-03-29 11:23 UTC (permalink / raw)
To: Vinod Koul
Cc: Danila Tikhonov, andersson, kishon, robh, krzysztof.kozlowski+dt,
conor+dt, linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <ZgUf_I2KBMhenNEv@matsya>
On 28.03.2024 8:45 AM, Vinod Koul wrote:
> On 27-03-24, 22:38, Konrad Dybcio wrote:
>> On 27.03.2024 7:06 PM, Danila Tikhonov wrote:
>>> Add the tables and constants for init sequences for UFS QMP phy found in
>>> SM8475 SoC.
>>>
>>> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
>>> ---
>>
>> Worth mentioning that SM8475 is a respin of SM8450 on a different
>> process node, which probably forced some electrical changes.
>
> should the tables be resued from 8450 instead of 8550 as in this patch?
No, and the reason why is my message above
Konrad
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: qcom: sm6350: Add DisplayPort controller
From: Konrad Dybcio @ 2024-03-29 11:20 UTC (permalink / raw)
To: Luca Weiss, Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh,
Krishna Manikandan, Bjorn Andersson
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel
In-Reply-To: <20240329-sm6350-dp-v2-3-e46dceb32ef5@fairphone.com>
On 29.03.2024 8:45 AM, Luca Weiss wrote:
> Add the node for the DisplayPort controller found on the SM6350 SoC.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply
* Re: [PATCH v6 19/23] dt-bindings: crypto: meson: support new SoC's
From: Alexey Romanov @ 2024-03-29 11:16 UTC (permalink / raw)
To: Conor Dooley
Cc: neil.armstrong@linaro.org, clabbe@baylibre.com,
herbert@gondor.apana.org.au, davem@davemloft.net,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, vadim.fedorenko@linux.dev,
linux-crypto@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kernel
In-Reply-To: <20240326-boneless-patrol-b1156a4be70b@spud>
Hello,
On Tue, Mar 26, 2024 at 06:04:46PM +0000, Conor Dooley wrote:
> On Tue, Mar 26, 2024 at 06:32:15PM +0300, Alexey Romanov wrote:
> > Now crypto module available at G12A/G12B/S4/A1/SM1/AXG.
> >
> > 1. Add new compatibles:
> > - amlogic,g12a-crypto
> > - amlogic,axg-crypto
> > - amlogic,a1-crypto
> > - amlogic,s4-crypto (uses a1-crypto as fallback)
> >
> > 2. Add power-domains in schema.
> >
> > Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
> > ---
> > .../bindings/crypto/amlogic,gxl-crypto.yaml | 15 +++++++++++++--
> > 1 file changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > index d3af7b4d5f39..c92edde314aa 100644
> > --- a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > +++ b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > @@ -11,8 +11,16 @@ maintainers:
> >
> > properties:
> > compatible:
> > - items:
> > - - const: amlogic,gxl-crypto
> > + oneOf:
> > + - items:
> > + - enum:
> > + - amlogic,s4-crypto
> > + - const: amlogic,a1-crypto
> > + - enum:
> > + - amlogic,gxl-crypto
> > + - amlogic,axg-crypto
> > + - amlogic,g12a-crypto
> > + - amlogic,a1-crypto
> >
> > reg:
> > maxItems: 1
> > @@ -21,6 +29,9 @@ properties:
> > items:
> > - description: Interrupt for flow 0
> >
> > + power-domains:
> > + maxItems: 1
>
> Is power-domains valid for the devices that existed prior to your patch?
For existed devices (GXL) power domain doesn't required.
--
Thank you,
Alexey
^ permalink raw reply
* Re: [PATCH v6 17/23] dt-bindings: crypto: meson: remove clk and second interrupt line for GXL
From: Alexey Romanov @ 2024-03-29 11:14 UTC (permalink / raw)
To: Conor Dooley
Cc: neil.armstrong@linaro.org, clabbe@baylibre.com,
herbert@gondor.apana.org.au, davem@davemloft.net,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, vadim.fedorenko@linux.dev,
linux-crypto@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kernel
In-Reply-To: <20240326-obscurity-angriness-d7bb48bc9eaa@spud>
Hi Conor,
On Tue, Mar 26, 2024 at 06:09:37PM +0000, Conor Dooley wrote:
> On Tue, Mar 26, 2024 at 06:32:13PM +0300, Alexey Romanov wrote:
> > GXL crypto IP uses DMA engine, which doesn't require clk input
> > and second interrupt line.
> >
> > Fixes: c4a0457eb858 ("ARM64: dts: amlogic: adds crypto hardware node")
>
> How does this fix a commit that only modifies a dts? The commit cited
> here should be a dt-bindings commit.
Yep, my bad. Will fix it in next series.
>
> However, your commit message says "require" but you do more than remove
> these as required, you remove them entirely. What am I missing?
Crypto HW isn't connected to clk / 2nd interrput line, so we must remove
them from dt. I will reformulate commit message.
>
> Thanks,
> Conor.
>
> > Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
> > ---
> > .../bindings/crypto/amlogic,gxl-crypto.yaml | 13 +------------
> > 1 file changed, 1 insertion(+), 12 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > index 948e11ebe4ee..d3af7b4d5f39 100644
> > --- a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > +++ b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > @@ -20,20 +20,11 @@ properties:
> > interrupts:
> > items:
> > - description: Interrupt for flow 0
> > - - description: Interrupt for flow 1
> > -
> > - clocks:
> > - maxItems: 1
> > -
> > - clock-names:
> > - const: blkmv
> >
> > required:
> > - compatible
> > - reg
> > - interrupts
> > - - clocks
> > - - clock-names
> >
> > additionalProperties: false
> >
> > @@ -46,7 +37,5 @@ examples:
> > crypto: crypto-engine@c883e000 {
> > compatible = "amlogic,gxl-crypto";
> > reg = <0xc883e000 0x36>;
> > - interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
> > - clocks = <&clkc CLKID_BLKMV>;
> > - clock-names = "blkmv";
> > + interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>;
> > };
> > --
> > 2.34.1
> >
--
Thank you,
Alexey
^ permalink raw reply
* Re: [PATCH 0/4] Add USB Support on Qualcomm's QDU/QRU1000 Platform
From: Komal Bajaj @ 2024-03-29 11:02 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Wesley Cheng, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-usb
In-Reply-To: <CAA8EJpojQg2BHvR5kZtRxyXWRKy6zV=88_bdcuMH+QE-n4k73A@mail.gmail.com>
On 3/19/2024 3:05 PM, Dmitry Baryshkov wrote:
> On Tue, 19 Mar 2024 at 11:08, Komal Bajaj <quic_kbajaj@quicinc.com> wrote:
>>
>> This series adds support of USB3 PHY support for Qualcomm's QDU/QRU1000 Platform.
>>
>> ---------
>> Changes in v2:
>> * Dropped extra lines
>> * Sorted the tables alphabetically
>> * Link to v1: https://lore.kernel.org/linux-arm-msm/20240311120215.16845-1-quic_kbajaj@quicinc.com/
>
> So, this is v2, but you didn't mark patches as v2. Please use b4 for
> sending patches. It can handle patch revisions automatically.
Apologies for this, forgot to mark patches as v2.
I will be careful next time.
>
>>
>> Komal Bajaj (4):
>> dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000
>> dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY
>> dt-bindings: usb: dwc3: Add QDU1000 compatible
>> phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000
>>
>> .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 2 +
>> .../bindings/phy/qcom,usb-snps-femto-v2.yaml | 1 +
>> .../devicetree/bindings/usb/qcom,dwc3.yaml | 3 ++
>> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 49 +++++++++++++++++++
>> 4 files changed, 55 insertions(+)
>
>
>
^ permalink raw reply
* Re: [PATCH v4 4/4] remoteproc: stm32: Add support of an OP-TEE TA to load the firmware
From: Arnaud POULIQUEN @ 2024-03-29 10:57 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Bjorn Andersson, Jens Wiklander, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-stm32, linux-arm-kernel, linux-remoteproc,
linux-kernel, op-tee, devicetree
In-Reply-To: <ZgRT7PtzIogAWc50@p14s>
On 3/27/24 18:14, Mathieu Poirier wrote:
> On Tue, Mar 26, 2024 at 08:31:33PM +0100, Arnaud POULIQUEN wrote:
>>
>>
>> On 3/25/24 17:51, Mathieu Poirier wrote:
>>> On Fri, Mar 08, 2024 at 03:47:08PM +0100, Arnaud Pouliquen wrote:
>>>> The new TEE remoteproc device is used to manage remote firmware in a
>>>> secure, trusted context. The 'st,stm32mp1-m4-tee' compatibility is
>>>> introduced to delegate the loading of the firmware to the trusted
>>>> execution context. In such cases, the firmware should be signed and
>>>> adhere to the image format defined by the TEE.
>>>>
>>>> Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
>>>> ---
>>>> Updates from V3:
>>>> - remove support of the attach use case. Will be addressed in a separate
>>>> thread,
>>>> - add st_rproc_tee_ops::parse_fw ops,
>>>> - inverse call of devm_rproc_alloc()and tee_rproc_register() to manage cross
>>>> reference between the rproc struct and the tee_rproc struct in tee_rproc.c.
>>>> ---
>>>> drivers/remoteproc/stm32_rproc.c | 60 +++++++++++++++++++++++++++++---
>>>> 1 file changed, 56 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/remoteproc/stm32_rproc.c b/drivers/remoteproc/stm32_rproc.c
>>>> index 8cd838df4e92..13df33c78aa2 100644
>>>> --- a/drivers/remoteproc/stm32_rproc.c
>>>> +++ b/drivers/remoteproc/stm32_rproc.c
>>>> @@ -20,6 +20,7 @@
>>>> #include <linux/remoteproc.h>
>>>> #include <linux/reset.h>
>>>> #include <linux/slab.h>
>>>> +#include <linux/tee_remoteproc.h>
>>>> #include <linux/workqueue.h>
>>>>
>>>> #include "remoteproc_internal.h"
>>>> @@ -49,6 +50,9 @@
>>>> #define M4_STATE_STANDBY 4
>>>> #define M4_STATE_CRASH 5
>>>>
>>>> +/* Remote processor unique identifier aligned with the Trusted Execution Environment definitions */
>>>
>>> Why is this the case? At least from the kernel side it is possible to call
>>> tee_rproc_register() with any kind of value, why is there a need to be any
>>> kind of alignment with the TEE?
>>
>>
>> The use of the proc_id is to identify a processor in case of multi co-processors.
>>
>
> That is well understood.
>
>> For instance we can have a system with A DSP and a modem. We would use the same
>> TEE service, but
>
> That too.
>
>> the TEE driver will probably be different, same for the signature key.
>
> What TEE driver are we talking about here?
In OP-TEE remoteproc frameork is divided in 2 or 3 layers:
- the remoteproc Trusted Application (TA) [1] which is platform agnostic
- The remoteproc Pseudo Trusted Application (PTA) [2] which is platform
dependent and can rely on the proc ID to retrieve the context.
- the remoteproc driver (optional for some platforms) [3], which is in charge
of DT parsing and platform configuration.
Here TEE driver can be interpreted by remote PTA and/or platform driver.
[1]
https://elixir.bootlin.com/op-tee/latest/source/ta/remoteproc/src/remoteproc_core.c
[2]
https://elixir.bootlin.com/op-tee/latest/source/core/pta/stm32mp/remoteproc_pta.c
[3]
https://elixir.bootlin.com/op-tee/latest/source/core/drivers/remoteproc/stm32_remoteproc.c
>
>> In such case the proc ID allows to identify the the processor you want to address.
>>
>
> That too is well understood, but there is no alignment needed with the TEE, i.e
> the TEE application is not expecting a value of '0'. We could set
> STM32_MP1_M4_PROC_ID to 0xDEADBEEF and things would work. This driver won't go
> anywhere for as long as it is not the case.
Here I suppose that you do not challenge the rproc_ID use in general, but for
the stm32mp1 platform as we have only one remote processor. I'm right?
In OP-TEE the check is done here:
https://elixir.bootlin.com/op-tee/latest/source/core/drivers/remoteproc/stm32_remoteproc.c#L64
If driver does not register the proc ID an error is returned indicating that the
feature is not supported.
In case of stm32mp1 yes we could consider it as useless as we have only one
remote proc.
Nevertheless I can not guaranty that a customer will not add an external
companion processor that uses OP-TEE to authenticate the associated firmware. As
the trusted Application is the unique entry point. he will need the proc_id to
identify the target at PTA level.
So from my point of view having a proc ID on stm32MP1 (and on stm32mp2 that will
reuse same driver) aligned between Linux and OP-TEE is useful.
That said using a TEE_REMOTEPROC_DEFAULT_ID is something that could be
more generic (for linux and OP-TEE). This ID could be reuse in the stm32mp
driver and platform drivers with an unique internal remote processor.
It that solution would be ok for you?
Regards,
Arnaud
>
>>
>>>
>>>> +#define STM32_MP1_M4_PROC_ID 0
>>>> +
>>>> struct stm32_syscon {
>>>> struct regmap *map;
>>>> u32 reg;
>>>> @@ -257,6 +261,19 @@ static int stm32_rproc_release(struct rproc *rproc)
>>>> return 0;
>>>> }
>>>>
>>>> +static int stm32_rproc_tee_stop(struct rproc *rproc)
>>>> +{
>>>> + int err;
>>>> +
>>>> + stm32_rproc_request_shutdown(rproc);
>>>> +
>>>> + err = tee_rproc_stop(rproc);
>>>> + if (err)
>>>> + return err;
>>>> +
>>>> + return stm32_rproc_release(rproc);
>>>> +}
>>>> +
>>>> static int stm32_rproc_prepare(struct rproc *rproc)
>>>> {
>>>> struct device *dev = rproc->dev.parent;
>>>> @@ -693,8 +710,19 @@ static const struct rproc_ops st_rproc_ops = {
>>>> .get_boot_addr = rproc_elf_get_boot_addr,
>>>> };
>>>>
>>>> +static const struct rproc_ops st_rproc_tee_ops = {
>>>> + .prepare = stm32_rproc_prepare,
>>>> + .start = tee_rproc_start,
>>>> + .stop = stm32_rproc_tee_stop,
>>>> + .kick = stm32_rproc_kick,
>>>> + .load = tee_rproc_load_fw,
>>>> + .parse_fw = tee_rproc_parse_fw,
>>>> + .find_loaded_rsc_table = tee_rproc_find_loaded_rsc_table,
>>>> +};
>>>> +
>>>> static const struct of_device_id stm32_rproc_match[] = {
>>>> - { .compatible = "st,stm32mp1-m4" },
>>>> + {.compatible = "st,stm32mp1-m4",},
>>>> + {.compatible = "st,stm32mp1-m4-tee",},
>>>> {},
>>>> };
>>>> MODULE_DEVICE_TABLE(of, stm32_rproc_match);
>>>> @@ -853,6 +881,7 @@ static int stm32_rproc_probe(struct platform_device *pdev)
>>>> struct device *dev = &pdev->dev;
>>>> struct stm32_rproc *ddata;
>>>> struct device_node *np = dev->of_node;
>>>> + struct tee_rproc *trproc = NULL;
>>>> struct rproc *rproc;
>>>> unsigned int state;
>>>> int ret;
>>>> @@ -861,9 +890,26 @@ static int stm32_rproc_probe(struct platform_device *pdev)
>>>> if (ret)
>>>> return ret;
>>>>
>>>> - rproc = devm_rproc_alloc(dev, np->name, &st_rproc_ops, NULL, sizeof(*ddata));
>>>> - if (!rproc)
>>>> - return -ENOMEM;
>>>> + if (of_device_is_compatible(np, "st,stm32mp1-m4-tee")) {
>>>> + /*
>>>> + * Delegate the firmware management to the secure context.
>>>> + * The firmware loaded has to be signed.
>>>> + */
>>>> + rproc = devm_rproc_alloc(dev, np->name, &st_rproc_tee_ops, NULL, sizeof(*ddata));
>>>> + if (!rproc)
>>>> + return -ENOMEM;
>>>> +
>>>> + trproc = tee_rproc_register(dev, rproc, STM32_MP1_M4_PROC_ID);
>>>> + if (IS_ERR(trproc)) {
>>>> + dev_err_probe(dev, PTR_ERR(trproc),
>>>> + "signed firmware not supported by TEE\n");
>>>> + return PTR_ERR(trproc);
>>>> + }
>>>> + } else {
>>>> + rproc = devm_rproc_alloc(dev, np->name, &st_rproc_ops, NULL, sizeof(*ddata));
>>>> + if (!rproc)
>>>> + return -ENOMEM;
>>>> + }
>>>>
>>>> ddata = rproc->priv;
>>>>
>>>> @@ -915,6 +961,9 @@ static int stm32_rproc_probe(struct platform_device *pdev)
>>>> dev_pm_clear_wake_irq(dev);
>>>> device_init_wakeup(dev, false);
>>>> }
>>>> + if (trproc)
>>>
>>> if (rproc->tee_interface)
>>>
>>>
>>> I am done reviewing this set.
>>
>> Thank for your review!
>> Arnaud
>>
>>>
>>> Thanks,
>>> Mathieu
>>>
>>>> + tee_rproc_unregister(trproc);
>>>> +
>>>> return ret;
>>>> }
>>>>
>>>> @@ -935,6 +984,9 @@ static void stm32_rproc_remove(struct platform_device *pdev)
>>>> dev_pm_clear_wake_irq(dev);
>>>> device_init_wakeup(dev, false);
>>>> }
>>>> + if (rproc->tee_interface)
>>>> + tee_rproc_unregister(rproc->tee_interface);
>>>> +
>>>> }
>>>>
>>>> static int stm32_rproc_suspend(struct device *dev)
>>>> --
>>>> 2.25.1
>>>>
^ permalink raw reply
* Re: [PATCH v5 4/5] clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks
From: Varadarajan Narayanan @ 2024-03-29 10:55 UTC (permalink / raw)
To: Stephen Boyd
Cc: andersson, conor+dt, devicetree, djakov, dmitry.baryshkov,
konrad.dybcio, krzysztof.kozlowski+dt, linux-arm-msm, linux-clk,
linux-kernel, linux-pm, mturquette, quic_anusha, robh
In-Reply-To: <95f4e99a60cc97770fc3cee850b62faf.sboyd@kernel.org>
On Thu, Mar 28, 2024 at 02:51:09PM -0700, Stephen Boyd wrote:
> Quoting Varadarajan Narayanan (2024-03-28 00:59:35)
> > diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> > index 0a3f846695b8..187fd9dcdf49 100644
> > --- a/drivers/clk/qcom/gcc-ipq9574.c
> > +++ b/drivers/clk/qcom/gcc-ipq9574.c
> > @@ -4301,6 +4302,56 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
> > [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
> > };
> >
> > +#define IPQ_APPS_ID 9574 /* some unique value */
>
> How is this supposed to stay unique?
The icc-clk driver expects some number that wouldn't interfere
with the existing nodes. So just used the SoC id itself.
> I don't understand icc_node_create() API quite honestly. Why
> can't icc_clk_register() maintain some ida of allocated
> numbers? Or is there some global number space that we can
> "reserve" from? I'm quite amazed this is how things are
> connected in interconnect framework.
>
> > +
> > +enum {
> > + ICC_ANOC_PCIE0,
> > + ICC_SNOC_PCIE0,
> > + ICC_ANOC_PCIE1,
> > + ICC_SNOC_PCIE1,
> > + ICC_ANOC_PCIE2,
> > + ICC_SNOC_PCIE2,
> > + ICC_ANOC_PCIE3,
> > + ICC_SNOC_PCIE3,
> > + ICC_SNOC_USB,
> > + ICC_ANOC_USB_AXI,
> > + ICC_NSSNOC_NSSCC,
> > + ICC_NSSNOC_SNOC_0,
> > + ICC_NSSNOC_SNOC_1,
> > + ICC_NSSNOC_PCNOC_1,
> > + ICC_NSSNOC_QOSGEN_REF,
> > + ICC_NSSNOC_TIMEOUT_REF,
> > + ICC_NSSNOC_XO_DCD,
> > + ICC_NSSNOC_ATB,
> > + ICC_MEM_NOC_NSSNOC,
> > + ICC_NSSNOC_MEMNOC,
> > + ICC_NSSNOC_MEM_NOC_1,
> > +};
>
> Are these supposed to be in a dt-binding header?
Since these don't directly relate to the ids in the dt-bindings
not sure if they will be permitted there. Will move and post a
new version and get feedback.
Thanks
Varada
> > +
> > +static struct clk_hw *icc_ipq9574_hws[] = {
> > + [ICC_ANOC_PCIE0] = &gcc_anoc_pcie0_1lane_m_clk.clkr.hw,
> > + [ICC_SNOC_PCIE0] = &gcc_anoc_pcie1_1lane_m_clk.clkr.hw,
> > + [ICC_ANOC_PCIE1] = &gcc_anoc_pcie2_2lane_m_clk.clkr.hw,
> > + [ICC_SNOC_PCIE1] = &gcc_anoc_pcie3_2lane_m_clk.clkr.hw,
> > + [ICC_ANOC_PCIE2] = &gcc_snoc_pcie0_1lane_s_clk.clkr.hw,
> > + [ICC_SNOC_PCIE2] = &gcc_snoc_pcie1_1lane_s_clk.clkr.hw,
^ permalink raw reply
* Re: [PATCH v5 3/5] clk: qcom: common: Add interconnect clocks support
From: Varadarajan Narayanan @ 2024-03-29 10:48 UTC (permalink / raw)
To: Stephen Boyd
Cc: andersson, conor+dt, devicetree, djakov, dmitry.baryshkov,
konrad.dybcio, krzysztof.kozlowski+dt, linux-arm-msm, linux-clk,
linux-kernel, linux-pm, mturquette, quic_anusha, robh
In-Reply-To: <80131262978e6e4799864cdfd0784fdf.sboyd@kernel.org>
On Thu, Mar 28, 2024 at 02:54:52PM -0700, Stephen Boyd wrote:
> Quoting Varadarajan Narayanan (2024-03-28 00:59:34)
> > diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
> > index 75f09e6e057e..9fa271812373 100644
> > --- a/drivers/clk/qcom/common.c
> > +++ b/drivers/clk/qcom/common.c
> > @@ -8,6 +8,8 @@
> > #include <linux/regmap.h>
> > #include <linux/platform_device.h>
> > #include <linux/clk-provider.h>
> > +#include <linux/interconnect-clk.h>
> > +#include <linux/interconnect-provider.h>
>
> Do we need the second include?
Will remove.
> > #include <linux/reset-controller.h>
> > #include <linux/of.h>
> >
> > @@ -234,6 +236,41 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
> > return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
> > }
> >
> > +#if IS_ENABLED(CONFIG_INTERCONNECT_CLK)
> > +static int qcom_cc_icc_register(struct device *dev,
> > + const struct qcom_cc_desc *desc)
> > +{
> > + struct icc_clk_data *icd;
> > + int i;
> > +
> > + if (!desc->icc_hws)
> > + return 0;
> > +
> > + icd = devm_kcalloc(dev, desc->num_icc_hws, sizeof(*icd), GFP_KERNEL);
> > + if (!icd)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < desc->num_icc_hws; i++) {
> > + icd[i].clk = devm_clk_hw_get_clk(dev, desc->icc_hws[i], "qcom");
>
> Make the con_id "icc" instead please, so we know the consumer is
> icc_clk.
Ok.
> Even better would be for the icc_clk device itself to be the
> one requesting with devm_clk_hw_get_clk() so that we associate the clk
> handle with the consumer device. It would also help us make it so that
> drivers defer probe until their clk isn't an orphan.
Not sure if I understand the comments correctly.
In one of the previous patches, had
icd[i].clk = clks[noc_clks[i]]->hw.clk;
This was said to be error prone since the clock would not be
ref counted. Hence used devm_clk_hw_get_clk before doing
icc_clk_register.
Now, are you suggesting to use the direct clock pointer
and do a devm_clk_hw_get_clk from the consumer driver?
This will take care of the refcounting. However, we will
have to add these clock entries to the consumer DT node.
Is this ok?
> > + if (IS_ERR(icd[i].clk))
> > + return dev_err_probe(dev, PTR_ERR(icd[i].clk),
> > + "get clock failed (%ld)\n",
> > + PTR_ERR(icd[i].clk));
> > +
> > + icd[i].name = clk_hw_get_name(desc->icc_hws[i]);
> > + }
> > +
> > + return PTR_ERR_OR_ZERO(devm_icc_clk_register(dev, desc->first_id,
> > + desc->num_icc_hws, icd));
> > +}
> > +#else
> > +static int qcom_cc_icc_register(struct device *dev,
> > + const struct qcom_cc_desc *desc)
> > +{
> > + return 0;
> > +}
>
> Instead of this please have an
>
> if (!IS_ENABLED(CONFIG_INTERCONNECT_CLK))
> return 0;
Ok.
> > +#endif
> > +
> > int qcom_cc_really_probe(struct platform_device *pdev,
> > const struct qcom_cc_desc *desc, struct regmap *regmap)
> > {
> > @@ -303,7 +340,7 @@ int qcom_cc_really_probe(struct platform_device *pdev,
> > if (ret)
> > return ret;
> >
> > - return 0;
> > + return qcom_cc_icc_register(dev, desc);
> > }
> > EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
> >
> > diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
> > index 9c8f7b798d9f..d8ac26d83f3c 100644
> > --- a/drivers/clk/qcom/common.h
> > +++ b/drivers/clk/qcom/common.h
> > @@ -29,6 +29,9 @@ struct qcom_cc_desc {
> > size_t num_gdscs;
> > struct clk_hw **clk_hws;
> > size_t num_clk_hws;
> > + struct clk_hw **icc_hws;
> > + size_t num_icc_hws;
> > + unsigned int first_id;
>
> 'first_id' is gross.
will change it to 'icc_id'.
Thanks
Varada
^ permalink raw reply
* [PATCH] arm64: dts: allwinner: h616: Fix I2C0 pins
From: Andre Przywara @ 2024-03-29 10:38 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland
Cc: devicetree, linux-sunxi
Currently we specify the pins for the I2C0 function as PI6 and PI7, even
though they are actually PI5 and PI6. Linux' pinctrl driver and the H616
user manual confirm this.
Fix the pin names in the pins property. None of the existing DTs in the
tree seems to use I2C0, which explains why this went unnoticed.
Fixes: 0d17c8651188 ("arm64: dts: allwinner: Add Allwinner H616 .dtsi file")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index f756a396ea3da..95f09204337f0 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -227,7 +227,7 @@ ext_rgmii_pins: rgmii-pins {
};
i2c0_pins: i2c0-pins {
- pins = "PI6", "PI7";
+ pins = "PI5", "PI6";
function = "i2c0";
};
--
2.35.8
^ permalink raw reply related
* Re: [PATCH RFC 02/11] dt-bindings: riscv: Add Sdtrig optional CSRs existence on DT
From: Conor Dooley @ 2024-03-29 10:31 UTC (permalink / raw)
To: Max Hsu
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Rafael J. Wysocki, Pavel Machek,
Anup Patel, Atish Patra, Paolo Bonzini, Shuah Khan,
Palmer Dabbelt, linux-riscv, devicetree, linux-kernel, linux-pm,
kvm, kvm-riscv, linux-kselftest
In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-2-1534f93b94a7@sifive.com>
[-- Attachment #1: Type: text/plain, Size: 2013 bytes --]
On Fri, Mar 29, 2024 at 05:26:18PM +0800, Max Hsu wrote:
> The mcontext/hcontext/scontext CSRs are optional in the Sdtrig extension,
> to prevent RW operations to the missing CSRs, which will cause
> illegal instructions.
>
> As a solution, we have proposed the dt format for these CSRs.
As I mentioned in your other patch, I amn't sure what the actual value
is in being told about "sdtrig" itself if so many of the CSRs are
optional. I think we should define pseudo extensions that represent
usable subsets that are allowed by riscv,isa-extensions, such as
those you describe here: sdtrig + mcontext, sdtrig + scontext and
sdtrig + hcontext. Probably also for strig + mscontext. What
additional value does having a debug child node give us that makes
it worth having over something like the above?
Thanks,
Conor.
>
> Signed-off-by: Max Hsu <max.hsu@sifive.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index d87dd50f1a4b..c713a48c5025 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -137,6 +137,24 @@ properties:
> DMIPS/MHz, relative to highest capacity-dmips-mhz
> in the system.
>
> + debug:
> + type: object
> + properties:
> + compatible:
> + const: riscv,debug-v1.0.0
> + trigger-module:
> + type: object
> + description: |
> + An indication set of optional CSR existence from
> + riscv-debug-spec Sdtrig extension
> + properties:
> + mcontext-present:
> + type: boolean
> + hcontext-present:
> + type: boolean
> + scontext-present:
> + type: boolean
> +
> anyOf:
> - required:
> - riscv,isa
>
> --
> 2.43.2
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v1 3/5] dt-bindings: gpio: mpfs: allow gpio-line-names
From: Bartosz Golaszewski @ 2024-03-29 10:29 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, Conor Dooley, Daire McNamara, Jamie Gibbons,
Valentina Fernandez, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Lorenzo Pieralisi, Krzysztof Wilczyński,
Bjorn Helgaas, linux-gpio, devicetree, linux-kernel, linux-pci
In-Reply-To: <20240327-overrate-overuse-1e32abccd001@spud>
On Wed, Mar 27, 2024 at 1:25 PM Conor Dooley <conor@kernel.org> wrote:
>
> From: Jamie Gibbons <jamie.gibbons@microchip.com>
>
> The BeagleV Fire devicetree will make use of gpio-line-names, allow it
> in the binding.
>
> Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> index 6884dacb2865..d61569b3f15b 100644
> --- a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> @@ -44,6 +44,7 @@ properties:
> default: 32
>
> gpio-controller: true
> + gpio-line-names: true
>
> patternProperties:
> "^.+-hog(-[0-9]+)?$":
> --
> 2.43.0
>
Applied, thanks!
Bart
^ permalink raw reply
* Re: [PATCH v1 2/5] dt-bindings: gpio: mpfs: add coreGPIO support
From: Bartosz Golaszewski @ 2024-03-29 10:28 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, Conor Dooley, Daire McNamara, Jamie Gibbons,
Valentina Fernandez, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Lorenzo Pieralisi, Krzysztof Wilczyński,
Bjorn Helgaas, linux-gpio, devicetree, linux-kernel, linux-pci
In-Reply-To: <20240327-procurer-rascal-33bca7d5d14b@spud>
On Wed, Mar 27, 2024 at 1:25 PM Conor Dooley <conor@kernel.org> wrote:
>
> From: Jamie Gibbons <jamie.gibbons@microchip.com>
>
> The GPIO controllers on PolarFire SoC were based on the "soft" IP
> CoreGPIO, but the inp/outp registers are at different offsets. Add
> compatible to allow for support of both sets of offsets. The soft
> core will not always have interrupts wired up, so only enforce them for
> the "hard" core on PolarFire SoC.
>
> Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
Applied, thanks!
Bart
^ permalink raw reply
* Re: [PATCH RFC 05/11] riscv: cpufeature: Add Sdtrig optional CSRs checks
From: Conor Dooley @ 2024-03-29 10:21 UTC (permalink / raw)
To: Max Hsu
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Rafael J. Wysocki, Pavel Machek,
Anup Patel, Atish Patra, Paolo Bonzini, Shuah Khan,
Palmer Dabbelt, linux-riscv, devicetree, linux-kernel, linux-pm,
kvm, kvm-riscv, linux-kselftest
In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-5-1534f93b94a7@sifive.com>
[-- Attachment #1: Type: text/plain, Size: 8947 bytes --]
On Fri, Mar 29, 2024 at 05:26:21PM +0800, Max Hsu wrote:
> Sdtrig extension introduce two optional CSRs [hcontext/scontext],
> that will be storing PID/Guest OS ID for the debug feature.
>
> The availability of these two CSRs will be determined by
> DTS and Smstateen extension [h/s]stateen0 CSR bit 57.
>
> If all CPUs hcontext/scontext checks are satisfied, it will enable the
> use_hcontext/use_scontext static branch.
>
> Signed-off-by: Max Hsu <max.hsu@sifive.com>
> ---
> arch/riscv/include/asm/switch_to.h | 6 ++
> arch/riscv/kernel/cpufeature.c | 161 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 167 insertions(+)
>
> diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
> index 7efdb0584d47..07432550ed54 100644
> --- a/arch/riscv/include/asm/switch_to.h
> +++ b/arch/riscv/include/asm/switch_to.h
> @@ -69,6 +69,12 @@ static __always_inline bool has_fpu(void) { return false; }
> #define __switch_to_fpu(__prev, __next) do { } while (0)
> #endif
>
> +DECLARE_STATIC_KEY_FALSE(use_scontext);
> +static __always_inline bool has_scontext(void)
> +{
> + return static_branch_likely(&use_scontext);
> +}
> +
> extern struct task_struct *__switch_to(struct task_struct *,
> struct task_struct *);
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 080c06b76f53..44ff84b920af 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -35,6 +35,19 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
> /* Per-cpu ISA extensions. */
> struct riscv_isainfo hart_isa[NR_CPUS];
>
> +atomic_t hcontext_disable;
> +atomic_t scontext_disable;
> +
> +DEFINE_STATIC_KEY_FALSE_RO(use_hcontext);
> +EXPORT_SYMBOL(use_hcontext);
> +
> +DEFINE_STATIC_KEY_FALSE_RO(use_scontext);
> +EXPORT_SYMBOL(use_scontext);
> +
> +/* Record the maximum number that the hcontext CSR allowed to hold */
> +atomic_long_t hcontext_id_share;
> +EXPORT_SYMBOL(hcontext_id_share);
> +
> /**
> * riscv_isa_extension_base() - Get base extension word
> *
> @@ -719,6 +732,154 @@ unsigned long riscv_get_elf_hwcap(void)
> return hwcap;
> }
>
> +static void __init sdtrig_percpu_csrs_check(void *data)
> +{
> + struct device_node *node;
> + struct device_node *debug_node;
> + struct device_node *trigger_module;
> +
> + unsigned int cpu = smp_processor_id();
> +
> + /*
> + * Expect every cpu node has the [h/s]context-present property
> + * otherwise, jump to sdtrig_csrs_disable_all to disable all access to
> + * [h/s]context CSRs
I think the wording of this comment is kinda strange. What you're trying
to say is that homogeneous support for sdtrig (and the contexts) is
required.
> + */
> + node = of_cpu_device_node_get(cpu);
If there's no ACPI support, shouldn't the first thing here by a fast
path out before you start assuming DT?
> + if (!node)
> + goto sdtrig_csrs_disable_all;
> +
> + debug_node = of_get_compatible_child(node, "riscv,debug-v1.0.0");
> + of_node_put(node);
> +
> + if (!debug_node)
> + goto sdtrig_csrs_disable_all;
> +
> + trigger_module = of_get_child_by_name(debug_node, "trigger-module");
> + of_node_put(debug_node);
> +
> + if (!trigger_module)
> + goto sdtrig_csrs_disable_all;
> +
> + if (!(IS_ENABLED(CONFIG_KVM) &&
> + of_property_read_bool(trigger_module, "hcontext-present")))
> + atomic_inc(&hcontext_disable);
> +
> + if (!of_property_read_bool(trigger_module, "scontext-present"))
> + atomic_inc(&scontext_disable);
I think we should define pseudo extensions for {h,s}context-present and
parse this out of riscv,isa-extensions. That'd also give you the per-cpu
checks for homogeneous support for "free".
My immediate thought is that sdtrig doesn't seem valuable in isolation,
if you're gonna need additional properties that communicate support for
additional modes.
> + of_node_put(trigger_module);
> +
> + /*
> + * Before access to hcontext/scontext CSRs, if the smstateen
> + * extension is present, the accessibility will be controlled
> + * by the hstateen0[H]/sstateen0 CSRs.
> + */
> + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SMSTATEEN)) {
Why can't you use the non-underscore prefixed version of this function
here?
> + u64 hstateen_bit, sstateen_bit;
> +
> + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_h)) {
> +#if __riscv_xlen > 32
> + csr_set(CSR_HSTATEEN0, SMSTATEEN0_HSCONTEXT);
For zkr we require the CSR to be usable at the privilege level to which
the DT is passed:
- const: zkr
description:
The standard Zkr entropy source extension as ratified in version
1.0 of RISC-V Cryptography Extensions Volume I specification.
This string being present means that the CSR associated to this
extension is accessible at the privilege level to which that
device-tree has been provided.
I wonder if we should do something similar here and make this a
requirement for anything with bits in stateen registers. I'd love to
avoid having to read CSRs on all harts before being able to make
judgements about whether or not an extension is enabled. I dunno if that
is possible here though, given you want to also make some checks on the
exact nature of the support below.
Cheers,
Conor.
> + hstateen_bit = csr_read(CSR_HSTATEEN0);
> +#else
> + csr_set(CSR_HSTATEEN0H, SMSTATEEN0_HSCONTEXT >> 32);
> + hstateen_bit = csr_read(CSR_HSTATEEN0H) << 32;
> +#endif
> + if (!(hstateen_bit & SMSTATEEN0_HSCONTEXT))
> + goto sdtrig_csrs_disable_all;
> +
> + } else {
> + if (IS_ENABLED(CONFIG_KVM))
> + atomic_inc(&hcontext_disable);
> +
> + /*
> + * In RV32, the smstateen extension doesn't provide
> + * high 32 bits of sstateen0 CSR which represent
> + * accessibility for scontext CSR;
> + * The decision is left on whether the dts has the
> + * property to access the scontext CSR.
> + */
> +#if __riscv_xlen > 32
> + csr_set(CSR_SSTATEEN0, SMSTATEEN0_HSCONTEXT);
> + sstateen_bit = csr_read(CSR_SSTATEEN0);
> +
> + if (!(sstateen_bit & SMSTATEEN0_HSCONTEXT))
> + atomic_inc(&scontext_disable);
> +#endif
> + }
> + }
> +
> + /*
> + * The code can only access hcontext/scontext CSRs if:
> + * The cpu dts node have [h/s]context-present;
> + * If Smstateen extension is presented, then the accessibility bit
> + * toward hcontext/scontext CSRs is enabled; Or the Smstateen extension
> + * isn't available, thus the access won't be blocked by it.
> + *
> + * With writing 1 to the every bit of these CSRs, we retrieve the
> + * maximum bits that is available on the CSRs. and decide
> + * whether it's suit for its context recording operation.
> + */
> + if (IS_ENABLED(CONFIG_KVM) &&
> + !atomic_read(&hcontext_disable)) {
> + unsigned long hcontext_available_bits = 0;
> +
> + csr_write(CSR_HCONTEXT, -1UL);
> + hcontext_available_bits = csr_swap(CSR_HCONTEXT, hcontext_available_bits);
> +
> + /* hcontext CSR is required by at least 1 bit */
> + if (hcontext_available_bits)
> + atomic_long_and(hcontext_available_bits, &hcontext_id_share);
> + else
> + atomic_inc(&hcontext_disable);
> + }
> +
> + if (!atomic_read(&scontext_disable)) {
> + unsigned long scontext_available_bits = 0;
> +
> + csr_write(CSR_SCONTEXT, -1UL);
> + scontext_available_bits = csr_swap(CSR_SCONTEXT, scontext_available_bits);
> +
> + /* scontext CSR is required by at least the sizeof pid_t */
> + if (scontext_available_bits < ((1UL << (sizeof(pid_t) << 3)) - 1))
> + atomic_inc(&scontext_disable);
> + }
> +
> + return;
> +
> +sdtrig_csrs_disable_all:
> + if (IS_ENABLED(CONFIG_KVM))
> + atomic_inc(&hcontext_disable);
> +
> + atomic_inc(&scontext_disable);
> +}
> +
> +static int __init sdtrig_enable_csrs_fill(void)
> +{
> + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SDTRIG)) {
> + atomic_long_set(&hcontext_id_share, -1UL);
> +
> + /* check every CPUs sdtrig extension optional CSRs */
> + sdtrig_percpu_csrs_check(NULL);
> + smp_call_function(sdtrig_percpu_csrs_check, NULL, 1);
> +
> + if (IS_ENABLED(CONFIG_KVM) &&
> + !atomic_read(&hcontext_disable)) {
> + pr_info("riscv-sdtrig: Writing 'GuestOS ID' to hcontext CSR is enabled\n");
> + static_branch_enable(&use_hcontext);
> + }
> +
> + if (!atomic_read(&scontext_disable)) {
> + pr_info("riscv-sdtrig: Writing 'PID' to scontext CSR is enabled\n");
> + static_branch_enable(&use_scontext);
> + }
> + }
> + return 0;
> +}
> +
> +arch_initcall(sdtrig_enable_csrs_fill);
> +
> void riscv_user_isa_enable(void)
> {
> if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
>
> --
> 2.43.2
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH 2/2] v2 arm64: dts: qcom: Add support for Samsung Galaxy Z Fold5
From: Alexandru Serdeliuc @ 2024-03-29 9:43 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <4e1c225f-9b9a-4300-b4d3-2fc38c9b573c@linaro.org>
Thanks, indeed, v3 will contain the right messages
On 29/3/24 1:54, Konrad Dybcio wrote:
> On 29.03.2024 12:08 AM, Alexandru Marc Serdeliuc via B4 Relay wrote:
>> From: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
>>
>> Add support for Samsung Galaxy Z Fold5 (q5q) foldable phone
>>
>> Currently working features:
>> - Framebuffer
>> - UFS
>> - i2c
>> - Buttons
>>
>> Signed-off-by: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
>> ---
> Looks like the commit message and contents got mixed up!
>
> Konrad
^ permalink raw reply
* Re: [PATCH 1/2] V2 arm64: dts: qcom: Add support for Samsung Galaxy Z Fold5
From: Alexandru Serdeliuc @ 2024-03-29 9:42 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <1cdbd387-e937-4d5c-bedb-b4275fdf84cc@linaro.org>
Thanks, i added some notes inline as I do not know how to proceed with
some if the requirements.
Just to be noted, the sm8550-samsung-q5q.dts it is based on
sm8550-mtp.dts so most of the stuff is from there
On 29/3/24 1:52, Konrad Dybcio wrote:
> On 29.03.2024 12:08 AM, Alexandru Marc Serdeliuc via B4 Relay wrote:
>> From: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
>>
>> Add support for Samsung Galaxy Z Fold5 (q5q) foldable phone
>>
>> Currently working features:
>> - Framebuffer
>> - UFS
>> - i2c
>> - Buttons
>>
>> Signed-off-by: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
>> ---
The [PATCH] string is added automatically to the subject by b4, I don't
know how to add/insert custom text in there, I am going to read the b4
docs and see if i can spot how to do it.
> Your commit title now includes "V2". Move it inside the square braces the
> next time around, so it's like [PATCH v3 1/2]. With b4, this should be done
> automagically, though..
>
> [...]
>
>> +/ {
>> + model = "Samsung Galaxy Z Fold5";
>> + compatible = "samsung,q5q", "qcom,sm8550";
>> + #address-cells = <0x02>;
>> + #size-cells = <0x02>;
thanks, going to remove them
> These two can go
>
> [...]
>
>> + reserved-memory {
>> + /*
>> + * The bootloader will only keep display hardware enabled
>> + * if this memory region is named exactly 'splash_region'
>> + */
this is a reality, without it the framebuffer do not work, due to abl
https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/blob/LA.VENDOR.1.0.r2-09400-WAIPIO.QSSI14.0/QcomModulePkg/Library/BootLib/UpdateDeviceTree.c?ref_type=tags#L220
How to proceed?
> Ouch.
>
> [...]
>
>> + vreg_l15b_1p8: ldo15 {
>> + regulator-name = "vreg_l15b_1p8";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + regulator-allow-set-load;
>> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
>> + RPMH_REGULATOR_MODE_HPM>;
>> + regulator-always-on;
I have removed the nodes that uses this as the driver for "Texas
Instruments i2c eUSB2" is not yet submitted by the porter, however,
those are took from the existing sm8550-mtp.dts
How to proceed?
> Any particular reason as to why?
>
> [...]
>
>> +&remoteproc_adsp {
>> + firmware-name = "qcom/sm8550/adsp.mbn",
>> + "qcom/sm8550/adsp_dtb.mbn";
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_cdsp {
>> + firmware-name = "qcom/sm8550/cdsp.mbn",
>> + "qcom/sm8550/cdsp_dtb.mbn";
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_mpss {
>> + firmware-name = "qcom/sm8550/modem.mbn",
>> + "qcom/sm8550/modem_dtb.mbn";
>> + status = "okay";
Those are took from the device's running Android /firmware and load
without error, I used this kind of firmware loaded on other devices as
well and seems to do the job, the lines are as well on existing
sm8550-mtp.dts
How to proceed?
> Unless you stole one from the factory, these firmwares will not
> load on your phone..
>
>> +};
>> +
>> +&sleep_clk {
>> + clock-frequency = <32000>;
>> +};
>> +
>> +&tlmm {
>> + gpio-reserved-ranges = <36 4>, <50 2>;
I have no idea, i took the ranges from the running Android FDT, without
those ranges the kernel do not boot, i can dig more into these ranges if
required
> Would you have an idea what these GPIOs are used for?
>
> Konrad
^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: imx6ull: add seeed studio NPi dev board
From: Parthiban @ 2024-03-29 9:40 UTC (permalink / raw)
To: Shawn Guo
Cc: robh+dt, krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer,
kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel, Parthiban
In-Reply-To: <ZgY82LADJS9FuvY6@dragon>
Dear Shawn,
On 3/29/24 09:30, Shawn Guo wrote:
> On Thu, Feb 29, 2024 at 01:53:37PM +0530, Parthiban Nallathambi wrote:
>> Add support for Seed Stuidos NPi i.MX6ULL SoM equipped with
>> 512MB RAM and 8GB eMMC or 512MB NAND flash. Development
>> board comes with either eMMC or NAND based SoM with peripheral
>> interfaces like 2 x ethernet, 2 x USB, LCD, CSI and more.
>>
>> Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
>> ---
>> arch/arm/boot/dts/nxp/imx/Makefile | 2 +
>> .../imx/imx6ull-seeed-npi-dev-board-emmc.dts | 19 +
>> .../imx/imx6ull-seeed-npi-dev-board-nand.dts | 19 +
>> .../nxp/imx/imx6ull-seeed-npi-dev-board.dtsi | 424 ++++++++++++++++++
>> .../boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi | 155 +++++++
>> 5 files changed, 619 insertions(+)
>> create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-emmc.dts
>> create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-nand.dts
>> create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
>> create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi
>
> Could you elaborate a bit the point of splitting imx6ull-seeed-npi.dtsi
> and imx6ull-seeed-npi-dev-board.dtsi? Why cannot they be a single file?
imx6ull-seeed-npi.dtsi is for the npi SoM and -dev-board is for the board which uses the SoM.
Thanks,
Parthiban N
>
> Shawn
>
^ permalink raw reply
* [PATCH RFC 11/11] KVM: riscv: selftests: Add Sdtrig Extension to get-reg-list test
From: Max Hsu @ 2024-03-29 9:26 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Rafael J. Wysocki, Pavel Machek,
Anup Patel, Atish Patra, Paolo Bonzini, Shuah Khan
Cc: Palmer Dabbelt, linux-riscv, devicetree, linux-kernel, linux-pm,
kvm, kvm-riscv, linux-kselftest, Max Hsu, Yong-Xuan Wang
In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com>
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Update the get-reg-list test to test the Sdtrig Extension is available
for guest OS.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Co-developed-by: Max Hsu <max.hsu@sifive.com>
Signed-off-by: Max Hsu <max.hsu@sifive.com>
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index b882b7b9b785..f2696e308509 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -41,6 +41,7 @@ bool filter_reg(__u64 reg)
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_I:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_M:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V:
+ case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SDTRIG:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC:
@@ -247,6 +248,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id)
"KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"
#define RISCV_CSR_SMSTATEEN(csr) \
"KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"
+#define RISCV_CSR_SDTRIG(csr) \
+ "KVM_REG_RISCV_CSR_SDTRIG | KVM_REG_RISCV_CSR_REG(" #csr ")"
static const char *general_csr_id_to_str(__u64 reg_off)
{
@@ -314,6 +317,18 @@ static const char *smstateen_csr_id_to_str(__u64 reg_off)
return NULL;
}
+static const char *sdtrig_csr_id_to_str(__u64 reg_off)
+{
+ /* reg_off is the offset into struct kvm_riscv_smstateen_csr */
+ switch (reg_off) {
+ case KVM_REG_RISCV_CSR_SDTRIG_REG(scontext):
+ return RISCV_CSR_SDTRIG(scontext);
+ }
+
+ TEST_FAIL("Unknown sdtrig csr reg: 0x%llx", reg_off);
+ return NULL;
+}
+
static const char *csr_id_to_str(const char *prefix, __u64 id)
{
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);
@@ -330,6 +345,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id)
return aia_csr_id_to_str(reg_off);
case KVM_REG_RISCV_CSR_SMSTATEEN:
return smstateen_csr_id_to_str(reg_off);
+ case KVM_REG_RISCV_CSR_SDTRIG:
+ return sdtrig_csr_id_to_str(reg_off);
}
return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
@@ -406,6 +423,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
KVM_ISA_EXT_ARR(I),
KVM_ISA_EXT_ARR(M),
KVM_ISA_EXT_ARR(V),
+ KVM_ISA_EXT_ARR(SDTRIG),
KVM_ISA_EXT_ARR(SMSTATEEN),
KVM_ISA_EXT_ARR(SSAIA),
KVM_ISA_EXT_ARR(SSTC),
@@ -764,6 +782,11 @@ static __u64 smstateen_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN,
};
+static __u64 sdtrig_regs[] = {
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SDTRIG | KVM_REG_RISCV_CSR_SDTRIG_REG(scontext),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SDTRIG,
+};
+
static __u64 fp_f_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]),
KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]),
@@ -853,6 +876,8 @@ static __u64 fp_d_regs[] = {
{"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}
#define SUBLIST_AIA \
{"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}
+#define SUBLIST_SDTRIG \
+ {"sdtrig", .feature = KVM_RISCV_ISA_EXT_SDTRIG, .regs = sdtrig_regs, .regs_n = ARRAY_SIZE(sdtrig_regs),}
#define SUBLIST_SMSTATEEN \
{"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}
#define SUBLIST_FP_F \
@@ -930,6 +955,7 @@ KVM_ISA_EXT_SUBLIST_CONFIG(aia, AIA);
KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F);
KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D);
KVM_ISA_EXT_SIMPLE_CONFIG(h, H);
+KVM_ISA_EXT_SUBLIST_CONFIG(sdtrig, SDTRIG);
KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN);
KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);
KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
@@ -985,6 +1011,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
&config_fp_f,
&config_fp_d,
&config_h,
+ &config_sdtrig,
&config_smstateen,
&config_sstc,
&config_svinval,
--
2.43.2
^ permalink raw reply related
* [PATCH RFC 10/11] riscv: KVM: Add hcontext support
From: Max Hsu @ 2024-03-29 9:26 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Rafael J. Wysocki, Pavel Machek,
Anup Patel, Atish Patra, Paolo Bonzini, Shuah Khan
Cc: Palmer Dabbelt, linux-riscv, devicetree, linux-kernel, linux-pm,
kvm, kvm-riscv, linux-kselftest, Max Hsu, Yong-Xuan Wang
In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com>
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
hcontext CSR store the ID of the currently running machine status.
When a virtual machine is initialized, it will obtain and utilize
the first available ID.
It will be updated to VM ID when switch to a virtual machine,
and updated to 0 when switch back to host machine.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Co-developed-by: Max Hsu <max.hsu@sifive.com>
Signed-off-by: Max Hsu <max.hsu@sifive.com>
---
arch/riscv/include/asm/kvm_host.h | 3 ++
arch/riscv/include/asm/kvm_vcpu_debug.h | 7 +++
arch/riscv/kvm/main.c | 4 ++
arch/riscv/kvm/vcpu_debug.c | 78 +++++++++++++++++++++++++++++++++
arch/riscv/kvm/vm.c | 4 ++
5 files changed, 96 insertions(+)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index d495279d99e1..b5d972783116 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -103,6 +103,9 @@ struct kvm_arch {
/* AIA Guest/VM context */
struct kvm_aia aia;
+
+ /* hcontext ID for guest VM */
+ unsigned long hcontext;
};
struct kvm_cpu_trap {
diff --git a/arch/riscv/include/asm/kvm_vcpu_debug.h b/arch/riscv/include/asm/kvm_vcpu_debug.h
index 6e7ce6b408a6..0a025fc4e6dd 100644
--- a/arch/riscv/include/asm/kvm_vcpu_debug.h
+++ b/arch/riscv/include/asm/kvm_vcpu_debug.h
@@ -11,6 +11,13 @@
#include <linux/types.h>
+DECLARE_STATIC_KEY_FALSE(use_hcontext);
+extern atomic_long_t hcontext_id_share;
+
+void kvm_riscv_debug_init(void);
+void kvm_riscv_debug_exit(void);
+void kvm_riscv_debug_get_hcontext_id(struct kvm *kvm);
+void kvm_riscv_debug_return_hcontext_id(struct kvm *kvm);
void kvm_riscv_debug_vcpu_swap_in_guest_context(struct kvm_vcpu *vcpu);
void kvm_riscv_debug_vcpu_swap_in_host_context(struct kvm_vcpu *vcpu);
diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
index 225a435d9c9a..ff28b96ad70b 100644
--- a/arch/riscv/kvm/main.c
+++ b/arch/riscv/kvm/main.c
@@ -125,6 +125,8 @@ static int __init riscv_kvm_init(void)
return rc;
}
+ kvm_riscv_debug_init();
+
return 0;
}
module_init(riscv_kvm_init);
@@ -133,6 +135,8 @@ static void __exit riscv_kvm_exit(void)
{
kvm_riscv_aia_exit();
+ kvm_riscv_debug_exit();
+
kvm_exit();
}
module_exit(riscv_kvm_exit);
diff --git a/arch/riscv/kvm/vcpu_debug.c b/arch/riscv/kvm/vcpu_debug.c
index e7e9263c2e30..5081c272f01d 100644
--- a/arch/riscv/kvm/vcpu_debug.c
+++ b/arch/riscv/kvm/vcpu_debug.c
@@ -6,6 +6,84 @@
#include <linux/kvm_host.h>
#include <asm/switch_to.h>
+DEFINE_SPINLOCK(hcontext_lock);
+unsigned long *hcontext_bitmap;
+unsigned long hcontext_bitmap_len;
+
+static __always_inline bool has_hcontext(void)
+{
+ return static_branch_likely(&use_hcontext);
+}
+
+void kvm_riscv_debug_init(void)
+{
+ /*
+ * As from riscv-debug-spec, Chapter 5.7.9:
+ * If the H extension is implemented, it’s recommended to
+ * implement no more than 7 bits on RV32 and 14 on RV64.
+ * Allocating bit array according to spec size.
+ */
+#if __riscv_xlen > 32
+ unsigned long tmp = atomic_long_read(&hcontext_id_share) & GENMASK(13, 0);
+#else
+ unsigned long tmp = atomic_long_read(&hcontext_id_share) & GENMASK(6, 0);
+#endif
+ if (has_hcontext()) {
+ while (tmp) {
+ kvm_info("hcontext: try to allocate 0x%lx-bit array\n", tmp);
+ hcontext_bitmap_len = tmp + 1;
+ hcontext_bitmap = bitmap_zalloc(tmp, 0);
+ if (hcontext_bitmap)
+ break;
+ tmp = tmp >> 1;
+ }
+
+ if (tmp == 0) {
+ /* We can't allocate any space for hcontext bitmap */
+ static_branch_disable(&use_hcontext);
+ } else {
+ /* ID 0 is hypervisor */
+ set_bit(0, hcontext_bitmap);
+ }
+ }
+}
+
+void kvm_riscv_debug_exit(void)
+{
+ if (has_hcontext()) {
+ static_branch_disable(&use_hcontext);
+ kfree(hcontext_bitmap);
+ }
+}
+
+void kvm_riscv_debug_get_hcontext_id(struct kvm *kvm)
+{
+ if (has_hcontext()) {
+ unsigned long free_id;
+
+ spin_lock(&hcontext_lock);
+ free_id = find_first_zero_bit(hcontext_bitmap, hcontext_bitmap_len);
+
+ /* share the maximum ID when we run out of the hcontext ID */
+ if (free_id <= hcontext_bitmap_len)
+ set_bit(free_id, hcontext_bitmap);
+ else
+ free_id -= 1;
+
+ kvm->arch.hcontext = free_id;
+ spin_unlock(&hcontext_lock);
+ }
+}
+
+void kvm_riscv_debug_return_hcontext_id(struct kvm *kvm)
+{
+ if (has_hcontext()) {
+ spin_lock(&hcontext_lock);
+ clear_bit(kvm->arch.hcontext, hcontext_bitmap);
+ spin_unlock(&hcontext_lock);
+ }
+}
+
void kvm_riscv_debug_vcpu_swap_in_guest_context(struct kvm_vcpu *vcpu)
{
struct kvm_vcpu_sdtrig_csr *csr = &vcpu->arch.sdtrig_csr;
diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c
index ce58bc48e5b8..275f5f05d4dd 100644
--- a/arch/riscv/kvm/vm.c
+++ b/arch/riscv/kvm/vm.c
@@ -45,6 +45,8 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
kvm_riscv_guest_timer_init(kvm);
+ kvm_riscv_debug_get_hcontext_id(kvm);
+
return 0;
}
@@ -53,6 +55,8 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
kvm_destroy_vcpus(kvm);
kvm_riscv_aia_destroy_vm(kvm);
+
+ kvm_riscv_debug_return_hcontext_id(kvm);
}
int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irql,
--
2.43.2
^ permalink raw reply related
* [PATCH RFC 09/11] riscv: KVM: Add scontext to ONE_REG
From: Max Hsu @ 2024-03-29 9:26 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Rafael J. Wysocki, Pavel Machek,
Anup Patel, Atish Patra, Paolo Bonzini, Shuah Khan
Cc: Palmer Dabbelt, linux-riscv, devicetree, linux-kernel, linux-pm,
kvm, kvm-riscv, linux-kselftest, Max Hsu, Yong-Xuan Wang
In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com>
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Updte the ONE_REG interface to allow the scontext CSR can be accessed from
user space.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Co-developed-by: Max Hsu <max.hsu@sifive.com>
Signed-off-by: Max Hsu <max.hsu@sifive.com>
---
arch/riscv/include/uapi/asm/kvm.h | 8 +++++
arch/riscv/kvm/vcpu_onereg.c | 62 +++++++++++++++++++++++++++++++++++++--
2 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 9f70da85ed51..1886722127d7 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -98,6 +98,11 @@ struct kvm_riscv_smstateen_csr {
unsigned long sstateen0;
};
+/* Sdtrig CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_sdtrig_csr {
+ unsigned long scontext;
+};
+
/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_timer {
__u64 frequency;
@@ -224,12 +229,15 @@ struct kvm_riscv_sbi_sta {
#define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
#define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
#define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_CSR_SDTRIG (0x3 << KVM_REG_RISCV_SUBTYPE_SHIFT)
#define KVM_REG_RISCV_CSR_REG(name) \
(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
#define KVM_REG_RISCV_CSR_AIA_REG(name) \
(offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
#define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \
(offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long))
+#define KVM_REG_RISCV_CSR_SDTRIG_REG(name) \
+ (offsetof(struct kvm_riscv_sdtrig_csr, name) / sizeof(unsigned long))
/* Timer registers are mapped as type 4 */
#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 10dda5ddc0a6..2796a86ec70b 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -471,6 +471,34 @@ static int kvm_riscv_vcpu_smstateen_get_csr(struct kvm_vcpu *vcpu,
return 0;
}
+static inline int kvm_riscv_vcpu_sdtrig_set_csr(struct kvm_vcpu *vcpu,
+ unsigned long reg_num,
+ unsigned long reg_val)
+{
+ struct kvm_vcpu_sdtrig_csr *csr = &vcpu->arch.sdtrig_csr;
+
+ if (reg_num >= sizeof(struct kvm_riscv_sdtrig_csr) /
+ sizeof(unsigned long))
+ return -EINVAL;
+
+ ((unsigned long *)csr)[reg_num] = reg_val;
+ return 0;
+}
+
+static int kvm_riscv_vcpu_sdtrig_get_csr(struct kvm_vcpu *vcpu,
+ unsigned long reg_num,
+ unsigned long *out_val)
+{
+ struct kvm_vcpu_sdtrig_csr *csr = &vcpu->arch.sdtrig_csr;
+
+ if (reg_num >= sizeof(struct kvm_riscv_sdtrig_csr) /
+ sizeof(unsigned long))
+ return -EINVAL;
+
+ *out_val = ((unsigned long *)csr)[reg_num];
+ return 0;
+}
+
static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu,
const struct kvm_one_reg *reg)
{
@@ -500,6 +528,11 @@ static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu,
rc = kvm_riscv_vcpu_smstateen_get_csr(vcpu, reg_num,
®_val);
break;
+ case KVM_REG_RISCV_CSR_SDTRIG:
+ rc = -EINVAL;
+ if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SDTRIG))
+ rc = kvm_riscv_vcpu_sdtrig_get_csr(vcpu, reg_num, ®_val);
+ break;
default:
rc = -ENOENT;
break;
@@ -545,6 +578,11 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu,
rc = kvm_riscv_vcpu_smstateen_set_csr(vcpu, reg_num,
reg_val);
break;
+ case KVM_REG_RISCV_CSR_SDTRIG:
+ rc = -EINVAL;
+ if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SDTRIG))
+ rc = kvm_riscv_vcpu_sdtrig_set_csr(vcpu, reg_num, reg_val);
+ break;
default:
rc = -ENOENT;
break;
@@ -803,6 +841,8 @@ static inline unsigned long num_csr_regs(const struct kvm_vcpu *vcpu)
n += sizeof(struct kvm_riscv_aia_csr) / sizeof(unsigned long);
if (riscv_isa_extension_available(vcpu->arch.isa, SMSTATEEN))
n += sizeof(struct kvm_riscv_smstateen_csr) / sizeof(unsigned long);
+ if (riscv_isa_extension_available(vcpu->arch.isa, SDTRIG))
+ n += sizeof(struct kvm_riscv_sdtrig_csr) / sizeof(unsigned long);
return n;
}
@@ -811,7 +851,7 @@ static int copy_csr_reg_indices(const struct kvm_vcpu *vcpu,
u64 __user *uindices)
{
int n1 = sizeof(struct kvm_riscv_csr) / sizeof(unsigned long);
- int n2 = 0, n3 = 0;
+ int n2 = 0, n3 = 0, n4 = 0;
/* copy general csr regs */
for (int i = 0; i < n1; i++) {
@@ -863,7 +903,25 @@ static int copy_csr_reg_indices(const struct kvm_vcpu *vcpu,
}
}
- return n1 + n2 + n3;
+ /* copy Sdtrig csr regs */
+ if (riscv_isa_extension_available(vcpu->arch.isa, SDTRIG)) {
+ n4 = sizeof(struct kvm_riscv_sdtrig_csr) / sizeof(unsigned long);
+
+ for (int i = 0; i < n4; i++) {
+ u64 size = IS_ENABLED(CONFIG_32BIT) ?
+ KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
+ u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR |
+ KVM_REG_RISCV_CSR_SDTRIG | i;
+
+ if (uindices) {
+ if (put_user(reg, uindices))
+ return -EFAULT;
+ uindices++;
+ }
+ }
+ }
+
+ return n1 + n2 + n3 + n4;
}
static inline unsigned long num_timer_regs(void)
--
2.43.2
^ permalink raw reply related
* [PATCH RFC 08/11] riscv: KVM: Add Sdtrig Extension Support for Guest/VM
From: Max Hsu @ 2024-03-29 9:26 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Rafael J. Wysocki, Pavel Machek,
Anup Patel, Atish Patra, Paolo Bonzini, Shuah Khan
Cc: Palmer Dabbelt, linux-riscv, devicetree, linux-kernel, linux-pm,
kvm, kvm-riscv, linux-kselftest, Max Hsu, Yong-Xuan Wang
In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com>
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
We extend the KVM ISA extension ONE_REG interface to allow VMM
tools to detect and enable Sdtrig extension for Guest/VM. We
also save/restore the scontext CSR for guest VCPUs and set the
HSCONTEXT bit in hstateen0 CSR if the scontext CSR is available
for Guest/VM when the Smstateen extension is present.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Co-developed-by: Max Hsu <max.hsu@sifive.com>
Signed-off-by: Max Hsu <max.hsu@sifive.com>
---
arch/riscv/include/asm/kvm_host.h | 11 +++++++++++
arch/riscv/include/asm/kvm_vcpu_debug.h | 17 +++++++++++++++++
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/Makefile | 1 +
arch/riscv/kvm/vcpu.c | 8 ++++++++
arch/riscv/kvm/vcpu_debug.c | 29 +++++++++++++++++++++++++++++
arch/riscv/kvm/vcpu_onereg.c | 1 +
7 files changed, 68 insertions(+)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 484d04a92fa6..d495279d99e1 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -21,6 +21,7 @@
#include <asm/kvm_vcpu_sbi.h>
#include <asm/kvm_vcpu_timer.h>
#include <asm/kvm_vcpu_pmu.h>
+#include <asm/kvm_vcpu_debug.h>
#define KVM_MAX_VCPUS 1024
@@ -175,6 +176,10 @@ struct kvm_vcpu_smstateen_csr {
unsigned long sstateen0;
};
+struct kvm_vcpu_sdtrig_csr {
+ unsigned long scontext;
+};
+
struct kvm_vcpu_arch {
/* VCPU ran at least once */
bool ran_atleast_once;
@@ -197,6 +202,9 @@ struct kvm_vcpu_arch {
unsigned long host_senvcfg;
unsigned long host_sstateen0;
+ /* SCONTEXT of Host */
+ unsigned long host_scontext;
+
/* CPU context of Host */
struct kvm_cpu_context host_context;
@@ -209,6 +217,9 @@ struct kvm_vcpu_arch {
/* CPU Smstateen CSR context of Guest VCPU */
struct kvm_vcpu_smstateen_csr smstateen_csr;
+ /* CPU Sdtrig CSR context of Guest VCPU */
+ struct kvm_vcpu_sdtrig_csr sdtrig_csr;
+
/* CPU context upon Guest VCPU reset */
struct kvm_cpu_context guest_reset_context;
diff --git a/arch/riscv/include/asm/kvm_vcpu_debug.h b/arch/riscv/include/asm/kvm_vcpu_debug.h
new file mode 100644
index 000000000000..6e7ce6b408a6
--- /dev/null
+++ b/arch/riscv/include/asm/kvm_vcpu_debug.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 SiFive
+ *
+ * Authors:
+ * Yong-Xuan Wang <yongxuan.wang@sifive.com>
+ */
+
+#ifndef __KVM_VCPU_RISCV_DEBUG_H
+#define __KVM_VCPU_RISCV_DEBUG_H
+
+#include <linux/types.h>
+
+void kvm_riscv_debug_vcpu_swap_in_guest_context(struct kvm_vcpu *vcpu);
+void kvm_riscv_debug_vcpu_swap_in_host_context(struct kvm_vcpu *vcpu);
+
+#endif
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index b1c503c2959c..9f70da85ed51 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -167,6 +167,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_ZFA,
KVM_RISCV_ISA_EXT_ZTSO,
KVM_RISCV_ISA_EXT_ZACAS,
+ KVM_RISCV_ISA_EXT_SDTRIG,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile
index c9646521f113..387be968d9ea 100644
--- a/arch/riscv/kvm/Makefile
+++ b/arch/riscv/kvm/Makefile
@@ -15,6 +15,7 @@ kvm-y += vmid.o
kvm-y += tlb.o
kvm-y += mmu.o
kvm-y += vcpu.o
+kvm-y += vcpu_debug.o
kvm-y += vcpu_exit.o
kvm-y += vcpu_fp.o
kvm-y += vcpu_vector.o
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index b5ca9f2e98ac..1d0e43ab0652 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -20,6 +20,7 @@
#include <asm/csr.h>
#include <asm/cacheflush.h>
#include <asm/kvm_vcpu_vector.h>
+#include <asm/switch_to.h>
const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
KVM_GENERIC_VCPU_STATS(),
@@ -504,6 +505,9 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
SMSTATEEN0_AIA_ISEL;
if (riscv_isa_extension_available(isa, SMSTATEEN))
cfg->hstateen0 |= SMSTATEEN0_SSTATEEN0;
+
+ if (has_scontext())
+ cfg->hstateen0 |= SMSTATEEN0_HSCONTEXT;
}
}
@@ -643,6 +647,8 @@ static __always_inline void kvm_riscv_vcpu_swap_in_guest_state(struct kvm_vcpu *
(cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
vcpu->arch.host_sstateen0 = csr_swap(CSR_SSTATEEN0,
smcsr->sstateen0);
+
+ kvm_riscv_debug_vcpu_swap_in_guest_context(vcpu);
}
static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_vcpu *vcpu)
@@ -656,6 +662,8 @@ static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_vcpu *v
(cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
smcsr->sstateen0 = csr_swap(CSR_SSTATEEN0,
vcpu->arch.host_sstateen0);
+
+ kvm_riscv_debug_vcpu_swap_in_host_context(vcpu);
}
/*
diff --git a/arch/riscv/kvm/vcpu_debug.c b/arch/riscv/kvm/vcpu_debug.c
new file mode 100644
index 000000000000..e7e9263c2e30
--- /dev/null
+++ b/arch/riscv/kvm/vcpu_debug.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 SiFive
+ */
+
+#include <linux/kvm_host.h>
+#include <asm/switch_to.h>
+
+void kvm_riscv_debug_vcpu_swap_in_guest_context(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_sdtrig_csr *csr = &vcpu->arch.sdtrig_csr;
+ unsigned long hcontext = vcpu->kvm->arch.hcontext;
+
+ if (has_hcontext())
+ csr_write(CSR_HCONTEXT, hcontext);
+ if (has_scontext())
+ vcpu->arch.host_scontext = csr_swap(CSR_SCONTEXT, csr->scontext);
+}
+
+void kvm_riscv_debug_vcpu_swap_in_host_context(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_sdtrig_csr *csr = &vcpu->arch.sdtrig_csr;
+
+ /* Hypervisor uses the hcontext ID 0 */
+ if (has_hcontext())
+ csr_write(CSR_HCONTEXT, 0);
+ if (has_scontext())
+ csr->scontext = csr_swap(CSR_SCONTEXT, vcpu->arch.host_scontext);
+}
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index f4a6124d25c9..10dda5ddc0a6 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -34,6 +34,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,
/* Multi letter extensions (alphabetically sorted) */
+ KVM_ISA_EXT_ARR(SDTRIG),
KVM_ISA_EXT_ARR(SMSTATEEN),
KVM_ISA_EXT_ARR(SSAIA),
KVM_ISA_EXT_ARR(SSTC),
--
2.43.2
^ permalink raw reply related
* [PATCH RFC 07/11] riscv: Add task switch support for scontext CSR
From: Max Hsu @ 2024-03-29 9:26 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Rafael J. Wysocki, Pavel Machek,
Anup Patel, Atish Patra, Paolo Bonzini, Shuah Khan
Cc: Palmer Dabbelt, linux-riscv, devicetree, linux-kernel, linux-pm,
kvm, kvm-riscv, linux-kselftest, Max Hsu, Nick Hu
In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com>
Write the next task PID to the scontext CSR if the use_scontext
static branch is enabled by the detection of the cpufeature.c
The scontext CSR needs to be saved and restored when entering
a non-retentive idle state so that when resuming the CPU,
the task's PID on the scontext CSR will be correct.
Co-developed-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Max Hsu <max.hsu@sifive.com>
---
arch/riscv/include/asm/suspend.h | 1 +
arch/riscv/include/asm/switch_to.h | 9 +++++++++
arch/riscv/kernel/suspend.c | 7 +++++++
3 files changed, 17 insertions(+)
diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
index 2ecace073869..5021cad7e815 100644
--- a/arch/riscv/include/asm/suspend.h
+++ b/arch/riscv/include/asm/suspend.h
@@ -13,6 +13,7 @@ struct suspend_context {
/* Saved and restored by low-level functions */
struct pt_regs regs;
/* Saved and restored by high-level functions */
+ unsigned long scontext;
unsigned long scratch;
unsigned long envcfg;
unsigned long tvec;
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 07432550ed54..289cd6b60978 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -8,6 +8,7 @@
#include <linux/jump_label.h>
#include <linux/sched/task_stack.h>
+#include <linux/pid.h>
#include <asm/vector.h>
#include <asm/cpufeature.h>
#include <asm/processor.h>
@@ -75,6 +76,12 @@ static __always_inline bool has_scontext(void)
return static_branch_likely(&use_scontext);
}
+static __always_inline void __switch_to_scontext(struct task_struct *__prev,
+ struct task_struct *__next)
+{
+ csr_write(CSR_SCONTEXT, task_pid_nr(__next));
+}
+
extern struct task_struct *__switch_to(struct task_struct *,
struct task_struct *);
@@ -86,6 +93,8 @@ do { \
__switch_to_fpu(__prev, __next); \
if (has_vector()) \
__switch_to_vector(__prev, __next); \
+ if (has_scontext()) \
+ __switch_to_scontext(__prev, __next); \
((last) = __switch_to(__prev, __next)); \
} while (0)
diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
index a086da222872..6b403a1f75c3 100644
--- a/arch/riscv/kernel/suspend.c
+++ b/arch/riscv/kernel/suspend.c
@@ -11,9 +11,13 @@
#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/suspend.h>
+#include <asm/switch_to.h>
void suspend_save_csrs(struct suspend_context *context)
{
+ if (has_scontext())
+ context->scontext = csr_read(CSR_SCONTEXT);
+
context->scratch = csr_read(CSR_SCRATCH);
if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
context->envcfg = csr_read(CSR_ENVCFG);
@@ -46,6 +50,9 @@ void suspend_save_csrs(struct suspend_context *context)
void suspend_restore_csrs(struct suspend_context *context)
{
+ if (has_scontext())
+ csr_write(CSR_SCONTEXT, context->scontext);
+
csr_write(CSR_SCRATCH, context->scratch);
if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
csr_write(CSR_ENVCFG, context->envcfg);
--
2.43.2
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox