* [PATCH AUTOSEL 6.8 13/68] arm64: dts: qcom: qcm6490-idp: Add definition for three LEDs
From: Sasha Levin @ 2024-03-29 12:25 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Hui Liu, Dmitry Baryshkov, Bjorn Andersson, Sasha Levin,
konrad.dybcio, robh, krzysztof.kozlowski+dt, conor+dt,
linux-arm-msm, devicetree
In-Reply-To: <20240329122652.3082296-1-sashal@kernel.org>
From: Hui Liu <quic_huliu@quicinc.com>
[ Upstream commit 8385383cc2c2f7039ecc57864043112cdc7026c7 ]
Add definition for three LEDs to make sure they can
be enabled base on QCOM LPG LED driver.
Signed-off-by: Hui Liu <quic_huliu@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-lpg-v6-1-f879cecbce69@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 28 ++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
index 03e97e27d16d4..b3853fba5c3c5 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7280.dtsi"
#include "pm7325.dtsi"
@@ -415,6 +416,33 @@ vreg_bob_3p296: bob {
};
};
+&pm8350c_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
--
2.43.0
^ permalink raw reply related
* [PATCH AUTOSEL 6.8 06/68] arm64: dts: qcom: Add support for Xiaomi Redmi Note 9S
From: Sasha Levin @ 2024-03-29 12:25 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Joe Mason, Konrad Dybcio, David Wronek, Bjorn Andersson,
Sasha Levin, robh, krzysztof.kozlowski+dt, conor+dt,
linux-arm-msm, devicetree
In-Reply-To: <20240329122652.3082296-1-sashal@kernel.org>
From: Joe Mason <buddyjojo06@outlook.com>
[ Upstream commit 6016fb7c91f72f4afbb4017e13cd91954d0f1a9b ]
Add a device tree for the Xiaomi Redmi Note 9S (curtana) phone, based on
sm7125-xiaomi-common.dtsi.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Joe Mason <buddyjojo06@outlook.com>
Signed-off-by: David Wronek <davidwronek@gmail.com>
Link: https://lore.kernel.org/r/20240121-sm7125-upstream-v4-8-f7d1212c8ebb@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/sm7125-xiaomi-curtana.dts | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 39889d5f8e123..2e6984bbbb836 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -210,6 +210,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts b/arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts
new file mode 100644
index 0000000000000..12f517a8492c3
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023, Joe Mason <buddyjojo06@outlook.com>
+ */
+
+/dts-v1/;
+
+#include "sm7125-xiaomi-common.dtsi"
+
+/ {
+ model = "Xiaomi Redmi Note 9S";
+ compatible = "xiaomi,curtana", "qcom,sm7125";
+
+ /* required for bootloader to select correct board */
+ qcom,board-id = <0x20022 1>;
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v2 3/3] arm64: dts: qcom: sm7225-fairphone-fp4: Enable USB role switching
From: Luca Weiss @ 2024-03-29 12:26 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss
In-Reply-To: <20240329-fp4-tcpm-v2-0-d7f8cd165355@fairphone.com>
Configure the Type-C and VBUS regulator on PM7250B and wire it up to the
USB PHY, so that USB role and orientation switching works.
For now USB Power Delivery properties are skipped / disabled, so that
the (presumably) bootloader-configured charger doesn't get messed with
and we can charge the phone with at least some amount of power.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 47 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 60 ++++++++++++++++++++++-
2 files changed, 106 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index b663c1b18f61..2e135989de8c 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1717,6 +1717,33 @@ usb_1_qmpphy: phy@88e8000 {
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
};
dc_noc: interconnect@9160000 {
@@ -1892,6 +1919,26 @@ usb_1_dwc3: usb@a600000 {
snps,hird-threshold = /bits/ 8 <0x10>;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss_out: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ };
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
index bc67e8c1fe4d..5d7778c48413 100644
--- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
+++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
@@ -19,6 +19,7 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/usb/pd.h>
#include "sm7225.dtsi"
#include "pm6150l.dtsi"
#include "pm6350.dtsi"
@@ -543,6 +544,53 @@ conn-therm@1 {
};
};
+&pm7250b_typec {
+ vdd-pdphy-supply = <&vreg_l3a>;
+
+ status = "okay";
+
+ connector {
+ compatible = "usb-c-connector";
+
+ power-role = "dual";
+ data-role = "dual";
+ self-powered;
+
+ /*
+ * Disable USB Power Delivery for now, seems to need extra work
+ * to support role switching while also letting the battery
+ * charge still - without charger driver
+ */
+ typec-power-opmode = "default";
+ pd-disable;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ pm7250b_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ pm7250b_ss_in: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_out>;
+ };
+ };
+ };
+ };
+};
+
+&pm7250b_vbus {
+ regulator-min-microamp = <500000>;
+ regulator-max-microamp = <1500000>;
+ status = "okay";
+};
+
&pmk8350_rtc {
status = "okay";
};
@@ -726,7 +774,12 @@ &usb_1 {
&usb_1_dwc3 {
maximum-speed = "super-speed";
- dr_mode = "peripheral";
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs_out {
+ remote-endpoint = <&pm7250b_hs_in>;
};
&usb_1_hsphy {
@@ -740,10 +793,15 @@ &usb_1_hsphy {
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l22a>;
vdda-pll-supply = <&vreg_l16a>;
+ orientation-switch;
status = "okay";
};
+&usb_1_qmpphy_out {
+ remote-endpoint = <&pm7250b_ss_in>;
+};
+
&wifi {
vdd-0.8-cx-mx-supply = <&vreg_l4a>;
vdd-1.8-xo-supply = <&vreg_l7a>;
--
2.44.0
^ permalink raw reply related
* [PATCH v2 2/3] arm64: dts: qcom: pm7250b: Add a TCPM description
From: Luca Weiss @ 2024-03-29 12:26 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss, Bryan O'Donoghue
In-Reply-To: <20240329-fp4-tcpm-v2-0-d7f8cd165355@fairphone.com>
Type-C port management functionality lives inside of the PMIC block on
pm7250b.
The Type-C port management logic controls orientation detection,
vbus/vconn sense and to send/receive Type-C Power Domain messages.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/pm7250b.dtsi | 39 +++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi
index 4faed25a787f..0205c2669093 100644
--- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi
@@ -51,6 +51,45 @@ pm7250b_vbus: usb-vbus-regulator@1100 {
status = "disabled";
};
+ pm7250b_typec: typec@1500 {
+ compatible = "qcom,pm7250b-typec", "qcom,pm8150b-typec";
+ reg = <0x1500>,
+ <0x1700>;
+ interrupts = <PM7250B_SID 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
+ <PM7250B_SID 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x15 0x03 IRQ_TYPE_EDGE_BOTH>,
+ <PM7250B_SID 0x15 0x04 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x15 0x05 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x15 0x06 IRQ_TYPE_EDGE_BOTH>,
+ <PM7250B_SID 0x15 0x07 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x00 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x01 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x02 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x03 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x04 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x05 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x06 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x07 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "or-rid-detect-change",
+ "vpd-detect",
+ "cc-state-change",
+ "vconn-oc",
+ "vbus-change",
+ "attach-detach",
+ "legacy-cable-detect",
+ "try-snk-src-detect",
+ "sig-tx",
+ "sig-rx",
+ "msg-tx",
+ "msg-rx",
+ "msg-tx-failed",
+ "msg-tx-discarded",
+ "msg-rx-discarded",
+ "fr-swap";
+ vdd-vbus-supply = <&pm7250b_vbus>;
+ };
+
pm7250b_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
--
2.44.0
^ permalink raw reply related
* [PATCH v2 1/3] arm64: dts: qcom: pm7250b: Add node for PMIC VBUS booster
From: Luca Weiss @ 2024-03-29 12:26 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss, Bryan O'Donoghue
In-Reply-To: <20240329-fp4-tcpm-v2-0-d7f8cd165355@fairphone.com>
Add the required DTS node for the USB VBUS output regulator, which is
available on PM7250B. This will provide the VBUS source to connected
peripherals.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/pm7250b.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi
index 3bf7cf5d1700..4faed25a787f 100644
--- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi
@@ -45,6 +45,12 @@ pmic@PM7250B_SID {
#address-cells = <1>;
#size-cells = <0>;
+ pm7250b_vbus: usb-vbus-regulator@1100 {
+ compatible = "qcom,pm7250b-vbus-reg", "qcom,pm8150b-vbus-reg";
+ reg = <0x1100>;
+ status = "disabled";
+ };
+
pm7250b_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
--
2.44.0
^ permalink raw reply related
* [PATCH v2 0/3] Add TCPM support for PM7250B and Fairphone 4
From: Luca Weiss @ 2024-03-29 12:26 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss, Bryan O'Donoghue
This series adds support for Type-C Port Management on the Fairphone 4
which enables USB role switching and orientation switching.
This enables a user for example to plug in a USB stick or a USB keyboard
to the Type-C port.
To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: ~postmarketos/upstreaming@lists.sr.ht
Cc: phone-devel@vger.kernel.org
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Changes in v2:
- Move disabled as last property for pm7250b_vbus
- Update USB graph to newer version, connect both HS and SS signals
- Update FP4 Type-C properties, try to keep phone charging intact by
disabling USB PD for now
- Pick up tags
- Drop patches that landed in linux-next already
- Link to v1: https://lore.kernel.org/r/20240322-fp4-tcpm-v1-0-c5644099d57b@fairphone.com
---
Luca Weiss (3):
arm64: dts: qcom: pm7250b: Add node for PMIC VBUS booster
arm64: dts: qcom: pm7250b: Add a TCPM description
arm64: dts: qcom: sm7225-fairphone-fp4: Enable USB role switching
arch/arm64/boot/dts/qcom/pm7250b.dtsi | 45 +++++++++++++++++
arch/arm64/boot/dts/qcom/sm6350.dtsi | 47 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 60 ++++++++++++++++++++++-
3 files changed, 151 insertions(+), 1 deletion(-)
---
base-commit: f3583a292140e0a2a2ca0ae0019108401b4c9158
change-id: 20240322-fp4-tcpm-2ad68ef55346
Best regards,
--
Luca Weiss <luca.weiss@fairphone.com>
^ permalink raw reply
* Re: [RFC PATCH v2 3/5] dt-bindings: clock: meson: document A1 SoC audio clock controller driver
From: Jerome Brunet @ 2024-03-29 12:24 UTC (permalink / raw)
To: Jan Dakinevich
Cc: Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Kevin Hilman,
Martin Blumenstingl, Philipp Zabel, linux-amlogic, linux-clk,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20240328010831.884487-4-jan.dakinevich@salutedevices.com>
On Thu 28 Mar 2024 at 04:08, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
> Add device tree bindings for A1 SoC audio clock and reset controllers.
>
> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
> ---
> .../bindings/clock/amlogic,a1-audio-clkc.yaml | 141 ++++++++++++++++++
> .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 +++++++++++++++
> .../reset/amlogic,meson-a1-audio-reset.h | 29 ++++
> 3 files changed, 292 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
> create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h
> create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
> new file mode 100644
> index 000000000000..1c9ef3292f3c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
> @@ -0,0 +1,141 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/amlogic,a1-audio-clkc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Amlogic A1 Audio Clock Control Unit and Reset Controller
> +
> +maintainers:
> + - Neil Armstrong <neil.armstrong@linaro.org>
> + - Jerome Brunet <jbrunet@baylibre.com>
> + - Jan Dakinevich <jan.dakinevich@salutedevices.com>
> +
> +properties:
> + compatible:
> + enum:
> + - amlogic,a1-audio-clkc
> + - amlogic,a1-audio2-clkc
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 6
> + maxItems: 7
> +
> + clock-names:
> + minItems: 6
> + maxItems: 7
> +
> +required:
> + - compatible
> + - '#clock-cells'
> + - reg
> + - clocks
> + - clock-names
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - amlogic,a1-audio-clkc
> + then:
> + properties:
> + clocks:
> + items:
> + - description: input core clock
> + - description: input main peripheral bus clock
> + - description: input dds_in
> + - description: input fixed pll div2
> + - description: input fixed pll div3
> + - description: input hifi_pll
> + - description: input oscillator (usually at 24MHz)
> + clocks-names:
> + items:
> + - const: core
> + - const: pclk
> + - const: dds_in
> + - const: fclk_div2
> + - const: fclk_div3
> + - const: hifi_pll
> + - const: xtal
> + required:
> + - '#reset-cells'
> + else:
> + properties:
> + clocks:
> + items:
> + - description: input main peripheral bus clock
> + - description: input dds_in
> + - description: input fixed pll div2
> + - description: input fixed pll div3
> + - description: input hifi_pll
> + - description: input oscillator (usually at 24MHz)
> + clock-names:
> + items:
> + - const: pclk
> + - const: dds_in
> + - const: fclk_div2
> + - const: fclk_div3
> + - const: hifi_pll
> + - const: xtal
All the optional slave clock inputs are missing from this dcoumentation..
They need to be documentated as well
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
> + #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
> + #include <dt-bindings/clock/amlogic,a1-audio-clkc.h>
> + audio {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clkc_audio: audio-clock-controller@fe050000 {
> + compatible = "amlogic,a1-audio-clkc";
> + reg = <0x0 0xfe050000 0x0 0xb0>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + clocks = <&clkc_audio2 AUD2_CLKID_AUDIOTOP>,
> + <&clkc_periphs CLKID_AUDIO>,
> + <&clkc_periphs CLKID_DDS_IN>,
> + <&clkc_pll CLKID_FCLK_DIV2>,
> + <&clkc_pll CLKID_FCLK_DIV3>,
> + <&clkc_pll CLKID_HIFI_PLL>,
> + <&xtal>;
> + clock-names = "core",
> + "pclk",
> + "dds_in",
> + "fclk_div2",
> + "fclk_div3",
> + "hifi_pll",
> + "xtal";
> + };
> +
> + clkc_audio2: audio-clock-controller@fe054800 {
> + compatible = "amlogic,a1-audio2-clkc";
> + reg = <0x0 0xfe054800 0x0 0x20>;
> + #clock-cells = <1>;
> + clocks = <&clkc_periphs CLKID_AUDIO>,
> + <&clkc_periphs CLKID_DDS_IN>,
> + <&clkc_pll CLKID_FCLK_DIV2>,
> + <&clkc_pll CLKID_FCLK_DIV3>,
> + <&clkc_pll CLKID_HIFI_PLL>,
> + <&xtal>;
> + clock-names = "pclk",
> + "dds_in",
> + "fclk_div2",
> + "fclk_div3",
> + "hifi_pll",
> + "xtal";
> + };
> + };
> diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
> new file mode 100644
> index 000000000000..b30df3b1ae08
> --- /dev/null
> +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
> @@ -0,0 +1,122 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
> + *
> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
> + */
> +
> +#ifndef __A1_AUDIO_CLKC_BINDINGS_H
> +#define __A1_AUDIO_CLKC_BINDINGS_H
> +
> +#define AUD_CLKID_DDR_ARB 1
> +#define AUD_CLKID_TDMIN_A 2
> +#define AUD_CLKID_TDMIN_B 3
> +#define AUD_CLKID_TDMIN_LB 4
> +#define AUD_CLKID_LOOPBACK 5
> +#define AUD_CLKID_TDMOUT_A 6
> +#define AUD_CLKID_TDMOUT_B 7
> +#define AUD_CLKID_FRDDR_A 8
> +#define AUD_CLKID_FRDDR_B 9
> +#define AUD_CLKID_TODDR_A 10
> +#define AUD_CLKID_TODDR_B 11
> +#define AUD_CLKID_SPDIFIN 12
> +#define AUD_CLKID_RESAMPLE 13
> +#define AUD_CLKID_EQDRC 14
> +#define AUD_CLKID_LOCKER 15
> +#define AUD_CLKID_MST_A_MCLK_SEL 16
> +#define AUD_CLKID_MST_A_MCLK_DIV 17
> +#define AUD_CLKID_MST_A_MCLK 18
> +#define AUD_CLKID_MST_B_MCLK_SEL 19
> +#define AUD_CLKID_MST_B_MCLK_DIV 20
> +#define AUD_CLKID_MST_B_MCLK 21
> +#define AUD_CLKID_MST_C_MCLK_SEL 22
> +#define AUD_CLKID_MST_C_MCLK_DIV 23
> +#define AUD_CLKID_MST_C_MCLK 24
> +#define AUD_CLKID_MST_D_MCLK_SEL 25
> +#define AUD_CLKID_MST_D_MCLK_DIV 26
> +#define AUD_CLKID_MST_D_MCLK 27
> +#define AUD_CLKID_SPDIFIN_CLK_SEL 28
> +#define AUD_CLKID_SPDIFIN_CLK_DIV 29
> +#define AUD_CLKID_SPDIFIN_CLK 30
> +#define AUD_CLKID_RESAMPLE_CLK_SEL 31
> +#define AUD_CLKID_RESAMPLE_CLK_DIV 32
> +#define AUD_CLKID_RESAMPLE_CLK 33
> +#define AUD_CLKID_LOCKER_IN_CLK_SEL 34
> +#define AUD_CLKID_LOCKER_IN_CLK_DIV 35
> +#define AUD_CLKID_LOCKER_IN_CLK 36
> +#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37
> +#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38
> +#define AUD_CLKID_LOCKER_OUT_CLK 39
> +#define AUD_CLKID_EQDRC_CLK_SEL 40
> +#define AUD_CLKID_EQDRC_CLK_DIV 41
> +#define AUD_CLKID_EQDRC_CLK 42
> +#define AUD_CLKID_MST_A_SCLK_PRE_EN 43
> +#define AUD_CLKID_MST_A_SCLK_DIV 44
> +#define AUD_CLKID_MST_A_SCLK_POST_EN 45
> +#define AUD_CLKID_MST_A_SCLK 46
> +#define AUD_CLKID_MST_B_SCLK_PRE_EN 47
> +#define AUD_CLKID_MST_B_SCLK_DIV 48
> +#define AUD_CLKID_MST_B_SCLK_POST_EN 49
> +#define AUD_CLKID_MST_B_SCLK 50
> +#define AUD_CLKID_MST_C_SCLK_PRE_EN 51
> +#define AUD_CLKID_MST_C_SCLK_DIV 52
> +#define AUD_CLKID_MST_C_SCLK_POST_EN 53
> +#define AUD_CLKID_MST_C_SCLK 54
> +#define AUD_CLKID_MST_D_SCLK_PRE_EN 55
> +#define AUD_CLKID_MST_D_SCLK_DIV 56
> +#define AUD_CLKID_MST_D_SCLK_POST_EN 57
> +#define AUD_CLKID_MST_D_SCLK 58
> +#define AUD_CLKID_MST_A_LRCLK_DIV 59
> +#define AUD_CLKID_MST_A_LRCLK 60
> +#define AUD_CLKID_MST_B_LRCLK_DIV 61
> +#define AUD_CLKID_MST_B_LRCLK 62
> +#define AUD_CLKID_MST_C_LRCLK_DIV 63
> +#define AUD_CLKID_MST_C_LRCLK 64
> +#define AUD_CLKID_MST_D_LRCLK_DIV 65
> +#define AUD_CLKID_MST_D_LRCLK 66
> +#define AUD_CLKID_TDMIN_A_SCLK_SEL 67
> +#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68
> +#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69
> +#define AUD_CLKID_TDMIN_A_SCLK 70
> +#define AUD_CLKID_TDMIN_A_LRCLK 71
> +#define AUD_CLKID_TDMIN_B_SCLK_SEL 72
> +#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73
> +#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74
> +#define AUD_CLKID_TDMIN_B_SCLK 75
> +#define AUD_CLKID_TDMIN_B_LRCLK 76
> +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77
> +#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78
> +#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79
> +#define AUD_CLKID_TDMIN_LB_SCLK 80
> +#define AUD_CLKID_TDMIN_LB_LRCLK 81
> +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82
> +#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83
> +#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84
> +#define AUD_CLKID_TDMOUT_A_SCLK 85
> +#define AUD_CLKID_TDMOUT_A_LRCLK 86
> +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87
> +#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88
> +#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89
> +#define AUD_CLKID_TDMOUT_B_SCLK 90
> +#define AUD_CLKID_TDMOUT_B_LRCLK 91
> +
> +#define AUD2_CLKID_DDR_ARB 1
> +#define AUD2_CLKID_PDM 2
> +#define AUD2_CLKID_TDMIN_VAD 3
> +#define AUD2_CLKID_TODDR_VAD 4
> +#define AUD2_CLKID_VAD 5
> +#define AUD2_CLKID_AUDIOTOP 6
> +#define AUD2_CLKID_VAD_MCLK_SEL 7
> +#define AUD2_CLKID_VAD_MCLK_DIV 8
> +#define AUD2_CLKID_VAD_MCLK 9
> +#define AUD2_CLKID_VAD_CLK_SEL 10
> +#define AUD2_CLKID_VAD_CLK_DIV 11
> +#define AUD2_CLKID_VAD_CLK 12
> +#define AUD2_CLKID_PDM_DCLK_SEL 13
> +#define AUD2_CLKID_PDM_DCLK_DIV 14
> +#define AUD2_CLKID_PDM_DCLK 15
> +#define AUD2_CLKID_PDM_SYSCLK_SEL 16
> +#define AUD2_CLKID_PDM_SYSCLK_DIV 17
> +#define AUD2_CLKID_PDM_SYSCLK 18
> +
> +#endif /* __A1_AUDIO_CLKC_BINDINGS_H */
> diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
> new file mode 100644
> index 000000000000..653fddba1d8f
> --- /dev/null
> +++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
> + *
> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
> + */
> +
> +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
> +#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
> +
> +#define AUD_RESET_DDRARB 0
> +#define AUD_RESET_TDMIN_A 1
> +#define AUD_RESET_TDMIN_B 2
> +#define AUD_RESET_TDMIN_LB 3
> +#define AUD_RESET_LOOPBACK 4
> +#define AUD_RESET_TDMOUT_A 5
> +#define AUD_RESET_TDMOUT_B 6
> +#define AUD_RESET_FRDDR_A 7
> +#define AUD_RESET_FRDDR_B 8
> +#define AUD_RESET_TODDR_A 9
> +#define AUD_RESET_TODDR_B 10
> +#define AUD_RESET_SPDIFIN 11
> +#define AUD_RESET_RESAMPLE 12
> +#define AUD_RESET_EQDRC 13
> +#define AUD_RESET_LOCKER 14
> +#define AUD_RESET_TOACODEC 30
> +#define AUD_RESET_CLKTREE 31
> +
> +#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */
--
Jerome
^ permalink raw reply
* Re: [PATCH 0/5] i.MX8M add DSI output endpoint
From: Shawn Guo @ 2024-03-29 12:16 UTC (permalink / raw)
To: Alexander Stein
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree,
imx, linux-arm-kernel, linux-kernel, linux
In-Reply-To: <20240301091413.3050689-1-alexander.stein@ew.tq-group.com>
On Fri, Mar 01, 2024 at 10:14:08AM +0100, Alexander Stein wrote:
> Hi,
>
> this series was initially triggered by dtbs_check warnings. Despite [1]
> rendering them invalid, this series still simplifies the DSI OF graphs on all
> i.MX8M variants by adding an empty output endpoint.
> Each board enabling DSI connection can simply reference the label.
> Patch 5 uses applies this to MBa8Mx board.
>
> Best regards,
> Alexander
>
> [1] https://lore.kernel.org/linux-samsung-soc/20231122-dtc-warnings-v2-1-bd4087325392@kernel.org/
>
> Alexander Stein (5):
> arm64: dts: imx8mm: Add empty DSI output endpoint
> arm64: dts: imx8mn: Add empty DSI output endpoint
> arm64: dts: imx8mq: Add empty DSI output endpoint
> arm64: dts: imx8mp: Add empty DSI output endpoint
> arm64: dts: mba8mx: Simplify DSI connection
Applied all, thanks!
^ permalink raw reply
* Re: [PATCH 2/2] v2 arm64: dts: qcom: Add support for Samsung Galaxy Z Fold5
From: Krzysztof Kozlowski @ 2024-03-29 12:11 UTC (permalink / raw)
To: serdeliuk, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240329-v2-dts-add-support-for-samsung-galaxy-zfold5-v1-2-9a91e635cacc@yahoo.com>
On 29/03/2024 00:08, Alexandru Marc Serdeliuc via B4 Relay wrote:
> From: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
>
> Add support for Samsung Galaxy Z Fold5 (q5q) foldable phone
Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching.
v2 is for sure wrong prefix. Other parts are also wrong, which above
command will tell you.
>
> Currently working features:
> - Framebuffer
> - UFS
> - i2c
> - Buttons
>
> Signed-off-by: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
Please go back and read my response.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 4/5] clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks
From: Krzysztof Kozlowski @ 2024-03-29 12:10 UTC (permalink / raw)
To: Varadarajan Narayanan, Stephen Boyd
Cc: andersson, conor+dt, devicetree, djakov, dmitry.baryshkov,
konrad.dybcio, krzysztof.kozlowski+dt, linux-arm-msm, linux-clk,
linux-kernel, linux-pm, mturquette, quic_anusha, robh
In-Reply-To: <ZgaeGZL7QXh75aSA@hu-varada-blr.qualcomm.com>
On 29/03/2024 11:55, Varadarajan Narayanan wrote:
>>> +
>>> +enum {
>>> + ICC_ANOC_PCIE0,
>>> + ICC_SNOC_PCIE0,
>>> + ICC_ANOC_PCIE1,
>>> + ICC_SNOC_PCIE1,
>>> + ICC_ANOC_PCIE2,
>>> + ICC_SNOC_PCIE2,
>>> + ICC_ANOC_PCIE3,
>>> + ICC_SNOC_PCIE3,
>>> + ICC_SNOC_USB,
>>> + ICC_ANOC_USB_AXI,
>>> + ICC_NSSNOC_NSSCC,
>>> + ICC_NSSNOC_SNOC_0,
>>> + ICC_NSSNOC_SNOC_1,
>>> + ICC_NSSNOC_PCNOC_1,
>>> + ICC_NSSNOC_QOSGEN_REF,
>>> + ICC_NSSNOC_TIMEOUT_REF,
>>> + ICC_NSSNOC_XO_DCD,
>>> + ICC_NSSNOC_ATB,
>>> + ICC_MEM_NOC_NSSNOC,
>>> + ICC_NSSNOC_MEMNOC,
>>> + ICC_NSSNOC_MEM_NOC_1,
>>> +};
>>
>> Are these supposed to be in a dt-binding header?
>
> Since these don't directly relate to the ids in the dt-bindings
> not sure if they will be permitted there. Will move and post a
> new version and get feedback.
You can answer this by yourself by looking at your DTS. Do you use them
as well in the DTS?
It's a pity we see here only parts of DTS, instead of full interconnect
usage.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: arm: fsl: Add Seeed studio NPi based boards
From: Shawn Guo @ 2024-03-29 12:08 UTC (permalink / raw)
To: Parthiban Nallathambi
Cc: robh+dt, krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer,
kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20240229082337.3090778-1-parthiban@linumiz.com>
On Thu, Feb 29, 2024 at 01:53:36PM +0530, Parthiban Nallathambi wrote:
> NPi i.MX6ULL eMMC/NAND is Seed Studios SoM using i.MX6ULL.
> Development baords can be either based on NAND or eMMC
> SoM.
>
> Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Applied both, thanks!
^ permalink raw reply
* Re: [PATCH v6 19/23] dt-bindings: crypto: meson: support new SoC's
From: Conor Dooley @ 2024-03-29 11:58 UTC (permalink / raw)
To: Alexey Romanov
Cc: Conor Dooley, neil.armstrong@linaro.org, clabbe@baylibre.com,
herbert@gondor.apana.org.au, davem@davemloft.net,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, vadim.fedorenko@linux.dev,
linux-crypto@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kernel
In-Reply-To: <20240329111601.po33wqdaaqpc54mo@cab-wsm-0029881>
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On Fri, Mar 29, 2024 at 11:16:06AM +0000, Alexey Romanov wrote:
> Hello,
>
> On Tue, Mar 26, 2024 at 06:04:46PM +0000, Conor Dooley wrote:
> > On Tue, Mar 26, 2024 at 06:32:15PM +0300, Alexey Romanov wrote:
> > > Now crypto module available at G12A/G12B/S4/A1/SM1/AXG.
> > >
> > > 1. Add new compatibles:
> > > - amlogic,g12a-crypto
> > > - amlogic,axg-crypto
> > > - amlogic,a1-crypto
> > > - amlogic,s4-crypto (uses a1-crypto as fallback)
> > >
> > > 2. Add power-domains in schema.
> > >
> > > Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
> > > ---
> > > .../bindings/crypto/amlogic,gxl-crypto.yaml | 15 +++++++++++++--
> > > 1 file changed, 13 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > > index d3af7b4d5f39..c92edde314aa 100644
> > > --- a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > > +++ b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > > @@ -11,8 +11,16 @@ maintainers:
> > >
> > > properties:
> > > compatible:
> > > - items:
> > > - - const: amlogic,gxl-crypto
> > > + oneOf:
> > > + - items:
> > > + - enum:
> > > + - amlogic,s4-crypto
> > > + - const: amlogic,a1-crypto
> > > + - enum:
> > > + - amlogic,gxl-crypto
> > > + - amlogic,axg-crypto
> > > + - amlogic,g12a-crypto
> > > + - amlogic,a1-crypto
> > >
> > > reg:
> > > maxItems: 1
> > > @@ -21,6 +29,9 @@ properties:
> > > items:
> > > - description: Interrupt for flow 0
> > >
> > > + power-domains:
> > > + maxItems: 1
> >
> > Is power-domains valid for the devices that existed prior to your patch?
>
> For existed devices (GXL) power domain doesn't required.
Required or not I'm not interested in, it's whether or not the hardware
has them. The GXL does for the VPU, so it might also have one for the
the crypto. If the crypto is not in a power domain on gxl, please make
power-domains only permitted for SoCs that do have power domains.
Cheers,
Conor.
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* Re: [PATCH v6 17/23] dt-bindings: crypto: meson: remove clk and second interrupt line for GXL
From: Conor Dooley @ 2024-03-29 11:55 UTC (permalink / raw)
To: Alexey Romanov
Cc: Conor Dooley, neil.armstrong@linaro.org, clabbe@baylibre.com,
herbert@gondor.apana.org.au, davem@davemloft.net,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, vadim.fedorenko@linux.dev,
linux-crypto@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kernel
In-Reply-To: <20240329111424.i2zp2coznqpnibk4@cab-wsm-0029881>
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On Fri, Mar 29, 2024 at 11:14:29AM +0000, Alexey Romanov wrote:
> Hi Conor,
>
> On Tue, Mar 26, 2024 at 06:09:37PM +0000, Conor Dooley wrote:
> > On Tue, Mar 26, 2024 at 06:32:13PM +0300, Alexey Romanov wrote:
> > > GXL crypto IP uses DMA engine, which doesn't require clk input
> > > and second interrupt line.
> > >
> > > Fixes: c4a0457eb858 ("ARM64: dts: amlogic: adds crypto hardware node")
> >
> > How does this fix a commit that only modifies a dts? The commit cited
> > here should be a dt-bindings commit.
>
> Yep, my bad. Will fix it in next series.
>
> >
> > However, your commit message says "require" but you do more than remove
> > these as required, you remove them entirely. What am I missing?
>
> Crypto HW isn't connected to clk / 2nd interrput line, so we must remove
> them from dt. I will reformulate commit message.
Yeah, please do. Be clear about the hardware not actually having these
things. And hopefully Corentin can chime in as to why he thought it did.
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* Re: 回复: [PATCH v2 1/2] ASoC: dt-bindings: Add bindings for Cadence I2S-MC controller
From: Krzysztof Kozlowski @ 2024-03-29 11:42 UTC (permalink / raw)
To: Xingyu Wu, Liam Girdwood, Mark Brown, Claudiu Beznea,
Jaroslav Kysela, Takashi Iwai, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
alsa-devel@alsa-project.org, linux-sound@vger.kernel.org
In-Reply-To: <NTZPR01MB09563633F5C3B5FBC95D61289F3AA@NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn>
On 29/03/2024 04:56, Xingyu Wu wrote:
>>> I want to keep the original IP compatible which can distinguish from the JH8100
>> SoC.
>>> Can I write it like this:
>>> compatible:
>>> enum:
>>> - starfive,jh8100-i2s
>>> const: cdns,i2s-mc
>>>
>>> and I write this in the DTS:
>>> compatible = "starfive,jh8100-i2s", "cdns,i2s-mc";
>>
>> Can you provide any rationale for this? I asked "unless you have other
>> arguments", so where are the arguments?
>>
>> Nothing was explained in patch changelog. Nothing was provided in this email
>> thread.
>
> I don't know if I understood what mark said[1]. Is it to keep the original IP and
> add other compatible?
>
> [1] https://lore.kernel.org/all/27155281-573c-493d-96fe-1f28ebb0ce5e@sirena.org.uk/
>
I stated and I keep my statement that such block is usually not usable
on its own and always needs some sort of quirks or SoC-specific
implementation. At least this is what I saw in other similar cases, but
not exactly I2S.
Therefore I think fallback is not usable here, thus please use only
starfive compatible. Drop the fallback. It could be added in the future
if I am proven wrong. If you think that fallback is usable alone, please
bring some real life case.
> Or should I only keep the compatible 'starfive,jh8110-i2s' and change the
> bindings name to same to this compatible?
Filename could be cdns,i2s-mc.yaml, assuming that's the name of original
IP block.
...
>>>>
>>>
>>> But this I2S can only use either DMA or interrupts.
>>
>> Just like many other components. DTS should reflect hardware. Hardware has
>> interrupts and DMA, right?
>
> Yes. The hardware can use interrupts and provide the handshake interface of
> DMA to DMA controller. In software, we can choose only one between them.
> Do I keep them both in the bindings and provide the selection in the driver?
Yes.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 0/4] Add USB Support on Qualcomm's QDU/QRU1000 Platform
From: Komal Bajaj @ 2024-03-29 11:28 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Wesley Cheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb
In-Reply-To: <2024032637-sessions-outcast-888a@gregkh>
On 3/26/2024 2:00 PM, Greg Kroah-Hartman wrote:
> On Tue, Mar 19, 2024 at 02:37:24PM +0530, Komal Bajaj wrote:
>> This series adds support of USB3 PHY support for Qualcomm's QDU/QRU1000 Platform.
>>
>> ---------
>> Changes in v2:
>> * Dropped extra lines
>> * Sorted the tables alphabetically
>> * Link to v1: https://lore.kernel.org/linux-arm-msm/20240311120215.16845-1-quic_kbajaj@quicinc.com/
>>
>> Komal Bajaj (4):
>> dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000
>> dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY
>> dt-bindings: usb: dwc3: Add QDU1000 compatible
>> phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000
>>
>> .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 2 +
>> .../bindings/phy/qcom,usb-snps-femto-v2.yaml | 1 +
>> .../devicetree/bindings/usb/qcom,dwc3.yaml | 3 ++
>> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 49 +++++++++++++++++++
>> 4 files changed, 55 insertions(+)
>>
>> --
>> 2.42.0
>>
>>
>
> The subject line here does not say v2, so I'm confused as to which one
> is which :(
>
> Please fix up and send a v3.
Apologies, forgot to mark patches as v2.
Will soon send v3 series with proper marking.
Thanks
Komal
>
> thanks,
>
> greg k-h
^ permalink raw reply
* [PATCH v7 2/2] dmaengine: Loongson1: Add Loongson-1 APB DMA driver
From: Keguang Zhang via B4 Relay @ 2024-03-29 11:26 UTC (permalink / raw)
To: Keguang Zhang, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Huacai Chen
Cc: linux-mips, dmaengine, devicetree, linux-kernel
In-Reply-To: <20240329-loongson1-dma-v7-0-37db58608de5@gmail.com>
From: Keguang Zhang <keguang.zhang@gmail.com>
This patch adds APB DMA driver for Loongson-1 SoCs.
Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
---
Changes in v7:
- Change the comptible to 'loongson,ls1*-apbdma'
- Update Kconfig and Makefile accordingly
- Rename the file to loongson1-apb-dma.c to keep the consistency
Changes in v6:
- Implement .device_prep_dma_cyclic for Loongson1 audio driver,
- as well as .device_pause and .device_resume.
- Set the limitation LS1X_DMA_MAX_DESC and put all descriptors
- into one page to save memory
- Move dma_pool_zalloc() into ls1x_dma_alloc_desc()
- Drop dma_slave_config structure
- Use .remove_new instead of .remove
- Use KBUILD_MODNAME for the driver name
- Improve the debug information
Changes in v5:
- Add DT support
- Use DT data instead of platform data
- Use chan_id of struct dma_chan instead of own id
- Use of_dma_xlate_by_chan_id() instead of ls1x_dma_filter()
- Update the author information to my official name
Changes in v4:
- Use dma_slave_map to find the proper channel.
- Explicitly call devm_request_irq() and tasklet_kill().
- Fix namespace issue.
- Some minor fixes and cleanups.
Changes in v3:
- Rename ls1x_dma_filter_fn to ls1x_dma_filter.
Changes in v2:
- Change the config from 'DMA_LOONGSON1' to 'LOONGSON1_DMA',
- and rearrange it in alphabetical order in Kconfig and Makefile.
- Fix comment style.
---
drivers/dma/Kconfig | 9 +
drivers/dma/Makefile | 1 +
drivers/dma/loongson1-apb-dma.c | 665 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 675 insertions(+)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 002a5ec80620..f7b06c4cdf3f 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -369,6 +369,15 @@ config K3_DMA
Support the DMA engine for Hisilicon K3 platform
devices.
+config LOONGSON1_APB_DMA
+ tristate "Loongson1 APB DMA support"
+ depends on MACH_LOONGSON32 || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ This selects support for the APB DMA controller in Loongson1 SoCs,
+ which is required by Loongson1 NAND and audio support.
+
config LPC18XX_DMAMUX
bool "NXP LPC18xx/43xx DMA MUX for PL080"
depends on ARCH_LPC18XX || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index dfd40d14e408..b26f6677978a 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_INTEL_IDMA64) += idma64.o
obj-$(CONFIG_INTEL_IOATDMA) += ioat/
obj-y += idxd/
obj-$(CONFIG_K3_DMA) += k3dma.o
+obj-$(CONFIG_LOONGSON1_APB_DMA) += loongson1-apb-dma.o
obj-$(CONFIG_LPC18XX_DMAMUX) += lpc18xx-dmamux.o
obj-$(CONFIG_LS2X_APB_DMA) += ls2x-apb-dma.o
obj-$(CONFIG_MILBEAUT_HDMAC) += milbeaut-hdmac.o
diff --git a/drivers/dma/loongson1-apb-dma.c b/drivers/dma/loongson1-apb-dma.c
new file mode 100644
index 000000000000..d474a2601e6e
--- /dev/null
+++ b/drivers/dma/loongson1-apb-dma.c
@@ -0,0 +1,665 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for Loongson-1 APB DMA Controller
+ *
+ * Copyright (C) 2015-2024 Keguang Zhang <keguang.zhang@gmail.com>
+ */
+
+#include <linux/dmapool.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "dmaengine.h"
+#include "virt-dma.h"
+
+/* Loongson-1 DMA Control Register */
+#define DMA_CTRL 0x0
+
+/* DMA Control Register Bits */
+#define DMA_STOP BIT(4)
+#define DMA_START BIT(3)
+#define DMA_ASK_VALID BIT(2)
+
+#define DMA_ADDR_MASK GENMASK(31, 6)
+
+/* DMA Next Field Bits */
+#define DMA_NEXT_VALID BIT(0)
+
+/* DMA Command Field Bits */
+#define DMA_RAM2DEV BIT(12)
+#define DMA_INT BIT(1)
+#define DMA_INT_MASK BIT(0)
+
+#define LS1X_DMA_MAX_CHANNELS 3
+
+/* Size of allocations for hardware descriptors */
+#define LS1X_DMA_DESCS_SIZE PAGE_SIZE
+#define LS1X_DMA_MAX_DESC \
+ (LS1X_DMA_DESCS_SIZE / sizeof(struct ls1x_dma_hwdesc))
+
+struct ls1x_dma_hwdesc {
+ u32 next; /* next descriptor address */
+ u32 saddr; /* memory DMA address */
+ u32 daddr; /* device DMA address */
+ u32 length;
+ u32 stride;
+ u32 cycles;
+ u32 cmd;
+ u32 stats;
+};
+
+struct ls1x_dma_desc {
+ struct virt_dma_desc vdesc;
+ enum dma_transfer_direction dir;
+ enum dma_transaction_type type;
+ unsigned int bus_width;
+
+ unsigned int nr_descs; /* number of descriptors */
+
+ struct ls1x_dma_hwdesc *hwdesc;
+ dma_addr_t hwdesc_phys;
+};
+
+struct ls1x_dma_chan {
+ struct virt_dma_chan vchan;
+ struct dma_pool *desc_pool;
+ phys_addr_t src_addr;
+ phys_addr_t dst_addr;
+ enum dma_slave_buswidth src_addr_width;
+ enum dma_slave_buswidth dst_addr_width;
+
+ void __iomem *reg_base;
+ int irq;
+
+ struct ls1x_dma_desc *desc;
+
+ struct ls1x_dma_hwdesc *curr_hwdesc;
+ dma_addr_t curr_hwdesc_phys;
+};
+
+struct ls1x_dma {
+ struct dma_device ddev;
+ void __iomem *reg_base;
+
+ unsigned int nr_chans;
+ struct ls1x_dma_chan chan[];
+};
+
+#define to_ls1x_dma_chan(dchan) \
+ container_of(dchan, struct ls1x_dma_chan, vchan.chan)
+
+#define to_ls1x_dma_desc(vd) \
+ container_of(vd, struct ls1x_dma_desc, vdesc)
+
+/* macros for registers read/write */
+#define chan_readl(chan, off) \
+ readl((chan)->reg_base + (off))
+
+#define chan_writel(chan, off, val) \
+ writel((val), (chan)->reg_base + (off))
+
+static inline struct device *chan2dev(struct dma_chan *chan)
+{
+ return &chan->dev->device;
+}
+
+static inline int ls1x_dma_query(struct ls1x_dma_chan *chan,
+ dma_addr_t *hwdesc_phys)
+{
+ struct dma_chan *dchan = &chan->vchan.chan;
+ int val, ret;
+
+ val = *hwdesc_phys & DMA_ADDR_MASK;
+ val |= DMA_ASK_VALID;
+ val |= dchan->chan_id;
+ chan_writel(chan, DMA_CTRL, val);
+ ret = readl_poll_timeout_atomic(chan->reg_base + DMA_CTRL, val,
+ !(val & DMA_ASK_VALID), 0, 3000);
+ if (ret)
+ dev_err(chan2dev(dchan), "failed to query DMA\n");
+
+ return ret;
+}
+
+static inline int ls1x_dma_start(struct ls1x_dma_chan *chan,
+ dma_addr_t *hwdesc_phys)
+{
+ struct dma_chan *dchan = &chan->vchan.chan;
+ int val, ret;
+
+ dev_dbg(chan2dev(dchan), "cookie=%d, starting hwdesc=%x\n",
+ dchan->cookie, *hwdesc_phys);
+
+ val = *hwdesc_phys & DMA_ADDR_MASK;
+ val |= DMA_START;
+ val |= dchan->chan_id;
+ chan_writel(chan, DMA_CTRL, val);
+ ret = readl_poll_timeout(chan->reg_base + DMA_CTRL, val,
+ !(val & DMA_START), 0, 3000);
+ if (ret)
+ dev_err(chan2dev(dchan), "failed to start DMA\n");
+
+ return ret;
+}
+
+static inline void ls1x_dma_stop(struct ls1x_dma_chan *chan)
+{
+ chan_writel(chan, DMA_CTRL, chan_readl(chan, DMA_CTRL) | DMA_STOP);
+}
+
+static void ls1x_dma_free_chan_resources(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+
+ dma_free_coherent(chan2dev(dchan), sizeof(struct ls1x_dma_hwdesc),
+ chan->curr_hwdesc, chan->curr_hwdesc_phys);
+ vchan_free_chan_resources(&chan->vchan);
+ dma_pool_destroy(chan->desc_pool);
+ chan->desc_pool = NULL;
+}
+
+static int ls1x_dma_alloc_chan_resources(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+
+ chan->desc_pool = dma_pool_create(dma_chan_name(dchan),
+ chan2dev(dchan),
+ sizeof(struct ls1x_dma_hwdesc),
+ __alignof__(struct ls1x_dma_hwdesc),
+ 0);
+ if (!chan->desc_pool)
+ return -ENOMEM;
+
+ /* allocate memory for querying current HW descriptor */
+ dma_set_coherent_mask(chan2dev(dchan), DMA_BIT_MASK(32));
+ chan->curr_hwdesc = dma_alloc_coherent(chan2dev(dchan),
+ sizeof(struct ls1x_dma_hwdesc),
+ &chan->curr_hwdesc_phys,
+ GFP_KERNEL);
+ if (!chan->curr_hwdesc)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void ls1x_dma_free_desc(struct virt_dma_desc *vdesc)
+{
+ struct ls1x_dma_desc *desc = to_ls1x_dma_desc(vdesc);
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(vdesc->tx.chan);
+
+ dma_pool_free(chan->desc_pool, desc->hwdesc, desc->hwdesc_phys);
+ chan->desc = NULL;
+ kfree(desc);
+}
+
+static struct ls1x_dma_desc *
+ls1x_dma_alloc_desc(struct dma_chan *dchan, int sg_len,
+ enum dma_transfer_direction direction,
+ enum dma_transaction_type type)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ struct ls1x_dma_desc *desc;
+
+ if (sg_len > LS1X_DMA_MAX_DESC) {
+ dev_err(chan2dev(dchan), "sg_len %u exceeds limit %lu",
+ sg_len, LS1X_DMA_MAX_DESC);
+ return NULL;
+ }
+
+ desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
+ if (!desc)
+ return NULL;
+
+ /* allocate HW descriptors */
+ desc->hwdesc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT,
+ &desc->hwdesc_phys);
+ if (!desc->hwdesc) {
+ dev_err(chan2dev(dchan), "failed to alloc HW descriptors\n");
+ ls1x_dma_free_desc(&desc->vdesc);
+ return NULL;
+ }
+
+ desc->dir = direction;
+ desc->type = type;
+ desc->nr_descs = sg_len;
+
+ return desc;
+}
+
+static int ls1x_dma_setup_hwdescs(struct dma_chan *dchan,
+ struct ls1x_dma_desc *desc,
+ struct scatterlist *sgl, unsigned int sg_len)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ dma_addr_t next_hwdesc_phys = desc->hwdesc_phys;
+
+ struct scatterlist *sg;
+ unsigned int dev_addr, cmd, i;
+
+ switch (desc->dir) {
+ case DMA_MEM_TO_DEV:
+ dev_addr = chan->dst_addr;
+ desc->bus_width = chan->dst_addr_width;
+ cmd = DMA_RAM2DEV | DMA_INT;
+ break;
+ case DMA_DEV_TO_MEM:
+ dev_addr = chan->src_addr;
+ desc->bus_width = chan->src_addr_width;
+ cmd = DMA_INT;
+ break;
+ default:
+ dev_err(chan2dev(dchan), "unsupported DMA direction: %s\n",
+ dmaengine_get_direction_text(desc->dir));
+ return -EINVAL;
+ }
+
+ /* setup HW descriptors */
+ for_each_sg(sgl, sg, sg_len, i) {
+ dma_addr_t buf_addr = sg_dma_address(sg);
+ size_t buf_len = sg_dma_len(sg);
+ struct ls1x_dma_hwdesc *hwdesc = &desc->hwdesc[i];
+
+ if (!is_dma_copy_aligned(dchan->device, buf_addr, 0, buf_len)) {
+ dev_err(chan2dev(dchan), "buffer is not aligned!\n");
+ return -EINVAL;
+ }
+
+ hwdesc->saddr = buf_addr;
+ hwdesc->daddr = dev_addr;
+ hwdesc->length = buf_len / desc->bus_width;
+ hwdesc->stride = 0;
+ hwdesc->cycles = 1;
+ hwdesc->cmd = cmd;
+
+ if (i) {
+ next_hwdesc_phys += sizeof(*hwdesc);
+ desc->hwdesc[i - 1].next = next_hwdesc_phys
+ | DMA_NEXT_VALID;
+ }
+ }
+
+ if (desc->type == DMA_CYCLIC)
+ desc->hwdesc[i - 1].next = desc->hwdesc_phys | DMA_NEXT_VALID;
+
+ for_each_sg(sgl, sg, sg_len, i) {
+ struct ls1x_dma_hwdesc *hwdesc = &desc->hwdesc[i];
+
+ print_hex_dump_debug("HW DESC: ", DUMP_PREFIX_OFFSET, 16, 4,
+ hwdesc, sizeof(*hwdesc), false);
+ }
+
+ return 0;
+}
+
+static struct dma_async_tx_descriptor *
+ls1x_dma_prep_slave_sg(struct dma_chan *dchan,
+ struct scatterlist *sgl, unsigned int sg_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ struct ls1x_dma_desc *desc;
+
+ dev_dbg(chan2dev(dchan), "sg_len=%u flags=0x%lx dir=%s\n",
+ sg_len, flags, dmaengine_get_direction_text(direction));
+
+ desc = ls1x_dma_alloc_desc(dchan, sg_len, direction, DMA_SLAVE);
+ if (!desc)
+ return NULL;
+
+ if (ls1x_dma_setup_hwdescs(dchan, desc, sgl, sg_len)) {
+ ls1x_dma_free_desc(&desc->vdesc);
+ return NULL;
+ }
+
+ return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
+}
+
+static struct dma_async_tx_descriptor *
+ls1x_dma_prep_dma_cyclic(struct dma_chan *dchan,
+ dma_addr_t buf_addr, size_t buf_len, size_t period_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ struct ls1x_dma_desc *desc;
+ struct scatterlist *sgl;
+ unsigned int sg_len;
+ unsigned int i;
+
+ dev_dbg(chan2dev(dchan),
+ "buf_len=%d period_len=%zu flags=0x%lx dir=%s\n", buf_len,
+ period_len, flags, dmaengine_get_direction_text(direction));
+
+ sg_len = buf_len / period_len;
+ desc = ls1x_dma_alloc_desc(dchan, sg_len, direction, DMA_CYCLIC);
+ if (!desc)
+ return NULL;
+
+ /* allocate the scatterlist */
+ sgl = kmalloc_array(sg_len, sizeof(*sgl), GFP_NOWAIT);
+ if (!sgl)
+ return NULL;
+
+ sg_init_table(sgl, sg_len);
+ for (i = 0; i < sg_len; ++i) {
+ sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(buf_addr)),
+ period_len, offset_in_page(buf_addr));
+ sg_dma_address(&sgl[i]) = buf_addr;
+ sg_dma_len(&sgl[i]) = period_len;
+ buf_addr += period_len;
+ }
+
+ if (ls1x_dma_setup_hwdescs(dchan, desc, sgl, sg_len)) {
+ ls1x_dma_free_desc(&desc->vdesc);
+ return NULL;
+ }
+
+ kfree(sgl);
+
+ return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
+}
+
+static int ls1x_dma_slave_config(struct dma_chan *dchan,
+ struct dma_slave_config *config)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+
+ chan->src_addr = config->src_addr;
+ chan->src_addr_width = config->src_addr_width;
+ chan->dst_addr = config->dst_addr;
+ chan->dst_addr_width = config->dst_addr_width;
+
+ return 0;
+}
+
+static int ls1x_dma_pause(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ ret = ls1x_dma_query(chan, &chan->curr_hwdesc_phys);
+ if (!ret)
+ ls1x_dma_stop(chan);
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+ return ret;
+}
+
+static int ls1x_dma_resume(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ ret = ls1x_dma_start(chan, &chan->curr_hwdesc_phys);
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+ return ret;
+}
+
+static int ls1x_dma_terminate_all(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ unsigned long flags;
+ LIST_HEAD(head);
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ ls1x_dma_stop(chan);
+ vchan_get_all_descriptors(&chan->vchan, &head);
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+ vchan_dma_desc_free_list(&chan->vchan, &head);
+
+ return 0;
+}
+
+static enum dma_status ls1x_dma_tx_status(struct dma_chan *dchan,
+ dma_cookie_t cookie,
+ struct dma_tx_state *state)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ struct virt_dma_desc *vdesc;
+ enum dma_status status;
+ size_t bytes = 0;
+ unsigned long flags;
+
+ status = dma_cookie_status(dchan, cookie, state);
+ if (status == DMA_COMPLETE)
+ return status;
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ vdesc = vchan_find_desc(&chan->vchan, cookie);
+ if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) {
+ struct ls1x_dma_desc *desc = chan->desc;
+ int i;
+
+ if (ls1x_dma_query(chan, &chan->curr_hwdesc_phys))
+ return status;
+
+ /* locate the current HW descriptor */
+ for (i = 0; i < desc->nr_descs; i++)
+ if (desc->hwdesc[i].next == chan->curr_hwdesc->next)
+ break;
+
+ /* count the residues */
+ for (; i < desc->nr_descs; i++)
+ bytes += desc->hwdesc[i].length * desc->bus_width;
+
+ dma_set_residue(state, bytes);
+ }
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+ return status;
+}
+
+static void ls1x_dma_issue_pending(struct dma_chan *dchan)
+{
+ struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
+ struct virt_dma_desc *vdesc;
+ unsigned long flags;
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
+ vdesc = vchan_next_desc(&chan->vchan);
+ if (!vdesc) {
+ chan->desc = NULL;
+ return;
+ }
+ chan->desc = to_ls1x_dma_desc(vdesc);
+ ls1x_dma_start(chan, &chan->desc->hwdesc_phys);
+ }
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+}
+
+static irqreturn_t ls1x_dma_irq_handler(int irq, void *data)
+{
+ struct ls1x_dma_chan *chan = data;
+ struct ls1x_dma_desc *desc = chan->desc;
+ struct dma_chan *dchan = &chan->vchan.chan;
+
+ if (!desc) {
+ dev_warn(chan2dev(dchan),
+ "IRQ %d with no active descriptor on channel %d\n",
+ irq, dchan->chan_id);
+ return IRQ_NONE;
+ }
+
+ dev_dbg(chan2dev(dchan), "DMA IRQ %d on channel %d\n", irq,
+ dchan->chan_id);
+
+ spin_lock(&chan->vchan.lock);
+
+ if (desc->type == DMA_CYCLIC) {
+ vchan_cyclic_callback(&desc->vdesc);
+ } else {
+ list_del(&desc->vdesc.node);
+ vchan_cookie_complete(&desc->vdesc);
+ chan->desc = NULL;
+ }
+
+ spin_unlock(&chan->vchan.lock);
+ return IRQ_HANDLED;
+}
+
+static int ls1x_dma_chan_probe(struct platform_device *pdev,
+ struct ls1x_dma *dma, int chan_id)
+{
+ struct device *dev = &pdev->dev;
+ struct ls1x_dma_chan *chan = &dma->chan[chan_id];
+ char pdev_irqname[4];
+ char *irqname;
+ int ret;
+
+ sprintf(pdev_irqname, "ch%u", chan_id);
+ chan->irq = platform_get_irq_byname(pdev, pdev_irqname);
+ if (chan->irq < 0)
+ return -ENODEV;
+
+ irqname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
+ dev_name(dev), pdev_irqname);
+ if (!irqname)
+ return -ENOMEM;
+
+ ret = devm_request_irq(dev, chan->irq, ls1x_dma_irq_handler,
+ IRQF_SHARED, irqname, chan);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to request IRQ %u!\n", chan->irq);
+
+ chan->reg_base = dma->reg_base;
+ chan->vchan.desc_free = ls1x_dma_free_desc;
+ vchan_init(&chan->vchan, &dma->ddev);
+ dev_info(dev, "%s (irq %d) initialized\n", pdev_irqname, chan->irq);
+
+ return 0;
+}
+
+static void ls1x_dma_chan_remove(struct ls1x_dma *dma, int chan_id)
+{
+ struct device *dev = dma->ddev.dev;
+ struct ls1x_dma_chan *chan = &dma->chan[chan_id];
+
+ devm_free_irq(dev, chan->irq, chan);
+ list_del(&chan->vchan.chan.device_node);
+ tasklet_kill(&chan->vchan.task);
+}
+
+static int ls1x_dma_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct dma_device *ddev;
+ struct ls1x_dma *dma;
+ int nr_chans, ret, i;
+
+ nr_chans = platform_irq_count(pdev);
+ if (nr_chans <= 0)
+ return nr_chans;
+ if (nr_chans > LS1X_DMA_MAX_CHANNELS)
+ return dev_err_probe(dev, -EINVAL,
+ "nr_chans=%d exceeds the maximum\n",
+ nr_chans);
+
+ dma = devm_kzalloc(dev, struct_size(dma, chan, nr_chans), GFP_KERNEL);
+ if (!dma)
+ return -ENOMEM;
+
+ /* initialize DMA device */
+ dma->reg_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(dma->reg_base))
+ return PTR_ERR(dma->reg_base);
+
+ ddev = &dma->ddev;
+ ddev->dev = dev;
+ ddev->copy_align = DMAENGINE_ALIGN_4_BYTES;
+ ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+ ddev->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+ ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+ ddev->max_sg_burst = LS1X_DMA_MAX_DESC;
+ ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+ ddev->device_alloc_chan_resources = ls1x_dma_alloc_chan_resources;
+ ddev->device_free_chan_resources = ls1x_dma_free_chan_resources;
+ ddev->device_prep_slave_sg = ls1x_dma_prep_slave_sg;
+ ddev->device_prep_dma_cyclic = ls1x_dma_prep_dma_cyclic;
+ ddev->device_config = ls1x_dma_slave_config;
+ ddev->device_pause = ls1x_dma_pause;
+ ddev->device_resume = ls1x_dma_resume;
+ ddev->device_terminate_all = ls1x_dma_terminate_all;
+ ddev->device_tx_status = ls1x_dma_tx_status;
+ ddev->device_issue_pending = ls1x_dma_issue_pending;
+
+ dma_cap_set(DMA_SLAVE, ddev->cap_mask);
+ INIT_LIST_HEAD(&ddev->channels);
+
+ /* initialize DMA channels */
+ for (i = 0; i < nr_chans; i++) {
+ ret = ls1x_dma_chan_probe(pdev, dma, i);
+ if (ret)
+ return ret;
+ }
+ dma->nr_chans = nr_chans;
+
+ ret = dmaenginem_async_device_register(ddev);
+ if (ret) {
+ dev_err(dev, "failed to register DMA device! %d\n", ret);
+ return ret;
+ }
+
+ ret =
+ of_dma_controller_register(dev->of_node, of_dma_xlate_by_chan_id,
+ ddev);
+ if (ret) {
+ dev_err(dev, "failed to register DMA controller! %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, dma);
+ dev_info(dev, "Loongson1 DMA driver registered\n");
+
+ return 0;
+}
+
+static void ls1x_dma_remove(struct platform_device *pdev)
+{
+ struct ls1x_dma *dma = platform_get_drvdata(pdev);
+ int i;
+
+ of_dma_controller_free(pdev->dev.of_node);
+
+ for (i = 0; i < dma->nr_chans; i++)
+ ls1x_dma_chan_remove(dma, i);
+}
+
+static const struct of_device_id ls1x_dma_match[] = {
+ { .compatible = "loongson,ls1b-apbdma" },
+ { .compatible = "loongson,ls1c-apbdma" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ls1x_dma_match);
+
+static struct platform_driver ls1x_dma_driver = {
+ .probe = ls1x_dma_probe,
+ .remove_new = ls1x_dma_remove,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = ls1x_dma_match,
+ },
+};
+
+module_platform_driver(ls1x_dma_driver);
+
+MODULE_AUTHOR("Keguang Zhang <keguang.zhang@gmail.com>");
+MODULE_DESCRIPTION("Loongson-1 APB DMA Controller driver");
+MODULE_LICENSE("GPL");
--
2.40.1
^ permalink raw reply related
* [PATCH v7 0/2] Add support for Loongson1 APB DMA
From: Keguang Zhang via B4 Relay @ 2024-03-29 11:26 UTC (permalink / raw)
To: Keguang Zhang, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Huacai Chen
Cc: linux-mips, dmaengine, devicetree, linux-kernel
Add the driver and dt-binding document for Loongson1 APB DMA.
Changes in v7:
- Change the comptible to 'loongson,ls1*-apbdma' (suggested by Huacai Chen)
- Update the title and description part accordingly
- Rename the file to loongson,ls1b-apbdma.yaml
- Add a compatible string for LS1A
- Delete minItems of 'interrupts'
- Change patterns of 'interrupt-names' to const
- Rename the file to loongson1-apb-dma.c to keep the consistency
- Update Kconfig and Makefile accordingly
- Link to v6: https://lore.kernel.org/r/20240316-loongson1-dma-v6-0-90de2c3cc928@gmail.com
Changes in v6:
- Change the compatible to the fallback
- Implement .device_prep_dma_cyclic for Loongson1 sound driver,
- as well as .device_pause and .device_resume.
- Set the limitation LS1X_DMA_MAX_DESC and put all descriptors
- into one page to save memory
- Move dma_pool_zalloc() into ls1x_dma_alloc_desc()
- Drop dma_slave_config structure
- Use .remove_new instead of .remove
- Use KBUILD_MODNAME for the driver name
- Improve the debug information
- Some minor fixes
-
Changes in v5:
- Add the dt-binding document
- Add DT support
- Use DT information instead of platform data
- Use chan_id of struct dma_chan instead of own id
- Use of_dma_xlate_by_chan_id() instead of ls1x_dma_filter()
- Update the author information to my official name
-
Changes in v4:
- Use dma_slave_map to find the proper channel.
- Explicitly call devm_request_irq() and tasklet_kill().
- Fix namespace issue.
- Some minor fixes and cleanups.
-
Changes in v3:
- Rename ls1x_dma_filter_fn to ls1x_dma_filter.
-
Changes in v2:
- Change the config from 'DMA_LOONGSON1' to 'LOONGSON1_DMA',
- and rearrange it in alphabetical order in Kconfig and Makefile.
- Fix comment style.
---
Keguang Zhang (2):
dt-bindings: dma: Add Loongson-1 APB DMA
dmaengine: Loongson1: Add Loongson-1 APB DMA driver
.../bindings/dma/loongson,ls1b-apbdma.yaml | 65 ++
drivers/dma/Kconfig | 9 +
drivers/dma/Makefile | 1 +
drivers/dma/loongson1-apb-dma.c | 665 +++++++++++++++++++++
4 files changed, 740 insertions(+)
---
base-commit: a6bd6c9333397f5a0e2667d4d82fef8c970108f2
change-id: 20231120-loongson1-dma-163afe5708b9
Best regards,
--
Keguang Zhang <keguang.zhang@gmail.com>
^ permalink raw reply
* [PATCH v7 1/2] dt-bindings: dma: Add Loongson-1 APB DMA
From: Keguang Zhang via B4 Relay @ 2024-03-29 11:26 UTC (permalink / raw)
To: Keguang Zhang, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Huacai Chen
Cc: linux-mips, dmaengine, devicetree, linux-kernel
In-Reply-To: <20240329-loongson1-dma-v7-0-37db58608de5@gmail.com>
From: Keguang Zhang <keguang.zhang@gmail.com>
Add devicetree binding document for Loongson-1 APB DMA.
Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
---
Changes in v7:
- Change the comptible to 'loongson,ls1*-apbdma' (suggested by Huacai Chen)
- Update the title and description part accordingly
- Rename the file to loongson,ls1b-apbdma.yaml
- Add a compatible string for LS1A
- Delete minItems of 'interrupts'
- Change patterns of 'interrupt-names' to const
Changes in v6:
- Change the compatible to the fallback
- Some minor fixes
Changes in v5:
- A newly added patch
---
.../bindings/dma/loongson,ls1b-apbdma.yaml | 65 ++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml b/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml
new file mode 100644
index 000000000000..449da9fc2de1
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/loongson,ls1b-apbdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson-1 APB DMA Controller
+
+maintainers:
+ - Keguang Zhang <keguang.zhang@gmail.com>
+
+description:
+ Loongson-1 APB DMA controller provides 3 independent channels for
+ peripherals such as NAND, audio playback and capture.
+
+properties:
+ compatible:
+ oneOf:
+ - const: loongson,ls1b-apbdma
+ - items:
+ - enum:
+ - loongson,ls1a-apbdma
+ - loongson,ls1c-apbdma
+ - const: loongson,ls1b-apbdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: Each channel has a dedicated interrupt line.
+ maxItems: 3
+
+ interrupt-names:
+ items:
+ - const: ch0
+ - const: ch1
+ - const: ch2
+
+ '#dma-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - '#dma-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ dma-controller@1fd01160 {
+ compatible = "loongson,ls1b-apbdma";
+ reg = <0x1fd01160 0x4>;
+
+ interrupt-parent = <&intc0>;
+ interrupts = <13 IRQ_TYPE_EDGE_RISING>,
+ <14 IRQ_TYPE_EDGE_RISING>,
+ <15 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ch0", "ch1", "ch2";
+
+ #dma-cells = <1>;
+ };
--
2.40.1
^ permalink raw reply related
* Re: [PATCH 2/2] phy: qcom-qmp-ufs: Add SM8475 support
From: Konrad Dybcio @ 2024-03-29 11:23 UTC (permalink / raw)
To: Vinod Koul
Cc: Danila Tikhonov, andersson, kishon, robh, krzysztof.kozlowski+dt,
conor+dt, linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <ZgUf_I2KBMhenNEv@matsya>
On 28.03.2024 8:45 AM, Vinod Koul wrote:
> On 27-03-24, 22:38, Konrad Dybcio wrote:
>> On 27.03.2024 7:06 PM, Danila Tikhonov wrote:
>>> Add the tables and constants for init sequences for UFS QMP phy found in
>>> SM8475 SoC.
>>>
>>> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
>>> ---
>>
>> Worth mentioning that SM8475 is a respin of SM8450 on a different
>> process node, which probably forced some electrical changes.
>
> should the tables be resued from 8450 instead of 8550 as in this patch?
No, and the reason why is my message above
Konrad
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: qcom: sm6350: Add DisplayPort controller
From: Konrad Dybcio @ 2024-03-29 11:20 UTC (permalink / raw)
To: Luca Weiss, Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh,
Krishna Manikandan, Bjorn Andersson
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel
In-Reply-To: <20240329-sm6350-dp-v2-3-e46dceb32ef5@fairphone.com>
On 29.03.2024 8:45 AM, Luca Weiss wrote:
> Add the node for the DisplayPort controller found on the SM6350 SoC.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply
* Re: [PATCH v6 19/23] dt-bindings: crypto: meson: support new SoC's
From: Alexey Romanov @ 2024-03-29 11:16 UTC (permalink / raw)
To: Conor Dooley
Cc: neil.armstrong@linaro.org, clabbe@baylibre.com,
herbert@gondor.apana.org.au, davem@davemloft.net,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, vadim.fedorenko@linux.dev,
linux-crypto@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kernel
In-Reply-To: <20240326-boneless-patrol-b1156a4be70b@spud>
Hello,
On Tue, Mar 26, 2024 at 06:04:46PM +0000, Conor Dooley wrote:
> On Tue, Mar 26, 2024 at 06:32:15PM +0300, Alexey Romanov wrote:
> > Now crypto module available at G12A/G12B/S4/A1/SM1/AXG.
> >
> > 1. Add new compatibles:
> > - amlogic,g12a-crypto
> > - amlogic,axg-crypto
> > - amlogic,a1-crypto
> > - amlogic,s4-crypto (uses a1-crypto as fallback)
> >
> > 2. Add power-domains in schema.
> >
> > Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
> > ---
> > .../bindings/crypto/amlogic,gxl-crypto.yaml | 15 +++++++++++++--
> > 1 file changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > index d3af7b4d5f39..c92edde314aa 100644
> > --- a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > +++ b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > @@ -11,8 +11,16 @@ maintainers:
> >
> > properties:
> > compatible:
> > - items:
> > - - const: amlogic,gxl-crypto
> > + oneOf:
> > + - items:
> > + - enum:
> > + - amlogic,s4-crypto
> > + - const: amlogic,a1-crypto
> > + - enum:
> > + - amlogic,gxl-crypto
> > + - amlogic,axg-crypto
> > + - amlogic,g12a-crypto
> > + - amlogic,a1-crypto
> >
> > reg:
> > maxItems: 1
> > @@ -21,6 +29,9 @@ properties:
> > items:
> > - description: Interrupt for flow 0
> >
> > + power-domains:
> > + maxItems: 1
>
> Is power-domains valid for the devices that existed prior to your patch?
For existed devices (GXL) power domain doesn't required.
--
Thank you,
Alexey
^ permalink raw reply
* Re: [PATCH v6 17/23] dt-bindings: crypto: meson: remove clk and second interrupt line for GXL
From: Alexey Romanov @ 2024-03-29 11:14 UTC (permalink / raw)
To: Conor Dooley
Cc: neil.armstrong@linaro.org, clabbe@baylibre.com,
herbert@gondor.apana.org.au, davem@davemloft.net,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, vadim.fedorenko@linux.dev,
linux-crypto@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kernel
In-Reply-To: <20240326-obscurity-angriness-d7bb48bc9eaa@spud>
Hi Conor,
On Tue, Mar 26, 2024 at 06:09:37PM +0000, Conor Dooley wrote:
> On Tue, Mar 26, 2024 at 06:32:13PM +0300, Alexey Romanov wrote:
> > GXL crypto IP uses DMA engine, which doesn't require clk input
> > and second interrupt line.
> >
> > Fixes: c4a0457eb858 ("ARM64: dts: amlogic: adds crypto hardware node")
>
> How does this fix a commit that only modifies a dts? The commit cited
> here should be a dt-bindings commit.
Yep, my bad. Will fix it in next series.
>
> However, your commit message says "require" but you do more than remove
> these as required, you remove them entirely. What am I missing?
Crypto HW isn't connected to clk / 2nd interrput line, so we must remove
them from dt. I will reformulate commit message.
>
> Thanks,
> Conor.
>
> > Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
> > ---
> > .../bindings/crypto/amlogic,gxl-crypto.yaml | 13 +------------
> > 1 file changed, 1 insertion(+), 12 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > index 948e11ebe4ee..d3af7b4d5f39 100644
> > --- a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > +++ b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
> > @@ -20,20 +20,11 @@ properties:
> > interrupts:
> > items:
> > - description: Interrupt for flow 0
> > - - description: Interrupt for flow 1
> > -
> > - clocks:
> > - maxItems: 1
> > -
> > - clock-names:
> > - const: blkmv
> >
> > required:
> > - compatible
> > - reg
> > - interrupts
> > - - clocks
> > - - clock-names
> >
> > additionalProperties: false
> >
> > @@ -46,7 +37,5 @@ examples:
> > crypto: crypto-engine@c883e000 {
> > compatible = "amlogic,gxl-crypto";
> > reg = <0xc883e000 0x36>;
> > - interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
> > - clocks = <&clkc CLKID_BLKMV>;
> > - clock-names = "blkmv";
> > + interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>;
> > };
> > --
> > 2.34.1
> >
--
Thank you,
Alexey
^ permalink raw reply
* Re: [PATCH 0/4] Add USB Support on Qualcomm's QDU/QRU1000 Platform
From: Komal Bajaj @ 2024-03-29 11:02 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Wesley Cheng, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-usb
In-Reply-To: <CAA8EJpojQg2BHvR5kZtRxyXWRKy6zV=88_bdcuMH+QE-n4k73A@mail.gmail.com>
On 3/19/2024 3:05 PM, Dmitry Baryshkov wrote:
> On Tue, 19 Mar 2024 at 11:08, Komal Bajaj <quic_kbajaj@quicinc.com> wrote:
>>
>> This series adds support of USB3 PHY support for Qualcomm's QDU/QRU1000 Platform.
>>
>> ---------
>> Changes in v2:
>> * Dropped extra lines
>> * Sorted the tables alphabetically
>> * Link to v1: https://lore.kernel.org/linux-arm-msm/20240311120215.16845-1-quic_kbajaj@quicinc.com/
>
> So, this is v2, but you didn't mark patches as v2. Please use b4 for
> sending patches. It can handle patch revisions automatically.
Apologies for this, forgot to mark patches as v2.
I will be careful next time.
>
>>
>> Komal Bajaj (4):
>> dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000
>> dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY
>> dt-bindings: usb: dwc3: Add QDU1000 compatible
>> phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000
>>
>> .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 2 +
>> .../bindings/phy/qcom,usb-snps-femto-v2.yaml | 1 +
>> .../devicetree/bindings/usb/qcom,dwc3.yaml | 3 ++
>> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 49 +++++++++++++++++++
>> 4 files changed, 55 insertions(+)
>
>
>
^ permalink raw reply
* Re: [PATCH v4 4/4] remoteproc: stm32: Add support of an OP-TEE TA to load the firmware
From: Arnaud POULIQUEN @ 2024-03-29 10:57 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Bjorn Andersson, Jens Wiklander, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-stm32, linux-arm-kernel, linux-remoteproc,
linux-kernel, op-tee, devicetree
In-Reply-To: <ZgRT7PtzIogAWc50@p14s>
On 3/27/24 18:14, Mathieu Poirier wrote:
> On Tue, Mar 26, 2024 at 08:31:33PM +0100, Arnaud POULIQUEN wrote:
>>
>>
>> On 3/25/24 17:51, Mathieu Poirier wrote:
>>> On Fri, Mar 08, 2024 at 03:47:08PM +0100, Arnaud Pouliquen wrote:
>>>> The new TEE remoteproc device is used to manage remote firmware in a
>>>> secure, trusted context. The 'st,stm32mp1-m4-tee' compatibility is
>>>> introduced to delegate the loading of the firmware to the trusted
>>>> execution context. In such cases, the firmware should be signed and
>>>> adhere to the image format defined by the TEE.
>>>>
>>>> Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
>>>> ---
>>>> Updates from V3:
>>>> - remove support of the attach use case. Will be addressed in a separate
>>>> thread,
>>>> - add st_rproc_tee_ops::parse_fw ops,
>>>> - inverse call of devm_rproc_alloc()and tee_rproc_register() to manage cross
>>>> reference between the rproc struct and the tee_rproc struct in tee_rproc.c.
>>>> ---
>>>> drivers/remoteproc/stm32_rproc.c | 60 +++++++++++++++++++++++++++++---
>>>> 1 file changed, 56 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/remoteproc/stm32_rproc.c b/drivers/remoteproc/stm32_rproc.c
>>>> index 8cd838df4e92..13df33c78aa2 100644
>>>> --- a/drivers/remoteproc/stm32_rproc.c
>>>> +++ b/drivers/remoteproc/stm32_rproc.c
>>>> @@ -20,6 +20,7 @@
>>>> #include <linux/remoteproc.h>
>>>> #include <linux/reset.h>
>>>> #include <linux/slab.h>
>>>> +#include <linux/tee_remoteproc.h>
>>>> #include <linux/workqueue.h>
>>>>
>>>> #include "remoteproc_internal.h"
>>>> @@ -49,6 +50,9 @@
>>>> #define M4_STATE_STANDBY 4
>>>> #define M4_STATE_CRASH 5
>>>>
>>>> +/* Remote processor unique identifier aligned with the Trusted Execution Environment definitions */
>>>
>>> Why is this the case? At least from the kernel side it is possible to call
>>> tee_rproc_register() with any kind of value, why is there a need to be any
>>> kind of alignment with the TEE?
>>
>>
>> The use of the proc_id is to identify a processor in case of multi co-processors.
>>
>
> That is well understood.
>
>> For instance we can have a system with A DSP and a modem. We would use the same
>> TEE service, but
>
> That too.
>
>> the TEE driver will probably be different, same for the signature key.
>
> What TEE driver are we talking about here?
In OP-TEE remoteproc frameork is divided in 2 or 3 layers:
- the remoteproc Trusted Application (TA) [1] which is platform agnostic
- The remoteproc Pseudo Trusted Application (PTA) [2] which is platform
dependent and can rely on the proc ID to retrieve the context.
- the remoteproc driver (optional for some platforms) [3], which is in charge
of DT parsing and platform configuration.
Here TEE driver can be interpreted by remote PTA and/or platform driver.
[1]
https://elixir.bootlin.com/op-tee/latest/source/ta/remoteproc/src/remoteproc_core.c
[2]
https://elixir.bootlin.com/op-tee/latest/source/core/pta/stm32mp/remoteproc_pta.c
[3]
https://elixir.bootlin.com/op-tee/latest/source/core/drivers/remoteproc/stm32_remoteproc.c
>
>> In such case the proc ID allows to identify the the processor you want to address.
>>
>
> That too is well understood, but there is no alignment needed with the TEE, i.e
> the TEE application is not expecting a value of '0'. We could set
> STM32_MP1_M4_PROC_ID to 0xDEADBEEF and things would work. This driver won't go
> anywhere for as long as it is not the case.
Here I suppose that you do not challenge the rproc_ID use in general, but for
the stm32mp1 platform as we have only one remote processor. I'm right?
In OP-TEE the check is done here:
https://elixir.bootlin.com/op-tee/latest/source/core/drivers/remoteproc/stm32_remoteproc.c#L64
If driver does not register the proc ID an error is returned indicating that the
feature is not supported.
In case of stm32mp1 yes we could consider it as useless as we have only one
remote proc.
Nevertheless I can not guaranty that a customer will not add an external
companion processor that uses OP-TEE to authenticate the associated firmware. As
the trusted Application is the unique entry point. he will need the proc_id to
identify the target at PTA level.
So from my point of view having a proc ID on stm32MP1 (and on stm32mp2 that will
reuse same driver) aligned between Linux and OP-TEE is useful.
That said using a TEE_REMOTEPROC_DEFAULT_ID is something that could be
more generic (for linux and OP-TEE). This ID could be reuse in the stm32mp
driver and platform drivers with an unique internal remote processor.
It that solution would be ok for you?
Regards,
Arnaud
>
>>
>>>
>>>> +#define STM32_MP1_M4_PROC_ID 0
>>>> +
>>>> struct stm32_syscon {
>>>> struct regmap *map;
>>>> u32 reg;
>>>> @@ -257,6 +261,19 @@ static int stm32_rproc_release(struct rproc *rproc)
>>>> return 0;
>>>> }
>>>>
>>>> +static int stm32_rproc_tee_stop(struct rproc *rproc)
>>>> +{
>>>> + int err;
>>>> +
>>>> + stm32_rproc_request_shutdown(rproc);
>>>> +
>>>> + err = tee_rproc_stop(rproc);
>>>> + if (err)
>>>> + return err;
>>>> +
>>>> + return stm32_rproc_release(rproc);
>>>> +}
>>>> +
>>>> static int stm32_rproc_prepare(struct rproc *rproc)
>>>> {
>>>> struct device *dev = rproc->dev.parent;
>>>> @@ -693,8 +710,19 @@ static const struct rproc_ops st_rproc_ops = {
>>>> .get_boot_addr = rproc_elf_get_boot_addr,
>>>> };
>>>>
>>>> +static const struct rproc_ops st_rproc_tee_ops = {
>>>> + .prepare = stm32_rproc_prepare,
>>>> + .start = tee_rproc_start,
>>>> + .stop = stm32_rproc_tee_stop,
>>>> + .kick = stm32_rproc_kick,
>>>> + .load = tee_rproc_load_fw,
>>>> + .parse_fw = tee_rproc_parse_fw,
>>>> + .find_loaded_rsc_table = tee_rproc_find_loaded_rsc_table,
>>>> +};
>>>> +
>>>> static const struct of_device_id stm32_rproc_match[] = {
>>>> - { .compatible = "st,stm32mp1-m4" },
>>>> + {.compatible = "st,stm32mp1-m4",},
>>>> + {.compatible = "st,stm32mp1-m4-tee",},
>>>> {},
>>>> };
>>>> MODULE_DEVICE_TABLE(of, stm32_rproc_match);
>>>> @@ -853,6 +881,7 @@ static int stm32_rproc_probe(struct platform_device *pdev)
>>>> struct device *dev = &pdev->dev;
>>>> struct stm32_rproc *ddata;
>>>> struct device_node *np = dev->of_node;
>>>> + struct tee_rproc *trproc = NULL;
>>>> struct rproc *rproc;
>>>> unsigned int state;
>>>> int ret;
>>>> @@ -861,9 +890,26 @@ static int stm32_rproc_probe(struct platform_device *pdev)
>>>> if (ret)
>>>> return ret;
>>>>
>>>> - rproc = devm_rproc_alloc(dev, np->name, &st_rproc_ops, NULL, sizeof(*ddata));
>>>> - if (!rproc)
>>>> - return -ENOMEM;
>>>> + if (of_device_is_compatible(np, "st,stm32mp1-m4-tee")) {
>>>> + /*
>>>> + * Delegate the firmware management to the secure context.
>>>> + * The firmware loaded has to be signed.
>>>> + */
>>>> + rproc = devm_rproc_alloc(dev, np->name, &st_rproc_tee_ops, NULL, sizeof(*ddata));
>>>> + if (!rproc)
>>>> + return -ENOMEM;
>>>> +
>>>> + trproc = tee_rproc_register(dev, rproc, STM32_MP1_M4_PROC_ID);
>>>> + if (IS_ERR(trproc)) {
>>>> + dev_err_probe(dev, PTR_ERR(trproc),
>>>> + "signed firmware not supported by TEE\n");
>>>> + return PTR_ERR(trproc);
>>>> + }
>>>> + } else {
>>>> + rproc = devm_rproc_alloc(dev, np->name, &st_rproc_ops, NULL, sizeof(*ddata));
>>>> + if (!rproc)
>>>> + return -ENOMEM;
>>>> + }
>>>>
>>>> ddata = rproc->priv;
>>>>
>>>> @@ -915,6 +961,9 @@ static int stm32_rproc_probe(struct platform_device *pdev)
>>>> dev_pm_clear_wake_irq(dev);
>>>> device_init_wakeup(dev, false);
>>>> }
>>>> + if (trproc)
>>>
>>> if (rproc->tee_interface)
>>>
>>>
>>> I am done reviewing this set.
>>
>> Thank for your review!
>> Arnaud
>>
>>>
>>> Thanks,
>>> Mathieu
>>>
>>>> + tee_rproc_unregister(trproc);
>>>> +
>>>> return ret;
>>>> }
>>>>
>>>> @@ -935,6 +984,9 @@ static void stm32_rproc_remove(struct platform_device *pdev)
>>>> dev_pm_clear_wake_irq(dev);
>>>> device_init_wakeup(dev, false);
>>>> }
>>>> + if (rproc->tee_interface)
>>>> + tee_rproc_unregister(rproc->tee_interface);
>>>> +
>>>> }
>>>>
>>>> static int stm32_rproc_suspend(struct device *dev)
>>>> --
>>>> 2.25.1
>>>>
^ permalink raw reply
* Re: [PATCH v5 4/5] clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks
From: Varadarajan Narayanan @ 2024-03-29 10:55 UTC (permalink / raw)
To: Stephen Boyd
Cc: andersson, conor+dt, devicetree, djakov, dmitry.baryshkov,
konrad.dybcio, krzysztof.kozlowski+dt, linux-arm-msm, linux-clk,
linux-kernel, linux-pm, mturquette, quic_anusha, robh
In-Reply-To: <95f4e99a60cc97770fc3cee850b62faf.sboyd@kernel.org>
On Thu, Mar 28, 2024 at 02:51:09PM -0700, Stephen Boyd wrote:
> Quoting Varadarajan Narayanan (2024-03-28 00:59:35)
> > diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> > index 0a3f846695b8..187fd9dcdf49 100644
> > --- a/drivers/clk/qcom/gcc-ipq9574.c
> > +++ b/drivers/clk/qcom/gcc-ipq9574.c
> > @@ -4301,6 +4302,56 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
> > [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
> > };
> >
> > +#define IPQ_APPS_ID 9574 /* some unique value */
>
> How is this supposed to stay unique?
The icc-clk driver expects some number that wouldn't interfere
with the existing nodes. So just used the SoC id itself.
> I don't understand icc_node_create() API quite honestly. Why
> can't icc_clk_register() maintain some ida of allocated
> numbers? Or is there some global number space that we can
> "reserve" from? I'm quite amazed this is how things are
> connected in interconnect framework.
>
> > +
> > +enum {
> > + ICC_ANOC_PCIE0,
> > + ICC_SNOC_PCIE0,
> > + ICC_ANOC_PCIE1,
> > + ICC_SNOC_PCIE1,
> > + ICC_ANOC_PCIE2,
> > + ICC_SNOC_PCIE2,
> > + ICC_ANOC_PCIE3,
> > + ICC_SNOC_PCIE3,
> > + ICC_SNOC_USB,
> > + ICC_ANOC_USB_AXI,
> > + ICC_NSSNOC_NSSCC,
> > + ICC_NSSNOC_SNOC_0,
> > + ICC_NSSNOC_SNOC_1,
> > + ICC_NSSNOC_PCNOC_1,
> > + ICC_NSSNOC_QOSGEN_REF,
> > + ICC_NSSNOC_TIMEOUT_REF,
> > + ICC_NSSNOC_XO_DCD,
> > + ICC_NSSNOC_ATB,
> > + ICC_MEM_NOC_NSSNOC,
> > + ICC_NSSNOC_MEMNOC,
> > + ICC_NSSNOC_MEM_NOC_1,
> > +};
>
> Are these supposed to be in a dt-binding header?
Since these don't directly relate to the ids in the dt-bindings
not sure if they will be permitted there. Will move and post a
new version and get feedback.
Thanks
Varada
> > +
> > +static struct clk_hw *icc_ipq9574_hws[] = {
> > + [ICC_ANOC_PCIE0] = &gcc_anoc_pcie0_1lane_m_clk.clkr.hw,
> > + [ICC_SNOC_PCIE0] = &gcc_anoc_pcie1_1lane_m_clk.clkr.hw,
> > + [ICC_ANOC_PCIE1] = &gcc_anoc_pcie2_2lane_m_clk.clkr.hw,
> > + [ICC_SNOC_PCIE1] = &gcc_anoc_pcie3_2lane_m_clk.clkr.hw,
> > + [ICC_ANOC_PCIE2] = &gcc_snoc_pcie0_1lane_s_clk.clkr.hw,
> > + [ICC_SNOC_PCIE2] = &gcc_snoc_pcie1_1lane_s_clk.clkr.hw,
^ permalink raw reply
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