* Re: [PATCH 06/10] dt-bindings: iio: dac: add bindings doc for AXI DAC driver
From: David Lechner @ 2024-03-29 18:46 UTC (permalink / raw)
To: nuno.sa
Cc: linux-iio, devicetree, Dragos Bogdan, Jonathan Cameron,
Lars-Peter Clausen, Michael Hennerich, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Olivier Moysan
In-Reply-To: <20240328-iio-backend-axi-dac-v1-6-afc808b3fde3@analog.com>
On Thu, Mar 28, 2024 at 8:22 AM Nuno Sa via B4 Relay
<devnull+nuno.sa.analog.com@kernel.org> wrote:
>
> From: Nuno Sa <nuno.sa@analog.com>
>
> This adds the bindings documentation for the AXI DAC driver.
>
> Signed-off-by: Nuno Sa <nuno.sa@analog.com>
> ---
> .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 62 ++++++++++++++++++++++
> MAINTAINERS | 7 +++
> 2 files changed, 69 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml
> new file mode 100644
> index 000000000000..1018fd274f04
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/dac/adi,axi-dac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices AXI DAC IP core
> +
> +maintainers:
> + - Nuno Sa <nuno.sa@analog.com>
> +
> +description: |
> + Analog Devices Generic AXI DAC IP core for interfacing a DAC device
> + with a high speed serial (JESD204B/C) or source synchronous parallel
> + interface (LVDS/CMOS).
> + Usually, some other interface type (i.e SPI) is used as a control
> + interface for the actual DAC, while this IP core will interface
> + to the data-lines of the DAC and handle the streaming of data into
> + memory via DMA.
Isn't it the other way around for DAC, from memory to hardware?
^ permalink raw reply
* [PATCH v7 0/6] spmi: pmic-arb: Add support for multiple buses
From: Abel Vesa @ 2024-03-29 18:54 UTC (permalink / raw)
To: Stephen Boyd, Matthias Brugger, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, Neil Armstrong, AngeloGioacchino Del Regno,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Srini Kandagatla, Johan Hovold, linux-kernel, linux-arm-kernel,
linux-arm-msm, linux-mediatek, devicetree, Abel Vesa,
Krzysztof Kozlowski
This RFC prepares for and adds support for 2 buses, which is supported
in HW starting with version 7. Until now, none of the currently
supported platforms in upstream have used the second bus. The X1E80100
platform, on the other hand, needs the second bus for the USB2.0 to work
as there are 3 SMB2360 PMICs which provide eUSB2 repeaters and they are
all found on the second bus.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
Changes in v7:
- This time really collected Krzysztof's R-b tags
- Added Neil's R-b tag to the 4th patch
- Split the multi bus patch into two separate patches, one for adding
the bus object and one for the secondary bus, as per Neil's suggestion
- Fixed regression for single bus platforms triggered by casting to
pmic_arb instead of bus in pmic_arb_non_data_cmd_v1
- Fixed bus object allocation by using ctrl drvdata instead
- Prefixed the spmi node property in x1e80100 schema with '^'
- Fixed struct and function documentation warnings reported by Neil
Changes in v6 (resend):
- Collected Krzysztof's R-b tags
- Link to v6: https://lore.kernel.org/r/20240222-spmi-multi-master-support-v6-0-bc34ea9561da@linaro.org
Changes in v6:
- Changed the compatible to platform specific (X1E80100) along with the
schema. Fixed the spmi buses unit addresses and added the empty ranges
property. Added missing properties to the spmi buses and the
"unevaluatedProperties: false".
- Deprecated the "qcom,bus-id" in the legacy schema.
- Changed the driver to check for legacy compatible first
- Link to v5: https://lore.kernel.org/r/20240221-spmi-multi-master-support-v5-0-3255ca413a0b@linaro.org
Changes in v5:
- Dropped the RFC as there aren't any concerns about the approach anymore
- Dropped the unused dev and res variables from pmic_arb_get_obsrvr_chnls_v2
- Link to v4: https://lore.kernel.org/r/20240220-spmi-multi-master-support-v4-0-dc813c878ba8@linaro.org
Changes in v4:
- Fixed comment above pmic_arb_init_apid_v7 by dropping the extra "bus" word
- Swicthed to devm_platform_ioremap_resource_byname for obsrvr and chnls.
The core remains with platform_get_resource_byname as we need the core size.
- Dropped comment from probe related to the need of platform_get_resource_byname
as it not true anymore.
- Dropped the qcom,bus-id optional property.
- Link to v3: https://lore.kernel.org/r/20240214-spmi-multi-master-support-v3-0-0bae0ef04faf@linaro.org
Changes in v3:
- Split the change into 3 separate patches. First 2 patches are moving
apid init and core resources into version specific ops. Third one is
adding the support for 2 buses and dedicated compatible.
- Added separate bindings patch
- Link to v2: https://lore.kernel.org/r/20240213-spmi-multi-master-support-v2-1-b3b102326906@linaro.org
Changes in v2:
- Reworked it so that it registers a spmi controller for each bus
rather than relying on the generic framework to pass on the bus
(master) id.
- Link to v1: https://lore.kernel.org/r/20240207-spmi-multi-master-support-v1-0-ce57f301c7fd@linaro.org
---
Abel Vesa (6):
dt-bindings: spmi: Add X1E80100 SPMI PMIC ARB schema
dt-bindings: spmi: Deprecate qcom,bus-id
spmi: pmic-arb: Make the APID init a version operation
spmi: pmic-arb: Make core resources acquiring a version operation
spmi: pmic-arb: Register controller for bus instead of arbiter
spmi: pmic-arb: Add multi bus support
.../bindings/spmi/qcom,spmi-pmic-arb.yaml | 1 +
.../bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml | 136 +++
drivers/spmi/spmi-pmic-arb.c | 953 +++++++++++++--------
3 files changed, 723 insertions(+), 367 deletions(-)
---
base-commit: a6bd6c9333397f5a0e2667d4d82fef8c970108f2
change-id: 20240207-spmi-multi-master-support-832a704b779b
Best regards,
--
Abel Vesa <abel.vesa@linaro.org>
^ permalink raw reply
* [PATCH v7 1/6] dt-bindings: spmi: Add X1E80100 SPMI PMIC ARB schema
From: Abel Vesa @ 2024-03-29 18:54 UTC (permalink / raw)
To: Stephen Boyd, Matthias Brugger, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, Neil Armstrong, AngeloGioacchino Del Regno,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Srini Kandagatla, Johan Hovold, linux-kernel, linux-arm-kernel,
linux-arm-msm, linux-mediatek, devicetree, Abel Vesa,
Krzysztof Kozlowski
In-Reply-To: <20240329-spmi-multi-master-support-v7-0-7b902824246c@linaro.org>
Add dedicated schema for X1E80100 PMIC ARB (v7) as it allows multiple
buses by declaring them as child nodes.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
.../bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml | 136 +++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml
new file mode 100644
index 000000000000..f32a7ae33b4b
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm X1E80100 SPMI Controller (PMIC Arbiter v7)
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+
+description: |
+ The X1E80100 SPMI PMIC Arbiter implements HW version 7 and it's an SPMI
+ controller with wrapping arbitration logic to allow for multiple on-chip
+ devices to control up to 2 SPMI separate buses.
+
+ The PMIC Arbiter can also act as an interrupt controller, providing interrupts
+ to slave devices.
+
+properties:
+ compatible:
+ const: qcom,x1e80100-spmi-pmic-arb
+
+ reg:
+ items:
+ - description: core registers
+ - description: tx-channel per virtual slave regosters
+ - description: rx-channel (called observer) per virtual slave registers
+
+ reg-names:
+ items:
+ - const: core
+ - const: chnls
+ - const: obsrvr
+
+ ranges: true
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 2
+
+ qcom,ee:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 5
+ description: >
+ indicates the active Execution Environment identifier
+
+ qcom,channel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 5
+ description: >
+ which of the PMIC Arb provided channels to use for accesses
+
+patternProperties:
+ "^spmi@[a-f0-9]+$":
+ type: object
+ $ref: /schemas/spmi/spmi.yaml
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ items:
+ - description: configuration registers
+ - description: interrupt controller registers
+
+ reg-names:
+ items:
+ - const: cnfg
+ - const: intr
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: periph_irq
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 4
+ description: |
+ cell 1: slave ID for the requested interrupt (0-15)
+ cell 2: peripheral ID for requested interrupt (0-255)
+ cell 3: the requested peripheral interrupt (0-7)
+ cell 4: interrupt flags indicating level-sense information,
+ as defined in dt-bindings/interrupt-controller/irq.h
+
+required:
+ - compatible
+ - reg-names
+ - qcom,ee
+ - qcom,channel
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ spmi: arbiter@c400000 {
+ compatible = "qcom,x1e80100-spmi-pmic-arb";
+ reg = <0 0x0c400000 0 0x3000>,
+ <0 0x0c500000 0 0x4000000>,
+ <0 0x0c440000 0 0x80000>;
+ reg-names = "core", "chnls", "obsrvr";
+
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ spmi_bus0: spmi@c42d000 {
+ reg = <0 0x0c42d000 0 0x4000>,
+ <0 0x0c4c0000 0 0x10000>;
+ reg-names = "cnfg", "intr";
+
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related
* [PATCH v7 2/6] dt-bindings: spmi: Deprecate qcom,bus-id
From: Abel Vesa @ 2024-03-29 18:54 UTC (permalink / raw)
To: Stephen Boyd, Matthias Brugger, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, Neil Armstrong, AngeloGioacchino Del Regno,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Srini Kandagatla, Johan Hovold, linux-kernel, linux-arm-kernel,
linux-arm-msm, linux-mediatek, devicetree, Abel Vesa,
Krzysztof Kozlowski
In-Reply-To: <20240329-spmi-multi-master-support-v7-0-7b902824246c@linaro.org>
As it is optional and no platform is actually using the secondary bus,
deprecate the qcom,bus-id property. For newer platforms that implement
SPMI PMIC ARB v7 in HW, the X1E80100 approach should be used.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
index f983b4af6db9..51daf1b847a9 100644
--- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
+++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
@@ -92,6 +92,7 @@ properties:
description: >
SPMI bus instance. only applicable to PMIC arbiter version 7 and beyond.
Supported values, 0 = primary bus, 1 = secondary bus
+ deprecated: true
required:
- compatible
--
2.34.1
^ permalink raw reply related
* [PATCH v7 3/6] spmi: pmic-arb: Make the APID init a version operation
From: Abel Vesa @ 2024-03-29 18:54 UTC (permalink / raw)
To: Stephen Boyd, Matthias Brugger, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, Neil Armstrong, AngeloGioacchino Del Regno,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Srini Kandagatla, Johan Hovold, linux-kernel, linux-arm-kernel,
linux-arm-msm, linux-mediatek, devicetree, Abel Vesa
In-Reply-To: <20240329-spmi-multi-master-support-v7-0-7b902824246c@linaro.org>
Rather than using conditionals in probe function, add the APID init
as a version specific operation. Due to v7, which supports multiple
buses, pass on the bus index to be used for sorting out the apid base
and count.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
drivers/spmi/spmi-pmic-arb.c | 199 +++++++++++++++++++++++++++----------------
1 file changed, 124 insertions(+), 75 deletions(-)
diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
index 9ed1180fe31f..38fed8a585fe 100644
--- a/drivers/spmi/spmi-pmic-arb.c
+++ b/drivers/spmi/spmi-pmic-arb.c
@@ -183,6 +183,7 @@ struct spmi_pmic_arb {
* struct pmic_arb_ver_ops - version dependent functionality.
*
* @ver_str: version string.
+ * @init_apid: finds the apid base and count
* @ppid_to_apid: finds the apid for a given ppid.
* @non_data_cmd: on v1 issues an spmi non-data command.
* on v2 no HW support, returns -EOPNOTSUPP.
@@ -202,6 +203,7 @@ struct spmi_pmic_arb {
*/
struct pmic_arb_ver_ops {
const char *ver_str;
+ int (*init_apid)(struct spmi_pmic_arb *pmic_arb, int index);
int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
/* spmi commands (read_cmd, write_cmd, cmd) functionality */
int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
@@ -942,6 +944,38 @@ static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
return 0;
}
+static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb *pmic_arb)
+{
+ /*
+ * Initialize max_apid/min_apid to the opposite bounds, during
+ * the irq domain translation, we are sure to update these
+ */
+ pmic_arb->max_apid = 0;
+ pmic_arb->min_apid = pmic_arb->max_periphs - 1;
+
+ return 0;
+}
+
+static int pmic_arb_init_apid_v1(struct spmi_pmic_arb *pmic_arb, int index)
+{
+ u32 *mapping_table;
+
+ if (index) {
+ dev_err(&pmic_arb->spmic->dev, "Unsupported buses count %d detected\n",
+ index);
+ return -EINVAL;
+ }
+
+ mapping_table = devm_kcalloc(&pmic_arb->spmic->dev, pmic_arb->max_periphs,
+ sizeof(*mapping_table), GFP_KERNEL);
+ if (!mapping_table)
+ return -ENOMEM;
+
+ pmic_arb->mapping_table = mapping_table;
+
+ return pmic_arb_init_apid_min_max(pmic_arb);
+}
+
static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
{
u32 *mapping_table = pmic_arb->mapping_table;
@@ -1144,6 +1178,40 @@ static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
return 0x1000 * pmic_arb->ee + 0x8000 * apid;
}
+static int pmic_arb_init_apid_v5(struct spmi_pmic_arb *pmic_arb, int index)
+{
+ int ret;
+
+ if (index) {
+ dev_err(&pmic_arb->spmic->dev, "Unsupported buses count %d detected\n",
+ index);
+ return -EINVAL;
+ }
+
+ pmic_arb->base_apid = 0;
+ pmic_arb->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
+ PMIC_ARB_FEATURES_PERIPH_MASK;
+
+ if (pmic_arb->base_apid + pmic_arb->apid_count > pmic_arb->max_periphs) {
+ dev_err(&pmic_arb->spmic->dev, "Unsupported APID count %d detected\n",
+ pmic_arb->base_apid + pmic_arb->apid_count);
+ return -EINVAL;
+ }
+
+ ret = pmic_arb_init_apid_min_max(pmic_arb);
+ if (ret)
+ return ret;
+
+ ret = pmic_arb_read_apid_map_v5(pmic_arb);
+ if (ret) {
+ dev_err(&pmic_arb->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n",
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
/*
* v5 offset per ee and per apid for observer channels and per apid for
* read/write channels.
@@ -1178,6 +1246,49 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
return offset;
}
+/*
+ * Only v7 supports 2 buses. Each bus will get a different apid count, read
+ * from different registers.
+ */
+static int pmic_arb_init_apid_v7(struct spmi_pmic_arb *pmic_arb, int index)
+{
+ int ret;
+
+ if (index == 0) {
+ pmic_arb->base_apid = 0;
+ pmic_arb->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
+ PMIC_ARB_FEATURES_PERIPH_MASK;
+ } else if (index == 1) {
+ pmic_arb->base_apid = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
+ PMIC_ARB_FEATURES_PERIPH_MASK;
+ pmic_arb->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES1) &
+ PMIC_ARB_FEATURES_PERIPH_MASK;
+ } else {
+ dev_err(&pmic_arb->spmic->dev, "Unsupported buses count %d detected\n",
+ index);
+ return -EINVAL;
+ }
+
+ if (pmic_arb->base_apid + pmic_arb->apid_count > pmic_arb->max_periphs) {
+ dev_err(&pmic_arb->spmic->dev, "Unsupported APID count %d detected\n",
+ pmic_arb->base_apid + pmic_arb->apid_count);
+ return -EINVAL;
+ }
+
+ ret = pmic_arb_init_apid_min_max(pmic_arb);
+ if (ret)
+ return ret;
+
+ ret = pmic_arb_read_apid_map_v5(pmic_arb);
+ if (ret) {
+ dev_err(&pmic_arb->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n",
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
/*
* v7 offset per ee and per apid for observer channels and per apid for
* read/write channels.
@@ -1358,6 +1469,7 @@ pmic_arb_apid_owner_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
static const struct pmic_arb_ver_ops pmic_arb_v1 = {
.ver_str = "v1",
+ .init_apid = pmic_arb_init_apid_v1,
.ppid_to_apid = pmic_arb_ppid_to_apid_v1,
.non_data_cmd = pmic_arb_non_data_cmd_v1,
.offset = pmic_arb_offset_v1,
@@ -1372,6 +1484,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v1 = {
static const struct pmic_arb_ver_ops pmic_arb_v2 = {
.ver_str = "v2",
+ .init_apid = pmic_arb_init_apid_v1,
.ppid_to_apid = pmic_arb_ppid_to_apid_v2,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
.offset = pmic_arb_offset_v2,
@@ -1386,6 +1499,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v2 = {
static const struct pmic_arb_ver_ops pmic_arb_v3 = {
.ver_str = "v3",
+ .init_apid = pmic_arb_init_apid_v1,
.ppid_to_apid = pmic_arb_ppid_to_apid_v2,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
.offset = pmic_arb_offset_v2,
@@ -1400,6 +1514,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v3 = {
static const struct pmic_arb_ver_ops pmic_arb_v5 = {
.ver_str = "v5",
+ .init_apid = pmic_arb_init_apid_v5,
.ppid_to_apid = pmic_arb_ppid_to_apid_v5,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
.offset = pmic_arb_offset_v5,
@@ -1414,6 +1529,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v5 = {
static const struct pmic_arb_ver_ops pmic_arb_v7 = {
.ver_str = "v7",
+ .init_apid = pmic_arb_init_apid_v7,
.ppid_to_apid = pmic_arb_ppid_to_apid_v5,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
.offset = pmic_arb_offset_v7,
@@ -1439,7 +1555,6 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
struct spmi_controller *ctrl;
struct resource *res;
void __iomem *core;
- u32 *mapping_table;
u32 channel, ee, hw_ver;
int err;
@@ -1467,12 +1582,6 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
pmic_arb->core_size = resource_size(res);
- pmic_arb->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
- sizeof(*pmic_arb->ppid_to_apid),
- GFP_KERNEL);
- if (!pmic_arb->ppid_to_apid)
- return -ENOMEM;
-
hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
@@ -1506,58 +1615,17 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
return PTR_ERR(pmic_arb->wr_base);
}
- pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS;
+ dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
+ pmic_arb->ver_ops->ver_str, hw_ver);
- if (hw_ver >= PMIC_ARB_VERSION_V7_MIN) {
+ if (hw_ver < PMIC_ARB_VERSION_V7_MIN)
+ pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS;
+ else
pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V7;
- /* Optional property for v7: */
- of_property_read_u32(pdev->dev.of_node, "qcom,bus-id",
- &pmic_arb->bus_instance);
- if (pmic_arb->bus_instance > 1) {
- dev_err(&pdev->dev, "invalid bus instance (%u) specified\n",
- pmic_arb->bus_instance);
- return -EINVAL;
- }
-
- if (pmic_arb->bus_instance == 0) {
- pmic_arb->base_apid = 0;
- pmic_arb->apid_count =
- readl_relaxed(core + PMIC_ARB_FEATURES) &
- PMIC_ARB_FEATURES_PERIPH_MASK;
- } else {
- pmic_arb->base_apid =
- readl_relaxed(core + PMIC_ARB_FEATURES) &
- PMIC_ARB_FEATURES_PERIPH_MASK;
- pmic_arb->apid_count =
- readl_relaxed(core + PMIC_ARB_FEATURES1) &
- PMIC_ARB_FEATURES_PERIPH_MASK;
- }
- if (pmic_arb->base_apid + pmic_arb->apid_count > pmic_arb->max_periphs) {
- dev_err(&pdev->dev, "Unsupported APID count %d detected\n",
- pmic_arb->base_apid + pmic_arb->apid_count);
- return -EINVAL;
- }
- } else if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
- pmic_arb->base_apid = 0;
- pmic_arb->apid_count = readl_relaxed(core + PMIC_ARB_FEATURES) &
- PMIC_ARB_FEATURES_PERIPH_MASK;
-
- if (pmic_arb->apid_count > pmic_arb->max_periphs) {
- dev_err(&pdev->dev, "Unsupported APID count %d detected\n",
- pmic_arb->apid_count);
- return -EINVAL;
- }
- }
-
- pmic_arb->apid_data = devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs,
- sizeof(*pmic_arb->apid_data),
- GFP_KERNEL);
- if (!pmic_arb->apid_data)
- return -ENOMEM;
-
- dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
- pmic_arb->ver_ops->ver_str, hw_ver);
+ err = pmic_arb->ver_ops->init_apid(pmic_arb, 0);
+ if (err)
+ return err;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
@@ -1599,16 +1667,6 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
}
pmic_arb->ee = ee;
- mapping_table = devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs,
- sizeof(*mapping_table), GFP_KERNEL);
- if (!mapping_table)
- return -ENOMEM;
-
- pmic_arb->mapping_table = mapping_table;
- /* Initialize max_apid/min_apid to the opposite bounds, during
- * the irq domain translation, we are sure to update these */
- pmic_arb->max_apid = 0;
- pmic_arb->min_apid = pmic_arb->max_periphs - 1;
platform_set_drvdata(pdev, ctrl);
raw_spin_lock_init(&pmic_arb->lock);
@@ -1617,15 +1675,6 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
ctrl->read_cmd = pmic_arb_read_cmd;
ctrl->write_cmd = pmic_arb_write_cmd;
- if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
- err = pmic_arb_read_apid_map_v5(pmic_arb);
- if (err) {
- dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n",
- err);
- return err;
- }
- }
-
dev_dbg(&pdev->dev, "adding irq domain\n");
pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
&pmic_arb_irq_domain_ops, pmic_arb);
--
2.34.1
^ permalink raw reply related
* [PATCH v7 4/6] spmi: pmic-arb: Make core resources acquiring a version operation
From: Abel Vesa @ 2024-03-29 18:54 UTC (permalink / raw)
To: Stephen Boyd, Matthias Brugger, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, Neil Armstrong, AngeloGioacchino Del Regno,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Srini Kandagatla, Johan Hovold, linux-kernel, linux-arm-kernel,
linux-arm-msm, linux-mediatek, devicetree, Abel Vesa
In-Reply-To: <20240329-spmi-multi-master-support-v7-0-7b902824246c@linaro.org>
Rather than setting up the core, obsrv and chnls in probe by using
version specific conditionals, add a dedicated "get_core_resources"
version specific op and move the acquiring in there. Since there are
no current users of the second bus yet, drop the comment about why
devm_platform_ioremap_resource can't be used in case of "core",
as it is not applicable anymore.
Don't switch to devm_platform_ioremap_resource though as we need
to keep track of core size.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
drivers/spmi/spmi-pmic-arb.c | 113 +++++++++++++++++++++++++++----------------
1 file changed, 70 insertions(+), 43 deletions(-)
diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
index 38fed8a585fe..188252bfb95f 100644
--- a/drivers/spmi/spmi-pmic-arb.c
+++ b/drivers/spmi/spmi-pmic-arb.c
@@ -203,6 +203,7 @@ struct spmi_pmic_arb {
*/
struct pmic_arb_ver_ops {
const char *ver_str;
+ int (*get_core_resources)(struct platform_device *pdev, void __iomem *core);
int (*init_apid)(struct spmi_pmic_arb *pmic_arb, int index);
int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
/* spmi commands (read_cmd, write_cmd, cmd) functionality */
@@ -956,6 +957,19 @@ static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb *pmic_arb)
return 0;
}
+static int pmic_arb_get_core_resources_v1(struct platform_device *pdev,
+ void __iomem *core)
+{
+ struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);
+
+ pmic_arb->wr_base = core;
+ pmic_arb->rd_base = core;
+
+ pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS;
+
+ return 0;
+}
+
static int pmic_arb_init_apid_v1(struct spmi_pmic_arb *pmic_arb, int index)
{
u32 *mapping_table;
@@ -1063,6 +1077,33 @@ static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
return apid;
}
+static int pmic_arb_get_obsrvr_chnls_v2(struct platform_device *pdev)
+{
+ struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);
+
+ pmic_arb->rd_base = devm_platform_ioremap_resource_byname(pdev, "obsrvr");
+ if (IS_ERR(pmic_arb->rd_base))
+ return PTR_ERR(pmic_arb->rd_base);
+
+ pmic_arb->wr_base = devm_platform_ioremap_resource_byname(pdev, "chnls");
+ if (IS_ERR(pmic_arb->wr_base))
+ return PTR_ERR(pmic_arb->wr_base);
+
+ return 0;
+}
+
+static int pmic_arb_get_core_resources_v2(struct platform_device *pdev,
+ void __iomem *core)
+{
+ struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);
+
+ pmic_arb->core = core;
+
+ pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS;
+
+ return pmic_arb_get_obsrvr_chnls_v2(pdev);
+}
+
static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
{
u16 apid_valid;
@@ -1246,6 +1287,18 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
return offset;
}
+static int pmic_arb_get_core_resources_v7(struct platform_device *pdev,
+ void __iomem *core)
+{
+ struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);
+
+ pmic_arb->core = core;
+
+ pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V7;
+
+ return pmic_arb_get_obsrvr_chnls_v2(pdev);
+}
+
/*
* Only v7 supports 2 buses. Each bus will get a different apid count, read
* from different registers.
@@ -1469,6 +1522,7 @@ pmic_arb_apid_owner_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
static const struct pmic_arb_ver_ops pmic_arb_v1 = {
.ver_str = "v1",
+ .get_core_resources = pmic_arb_get_core_resources_v1,
.init_apid = pmic_arb_init_apid_v1,
.ppid_to_apid = pmic_arb_ppid_to_apid_v1,
.non_data_cmd = pmic_arb_non_data_cmd_v1,
@@ -1484,6 +1538,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v1 = {
static const struct pmic_arb_ver_ops pmic_arb_v2 = {
.ver_str = "v2",
+ .get_core_resources = pmic_arb_get_core_resources_v2,
.init_apid = pmic_arb_init_apid_v1,
.ppid_to_apid = pmic_arb_ppid_to_apid_v2,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
@@ -1499,6 +1554,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v2 = {
static const struct pmic_arb_ver_ops pmic_arb_v3 = {
.ver_str = "v3",
+ .get_core_resources = pmic_arb_get_core_resources_v2,
.init_apid = pmic_arb_init_apid_v1,
.ppid_to_apid = pmic_arb_ppid_to_apid_v2,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
@@ -1514,6 +1570,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v3 = {
static const struct pmic_arb_ver_ops pmic_arb_v5 = {
.ver_str = "v5",
+ .get_core_resources = pmic_arb_get_core_resources_v2,
.init_apid = pmic_arb_init_apid_v5,
.ppid_to_apid = pmic_arb_ppid_to_apid_v5,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
@@ -1529,6 +1586,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v5 = {
static const struct pmic_arb_ver_ops pmic_arb_v7 = {
.ver_str = "v7",
+ .get_core_resources = pmic_arb_get_core_resources_v7,
.init_apid = pmic_arb_init_apid_v7,
.ppid_to_apid = pmic_arb_ppid_to_apid_v5,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
@@ -1565,16 +1623,6 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
pmic_arb = spmi_controller_get_drvdata(ctrl);
pmic_arb->spmic = ctrl;
- /*
- * Please don't replace this with devm_platform_ioremap_resource() or
- * devm_ioremap_resource(). These both result in a call to
- * devm_request_mem_region() which prevents multiple mappings of this
- * register address range. SoCs with PMIC arbiter v7 may define two
- * arbiter devices, for the two physical SPMI interfaces, which share
- * some register address ranges (i.e. "core", "obsrvr", and "chnls").
- * Ensure that both devices probe successfully by calling devm_ioremap()
- * which does not result in a devm_request_mem_region() call.
- */
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
core = devm_ioremap(&ctrl->dev, res->start, resource_size(res));
if (IS_ERR(core))
@@ -1584,44 +1632,23 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
- if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
+ if (hw_ver < PMIC_ARB_VERSION_V2_MIN)
pmic_arb->ver_ops = &pmic_arb_v1;
- pmic_arb->wr_base = core;
- pmic_arb->rd_base = core;
- } else {
- pmic_arb->core = core;
-
- if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
- pmic_arb->ver_ops = &pmic_arb_v2;
- else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
- pmic_arb->ver_ops = &pmic_arb_v3;
- else if (hw_ver < PMIC_ARB_VERSION_V7_MIN)
- pmic_arb->ver_ops = &pmic_arb_v5;
- else
- pmic_arb->ver_ops = &pmic_arb_v7;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "obsrvr");
- pmic_arb->rd_base = devm_ioremap(&ctrl->dev, res->start,
- resource_size(res));
- if (IS_ERR(pmic_arb->rd_base))
- return PTR_ERR(pmic_arb->rd_base);
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "chnls");
- pmic_arb->wr_base = devm_ioremap(&ctrl->dev, res->start,
- resource_size(res));
- if (IS_ERR(pmic_arb->wr_base))
- return PTR_ERR(pmic_arb->wr_base);
- }
+ else if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
+ pmic_arb->ver_ops = &pmic_arb_v2;
+ else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
+ pmic_arb->ver_ops = &pmic_arb_v3;
+ else if (hw_ver < PMIC_ARB_VERSION_V7_MIN)
+ pmic_arb->ver_ops = &pmic_arb_v5;
+ else
+ pmic_arb->ver_ops = &pmic_arb_v7;
dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
pmic_arb->ver_ops->ver_str, hw_ver);
- if (hw_ver < PMIC_ARB_VERSION_V7_MIN)
- pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS;
- else
- pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V7;
+ err = pmic_arb->ver_ops->get_core_resources(pdev, core);
+ if (err)
+ return err;
err = pmic_arb->ver_ops->init_apid(pmic_arb, 0);
if (err)
--
2.34.1
^ permalink raw reply related
* [PATCH v7 5/6] spmi: pmic-arb: Register controller for bus instead of arbiter
From: Abel Vesa @ 2024-03-29 18:54 UTC (permalink / raw)
To: Stephen Boyd, Matthias Brugger, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, Neil Armstrong, AngeloGioacchino Del Regno,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Srini Kandagatla, Johan Hovold, linux-kernel, linux-arm-kernel,
linux-arm-msm, linux-mediatek, devicetree, Abel Vesa
In-Reply-To: <20240329-spmi-multi-master-support-v7-0-7b902824246c@linaro.org>
Introduce the bus object in order to decouple the resources
that are bus specific from the arbiter. This way the SPMI controller
is registered with the generic framework at a bus level rather than
arbiter. This is needed in order to prepare for multi bus support.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
drivers/spmi/spmi-pmic-arb.c | 703 +++++++++++++++++++++++--------------------
1 file changed, 372 insertions(+), 331 deletions(-)
diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
index 188252bfb95f..19ff8665f3d9 100644
--- a/drivers/spmi/spmi-pmic-arb.c
+++ b/drivers/spmi/spmi-pmic-arb.c
@@ -13,6 +13,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spmi.h>
@@ -125,58 +126,72 @@ struct apid_data {
u8 irq_ee;
};
+struct spmi_pmic_arb;
+
/**
- * struct spmi_pmic_arb - SPMI PMIC Arbiter object
+ * struct spmi_pmic_arb_bus - SPMI PMIC Arbiter Bus object
*
- * @rd_base: on v1 "core", on v2 "observer" register base off DT.
- * @wr_base: on v1 "core", on v2 "chnls" register base off DT.
+ * @pmic_arb: the SPMI PMIC Arbiter the bus belongs to.
+ * @domain: irq domain object for PMIC IRQ domain
* @intr: address of the SPMI interrupt control registers.
* @cnfg: address of the PMIC Arbiter configuration registers.
- * @lock: lock to synchronize accesses.
- * @channel: execution environment channel to use for accesses.
- * @irq: PMIC ARB interrupt.
- * @ee: the current Execution Environment
- * @bus_instance: on v7: 0 = primary SPMI bus, 1 = secondary SPMI bus
- * @min_apid: minimum APID (used for bounding IRQ search)
- * @max_apid: maximum APID
+ * @spmic: spmi controller registered for this bus
* @base_apid: on v7: minimum APID associated with the particular SPMI
* bus instance
* @apid_count: on v5 and v7: number of APIDs associated with the
* particular SPMI bus instance
* @mapping_table: in-memory copy of PPID -> APID mapping table.
- * @domain: irq domain object for PMIC IRQ domain
- * @spmic: SPMI controller object
- * @ver_ops: version dependent operations.
+ * @mapping_table_valid:bitmap containing valid-only periphs.
* @ppid_to_apid: in-memory copy of PPID -> APID mapping table.
* @last_apid: Highest value APID in use
* @apid_data: Table of data for all APIDs
+ * @min_apid: minimum APID (used for bounding IRQ search)
+ * @max_apid: maximum APID
+ * @irq: PMIC ARB interrupt.
+ */
+struct spmi_pmic_arb_bus {
+ struct spmi_pmic_arb *pmic_arb;
+ struct irq_domain *domain;
+ void __iomem *intr;
+ void __iomem *cnfg;
+ struct spmi_controller *spmic;
+ u16 base_apid;
+ int apid_count;
+ u32 *mapping_table;
+ DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
+ u16 *ppid_to_apid;
+ u16 last_apid;
+ struct apid_data *apid_data;
+ u16 min_apid;
+ u16 max_apid;
+ int irq;
+};
+
+/**
+ * struct spmi_pmic_arb - SPMI PMIC Arbiter object
+ *
+ * @rd_base: on v1 "core", on v2 "observer" register base off DT.
+ * @wr_base: on v1 "core", on v2 "chnls" register base off DT.
+ * @core: core register base for v2 and above only (see above)
+ * @core_size: core register base size
+ * @lock: lock to synchronize accesses.
+ * @channel: execution environment channel to use for accesses.
+ * @ee: the current Execution Environment
+ * @ver_ops: version dependent operations.
* @max_periphs: Number of elements in apid_data[]
+ * @bus: per arbiter bus instance
*/
struct spmi_pmic_arb {
void __iomem *rd_base;
void __iomem *wr_base;
- void __iomem *intr;
- void __iomem *cnfg;
void __iomem *core;
resource_size_t core_size;
raw_spinlock_t lock;
u8 channel;
- int irq;
u8 ee;
- u32 bus_instance;
- u16 min_apid;
- u16 max_apid;
- u16 base_apid;
- int apid_count;
- u32 *mapping_table;
- DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
- struct irq_domain *domain;
- struct spmi_controller *spmic;
const struct pmic_arb_ver_ops *ver_ops;
- u16 *ppid_to_apid;
- u16 last_apid;
- struct apid_data *apid_data;
int max_periphs;
+ struct spmi_pmic_arb_bus *bus;
};
/**
@@ -204,21 +219,21 @@ struct spmi_pmic_arb {
struct pmic_arb_ver_ops {
const char *ver_str;
int (*get_core_resources)(struct platform_device *pdev, void __iomem *core);
- int (*init_apid)(struct spmi_pmic_arb *pmic_arb, int index);
- int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
+ int (*init_apid)(struct spmi_pmic_arb_bus *bus);
+ int (*ppid_to_apid)(struct spmi_pmic_arb_bus *bus, u16 ppid);
/* spmi commands (read_cmd, write_cmd, cmd) functionality */
- int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
- enum pmic_arb_channel ch_type);
+ int (*offset)(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type);
u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
/* Interrupts controller functionality (offset of PIC registers) */
- void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
+ void __iomem *(*owner_acc_status)(struct spmi_pmic_arb_bus *bus, u8 m,
u16 n);
- void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
- void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
- void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
+ void __iomem *(*acc_enable)(struct spmi_pmic_arb_bus *bus, u16 n);
+ void __iomem *(*irq_status)(struct spmi_pmic_arb_bus *bus, u16 n);
+ void __iomem *(*irq_clear)(struct spmi_pmic_arb_bus *bus, u16 n);
u32 (*apid_map_offset)(u16 n);
- void __iomem *(*apid_owner)(struct spmi_pmic_arb *pmic_arb, u16 n);
+ void __iomem *(*apid_owner)(struct spmi_pmic_arb_bus *bus, u16 n);
};
static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
@@ -235,6 +250,7 @@ static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
/**
* pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
+ * @pmic_arb: the SPMI PMIC arbiter
* @bc: byte count -1. range: 0..3
* @reg: register's address
* @buf: output parameter, length must be bc + 1
@@ -249,6 +265,7 @@ pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
/**
* pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register
+ * @pmic_arb: the SPMI PMIC arbiter
* @bc: byte-count -1. range: 0..3.
* @reg: register's address.
* @buf: buffer to write. length must be bc + 1.
@@ -266,13 +283,14 @@ static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
void __iomem *base, u8 sid, u16 addr,
enum pmic_arb_channel ch_type)
{
- struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u32 status = 0;
u32 timeout = PMIC_ARB_TIMEOUT_US;
u32 offset;
int rc;
- rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
+ rc = pmic_arb->ver_ops->offset(bus, sid, addr, ch_type);
if (rc < 0)
return rc;
@@ -315,13 +333,14 @@ static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
static int
pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
{
- struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
unsigned long flags;
u32 cmd;
int rc;
u32 offset;
- rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
+ rc = pmic_arb->ver_ops->offset(bus, sid, 0, PMIC_ARB_CHANNEL_RW);
if (rc < 0)
return rc;
@@ -357,20 +376,21 @@ static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
}
-static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, u8 sid,
+static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb_bus *bus, u8 opc, u8 sid,
u16 addr, size_t len, u32 *cmd, u32 *offset)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u8 bc = len - 1;
int rc;
- rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
+ rc = pmic_arb->ver_ops->offset(bus, sid, addr,
PMIC_ARB_CHANNEL_OBS);
if (rc < 0)
return rc;
*offset = rc;
if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
- dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
+ dev_err(&bus->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
PMIC_ARB_MAX_TRANS_BYTES, len);
return -EINVAL;
}
@@ -394,7 +414,8 @@ static int pmic_arb_read_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
u32 offset, u8 sid, u16 addr, u8 *buf,
size_t len)
{
- struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u8 bc = len - 1;
int rc;
@@ -416,12 +437,13 @@ static int pmic_arb_read_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
u16 addr, u8 *buf, size_t len)
{
- struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
unsigned long flags;
u32 cmd, offset;
int rc;
- rc = pmic_arb_fmt_read_cmd(pmic_arb, opc, sid, addr, len, &cmd,
+ rc = pmic_arb_fmt_read_cmd(bus, opc, sid, addr, len, &cmd,
&offset);
if (rc)
return rc;
@@ -433,21 +455,22 @@ static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
return rc;
}
-static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc,
+static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb_bus *bus, u8 opc,
u8 sid, u16 addr, size_t len, u32 *cmd,
u32 *offset)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u8 bc = len - 1;
int rc;
- rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
+ rc = pmic_arb->ver_ops->offset(bus, sid, addr,
PMIC_ARB_CHANNEL_RW);
if (rc < 0)
return rc;
*offset = rc;
if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
- dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
+ dev_err(&bus->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
PMIC_ARB_MAX_TRANS_BYTES, len);
return -EINVAL;
}
@@ -473,7 +496,8 @@ static int pmic_arb_write_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
u32 offset, u8 sid, u16 addr,
const u8 *buf, size_t len)
{
- struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u8 bc = len - 1;
/* Write data to FIFOs */
@@ -492,12 +516,13 @@ static int pmic_arb_write_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
u16 addr, const u8 *buf, size_t len)
{
- struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
unsigned long flags;
u32 cmd, offset;
int rc;
- rc = pmic_arb_fmt_write_cmd(pmic_arb, opc, sid, addr, len, &cmd,
+ rc = pmic_arb_fmt_write_cmd(bus, opc, sid, addr, len, &cmd,
&offset);
if (rc)
return rc;
@@ -513,18 +538,19 @@ static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
static int pmic_arb_masked_write(struct spmi_controller *ctrl, u8 sid, u16 addr,
const u8 *buf, const u8 *mask, size_t len)
{
- struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u32 read_cmd, read_offset, write_cmd, write_offset;
u8 temp[PMIC_ARB_MAX_TRANS_BYTES];
unsigned long flags;
int rc, i;
- rc = pmic_arb_fmt_read_cmd(pmic_arb, SPMI_CMD_EXT_READL, sid, addr, len,
+ rc = pmic_arb_fmt_read_cmd(bus, SPMI_CMD_EXT_READL, sid, addr, len,
&read_cmd, &read_offset);
if (rc)
return rc;
- rc = pmic_arb_fmt_write_cmd(pmic_arb, SPMI_CMD_EXT_WRITEL, sid, addr,
+ rc = pmic_arb_fmt_write_cmd(bus, SPMI_CMD_EXT_WRITEL, sid, addr,
len, &write_cmd, &write_offset);
if (rc)
return rc;
@@ -567,25 +593,25 @@ struct spmi_pmic_arb_qpnpint_type {
static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
size_t len)
{
- struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);
u8 sid = hwirq_to_sid(d->hwirq);
u8 per = hwirq_to_per(d->hwirq);
- if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
+ if (pmic_arb_write_cmd(bus->spmic, SPMI_CMD_EXT_WRITEL, sid,
(per << 8) + reg, buf, len))
- dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
+ dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x\n",
d->irq);
}
static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
{
- struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);
u8 sid = hwirq_to_sid(d->hwirq);
u8 per = hwirq_to_per(d->hwirq);
- if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
+ if (pmic_arb_read_cmd(bus->spmic, SPMI_CMD_EXT_READL, sid,
(per << 8) + reg, buf, len))
- dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
+ dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x\n",
d->irq);
}
@@ -593,47 +619,49 @@ static int qpnpint_spmi_masked_write(struct irq_data *d, u8 reg,
const void *buf, const void *mask,
size_t len)
{
- struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);
u8 sid = hwirq_to_sid(d->hwirq);
u8 per = hwirq_to_per(d->hwirq);
int rc;
- rc = pmic_arb_masked_write(pmic_arb->spmic, sid, (per << 8) + reg, buf,
+ rc = pmic_arb_masked_write(bus->spmic, sid, (per << 8) + reg, buf,
mask, len);
if (rc)
- dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x rc=%d\n",
+ dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x rc=%d\n",
d->irq, rc);
return rc;
}
-static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
+static void cleanup_irq(struct spmi_pmic_arb_bus *bus, u16 apid, int id)
{
- u16 ppid = pmic_arb->apid_data[apid].ppid;
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
+ u16 ppid = bus->apid_data[apid].ppid;
u8 sid = ppid >> 8;
u8 per = ppid & 0xFF;
u8 irq_mask = BIT(id);
- dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n",
- __func__, apid, sid, per, id);
- writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
+ dev_err_ratelimited(&bus->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n",
+ __func__, apid, sid, per, id);
+ writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(bus, apid));
}
-static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
+static int periph_interrupt(struct spmi_pmic_arb_bus *bus, u16 apid)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
unsigned int irq;
u32 status, id;
int handled = 0;
- u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
- u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
+ u8 sid = (bus->apid_data[apid].ppid >> 8) & 0xF;
+ u8 per = bus->apid_data[apid].ppid & 0xFF;
- status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
+ status = readl_relaxed(pmic_arb->ver_ops->irq_status(bus, apid));
while (status) {
id = ffs(status) - 1;
status &= ~BIT(id);
- irq = irq_find_mapping(pmic_arb->domain,
- spec_to_hwirq(sid, per, id, apid));
+ irq = irq_find_mapping(bus->domain,
+ spec_to_hwirq(sid, per, id, apid));
if (irq == 0) {
- cleanup_irq(pmic_arb, apid, id);
+ cleanup_irq(bus, apid, id);
continue;
}
generic_handle_irq(irq);
@@ -645,16 +673,17 @@ static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
static void pmic_arb_chained_irq(struct irq_desc *desc)
{
- struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
+ struct spmi_pmic_arb_bus *bus = irq_desc_get_handler_data(desc);
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
struct irq_chip *chip = irq_desc_get_chip(desc);
- int first = pmic_arb->min_apid;
- int last = pmic_arb->max_apid;
+ int first = bus->min_apid;
+ int last = bus->max_apid;
/*
* acc_offset will be non-zero for the secondary SPMI bus instance on
* v7 controllers.
*/
- int acc_offset = pmic_arb->base_apid >> 5;
+ int acc_offset = bus->base_apid >> 5;
u8 ee = pmic_arb->ee;
u32 status, enable, handled = 0;
int i, id, apid;
@@ -665,7 +694,7 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
chained_irq_enter(chip, desc);
for (i = first >> 5; i <= last >> 5; ++i) {
- status = readl_relaxed(ver_ops->owner_acc_status(pmic_arb, ee, i - acc_offset));
+ status = readl_relaxed(ver_ops->owner_acc_status(bus, ee, i - acc_offset));
if (status)
acc_valid = true;
@@ -679,9 +708,9 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
continue;
}
enable = readl_relaxed(
- ver_ops->acc_enable(pmic_arb, apid));
+ ver_ops->acc_enable(bus, apid));
if (enable & SPMI_PIC_ACC_ENABLE_BIT)
- if (periph_interrupt(pmic_arb, apid) != 0)
+ if (periph_interrupt(bus, apid) != 0)
handled++;
}
}
@@ -690,19 +719,19 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
if (!acc_valid) {
for (i = first; i <= last; i++) {
/* skip if APPS is not irq owner */
- if (pmic_arb->apid_data[i].irq_ee != pmic_arb->ee)
+ if (bus->apid_data[i].irq_ee != pmic_arb->ee)
continue;
irq_status = readl_relaxed(
- ver_ops->irq_status(pmic_arb, i));
+ ver_ops->irq_status(bus, i));
if (irq_status) {
enable = readl_relaxed(
- ver_ops->acc_enable(pmic_arb, i));
+ ver_ops->acc_enable(bus, i));
if (enable & SPMI_PIC_ACC_ENABLE_BIT) {
- dev_dbg(&pmic_arb->spmic->dev,
+ dev_dbg(&bus->spmic->dev,
"Dispatching IRQ for apid=%d status=%x\n",
i, irq_status);
- if (periph_interrupt(pmic_arb, i) != 0)
+ if (periph_interrupt(bus, i) != 0)
handled++;
}
}
@@ -717,12 +746,13 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
static void qpnpint_irq_ack(struct irq_data *d)
{
- struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u8 irq = hwirq_to_irq(d->hwirq);
u16 apid = hwirq_to_apid(d->hwirq);
u8 data;
- writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
+ writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(bus, apid));
data = BIT(irq);
qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
@@ -738,14 +768,15 @@ static void qpnpint_irq_mask(struct irq_data *d)
static void qpnpint_irq_unmask(struct irq_data *d)
{
- struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
u8 irq = hwirq_to_irq(d->hwirq);
u16 apid = hwirq_to_apid(d->hwirq);
u8 buf[2];
writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
- ver_ops->acc_enable(pmic_arb, apid));
+ ver_ops->acc_enable(bus, apid));
qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
if (!(buf[0] & BIT(irq))) {
@@ -802,9 +833,9 @@ static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)
{
- struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);
- return irq_set_irq_wake(pmic_arb->irq, on);
+ return irq_set_irq_wake(bus->irq, on);
}
static int qpnpint_get_irqchip_state(struct irq_data *d,
@@ -826,17 +857,18 @@ static int qpnpint_get_irqchip_state(struct irq_data *d,
static int qpnpint_irq_domain_activate(struct irq_domain *domain,
struct irq_data *d, bool reserve)
{
- struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
+ struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u16 periph = hwirq_to_per(d->hwirq);
u16 apid = hwirq_to_apid(d->hwirq);
u16 sid = hwirq_to_sid(d->hwirq);
u16 irq = hwirq_to_irq(d->hwirq);
u8 buf;
- if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
- dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
+ if (bus->apid_data[apid].irq_ee != pmic_arb->ee) {
+ dev_err(&bus->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
sid, periph, irq, pmic_arb->ee,
- pmic_arb->apid_data[apid].irq_ee);
+ bus->apid_data[apid].irq_ee);
return -ENODEV;
}
@@ -863,15 +895,16 @@ static int qpnpint_irq_domain_translate(struct irq_domain *d,
unsigned long *out_hwirq,
unsigned int *out_type)
{
- struct spmi_pmic_arb *pmic_arb = d->host_data;
+ struct spmi_pmic_arb_bus *bus = d->host_data;
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u32 *intspec = fwspec->param;
u16 apid, ppid;
int rc;
- dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
+ dev_dbg(&bus->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
intspec[0], intspec[1], intspec[2]);
- if (irq_domain_get_of_node(d) != pmic_arb->spmic->dev.of_node)
+ if (irq_domain_get_of_node(d) != bus->spmic->dev.of_node)
return -EINVAL;
if (fwspec->param_count != 4)
return -EINVAL;
@@ -879,37 +912,37 @@ static int qpnpint_irq_domain_translate(struct irq_domain *d,
return -EINVAL;
ppid = intspec[0] << 8 | intspec[1];
- rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
+ rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid);
if (rc < 0) {
- dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
- intspec[0], intspec[1], intspec[2], rc);
+ dev_err(&bus->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
+ intspec[0], intspec[1], intspec[2], rc);
return rc;
}
apid = rc;
/* Keep track of {max,min}_apid for bounding search during interrupt */
- if (apid > pmic_arb->max_apid)
- pmic_arb->max_apid = apid;
- if (apid < pmic_arb->min_apid)
- pmic_arb->min_apid = apid;
+ if (apid > bus->max_apid)
+ bus->max_apid = apid;
+ if (apid < bus->min_apid)
+ bus->min_apid = apid;
*out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);
*out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
- dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
+ dev_dbg(&bus->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
return 0;
}
static struct lock_class_key qpnpint_irq_lock_class, qpnpint_irq_request_class;
-static void qpnpint_irq_domain_map(struct spmi_pmic_arb *pmic_arb,
+static void qpnpint_irq_domain_map(struct spmi_pmic_arb_bus *bus,
struct irq_domain *domain, unsigned int virq,
irq_hw_number_t hwirq, unsigned int type)
{
irq_flow_handler_t handler;
- dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n",
+ dev_dbg(&bus->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n",
virq, hwirq, type);
if (type & IRQ_TYPE_EDGE_BOTH)
@@ -920,7 +953,7 @@ static void qpnpint_irq_domain_map(struct spmi_pmic_arb *pmic_arb,
irq_set_lockdep_class(virq, &qpnpint_irq_lock_class,
&qpnpint_irq_request_class);
- irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, pmic_arb,
+ irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, bus,
handler, NULL, NULL);
}
@@ -928,7 +961,7 @@ static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
unsigned int virq, unsigned int nr_irqs,
void *data)
{
- struct spmi_pmic_arb *pmic_arb = domain->host_data;
+ struct spmi_pmic_arb_bus *bus = domain->host_data;
struct irq_fwspec *fwspec = data;
irq_hw_number_t hwirq;
unsigned int type;
@@ -939,20 +972,22 @@ static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
return ret;
for (i = 0; i < nr_irqs; i++)
- qpnpint_irq_domain_map(pmic_arb, domain, virq + i, hwirq + i,
+ qpnpint_irq_domain_map(bus, domain, virq + i, hwirq + i,
type);
return 0;
}
-static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb *pmic_arb)
+static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb_bus *bus)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
+
/*
* Initialize max_apid/min_apid to the opposite bounds, during
* the irq domain translation, we are sure to update these
*/
- pmic_arb->max_apid = 0;
- pmic_arb->min_apid = pmic_arb->max_periphs - 1;
+ bus->max_apid = 0;
+ bus->min_apid = pmic_arb->max_periphs - 1;
return 0;
}
@@ -970,43 +1005,38 @@ static int pmic_arb_get_core_resources_v1(struct platform_device *pdev,
return 0;
}
-static int pmic_arb_init_apid_v1(struct spmi_pmic_arb *pmic_arb, int index)
+static int pmic_arb_init_apid_v1(struct spmi_pmic_arb_bus *bus)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u32 *mapping_table;
- if (index) {
- dev_err(&pmic_arb->spmic->dev, "Unsupported buses count %d detected\n",
- index);
- return -EINVAL;
- }
-
- mapping_table = devm_kcalloc(&pmic_arb->spmic->dev, pmic_arb->max_periphs,
+ mapping_table = devm_kcalloc(&bus->spmic->dev, pmic_arb->max_periphs,
sizeof(*mapping_table), GFP_KERNEL);
if (!mapping_table)
return -ENOMEM;
- pmic_arb->mapping_table = mapping_table;
+ bus->mapping_table = mapping_table;
- return pmic_arb_init_apid_min_max(pmic_arb);
+ return pmic_arb_init_apid_min_max(bus);
}
-static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
+static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb_bus *bus, u16 ppid)
{
- u32 *mapping_table = pmic_arb->mapping_table;
+ u32 *mapping_table = bus->mapping_table;
int index = 0, i;
u16 apid_valid;
u16 apid;
u32 data;
- apid_valid = pmic_arb->ppid_to_apid[ppid];
+ apid_valid = bus->ppid_to_apid[ppid];
if (apid_valid & PMIC_ARB_APID_VALID) {
apid = apid_valid & ~PMIC_ARB_APID_VALID;
return apid;
}
for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
- if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
- mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
+ if (!test_and_set_bit(index, bus->mapping_table_valid))
+ mapping_table[index] = readl_relaxed(bus->cnfg +
SPMI_MAPPING_TABLE_REG(index));
data = mapping_table[index];
@@ -1016,9 +1046,9 @@ static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
} else {
apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
- pmic_arb->ppid_to_apid[ppid]
+ bus->ppid_to_apid[ppid]
= apid | PMIC_ARB_APID_VALID;
- pmic_arb->apid_data[apid].ppid = ppid;
+ bus->apid_data[apid].ppid = ppid;
return apid;
}
} else {
@@ -1026,9 +1056,9 @@ static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
} else {
apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
- pmic_arb->ppid_to_apid[ppid]
+ bus->ppid_to_apid[ppid]
= apid | PMIC_ARB_APID_VALID;
- pmic_arb->apid_data[apid].ppid = ppid;
+ bus->apid_data[apid].ppid = ppid;
return apid;
}
}
@@ -1038,24 +1068,26 @@ static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
}
/* v1 offset per ee */
-static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
- enum pmic_arb_channel ch_type)
+static int pmic_arb_offset_v1(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
return 0x800 + 0x80 * pmic_arb->channel;
}
-static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
+static u16 pmic_arb_find_apid(struct spmi_pmic_arb_bus *bus, u16 ppid)
{
- struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
+ struct apid_data *apidd = &bus->apid_data[bus->last_apid];
u32 regval, offset;
u16 id, apid;
- for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
+ for (apid = bus->last_apid; ; apid++, apidd++) {
offset = pmic_arb->ver_ops->apid_map_offset(apid);
if (offset >= pmic_arb->core_size)
break;
- regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb,
+ regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus,
apid));
apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
apidd->write_ee = apidd->irq_ee;
@@ -1065,14 +1097,14 @@ static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
continue;
id = (regval >> 8) & PMIC_ARB_PPID_MASK;
- pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
+ bus->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
apidd->ppid = id;
if (id == ppid) {
apid |= PMIC_ARB_APID_VALID;
break;
}
}
- pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
+ bus->last_apid = apid & ~PMIC_ARB_APID_VALID;
return apid;
}
@@ -1104,21 +1136,22 @@ static int pmic_arb_get_core_resources_v2(struct platform_device *pdev,
return pmic_arb_get_obsrvr_chnls_v2(pdev);
}
-static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
+static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb_bus *bus, u16 ppid)
{
u16 apid_valid;
- apid_valid = pmic_arb->ppid_to_apid[ppid];
+ apid_valid = bus->ppid_to_apid[ppid];
if (!(apid_valid & PMIC_ARB_APID_VALID))
- apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
+ apid_valid = pmic_arb_find_apid(bus, ppid);
if (!(apid_valid & PMIC_ARB_APID_VALID))
return -ENODEV;
return apid_valid & ~PMIC_ARB_APID_VALID;
}
-static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
+static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
struct apid_data *apidd;
struct apid_data *prev_apidd;
u16 i, apid, ppid, apid_max;
@@ -1140,9 +1173,9 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
* where N = number of APIDs supported by the primary bus and
* M = number of APIDs supported by the secondary bus
*/
- apidd = &pmic_arb->apid_data[pmic_arb->base_apid];
- apid_max = pmic_arb->base_apid + pmic_arb->apid_count;
- for (i = pmic_arb->base_apid; i < apid_max; i++, apidd++) {
+ apidd = &bus->apid_data[bus->base_apid];
+ apid_max = bus->base_apid + bus->apid_count;
+ for (i = bus->base_apid; i < apid_max; i++, apidd++) {
offset = pmic_arb->ver_ops->apid_map_offset(i);
if (offset >= pmic_arb->core_size)
break;
@@ -1153,19 +1186,18 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
- regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb,
- i));
+ regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus, i));
apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
- valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
- apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
- prev_apidd = &pmic_arb->apid_data[apid];
+ valid = bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
+ apid = bus->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
+ prev_apidd = &bus->apid_data[apid];
if (!valid || apidd->write_ee == pmic_arb->ee) {
/* First PPID mapping or one for this EE */
- pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
+ bus->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
} else if (valid && is_irq_ee &&
prev_apidd->write_ee == pmic_arb->ee) {
/*
@@ -1176,42 +1208,43 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
}
apidd->ppid = ppid;
- pmic_arb->last_apid = i;
+ bus->last_apid = i;
}
/* Dump the mapping table for debug purposes. */
- dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
+ dev_dbg(&bus->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
- apid = pmic_arb->ppid_to_apid[ppid];
+ apid = bus->ppid_to_apid[ppid];
if (apid & PMIC_ARB_APID_VALID) {
apid &= ~PMIC_ARB_APID_VALID;
- apidd = &pmic_arb->apid_data[apid];
- dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
- ppid, apid, apidd->write_ee, apidd->irq_ee);
+ apidd = &bus->apid_data[apid];
+ dev_dbg(&bus->spmic->dev, "%#03X %3u %2u %2u\n",
+ ppid, apid, apidd->write_ee, apidd->irq_ee);
}
}
return 0;
}
-static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
+static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb_bus *bus, u16 ppid)
{
- if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
+ if (!(bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
return -ENODEV;
- return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
+ return bus->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
}
/* v2 offset per ppid and per ee */
-static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
- enum pmic_arb_channel ch_type)
+static int pmic_arb_offset_v2(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u16 apid;
u16 ppid;
int rc;
ppid = sid << 8 | ((addr >> 8) & 0xFF);
- rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
+ rc = pmic_arb_ppid_to_apid_v2(bus, ppid);
if (rc < 0)
return rc;
@@ -1219,33 +1252,28 @@ static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
return 0x1000 * pmic_arb->ee + 0x8000 * apid;
}
-static int pmic_arb_init_apid_v5(struct spmi_pmic_arb *pmic_arb, int index)
+static int pmic_arb_init_apid_v5(struct spmi_pmic_arb_bus *bus)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
int ret;
- if (index) {
- dev_err(&pmic_arb->spmic->dev, "Unsupported buses count %d detected\n",
- index);
- return -EINVAL;
- }
-
- pmic_arb->base_apid = 0;
- pmic_arb->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
+ bus->base_apid = 0;
+ bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
PMIC_ARB_FEATURES_PERIPH_MASK;
- if (pmic_arb->base_apid + pmic_arb->apid_count > pmic_arb->max_periphs) {
- dev_err(&pmic_arb->spmic->dev, "Unsupported APID count %d detected\n",
- pmic_arb->base_apid + pmic_arb->apid_count);
+ if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) {
+ dev_err(&bus->spmic->dev, "Unsupported APID count %d detected\n",
+ bus->base_apid + bus->apid_count);
return -EINVAL;
}
- ret = pmic_arb_init_apid_min_max(pmic_arb);
+ ret = pmic_arb_init_apid_min_max(bus);
if (ret)
return ret;
- ret = pmic_arb_read_apid_map_v5(pmic_arb);
+ ret = pmic_arb_read_apid_map_v5(bus);
if (ret) {
- dev_err(&pmic_arb->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n",
+ dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n",
ret);
return ret;
}
@@ -1257,15 +1285,16 @@ static int pmic_arb_init_apid_v5(struct spmi_pmic_arb *pmic_arb, int index)
* v5 offset per ee and per apid for observer channels and per apid for
* read/write channels.
*/
-static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
- enum pmic_arb_channel ch_type)
+static int pmic_arb_offset_v5(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u16 apid;
int rc;
u32 offset = 0;
u16 ppid = (sid << 8) | (addr >> 8);
- rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
+ rc = pmic_arb_ppid_to_apid_v5(bus, ppid);
if (rc < 0)
return rc;
@@ -1275,8 +1304,8 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
break;
case PMIC_ARB_CHANNEL_RW:
- if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) {
- dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
+ if (bus->apid_data[apid].write_ee != pmic_arb->ee) {
+ dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
sid, addr);
return -EPERM;
}
@@ -1299,62 +1328,20 @@ static int pmic_arb_get_core_resources_v7(struct platform_device *pdev,
return pmic_arb_get_obsrvr_chnls_v2(pdev);
}
-/*
- * Only v7 supports 2 buses. Each bus will get a different apid count, read
- * from different registers.
- */
-static int pmic_arb_init_apid_v7(struct spmi_pmic_arb *pmic_arb, int index)
-{
- int ret;
-
- if (index == 0) {
- pmic_arb->base_apid = 0;
- pmic_arb->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
- PMIC_ARB_FEATURES_PERIPH_MASK;
- } else if (index == 1) {
- pmic_arb->base_apid = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
- PMIC_ARB_FEATURES_PERIPH_MASK;
- pmic_arb->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES1) &
- PMIC_ARB_FEATURES_PERIPH_MASK;
- } else {
- dev_err(&pmic_arb->spmic->dev, "Unsupported buses count %d detected\n",
- index);
- return -EINVAL;
- }
-
- if (pmic_arb->base_apid + pmic_arb->apid_count > pmic_arb->max_periphs) {
- dev_err(&pmic_arb->spmic->dev, "Unsupported APID count %d detected\n",
- pmic_arb->base_apid + pmic_arb->apid_count);
- return -EINVAL;
- }
-
- ret = pmic_arb_init_apid_min_max(pmic_arb);
- if (ret)
- return ret;
-
- ret = pmic_arb_read_apid_map_v5(pmic_arb);
- if (ret) {
- dev_err(&pmic_arb->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n",
- ret);
- return ret;
- }
-
- return 0;
-}
-
/*
* v7 offset per ee and per apid for observer channels and per apid for
* read/write channels.
*/
-static int pmic_arb_offset_v7(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
- enum pmic_arb_channel ch_type)
+static int pmic_arb_offset_v7(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,
+ enum pmic_arb_channel ch_type)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u16 apid;
int rc;
u32 offset = 0;
u16 ppid = (sid << 8) | (addr >> 8);
- rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
+ rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid);
if (rc < 0)
return rc;
@@ -1364,8 +1351,8 @@ static int pmic_arb_offset_v7(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
offset = 0x8000 * pmic_arb->ee + 0x20 * apid;
break;
case PMIC_ARB_CHANNEL_RW:
- if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) {
- dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
+ if (bus->apid_data[apid].write_ee != pmic_arb->ee) {
+ dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
sid, addr);
return -EPERM;
}
@@ -1387,104 +1374,110 @@ static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
}
static void __iomem *
-pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb_bus *bus, u8 m, u16 n)
{
- return pmic_arb->intr + 0x20 * m + 0x4 * n;
+ return bus->intr + 0x20 * m + 0x4 * n;
}
static void __iomem *
-pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb_bus *bus, u8 m, u16 n)
{
- return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
+ return bus->intr + 0x100000 + 0x1000 * m + 0x4 * n;
}
static void __iomem *
-pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb_bus *bus, u8 m, u16 n)
{
- return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
+ return bus->intr + 0x200000 + 0x1000 * m + 0x4 * n;
}
static void __iomem *
-pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb_bus *bus, u8 m, u16 n)
{
- return pmic_arb->intr + 0x10000 * m + 0x4 * n;
+ return bus->intr + 0x10000 * m + 0x4 * n;
}
static void __iomem *
-pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
+pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb_bus *bus, u8 m, u16 n)
{
- return pmic_arb->intr + 0x1000 * m + 0x4 * n;
+ return bus->intr + 0x1000 * m + 0x4 * n;
}
static void __iomem *
-pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_acc_enable_v1(struct spmi_pmic_arb_bus *bus, u16 n)
{
- return pmic_arb->intr + 0x200 + 0x4 * n;
+ return bus->intr + 0x200 + 0x4 * n;
}
static void __iomem *
-pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_acc_enable_v2(struct spmi_pmic_arb_bus *bus, u16 n)
{
- return pmic_arb->intr + 0x1000 * n;
+ return bus->intr + 0x1000 * n;
}
static void __iomem *
-pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_acc_enable_v5(struct spmi_pmic_arb_bus *bus, u16 n)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
return pmic_arb->wr_base + 0x100 + 0x10000 * n;
}
static void __iomem *
-pmic_arb_acc_enable_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_acc_enable_v7(struct spmi_pmic_arb_bus *bus, u16 n)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
return pmic_arb->wr_base + 0x100 + 0x1000 * n;
}
static void __iomem *
-pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_irq_status_v1(struct spmi_pmic_arb_bus *bus, u16 n)
{
- return pmic_arb->intr + 0x600 + 0x4 * n;
+ return bus->intr + 0x600 + 0x4 * n;
}
static void __iomem *
-pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_irq_status_v2(struct spmi_pmic_arb_bus *bus, u16 n)
{
- return pmic_arb->intr + 0x4 + 0x1000 * n;
+ return bus->intr + 0x4 + 0x1000 * n;
}
static void __iomem *
-pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_irq_status_v5(struct spmi_pmic_arb_bus *bus, u16 n)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
return pmic_arb->wr_base + 0x104 + 0x10000 * n;
}
static void __iomem *
-pmic_arb_irq_status_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_irq_status_v7(struct spmi_pmic_arb_bus *bus, u16 n)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
return pmic_arb->wr_base + 0x104 + 0x1000 * n;
}
static void __iomem *
-pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_irq_clear_v1(struct spmi_pmic_arb_bus *bus, u16 n)
{
- return pmic_arb->intr + 0xA00 + 0x4 * n;
+ return bus->intr + 0xA00 + 0x4 * n;
}
static void __iomem *
-pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_irq_clear_v2(struct spmi_pmic_arb_bus *bus, u16 n)
{
- return pmic_arb->intr + 0x8 + 0x1000 * n;
+ return bus->intr + 0x8 + 0x1000 * n;
}
static void __iomem *
-pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_irq_clear_v5(struct spmi_pmic_arb_bus *bus, u16 n)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
return pmic_arb->wr_base + 0x108 + 0x10000 * n;
}
static void __iomem *
-pmic_arb_irq_clear_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_irq_clear_v7(struct spmi_pmic_arb_bus *bus, u16 n)
{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
return pmic_arb->wr_base + 0x108 + 0x1000 * n;
}
@@ -1504,9 +1497,9 @@ static u32 pmic_arb_apid_map_offset_v7(u16 n)
}
static void __iomem *
-pmic_arb_apid_owner_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_apid_owner_v2(struct spmi_pmic_arb_bus *bus, u16 n)
{
- return pmic_arb->cnfg + 0x700 + 0x4 * n;
+ return bus->cnfg + 0x700 + 0x4 * n;
}
/*
@@ -1515,9 +1508,9 @@ pmic_arb_apid_owner_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
* 0.
*/
static void __iomem *
-pmic_arb_apid_owner_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
+pmic_arb_apid_owner_v7(struct spmi_pmic_arb_bus *bus, u16 n)
{
- return pmic_arb->cnfg + 0x4 * (n - pmic_arb->base_apid);
+ return bus->cnfg + 0x4 * (n - bus->base_apid);
}
static const struct pmic_arb_ver_ops pmic_arb_v1 = {
@@ -1587,7 +1580,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v5 = {
static const struct pmic_arb_ver_ops pmic_arb_v7 = {
.ver_str = "v7",
.get_core_resources = pmic_arb_get_core_resources_v7,
- .init_apid = pmic_arb_init_apid_v7,
+ .init_apid = pmic_arb_init_apid_v5,
.ppid_to_apid = pmic_arb_ppid_to_apid_v5,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
.offset = pmic_arb_offset_v7,
@@ -1607,29 +1600,120 @@ static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
.translate = qpnpint_irq_domain_translate,
};
+static int spmi_pmic_arb_bus_init(struct platform_device *pdev,
+ struct device_node *node,
+ struct spmi_pmic_arb *pmic_arb)
+{
+ struct spmi_pmic_arb_bus *bus;
+ struct device *dev = &pdev->dev;
+ struct spmi_controller *ctrl;
+ void __iomem *intr;
+ void __iomem *cnfg;
+ int index, ret;
+ u32 irq;
+
+ ctrl = devm_spmi_controller_alloc(dev, sizeof(*bus));
+ if (IS_ERR(ctrl))
+ return PTR_ERR(ctrl);
+
+ ctrl->cmd = pmic_arb_cmd;
+ ctrl->read_cmd = pmic_arb_read_cmd;
+ ctrl->write_cmd = pmic_arb_write_cmd;
+
+ bus = spmi_controller_get_drvdata(ctrl);
+
+ pmic_arb->bus = bus;
+
+ bus->ppid_to_apid = devm_kcalloc(dev, PMIC_ARB_MAX_PPID,
+ sizeof(*bus->ppid_to_apid),
+ GFP_KERNEL);
+ if (!bus->ppid_to_apid)
+ return -ENOMEM;
+
+ bus->apid_data = devm_kcalloc(dev, pmic_arb->max_periphs,
+ sizeof(*bus->apid_data),
+ GFP_KERNEL);
+ if (!bus->apid_data)
+ return -ENOMEM;
+
+ index = of_property_match_string(node, "reg-names", "cnfg");
+ if (index < 0) {
+ dev_err(dev, "cnfg reg region missing");
+ return -EINVAL;
+ }
+
+ cnfg = devm_of_iomap(dev, node, index, NULL);
+ if (IS_ERR(cnfg))
+ return PTR_ERR(cnfg);
+
+ index = of_property_match_string(node, "reg-names", "intr");
+ if (index < 0) {
+ dev_err(dev, "intr reg region missing");
+ return -EINVAL;
+ }
+
+ intr = devm_of_iomap(dev, node, index, NULL);
+ if (IS_ERR(intr))
+ return PTR_ERR(intr);
+
+ irq = of_irq_get_byname(node, "periph_irq");
+ if (irq < 0)
+ return irq;
+
+ bus->pmic_arb = pmic_arb;
+ bus->intr = intr;
+ bus->cnfg = cnfg;
+ bus->irq = irq;
+ bus->spmic = ctrl;
+
+ ret = pmic_arb->ver_ops->init_apid(bus);
+ if (ret)
+ return ret;
+
+ dev_dbg(&pdev->dev, "adding irq domain\n");
+
+ bus->domain = irq_domain_add_tree(dev->of_node,
+ &pmic_arb_irq_domain_ops, bus);
+ if (!bus->domain) {
+ dev_err(&pdev->dev, "unable to create irq_domain\n");
+ return -ENOMEM;
+ }
+
+ irq_set_chained_handler_and_data(bus->irq,
+ pmic_arb_chained_irq, bus);
+
+ ctrl->dev.of_node = node;
+
+ ret = devm_spmi_controller_add(dev, ctrl);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int spmi_pmic_arb_probe(struct platform_device *pdev)
{
struct spmi_pmic_arb *pmic_arb;
- struct spmi_controller *ctrl;
+ struct device *dev = &pdev->dev;
struct resource *res;
void __iomem *core;
u32 channel, ee, hw_ver;
int err;
- ctrl = devm_spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
- if (IS_ERR(ctrl))
- return PTR_ERR(ctrl);
-
- pmic_arb = spmi_controller_get_drvdata(ctrl);
- pmic_arb->spmic = ctrl;
+ pmic_arb = devm_kzalloc(dev, sizeof(*pmic_arb), GFP_KERNEL);
+ if (!pmic_arb)
+ return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
- core = devm_ioremap(&ctrl->dev, res->start, resource_size(res));
+ core = devm_ioremap(dev, res->start, resource_size(res));
if (IS_ERR(core))
return PTR_ERR(core);
pmic_arb->core_size = resource_size(res);
+ platform_set_drvdata(pdev, pmic_arb);
+ raw_spin_lock_init(&pmic_arb->lock);
+
hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
if (hw_ver < PMIC_ARB_VERSION_V2_MIN)
@@ -1643,30 +1727,12 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
else
pmic_arb->ver_ops = &pmic_arb_v7;
- dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
- pmic_arb->ver_ops->ver_str, hw_ver);
-
err = pmic_arb->ver_ops->get_core_resources(pdev, core);
if (err)
return err;
- err = pmic_arb->ver_ops->init_apid(pmic_arb, 0);
- if (err)
- return err;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
- pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
- if (IS_ERR(pmic_arb->intr))
- return PTR_ERR(pmic_arb->intr);
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg");
- pmic_arb->cnfg = devm_ioremap_resource(&ctrl->dev, res);
- if (IS_ERR(pmic_arb->cnfg))
- return PTR_ERR(pmic_arb->cnfg);
-
- pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
- if (pmic_arb->irq < 0)
- return pmic_arb->irq;
+ dev_info(dev, "PMIC arbiter version %s (0x%x)\n",
+ pmic_arb->ver_ops->ver_str, hw_ver);
err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
if (err) {
@@ -1695,42 +1761,17 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
pmic_arb->ee = ee;
- platform_set_drvdata(pdev, ctrl);
- raw_spin_lock_init(&pmic_arb->lock);
-
- ctrl->cmd = pmic_arb_cmd;
- ctrl->read_cmd = pmic_arb_read_cmd;
- ctrl->write_cmd = pmic_arb_write_cmd;
-
- dev_dbg(&pdev->dev, "adding irq domain\n");
- pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
- &pmic_arb_irq_domain_ops, pmic_arb);
- if (!pmic_arb->domain) {
- dev_err(&pdev->dev, "unable to create irq_domain\n");
- return -ENOMEM;
- }
-
- irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq,
- pmic_arb);
- err = spmi_controller_add(ctrl);
- if (err)
- goto err_domain_remove;
-
- return 0;
-
-err_domain_remove:
- irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
- irq_domain_remove(pmic_arb->domain);
- return err;
+ return spmi_pmic_arb_bus_init(pdev, dev->of_node, pmic_arb);
}
static void spmi_pmic_arb_remove(struct platform_device *pdev)
{
- struct spmi_controller *ctrl = platform_get_drvdata(pdev);
- struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
- spmi_controller_remove(ctrl);
- irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
- irq_domain_remove(pmic_arb->domain);
+ struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);
+ struct spmi_pmic_arb_bus *bus = pmic_arb->bus;
+
+ irq_set_chained_handler_and_data(bus->irq,
+ NULL, NULL);
+ irq_domain_remove(bus->domain);
}
static const struct of_device_id spmi_pmic_arb_match_table[] = {
--
2.34.1
^ permalink raw reply related
* [PATCH v7 6/6] spmi: pmic-arb: Add multi bus support
From: Abel Vesa @ 2024-03-29 18:54 UTC (permalink / raw)
To: Stephen Boyd, Matthias Brugger, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, Neil Armstrong, AngeloGioacchino Del Regno,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Srini Kandagatla, Johan Hovold, linux-kernel, linux-arm-kernel,
linux-arm-msm, linux-mediatek, devicetree, Abel Vesa
In-Reply-To: <20240329-spmi-multi-master-support-v7-0-7b902824246c@linaro.org>
Starting with HW version 7, there are actually two separate buses
(with two separate sets of wires). So add support for the second bus.
The first platform that needs this support for the second bus is the
Qualcomm X1 Elite, so add the compatible for it as well.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
drivers/spmi/spmi-pmic-arb.c | 138 +++++++++++++++++++++++++++++++++++++------
1 file changed, 120 insertions(+), 18 deletions(-)
diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
index 19ff8665f3d9..56f2b3190d82 100644
--- a/drivers/spmi/spmi-pmic-arb.c
+++ b/drivers/spmi/spmi-pmic-arb.c
@@ -13,6 +13,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@@ -95,6 +96,8 @@ enum pmic_arb_channel {
PMIC_ARB_CHANNEL_OBS,
};
+#define PMIC_ARB_MAX_BUSES 2
+
/* Maximum number of support PMIC peripherals */
#define PMIC_ARB_MAX_PERIPHS 512
#define PMIC_ARB_MAX_PERIPHS_V7 1024
@@ -148,6 +151,7 @@ struct spmi_pmic_arb;
* @min_apid: minimum APID (used for bounding IRQ search)
* @max_apid: maximum APID
* @irq: PMIC ARB interrupt.
+ * @id: unique ID of the bus
*/
struct spmi_pmic_arb_bus {
struct spmi_pmic_arb *pmic_arb;
@@ -165,6 +169,7 @@ struct spmi_pmic_arb_bus {
u16 min_apid;
u16 max_apid;
int irq;
+ u8 id;
};
/**
@@ -179,7 +184,8 @@ struct spmi_pmic_arb_bus {
* @ee: the current Execution Environment
* @ver_ops: version dependent operations.
* @max_periphs: Number of elements in apid_data[]
- * @bus: per arbiter bus instance
+ * @buses: per arbiter buses instances
+ * @buses_available: number of buses registered
*/
struct spmi_pmic_arb {
void __iomem *rd_base;
@@ -191,7 +197,8 @@ struct spmi_pmic_arb {
u8 ee;
const struct pmic_arb_ver_ops *ver_ops;
int max_periphs;
- struct spmi_pmic_arb_bus *bus;
+ struct spmi_pmic_arb_bus *buses[PMIC_ARB_MAX_BUSES];
+ int buses_available;
};
/**
@@ -219,7 +226,7 @@ struct spmi_pmic_arb {
struct pmic_arb_ver_ops {
const char *ver_str;
int (*get_core_resources)(struct platform_device *pdev, void __iomem *core);
- int (*init_apid)(struct spmi_pmic_arb_bus *bus);
+ int (*init_apid)(struct spmi_pmic_arb_bus *bus, int index);
int (*ppid_to_apid)(struct spmi_pmic_arb_bus *bus, u16 ppid);
/* spmi commands (read_cmd, write_cmd, cmd) functionality */
int (*offset)(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,
@@ -308,8 +315,8 @@ static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
}
if (status & PMIC_ARB_STATUS_FAILURE) {
- dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x)\n",
- __func__, sid, addr, status);
+ dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x) reg: 0x%x\n",
+ __func__, sid, addr, status, offset);
WARN_ON(1);
return -EIO;
}
@@ -325,8 +332,8 @@ static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
udelay(1);
}
- dev_err(&ctrl->dev, "%s: %#x %#x: timeout, status %#x\n",
- __func__, sid, addr, status);
+ dev_err(&ctrl->dev, "%s: %#x %#x %#x: timeout, status %#x\n",
+ __func__, bus->id, sid, addr, status);
return -ETIMEDOUT;
}
@@ -1005,11 +1012,17 @@ static int pmic_arb_get_core_resources_v1(struct platform_device *pdev,
return 0;
}
-static int pmic_arb_init_apid_v1(struct spmi_pmic_arb_bus *bus)
+static int pmic_arb_init_apid_v1(struct spmi_pmic_arb_bus *bus, int index)
{
struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
u32 *mapping_table;
+ if (index) {
+ dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n",
+ index);
+ return -EINVAL;
+ }
+
mapping_table = devm_kcalloc(&bus->spmic->dev, pmic_arb->max_periphs,
sizeof(*mapping_table), GFP_KERNEL);
if (!mapping_table)
@@ -1252,11 +1265,17 @@ static int pmic_arb_offset_v2(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,
return 0x1000 * pmic_arb->ee + 0x8000 * apid;
}
-static int pmic_arb_init_apid_v5(struct spmi_pmic_arb_bus *bus)
+static int pmic_arb_init_apid_v5(struct spmi_pmic_arb_bus *bus, int index)
{
struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
int ret;
+ if (index) {
+ dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n",
+ index);
+ return -EINVAL;
+ }
+
bus->base_apid = 0;
bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
PMIC_ARB_FEATURES_PERIPH_MASK;
@@ -1328,6 +1347,50 @@ static int pmic_arb_get_core_resources_v7(struct platform_device *pdev,
return pmic_arb_get_obsrvr_chnls_v2(pdev);
}
+/*
+ * Only v7 supports 2 buses. Each bus will get a different apid count, read
+ * from different registers.
+ */
+static int pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index)
+{
+ struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
+ int ret;
+
+ if (index == 0) {
+ bus->base_apid = 0;
+ bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
+ PMIC_ARB_FEATURES_PERIPH_MASK;
+ } else if (index == 1) {
+ bus->base_apid = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
+ PMIC_ARB_FEATURES_PERIPH_MASK;
+ bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES1) &
+ PMIC_ARB_FEATURES_PERIPH_MASK;
+ } else {
+ dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n",
+ bus->id);
+ return -EINVAL;
+ }
+
+ if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) {
+ dev_err(&bus->spmic->dev, "Unsupported APID count %d detected\n",
+ bus->base_apid + bus->apid_count);
+ return -EINVAL;
+ }
+
+ ret = pmic_arb_init_apid_min_max(bus);
+ if (ret)
+ return ret;
+
+ ret = pmic_arb_read_apid_map_v5(bus);
+ if (ret) {
+ dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n",
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
/*
* v7 offset per ee and per apid for observer channels and per apid for
* read/write channels.
@@ -1580,7 +1643,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v5 = {
static const struct pmic_arb_ver_ops pmic_arb_v7 = {
.ver_str = "v7",
.get_core_resources = pmic_arb_get_core_resources_v7,
- .init_apid = pmic_arb_init_apid_v5,
+ .init_apid = pmic_arb_init_apid_v7,
.ppid_to_apid = pmic_arb_ppid_to_apid_v5,
.non_data_cmd = pmic_arb_non_data_cmd_v2,
.offset = pmic_arb_offset_v7,
@@ -1604,6 +1667,7 @@ static int spmi_pmic_arb_bus_init(struct platform_device *pdev,
struct device_node *node,
struct spmi_pmic_arb *pmic_arb)
{
+ int bus_index = pmic_arb->buses_available;
struct spmi_pmic_arb_bus *bus;
struct device *dev = &pdev->dev;
struct spmi_controller *ctrl;
@@ -1622,7 +1686,7 @@ static int spmi_pmic_arb_bus_init(struct platform_device *pdev,
bus = spmi_controller_get_drvdata(ctrl);
- pmic_arb->bus = bus;
+ pmic_arb->buses[bus_index] = bus;
bus->ppid_to_apid = devm_kcalloc(dev, PMIC_ARB_MAX_PPID,
sizeof(*bus->ppid_to_apid),
@@ -1665,12 +1729,13 @@ static int spmi_pmic_arb_bus_init(struct platform_device *pdev,
bus->cnfg = cnfg;
bus->irq = irq;
bus->spmic = ctrl;
+ bus->id = bus_index;
- ret = pmic_arb->ver_ops->init_apid(bus);
+ ret = pmic_arb->ver_ops->init_apid(bus, bus_index);
if (ret)
return ret;
- dev_dbg(&pdev->dev, "adding irq domain\n");
+ dev_dbg(&pdev->dev, "adding irq domain for bus %d\n", bus_index);
bus->domain = irq_domain_add_tree(dev->of_node,
&pmic_arb_irq_domain_ops, bus);
@@ -1683,14 +1748,53 @@ static int spmi_pmic_arb_bus_init(struct platform_device *pdev,
pmic_arb_chained_irq, bus);
ctrl->dev.of_node = node;
+ dev_set_name(&ctrl->dev, "spmi-%d", bus_index);
ret = devm_spmi_controller_add(dev, ctrl);
if (ret)
return ret;
+ pmic_arb->buses_available++;
+
return 0;
}
+static int spmi_pmic_arb_register_buses(struct spmi_pmic_arb *pmic_arb,
+ struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ struct device_node *child;
+ int ret;
+
+ /* legacy mode doesn't provide child node for the bus */
+ if (of_device_is_compatible(node, "qcom,spmi-pmic-arb"))
+ return spmi_pmic_arb_bus_init(pdev, node, pmic_arb);
+
+ for_each_available_child_of_node(node, child) {
+ if (of_node_name_eq(child, "spmi")) {
+ ret = spmi_pmic_arb_bus_init(pdev, child, pmic_arb);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static void spmi_pmic_arb_deregister_buses(struct spmi_pmic_arb *pmic_arb)
+{
+ int i;
+
+ for (i = 0; i < PMIC_ARB_MAX_BUSES; i++) {
+ struct spmi_pmic_arb_bus *bus = pmic_arb->buses[i];
+
+ irq_set_chained_handler_and_data(bus->irq,
+ NULL, NULL);
+ irq_domain_remove(bus->domain);
+ }
+}
+
static int spmi_pmic_arb_probe(struct platform_device *pdev)
{
struct spmi_pmic_arb *pmic_arb;
@@ -1761,21 +1865,19 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
pmic_arb->ee = ee;
- return spmi_pmic_arb_bus_init(pdev, dev->of_node, pmic_arb);
+ return spmi_pmic_arb_register_buses(pmic_arb, pdev);
}
static void spmi_pmic_arb_remove(struct platform_device *pdev)
{
struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);
- struct spmi_pmic_arb_bus *bus = pmic_arb->bus;
- irq_set_chained_handler_and_data(bus->irq,
- NULL, NULL);
- irq_domain_remove(bus->domain);
+ spmi_pmic_arb_deregister_buses(pmic_arb);
}
static const struct of_device_id spmi_pmic_arb_match_table[] = {
{ .compatible = "qcom,spmi-pmic-arb", },
+ { .compatible = "qcom,x1e80100-spmi-pmic-arb", },
{},
};
MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v6 3/4] firmware: arm_scmi: Add SCMI v3.2 pincontrol protocol basic support
From: Andy Shevchenko @ 2024-03-29 19:00 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Linus Walleij, Dan Carpenter, linux-arm-kernel,
linux-kernel, devicetree, linux-gpio, Peng Fan, Oleksii Moisieiev
In-Reply-To: <20240323-pinctrl-scmi-v6-3-a895243257c0@nxp.com>
Sat, Mar 23, 2024 at 08:15:16PM +0800, Peng Fan (OSS) kirjoitti:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add basic implementation of the SCMI v3.2 pincontrol protocol.
...
> scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_VIRTIO) += virtio.o
> scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_OPTEE) += optee.o
> scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o system.o voltage.o powercap.o
Actually you want to have := here.
> +scmi-protocols-y += pinctrl.o
> scmi-module-objs := $(scmi-driver-y) $(scmi-protocols-y) $(scmi-transport-y)
Side note: The -objs has to be -y
...
> +#include <linux/module.h>
> +#include <linux/scmi_protocol.h>
> +#include <linux/slab.h>
This is semi-random list of headers. Please, follow IWYU principle
(include what you use). There are a lot of inclusions I see missing
(just in the context of this page I see bits.h, types.h, and
asm/byteorder.h).
...
> +enum scmi_pinctrl_protocol_cmd {
> + PINCTRL_ATTRIBUTES = 0x3,
> + PINCTRL_LIST_ASSOCIATIONS = 0x4,
> + PINCTRL_SETTINGS_GET = 0x5,
> + PINCTRL_SETTINGS_CONFIGURE = 0x6,
> + PINCTRL_REQUEST = 0x7,
> + PINCTRL_RELEASE = 0x8,
> + PINCTRL_NAME_GET = 0x9,
> + PINCTRL_SET_PERMISSIONS = 0xa
Leave trailing comma as it's not a termination.
> +};
...
> +static int scmi_pinctrl_attributes_get(const struct scmi_protocol_handle *ph,
> + struct scmi_pinctrl_info *pi)
> +{
> + int ret;
> + struct scmi_xfer *t;
> + struct scmi_msg_pinctrl_protocol_attributes *attr;
> +
> + ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES, 0, sizeof(*attr),
> + &t);
This looks much better on a single line.
> + if (ret)
> + return ret;
> +
> + attr = t->rx.buf;
> +
> + ret = ph->xops->do_xfer(ph, t);
> + if (!ret) {
> + pi->nr_functions = GET_FUNCTIONS_NR(attr->attributes_high);
> + pi->nr_groups = GET_GROUPS_NR(attr->attributes_low);
> + pi->nr_pins = GET_PINS_NR(attr->attributes_low);
> + }
> +
> + ph->xops->xfer_put(ph, t);
> + return ret;
> +}
...
> + ret = ph->xops->xfer_get_init(ph, PINCTRL_ATTRIBUTES, sizeof(*tx),
> + sizeof(*rx), &t);
Possible to have on a single line (if you use relaxed 100 limit).
Or (re)split it more logically:
ret = ph->xops->xfer_get_init(ph, PINCTRL_ATTRIBUTES,
sizeof(*tx), sizeof(*rx), &t);
> + if (ret)
> + return ret;
...
> + /*
> + * If supported overwrite short name with the extended one;
> + * on error just carry on and use already provided short name.
> + */
> + if (!ret && ext_name_flag)
Please, use standard pattern, i.e.
if (ret)
return ret;
> + ph->hops->extended_name_get(ph, PINCTRL_NAME_GET, selector,
> + (u32 *)&type, name,
Why is an explicit casting needed?
> + SCMI_MAX_STR_SIZE);
> + return ret;
...
> + iter = ph->hops->iter_response_init(ph, &ops, size,
> + PINCTRL_LIST_ASSOCIATIONS,
> + sizeof(struct scmi_msg_pinctrl_list_assoc),
> + &ipriv);
> +
Redundant blank line.
> + if (IS_ERR(iter))
> + return PTR_ERR(iter);
...
> + if (p->flag == 1)
> + attributes |= FIELD_PREP(SKIP_CONFIGS_MASK, desc_index);
> + else if (!p->flag)
Be consistent, i.e. if (p->flag == 0)
> + attributes |= FIELD_PREP(CONFIG_TYPE_MASK, p->config_types[0]);
...
> + st->num_remaining = le32_get_bits(r->num_configs,
> + GENMASK(31, 24));
One line?
...
> + if (!p->flag) {
> + if (p->config_types[0] !=
> + le32_get_bits(r->configs[st->loop_idx * 2], GENMASK(7, 0)))
> + return -EINVAL;
> + } else if (p->flag == 1) {
> + p->config_types[st->desc_index + st->loop_idx] =
> + le32_get_bits(r->configs[st->loop_idx * 2],
> + GENMASK(7, 0));
With a temporary variable for r->configs[st->loop_idx * 2] the above can be
written in much better way.
> + } else if (p->flag == 2) {
> + return 0;
> + }
> + p->config_values[st->desc_index + st->loop_idx] =
> + le32_to_cpu(r->configs[st->loop_idx * 2 + 1]);
For the sake of consistency with the above suggestion also temporary for next
config value.
...
> + iter = ph->hops->iter_response_init(ph, &ops, 1, PINCTRL_SETTINGS_GET,
> + sizeof(struct scmi_msg_settings_get),
> + &ipriv);
> +
Redundant blank line.
> + if (IS_ERR(iter))
> + return PTR_ERR(iter);
...
> +static int scmi_pinctrl_get_group_info(const struct scmi_protocol_handle *ph,
> + u32 selector,
> + struct scmi_group_info *group)
> +{
> + int ret;
> + if (!group)
> + return -EINVAL;
When the above is not a dead code?
> + ret = scmi_pinctrl_attributes(ph, GROUP_TYPE, selector,
> + group->name,
> + &group->nr_pins);
> + if (ret)
> + return ret;
> +
> + if (!group->nr_pins) {
> + dev_err(ph->dev, "Group %d has 0 elements", selector);
> + return -ENODATA;
> + }
> +
> + group->group_pins = kmalloc_array(group->nr_pins,
> + sizeof(*group->group_pins),
> + GFP_KERNEL);
> + if (!group->group_pins)
> + return -ENOMEM;
> +
> + ret = scmi_pinctrl_list_associations(ph, selector, GROUP_TYPE,
> + group->nr_pins, group->group_pins);
> + if (ret) {
> + kfree(group->group_pins);
> + return ret;
> + }
> +
> + group->present = true;
> + return 0;
> +}
...
> + ret = scmi_pinctrl_get_group_info(ph, selector,
> + &pi->groups[selector]);
One line?
> + if (ret)
> + return ret;
...
> + ret = scmi_pinctrl_attributes(ph, FUNCTION_TYPE, selector,
> + func->name,
> + &func->nr_groups);
At least last two lines can be joined.
> + if (ret)
> + return ret;
...
> + ret = scmi_pinctrl_attributes(ph, PIN_TYPE, selector,
> + pin->name, NULL);
It's pleany of room on the previous line.
> + if (ret)
> + return ret;
...
> + ret = scmi_pinctrl_get_pin_info(ph, selector,
> + &pi->pins[selector]);
Ditto.
> + if (ret)
> + return ret;
...
> +static int scmi_pinctrl_protocol_init(const struct scmi_protocol_handle *ph)
> +{
> + int ret;
> + u32 version;
> + struct scmi_pinctrl_info *pinfo;
> +
> + ret = ph->xops->version_get(ph, &version);
> + if (ret)
> + return ret;
> +
> + dev_dbg(ph->dev, "Pinctrl Version %d.%d\n",
> + PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version));
> +
> + pinfo = devm_kzalloc(ph->dev, sizeof(*pinfo), GFP_KERNEL);
Huh?!
Please, get yourself familiar with the scope of devm APIs.
> + if (!pinfo)
> + return -ENOMEM;
> +
> + ret = scmi_pinctrl_attributes_get(ph, pinfo);
> + if (ret)
> + return ret;
> +
> + pinfo->pins = devm_kcalloc(ph->dev, pinfo->nr_pins,
> + sizeof(*pinfo->pins),
> + GFP_KERNEL);
> + if (!pinfo->pins)
> + return -ENOMEM;
> +
> + pinfo->groups = devm_kcalloc(ph->dev, pinfo->nr_groups,
> + sizeof(*pinfo->groups),
> + GFP_KERNEL);
> + if (!pinfo->groups)
> + return -ENOMEM;
> +
> + pinfo->functions = devm_kcalloc(ph->dev, pinfo->nr_functions,
> + sizeof(*pinfo->functions),
> + GFP_KERNEL);
> + if (!pinfo->functions)
> + return -ENOMEM;
> +
> + pinfo->version = version;
> +
> + return ph->set_priv(ph, pinfo, version);
> +}
> +
> +static int scmi_pinctrl_protocol_deinit(const struct scmi_protocol_handle *ph)
> +{
> + int i;
> + struct scmi_pinctrl_info *pi = ph->get_priv(ph);
> +
> + for (i = 0; i < pi->nr_groups; i++) {
> + if (pi->groups[i].present) {
> + kfree(pi->groups[i].group_pins);
> + pi->groups[i].present = false;
> + }
> + }
> +
> + for (i = 0; i < pi->nr_functions; i++) {
> + if (pi->functions[i].present) {
> + kfree(pi->functions[i].groups);
This is wrong in conjunction with the above.
> + pi->functions[i].present = false;
> + }
> + }
> +
> + return 0;
> +}
...
> +static const struct scmi_protocol scmi_pinctrl = {
> + .id = SCMI_PROTOCOL_PINCTRL,
> + .owner = THIS_MODULE,
> + .instance_init = &scmi_pinctrl_protocol_init,
> + .instance_deinit = &scmi_pinctrl_protocol_deinit,
> + .ops = &pinctrl_proto_ops,
> + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION,
> +};
> +
Redundant blank line.
> +DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(pinctrl, scmi_pinctrl)
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH 07/10] dt-bindings: iio: dac: add bindings doc for AD9739A
From: David Lechner @ 2024-03-29 19:06 UTC (permalink / raw)
To: nuno.sa
Cc: linux-iio, devicetree, Dragos Bogdan, Jonathan Cameron,
Lars-Peter Clausen, Michael Hennerich, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Olivier Moysan
In-Reply-To: <20240328-iio-backend-axi-dac-v1-7-afc808b3fde3@analog.com>
On Thu, Mar 28, 2024 at 8:23 AM Nuno Sa via B4 Relay
<devnull+nuno.sa.analog.com@kernel.org> wrote:
>
> From: Nuno Sa <nuno.sa@analog.com>
>
> This adds the bindings documentation for the 14 bit
> RF Digital-to-Analog converter.
>
> Signed-off-by: Nuno Sa <nuno.sa@analog.com>
> ---
> .../devicetree/bindings/iio/dac/adi,ad9739a.yaml | 88 ++++++++++++++++++++++
> MAINTAINERS | 8 ++
> 2 files changed, 96 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad9739a.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad9739a.yaml
> new file mode 100644
> index 000000000000..24bcec763a9b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad9739a.yaml
> @@ -0,0 +1,88 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/dac/adi,ad9739a.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices AD9739A RF DAC
> +
> +maintainers:
> + - Dragos Bogdan <dragos.bogdan@analog.com>
> + - Nuno Sa <nuno.sa@analog.com>
> +
> +description: |
> + The AD9739A is a 14-bit, 2.5 GSPS high performance RF DACs that are capable
> + of synthesizing wideband signals from dc up to 3 GHz.
> +
> + https://www.analog.com/media/en/technical-documentation/data-sheets/ad9737a_9739a.pdf
> +
> +properties:
> + compatible:
> + enum:
> + - adi,ad9739a
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
I also see an IRQ pin on the datasheet. Do we need an interrupts
property for that?
> +
> + reset-gpios:
> + maxItems: 1
> +
> + vdd_3_3-supply:
> + description: 3.3V Digital input supply.
vdd33-supply would better match the datasheet name
> +
> + vdd-supply:
> + description: 1.8V Digital input supply.
> +
> + vdda-supply:
> + description: 3.3V Analog input supply.
> +
> + vddc-supply:
> + description: 1.8V Clock input supply.
I see a VREF voltage reference input in the datasheet. Do we need a vref-supply?
^ permalink raw reply
* Re: [PATCH v6 4/4] pinctrl: Implementation of the generic scmi-pinctrl driver
From: Andy Shevchenko @ 2024-03-29 19:10 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Linus Walleij, Dan Carpenter, linux-arm-kernel,
linux-kernel, devicetree, linux-gpio, Peng Fan, Oleksii Moisieiev
In-Reply-To: <20240323-pinctrl-scmi-v6-4-a895243257c0@nxp.com>
Sat, Mar 23, 2024 at 08:15:17PM +0800, Peng Fan (OSS) kirjoitti:
> From: Peng Fan <peng.fan@nxp.com>
>
> scmi-pinctrl driver implements pinctrl driver interface and using
> SCMI protocol to redirect messages from pinctrl subsystem SDK to
> SCMI platform firmware, which does the changes in HW.
...
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/module.h>
> +#include <linux/seq_file.h>
> +#include <linux/scmi_protocol.h>
> +#include <linux/slab.h>
Use IWYU principle. There are missing header inclusions and/or forward
declarations.
...
> +struct scmi_pinctrl_funcs {
> + unsigned int num_groups;
> + const char **groups;
> +};
This is repeating struct pinfunction. Why can't the latter be used?
...
> +err_free:
> + devm_kfree(pmx->dev, groups);
Why?!
This is 99.9% that the initial allocation must not be devm.
...
> + *p_config_value = kcalloc(num_configs, sizeof(u32), GFP_KERNEL);
sizeof(**p_config_value)?
> + *p_config_type = kcalloc(num_configs,
> + sizeof(enum scmi_pinctrl_conf_type),
sizeof(**p_config_type)?
> + GFP_KERNEL);
> +
> + if (!*p_config_value || !*p_config_type) {
> + kfree(*p_config_value);
> + kfree(*p_config_type);
> + return -ENOMEM;
Why to allocate / free memory in the case when you know that the first one
failed?
> + }
...
> +static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx,
> + struct pinctrl_desc *desc)
> +{
> + struct pinctrl_pin_desc *pins;
> + unsigned int npins;
> + int ret, i;
> +
> + npins = pinctrl_ops->count_get(pmx->ph, PIN_TYPE);
> + pins = devm_kmalloc_array(pmx->dev, npins, sizeof(*pins), GFP_KERNEL);
> + if (!pins)
> + return -ENOMEM;
> +
> + for (i = 0; i < npins; i++) {
> + pins[i].number = i;
> + ret = pinctrl_ops->name_get(pmx->ph, i, PIN_TYPE, &pins[i].name);
> + if (ret)
> + return dev_err_probe(pmx->dev, ret,
> + "Can't get name for pin %d", i);
> + }
> +
> + desc->npins = npins;
> + desc->pins = pins;
> + dev_dbg(pmx->dev, "got pins %d", npins);
%u
> + return 0;
> +}
...
> + pinctrl_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_PINCTRL,
> + &ph);
One line.
> + if (IS_ERR(pinctrl_ops))
> + return PTR_ERR(pinctrl_ops);
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH 09/23] media: i2c: imx258: Add support for running on 2 CSI data lanes
From: Luigi311 @ 2024-03-29 19:10 UTC (permalink / raw)
To: Sakari Ailus
Cc: linux-media, dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, devicetree, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <493be807-819b-4871-a996-cbe0dd020065@luigi311.com>
On 3/28/24 17:42, Luigi311 wrote:
> On 3/28/24 02:19, Sakari Ailus wrote:
>> Hi Luigi311, Dave,
>>
>> On Wed, Mar 27, 2024 at 05:16:55PM -0600, git@luigi311.com wrote:
>>> From: Dave Stevenson <dave.stevenson@raspberrypi.com>
>>>
>>> Extends the driver to also support 2 data lanes.
>>> Frame rates are obviously more restricted on 2 lanes, but some
>>> hardware simply hasn't wired more up.
>>>
>>> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
>>> Signed-off-by: Luigi311 <git@luigi311.com>
>>> ---
>>> drivers/media/i2c/imx258.c | 214 ++++++++++++++++++++++++++++++++-----
>>> 1 file changed, 190 insertions(+), 24 deletions(-)
>>>
>>> diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
>>> index 6ee7de079454..c65b9aad3b0a 100644
>>> --- a/drivers/media/i2c/imx258.c
>>> +++ b/drivers/media/i2c/imx258.c
>>> @@ -86,12 +86,18 @@ struct imx258_reg_list {
>>> const struct imx258_reg *regs;
>>> };
>>>
>>> +enum {
>>> + IMX258_2_LANE_MODE,
>>> + IMX258_4_LANE_MODE,
>>> + IMX258_LANE_CONFIGS,
>>> +};
>>> +
>>> /* Link frequency config */
>>> struct imx258_link_freq_config {
>>> u32 pixels_per_line;
>>>
>>> /* PLL registers for this link frequency */
>>> - struct imx258_reg_list reg_list;
>>> + struct imx258_reg_list reg_list[IMX258_LANE_CONFIGS];
>>> };
>>>
>>> /* Mode : resolution and related config&values */
>>> @@ -111,8 +117,34 @@ struct imx258_mode {
>>> struct imx258_reg_list reg_list;
>>> };
>>>
>>> -/* 4208x3120 needs 1267Mbps/lane, 4 lanes */
>>> -static const struct imx258_reg mipi_1267mbps_19_2mhz[] = {
>>> +/*
>>> + * 4208x3120 @ 30 fps needs 1267Mbps/lane, 4 lanes.
>>> + * To avoid further computation of clock settings, adopt the same per
>>> + * lane data rate when using 2 lanes, thus allowing a maximum of 15fps.
>>> + */
>>> +static const struct imx258_reg mipi_1267mbps_19_2mhz_2l[] = {
>>> + { 0x0136, 0x13 },
>>> + { 0x0137, 0x33 },
>>> + { 0x0301, 0x0A },
>>> + { 0x0303, 0x02 },
>>> + { 0x0305, 0x03 },
>>> + { 0x0306, 0x00 },
>>> + { 0x0307, 0xC6 },
>>> + { 0x0309, 0x0A },
>>> + { 0x030B, 0x01 },
>>> + { 0x030D, 0x02 },
>>> + { 0x030E, 0x00 },
>>> + { 0x030F, 0xD8 },
>>> + { 0x0310, 0x00 },
>>> +
>>> + { 0x0114, 0x01 },
>>> + { 0x0820, 0x09 },
>>> + { 0x0821, 0xa6 },
>>> + { 0x0822, 0x66 },
>>> + { 0x0823, 0x66 },
>>> +};
>>> +
>>> +static const struct imx258_reg mipi_1267mbps_19_2mhz_4l[] = {
>>> { 0x0136, 0x13 },
>>> { 0x0137, 0x33 },
>>> { 0x0301, 0x05 },
>>> @@ -126,16 +158,18 @@ static const struct imx258_reg mipi_1267mbps_19_2mhz[] = {
>>> { 0x030E, 0x00 },
>>> { 0x030F, 0xD8 },
>>> { 0x0310, 0x00 },
>>> +
>>> + { 0x0114, 0x03 },
>>> { 0x0820, 0x13 },
>>> { 0x0821, 0x4C },
>>> { 0x0822, 0xCC },
>>> { 0x0823, 0xCC },
>>> };
>>>
>>> -static const struct imx258_reg mipi_1272mbps_24mhz[] = {
>>> +static const struct imx258_reg mipi_1272mbps_24mhz_2l[] = {
>>> { 0x0136, 0x18 },
>>> { 0x0137, 0x00 },
>>> - { 0x0301, 0x05 },
>>> + { 0x0301, 0x0a },
>>> { 0x0303, 0x02 },
>>> { 0x0305, 0x04 },
>>> { 0x0306, 0x00 },
>>> @@ -146,13 +180,59 @@ static const struct imx258_reg mipi_1272mbps_24mhz[] = {
>>> { 0x030E, 0x00 },
>>> { 0x030F, 0xD8 },
>>> { 0x0310, 0x00 },
>>> +
>>> + { 0x0114, 0x01 },
>>> { 0x0820, 0x13 },
>>> { 0x0821, 0x4C },
>>> { 0x0822, 0xCC },
>>> { 0x0823, 0xCC },
>>> };
>>>
>>> -static const struct imx258_reg mipi_640mbps_19_2mhz[] = {
>>> +static const struct imx258_reg mipi_1272mbps_24mhz_4l[] = {
>>> + { 0x0136, 0x18 },
>>> + { 0x0137, 0x00 },
>>> + { 0x0301, 0x05 },
>>> + { 0x0303, 0x02 },
>>> + { 0x0305, 0x04 },
>>> + { 0x0306, 0x00 },
>>> + { 0x0307, 0xD4 },
>>> + { 0x0309, 0x0A },
>>> + { 0x030B, 0x01 },
>>> + { 0x030D, 0x02 },
>>> + { 0x030E, 0x00 },
>>> + { 0x030F, 0xD8 },
>>> + { 0x0310, 0x00 },
>>> +
>>> + { 0x0114, 0x03 },
>>> + { 0x0820, 0x13 },
>>> + { 0x0821, 0xE0 },
>>> + { 0x0822, 0x00 },
>>> + { 0x0823, 0x00 },
>>> +};
>>> +
>>> +static const struct imx258_reg mipi_640mbps_19_2mhz_2l[] = {
>>> + { 0x0136, 0x13 },
>>> + { 0x0137, 0x33 },
>>> + { 0x0301, 0x05 },
>>> + { 0x0303, 0x02 },
>>> + { 0x0305, 0x03 },
>>> + { 0x0306, 0x00 },
>>> + { 0x0307, 0x64 },
>>> + { 0x0309, 0x0A },
>>> + { 0x030B, 0x01 },
>>> + { 0x030D, 0x02 },
>>> + { 0x030E, 0x00 },
>>> + { 0x030F, 0xD8 },
>>> + { 0x0310, 0x00 },
>>> +
>>> + { 0x0114, 0x01 },
>>> + { 0x0820, 0x05 },
>>> + { 0x0821, 0x00 },
>>> + { 0x0822, 0x00 },
>>> + { 0x0823, 0x00 },
>>> +};
>>> +
>>> +static const struct imx258_reg mipi_640mbps_19_2mhz_4l[] = {
>>> { 0x0136, 0x13 },
>>> { 0x0137, 0x33 },
>>> { 0x0301, 0x05 },
>>> @@ -166,13 +246,37 @@ static const struct imx258_reg mipi_640mbps_19_2mhz[] = {
>>> { 0x030E, 0x00 },
>>> { 0x030F, 0xD8 },
>>> { 0x0310, 0x00 },
>>> +
>>> + { 0x0114, 0x03 },
>>> + { 0x0820, 0x0A },
>>> + { 0x0821, 0x00 },
>>> + { 0x0822, 0x00 },
>>> + { 0x0823, 0x00 },
>>> +};
>>> +
>>> +static const struct imx258_reg mipi_642mbps_24mhz_2l[] = {
>>> + { 0x0136, 0x18 },
>>> + { 0x0137, 0x00 },
>>> + { 0x0301, 0x0A },
>>> + { 0x0303, 0x02 },
>>> + { 0x0305, 0x04 },
>>> + { 0x0306, 0x00 },
>>> + { 0x0307, 0x6B },
>>> + { 0x0309, 0x0A },
>>> + { 0x030B, 0x01 },
>>> + { 0x030D, 0x02 },
>>> + { 0x030E, 0x00 },
>>> + { 0x030F, 0xD8 },
>>> + { 0x0310, 0x00 },
>>> +
>>> + { 0x0114, 0x01 },
>>> { 0x0820, 0x0A },
>>> { 0x0821, 0x00 },
>>> { 0x0822, 0x00 },
>>> { 0x0823, 0x00 },
>>> };
>>>
>>> -static const struct imx258_reg mipi_642mbps_24mhz[] = {
>>> +static const struct imx258_reg mipi_642mbps_24mhz_4l[] = {
>>> { 0x0136, 0x18 },
>>> { 0x0137, 0x00 },
>>> { 0x0301, 0x05 },
>>> @@ -186,6 +290,8 @@ static const struct imx258_reg mipi_642mbps_24mhz[] = {
>>> { 0x030E, 0x00 },
>>> { 0x030F, 0xD8 },
>>> { 0x0310, 0x00 },
>>> +
>>> + { 0x0114, 0x03 },
>>> { 0x0820, 0x0A },
>>> { 0x0821, 0x00 },
>>> { 0x0822, 0x00 },
>>> @@ -240,7 +346,6 @@ static const struct imx258_reg mode_common_regs[] = {
>>> { 0x5F05, 0xED },
>>> { 0x0112, 0x0A },
>>> { 0x0113, 0x0A },
>>> - { 0x0114, 0x03 },
>>> { 0x0342, 0x14 },
>>> { 0x0343, 0xE8 },
>>> { 0x0344, 0x00 },
>>> @@ -359,11 +464,13 @@ enum {
>>>
>>> /*
>>> * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
>>> - * data rate => double data rate; number of lanes => 4; bits per pixel => 10
>>> + * data rate => double data rate;
>>> + * number of lanes => (configurable 2 or 4);
>>> + * bits per pixel => 10
>>> */
>>> -static u64 link_freq_to_pixel_rate(u64 f)
>>> +static u64 link_freq_to_pixel_rate(u64 f, unsigned int nlanes)
>>> {
>>> - f *= 2 * 4;
>>> + f *= 2 * nlanes;
>>> do_div(f, 10);
>>>
>>> return f;
>>> @@ -393,15 +500,27 @@ static const struct imx258_link_freq_config link_freq_configs_19_2[] = {
>>> [IMX258_LINK_FREQ_1267MBPS] = {
>>> .pixels_per_line = IMX258_PPL_DEFAULT,
>>> .reg_list = {
>>> - .num_of_regs = ARRAY_SIZE(mipi_1267mbps_19_2mhz),
>>> - .regs = mipi_1267mbps_19_2mhz,
>>> + [IMX258_2_LANE_MODE] = {
>>> + .num_of_regs = ARRAY_SIZE(mipi_1267mbps_19_2mhz_2l),
>>> + .regs = mipi_1267mbps_19_2mhz_2l,
>>> + },
>>> + [IMX258_4_LANE_MODE] = {
>>> + .num_of_regs = ARRAY_SIZE(mipi_1267mbps_19_2mhz_4l),
>>> + .regs = mipi_1267mbps_19_2mhz_4l,
>>> + },
>>> }
>>> },
>>> [IMX258_LINK_FREQ_640MBPS] = {
>>> .pixels_per_line = IMX258_PPL_DEFAULT,
>>> .reg_list = {
>>> - .num_of_regs = ARRAY_SIZE(mipi_640mbps_19_2mhz),
>>> - .regs = mipi_640mbps_19_2mhz,
>>> + [IMX258_2_LANE_MODE] = {
>>> + .num_of_regs = ARRAY_SIZE(mipi_640mbps_19_2mhz_2l),
>>> + .regs = mipi_640mbps_19_2mhz_2l,
>>> + },
>>> + [IMX258_4_LANE_MODE] = {
>>> + .num_of_regs = ARRAY_SIZE(mipi_640mbps_19_2mhz_4l),
>>> + .regs = mipi_640mbps_19_2mhz_4l,
>>> + },
>>> }
>>> },
>>> };
>>> @@ -410,15 +529,27 @@ static const struct imx258_link_freq_config link_freq_configs_24[] = {
>>> [IMX258_LINK_FREQ_1267MBPS] = {
>>> .pixels_per_line = IMX258_PPL_DEFAULT,
>>> .reg_list = {
>>> - .num_of_regs = ARRAY_SIZE(mipi_1272mbps_24mhz),
>>> - .regs = mipi_1272mbps_24mhz,
>>> + [IMX258_2_LANE_MODE] = {
>>> + .num_of_regs = ARRAY_SIZE(mipi_1272mbps_24mhz_2l),
>>> + .regs = mipi_1272mbps_24mhz_2l,
>>> + },
>>> + [IMX258_4_LANE_MODE] = {
>>> + .num_of_regs = ARRAY_SIZE(mipi_1272mbps_24mhz_4l),
>>> + .regs = mipi_1272mbps_24mhz_4l,
>>> + },
>>> }
>>> },
>>> [IMX258_LINK_FREQ_640MBPS] = {
>>> .pixels_per_line = IMX258_PPL_DEFAULT,
>>> .reg_list = {
>>> - .num_of_regs = ARRAY_SIZE(mipi_642mbps_24mhz),
>>> - .regs = mipi_642mbps_24mhz,
>>> + [IMX258_2_LANE_MODE] = {
>>> + .num_of_regs = ARRAY_SIZE(mipi_642mbps_24mhz_2l),
>>> + .regs = mipi_642mbps_24mhz_2l,
>>> + },
>>> + [IMX258_4_LANE_MODE] = {
>>> + .num_of_regs = ARRAY_SIZE(mipi_642mbps_24mhz_4l),
>>> + .regs = mipi_642mbps_24mhz_4l,
>>> + },
>>> }
>>> },
>>> };
>>> @@ -477,6 +608,7 @@ struct imx258 {
>>>
>>> const struct imx258_link_freq_config *link_freq_configs;
>>> const s64 *link_freq_menu_items;
>>> + unsigned int nlanes;
>>>
>>> /*
>>> * Mutex for serialized access:
>>> @@ -782,7 +914,7 @@ static int imx258_set_pad_format(struct v4l2_subdev *sd,
>>> __v4l2_ctrl_s_ctrl(imx258->link_freq, mode->link_freq_index);
>>>
>>> link_freq = imx258->link_freq_menu_items[mode->link_freq_index];
>>> - pixel_rate = link_freq_to_pixel_rate(link_freq);
>>> + pixel_rate = link_freq_to_pixel_rate(link_freq, imx258->nlanes);
>>> __v4l2_ctrl_s_ctrl_int64(imx258->pixel_rate, pixel_rate);
>>> /* Update limits and set FPS to default */
>>> vblank_def = imx258->cur_mode->vts_def -
>>> @@ -811,11 +943,13 @@ static int imx258_start_streaming(struct imx258 *imx258)
>>> {
>>> struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
>>> const struct imx258_reg_list *reg_list;
>>> + const struct imx258_link_freq_config *link_freq_cfg;
>>> int ret, link_freq_index;
>>>
>>> /* Setup PLL */
>>> link_freq_index = imx258->cur_mode->link_freq_index;
>>> - reg_list = &imx258->link_freq_configs[link_freq_index].reg_list;
>>> + link_freq_cfg = &imx258->link_freq_configs[link_freq_index];
>>> + reg_list = &link_freq_cfg->reg_list[imx258->nlanes == 2 ? 0 : 1];
>>> ret = imx258_write_regs(imx258, reg_list->regs, reg_list->num_of_regs);
>>> if (ret) {
>>> dev_err(&client->dev, "%s failed to set plls\n", __func__);
>>> @@ -1033,9 +1167,11 @@ static int imx258_init_controls(struct imx258 *imx258)
>>> vflip->flags |= V4L2_CTRL_FLAG_READ_ONLY;
>>>
>>> pixel_rate_max =
>>> - link_freq_to_pixel_rate(imx258->link_freq_menu_items[0]);
>>> + link_freq_to_pixel_rate(imx258->link_freq_menu_items[0],
>>> + imx258->nlanes);
>>> pixel_rate_min =
>>> - link_freq_to_pixel_rate(imx258->link_freq_menu_items[1]);
>>> + link_freq_to_pixel_rate(imx258->link_freq_menu_items[1],
>>> + imx258->nlanes);
>>> /* By default, PIXEL_RATE is read only */
>>> imx258->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops,
>>> V4L2_CID_PIXEL_RATE,
>>> @@ -1132,6 +1268,10 @@ static int imx258_get_regulators(struct imx258 *imx258,
>>> static int imx258_probe(struct i2c_client *client)
>>> {
>>> struct imx258 *imx258;
>>> + struct fwnode_handle *endpoint;
>>> + struct v4l2_fwnode_endpoint ep = {
>>> + .bus_type = V4L2_MBUS_CSI2_DPHY
>>> + };
>>> int ret;
>>> u32 val = 0;
>>>
>>> @@ -1172,13 +1312,35 @@ static int imx258_probe(struct i2c_client *client)
>>> return -EINVAL;
>>> }
>>>
>>> + endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL);
>>> + if (!endpoint) {
>>> + dev_err(&client->dev, "Endpoint node not found\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep);
>>
>> Here you're obtaining the list of supported link frequencies from the
>> firmware but it is not validated (nor it was validated by the driver
>> previously). I'd regard that a driver bug but fixing it at this point could
>> introduce adverse effects elsewhere.
>>
>> I think what I'd do here is that I'd ignore the issue if there are no
>> frequencies defined for the endpoint but if there are, then enable only
>> those that are listed in the endpoint.
>>
>> Could you add a patch to do this, please? v4l2_link_freq_to_bitmap() has
>> been recently added to facilitate this.
>>
>
> I can give this a try, it would be similar to this patch that you submitted
> earlier for the imx319 here
> https://github.com/torvalds/linux/commit/726a09c1b6890887b7388745a26c8e93867780ca
> right?
>
I believe I got this implemented, added in that v4l2_link_freq_to_bitmap()
and it failed to probe the imx258 device due to missing frequencies so I
checked the device dts and the imx258 had no link-frequencies specified so
added in 321000000 and 636000000 to match the 24mhz and it worked, I then
swapped it over to bogus numbers 311000000 and 626000000 and it complained
about no matching link frequencies found so it failed to probe. Looks
like its working with that new function now. Will include in next revision
>>> + fwnode_handle_put(endpoint);
>>> + if (ret) {
>>> + dev_err(&client->dev, "Parsing endpoint node failed\n");
>>> + return ret;
>>> + }
>>> +
>>> + /* Get number of data lanes */
>>> + imx258->nlanes = ep.bus.mipi_csi2.num_data_lanes;
>>> + if (imx258->nlanes != 2 && imx258->nlanes != 4) {
>>> + dev_err(&client->dev, "Invalid data lanes: %u\n",
>>> + imx258->nlanes);
>>> + ret = -EINVAL;
>>> + goto error_endpoint_free;
>>> + }
>>> +
>>> /* Initialize subdev */
>>> v4l2_i2c_subdev_init(&imx258->sd, client, &imx258_subdev_ops);
>>>
>>> /* Will be powered off via pm_runtime_idle */
>>> ret = imx258_power_on(&client->dev);
>>> if (ret)
>>> - return ret;
>>> + goto error_endpoint_free;
>>>
>>> /* Check module identity */
>>> ret = imx258_identify_module(imx258);
>>> @@ -1211,6 +1373,7 @@ static int imx258_probe(struct i2c_client *client)
>>> pm_runtime_set_active(&client->dev);
>>> pm_runtime_enable(&client->dev);
>>> pm_runtime_idle(&client->dev);
>>> + v4l2_fwnode_endpoint_free(&ep);
>>>
>>> return 0;
>>>
>>> @@ -1223,6 +1386,9 @@ static int imx258_probe(struct i2c_client *client)
>>> error_identify:
>>> imx258_power_off(&client->dev);
>>>
>>> +error_endpoint_free:
>>> + v4l2_fwnode_endpoint_free(&ep);
>>> +
>>> return ret;
>>> }
>>>
>>
>
^ permalink raw reply
* Re: [PATCH v3 net-next 0/2] Add en8811h phy driver and devicetree binding doc
From: patchwork-bot+netdevbpf @ 2024-03-29 19:10 UTC (permalink / raw)
To: Eric Woudstra
Cc: davem, edumazet, kuba, pabeni, robh+dt, krzysztof.kozlowski+dt,
conor+dt, andrew, hkallweit1, linux, matthias.bgg,
angelogioacchino.delregno, frank-w, daniel, lucien.jheng, hujy652,
netdev, devicetree
In-Reply-To: <20240326162305.303598-1-ericwouds@gmail.com>
Hello:
This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Tue, 26 Mar 2024 17:23:03 +0100 you wrote:
> This patch series adds the driver and the devicetree binding documentation
> for the Airoha en8811h PHY.
>
> Changes in PATCH v3:
>
> air_en8811h.c:
> * Dedicated __air_buckpbus_reg_modify()
> * Renamed host to mcu
> * Append 'S' to AIR_PHY_LED_DUR_BLINK_xxxM
> * Handle hw-leds as in mt798x_phy_led_hw_control_set(), add 2500Mbps
> * Moved firmware loading to .probe()
> * Disable leds after firmware load
> * Moved 'waiting for mcu ready' to dedicated function
> * Return -EINVAL from .config_aneg() when auto-neg is turned off
> * Removed check for AUTONEG_ENABLE from .read_status()
> * Added more details about mode 1
> * Use macros from wordpart.h
> * Set rate_matching in .read_status(), fixes 100Mbps traffic
>
> [...]
Here is the summary with links:
- [v3,net-next,1/2] dt-bindings: net: airoha,en8811h: Add en8811h
https://git.kernel.org/netdev/net-next/c/2434ba2bc851
- [v3,net-next,2/2] net: phy: air_en8811h: Add the Airoha EN8811H PHY driver
https://git.kernel.org/netdev/net-next/c/71e79430117d
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH] dt-bindings: pci: altera: covert to yaml
From: Krzysztof Kozlowski @ 2024-03-29 19:27 UTC (permalink / raw)
To: matthew.gerlach, joyce.ooi, bhelgaas, lpieralisi, kw, robh,
krzysztof.kozlowski+dt, conor+dt, linux-pci, devicetree,
linux-kernel
In-Reply-To: <20240329170031.3379524-1-matthew.gerlach@linux.intel.com>
On 29/03/2024 18:00, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> Covert the device tree bindings for the Altera Root
> Port controller from text to yaml.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> ---
...
> diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
> new file mode 100644
> index 000000000000..8f1ad1362ad1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
> @@ -0,0 +1,106 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (C) 2024, Intel Corporation
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera PCIe Root Port
> +
> +maintainers:
> + - Matthew Gerlach <matthew.gerlach@linux.intel.com>
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - altr,pcie-root-port-1.0
> + - altr,pcie-root-port-2.0
> +
> + reg:
> + minItems: 2
> + maxItems: 3
> +
> + reg-names:
> + description:
> + TX slave port region (Txs)
> + Control register access region (Cra)
> + Hard IP region if altr,pcie-root-port-2.0 (Hip)
All these go to reg as description of items.
Both - reg and reg-names - need constraints per variant in
allOf:if:then:. Move allOf: to bottom of file, just like example-schema
is showing.
> +
> + items:
> + - const: Txs
> + - const: Cra
> + - const: Hip
> + minItems: 2
> +
> + device_type:
> + const: pci
I don't think you need it.
> +
> + "#address-cells":
> + const: 3
Drop
> +
> + "#size-cells":
> + const: 2
Drop
> +
> + interrupts:
> + minItems: 1
This should be maxItems.
> +
> + interrupt-map-mask:
> + items:
> + - const: 0
> + - const: 0
> + - const: 0
> + - const: 7
I guess as well.
> +
> + interrupt-map:
> + maxItems: 4
> +
> + "#interrupt-cells":
> + const: 1
Drop
> +
> + msi-parent:
> + description: Link to the hardware entity that serves as the MSI controller.
Just true.
Please open existing, recent PCI bindings and look how it is done.
> +
> + bus-range:
> + description: PCI bus numbers covered.
Drop
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - device_type
> + - "#address-cells"
> + - "#size-cells"
> + - interrupts
> + - interrupt-map
> + - interrupt-map-mask
> + - "#interrupt-cells"
This also needs cleaning.
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + pcie_0: pcie@c00000000 {
> + compatible = "altr,pcie-root-port-1.0";
> + reg = <0xc0000000 0x20000000>,
> + <0xff220000 0x00004000>;
Misaligned.
> + reg-names = "Txs", "Cra";
> + interrupt-parent = <&hps_0_arm_gic_0>;
> + interrupts = <0 40 4>;
Use defines for common constnats.
> + #interrupt-cells = <1>;
> + bus-range = <0x0 0xFF>;
Lowercase hex
> + device_type = "pci";
> + msi-parent = <&msi_to_gic_gen_0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc 1>,
> + <0 0 0 2 &pcie_intc 2>,
> + <0 0 0 3 &pcie_intc 3>,
> + <0 0 0 4 &pcie_intc 4>;
> + ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
> + 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
Misaligned.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: reset: Add Amlogic T7 Reset Controller
From: Krzysztof Kozlowski @ 2024-03-29 19:39 UTC (permalink / raw)
To: kelvin.zhang, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl
Cc: devicetree, linux-arm-kernel, linux-amlogic, linux-kernel,
Zelong Dong
In-Reply-To: <20240329-t7-reset-v1-1-4c6e2e68359e@amlogic.com>
On 29/03/2024 10:17, Kelvin Zhang via B4 Relay wrote:
> From: Zelong Dong <zelong.dong@amlogic.com>
>
> Add a new compatible and the related header file
> for Amlogic T7 Reset Controller.
>
> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
> Signed-off-by: Kelvin Zhang <kelvin.zhang@amlogic.com>
> ---
> .../bindings/reset/amlogic,meson-reset.yaml | 1 +
> include/dt-bindings/reset/amlogic,t7-reset.h | 197 +++++++++++++++++++++
> 2 files changed, 198 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
> index f0c6c0df0ce3..fefe343e5afe 100644
> --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
> @@ -19,6 +19,7 @@ properties:
> - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
> - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
> - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs
> + - amlogic,t7-reset # Reset Controller on T7 and compatible SoCs
>
If there is going to be any resend, please drop the comment. It's not
really helpful and makes it trickier to read.
> reg:
> maxItems: 1
> diff --git a/include/dt-bindings/reset/amlogic,t7-reset.h b/include/dt-bindings/reset/amlogic,t7-reset.h
> new file mode 100644
> index 000000000000..ca4a832eeeec
> --- /dev/null
> +++ b/include/dt-bindings/reset/amlogic,t7-reset.h
> @@ -0,0 +1,197 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_AMLOGIC_T7_RESET_H
> +#define _DT_BINDINGS_AMLOGIC_T7_RESET_H
> +
> +/* RESET0 */
> +/* 0-3 */
I assume this matches existing drivers which do not use IDs but map the
binding to hardware value? I remember we talked about changing it, so if
something happened about this and it could be changed: please change.
Otherwise, it's fine:
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 0/5] Support for Cadence xSPI Marvell modifications
From: Witold Sadowski @ 2024-03-29 19:48 UTC (permalink / raw)
To: linux-kernel, linux-spi, devicetree
Cc: broonie, robh, krzysztof.kozlowski+dt, conor+dt, pthombar,
Witold Sadowski
This patch series is adding support for additional
Marvell HW overlay build on top of Cadence xSPI IP
It includes:
- Clock and PHY configuration
- ACPI support
- Additional MRVL HW overlay to support tranfer operations
Piyush Malgujar (1):
driver: spi: cadence: Add ACPI support
Witold Sadowski (4):
spi: cadence: Add new bindings documentation for Cadence XSPI
spi: cadence: Add Marvell IP modification changes
spi: cadence: Force single modebyte
cadence-xspi: Add xfer capabilities
.../devicetree/bindings/spi/cdns,xspi.yaml | 84 ++-
drivers/spi/spi-cadence-xspi.c | 675 +++++++++++++++++-
2 files changed, 738 insertions(+), 21 deletions(-)
--
2.17.1
^ permalink raw reply
* [PATCH 1/5] spi: cadence: Add new bindings documentation for Cadence XSPI
From: Witold Sadowski @ 2024-03-29 19:48 UTC (permalink / raw)
To: linux-kernel, linux-spi, devicetree
Cc: broonie, robh, krzysztof.kozlowski+dt, conor+dt, pthombar,
Witold Sadowski
In-Reply-To: <20240329194849.25554-1-wsadowski@marvell.com>
Add new bindings:
- mrvl,xspi-nor compatible string
Compatible string to enable Marvell XSPI modification
- Multiple PHY configuration registers
- base for xfer register set
Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
---
.../devicetree/bindings/spi/cdns,xspi.yaml | 84 ++++++++++++++++++-
1 file changed, 83 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml
index eb0f92468185..d1fde8d4e9b8 100644
--- a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml
@@ -20,23 +20,74 @@ allOf:
properties:
compatible:
- const: cdns,xspi-nor
+ - const: cdns,xspi-nor
+ - const: mrvl,xspi-nor
reg:
items:
- description: address and length of the controller register set
- description: address and length of the Slave DMA data port
- description: address and length of the auxiliary registers
+ - description: address and length of the xfer registers
reg-names:
items:
- const: io
- const: sdma
- const: aux
+ - const: xferbase
interrupts:
maxItems: 1
+ cdns,dll-phy-control:
+ description: |
+ PHY config register. Valid only for cdns,mrvl-xspi-nor
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x707
+
+ cdns,rfile-phy-control:
+ description: |
+ PHY config register. Valid only for cdns,mrvl-xspi-nor
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x40000
+
+ cdns,rfile-phy-tsel:
+ description: |
+ PHY config register. Valid only for cdns,mrvl-xspi-nor
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+ cdns,phy-dq-timing:
+ description: |
+ PHY config register. Valid only for cdns,mrvl-xspi-nor
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x101
+
+ cdns,phy-dqs-timing:
+ description: |
+ PHY config register. Valid only for cdns,mrvl-xspi-nor
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x700404
+
+ cdns,phy-gate-lpbk-ctrl:
+ description: |
+ PHY config register. Valid only for cdns,mrvl-xspi-nor
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x200030
+
+ cdns,phy-dll-master-ctrl:
+ description: |
+ PHY config register. Valid only for cdns,mrvl-xspi-nor
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x00800000
+
+ cdns,phy-dll-slave-ctrl:
+ description: |
+ PHY config register. Valid only for cdns,mrvl-xspi-nor
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x0000ff01
+
required:
- compatible
- reg
@@ -68,6 +119,37 @@ examples:
reg = <0>;
};
+ flash@1 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <75000000>;
+ reg = <1>;
+ };
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ xspi: spi@a0010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,xspi-nor";
+ reg = <0x0 0xa0010000 0x0 0x1040>,
+ <0x0 0xb0000000 0x0 0x1000>,
+ <0x0 0xa0020000 0x0 0x100>;
+ <0x0 0xa0090000 0x0 0x100>;
+ reg-names = "io", "sdma", "aux", "xferbase";
+ interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <75000000>;
+ reg = <0>;
+ };
+
flash@1 {
compatible = "jedec,spi-nor";
spi-max-frequency = <75000000>;
--
2.17.1
^ permalink raw reply related
* [PATCH 2/5] spi: cadence: Add Marvell IP modification changes
From: Witold Sadowski @ 2024-03-29 19:48 UTC (permalink / raw)
To: linux-kernel, linux-spi, devicetree
Cc: broonie, robh, krzysztof.kozlowski+dt, conor+dt, pthombar,
Witold Sadowski
In-Reply-To: <20240329194849.25554-1-wsadowski@marvell.com>
Add support for Marvell IP modification - clock divider,
and PHY config, and IRQ clearing.
Clock divider block is build into Cadence XSPI controller
and is connected directly to 800MHz clock.
As PHY config is not set directly in IP block, driver can
load custom PHY configuration values.
To correctly clear interrupt in Marvell implementation
MSI-X must be cleared too.
Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
---
drivers/spi/spi-cadence-xspi.c | 311 ++++++++++++++++++++++++++++++++-
1 file changed, 306 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c
index 8648b8eb080d..f570b2920b18 100644
--- a/drivers/spi/spi-cadence-xspi.c
+++ b/drivers/spi/spi-cadence-xspi.c
@@ -189,6 +189,43 @@
((op)->data.dir == SPI_MEM_DATA_IN) ? \
CDNS_XSPI_STIG_CMD_DIR_READ : CDNS_XSPI_STIG_CMD_DIR_WRITE))
+/*PHY default values*/
+#define REGS_DLL_PHY_CTRL 0x00000707
+#define CTB_RFILE_PHY_CTRL 0x00004000
+#define RFILE_PHY_TSEL 0x00000000
+#define RFILE_PHY_DQ_TIMING 0x00000101
+#define RFILE_PHY_DQS_TIMING 0x00700404
+#define RFILE_PHY_GATE_LPBK_CTRL 0x00200030
+#define RFILE_PHY_DLL_MASTER_CTRL 0x00800000
+#define RFILE_PHY_DLL_SLAVE_CTRL 0x0000ff01
+
+/*PHY config rtegisters*/
+#define CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL 0x1034
+#define CDNS_XSPI_PHY_CTB_RFILE_PHY_CTRL 0x0080
+#define CDNS_XSPI_PHY_CTB_RFILE_PHY_TSEL 0x0084
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQ_TIMING 0x0000
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQS_TIMING 0x0004
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL 0x0008
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL 0x000c
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL 0x0010
+#define CDNS_XSPI_DATASLICE_RFILE_PHY_DLL_OBS_REG_0 0x001c
+
+#define CDNS_XSPI_DLL_RST_N BIT(24)
+#define CDNS_XSPI_DLL_LOCK BIT(0)
+
+/* Marvell clock config register */
+#define CDNS_MRVL_XSPI_CLK_CTRL_AUX_REG 0x2020
+#define CDNS_MRVL_XSPI_CLK_ENABLE BIT(0)
+#define CDNS_MRVL_XSPI_CLK_DIV GENMASK(4, 1)
+
+/* Marvell MSI-X clear interrupt register */
+#define CDNS_MRVL_XSPI_SPIX_INTR_AUX 0x2000
+#define CDNS_MRVL_MSIX_CLEAR_IRQ 0x01
+
+/* Marvell clock macros */
+#define CDNS_MRVL_XSPI_CLOCK_IO_HZ 800000000
+#define CDNS_MRVL_XSPI_CLOCK_DIVIDED(div) ((CDNS_MRVL_XSPI_CLOCK_IO_HZ) / (div))
+
enum cdns_xspi_stig_instr_type {
CDNS_XSPI_STIG_INSTR_TYPE_0,
CDNS_XSPI_STIG_INSTR_TYPE_1,
@@ -208,6 +245,7 @@ enum cdns_xspi_stig_cmd_dir {
struct cdns_xspi_dev {
struct platform_device *pdev;
struct device *dev;
+ bool mrvl_hw_overlay;
void __iomem *iobase;
void __iomem *auxbase;
@@ -228,6 +266,157 @@ struct cdns_xspi_dev {
u8 hw_num_banks;
};
+#define MRVL_DEFAULT_CLK 25000000
+
+const int cdns_mrvl_xspi_clk_div_list[] = {
+ 4, //0x0 = Divide by 4. SPI clock is 200 MHz.
+ 6, //0x1 = Divide by 6. SPI clock is 133.33 MHz.
+ 8, //0x2 = Divide by 8. SPI clock is 100 MHz.
+ 10, //0x3 = Divide by 10. SPI clock is 80 MHz.
+ 12, //0x4 = Divide by 12. SPI clock is 66.666 MHz.
+ 16, //0x5 = Divide by 16. SPI clock is 50 MHz.
+ 18, //0x6 = Divide by 18. SPI clock is 44.44 MHz.
+ 20, //0x7 = Divide by 20. SPI clock is 40 MHz.
+ 24, //0x8 = Divide by 24. SPI clock is 33.33 MHz.
+ 32, //0x9 = Divide by 32. SPI clock is 25 MHz.
+ 40, //0xA = Divide by 40. SPI clock is 20 MHz.
+ 50, //0xB = Divide by 50. SPI clock is 16 MHz.
+ 64, //0xC = Divide by 64. SPI clock is 12.5 MHz.
+ 128, //0xD = Divide by 128. SPI clock is 6.25 MHz.
+ -1 //End of list
+};
+
+static bool cdns_xspi_reset_dll(struct cdns_xspi_dev *cdns_xspi)
+{
+ u32 dll_cntrl = readl(cdns_xspi->iobase +
+ CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL);
+ u32 dll_lock;
+
+ /*Reset DLL*/
+ dll_cntrl |= CDNS_XSPI_DLL_RST_N;
+ writel(dll_cntrl, cdns_xspi->iobase +
+ CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL);
+
+ /*Wait for DLL lock*/
+ return readl_relaxed_poll_timeout(cdns_xspi->iobase +
+ CDNS_XSPI_INTR_STATUS_REG,
+ dll_lock, ((dll_lock & CDNS_XSPI_DLL_LOCK) == 1), 10, 10000);
+}
+
+static void cdns_configure_phy_register_io(struct cdns_xspi_dev *cdns_xspi,
+ const char *prop_name,
+ u64 default_value, u64 offset)
+{
+ struct device_node *node_prop = cdns_xspi->pdev->dev.of_node;
+ u64 phy_cfg;
+
+ if (of_property_read_u64(node_prop, prop_name, &phy_cfg))
+ phy_cfg = default_value;
+ writel(phy_cfg,
+ cdns_xspi->iobase + offset);
+}
+
+static void cdns_configure_phy_register_aux(struct cdns_xspi_dev *cdns_xspi,
+ const char *prop_name,
+ u64 default_value, u64 offset)
+{
+ struct device_node *node_prop = cdns_xspi->pdev->dev.of_node;
+ u64 phy_cfg;
+
+ if (of_property_read_u64(node_prop, "cdns,dll-phy-control", &phy_cfg))
+ phy_cfg = default_value;
+ writel(phy_cfg,
+ cdns_xspi->auxbase + offset);
+}
+
+//Static confiuration of PHY
+static bool cdns_xspi_configure_phy(struct cdns_xspi_dev *cdns_xspi)
+{
+ cdns_configure_phy_register_io(cdns_xspi,
+ "cdns,dll-phy-control",
+ REGS_DLL_PHY_CTRL,
+ CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL);
+ cdns_configure_phy_register_aux(cdns_xspi,
+ "cdns,rfile-phy-control",
+ CTB_RFILE_PHY_CTRL,
+ CDNS_XSPI_PHY_CTB_RFILE_PHY_CTRL);
+ cdns_configure_phy_register_aux(cdns_xspi,
+ "cdns,rfile-phy-tsel",
+ RFILE_PHY_TSEL,
+ CDNS_XSPI_PHY_CTB_RFILE_PHY_TSEL);
+ cdns_configure_phy_register_aux(cdns_xspi,
+ "cdns,phy-dq-timing",
+ RFILE_PHY_DQ_TIMING,
+ CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQ_TIMING);
+ cdns_configure_phy_register_aux(cdns_xspi,
+ "cdns,phy-dqs-timing",
+ RFILE_PHY_DQS_TIMING,
+ CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQS_TIMING);
+ cdns_configure_phy_register_aux(cdns_xspi,
+ "cdns,phy-gate-lpbk-ctrl",
+ RFILE_PHY_GATE_LPBK_CTRL,
+ CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL);
+ cdns_configure_phy_register_aux(cdns_xspi,
+ "cdns,phy-dll-master-ctrl",
+ RFILE_PHY_DLL_MASTER_CTRL,
+ CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL);
+ cdns_configure_phy_register_aux(cdns_xspi,
+ "cdns,phy-dll-slave-ctrl",
+ RFILE_PHY_DLL_SLAVE_CTRL,
+ CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL);
+
+ return cdns_xspi_reset_dll(cdns_xspi);
+}
+
+// Find max avalible clock
+static bool cdns_mrvl_xspi_setup_clock(struct cdns_xspi_dev *cdns_xspi,
+ int requested_clk)
+{
+ int i = 0;
+ int clk_val;
+ u32 clk_reg;
+ bool update_clk = false;
+
+ while (cdns_mrvl_xspi_clk_div_list[i] > 0) {
+ clk_val = CDNS_MRVL_XSPI_CLOCK_DIVIDED(
+ cdns_mrvl_xspi_clk_div_list[i]);
+ if (clk_val <= requested_clk)
+ break;
+ i++;
+ }
+
+ if (cdns_mrvl_xspi_clk_div_list[i] == -1) {
+ dev_info(cdns_xspi->dev,
+ "Unable to find clk div for CLK: %d - using 6.25MHz\n",
+ requested_clk);
+ i = 0x0D;
+ } else {
+ dev_dbg(cdns_xspi->dev, "Found clk div: %d, clk val: %d\n",
+ cdns_mrvl_xspi_clk_div_list[i],
+ CDNS_MRVL_XSPI_CLOCK_DIVIDED(
+ cdns_mrvl_xspi_clk_div_list[i]));
+ }
+
+ clk_reg = readl(cdns_xspi->auxbase + CDNS_MRVL_XSPI_CLK_CTRL_AUX_REG);
+
+ if (FIELD_GET(CDNS_MRVL_XSPI_CLK_DIV, clk_reg) != i) {
+ clk_reg &= ~CDNS_MRVL_XSPI_CLK_ENABLE;
+ writel(clk_reg,
+ cdns_xspi->auxbase + CDNS_MRVL_XSPI_CLK_CTRL_AUX_REG);
+ clk_reg = FIELD_PREP(CDNS_MRVL_XSPI_CLK_DIV, i);
+ clk_reg &= ~CDNS_MRVL_XSPI_CLK_DIV;
+ clk_reg |= FIELD_PREP(CDNS_MRVL_XSPI_CLK_DIV, i);
+ clk_reg |= CDNS_MRVL_XSPI_CLK_ENABLE;
+ update_clk = true;
+ }
+
+ if (update_clk)
+ writel(clk_reg,
+ cdns_xspi->auxbase + CDNS_MRVL_XSPI_CLK_CTRL_AUX_REG);
+
+ return update_clk;
+}
+
static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_dev *cdns_xspi)
{
u32 ctrl_stat;
@@ -291,6 +480,10 @@ static void cdns_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi,
bool enabled)
{
u32 intr_enable;
+ u32 irq_status;
+
+ irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
+ writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
if (enabled)
@@ -315,6 +508,9 @@ static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
return -EIO;
}
+ writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG),
+ cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG);
+
ctrl_features = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_FEATURES_REG);
cdns_xspi->hw_num_banks = FIELD_GET(CDNS_XSPI_NUM_BANKS, ctrl_features);
cdns_xspi_set_interrupts(cdns_xspi, false);
@@ -322,6 +518,70 @@ static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
return 0;
}
+static void mrvl_ioreadq(void __iomem *addr, void *buf, int len)
+{
+ int i = 0;
+ int rcount = len / 8;
+ int rcount_nf = len % 8;
+ uint64_t tmp;
+ uint64_t *buf64 = (uint64_t *)buf;
+
+ if (((uint64_t)buf % 8) == 0) {
+ for (i = 0; i < rcount; i++)
+ *buf64++ = readq(addr);
+ } else {
+ for (i = 0; i < rcount; i++) {
+ tmp = readq(addr);
+ memcpy(buf+(i*8), &tmp, 8);
+ }
+ }
+
+ if (rcount_nf != 0) {
+ tmp = readq(addr);
+ memcpy(buf+(i*8), &tmp, rcount_nf);
+ }
+}
+
+static void mrvl_iowriteq(void __iomem *addr, const void *buf, int len)
+{
+ int i = 0;
+ int rcount = len / 8;
+ int rcount_nf = len % 8;
+ uint64_t tmp;
+ uint64_t *buf64 = (uint64_t *)buf;
+
+ if (((uint64_t)buf % 8) == 0) {
+ for (i = 0; i < rcount; i++)
+ writeq(*buf64++, addr);
+ } else {
+ for (i = 0; i < rcount; i++) {
+ memcpy(&tmp, buf+(i*8), 8);
+ writeq(tmp, addr);
+ }
+ }
+
+ if (rcount_nf != 0) {
+ memcpy(&tmp, buf+(i*8), rcount_nf);
+ writeq(tmp, addr);
+ }
+}
+
+static void cdns_xspi_sdma_memread(struct cdns_xspi_dev *cdns_xspi, int len)
+{
+ if (cdns_xspi->mrvl_hw_overlay)
+ mrvl_ioreadq(cdns_xspi->sdmabase, cdns_xspi->in_buffer, len);
+ else
+ ioread8_rep(cdns_xspi->sdmabase, cdns_xspi->in_buffer, len);
+}
+
+static void cdns_xspi_sdma_memwrite(struct cdns_xspi_dev *cdns_xspi, int len)
+{
+ if (cdns_xspi->mrvl_hw_overlay)
+ mrvl_iowriteq(cdns_xspi->sdmabase, cdns_xspi->out_buffer, len);
+ else
+ iowrite8_rep(cdns_xspi->sdmabase, cdns_xspi->out_buffer, len);
+}
+
static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
{
u32 sdma_size, sdma_trd_info;
@@ -333,13 +593,11 @@ static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
switch (sdma_dir) {
case CDNS_XSPI_SDMA_DIR_READ:
- ioread8_rep(cdns_xspi->sdmabase,
- cdns_xspi->in_buffer, sdma_size);
+ cdns_xspi_sdma_memread(cdns_xspi, sdma_size);
break;
case CDNS_XSPI_SDMA_DIR_WRITE:
- iowrite8_rep(cdns_xspi->sdmabase,
- cdns_xspi->out_buffer, sdma_size);
+ cdns_xspi_sdma_memwrite(cdns_xspi, sdma_size);
break;
}
}
@@ -411,6 +669,9 @@ static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi,
if (cdns_xspi->cur_cs != spi_get_chipselect(mem->spi, 0))
cdns_xspi->cur_cs = spi_get_chipselect(mem->spi, 0);
+ if (cdns_xspi->mrvl_hw_overlay)
+ cdns_mrvl_xspi_setup_clock(cdns_xspi, mem->spi->max_speed_hz);
+
return cdns_xspi_send_stig_command(cdns_xspi, op,
(dir != SPI_MEM_NO_DATA));
}
@@ -451,6 +712,10 @@ static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev)
irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
+ if (cdns_xspi->mrvl_hw_overlay)
+ writel(CDNS_MRVL_MSIX_CLEAR_IRQ,
+ cdns_xspi->auxbase + CDNS_MRVL_XSPI_SPIX_INTR_AUX);
+
if (irq_status &
(CDNS_XSPI_SDMA_ERROR | CDNS_XSPI_SDMA_TRIGGER |
CDNS_XSPI_STIG_DONE)) {
@@ -524,6 +789,27 @@ static void cdns_xspi_print_phy_config(struct cdns_xspi_dev *cdns_xspi)
readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL));
}
+static int cdns_xspi_setup(struct spi_device *spi_dev)
+{
+ struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(spi_dev->master);
+
+ if (cdns_xspi->mrvl_hw_overlay)
+ cdns_mrvl_xspi_setup_clock(cdns_xspi, spi_dev->max_speed_hz);
+
+ return 0;
+}
+
+static bool cdns_xspi_get_hw_overlay(struct platform_device *pdev)
+{
+ int err;
+
+ err = device_property_match_string(&pdev->dev,
+ "compatible", "mrvl,xspi-nor");
+
+
+ return (err >= 0);
+}
+
static int cdns_xspi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -531,6 +817,7 @@ static int cdns_xspi_probe(struct platform_device *pdev)
struct cdns_xspi_dev *cdns_xspi = NULL;
struct resource *res;
int ret;
+ bool hw_overlay;
host = devm_spi_alloc_host(dev, sizeof(*cdns_xspi));
if (!host)
@@ -540,10 +827,15 @@ static int cdns_xspi_probe(struct platform_device *pdev)
SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL | SPI_RX_OCTAL |
SPI_MODE_0 | SPI_MODE_3;
+ hw_overlay = cdns_xspi_get_hw_overlay(pdev);
+
host->mem_ops = &cadence_xspi_mem_ops;
host->dev.of_node = pdev->dev.of_node;
host->bus_num = -1;
+ if (hw_overlay)
+ host->setup = cdns_xspi_setup;
+
platform_set_drvdata(pdev, host);
cdns_xspi = spi_controller_get_devdata(host);
@@ -555,6 +847,8 @@ static int cdns_xspi_probe(struct platform_device *pdev)
init_completion(&cdns_xspi->auto_cmd_complete);
init_completion(&cdns_xspi->sdma_complete);
+ cdns_xspi->mrvl_hw_overlay = hw_overlay;
+
ret = cdns_xspi_of_get_plat_data(pdev);
if (ret)
return -ENODEV;
@@ -588,8 +882,12 @@ static int cdns_xspi_probe(struct platform_device *pdev)
return ret;
}
- cdns_xspi_print_phy_config(cdns_xspi);
+ if (hw_overlay) {
+ cdns_mrvl_xspi_setup_clock(cdns_xspi, MRVL_DEFAULT_CLK);
+ cdns_xspi_configure_phy(cdns_xspi);
+ }
+ cdns_xspi_print_phy_config(cdns_xspi);
ret = cdns_xspi_controller_init(cdns_xspi);
if (ret) {
dev_err(dev, "Failed to initialize controller\n");
@@ -613,6 +911,9 @@ static const struct of_device_id cdns_xspi_of_match[] = {
{
.compatible = "cdns,xspi-nor",
},
+ {
+ .compatible = "mrvl,xspi-nor",
+ },
{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, cdns_xspi_of_match);
--
2.17.1
^ permalink raw reply related
* [PATCH 3/5] spi: cadence: Force single modebyte
From: Witold Sadowski @ 2024-03-29 19:48 UTC (permalink / raw)
To: linux-kernel, linux-spi, devicetree
Cc: broonie, robh, krzysztof.kozlowski+dt, conor+dt, pthombar,
Witold Sadowski
In-Reply-To: <20240329194849.25554-1-wsadowski@marvell.com>
During dummy-cycles xSPI will switch GPIO into Hi-Z mode.
To prevent unforeseen consequences of that behaviour, force send
single modebyte(0x00).
Modebyte will be send only if number of dummy-cycles is not equal
to 0. Code must also reduce dummycycle byte count by one - as one byte
is send as modebyte.
Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
---
drivers/spi/spi-cadence-xspi.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c
index f570b2920b18..cce14473e88e 100644
--- a/drivers/spi/spi-cadence-xspi.c
+++ b/drivers/spi/spi-cadence-xspi.c
@@ -145,6 +145,9 @@
#define CDNS_XSPI_STIG_DONE_FLAG BIT(0)
#define CDNS_XSPI_TRD_STATUS 0x0104
+#define MODE_NO_OF_BYTES GENMASK(25, 24)
+#define MODEBYTES_COUNT 1
+
/* Helper macros for filling command registers */
#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase) ( \
FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, (data_phase) ? \
@@ -157,9 +160,10 @@
FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR3, ((op)->addr.val >> 24) & 0xFF) | \
FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR4, ((op)->addr.val >> 32) & 0xFF))
-#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op) ( \
+#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, modebytes) ( \
FIELD_PREP(CDNS_XSPI_CMD_P1_R3_ADDR5, ((op)->addr.val >> 40) & 0xFF) | \
FIELD_PREP(CDNS_XSPI_CMD_P1_R3_CMD, (op)->cmd.opcode) | \
+ FIELD_PREP(MODE_NO_OF_BYTES, modebytes) | \
FIELD_PREP(CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES, (op)->addr.nbytes))
#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, chipsel) ( \
@@ -173,12 +177,12 @@
#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op) \
FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R2_DCNT_L, (op)->data.nbytes & 0xFFFF)
-#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op) ( \
+#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op, dummybytes) ( \
FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \
((op)->data.nbytes >> 16) & 0xffff) | \
FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, \
(op)->dummy.buswidth != 0 ? \
- (((op)->dummy.nbytes * 8) / (op)->dummy.buswidth) : \
+ (((dummybytes) * 8) / (op)->dummy.buswidth) : \
0))
#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \
@@ -609,6 +613,7 @@ static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi,
u32 cmd_regs[6];
u32 cmd_status;
int ret;
+ int dummybytes = op->dummy.nbytes;
ret = cdns_xspi_wait_for_controller_idle(cdns_xspi);
if (ret < 0)
@@ -623,7 +628,12 @@ static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi,
memset(cmd_regs, 0, sizeof(cmd_regs));
cmd_regs[1] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase);
cmd_regs[2] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op);
- cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op);
+ if (dummybytes != 0) {
+ cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, 1);
+ dummybytes--;
+ } else {
+ cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, 0);
+ }
cmd_regs[4] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op,
cdns_xspi->cur_cs);
@@ -633,7 +643,7 @@ static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi,
cmd_regs[0] = CDNS_XSPI_STIG_DONE_FLAG;
cmd_regs[1] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_1(op);
cmd_regs[2] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op);
- cmd_regs[3] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op);
+ cmd_regs[3] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op, dummybytes);
cmd_regs[4] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op,
cdns_xspi->cur_cs);
--
2.17.1
^ permalink raw reply related
* [PATCH 4/5] driver: spi: cadence: Add ACPI support
From: Witold Sadowski @ 2024-03-29 19:48 UTC (permalink / raw)
To: linux-kernel, linux-spi, devicetree
Cc: broonie, robh, krzysztof.kozlowski+dt, conor+dt, pthombar,
Piyush Malgujar, Witold Sadowski
In-Reply-To: <20240329194849.25554-1-wsadowski@marvell.com>
From: Piyush Malgujar <pmalgujar@marvell.com>
These changes enables to read the configs from ACPI tables as
required for successful probing in ACPI uefi environment.
In case of ACPI disabled/dts based environment, it will continue to
read configs from dts as before.
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
---
drivers/spi/spi-cadence-xspi.c | 97 ++++++++++++++++++++++++++++++----
1 file changed, 86 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c
index cce14473e88e..01e81d40f04c 100644
--- a/drivers/spi/spi-cadence-xspi.c
+++ b/drivers/spi/spi-cadence-xspi.c
@@ -2,6 +2,7 @@
// Cadence XSPI flash controller driver
// Copyright (C) 2020-21 Cadence
+#include <linux/acpi.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
@@ -14,6 +15,7 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
+#include <linux/property.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
#include <linux/bitfield.h>
@@ -686,6 +688,67 @@ static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi,
(dir != SPI_MEM_NO_DATA));
}
+#ifdef CONFIG_ACPI
+static bool cdns_xspi_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ struct spi_device *spi = mem->spi;
+ const union acpi_object *obj;
+ struct acpi_device *adev;
+
+ adev = ACPI_COMPANION(&spi->dev);
+
+ if (!acpi_dev_get_property(adev, "spi-tx-bus-width", ACPI_TYPE_INTEGER,
+ &obj)) {
+ switch (obj->integer.value) {
+ case 1:
+ break;
+ case 2:
+ spi->mode |= SPI_TX_DUAL;
+ break;
+ case 4:
+ spi->mode |= SPI_TX_QUAD;
+ break;
+ case 8:
+ spi->mode |= SPI_TX_OCTAL;
+ break;
+ default:
+ dev_warn(&spi->dev,
+ "spi-tx-bus-width %lld not supported\n",
+ obj->integer.value);
+ break;
+ }
+ }
+
+ if (!acpi_dev_get_property(adev, "spi-rx-bus-width", ACPI_TYPE_INTEGER,
+ &obj)) {
+ switch (obj->integer.value) {
+ case 1:
+ break;
+ case 2:
+ spi->mode |= SPI_RX_DUAL;
+ break;
+ case 4:
+ spi->mode |= SPI_RX_QUAD;
+ break;
+ case 8:
+ spi->mode |= SPI_RX_OCTAL;
+ break;
+ default:
+ dev_warn(&spi->dev,
+ "spi-rx-bus-width %lld not supported\n",
+ obj->integer.value);
+ break;
+ }
+ }
+
+ if (!spi_mem_default_supports_op(mem, op))
+ return false;
+
+ return true;
+}
+#endif
+
static int cdns_xspi_mem_op_execute(struct spi_mem *mem,
const struct spi_mem_op *op)
{
@@ -709,6 +772,9 @@ static int cdns_xspi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *
}
static const struct spi_controller_mem_ops cadence_xspi_mem_ops = {
+#ifdef CONFIG_ACPI
+ .supports_op = cdns_xspi_supports_op,
+#endif
.exec_op = cdns_xspi_mem_op_execute,
.adjust_op_size = cdns_xspi_adjust_mem_op_size,
};
@@ -760,21 +826,20 @@ static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev)
static int cdns_xspi_of_get_plat_data(struct platform_device *pdev)
{
- struct device_node *node_prop = pdev->dev.of_node;
- struct device_node *node_child;
+ struct fwnode_handle *fwnode_child;
unsigned int cs;
- for_each_child_of_node(node_prop, node_child) {
- if (!of_device_is_available(node_child))
+ device_for_each_child_node(&pdev->dev, fwnode_child) {
+ if (!fwnode_device_is_available(fwnode_child))
continue;
- if (of_property_read_u32(node_child, "reg", &cs)) {
+ if (fwnode_property_read_u32(fwnode_child, "reg", &cs)) {
dev_err(&pdev->dev, "Couldn't get memory chip select\n");
- of_node_put(node_child);
+ fwnode_handle_put(fwnode_child);
return -ENXIO;
} else if (cs >= CDNS_XSPI_MAX_BANKS) {
dev_err(&pdev->dev, "reg (cs) parameter value too large\n");
- of_node_put(node_child);
+ fwnode_handle_put(fwnode_child);
return -ENXIO;
}
}
@@ -816,7 +881,6 @@ static bool cdns_xspi_get_hw_overlay(struct platform_device *pdev)
err = device_property_match_string(&pdev->dev,
"compatible", "mrvl,xspi-nor");
-
return (err >= 0);
}
@@ -841,6 +905,7 @@ static int cdns_xspi_probe(struct platform_device *pdev)
host->mem_ops = &cadence_xspi_mem_ops;
host->dev.of_node = pdev->dev.of_node;
+ host->dev.fwnode = pdev->dev.fwnode;
host->bus_num = -1;
if (hw_overlay)
@@ -863,19 +928,21 @@ static int cdns_xspi_probe(struct platform_device *pdev)
if (ret)
return -ENODEV;
- cdns_xspi->iobase = devm_platform_ioremap_resource_byname(pdev, "io");
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ cdns_xspi->iobase = devm_ioremap_resource(dev, res);
if (IS_ERR(cdns_xspi->iobase)) {
dev_err(dev, "Failed to remap controller base address\n");
return PTR_ERR(cdns_xspi->iobase);
}
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sdma");
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
cdns_xspi->sdmabase = devm_ioremap_resource(dev, res);
if (IS_ERR(cdns_xspi->sdmabase))
return PTR_ERR(cdns_xspi->sdmabase);
cdns_xspi->sdmasize = resource_size(res);
- cdns_xspi->auxbase = devm_platform_ioremap_resource_byname(pdev, "aux");
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ cdns_xspi->auxbase = devm_ioremap_resource(dev, res);
if (IS_ERR(cdns_xspi->auxbase)) {
dev_err(dev, "Failed to remap AUX address\n");
return PTR_ERR(cdns_xspi->auxbase);
@@ -917,6 +984,13 @@ static int cdns_xspi_probe(struct platform_device *pdev)
return 0;
}
+static const struct acpi_device_id cdns_xspi_acpi_match[] = {
+ {"cdns,xspi-nor", 0},
+ {"mrvl,xspi-nor", 0},
+ {},
+};
+MODULE_DEVICE_TABLE(acpi, cdns_xspi_acpi_match);
+#ifdef CONFIG_OF
static const struct of_device_id cdns_xspi_of_match[] = {
{
.compatible = "cdns,xspi-nor",
@@ -933,6 +1007,7 @@ static struct platform_driver cdns_xspi_platform_driver = {
.driver = {
.name = CDNS_XSPI_NAME,
.of_match_table = cdns_xspi_of_match,
+ .acpi_match_table = cdns_xspi_acpi_match,
},
};
--
2.17.1
^ permalink raw reply related
* [PATCH 5/5] cadence-xspi: Add xfer capabilities
From: Witold Sadowski @ 2024-03-29 19:48 UTC (permalink / raw)
To: linux-kernel, linux-spi, devicetree
Cc: broonie, robh, krzysztof.kozlowski+dt, conor+dt, pthombar,
Witold Sadowski
In-Reply-To: <20240329194849.25554-1-wsadowski@marvell.com>
Add support for iMRVL xfer hw_overlay of Cadence xSPI
block.
MRVL Xfer overlay extend xSPI capabilities, to support
non-memory SPI operations.
With generic xSPI command it allows to create any
required SPI transaction
Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
---
drivers/spi/spi-cadence-xspi.c | 249 +++++++++++++++++++++++++++++++++
1 file changed, 249 insertions(+)
diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c
index 01e81d40f04c..451f83d53898 100644
--- a/drivers/spi/spi-cadence-xspi.c
+++ b/drivers/spi/spi-cadence-xspi.c
@@ -219,19 +219,38 @@
#define CDNS_XSPI_DLL_RST_N BIT(24)
#define CDNS_XSPI_DLL_LOCK BIT(0)
+#define CDNS_XSPI_POLL_TIMEOUT_US 1000
+#define CDNS_XSPI_POLL_DELAY_US 10
+
/* Marvell clock config register */
#define CDNS_MRVL_XSPI_CLK_CTRL_AUX_REG 0x2020
#define CDNS_MRVL_XSPI_CLK_ENABLE BIT(0)
#define CDNS_MRVL_XSPI_CLK_DIV GENMASK(4, 1)
+
/* Marvell MSI-X clear interrupt register */
#define CDNS_MRVL_XSPI_SPIX_INTR_AUX 0x2000
#define CDNS_MRVL_MSIX_CLEAR_IRQ 0x01
+#define SPIX_XFER_FUNC_CTRL 0x210
+#define SPIX_XFER_FUNC_CTRL_READ_DATA(i) (0x000 + 8 * (i))
+
/* Marvell clock macros */
#define CDNS_MRVL_XSPI_CLOCK_IO_HZ 800000000
#define CDNS_MRVL_XSPI_CLOCK_DIVIDED(div) ((CDNS_MRVL_XSPI_CLOCK_IO_HZ) / (div))
+/* Marvell XFER registers */
+#define XFER_SOFT_RESET BIT(11)
+#define XFER_CS_N_HOLD GENMASK(9, 6)
+#define XFER_RECEIVE_ENABLE BIT(4)
+#define XFER_FUNC_ENABLE BIT(3)
+#define XFER_CLK_CAPTURE_POL BIT(2)
+#define XFER_CLK_DRIVE_POL BIT(1)
+#define XFER_FUNC_START BIT(0)
+
+#define XFER_QWORD_COUNT 32
+#define XFER_QWORD_BYTECOUNT 8
+
enum cdns_xspi_stig_instr_type {
CDNS_XSPI_STIG_INSTR_TYPE_0,
CDNS_XSPI_STIG_INSTR_TYPE_1,
@@ -256,6 +275,7 @@ struct cdns_xspi_dev {
void __iomem *iobase;
void __iomem *auxbase;
void __iomem *sdmabase;
+ void __iomem *xferbase;
int irq;
int cur_cs;
@@ -270,6 +290,9 @@ struct cdns_xspi_dev {
const void *out_buffer;
u8 hw_num_banks;
+
+ bool xfer_in_progress;
+ int current_xfer_qword;
};
#define MRVL_DEFAULT_CLK 25000000
@@ -884,6 +907,221 @@ static bool cdns_xspi_get_hw_overlay(struct platform_device *pdev)
return (err >= 0);
}
+
+static int cdns_xspi_prepare_generic(int cs, const void *dout, int len, int glue, u32 *cmd_regs)
+{
+ u8 *data = (u8 *)dout;
+ int i;
+ int data_counter = 0;
+
+ memset(cmd_regs, 0x00, 6*4);
+
+ if (len > 7) {
+ for (i = (len >= 10 ? 2 : len - 8); i >= 0 ; i--)
+ cmd_regs[3] |= data[data_counter++] << (8*i);
+ }
+ if (len > 3) {
+ for (i = (len >= 7 ? 3 : len - 4); i >= 0; i--)
+ cmd_regs[2] |= data[data_counter++] << (8*i);
+ }
+ for (i = (len >= 3 ? 2 : len - 1); i >= 0 ; i--)
+ cmd_regs[1] |= data[data_counter++] << (8 + 8*i);
+
+ cmd_regs[1] |= 96;
+ cmd_regs[3] |= len << 24;
+ cmd_regs[4] |= cs << 12;
+
+ if (glue == 1)
+ cmd_regs[4] |= 1 << 28;
+
+ return 0;
+}
+
+unsigned char reverse_bits(unsigned char num)
+{
+ unsigned int count = sizeof(num) * 8 - 1;
+ unsigned int reverse_num = num;
+
+ num >>= 1;
+ while (num) {
+ reverse_num <<= 1;
+ reverse_num |= num & 1;
+ num >>= 1;
+ count--;
+ }
+ reverse_num <<= count;
+ return reverse_num;
+}
+
+static void cdns_xspi_read_single_qword(struct cdns_xspi_dev *cdns_xspi, u8 **buffer)
+{
+ u64 d = readq(cdns_xspi->xferbase +
+ SPIX_XFER_FUNC_CTRL_READ_DATA(cdns_xspi->current_xfer_qword));
+ u8 *ptr = (u8 *)&d;
+ int k;
+
+ for (k = 0; k < 8; k++) {
+ u8 val = reverse_bits((ptr[k]));
+ **buffer = val;
+ *buffer = *buffer + 1;
+ }
+
+ cdns_xspi->current_xfer_qword++;
+ cdns_xspi->current_xfer_qword %= XFER_QWORD_COUNT;
+}
+
+static void cdns_xspi_finish_read(struct cdns_xspi_dev *cdns_xspi, u8 **buffer, u32 data_count)
+{
+ u64 d = readq(cdns_xspi->xferbase +
+ SPIX_XFER_FUNC_CTRL_READ_DATA(cdns_xspi->current_xfer_qword));
+ u8 *ptr = (u8 *)&d;
+ int k;
+
+ for (k = 0; k < data_count % XFER_QWORD_BYTECOUNT; k++) {
+ u8 val = reverse_bits((ptr[k]));
+ **buffer = val;
+ *buffer = *buffer + 1;
+ }
+
+ cdns_xspi->current_xfer_qword++;
+ cdns_xspi->current_xfer_qword %= XFER_QWORD_COUNT;
+}
+
+static int cdns_xspi_prepare_transfer(int cs, int dir, int len, u32 *cmd_regs)
+{
+ memset(cmd_regs, 0x00, 6*4);
+
+ cmd_regs[1] |= 127;
+ cmd_regs[2] |= len << 16;
+ cmd_regs[4] |= dir << 4; //dir = 0 read, dir =1 write
+ cmd_regs[4] |= cs << 12;
+
+ return 0;
+}
+
+bool cdns_xspi_stig_ready(struct cdns_xspi_dev *cdns_xspi, bool sleep)
+{
+ u32 ctrl_stat;
+
+ return readl_relaxed_poll_timeout
+ (cdns_xspi->iobase + CDNS_XSPI_CTRL_STATUS_REG,
+ ctrl_stat,
+ ((ctrl_stat & BIT(3)) == 0),
+ sleep ? CDNS_XSPI_POLL_DELAY_US : 0,
+ sleep ? CDNS_XSPI_POLL_TIMEOUT_US : 0);
+}
+
+bool cdns_xspi_sdma_ready(struct cdns_xspi_dev *cdns_xspi, bool sleep)
+{
+ u32 ctrl_stat;
+
+ return readl_relaxed_poll_timeout
+ (cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG,
+ ctrl_stat,
+ (ctrl_stat & CDNS_XSPI_SDMA_TRIGGER),
+ sleep ? CDNS_XSPI_POLL_DELAY_US : 0,
+ sleep ? CDNS_XSPI_POLL_TIMEOUT_US : 0);
+}
+
+int cdns_xspi_transfer_one_message_b0(struct spi_controller *master,
+ struct spi_message *m)
+{
+ struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(master);
+ struct spi_device *spi = m->spi;
+ struct spi_transfer *t = NULL;
+
+ const int max_len = XFER_QWORD_BYTECOUNT * XFER_QWORD_COUNT;
+ int current_cycle_count;
+ int cs = spi->chip_select;
+ int cs_change = 0;
+
+ /* Enable xfer state machine */
+ if (!cdns_xspi->xfer_in_progress) {
+ u32 xfer_control = readl(cdns_xspi->xferbase + SPIX_XFER_FUNC_CTRL);
+
+ cdns_xspi->current_xfer_qword = 0;
+ cdns_xspi->xfer_in_progress = true;
+ xfer_control |= (XFER_RECEIVE_ENABLE |
+ XFER_CLK_CAPTURE_POL |
+ XFER_FUNC_START |
+ XFER_SOFT_RESET |
+ FIELD_PREP(XFER_CS_N_HOLD, (1 << cs)));
+ xfer_control &= ~(XFER_FUNC_ENABLE | XFER_CLK_DRIVE_POL);
+ writel(xfer_control, cdns_xspi->xferbase + SPIX_XFER_FUNC_CTRL);
+ }
+
+ list_for_each_entry(t, &m->transfers, transfer_list) {
+ u8 *txd = (u8 *) t->tx_buf;
+ u8 *rxd = (u8 *) t->rx_buf;
+ u8 data[10];
+ u32 cmd_regs[6];
+
+ if (!txd)
+ txd = data;
+
+ cdns_xspi->in_buffer = txd + 1;
+ cdns_xspi->out_buffer = txd + 1;
+
+ while (t->len) {
+
+ current_cycle_count = t->len > max_len ? max_len : t->len;
+
+ if (current_cycle_count < 10) {
+ cdns_xspi_prepare_generic(cs, txd, current_cycle_count,
+ false, cmd_regs);
+ cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
+ if (cdns_xspi_stig_ready(cdns_xspi, true))
+ return -EIO;
+ } else {
+ cdns_xspi_prepare_generic(cs, txd, 1, true, cmd_regs);
+ cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
+ cdns_xspi_prepare_transfer(cs, 1, current_cycle_count - 1,
+ cmd_regs);
+ cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
+ if (cdns_xspi_sdma_ready(cdns_xspi, true))
+ return -EIO;
+ cdns_xspi_sdma_handle(cdns_xspi);
+ if (cdns_xspi_stig_ready(cdns_xspi, true))
+ return -EIO;
+
+ cdns_xspi->in_buffer += current_cycle_count;
+ cdns_xspi->out_buffer += current_cycle_count;
+ }
+
+ if (rxd) {
+ int j;
+
+ for (j = 0; j < current_cycle_count / 8; j++)
+ cdns_xspi_read_single_qword(cdns_xspi, &rxd);
+ cdns_xspi_finish_read(cdns_xspi, &rxd, current_cycle_count);
+ } else {
+ cdns_xspi->current_xfer_qword += current_cycle_count /
+ XFER_QWORD_BYTECOUNT;
+ if (current_cycle_count % XFER_QWORD_BYTECOUNT)
+ cdns_xspi->current_xfer_qword++;
+
+ cdns_xspi->current_xfer_qword %= XFER_QWORD_COUNT;
+ }
+ cs_change = t->cs_change;
+ t->len -= current_cycle_count;
+ }
+ }
+
+ if (!cs_change) {
+ u32 xfer_control = readl(cdns_xspi->xferbase + SPIX_XFER_FUNC_CTRL);
+
+ xfer_control &= ~(XFER_RECEIVE_ENABLE |
+ XFER_SOFT_RESET);
+ writel(xfer_control, cdns_xspi->xferbase + SPIX_XFER_FUNC_CTRL);
+ cdns_xspi->xfer_in_progress = false;
+ }
+
+ m->status = 0;
+ spi_finalize_current_message(master);
+
+ return 0;
+}
+
static int cdns_xspi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -948,6 +1186,16 @@ static int cdns_xspi_probe(struct platform_device *pdev)
return PTR_ERR(cdns_xspi->auxbase);
}
+ if (hw_overlay) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
+ cdns_xspi->xferbase = devm_ioremap_resource(dev, res);
+ if (IS_ERR(cdns_xspi->xferbase)) {
+ dev_info(dev, "XFER register base not found, set it\n");
+ // For compatibility with older firmware
+ cdns_xspi->xferbase = cdns_xspi->iobase + 0x8000;
+ }
+ }
+
cdns_xspi->irq = platform_get_irq(pdev, 0);
if (cdns_xspi->irq < 0)
return -ENXIO;
@@ -962,6 +1210,7 @@ static int cdns_xspi_probe(struct platform_device *pdev)
if (hw_overlay) {
cdns_mrvl_xspi_setup_clock(cdns_xspi, MRVL_DEFAULT_CLK);
cdns_xspi_configure_phy(cdns_xspi);
+ host->transfer_one_message = cdns_xspi_transfer_one_message_b0;
}
cdns_xspi_print_phy_config(cdns_xspi);
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v2 27/27] kselftest/riscv: kselftest for user mode cfi
From: Muhammad Usama Anjum @ 2024-03-29 19:50 UTC (permalink / raw)
To: Deepak Gupta, paul.walmsley, rick.p.edgecombe, broonie,
Szabolcs.Nagy, kito.cheng, keescook, ajones, conor.dooley, cleger,
atishp, alex, bjorn, alexghiti, samuel.holland, palmer, conor,
linux-doc, linux-riscv, linux-kernel, devicetree, linux-mm,
linux-arch, linux-kselftest
Cc: Muhammad Usama Anjum, corbet, tech-j-ext, palmer, aou, robh+dt,
krzysztof.kozlowski+dt, oleg, akpm, arnd, ebiederm, Liam.Howlett,
vbabka, lstoakes, shuah, brauner, andy.chiu, jerry.shih,
hankuan.chen, greentime.hu, evan, xiao.w.wang, charlie, apatel,
mchitale, dbarboza, sameo, shikemeng, willy, vincent.chen, guoren,
samitolvanen, songshuaishuai, gerg, heiko, bhe, jeeheng.sia, cyy,
maskray, ancientmodern4, mathis.salmen, cuiyunhui, bgray, mpe,
baruch, alx, david, catalin.marinas, revest, josh, shr, deller,
omosnace, ojeda, jhubbard
In-Reply-To: <20240329044459.3990638-28-debug@rivosinc.com>
On 3/29/24 9:44 AM, Deepak Gupta wrote:
> Adds kselftest for RISC-V control flow integrity implementation for user
> mode. There is not a lot going on in kernel for enabling landing pad for
> user mode. Thus kselftest simply enables landing pad for the binary and
> a signal handler is registered for SIGSEGV. Any control flow violation are
> reported as SIGSEGV with si_code = SEGV_CPERR. Test will fail on recieving
> any SEGV_CPERR. Shadow stack part has more changes in kernel and thus there
> are separate tests for that
> - enable and disable
> - Exercise `map_shadow_stack` syscall
> - `fork` test to make sure COW works for shadow stack pages
> - gup tests
> As of today kernel uses FOLL_FORCE when access happens to memory via
> /proc/<pid>/mem. Not breaking that for shadow stack
> - signal test. Make sure signal delivery results in token creation on
> shadow stack and consumes (and verifies) token on sigreturn
> - shadow stack protection test. attempts to write using regular store
> instruction on shadow stack memory must result in access faults
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> ---
> tools/testing/selftests/riscv/Makefile | 2 +-
> tools/testing/selftests/riscv/cfi/Makefile | 10 +
> .../testing/selftests/riscv/cfi/cfi_rv_test.h | 85 ++++
> .../selftests/riscv/cfi/riscv_cfi_test.c | 91 +++++
> .../testing/selftests/riscv/cfi/shadowstack.c | 376 ++++++++++++++++++
> .../testing/selftests/riscv/cfi/shadowstack.h | 39 ++
Please add generated binaries in the .gitignore files.
> 6 files changed, 602 insertions(+), 1 deletion(-)
> create mode 100644 tools/testing/selftests/riscv/cfi/Makefile
> create mode 100644 tools/testing/selftests/riscv/cfi/cfi_rv_test.h
> create mode 100644 tools/testing/selftests/riscv/cfi/riscv_cfi_test.c
> create mode 100644 tools/testing/selftests/riscv/cfi/shadowstack.c
> create mode 100644 tools/testing/selftests/riscv/cfi/shadowstack.h
>
> diff --git a/tools/testing/selftests/riscv/Makefile b/tools/testing/selftests/riscv/Makefile
> index 4a9ff515a3a0..867e5875b7ce 100644
> --- a/tools/testing/selftests/riscv/Makefile
> +++ b/tools/testing/selftests/riscv/Makefile
> @@ -5,7 +5,7 @@
> ARCH ?= $(shell uname -m 2>/dev/null || echo not)
>
> ifneq (,$(filter $(ARCH),riscv))
> -RISCV_SUBTARGETS ?= hwprobe vector mm
> +RISCV_SUBTARGETS ?= hwprobe vector mm cfi
> else
> RISCV_SUBTARGETS :=
> endif
> diff --git a/tools/testing/selftests/riscv/cfi/Makefile b/tools/testing/selftests/riscv/cfi/Makefile
> new file mode 100644
> index 000000000000..77f12157fa29
> --- /dev/null
> +++ b/tools/testing/selftests/riscv/cfi/Makefile
> @@ -0,0 +1,10 @@
> +CFLAGS += -I$(top_srcdir)/tools/include
> +
> +CFLAGS += -march=rv64gc_zicfilp_zicfiss
> +
> +TEST_GEN_PROGS := cfitests
> +
> +include ../../lib.mk
> +
> +$(OUTPUT)/cfitests: riscv_cfi_test.c shadowstack.c
> + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^
> diff --git a/tools/testing/selftests/riscv/cfi/cfi_rv_test.h b/tools/testing/selftests/riscv/cfi/cfi_rv_test.h
> new file mode 100644
> index 000000000000..27267a2e1008
> --- /dev/null
> +++ b/tools/testing/selftests/riscv/cfi/cfi_rv_test.h
> @@ -0,0 +1,85 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef SELFTEST_RISCV_CFI_H
> +#define SELFTEST_RISCV_CFI_H
> +#include <stddef.h>
> +#include <sys/types.h>
> +#include "shadowstack.h"
> +
> +#define RISCV_CFI_SELFTEST_COUNT RISCV_SHADOW_STACK_TESTS
> +
> +#define CHILD_EXIT_CODE_SSWRITE 10
> +#define CHILD_EXIT_CODE_SIG_TEST 11
> +
> +#define BAD_POINTER (NULL)
> +
> +#define my_syscall5(num, arg1, arg2, arg3, arg4, arg5) \
> +({ \
> + register long _num __asm__ ("a7") = (num); \
> + register long _arg1 __asm__ ("a0") = (long)(arg1); \
> + register long _arg2 __asm__ ("a1") = (long)(arg2); \
> + register long _arg3 __asm__ ("a2") = (long)(arg3); \
> + register long _arg4 __asm__ ("a3") = (long)(arg4); \
> + register long _arg5 __asm__ ("a4") = (long)(arg5); \
> + \
> + __asm__ volatile ( \
> + "ecall\n" \
> + : "+r"(_arg1) \
> + : "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \
> + "r"(_num) \
> + : "memory", "cc" \
> + ); \
> + _arg1; \
> +})
> +
> +#define my_syscall3(num, arg1, arg2, arg3) \
> +({ \
> + register long _num __asm__ ("a7") = (num); \
> + register long _arg1 __asm__ ("a0") = (long)(arg1); \
> + register long _arg2 __asm__ ("a1") = (long)(arg2); \
> + register long _arg3 __asm__ ("a2") = (long)(arg3); \
> + \
> + __asm__ volatile ( \
> + "ecall\n" \
> + : "+r"(_arg1) \
> + : "r"(_arg2), "r"(_arg3), \
> + "r"(_num) \
> + : "memory", "cc" \
> + ); \
> + _arg1; \
> +})
> +
> +#ifndef __NR_prctl
> +#define __NR_prctl 167
> +#endif
> +
> +#ifndef __NR_map_shadow_stack
> +#define __NR_map_shadow_stack 453
> +#endif
> +
> +#define CSR_SSP 0x011
> +
> +#ifdef __ASSEMBLY__
> +#define __ASM_STR(x) x
> +#else
> +#define __ASM_STR(x) #x
> +#endif
> +
> +#define csr_read(csr) \
> +({ \
> + register unsigned long __v; \
> + __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
> + : "=r" (__v) : \
> + : "memory"); \
> + __v; \
> +})
> +
> +#define csr_write(csr, val) \
> +({ \
> + unsigned long __v = (unsigned long) (val); \
> + __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
> + : : "rK" (__v) \
> + : "memory"); \
> +})
> +
> +#endif
> diff --git a/tools/testing/selftests/riscv/cfi/riscv_cfi_test.c b/tools/testing/selftests/riscv/cfi/riscv_cfi_test.c
> new file mode 100644
> index 000000000000..c116ae4bb358
> --- /dev/null
> +++ b/tools/testing/selftests/riscv/cfi/riscv_cfi_test.c
> @@ -0,0 +1,91 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#include "../../kselftest.h"
> +#include <signal.h>
> +#include <asm/ucontext.h>
> +#include <linux/prctl.h>
> +#include "cfi_rv_test.h"
> +
> +/* do not optimize cfi related test functions */
> +#pragma GCC push_options
> +#pragma GCC optimize("O0")
> +
> +#define SEGV_CPERR 10 /* control protection fault */
> +
> +void sigsegv_handler(int signum, siginfo_t *si, void *uc)
> +{
> + struct ucontext *ctx = (struct ucontext *) uc;
> +
> + if (si->si_code == SEGV_CPERR) {
> + printf("Control flow violation happened somewhere\n");
> + printf("pc where violation happened %lx\n", ctx->uc_mcontext.gregs[0]);
> + exit(-1);
> + }
> +
> + /* null pointer deref */
> + if (si->si_addr == BAD_POINTER)
> + exit(CHILD_EXIT_CODE_NULL_PTR_DEREF);
> +
> + /* shadow stack write case */
> + exit(CHILD_EXIT_CODE_SSWRITE);
> +}
> +
> +int lpad_enable(void)
> +{
> + int ret = 0;
> +
> + ret = my_syscall5(__NR_prctl, PR_SET_INDIR_BR_LP_STATUS, PR_INDIR_BR_LP_ENABLE, 0, 0, 0);
> +
> + return ret;
> +}
> +
> +bool register_signal_handler(void)
> +{
> + struct sigaction sa = {};
> +
> + sa.sa_sigaction = sigsegv_handler;
> + sa.sa_flags = SA_SIGINFO;
> + if (sigaction(SIGSEGV, &sa, NULL)) {
> + printf("registering signal handler for landing pad violation failed\n");
> + return false;
> + }
> +
> + return true;
> +}
> +
> +int main(int argc, char *argv[])
> +{
> + int ret = 0;
> + unsigned long lpad_status = 0;
> +
> + ksft_print_header();
> +
> + ksft_set_plan(RISCV_CFI_SELFTEST_COUNT);
> +
> + ksft_print_msg("starting risc-v tests\n");
> +
> + /*
> + * Landing pad test. Not a lot of kernel changes to support landing
> + * pad for user mode except lighting up a bit in senvcfg via a prctl
> + * Enable landing pad through out the execution of test binary
> + */
> + ret = my_syscall5(__NR_prctl, PR_GET_INDIR_BR_LP_STATUS, &lpad_status, 0, 0, 0);
> + if (ret)
> + ksft_exit_skip("Get landing pad status failed with %d\n", ret);
> +
> + ret = lpad_enable();
> +
> + if (ret)
> + ksft_exit_skip("Enabling landing pad failed with %d\n", ret);
> +
> + if (!register_signal_handler())
> + ksft_exit_skip("registering signal handler for SIGSEGV failed\n");
> +
> + ksft_print_msg("landing pad enabled for binary\n");
> + ksft_print_msg("starting risc-v shadow stack tests\n");
> + execute_shadow_stack_tests();
> +
> + ksft_finished();
> +}
> +
> +#pragma GCC pop_options
> diff --git a/tools/testing/selftests/riscv/cfi/shadowstack.c b/tools/testing/selftests/riscv/cfi/shadowstack.c
> new file mode 100644
> index 000000000000..126654801bed
> --- /dev/null
> +++ b/tools/testing/selftests/riscv/cfi/shadowstack.c
> @@ -0,0 +1,376 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#include "../../kselftest.h"
> +#include <sys/wait.h>
> +#include <signal.h>
> +#include <fcntl.h>
> +#include <unistd.h>
> +#include <sys/mman.h>
> +#include "shadowstack.h"
> +#include "cfi_rv_test.h"
> +
> +/* do not optimize shadow stack related test functions */
> +#pragma GCC push_options
> +#pragma GCC optimize("O0")
> +
> +void zar(void)
> +{
> + unsigned long ssp = 0, swaped_val = 0;
> +
> + ssp = csr_read(CSR_SSP);
> + printf("inside %s and shadow stack ptr is %lx\n", __func__, ssp);
> +}
> +
> +void bar(void)
> +{
> + printf("inside %s\n", __func__);
> + zar();
> +}
> +
> +void foo(void)
> +{
> + printf("inside %s\n", __func__);
> + bar();
> +}
> +
> +void zar_child(void)
> +{
> + unsigned long ssp = 0;
> +
> + ssp = csr_read(CSR_SSP);
> + printf("inside %s and shadow stack ptr is %lx\n", __func__, ssp);
> +}
> +
> +void bar_child(void)
> +{
> + printf("inside %s\n", __func__);
> + zar_child();
> +}
> +
> +void foo_child(void)
> +{
> + printf("inside %s\n", __func__);
> + bar_child();
> +}
> +
> +typedef void (call_func_ptr)(void);
> +/*
> + * call couple of functions to test push pop.
> + */
> +int shadow_stack_call_tests(call_func_ptr fn_ptr, bool parent)
> +{
> + if (parent)
> + printf("call test for parent\n");
> + else
> + printf("call test for child\n");
> +
> + (fn_ptr)();
> +
> + return 0;
> +}
> +
> +bool enable_disable_check(unsigned long test_num, void *ctx)
> +{
> + int ret = 0;
> +
> + if (!my_syscall5(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, PR_SHADOW_STACK_ENABLE, 0, 0, 0)) {
> + printf("Shadow stack was enabled\n");
> + shadow_stack_call_tests(&foo, true);
> +
> + ret = my_syscall5(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, 0, 0, 0, 0);
> + if (ret)
> + ksft_test_result_fail("shadow stack disable failed\n");
> + } else {
> + ksft_test_result_fail("shadow stack enable failed\n");
> + ret = -EINVAL;
> + }
> +
> + return ret ? false : true;
> +}
> +
> +/* forks a thread, and ensure shadow stacks fork out */
> +bool shadow_stack_fork_test(unsigned long test_num, void *ctx)
> +{
> + int pid = 0, child_status = 0, parent_pid = 0;
> +
> + printf("exercising shadow stack fork test\n");
> +
> + if (my_syscall5(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, PR_SHADOW_STACK_ENABLE, 0, 0, 0)) {
> + printf("shadow stack enable prctl failed\n");
> + return false;
> + }
> +
> + parent_pid = getpid();
> + pid = fork();
> +
> + if (pid) {
> + printf("Parent pid %d and child pid %d\n", parent_pid, pid);
> + shadow_stack_call_tests(&foo, true);
> + } else
> + shadow_stack_call_tests(&foo_child, false);
> +
> + if (pid) {
> + printf("waiting on child to finish\n");
> + wait(&child_status);
> + } else {
> + /* exit child gracefully */
> + exit(0);
> + }
> +
> + if (pid && WIFSIGNALED(child_status)) {
> + printf("child faulted");
> + return false;
> + }
> +
> + /* disable shadow stack again */
> + if (my_syscall5(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, 0, 0, 0, 0)) {
> + printf("shadow stack disable prctl failed\n");
> + return false;
> + }
> +
> + return true;
> +}
> +
> +/* exercise `map_shadow_stack`, pivot to it and call some functions to ensure it works */
> +#define SHADOW_STACK_ALLOC_SIZE 4096
> +bool shadow_stack_map_test(unsigned long test_num, void *ctx)
> +{
> + unsigned long shdw_addr;
> + int ret = 0;
> +
> + shdw_addr = my_syscall3(__NR_map_shadow_stack, NULL, SHADOW_STACK_ALLOC_SIZE, 0);
> +
> + if (((long) shdw_addr) <= 0) {
> + printf("map_shadow_stack failed with error code %d\n", (int) shdw_addr);
> + return false;
> + }
> +
> + ret = munmap((void *) shdw_addr, SHADOW_STACK_ALLOC_SIZE);
> +
> + if (ret) {
> + printf("munmap failed with error code %d\n", ret);
> + return false;
> + }
> +
> + return true;
> +}
> +
> +/*
> + * shadow stack protection tests. map a shadow stack and
> + * validate all memory protections work on it
> + */
> +bool shadow_stack_protection_test(unsigned long test_num, void *ctx)
> +{
> + unsigned long shdw_addr;
> + unsigned long *write_addr = NULL;
> + int ret = 0, pid = 0, child_status = 0;
> +
> + shdw_addr = my_syscall3(__NR_map_shadow_stack, NULL, SHADOW_STACK_ALLOC_SIZE, 0);
> +
> + if (((long) shdw_addr) <= 0) {
> + printf("map_shadow_stack failed with error code %d\n", (int) shdw_addr);
> + return false;
> + }
> +
> + write_addr = (unsigned long *) shdw_addr;
> + pid = fork();
> +
> + /* no child was created, return false */
> + if (pid == -1)
> + return false;
> +
> + /*
> + * try to perform a store from child on shadow stack memory
> + * it should result in SIGSEGV
> + */
> + if (!pid) {
> + /* below write must lead to SIGSEGV */
> + *write_addr = 0xdeadbeef;
> + } else {
> + wait(&child_status);
> + }
> +
> + /* test fail, if 0xdeadbeef present on shadow stack address */
> + if (*write_addr == 0xdeadbeef) {
> + printf("write suceeded\n");
> + return false;
> + }
> +
> + /* if child reached here, then fail */
> + if (!pid) {
> + printf("child reached unreachable state\n");
> + return false;
> + }
> +
> + /* if child exited via signal handler but not for write on ss */
> + if (WIFEXITED(child_status) &&
> + WEXITSTATUS(child_status) != CHILD_EXIT_CODE_SSWRITE) {
> + printf("child wasn't signaled for write on shadow stack\n");
> + return false;
> + }
> +
> + ret = munmap(write_addr, SHADOW_STACK_ALLOC_SIZE);
> + if (ret) {
> + printf("munmap failed with error code %d\n", ret);
> + return false;
> + }
> +
> + return true;
> +}
> +
> +#define SS_MAGIC_WRITE_VAL 0xbeefdead
> +
> +int gup_tests(int mem_fd, unsigned long *shdw_addr)
> +{
> + unsigned long val = 0;
> +
> + lseek(mem_fd, (unsigned long)shdw_addr, SEEK_SET);
> + if (read(mem_fd, &val, sizeof(val)) < 0) {
> + printf("reading shadow stack mem via gup failed\n");
> + return 1;
> + }
> +
> + val = SS_MAGIC_WRITE_VAL;
> + lseek(mem_fd, (unsigned long)shdw_addr, SEEK_SET);
> + if (write(mem_fd, &val, sizeof(val)) < 0) {
> + printf("writing shadow stack mem via gup failed\n");
> + return 1;
> + }
> +
> + if (*shdw_addr != SS_MAGIC_WRITE_VAL) {
> + printf("GUP write to shadow stack memory didn't happen\n");
> + return 1;
> + }
> +
> + return 0;
> +}
> +
> +bool shadow_stack_gup_tests(unsigned long test_num, void *ctx)
> +{
> + unsigned long shdw_addr = 0;
> + unsigned long *write_addr = NULL;
> + int fd = 0;
> + bool ret = false;
> +
> + shdw_addr = my_syscall3(__NR_map_shadow_stack, NULL, SHADOW_STACK_ALLOC_SIZE, 0);
> +
> + if (((long) shdw_addr) <= 0) {
> + printf("map_shadow_stack failed with error code %d\n", (int) shdw_addr);
> + return false;
> + }
> +
> + write_addr = (unsigned long *) shdw_addr;
> +
> + fd = open("/proc/self/mem", O_RDWR);
> + if (fd == -1)
> + return false;
> +
> + if (gup_tests(fd, write_addr)) {
> + printf("gup tests failed\n");
> + goto out;
> + }
> +
> + ret = true;
> +out:
> + if (shdw_addr && munmap(write_addr, SHADOW_STACK_ALLOC_SIZE)) {
> + printf("munmap failed with error code %d\n", ret);
> + ret = false;
> + }
> +
> + return ret;
> +}
> +
> +volatile bool break_loop;
> +
> +void sigusr1_handler(int signo)
> +{
> + printf("In sigusr1 handler\n");
> + break_loop = true;
> +}
> +
> +bool sigusr1_signal_test(void)
> +{
> + if (signal(SIGUSR1, sigusr1_handler) == SIG_ERR) {
> + printf("registerting sigusr1 handler failed\n");
> + return false;
> + }
> +
> + return true;
> +}
> +/*
> + * shadow stack signal test. shadow stack must be enabled.
> + * register a signal, fork another thread which is waiting
> + * on signal. Send a signal from parent to child, verify
> + * that signal was received by child. If not test fails
> + */
> +bool shadow_stack_signal_test(unsigned long test_num, void *ctx)
> +{
> + int pid = 0, child_status = 0;
> + unsigned long ssp = 0;
> +
> + if (my_syscall5(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, PR_SHADOW_STACK_ENABLE, 0, 0, 0)) {
> + printf("shadow stack enable prctl failed\n");
> + return false;
> + }
> +
> + pid = fork();
> +
> + if (pid == -1) {
> + printf("signal test: fork failed\n");
> + goto out;
> + }
> +
> + if (pid == 0) {
> + /* this should be caught by signal handler and do an exit */
> + if (!sigusr1_signal_test()) {
> + printf("sigusr1_signal_test failed\n");
> + exit(-1);
> + }
> +
> + while (!break_loop)
> + sleep(1);
> +
> + exit(11);
> + /* child shouldn't go beyond here */
> + }
> + /* send SIGUSR1 to child */
> + kill(pid, SIGUSR1);
> + wait(&child_status);
> +
> +out:
> + if (my_syscall5(__NR_prctl, PR_SET_SHADOW_STACK_STATUS, 0, 0, 0, 0)) {
> + printf("shadow stack disable prctl failed\n");
> + return false;
> + }
> +
> + return (WIFEXITED(child_status) &&
> + WEXITSTATUS(child_status) == 11);
> +}
> +
> +int execute_shadow_stack_tests(void)
> +{
> + int ret = 0;
> + unsigned long test_count = 0;
> + unsigned long shstk_status = 0;
> +
> + printf("Executing RISC-V shadow stack self tests\n");
> +
> + ret = my_syscall5(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, &shstk_status, 0, 0, 0);
> +
> + if (ret != 0)
> + ksft_exit_skip("Get shadow stack status failed with %d\n", ret);
> +
> + /*
> + * If we are here that means get shadow stack status succeeded and
> + * thus shadow stack support is baked in the kernel.
> + */
> + while (test_count < ARRAY_SIZE(shstk_tests)) {
> + ksft_test_result((*shstk_tests[test_count].t_func)(test_count, NULL),
> + shstk_tests[test_count].name);
> + test_count++;
> + }
> +
> + return 0;
> +}
> +
> +#pragma GCC pop_options
> diff --git a/tools/testing/selftests/riscv/cfi/shadowstack.h b/tools/testing/selftests/riscv/cfi/shadowstack.h
> new file mode 100644
> index 000000000000..92cb0752238d
> --- /dev/null
> +++ b/tools/testing/selftests/riscv/cfi/shadowstack.h
> @@ -0,0 +1,39 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef SELFTEST_SHADOWSTACK_TEST_H
> +#define SELFTEST_SHADOWSTACK_TEST_H
> +#include <stddef.h>
> +#include <linux/prctl.h>
> +
> +/*
> + * a cfi test returns true for success or false for fail
> + * takes a number for test number to index into array and void pointer.
> + */
> +typedef bool (*shstk_test_func)(unsigned long test_num, void *);
> +
> +struct shadow_stack_tests {
> + char *name;
> + shstk_test_func t_func;
> +};
> +
> +bool enable_disable_check(unsigned long test_num, void *ctx);
> +bool shadow_stack_fork_test(unsigned long test_num, void *ctx);
> +bool shadow_stack_map_test(unsigned long test_num, void *ctx);
> +bool shadow_stack_protection_test(unsigned long test_num, void *ctx);
> +bool shadow_stack_gup_tests(unsigned long test_num, void *ctx);
> +bool shadow_stack_signal_test(unsigned long test_num, void *ctx);
> +
> +static struct shadow_stack_tests shstk_tests[] = {
> + { "enable disable\n", enable_disable_check },
> + { "shstk fork test\n", shadow_stack_fork_test },
> + { "map shadow stack syscall\n", shadow_stack_map_test },
> + { "shadow stack gup tests\n", shadow_stack_gup_tests },
> + { "shadow stack signal tests\n", shadow_stack_signal_test},
> + { "memory protections of shadow stack memory\n", shadow_stack_protection_test }
> +};
> +
> +#define RISCV_SHADOW_STACK_TESTS ARRAY_SIZE(shstk_tests)
> +
> +int execute_shadow_stack_tests(void);
> +
> +#endif
--
BR,
Muhammad Usama Anjum
^ permalink raw reply
* Re: [PATCH v2 27/27] kselftest/riscv: kselftest for user mode cfi
From: Deepak Gupta @ 2024-03-29 20:02 UTC (permalink / raw)
To: Muhammad Usama Anjum
Cc: paul.walmsley, rick.p.edgecombe, broonie, Szabolcs.Nagy,
kito.cheng, keescook, ajones, conor.dooley, cleger, atishp, alex,
bjorn, alexghiti, samuel.holland, palmer, conor, linux-doc,
linux-riscv, linux-kernel, devicetree, linux-mm, linux-arch,
linux-kselftest, corbet, tech-j-ext, palmer, aou, robh+dt,
krzysztof.kozlowski+dt, oleg, akpm, arnd, ebiederm, Liam.Howlett,
vbabka, lstoakes, shuah, brauner, andy.chiu, jerry.shih,
hankuan.chen, greentime.hu, evan, xiao.w.wang, charlie, apatel,
mchitale, dbarboza, sameo, shikemeng, willy, vincent.chen, guoren,
samitolvanen, songshuaishuai, gerg, heiko, bhe, jeeheng.sia, cyy,
maskray, ancientmodern4, mathis.salmen, cuiyunhui, bgray, mpe,
baruch, alx, david, catalin.marinas, revest, josh, shr, deller,
omosnace, ojeda, jhubbard
In-Reply-To: <4b38393a-f69d-4a77-a896-b6cd42c7edcf@collabora.com>
On Fri, Mar 29, 2024 at 12:50 PM Muhammad Usama Anjum
<usama.anjum@collabora.com> wrote:
>
> On 3/29/24 9:44 AM, Deepak Gupta wrote:
> > Adds kselftest for RISC-V control flow integrity implementation for user
> > mode. There is not a lot going on in kernel for enabling landing pad for
> > user mode. Thus kselftest simply enables landing pad for the binary and
> > a signal handler is registered for SIGSEGV. Any control flow violation are
> > reported as SIGSEGV with si_code = SEGV_CPERR. Test will fail on recieving
> > any SEGV_CPERR. Shadow stack part has more changes in kernel and thus there
> > are separate tests for that
> > - enable and disable
> > - Exercise `map_shadow_stack` syscall
> > - `fork` test to make sure COW works for shadow stack pages
> > - gup tests
> > As of today kernel uses FOLL_FORCE when access happens to memory via
> > /proc/<pid>/mem. Not breaking that for shadow stack
> > - signal test. Make sure signal delivery results in token creation on
> > shadow stack and consumes (and verifies) token on sigreturn
> > - shadow stack protection test. attempts to write using regular store
> > instruction on shadow stack memory must result in access faults
> >
> > Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> > ---
> > tools/testing/selftests/riscv/Makefile | 2 +-
> > tools/testing/selftests/riscv/cfi/Makefile | 10 +
> > .../testing/selftests/riscv/cfi/cfi_rv_test.h | 85 ++++
> > .../selftests/riscv/cfi/riscv_cfi_test.c | 91 +++++
> > .../testing/selftests/riscv/cfi/shadowstack.c | 376 ++++++++++++++++++
> > .../testing/selftests/riscv/cfi/shadowstack.h | 39 ++
> Please add generated binaries in the .gitignore files.
hmm...
I don't see binary as part of the patch. Which file are you referring
to here being binary?
>
^ permalink raw reply
* [PATCH 0/3] iio: adc: add ADC driver for XuanTie TH1520 SoC
From: wefu @ 2024-03-29 20:01 UTC (permalink / raw)
To: jszhang, guoren, conor, robh, krzysztof.kozlowski+dt,
paul.walmsley, palmer, aou, jic23, lars, andriy.shevchenko,
nuno.sa, marcelo.schmitt, bigunclemax, marius.cristea, fr0st61te,
okan.sahin, marcus.folkesson, schnelle, lee, mike.looijmans
Cc: linux-riscv, devicetree, linux-kernel, linux-iio, Wei Fu
From: Wei Fu <wefu@redhat.com>
This patchset adds initial support for XuanTie TH1520 ADC driver.
This is modified from XuanTie TH1520 Linux_SDK_V1.4.2(linux v5.10.113)
The original author is Fugang Duan <duanfugang.dfg@linux.alibaba.com>
Wei Fu (3):
drivers/iio/adc: Add XuanTie TH1520 ADC driver
riscv: dts: thead: Add XuanTie TH1520 ADC device node
dt-bindings: adc: Document XuanTie TH1520 ADC
.../bindings/iio/adc/thead,th1520.yaml | 52 ++
arch/riscv/boot/dts/thead/th1520.dtsi | 10 +
drivers/iio/adc/Kconfig | 13 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/xuantie-th1520-adc.c | 572 ++++++++++++++++++
drivers/iio/adc/xuantie-th1520-adc.h | 193 ++++++
6 files changed, 841 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/thead,th1520.yaml
create mode 100644 drivers/iio/adc/xuantie-th1520-adc.c
create mode 100644 drivers/iio/adc/xuantie-th1520-adc.h
--
2.44.0
^ permalink raw reply
* [PATCH 1/3] drivers/iio/adc: Add XuanTie TH1520 ADC driver
From: wefu @ 2024-03-29 20:01 UTC (permalink / raw)
To: jszhang, guoren, conor, robh, krzysztof.kozlowski+dt,
paul.walmsley, palmer, aou, jic23, lars, andriy.shevchenko,
nuno.sa, marcelo.schmitt, bigunclemax, marius.cristea, fr0st61te,
okan.sahin, marcus.folkesson, schnelle, lee, mike.looijmans
Cc: linux-riscv, devicetree, linux-kernel, linux-iio, Wei Fu
In-Reply-To: <20240329200241.4122000-1-wefu@redhat.com>
From: Wei Fu <wefu@redhat.com>
Signed-off-by: Wei Fu <wefu@redhat.com>
---
drivers/iio/adc/Kconfig | 13 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/xuantie-th1520-adc.c | 572 +++++++++++++++++++++++++++
drivers/iio/adc/xuantie-th1520-adc.h | 193 +++++++++
4 files changed, 779 insertions(+)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 0d9282fa67f5..9e37ba2a877a 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -1515,4 +1515,17 @@ config XILINX_AMS
The driver can also be built as a module. If so, the module will be called
xilinx-ams.
+config XUANTIE_TH1520_ADC
+ tristate "XuanTie TH1520 ADC driver"
+ depends on OF
+ depends on HAS_IOMEM
+ depends on ARCH_THEAD
+ default y
+ help
+ Say yes here to support for XuanTie TH1520 MPW analog-to-digital
+ converter.
+
+ This driver can also be built as a module. If so, the module will be
+ called xuantie-th1520-adc.
+
endmenu
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index b3c434722364..820e2a136b33 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -135,4 +135,5 @@ obj-$(CONFIG_VIPERBOARD_ADC) += viperboard_adc.o
xilinx-xadc-y := xilinx-xadc-core.o xilinx-xadc-events.o
obj-$(CONFIG_XILINX_XADC) += xilinx-xadc.o
obj-$(CONFIG_XILINX_AMS) += xilinx-ams.o
+obj-$(CONFIG_XUANTIE_TH1520_ADC) += xuantie-th1520-adc.o
obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o
diff --git a/drivers/iio/adc/xuantie-th1520-adc.c b/drivers/iio/adc/xuantie-th1520-adc.c
new file mode 100644
index 000000000000..df0452c2abe7
--- /dev/null
+++ b/drivers/iio/adc/xuantie-th1520-adc.c
@@ -0,0 +1,572 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * XuanTie TH1520 ADC driver
+ *
+ * Copyright (C) 2021-2024 Alibaba Group Holding Limited.
+ * Fugang Duan <duanfugang.dfg@linux.alibaba.com>
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/regulator/consumer.h>
+#include <linux/of_platform.h>
+#include <linux/err.h>
+
+#include <linux/iio/iio.h>
+#include <linux/iio/buffer.h>
+#include <linux/iio/sysfs.h>
+
+#include "xuantie-th1520-adc.h"
+
+static inline void th1520_adc_cfg_init(struct th1520_adc *info)
+{
+ struct th1520_adc_feature *adc_feature = &info->adc_feature;
+
+ /* set default Configuration for ADC controller */
+ adc_feature->selres_sel = TH1520_ADC_SELRES_12BIT;
+ adc_feature->input_mode = TH1520_ADC_SINGLE_ENDED_INPUTS;
+ adc_feature->vol_ref = TH1520_ADC_VOL_VREF;
+ adc_feature->offset_mode = TH1520_ADC_OFFSET_DIS;
+ adc_feature->conv_mode = TH1520_ADC_MODE_SINGLE;
+ adc_feature->clk_sel = TH1520_ADC_FCLK_TYP_1M;
+
+ adc_feature->int_actual = TH1520_ADC_ACTUAL_ALL;
+ adc_feature->int_detal = TH1520_ADC_DETAL_ALL;
+
+ info->ch0_offmeas = 0;
+ info->ch1_offmeas = 0;
+}
+
+static void th1520_adc_reg_set(struct th1520_adc *info)
+{
+ u32 phy_cfg = 0;
+ u32 op_ctrl = 0;
+ struct th1520_adc_feature *adc_feature = &info->adc_feature;
+
+ /* phy_cfg */
+ switch (adc_feature->selres_sel) {
+ case TH1520_ADC_SELRES_6BIT:
+ phy_cfg |= TH1520_ADC_PHY_CFG_SELRES_6BIT;
+ break;
+ case TH1520_ADC_SELRES_8BIT:
+ phy_cfg |= TH1520_ADC_PHY_CFG_SELRES_8BIT;
+ break;
+ case TH1520_ADC_SELRES_10BIT:
+ phy_cfg |= TH1520_ADC_PHY_CFG_SELRES_10BIT;
+ break;
+ case TH1520_ADC_SELRES_12BIT:
+ phy_cfg |= TH1520_ADC_PHY_CFG_SELRES_12BIT;
+ break;
+ default:
+ break;
+ }
+
+ switch (adc_feature->input_mode) {
+ case TH1520_ADC_SINGLE_ENDED_INPUTS:
+ phy_cfg |= TH1520_ADC_PHY_CFG_SELDIFF_SINGLE_ENDED_INPUTS;
+ break;
+ case TH1520_ADC_DIFFERENTIAL_INPUTS:
+ phy_cfg |= TH1520_ADC_PHY_CFG_SELDIFF_DIFFERENTIAL_INPUTS;
+ break;
+ default:
+ break;
+ }
+
+ switch (adc_feature->vol_ref) {
+ case TH1520_ADC_VOL_VREF:
+ phy_cfg |= TH1520_ADC_PHY_CFG_SELBG_EXTERNAL |
+ TH1520_ADC_PHY_CFG_SELREF_EXT;
+ break;
+ case TH1520_ADC_VOL_INTE:
+ phy_cfg |= TH1520_ADC_PHY_CFG_SELBG_INTERNAL |
+ TH1520_ADC_PHY_CFG_SELREF_INTERNAL;
+ break;
+ default:
+ break;
+ }
+
+ /* op_ctrl */
+ switch (adc_feature->conv_mode) {
+ case TH1520_ADC_MODE_SINGLE:
+ op_ctrl |= TH1520_ADC_OP_CTRL_MODE_SINGLE;
+ break;
+ case TH1520_ADC_MODE_CONTINOUS:
+ op_ctrl |= TH1520_ADC_OP_CTRL_MODE_CONTINOUS;
+ break;
+ default:
+ break;
+ }
+
+ writel(phy_cfg, info->regs + TH1520_ADC_PHY_CFG);
+ writel(op_ctrl, info->regs + TH1520_ADC_OP_CTRL);
+
+ writel(TH1520_ADC_PHY_ENCTR, info->regs + TH1520_ADC_PHY_TEST);
+
+ /* disable the irq */
+ writel(0xff, info->regs + TH1520_ADC_INT_CTRL1);
+ writel(0xff, info->regs + TH1520_ADC_INT_CTRL2);
+
+ if (adc_feature->conv_mode == TH1520_ADC_MODE_CONTINOUS)
+ writel(TH1520_ADC_PHY_CTRL_ENADC_EN,
+ info->regs + TH1520_ADC_PHY_CTRL);
+}
+
+static void th1520_adc_fclk_set(struct th1520_adc *info)
+{
+ int fclk_ctrl = 0;
+ int start_time = 0;
+ int sample_time = 0;
+ struct th1520_adc_feature *adc_feature = &info->adc_feature;
+
+ switch (adc_feature->clk_sel) {
+ case TH1520_ADC_FCLK_TYP_1M:
+ fclk_ctrl = TH1520_ADC_FCLK_CTRL_TYP_1M;
+ start_time = TH1520_ADC_START_TIME_TYP_1M;
+ if (adc_feature->selres_sel == TH1520_ADC_SELRES_6BIT)
+ sample_time = TH1520_ADC_SAMPLE_TIME_TYP_6BIT;
+ else if (adc_feature->selres_sel == TH1520_ADC_SELRES_8BIT)
+ sample_time = TH1520_ADC_SAMPLE_TIME_TYP_8BIT;
+ else if (adc_feature->selres_sel == TH1520_ADC_SELRES_10BIT)
+ sample_time = TH1520_ADC_SAMPLE_TIME_TYP_10BIT;
+ else if (adc_feature->selres_sel == TH1520_ADC_SELRES_12BIT)
+ sample_time = TH1520_ADC_SAMPLE_TIME_TYP_12BIT;
+ else {
+ pr_err("[%s,%d]invalid selres select\n",
+ __func__, __LINE__);
+ return;
+ }
+ break;
+ default:
+ break;
+ }
+ writel(fclk_ctrl, info->regs + TH1520_ADC_FCLK_CTRL);
+ writel(start_time, info->regs + TH1520_ADC_START_TIME);
+ writel(sample_time, info->regs + TH1520_ADC_SAMPLE_TIME);
+}
+
+static void th1520_adc_hw_init(struct th1520_adc *info)
+{
+ th1520_adc_reg_set(info);
+ th1520_adc_fclk_set(info);
+}
+
+static const struct iio_chan_spec th1520_adc_iio_channels[] = {
+ TH1520_ADC_CHAN(0, IIO_VOLTAGE),
+ TH1520_ADC_CHAN(1, IIO_VOLTAGE),
+ TH1520_ADC_CHAN(2, IIO_VOLTAGE),
+ TH1520_ADC_CHAN(3, IIO_VOLTAGE),
+ TH1520_ADC_CHAN(4, IIO_VOLTAGE),
+ TH1520_ADC_CHAN(5, IIO_VOLTAGE),
+ TH1520_ADC_CHAN(6, IIO_VOLTAGE),
+ TH1520_ADC_CHAN(7, IIO_VOLTAGE),
+ /* sentinel */
+};
+
+static irqreturn_t th1520_adc_isr(int irq, void *dev_id)
+{
+ struct iio_dev *indio_dev = dev_id;
+ struct th1520_adc *info = iio_priv(indio_dev);
+ /* TBD */
+ complete(&info->completion);
+ return IRQ_HANDLED;
+}
+
+static int th1520_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long mask)
+{
+ int tmp;
+ long ret;
+ struct th1520_adc *info = iio_priv(indio_dev);
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ mutex_lock(&info->mlock);
+
+ if (info->adc_feature.conv_mode == TH1520_ADC_MODE_SINGLE) {
+ uint ievent;
+ uint vld_flag;
+ uint phy_ctrl;
+ uint real_chan;
+ uint op_ctrl = 0;
+ uint single_retry = TH1520_ADC_FIFO_DATA_SIZE;
+
+ op_ctrl = readl(info->regs + TH1520_ADC_OP_CTRL);
+ op_ctrl &= ~TH1520_ADC_OP_CTRL_CH_EN_ALL;
+ op_ctrl |= (BIT(chan->channel + TH1520_ADC_OP_CTRL_CH_EN_0) &
+ TH1520_ADC_OP_CTRL_CH_EN_ALL);
+ writel(op_ctrl, info->regs + TH1520_ADC_OP_CTRL);
+
+ writel(TH1520_ADC_PHY_CTRL_ENADC_EN,
+ info->regs + TH1520_ADC_PHY_CTRL);
+
+ vld_flag = TH1520_ADC_SAMPLE_DATA_CH0_VLD;
+
+ while (single_retry--) {
+ writel(TH1520_ADC_OP_SINGLE_START_EN,
+ info->regs + TH1520_ADC_OP_SINGLE_START);
+ /* wait the sampling result */
+ ret = readl_poll_timeout(info->regs +
+ TH1520_ADC_SAMPLE_DATA,
+ ievent,
+ ievent & vld_flag, 100,
+ TH1520_ADC_TIMEOUT);
+ if (ret)
+ pr_err("wait the sampling timeout\n");
+
+ real_chan =
+ (ievent & TH1520_ADC_SAMPLE_DATA_CH0_NUMBER) >>
+ TH1520_ADC_SAMPLE_DATA_CH0_NUMBER_OFF;
+ if (real_chan == chan->channel)
+ break;
+ }
+
+ phy_ctrl = readl(info->regs + TH1520_ADC_PHY_CTRL);
+ phy_ctrl &= ~TH1520_ADC_PHY_CTRL_ENADC_EN;
+ writel(phy_ctrl, info->regs + TH1520_ADC_PHY_CTRL);
+
+ /* read the sampling data */
+ *val = (ievent & TH1520_ADC_SAMPLE_DATA_CH0) >>
+ TH1520_ADC_SAMPLE_DATA_CH0_OFF;
+ } else {
+ uint ievent;
+ uint vld_flag;
+ uint op_single;
+ uint op_ctrl = 0;
+
+ op_ctrl = readl(info->regs + TH1520_ADC_OP_CTRL);
+ op_ctrl &= ~TH1520_ADC_OP_CTRL_CH_EN_ALL;
+ op_ctrl |= (BIT(chan->channel + TH1520_ADC_OP_CTRL_CH_EN_0) &
+ TH1520_ADC_OP_CTRL_CH_EN_ALL);
+ writel(op_ctrl, info->regs + TH1520_ADC_OP_CTRL);
+
+ op_single = readl(info->regs +
+ TH1520_ADC_OP_SINGLE_START);
+ op_single &= ~TH1520_ADC_OP_SINGLE_START_EN;
+ writel(op_single,
+ info->regs + TH1520_ADC_OP_SINGLE_START);
+
+ vld_flag = TH1520_ADC_SAMPLE_DATA_CH0_VLD |
+ TH1520_ADC_SAMPLE_DATA_CH1_VLD;
+
+ /* wait the sampling result */
+ ret = readl_poll_timeout(info->regs +
+ TH1520_ADC_SAMPLE_DATA,
+ ievent, ievent & vld_flag, 10,
+ TH1520_ADC_TIMEOUT);
+ if (ret)
+ pr_err("wait the sampling timeout\n");
+
+ /* read the sampling data */
+ tmp = readl(info->regs + TH1520_ADC_SAMPLE_DATA);
+ if (tmp & TH1520_ADC_SAMPLE_DATA_CH0_VLD)
+ *val = (tmp & TH1520_ADC_SAMPLE_DATA_CH0) >>
+ TH1520_ADC_SAMPLE_DATA_CH0_OFF;
+ else
+ *val = (tmp & TH1520_ADC_SAMPLE_DATA_CH1) >>
+ TH1520_ADC_SAMPLE_DATA_CH1_OFF;
+ }
+
+ mutex_unlock(&info->mlock);
+ return IIO_VAL_INT;
+
+ case IIO_CHAN_INFO_SCALE:
+ *val = info->vref_uv / 1000;
+ *val2 = info->adc_feature.selres_sel;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ *val = info->current_clk;
+ *val2 = 0;
+ return IIO_VAL_INT;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static void th1520_adc_reset(struct th1520_adc *info)
+{
+ u32 tmp = readl(info->regs + TH1520_ADC_PHY_CTRL);
+
+ tmp |= TH1520_ADC_PHY_CTRL_RST_EN;
+ writel(tmp, info->regs + TH1520_ADC_PHY_CTRL);
+
+ usleep_range(10, 15);
+
+ tmp &= ~TH1520_ADC_PHY_CTRL_RST_EN;
+ writel(tmp, info->regs + TH1520_ADC_PHY_CTRL);
+}
+
+static void th1520_adc_set_clk(struct th1520_adc *info, int val)
+{
+ u32 count;
+ u32 apb_clk;
+ int fclk_ctrl;
+
+ apb_clk = clk_get_rate(info->clk);
+ count = DIV_ROUND_UP(apb_clk, val);
+ info->current_clk = apb_clk / count;
+
+ fclk_ctrl = readl(info->regs + TH1520_ADC_FCLK_CTRL);
+ fclk_ctrl &= ~TH1520_ADC_FCLK_CTRL_FCLLK_DIV;
+ fclk_ctrl |= count;
+ writel(fclk_ctrl, info->regs + TH1520_ADC_FCLK_CTRL);
+}
+
+static int th1520_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val, int val2, long mask)
+{
+ struct th1520_adc *info = iio_priv(indio_dev);
+
+ if (mask != IIO_CHAN_INFO_SAMP_FREQ)
+ return -EINVAL;
+
+ mutex_lock(&info->mlock);
+ th1520_adc_set_clk(info, val);
+ mutex_unlock(&info->mlock);
+
+ return 0;
+}
+
+static const struct iio_info th1520_adc_iio_info = {
+ .read_raw = &th1520_read_raw,
+ .write_raw = &th1520_write_raw,
+};
+
+static const struct of_device_id th1520_adc_match[] = {
+ { .compatible = "thead,th1520-adc", },
+ { /* end */ }
+};
+MODULE_DEVICE_TABLE(of, th1520_adc_match);
+
+static ssize_t th1520_adc_res_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ size_t bufpos = 0, count = 5;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+ struct th1520_adc *info = iio_priv(indio_dev);
+
+ snprintf(buf + bufpos, count - bufpos, "%.*x: ", 4,
+ info->adc_feature.selres_sel);
+ bufpos += 4;
+ buf[bufpos++] = '\n';
+
+ return bufpos;
+}
+
+static ssize_t th1520_adc_res_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ unsigned long res;
+ char *start = (char *)buf;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+ struct th1520_adc *info = iio_priv(indio_dev);
+
+ if (kstrtoul(start, 0, &res))
+ return -EINVAL;
+
+ switch (res) {
+ case TH1520_ADC_SELRES_6BIT:
+ case TH1520_ADC_SELRES_8BIT:
+ case TH1520_ADC_SELRES_10BIT:
+ case TH1520_ADC_SELRES_12BIT:
+ info->adc_feature.selres_sel = res;
+ th1520_adc_reset(info);
+ th1520_adc_hw_init(info);
+ break;
+ default:
+ dev_err(dev, "not support res\n");
+ return -EINVAL;
+ }
+
+ return size;
+}
+
+static DEVICE_ATTR_RW(th1520_adc_res);
+
+static int th1520_adc_probe(struct platform_device *pdev)
+{
+ int irq;
+ int ret;
+ struct resource *mem;
+ struct th1520_adc *info;
+ struct iio_dev *indio_dev;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev,
+ sizeof(struct th1520_adc));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "Failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ info = iio_priv(indio_dev);
+ info->dev = &pdev->dev;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ ret = devm_request_irq(info->dev, irq, th1520_adc_isr, 0,
+ dev_name(&pdev->dev), indio_dev);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
+ return ret;
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ info->regs = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(info->regs))
+ return PTR_ERR(info->regs);
+
+ info->clk = devm_clk_get(&pdev->dev, "adc");
+ if (IS_ERR(info->clk)) {
+ dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
+ PTR_ERR(info->clk));
+ return PTR_ERR(info->clk);
+ }
+
+ info->vref = devm_regulator_get(&pdev->dev, "vref");
+ if (IS_ERR(info->vref))
+ return PTR_ERR(info->vref);
+
+ ret = regulator_enable(info->vref);
+ if (ret)
+ return ret;
+
+ info->vref_uv = regulator_get_voltage(info->vref);
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ mutex_init(&info->mlock);
+ init_completion(&info->completion);
+
+ indio_dev->name = dev_name(&pdev->dev);
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->info = &th1520_adc_iio_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->channels = th1520_adc_iio_channels;
+ indio_dev->num_channels = ARRAY_SIZE(th1520_adc_iio_channels);
+
+ ret = clk_prepare_enable(info->clk);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Could not prepare or enable the clock.\n");
+ goto error_adc_clk_enable;
+ }
+
+ th1520_adc_cfg_init(info);
+ th1520_adc_reset(info);
+ th1520_adc_hw_init(info);
+
+ ret = iio_device_register(indio_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't register the device.\n");
+ goto error_iio_device_register;
+ }
+
+ ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_th1520_adc_res.attr);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to create adc debug sysfs.\n");
+ goto error_iio_device_register;
+ }
+
+ dev_info(&pdev->dev, "XuanTie TH1520 adc registered.\n");
+ return 0;
+
+error_iio_device_register:
+ clk_disable_unprepare(info->clk);
+error_adc_clk_enable:
+ regulator_disable(info->vref);
+
+ return ret;
+}
+
+static int th1520_adc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+ struct th1520_adc *info = iio_priv(indio_dev);
+
+ iio_device_unregister(indio_dev);
+ regulator_disable(info->vref);
+ clk_disable_unprepare(info->clk);
+
+ return 0;
+}
+
+static int __maybe_unused th1520_adc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct th1520_adc *info = iio_priv(indio_dev);
+ int phy_ctrl;
+
+ phy_ctrl = readl(info->regs + TH1520_ADC_PHY_CTRL);
+ phy_ctrl &= ~TH1520_ADC_PHY_CTRL_ENADC_EN;
+ writel(phy_ctrl, info->regs + TH1520_ADC_PHY_CTRL);
+
+ clk_disable_unprepare(info->clk);
+ regulator_disable(info->vref);
+
+ return 0;
+}
+
+static int __maybe_unused th1520_adc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct th1520_adc *info = iio_priv(indio_dev);
+ int ret;
+
+ ret = regulator_enable(info->vref);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(info->clk);
+ if (ret)
+ goto disable_reg;
+
+ th1520_adc_reset(info);
+ th1520_adc_set_clk(info, info->current_clk);
+ th1520_adc_hw_init(info);
+
+ return 0;
+
+disable_reg:
+ regulator_disable(info->vref);
+ return ret;
+}
+
+static SIMPLE_DEV_PM_OPS(th1520_adc_pm_ops,
+ th1520_adc_suspend, th1520_adc_resume);
+
+static struct platform_driver th1520_adc_driver = {
+ .probe = th1520_adc_probe,
+ .remove = th1520_adc_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = th1520_adc_match,
+ .pm = &th1520_adc_pm_ops,
+ },
+};
+module_platform_driver(th1520_adc_driver);
+
+MODULE_AUTHOR("fugang.duan <duanfugang.dfg@linux.alibaba.com>");
+MODULE_DESCRIPTION("XuanTie TH1520 ADC driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/iio/adc/xuantie-th1520-adc.h b/drivers/iio/adc/xuantie-th1520-adc.h
new file mode 100644
index 000000000000..c38d17fc6bbe
--- /dev/null
+++ b/drivers/iio/adc/xuantie-th1520-adc.h
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * XuanTie TH1520 ADC driver
+ *
+ * Copyright (C) 2021-2024 Alibaba Group Holding Limited.
+ * Fugang Duan <duanfugang.dfg@linux.alibaba.com>
+ *
+ */
+
+#include <linux/bitops.h>
+
+/* This will be the driver name the kernel reports */
+#define DRIVER_NAME "xuantie-th1520-adc"
+
+/* ADC registers */
+#define TH1520_ADC_PHY_CFG 0x00
+#define TH1520_ADC_PHY_CTRL 0x04
+#define TH1520_ADC_PHY_TEST 0x08
+#define TH1520_ADC_OP_CTRL 0x0C
+#define TH1520_ADC_OP_SINGLE_START 0x10
+#define TH1520_ADC_FCLK_CTRL 0x14
+#define TH1520_ADC_START_TIME 0x18
+#define TH1520_ADC_SAMPLE_TIME 0x1C
+#define TH1520_ADC_SAMPLE_DATA 0x20
+#define TH1520_ADC_INT_CTRL1 0x50
+#define TH1520_ADC_INT_CTRL2 0x54
+#define TH1520_ADC_INT_STATUS 0x58
+#define TH1520_ADC_INT_ACTUAL_VALUE_CH0 0x60
+#define TH1520_ADC_INT_ACTUAL_VALUE_CH1 0x64
+#define TH1520_ADC_INT_DELTA_VALUE_CH0 0x90
+#define TH1520_ADC_INT_DELTA_VALUE_CH1 0x94
+
+/* Configuration register field define */
+#define TH1520_ADC_PHY_CFG_SELRES_6BIT (0x0)
+#define TH1520_ADC_PHY_CFG_SELRES_8BIT (0x1)
+#define TH1520_ADC_PHY_CFG_SELRES_10BIT (0x2)
+#define TH1520_ADC_PHY_CFG_SELRES_12BIT (0x3)
+#define TH1520_ADC_PHY_CFG_SELDIFF_SINGLE_ENDED_INPUTS (0x0 << 4)
+#define TH1520_ADC_PHY_CFG_SELDIFF_DIFFERENTIAL_INPUTS (0x1 << 4)
+#define TH1520_ADC_PHY_CFG_SELBG_INTERNAL (0x1 << 8)
+#define TH1520_ADC_PHY_CFG_SELBG_EXTERNAL (0x0 << 8)
+#define TH1520_ADC_PHY_CFG_SELREF_INTERNAL (0x1 << 12)
+#define TH1520_ADC_PHY_CFG_SELREF_EXT (0x0 << 12)
+
+/* PHY CTRL register field define */
+#define TH1520_ADC_PHY_CTRL_ENOFFSET_EN (0x1 << 12)
+#define TH1520_ADC_PHY_CTRL_ENOFFMEAS_EN (0x1 << 8)
+#define TH1520_ADC_PHY_CTRL_RST_EN (0x1 << 4)
+#define TH1520_ADC_PHY_CTRL_ENADC_EN (0x1 << 0)
+
+/* ADC OP ctrl field define */
+#define TH1520_ADC_OP_CTRL_CH_EN_ALL GENMASK(19, 12)
+#define TH1520_ADC_OP_CTRL_CH_EN_0 (12)
+#define TH1520_ADC_OP_CTRL_MODE_SINGLE (0x1 << 0)
+#define TH1520_ADC_OP_CTRL_MODE_CONTINOUS (0x0 << 0)
+
+/* ADC OP single start */
+#define TH1520_ADC_OP_SINGLE_START_EN BIT(0)
+
+/* ADC fclk ctrl */
+#define TH1520_ADC_FCLK_CTRL_FCLLK_DIV GENMASK(6, 0)
+#define TH1520_ADC_FCLK_CTRL_TYP_1M (0x10004)
+#define TH1520_ADC_START_TIME_TYP_1M (0x160)
+#define TH1520_ADC_SAMPLE_TIME_TYP_1M (0x10)
+#define TH1520_ADC_SAMPLE_TIME_TYP_6BIT (8)
+#define TH1520_ADC_SAMPLE_TIME_TYP_8BIT (10)
+#define TH1520_ADC_SAMPLE_TIME_TYP_10BIT (12)
+#define TH1520_ADC_SAMPLE_TIME_TYP_12BIT (14)
+
+/* ADC sample data */
+#define TH1520_ADC_SAMPLE_DATA_CH1 GENMASK(27, 16)
+#define TH1520_ADC_SAMPLE_DATA_CH1_OFF (16)
+#define TH1520_ADC_SAMPLE_DATA_CH1_VLD BIT(31)
+#define TH1520_ADC_SAMPLE_DATA_CH1_NUMBER GENMASK(30, 28)
+#define TH1520_ADC_SAMPLE_DATA_CH1_NUMBER_OFF (28)
+#define TH1520_ADC_SAMPLE_DATA_CH0 GENMASK(11, 0)
+#define TH1520_ADC_SAMPLE_DATA_CH0_VLD BIT(15)
+#define TH1520_ADC_SAMPLE_DATA_CH0_OFF (0)
+#define TH1520_ADC_SAMPLE_DATA_CH0_NUMBER GENMASK(14, 12)
+#define TH1520_ADC_SAMPLE_DATA_CH0_NUMBER_OFF (12)
+
+/* ADC INT Ctrl */
+#define TH1520_ADC_INT_CTRL1_CH1_INT_MODE BIT(1)
+#define TH1520_ADC_INT_CTRL1_CH0_INT_MODE BIT(0)
+#define TH1520_ADC_INT_CTRL2_CH1_INT_MASK BIT(1)
+#define TH1520_ADC_INT_CTRL2_CH0_INT_MASK BIT(0)
+#define TH1520_ADC_INT_STS_CH1_INT_STS BIT(1)
+#define TH1520_ADC_INT_STS_CH0_INT_STS BIT(0)
+
+#define TH1520_ADC_ACTUAL_VALUE_CH0_HVAL GENMASK(27, 16)
+#define TH1520_ADC_ACTUAL_VALUE_CH0_HVAL_OFF (16)
+#define TH1520_ADC_ACTUAL_VALUE_CH0_LVAL GENMASK(11, 0)
+#define TH1520_ADC_ACTUAL_VALUE_CH0_LVAL_OFF (0)
+#define TH1520_ADC_ACTUAL_VALUE_CH1_HVAL GENMASK(27, 16)
+#define TH1520_ADC_ACTUAL_VALUE_CH1_HVAL_OFF (16)
+#define TH1520_ADC_ACTUAL_VALUE_CH1_LVAL GENMASK(11, 0)
+#define TH1520_ADC_ACTUAL_VALUE_CH1_LVAL_OFF (0)
+
+#define TH1520_ADC_DLT_VALUE_CH0_HVAL GENMASK(27, 16)
+#define TH1520_ADC_DLT_VALUE_CH0_HVAL_OFF (16)
+#define TH1520_ADC_DLT_VALUE_CH0_LVAL GENMASK(11, 0)
+#define TH1520_ADC_DLT_VALUE_CH0_LVAL_OFF (0)
+#define TH1520_ADC_DLT_VALUE_CH1_HVAL GENMASK(27, 16)
+#define TH1520_ADC_DLT_VALUE_CH1_HVAL_OFF (16)
+#define TH1520_ADC_DLT_VALUE_CH1_LVAL GENMASK(11, 0)
+#define TH1520_ADC_DLT_VALUE_CH1_LVAL_OFF (0)
+
+#define TH1520_ADC_FIFO_DATA_SIZE 32
+#define TH1520_ADC_PHY_ENCTR 0x8e0
+#define TH1520_ADC_TIMEOUT 500000
+
+#define TH1520_ADC_CHAN(_idx, _chan_type) { \
+ .type = (_chan_type), \
+ .indexed = 1, \
+ .channel = (_idx), \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
+}
+
+enum vol_ref {
+ TH1520_ADC_VOL_VREF,
+ TH1520_ADC_VOL_INTE,
+};
+
+enum input_mode_sel {
+ TH1520_ADC_SINGLE_ENDED_INPUTS,
+ TH1520_ADC_DIFFERENTIAL_INPUTS,
+};
+
+enum selres_sel {
+ TH1520_ADC_SELRES_6BIT = 6,
+ TH1520_ADC_SELRES_8BIT = 8,
+ TH1520_ADC_SELRES_10BIT = 10,
+ TH1520_ADC_SELRES_12BIT = 12,
+};
+
+enum offset_mode_sel {
+ TH1520_ADC_OFFSET_DIS = 0,
+ TH1520_ADC_OFFSET_EN,
+};
+
+enum conversion_mode_sel {
+ TH1520_ADC_MODE_SINGLE,
+ TH1520_ADC_MODE_CONTINOUS,
+};
+
+enum clk_sel {
+ TH1520_ADC_FCLK_TYP_1M,
+};
+
+enum int_actual_mask {
+ TH1520_ADC_ACTUAL_CH0,
+ TH1520_ADC_ACTUAL_CH1,
+ TH1520_ADC_ACTUAL_ALL,
+
+};
+
+enum int_delta_mask {
+ TH1520_ADC_DETAL_CH0,
+ TH1520_ADC_DETAL_CH1,
+ TH1520_ADC_DETAL_ALL,
+};
+
+struct th1520_adc_feature {
+ enum selres_sel selres_sel;
+ enum input_mode_sel input_mode;
+ enum vol_ref vol_ref;
+ enum offset_mode_sel offset_mode;
+ enum conversion_mode_sel conv_mode;
+ enum clk_sel clk_sel;
+ enum int_actual_mask int_actual;
+ enum int_delta_mask int_detal;
+};
+
+struct th1520_adc {
+ struct device *dev;
+ void __iomem *regs;
+ struct clk *clk;
+
+ u32 vref_uv;
+ u32 value;
+ struct regulator *vref;
+ struct th1520_adc_feature adc_feature;
+ u32 current_clk;
+ u32 ch0_offmeas;
+ u32 ch1_offmeas;
+
+ struct completion completion;
+ /* lock to protect against multiple access to the device */
+ struct mutex mlock;
+};
+
--
2.44.0
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