* Re: [PATCH v5 1/4] dt-bindings: clock: support i.MX95 BLK CTL module
From: Krzysztof Kozlowski @ 2024-03-31 19:54 UTC (permalink / raw)
To: Peng Fan, Peng Fan (OSS), Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Abel Vesa
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <DU0PR04MB94171DDC725D52E66DF3A77F88382@DU0PR04MB9417.eurprd04.prod.outlook.com>
On 31/03/2024 13:58, Peng Fan wrote:
>>> + const: 1
>>> + description:
>>> + The clock consumer should specify the desired clock by having the
>> clock
>>> + ID in its "clocks" phandle cell. See
>>> + include/dt-bindings/clock/nxp,imx95-clock.h
>>
>> In such case, put header as your first patch in the patchset. I don't understand
>> why it was split in the first place...
>
> Rob gave a comment in v4, so I split the headers.
> "
> If this number can change, then it is not ABI and doesn't go in this
> header. With that dropped,
> "
Nothing here speaks about splitting headers. Absolutely NOTHING. Rob
commented that you added number which can change, thus this is not a
binding.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 0/4] Add support i.MX95 BLK CTL module clock features
From: Krzysztof Kozlowski @ 2024-03-31 19:53 UTC (permalink / raw)
To: Peng Fan, Peng Fan (OSS), Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Abel Vesa
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <DU0PR04MB9417426E1F8EA9560213E58488382@DU0PR04MB9417.eurprd04.prod.outlook.com>
On 31/03/2024 14:00, Peng Fan wrote:
>> Subject: Re: [PATCH v5 0/4] Add support i.MX95 BLK CTL module clock
>> features
>>
>> On 24/03/2024 08:51, Peng Fan (OSS) wrote:
>>> i.MX95's several MIXes has BLK CTL module which could be used for clk
>>> settings, QoS settings, Misc settings for a MIX. This patchset is to
>>> add the clk feature support, including dt-bindings
>>>
>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>> ---
>>> Changes in v5:
>>> - Merge bindings except the one has mux-controller
>>> - Separate clock ID headers in a separate patch per Rob's comments
>>
>> Where did he suggest it?
>
> See https://lore.kernel.org/all/20240315165422.GA1472059-robh@kernel.org/
>
He said under specific line about one specific define. There is
absolutely nothing about splitting the header into new patch.
NAK
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 4/4] clk: imx: add i.MX95 BLK CTL clk driver
From: Krzysztof Kozlowski @ 2024-03-31 19:52 UTC (permalink / raw)
To: Peng Fan, Peng Fan (OSS), Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Abel Vesa
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <DU0PR04MB941774D0A1CD037AB7108AAF88382@DU0PR04MB9417.eurprd04.prod.outlook.com>
On 31/03/2024 14:01, Peng Fan wrote:
>> Subject: Re: [PATCH v5 4/4] clk: imx: add i.MX95 BLK CTL clk driver
>>
>> On 24/03/2024 08:52, Peng Fan (OSS) wrote:
>>> From: Peng Fan <peng.fan@nxp.com>
>>>
>>
>> ...
>>
>>> +
>>> +static const struct of_device_id imx95_bc_of_match[] = {
>>> + { .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },
>>> + { .compatible = "nxp,imx95-display-master-csr", },
>>> + { .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
>>> + { .compatible = "nxp,imx95-display-csr", .data =
>> &dispmix_csr_dev_data },
>>> + { .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
>>> + { /* Sentinel */ },
>>> +};
>>> +MODULE_DEVICE_TABLE(of, imx95_bc_of_match);
>>> +
>>> +static struct platform_driver imx95_bc_driver = {
>>> + .probe = imx95_bc_probe,
>>> + .driver = {
>>> + .name = "imx95-blk-ctl",
>>> + .of_match_table = of_match_ptr(imx95_bc_of_match),
>>
>> Drop of_match_ptr(), causes warnings. From where did you copy such code?
>> Which mainline driver has such pattern?
>
> I recall that when COMPILE_TEST is selected, OF is not selected, kernel
> robot reports warning. This may not be true now.
>
This itself was never true. Any compilation, not robots, which you can
test by yourself will report warnings if your code is not correct. Don't
use random C syntax to suppress warnings, but actually something which
will work. of_match_ptr does not make sense without maybe_unused or
ifdef. But anyway of_match_ptr is not recommended.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4] dt-bindings: serial: actions,owl-uart: convert to dtschema
From: Krzysztof Kozlowski @ 2024-03-31 19:50 UTC (permalink / raw)
To: Kanak Shilledar
Cc: krzysztof.kozlowski+dt, robh+dt, devicetree, daniel.baluta,
Kanak Shilledar
In-Reply-To: <20240331132811.12060-1-kanakshilledar@gmail.com>
On 31/03/2024 15:28, Kanak Shilledar wrote:
> From: Kanak Shilledar <kanakshilledar111@protonmail.com>
>
> Convert the Actions Semi Owl UART to newer DT schema.
> Created DT schema based on the .txt file which had
> `compatible`, `reg` and `interrupts` as the
> required properties. This binding is used by Actions S500, S700
> and S900 SoC. S700 and S900 use the same UART compatible string.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
I explicitly asked you to drop my tag. Last time I raised the problem
that you implement some other changes and do not implement what reviewer
is asking for. It seems this continues the pattern.
> Signed-off-by: Kanak Shilledar <kanakshilledar111@protonmail.com>
> ---
> Changes in v4
> - added `clocks` property to fix warning of 'clocks' was unexpected
> while running `make dtbs_check`. `clocks` property was not defined
> in the original .txt file. `clocks` property is removed from the
> required section.
> - added `clocks` property in example
> - extended the devicetree with clocks node
Please keep the reset of the changelog.
You had two other versions, what was changing? Why this is not even
correct? Your v4 did not add clocks to the example. It was already in v3.
How can we know what you changed here if this changelog is totally
mixing everything from all changes?
Please read this carefully and read the feedback carefully. Then create
changelogs which represent REAL CHANGES, like:
https://lore.kernel.org/all/20240210-topic-8280_pcie-v3-0-ee7af6f892a0@linaro.org/
If someone asks you to drop the tag, you MUST drop the tag.
The patch is fine though, so I would give Review tag now. Keep above for
future and no need to resend just to fix it. If you send or resend, then
fix the changelog.
FWIW
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
BUT, your patch won't be applied... because you decided not to CC
maintainers. I have no clue how or why did you come up with such Cc
list. There is a guideline in your project, whether this is GSoC or
mentorship or whatever, how to send patches. Please read carefully this
guideline.
Standard form letter:
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC (and consider --no-git-fallback argument). It might
happen, that command when run on an older kernel, gives you outdated
entries. Therefore please be sure you base your patches on recent Linux
kernel.
Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline), work on fork of kernel
(don't, instead use mainline) or you ignore some maintainers (really
don't). Just use b4 and everything should be fine, although remember
about `b4 prep --auto-to-cc` if you added new patches to the patchset.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [EXTERNAL] Re: [PATCH v7 4/4] ASoc: dt-bindings: PCM6240: Add initial DT binding
From: Krzysztof Kozlowski @ 2024-03-31 19:42 UTC (permalink / raw)
To: Ding, Shenghao, linux-kernel@vger.kernel.org
Cc: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
linux-sound@vger.kernel.org, devicetree@vger.kernel.org,
perex@perex.cz, tiwai@suse.com, 13916275206@139.com,
Chawla, Mohit, soyer@irl.hu, Huang, Jonathan, tiwai@suse.de,
Djuandi, Peter, Agrawal, Manisha, Hari, Raj, Yashar, Avi,
Nagalla, Hari, Bajjuri, Praneeth, Baojun.Xu@fpt.com, Rob Herring
In-Reply-To: <41797fe7d5bb41b4bdea4ee7f4957291@ti.com>
On 31/03/2024 15:20, Ding, Shenghao wrote:
> Hi Krzysztof
> Answer inline
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Sent: Sunday, March 31, 2024 4:15 PM
>> To: Ding, Shenghao <shenghao-ding@ti.com>; linux-kernel@vger.kernel.org
>> Cc: lgirdwood@gmail.com; broonie@kernel.org; robh+dt@kernel.org;
>> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; linux-
>> sound@vger.kernel.org; devicetree@vger.kernel.org; perex@perex.cz;
>> tiwai@suse.com; 13916275206@139.com; Chawla, Mohit
>> <mohit.chawla@ti.com>; soyer@irl.hu; Huang, Jonathan
>> <jkhuang3@ti.com>; tiwai@suse.de; Djuandi, Peter <pdjuandi@ti.com>;
>> Agrawal, Manisha <manisha.agrawal@ti.com>; Hari, Raj <s-hari@ti.com>;
>> Yashar, Avi <aviel@ti.com>; Nagalla, Hari <hnagalla@ti.com>; Bajjuri,
>> Praneeth <praneeth@ti.com>; Baojun.Xu@fpt.com; Rob Herring
>> <robh@kernel.org>
>> Subject: [EXTERNAL] Re: [PATCH v7 4/4] ASoc: dt-bindings: PCM6240: Add
>> initial DT binding
>>
> .............................
>>> - remove unneeded items and if branches.
>>> - Add missing compatible devices, such as adc6120, etc.
>>> - Add necessary people into the list for DTS review
>>> - correct misaligned.
>>> - simplify the compatibility
>>> - remove sound-name-prefix and revert back
>>> - Add review information
>>
>> All these changes in v7 and you still kept Rob's review? I think either review
>> was not given or your changelog is just incorrect.
> Since Rob's review, nothing changed in yaml. Even in this patch, only removed kcontrol interfaces
> in the code and added the mixer-test report in cover-letter as Mark suggested, which is no effect
> on yaml file.
Then for the future, please use some reasonable format of changelog, e.g.:
https://lore.kernel.org/all/20240210-topic-8280_pcie-v3-0-ee7af6f892a0@linaro.org/
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 1/3] phy: rockchip: emmc: Enable pulldown for strobe line
From: Dragan Simic @ 2024-03-31 19:26 UTC (permalink / raw)
To: Alban Browaeys
Cc: Conor Dooley, dev, Vinod Koul, Kishon Vijay Abraham I,
Heiko Stuebner, Chris Ruehl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Christopher Obbard, Doug Anderson, Brian Norris,
Jensen Huang, linux-phy, linux-arm-kernel, linux-rockchip,
linux-kernel, devicetree
In-Reply-To: <871f0b24a38208d9c5d6abc87d83b067162c103e.camel@gmail.com>
Hello Alban,
On 2024-03-28 18:00, Alban Browaeys wrote:
> Le mardi 26 mars 2024 à 19:46 +0000, Conor Dooley a écrit :
>> On Tue, Mar 26, 2024 at 07:54:35PM +0100, Folker Schwesinger via B4
>> Relay wrote:
>> > From: Folker Schwesinger <dev@folker-schwesinger.de>
>> > - if (of_property_read_bool(dev->of_node, "rockchip,enable-
>> > strobe-pulldown"))
>> > - rk_phy->enable_strobe_pulldown =
>> > PHYCTRL_REN_STRB_ENABLE;
>> > + if (of_property_read_bool(dev->of_node, "rockchip,disable-
>> > strobe-pulldown"))
>> > + rk_phy->enable_strobe_pulldown =
>> > PHYCTRL_REN_STRB_DISABLE;
>>
>> Unfortunately you cannot do this.
>> Previously no property at all meant disabled and a property was
>> required
>> to enable it. With this change the absence of a property means that
>> it
>> will be enabled.
>> An old devicetree is that wanted this to be disabled would have no
>> property and will now end up with it enabled. This is an ABI break
>> and is
>> clearly not backwards compatible, that's a NAK unless it is
>> demonstrable
>> that noone actually wants to disable it at all.
>
> But the patch that introduced the new default to disable the pulldown
> explicitely introduced a regression for at least 4 boards.
> It took time to sort out that the default to disable pulldown was the
> culprit but still.
> Will we carry this new behavor that breaks the default design for
> rk3399 because since the regression was introduced new board definition
> might have expceted this new behavior.
>
> Could the best option be to revert to énot set a default enable/disable
> pulldown" (as before the commit that introduced the regression) and
> allow one to force the pulldown via the enable/disable pulldown
> property?
> I mean the commit that introduced a default value for the pulldown did
> not seem to be about fixing anything. But it broke a lot. ANd it was
> really really hard to find the description of this commit to understand
> that one had to enable pulldown to restore hs400.
Quite frankly, I think it's better to leave the default as-is, and
to fix the dts files for the boards that have been (or will be) tested
to work as expected and reliably in the HS400 mode. Perhaps this is
also a good opportunity to revisit the reliability of the HS400 mode
on various boards.
In other words, it could be that some boards now rely on the pull-down
being disabled by default, so enabling it by default might actually
break such boards. I know, the troublesome commit that disabled the
pull-down caused breakage, but fixing that might actually cause more
breakage at this point.
> In more than 3 years, only one board maintainer noticed that this
> property was required to get back HS400 and thanks to a user telling
> me that this board was working I found from this board that this
> property was "missing" from most board definitions (while it was not
> required before).
A couple of years ago I've also spent some time debugging HS400 not
working on a Rock 4, but ended up with limiting the speed to HS200 as
a workaround, so I agree about the whole thing being a mess.
> I am all for not breaking ABI. But what about not reverting a patch
> that already broke ABI because this patch introduced a new ABI that we
> don't want to break?
> I mean shouldn't a new commit with a new ABI that regressed the kernel
> be reverted?
>
> Mind fixing the initial regression 8b5c2b45b8f0 "phy: rockchip: set
> pulldown for strobe line in dts" does not necessarily mean changing the
> default to the opposite value but could also be reverting to not
> setting a default.
> Though I don't know if there are pros to setting a default.
>
>
>> If this patch fixes a problem on a board that you have, I would
>> suggest
>> that you add the property to enable it, as the binding tells you to.
>>
>> Thanks,
>> Conor.
>
>
> Regards,
> Alban
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: rockchip: Add enable-strobe-pulldown to emmc phy on ROCK Pi 4
From: Dragan Simic @ 2024-03-31 19:14 UTC (permalink / raw)
To: Folker Schwesinger
Cc: Vinod Koul, Yogesh Hegde, Heiko Stuebner, Chris Ruehl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christopher Obbard, linux-arm-kernel, linux-rockchip,
linux-kernel, devicetree
In-Reply-To: <20240327192641.14220-2-dev@folker-schwesinger.de>
On 2024-03-27 20:26, Folker Schwesinger wrote:
> Commit 8b5c2b45b8f0 disabled the internal pull-down for the strobe line
> causing I/O errors in HS400 mode for various eMMC modules.
>
> Enable the internal strobe pull-down for ROCK Pi 4 boards. Also
> re-enable
> HS400 mode, that was replaced with HS200 mode as a workaround for the
> stability issues in:
> cee572756aa2 ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK Pi
> 4").
>
> This was tested on ROCK 4SE and ROCK Pi 4B+.
>
> Fixes: 8b5c2b45b8f0 ("phy: rockchip: set pulldown for strobe line in
> dts")
> Signed-off-by: Folker Schwesinger <dev@folker-schwesinger.de>
Looking good to me.
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
> index 281a12180703..b9d6284bb804 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
> @@ -194,6 +194,7 @@ &cpu_b1 {
> };
>
> &emmc_phy {
> + rockchip,enable-strobe-pulldown;
> status = "okay";
> };
>
> @@ -648,7 +649,8 @@ &saradc {
> &sdhci {
> max-frequency = <150000000>;
> bus-width = <8>;
> - mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + mmc-hs400-enhanced-strobe;
> non-removable;
> status = "okay";
> };
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: rockchip: Add enable-strobe-pulldown to emmc phy on ROCK 4C+
From: Dragan Simic @ 2024-03-31 19:14 UTC (permalink / raw)
To: Folker Schwesinger
Cc: Vinod Koul, Yogesh Hegde, Heiko Stuebner, Chris Ruehl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christopher Obbard, linux-arm-kernel, linux-rockchip,
linux-kernel, devicetree
In-Reply-To: <20240327192641.14220-3-dev@folker-schwesinger.de>
On 2024-03-27 20:26, Folker Schwesinger wrote:
> Commit 8b5c2b45b8f0 disabled the internal pull-down for the strobe line
> causing I/O errors in HS400 mode for various eMMC modules.
>
> Enable the internal strobe pull-down for the ROCK 4C+ board. Also
> re-enable
> HS400 mode, that was replaced with HS200 mode as a workaround for the
> stability issues in:
> 2bd1d2dd808c ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK
> 4C+").
>
> Fixes: 8b5c2b45b8f0 ("phy: rockchip: set pulldown for strobe line in
> dts")
> Signed-off-by: Folker Schwesinger <dev@folker-schwesinger.de>
Looking good to me.
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
> b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
> index 7baf9d1b22fd..972aea843afd 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
> @@ -151,6 +151,7 @@ &cpu_b1 {
> };
>
> &emmc_phy {
> + rockchip,enable-strobe-pulldown;
> status = "okay";
> };
>
> @@ -549,7 +550,8 @@ &saradc {
> &sdhci {
> max-frequency = <150000000>;
> bus-width = <8>;
> - mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + mmc-hs400-enhanced-strobe;
> non-removable;
> status = "okay";
> };
^ permalink raw reply
* Re: [RFC][PATCH 1/2] clk: meson: T7: add support for Amlogic T7 SoC PLL clock driver
From: Lucas Tanure @ 2024-03-31 18:33 UTC (permalink / raw)
To: Xianwei Zhao, Yu Tu, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Michael Turquette
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel,
linux-clk
In-Reply-To: <CAJX_Q+0n3vPV58Qk9iZ0TsZ1Q75w18c35hoPvSi5-D0NA8Cv2w@mail.gmail.com>
On Sun, Mar 31, 2024 at 7:25 PM Lucas Tanure <tanure@linux.com> wrote:
>
> On Mon, Mar 18, 2024 at 11:44 AM Lucas Tanure <tanure@linux.com> wrote:
> >
> > Add the T7 PLL clock controller driver in the T7 SoC family.
> >
> > This is RFC patch that enables SDCard, Ethernet and Clocking
> > for Amlogic T7 soc.
> > In this current state the patch doesn't work and gives a kernel
> > panic when probing the meson-axg-mmc for the SDCard.
> > DO NOT MERGE.
> >
> > Signed-off-by: Lucas Tanure <tanure@linux.com>
> > ---
> > drivers/clk/meson/Kconfig | 25 +
> > drivers/clk/meson/Makefile | 2 +
> > drivers/clk/meson/t7-peripherals.c | 6368 +++++++++++++++++
> > drivers/clk/meson/t7-peripherals.h | 131 +
> > drivers/clk/meson/t7-pll.c | 1543 ++++
> > drivers/clk/meson/t7-pll.h | 83 +
> > .../clock/amlogic,t7-peripherals-clkc.h | 410 ++
> > .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 69 +
> > 8 files changed, 8631 insertions(+)
> > create mode 100644 drivers/clk/meson/t7-peripherals.c
> > create mode 100644 drivers/clk/meson/t7-peripherals.h
> > create mode 100644 drivers/clk/meson/t7-pll.c
> > create mode 100644 drivers/clk/meson/t7-pll.h
> > create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
> > create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
> >
> > diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> > index 29ffd14d267b..467b4bf86572 100644
> > --- a/drivers/clk/meson/Kconfig
> > +++ b/drivers/clk/meson/Kconfig
> > @@ -169,4 +169,29 @@ config COMMON_CLK_S4_PERIPHERALS
> > help
> > Support for the peripherals clock controller on Amlogic S805X2 and S905Y4
> > devices, AKA S4. Say Y if you want S4 peripherals clock controller to work.
> > +
> > +config COMMON_CLK_T7_PLL
> > + tristate "T7 SoC PLL clock controllers support"
> > + depends on ARM64
> > + default y
> > + select COMMON_CLK_MESON_CLKC_UTILS
> > + select COMMON_CLK_MESON_MPLL
> > + select COMMON_CLK_MESON_PLL
> > + select COMMON_CLK_MESON_REGMAP
> > + help
> > + Support for the PLL clock controller on Amlogic A113D2 device,AKA T7.
> > + Say Y if you want the board to work, because PLLs are the parent of
> > + most peripherals.
> > +
> > +config COMMON_CLK_T7_PERIPHERALS
> > + tristate "T7 SoC peripherals clock controllers support"
> > + depends on ARM64
> > + default y
> > + select COMMON_CLK_MESON_CLKC_UTILS
> > + select COMMON_CLK_MESON_REGMAP
> > + select COMMON_CLK_MESON_DUALDIV
> > + select COMMON_CLK_MESON_VID_PLL_DIV
> > + help
> > + Support for the peripherals clock controller on Amlogic A113D2 device, AKA T7.
> > + Say Y if you want T7 peripherals clock controller to work.
> > endmenu
> > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> > index 9ee4b954c896..9a044b70a227 100644
> > --- a/drivers/clk/meson/Makefile
> > +++ b/drivers/clk/meson/Makefile
> > @@ -24,3 +24,5 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
> > obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
> > obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
> > obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o
> > +obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o
> > +obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) += t7-peripherals.o
> > diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c
> > new file mode 100644
> > index 000000000000..f88fc2ae4dad
> > --- /dev/null
> > +++ b/drivers/clk/meson/t7-peripherals.c
> > @@ -0,0 +1,6368 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Amlogic Meson-T7 Clock Controller Driver
> > + *
> > + * Copyright (c) 2018 Amlogic, inc.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-regmap.h"
> > +#include "vid-pll-div.h"
> > +#include "clk-dualdiv.h"
> > +#include "t7-peripherals.h"
> > +#include "meson-clkc-utils.h"
> > +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
> > +
> > +
> > +/*
> > + *rtc 32k clock
> > + *
> > + *xtal--GATE------------------GATE---------------------|\
> > + * | -------- | \
> > + * | | | | \
> > + * ---| DUAL |----------------------| |
> > + * | | | |____GATE__
> > + * -------- | | rtc_32k_out
> > + * PAD-----------------------------------------| /
> > + * | /
> > + * DUAL function: |/
> > + * bit 28 in RTC_BY_OSCIN_CTRL0 control the dual function.
> > + * when bit 28 = 0
> > + * f = 24M/N0
> > + * when bit 28 = 1
> > + * output N1 and N2 in turns.
> > + * T = (x*T1 + y*T2)/x+y
> > + * f = (24M/(N0*M0 + N1*M1)) * (M0 + M1)
> > + * f: the frequecy value (HZ)
> > + * | | | |
> > + * | Div1 |-| Cnt1 |
> > + * /|______| |______|\
> > + * -| ______ ______ ---> Out
> > + * \| | | |/
> > + * | Div2 |-| Cnt2 |
> > + * |______| |______|
> > + **/
> > +
> > +/*
> > + * rtc 32k clock in gate
> > + */
> > +static struct clk_regmap t7_rtc_32k_clkin = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
> > + .bit_idx = 31,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "rtc_32k_clkin",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static const struct meson_clk_dualdiv_param t7_32k_div_table[] = {
> > + {
> > + .dual = 1,
> > + .n1 = 733,
> > + .m1 = 8,
> > + .n2 = 732,
> > + .m2 = 11,
> > + },
> > + {}
> > +};
> > +
> > +static struct clk_regmap t7_rtc_32k_div = {
> > + .data = &(struct meson_clk_dualdiv_data){
> > + .n1 = {
> > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
> > + .shift = 0,
> > + .width = 12,
> > + },
> > + .n2 = {
> > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
> > + .shift = 12,
> > + .width = 12,
> > + },
> > + .m1 = {
> > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
> > + .shift = 0,
> > + .width = 12,
> > + },
> > + .m2 = {
> > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
> > + .shift = 12,
> > + .width = 12,
> > + },
> > + .dual = {
> > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .table = t7_32k_div_table,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "rtc_32k_div",
> > + .ops = &meson_clk_dualdiv_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_rtc_32k_clkin.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_rtc_32k_xtal = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL1,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "rtc_32k_xtal",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_rtc_32k_clkin.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +/*
> > + * three parent for rtc clock out
> > + * pad is from where?
> > + */
> > +static u32 rtc_32k_sel[] = {0, 1};
> > +static struct clk_regmap t7_rtc_32k_sel = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_RTC_CTRL,
> > + .mask = 0x3,
> > + .shift = 0,
> > + .table = rtc_32k_sel,
> > + .flags = CLK_MUX_ROUND_CLOSEST,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "rtc_32k_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_rtc_32k_xtal.hw,
> > + &t7_rtc_32k_div.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_rtc_clk = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
> > + .bit_idx = 30,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "rtc_clk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_rtc_32k_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +/* sys clk */
> > +static u32 mux_table_sys_ab_clk_sel[] = { 0, 1, 2, 3, 4, 5, 7 };
> > +static const struct clk_parent_data t7_table_sys_ab_clk_sel[] = {
> > + { .fw_name = "xtal", },
> > + { .fw_name = "fclk_div2", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "axi_clk_frcpu", },
> > + { .hw = &t7_rtc_clk.hw }
> > +};
> > +
> > +static struct clk_regmap t7_sysclk_b_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SYS_CLK_CTRL0,
> > + .mask = 0x7,
> > + .shift = 26,
> > + .table = mux_table_sys_ab_clk_sel,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sysclk_b_sel",
> > + .ops = &clk_regmap_mux_ro_ops,
> > + .parent_data = t7_table_sys_ab_clk_sel,
> > + .num_parents = ARRAY_SIZE(t7_table_sys_ab_clk_sel),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sysclk_b_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_SYS_CLK_CTRL0,
> > + .shift = 16,
> > + .width = 10,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sysclk_b_div",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sysclk_b_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sysclk_b = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_SYS_CLK_CTRL0,
> > + .bit_idx = 29,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "sysclk_b",
> > + .ops = &clk_regmap_gate_ro_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sysclk_b_div.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sysclk_a_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SYS_CLK_CTRL0,
> > + .mask = 0x7,
> > + .shift = 10,
> > + .table = mux_table_sys_ab_clk_sel,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sysclk_a_sel",
> > + .ops = &clk_regmap_mux_ro_ops,
> > + .parent_data = t7_table_sys_ab_clk_sel,
> > + .num_parents = ARRAY_SIZE(t7_table_sys_ab_clk_sel),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sysclk_a_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_SYS_CLK_CTRL0,
> > + .shift = 0,
> > + .width = 10,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sysclk_a_div",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sysclk_a_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sysclk_a = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_SYS_CLK_CTRL0,
> > + .bit_idx = 13,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "sysclk_a",
> > + .ops = &clk_regmap_gate_ro_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sysclk_a_div.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sys_clk = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SYS_CLK_CTRL0,
> > + .mask = 0x1,
> > + .shift = 15,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sys_clk",
> > + .ops = &clk_regmap_mux_ro_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sysclk_a.hw,
> > + &t7_sysclk_b.hw,
> > + },
> > + .num_parents = 2,
> > + },
> > +};
> > +
> > +/*axi clk*/
> > +
> > +/*ceca_clk*/
> > +static struct clk_regmap t7_ceca_32k_clkin = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_CECA_CTRL0,
> > + .bit_idx = 31,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "ceca_32k_clkin",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_ceca_32k_div = {
> > + .data = &(struct meson_clk_dualdiv_data){
> > + .n1 = {
> > + .reg_off = CLKCTRL_CECA_CTRL0,
> > + .shift = 0,
> > + .width = 12,
> > + },
> > + .n2 = {
> > + .reg_off = CLKCTRL_CECA_CTRL0,
> > + .shift = 12,
> > + .width = 12,
> > + },
> > + .m1 = {
> > + .reg_off = CLKCTRL_CECA_CTRL1,
> > + .shift = 0,
> > + .width = 12,
> > + },
> > + .m2 = {
> > + .reg_off = CLKCTRL_CECA_CTRL1,
> > + .shift = 12,
> > + .width = 12,
> > + },
> > + .dual = {
> > + .reg_off = CLKCTRL_CECA_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .table = t7_32k_div_table,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "ceca_32k_div",
> > + .ops = &meson_clk_dualdiv_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_ceca_32k_clkin.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_ceca_32k_sel_pre = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_CECA_CTRL1,
> > + .mask = 0x1,
> > + .shift = 24,
> > + .flags = CLK_MUX_ROUND_CLOSEST,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "ceca_32k_sel_pre",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_ceca_32k_div.hw,
> > + &t7_ceca_32k_clkin.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_ceca_32k_sel = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_CECA_CTRL1,
> > + .mask = 0x1,
> > + .shift = 31,
> > + .flags = CLK_MUX_ROUND_CLOSEST,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "ceca_32k_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_ceca_32k_sel_pre.hw,
> > + &t7_rtc_clk.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_ceca_32k_clkout = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_CECA_CTRL0,
> > + .bit_idx = 30,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "ceca_32k_clkout",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_ceca_32k_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +/*cecb_clk*/
> > +static struct clk_regmap t7_cecb_32k_clkin = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_CECB_CTRL0,
> > + .bit_idx = 31,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "cecb_32k_clkin",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_cecb_32k_div = {
> > + .data = &(struct meson_clk_dualdiv_data){
> > + .n1 = {
> > + .reg_off = CLKCTRL_CECB_CTRL0,
> > + .shift = 0,
> > + .width = 12,
> > + },
> > + .n2 = {
> > + .reg_off = CLKCTRL_CECB_CTRL0,
> > + .shift = 12,
> > + .width = 12,
> > + },
> > + .m1 = {
> > + .reg_off = CLKCTRL_CECB_CTRL1,
> > + .shift = 0,
> > + .width = 12,
> > + },
> > + .m2 = {
> > + .reg_off = CLKCTRL_CECB_CTRL1,
> > + .shift = 12,
> > + .width = 12,
> > + },
> > + .dual = {
> > + .reg_off = CLKCTRL_CECB_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .table = t7_32k_div_table,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "cecb_32k_div",
> > + .ops = &meson_clk_dualdiv_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_cecb_32k_clkin.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_cecb_32k_sel_pre = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_CECB_CTRL1,
> > + .mask = 0x1,
> > + .shift = 24,
> > + .flags = CLK_MUX_ROUND_CLOSEST,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "cecb_32k_sel_pre",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_cecb_32k_div.hw,
> > + &t7_cecb_32k_clkin.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_cecb_32k_sel = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_CECB_CTRL1,
> > + .mask = 0x1,
> > + .shift = 31,
> > + .flags = CLK_MUX_ROUND_CLOSEST,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "cecb_32k_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_cecb_32k_sel_pre.hw,
> > + &t7_rtc_clk.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_cecb_32k_clkout = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_CECB_CTRL0,
> > + .bit_idx = 30,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "cecb_32k_clkout",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_cecb_32k_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static const struct clk_parent_data t7_sc_parent_data[] = {
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "xtal", }
> > +};
> > +
> > +static struct clk_regmap t7_sc_clk_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SC_CLK_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "sc_clk_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_sc_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_sc_parent_data),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sc_clk_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_SC_CLK_CTRL,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "sc_clk_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sc_clk_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sc_clk_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_SC_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sc_clk_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sc_clk_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +/*rama_clk*/
> > +
> > +/*dspa_clk*/
> > +static const struct clk_parent_data t7_dsp_parent_hws[] = {
> > + { .fw_name = "xtal", },
> > + { .fw_name = "fclk_div2p5", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "hifi_pll", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div7", },
> > + { .hw = &t7_rtc_clk.hw }
> > +};
> > +
> > +static struct clk_regmap t7_dspa_a_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_DSPA_CLK_CTRL0,
> > + .mask = 0x7,
> > + .shift = 10,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspa_a_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dsp_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_dsp_parent_hws),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspa_a_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_DSPA_CLK_CTRL0,
> > + .shift = 0,
> > + .width = 10,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspa_a_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dspa_a_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspa_a_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_DSPA_CLK_CTRL0,
> > + .bit_idx = 13,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dspa_a_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dspa_a_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspa_b_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_DSPA_CLK_CTRL0,
> > + .mask = 0x7,
> > + .shift = 26,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspa_b_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dsp_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_dsp_parent_hws),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspa_b_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_DSPA_CLK_CTRL0,
> > + .shift = 16,
> > + .width = 10,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspa_b_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dspa_b_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspa_b_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_DSPA_CLK_CTRL0,
> > + .bit_idx = 29,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dspa_b_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dspa_b_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspa_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_DSPA_CLK_CTRL0,
> > + .mask = 0x1,
> > + .shift = 15,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspa_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dspa_a_gate.hw,
> > + &t7_dspa_b_gate.hw,
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspb_a_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_DSPB_CLK_CTRL0,
> > + .mask = 0x7,
> > + .shift = 10,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspb_a_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dsp_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_dsp_parent_hws),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspb_a_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_DSPB_CLK_CTRL0,
> > + .shift = 0,
> > + .width = 10,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspb_a_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dspb_a_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspb_a_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_DSPB_CLK_CTRL0,
> > + .bit_idx = 13,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dspb_a_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dspb_a_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspb_b_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_DSPB_CLK_CTRL0,
> > + .mask = 0x7,
> > + .shift = 26,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspb_b_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dsp_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_dsp_parent_hws),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspb_b_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_DSPB_CLK_CTRL0,
> > + .shift = 16,
> > + .width = 10,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspb_b_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dspb_b_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspb_b_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_DSPB_CLK_CTRL0,
> > + .bit_idx = 29,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dspb_b_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dspb_b_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dspb_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_DSPB_CLK_CTRL0,
> > + .mask = 0x1,
> > + .shift = 15,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspb_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dspb_a_gate.hw,
> > + &t7_dspb_b_gate.hw,
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +/*12_24M clk*/
> > +static struct clk_regmap t7_24M_clk_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_CLK12_24_CTRL,
> > + .bit_idx = 11,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "24m",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_12M_clk_div = {
> > + .mult = 1,
> > + .div = 2,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "24m_div2",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_24M_clk_gate.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_12M_clk_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_CLK12_24_CTRL,
> > + .bit_idx = 10,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "12m",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_12M_clk_div.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_25M_clk_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_CLK12_24_CTRL,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "25M_clk_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "fclk_div2",
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_25M_clk_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_CLK12_24_CTRL,
> > + .bit_idx = 12,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "25m",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_25M_clk_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +/* Video Clocks */
> > +static struct clk_regmap t7_vid_pll_div = {
> > + .data = &(struct meson_vid_pll_div_data){
> > + .val = {
> > + .reg_off = CLKCTRL_VID_PLL_CLK0_DIV,
> > + .shift = 0,
> > + .width = 15,
> > + },
> > + .sel = {
> > + .reg_off = CLKCTRL_VID_PLL_CLK0_DIV,
> > + .shift = 16,
> > + .width = 2,
> > + },
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vid_pll_div",
> > + .ops = &meson_vid_pll_div_ro_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "hdmi_pll",
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static const struct clk_parent_data t7_vid_pll_parent_data[] = {
> > + { .hw = &t7_vid_pll_div.hw, },
> > + { .fw_name = "hdmi_pll", },
> > +};
> > +
> > +static struct clk_regmap t7_vid_pll_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VID_PLL_CLK0_DIV,
> > + .mask = 0x1,
> > + .shift = 18,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vid_pll_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + /*
> > + * bit 18 selects from 2 possible parents:
> > + * vid_pll_div or hdmi_pll
> > + */
> > + .parent_data = t7_vid_pll_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vid_pll_parent_data),
> > + .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vid_pll = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_PLL_CLK0_DIV,
> > + .bit_idx = 19,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vid_pll",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vid_pll_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static const struct clk_parent_data t7_vclk_parent_data[] = {
> > + { .hw = &t7_vid_pll.hw },
> > + { .fw_name = "gp0_pll", },
> > + { .fw_name = "hifi_pll", },
> > + { .fw_name = "mpll1", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div7" },
> > +};
> > +
> > +static struct clk_regmap t7_vclk_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VID_CLK0_CTRL,
> > + .mask = 0x7,
> > + .shift = 16,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_vclk_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vclk_parent_data),
> > + .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk2_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VIID_CLK0_CTRL,
> > + .mask = 0x7,
> > + .shift = 16,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk2_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_vclk_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vclk_parent_data),
> > + .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk_input = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_CLK0_DIV,
> > + .bit_idx = 16,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk_input",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk2_input = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VIID_CLK0_DIV,
> > + .bit_idx = 16,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk2_input",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk2_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VID_CLK0_DIV,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vclk_input.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk2_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VIID_CLK0_DIV,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk2_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vclk2_input.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_CLK0_CTRL,
> > + .bit_idx = 19,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk2 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VIID_CLK0_CTRL,
> > + .bit_idx = 19,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk2",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk2_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk_div1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_CLK0_CTRL,
> > + .bit_idx = 0,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk_div1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk_div2_en = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_CLK0_CTRL,
> > + .bit_idx = 1,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk_div2_en",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk_div4_en = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_CLK0_CTRL,
> > + .bit_idx = 2,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk_div4_en",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk_div6_en = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_CLK0_CTRL,
> > + .bit_idx = 3,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk_div6_en",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk_div12_en = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_CLK0_CTRL,
> > + .bit_idx = 4,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk_div12_en",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk2_div1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VIID_CLK0_CTRL,
> > + .bit_idx = 0,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk2_div1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk2.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk2_div2_en = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VIID_CLK0_CTRL,
> > + .bit_idx = 1,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk2_div2_en",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk2.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk2_div4_en = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VIID_CLK0_CTRL,
> > + .bit_idx = 2,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk2_div4_en",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk2.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk2_div6_en = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VIID_CLK0_CTRL,
> > + .bit_idx = 3,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk2_div6_en",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk2.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vclk2_div12_en = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VIID_CLK0_CTRL,
> > + .bit_idx = 4,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vclk2_div12_en",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vclk2.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_vclk_div2 = {
> > + .mult = 1,
> > + .div = 2,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk_div2",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vclk_div2_en.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_vclk_div4 = {
> > + .mult = 1,
> > + .div = 4,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk_div4",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vclk_div4_en.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_vclk_div6 = {
> > + .mult = 1,
> > + .div = 6,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk_div6",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vclk_div6_en.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_vclk_div12 = {
> > + .mult = 1,
> > + .div = 12,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk_div12",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vclk_div12_en.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_vclk2_div2 = {
> > + .mult = 1,
> > + .div = 2,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk2_div2",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vclk2_div2_en.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_vclk2_div4 = {
> > + .mult = 1,
> > + .div = 4,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk2_div4",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vclk2_div4_en.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_vclk2_div6 = {
> > + .mult = 1,
> > + .div = 6,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk2_div6",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vclk2_div6_en.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_vclk2_div12 = {
> > + .mult = 1,
> > + .div = 12,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vclk2_div12",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vclk2_div12_en.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
> > +static const struct clk_hw *t7_cts_parent_hws[] = {
> > + &t7_vclk_div1.hw,
> > + &t7_vclk_div2.hw,
> > + &t7_vclk_div4.hw,
> > + &t7_vclk_div6.hw,
> > + &t7_vclk_div12.hw,
> > + &t7_vclk2_div1.hw,
> > + &t7_vclk2_div2.hw,
> > + &t7_vclk2_div4.hw,
> > + &t7_vclk2_div6.hw,
> > + &t7_vclk2_div12.hw
> > +};
> > +
> > +static struct clk_regmap t7_cts_enci_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VID_CLK0_DIV,
> > + .mask = 0xf,
> > + .shift = 28,
> > + .table = mux_table_cts_sel,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "cts_enci_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = t7_cts_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_cts_parent_hws),
> > + .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_cts_encp_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VID_CLK1_DIV,
> > + .mask = 0xf,
> > + .shift = 20,
> > + .table = mux_table_cts_sel,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "cts_encp_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = t7_cts_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_cts_parent_hws),
> > + .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_cts_vdac_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VIID_CLK1_DIV,
> > + .mask = 0xf,
> > + .shift = 28,
> > + .table = mux_table_cts_sel,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "cts_vdac_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = t7_cts_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_cts_parent_hws),
> > + .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +/* TOFIX: add support for cts_tcon */
> > +static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
> > +static const struct clk_hw *t7_cts_hdmi_tx_parent_hws[] = {
> > + &t7_vclk_div1.hw,
> > + &t7_vclk_div2.hw,
> > + &t7_vclk_div4.hw,
> > + &t7_vclk_div6.hw,
> > + &t7_vclk_div12.hw,
> > + &t7_vclk2_div1.hw,
> > + &t7_vclk2_div2.hw,
> > + &t7_vclk2_div4.hw,
> > + &t7_vclk2_div6.hw,
> > + &t7_vclk2_div12.hw
> > +};
> > +
> > +static struct clk_regmap t7_hdmi_tx_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HDMI_CLK_CTRL,
> > + .mask = 0xf,
> > + .shift = 16,
> > + .table = mux_table_hdmi_tx_sel,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmi_tx_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = t7_cts_hdmi_tx_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_cts_hdmi_tx_parent_hws),
> > + .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_cts_enci = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_CLK2_CTRL2,
> > + .bit_idx = 0,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "cts_enci",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_cts_enci_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_cts_encp = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_CLK2_CTRL2,
> > + .bit_idx = 2,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "cts_encp",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_cts_encp_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_cts_vdac = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_CLK2_CTRL2,
> > + .bit_idx = 4,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "cts_vdac",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_cts_vdac_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmi_tx = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_CLK2_CTRL2,
> > + .bit_idx = 5,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmi_tx",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hdmi_tx_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static const struct clk_parent_data t7_hdmitx_sys_parent_data[] = {
> > + { .fw_name = "xtal", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div5", }
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_sys_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HDMI_CLK_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmitx_sys_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_hdmitx_sys_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_hdmitx_sys_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_sys_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_HDMI_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmitx_sys_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmitx_sys_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_sys = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_HDMI_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmitx_sys",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmitx_sys.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_prif_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HTX_CLK_CTRL0,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmitx_prif_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_hdmitx_sys_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_hdmitx_sys_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_prif_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_HTX_CLK_CTRL0,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmitx_prif_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmitx_prif_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_prif = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_HTX_CLK_CTRL0,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmitx_prif",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmitx_prif.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_200m_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HTX_CLK_CTRL0,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmitx_200m_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_hdmitx_sys_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_hdmitx_sys_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_200m_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_HTX_CLK_CTRL0,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmitx_200m_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmitx_200m_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_200m = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_HTX_CLK_CTRL0,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmitx_200m",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmitx_200m.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_aud_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HTX_CLK_CTRL1,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmitx_aud_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_hdmitx_sys_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_hdmitx_sys_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_aud_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_HTX_CLK_CTRL1,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmitx_aud_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmitx_aud_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmitx_aud = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_HTX_CLK_CTRL1,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmitx_aud",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmitx_aud_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_5m_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL0,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_5m_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_hdmitx_sys_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_hdmitx_sys_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_5m_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL0,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_5m_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_5m_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_5m = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL0,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmirx_5m",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_5m_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_2m_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL0,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_2m_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_hdmitx_sys_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_hdmitx_sys_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_2m_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL0,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_2m_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_2m_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_2m = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL0,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmirx_2m",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_2m_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_cfg_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL1,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_cfg_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_hdmitx_sys_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_hdmitx_sys_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_cfg_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL1,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_cfg_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_cfg_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_cfg = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL1,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmirx_cfg",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_cfg_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_hdcp_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL1,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_hdcp_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_hdmitx_sys_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_hdmitx_sys_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_hdcp_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL1,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_hdcp_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_hdcp_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_hdcp = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL1,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmirx_hdcp",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_hdcp_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_aud_pll_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL2,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_aud_pll_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_hdmitx_sys_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_hdmitx_sys_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_aud_pll_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL2,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_aud_pll_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_aud_pll_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_aud_pll = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL2,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmirx_aud_pll",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_aud_pll_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_acr_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL2,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_acr_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_hdmitx_sys_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_hdmitx_sys_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_acr_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL2,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_acr_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_acr_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_acr = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL2,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmirx_acr",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_acr_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_meter_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL3,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_meter_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_hdmitx_sys_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_hdmitx_sys_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_meter_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL3,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmirx_meter_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_meter_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmirx_meter = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_HRX_CLK_CTRL3,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hdmirx_meter",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_hdmirx_meter_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vid_lock_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VID_LOCK_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vid_lock_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vid_lock_clk = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VID_LOCK_CLK_CTRL,
> > + .bit_idx = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vid_lock_clk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vid_lock_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_ts_clk_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_TS_CLK_CTRL,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "ts_clk_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_ts_clk_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_TS_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "ts_clk_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_ts_clk_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +/*mali_clk*/
> > +/*
> > + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
> > + * muxed by a glitch-free switch on Meson8b and Meson8m2 and later.
> > + *
> > + * CLK_SET_RATE_PARENT is added for mali_0_sel clock
> > + * 1.gp0 pll only support the 846M, avoid other rate 500/400M from it
> > + * 2.hifi pll is used for other module, skip it, avoid some rate from it
> > + */
> > +static u32 mux_table_mali[] = { 0, 3, 4, 5, 6};
> > +
> > +static const struct clk_parent_data t7_mali_0_1_parent_data[] = {
> > + { .fw_name = "xtal", },
> > + { .fw_name = "fclk_div2p5", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div5", },
> > +};
> > +
> > +static struct clk_regmap t7_mali_0_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_MALI_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + .table = mux_table_mali,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mali_0_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_mali_0_1_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_mali_0_1_parent_data),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mali_0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_MALI_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mali_0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mali_0_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mali_0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_MALI_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mali_0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mali_0_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mali_1_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_MALI_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + .table = mux_table_mali,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mali_1_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_mali_0_1_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_mali_0_1_parent_data),
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mali_1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_MALI_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mali_1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mali_1_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mali_1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_MALI_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mali_1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mali_1_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static const struct clk_hw *t7_mali_parent_hws[] = {
> > + &t7_mali_0.hw,
> > + &t7_mali_1.hw
> > +};
> > +
> > +static struct clk_regmap t7_mali_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_MALI_CLK_CTRL,
> > + .mask = 1,
> > + .shift = 31,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mali",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = t7_mali_parent_hws,
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +/* cts_vdec_clk */
> > +static const struct clk_parent_data t7_dec_parent_hws[] = {
> > + { .fw_name = "fclk_div2p5", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div7", },
> > + { .fw_name = "hifi_pll", },
> > + { .fw_name = "gp0_pll", },
> > + { .fw_name = "xtal", }
> > +};
> > +
> > +static struct clk_regmap t7_vdec_p0_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vdec_p0_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dec_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_dec_parent_hws),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vdec_p0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VDEC_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vdec_p0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vdec_p0_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vdec_p0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VDEC_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vdec_p0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vdec_p0_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vdec_p1_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC3_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vdec_p1_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dec_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_dec_parent_hws),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vdec_p1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VDEC3_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vdec_p1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vdec_p1_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vdec_p1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VDEC3_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vdec_p1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vdec_p1_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vdec_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC3_CLK_CTRL,
> > + .mask = 0x1,
> > + .shift = 15,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vdec_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vdec_p0.hw,
> > + &t7_vdec_p1.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hcodec_p0_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hcodec_p0_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dec_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_dec_parent_hws),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hcodec_p0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VDEC_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hcodec_p0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hcodec_p0_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hcodec_p0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VDEC_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hcodec_p0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hcodec_p0_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hcodec_p1_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC3_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hcodec_p1_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dec_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_dec_parent_hws),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hcodec_p1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VDEC3_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hcodec_p1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hcodec_p1_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hcodec_p1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VDEC3_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hcodec_p1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hcodec_p1_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hcodec_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC3_CLK_CTRL,
> > + .mask = 0x1,
> > + .shift = 31,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hcodec_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hcodec_p0.hw,
> > + &t7_hcodec_p1.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static u32 mux_table_vdec[] = { 0, 1, 2, 3, 4};
> > +
> > +static const struct clk_parent_data t7_vdec_parent_data[] = {
> > + { .fw_name = "fclk_div2p5", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div7", },
> > +};
> > +
> > +static struct clk_regmap t7_hevcb_p0_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC2_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + .flags = CLK_MUX_ROUND_CLOSEST,
> > + .table = mux_table_vdec,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hevcb_p0_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_vdec_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vdec_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcb_p0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VDEC2_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + .flags = CLK_DIVIDER_ROUND_CLOSEST,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hevcb_p0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hevcb_p0_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcb_p0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VDEC2_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hevcb_p0_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hevcb_p0_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcb_p1_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC4_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hevcb_p1_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_vdec_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vdec_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcb_p1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VDEC4_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hevc_p1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hevcb_p1_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcb_p1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VDEC4_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hevcb_p1_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hevcb_p1_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcb_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC4_CLK_CTRL,
> > + .mask = 0x1,
> > + .shift = 31,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hevcb_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hevcb_p0.hw,
> > + &t7_hevcb_p1.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcf_p0_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC2_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hevcf_p0_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dec_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_dec_parent_hws),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcf_p0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VDEC2_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hevcf_p0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hevcf_p0_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcf_p0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VDEC2_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hevcf_p0_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hevcf_p0_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcf_p1_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC4_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hevcf_p1_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dec_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_dec_parent_hws),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcf_p1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VDEC4_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hevcf_p1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hevcf_p1_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcf_p1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VDEC4_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hevcf_p1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hevcf_p1_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hevcf_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDEC4_CLK_CTRL,
> > + .mask = 0x1,
> > + .shift = 15,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "hevcf_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hevcf_p0.hw,
> > + &t7_hevcf_p1.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +/*cts_wave420l_a/b/c_clk*/
> > +static const struct clk_parent_data t7_wave_parent_data[] = {
> > + { .fw_name = "xtal", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div7", },
> > + { .fw_name = "mpll2", },
> > + { .fw_name = "mpll3", },
> > + { .fw_name = "gp1_pll", }
> > +};
> > +
> > +static struct clk_regmap t7_wave_a_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_WAVE521_CLK_CTRL2,
> > + .mask = 0x7,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "wave_a_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_wave_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_wave_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_wave_a_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_WAVE521_CLK_CTRL2,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "wave_a_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_wave_a_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_wave_aclk = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_WAVE521_CLK_CTRL2,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "wave_aclk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_wave_a_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_wave_b_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_WAVE521_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "wave_b_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_wave_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_wave_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_wave_b_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_WAVE521_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "wave_b_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_wave_b_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_wave_bclk = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_WAVE521_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "wave_bclk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_wave_b_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_wave_c_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_WAVE521_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "wave_c_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_wave_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_wave_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_wave_c_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_WAVE521_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "wave_c_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_wave_c_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_wave_cclk = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_WAVE521_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "wave_cclk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_wave_c_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mipi_isp_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mipi_isp_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + /* Share parent with wave clk */
> > + .parent_data = t7_wave_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_wave_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mipi_isp_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mipi_isp_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mipi_isp_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mipi_isp = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "mipi_isp",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mipi_isp_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static const struct clk_parent_data t7_mipi_csi_parent_data[] = {
> > + { .fw_name = "xtal", },
> > + { .fw_name = "hifi_pll", },
> > + { .fw_name = "mpll1", },
> > + { .fw_name = "mpll2", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div7", }
> > +};
> > +
> > +static struct clk_regmap t7_mipi_csi_phy_sel0 = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mipi_csi_phy_sel0",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_mipi_csi_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_mipi_csi_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mipi_csi_phy_div0 = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mipi_csi_phy_div0",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mipi_csi_phy_sel0.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mipi_csi_phy0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "mipi_csi_phy0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mipi_csi_phy_div0.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mipi_csi_phy_sel1 = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mipi_csi_phy_sel1",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_mipi_csi_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_mipi_csi_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mipi_csi_phy_div1 = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mipi_csi_phy_div1",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mipi_csi_phy_sel1.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mipi_csi_phy1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "mipi_csi_phy1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mipi_csi_phy_div1.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mipi_csi_phy_clk = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL,
> > + .mask = 0x1,
> > + .shift = 31,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mipi_csi_phy_clk",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mipi_csi_phy0.hw,
> > + &t7_mipi_csi_phy1.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static const struct clk_parent_data t7_vpu_parent_data[] = {
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div7", },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_0_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VPU_CLK_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vpu_0_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_vpu_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vpu_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VPU_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vpu_0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vpu_0_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VPU_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vpu_0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vpu_0_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_1_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VPU_CLK_CTRL,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vpu_1_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_vpu_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vpu_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VPU_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vpu_1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vpu_1_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VPU_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vpu_1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vpu_1_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VPU_CLK_CTRL,
> > + .mask = 1,
> > + .shift = 31,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vpu",
> > + .ops = &clk_regmap_mux_ops,
> > + /*
> > + * bit 31 selects from 2 possible parents:
> > + * vpu_0 or vpu_1
> > + */
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vpu_0.hw,
> > + &t7_vpu_1.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_NO_REPARENT,
> > + },
> > +};
> > +
> > +static const struct clk_parent_data vpu_clkb_tmp_parent_data[] = {
> > + { .hw = &t7_vpu.hw, },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div7", },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkb_tmp_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VPU_CLKB_CTRL,
> > + .mask = 0x3,
> > + .shift = 20,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vpu_clkb_tmp_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = vpu_clkb_tmp_parent_data,
> > + .num_parents = ARRAY_SIZE(vpu_clkb_tmp_parent_data),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkb_tmp_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VPU_CLKB_CTRL,
> > + .shift = 16,
> > + .width = 4,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vpu_clkb_tmp_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vpu_clkb_tmp_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkb_tmp = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VPU_CLKB_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vpu_clkb_tmp",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vpu_clkb_tmp_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkb_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VPU_CLKB_CTRL,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vpu_clkb_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vpu_clkb_tmp.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkb = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VPU_CLKB_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vpu_clkb",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vpu_clkb_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static const struct clk_parent_data vpu_clkc_parent_data[] = {
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div7", },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkc_p0_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VPU_CLKC_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vpu_clkc_p0_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = vpu_clkc_parent_data,
> > + .num_parents = ARRAY_SIZE(vpu_clkc_parent_data),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkc_p0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VPU_CLKC_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vpu_clkc_p0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vpu_clkc_p0_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkc_p0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VPU_CLKC_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vpu_clkc_p0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vpu_clkc_p0_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkc_p1_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VPU_CLKC_CTRL,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vpu_clkc_p1_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = vpu_clkc_parent_data,
> > + .num_parents = ARRAY_SIZE(vpu_clkc_parent_data),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkc_p1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VPU_CLKC_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vpu_clkc_p1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vpu_clkc_p1_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkc_p1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VPU_CLKC_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vpu_clkc_p1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vpu_clkc_p1_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vpu_clkc_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VPU_CLKC_CTRL,
> > + .mask = 0x1,
> > + .shift = 31,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vpu_clkc_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vpu_clkc_p0.hw,
> > + &t7_vpu_clkc_p1.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static u32 t7_vapb_table[] = { 0, 1, 2, 3, 7};
> > +static const struct clk_parent_data t7_vapb_parent_data[] = {
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div7", },
> > + { .fw_name = "fclk_div2p5", },
> > +};
> > +
> > +static struct clk_regmap t7_vapb_0_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VAPBCLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + .table = t7_vapb_table
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vapb_0_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_vapb_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vapb_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vapb_0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VAPBCLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vapb_0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vapb_0_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vapb_0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VAPBCLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vapb_0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vapb_0_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vapb_1_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VAPBCLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vapb_1_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_vapb_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vapb_parent_data),
> > + .flags = CLK_SET_RATE_NO_REPARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vapb_1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VAPBCLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vapb_1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vapb_1_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vapb_1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VAPBCLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vapb_1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vapb_1_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vapb = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VAPBCLK_CTRL,
> > + .mask = 1,
> > + .shift = 31,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vapb_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vapb_0.hw,
> > + &t7_vapb_1.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gdcclk_0_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_GDC_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + .table = t7_vapb_table
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gdcclk_0_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + /* Share parent with vapb clk */
> > + .parent_data = t7_vapb_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vapb_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gdcclk_0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_GDC_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gdcclk_0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_gdcclk_0_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gdcclk_0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_GDC_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "gdcclk_0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_gdcclk_0_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gdcclk_1_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_GDC_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gdcclk_1_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_vapb_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vapb_parent_data),
> > + .flags = CLK_SET_RATE_NO_REPARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gdcclk_1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_GDC_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gdcclk_1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_gdcclk_1_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gdcclk_1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_GDC_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "gdcclk_1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_gdcclk_1_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gdcclk = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_GDC_CLK_CTRL,
> > + .mask = 1,
> > + .shift = 31,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gdcclk_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_gdcclk_0.hw,
> > + &t7_gdcclk_1.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gdc_clk = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_GDC_CLK_CTRL,
> > + .bit_idx = 30,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "gdc_clk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_gdcclk.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dewarpclk_0_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_AMLGDC_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + .table = t7_vapb_table
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dewarpclk_0_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + /* Share parent with vapb clk */
> > + .parent_data = t7_vapb_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vapb_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dewarpclk_0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_AMLGDC_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dewarpclk_0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dewarpclk_0_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dewarpclk_0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_AMLGDC_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dewarpclk_0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_dewarpclk_0_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dewarpclk_1_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_AMLGDC_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dewarpclk_1_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_vapb_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_vapb_parent_data),
> > + .flags = CLK_SET_RATE_NO_REPARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dewarpclk_1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_AMLGDC_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dewarpclk_1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dewarpclk_1_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dewarpclk_1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_AMLGDC_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dewarpclk_1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dewarpclk_1_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dewarpclk = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_AMLGDC_CLK_CTRL,
> > + .mask = 1,
> > + .shift = 31,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dewarpclk_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dewarpclk_0.hw,
> > + &t7_dewarpclk_1.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dewarp_clk = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_AMLGDC_CLK_CTRL,
> > + .bit_idx = 30,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dewarp_clk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dewarpclk.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static u32 t7_anakin_table[] = { 0, 1, 2, 3, 7};
> > +static const struct clk_parent_data t7_anakin_parent_data[] = {
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div2", },
> > + { .fw_name = "fclk_div2p5", },
> > +};
> > +
> > +static struct clk_regmap t7_anakin_0_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_ANAKIN_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + .table = t7_anakin_table
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "anakin_0_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_anakin_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_anakin_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_anakin_0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_ANAKIN_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "anakin_0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_anakin_0_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_anakin_0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_ANAKIN_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "anakin_0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_anakin_0_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_anakin_1_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_ANAKIN_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "anakin_1_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_anakin_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_anakin_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_anakin_1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_ANAKIN_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "anakin_1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_anakin_1_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_anakin_1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_ANAKIN_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "anakin_1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_anakin_1_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_anakin = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_ANAKIN_CLK_CTRL,
> > + .mask = 1,
> > + .shift = 31,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "anakin_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_anakin_0.hw,
> > + &t7_anakin_1.hw
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_anakin_clk = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_ANAKIN_CLK_CTRL,
> > + .bit_idx = 30,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "anakin_clk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_anakin.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_ge2d_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VAPBCLK_CTRL,
> > + .bit_idx = 30,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "ge2d_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_vapb.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +/*cts_hdcp22_esmclk*/
> > +
> > +/*cts_hdcp22_skpclk*/
> > +
> > +/* cts_vdin_meas_clk */
> > +static const struct clk_parent_data t7_vdin_parent_hws[] = {
> > + { .fw_name = "xtal", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div5", },
> > + { .hw = &t7_vid_pll.hw }
> > +};
> > +
> > +static struct clk_regmap t7_vdin_meas_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vdin_meas_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_vdin_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_vdin_parent_hws),
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vdin_meas_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "vdin_meas_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vdin_meas_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_vdin_meas_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "vdin_meas_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_vdin_meas_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static const struct clk_parent_data t7_sd_emmc_clk0_parent_data[] = {
> > + { .fw_name = "xtal", },
> > + { .fw_name = "fclk_div2", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "hifi_pll", },
> > + { .fw_name = "fclk_div2p5", },
> > + { .fw_name = "mpll2", },
> > + { .fw_name = "mpll3", },
> > + { .fw_name = "gp0_pll", }
> > +};
> > +
> > +static struct clk_regmap t7_sd_emmc_c_clk0_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_NAND_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "sd_emmc_c_clk0_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_sd_emmc_clk0_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_sd_emmc_clk0_parent_data),
> > + .flags = CLK_GET_RATE_NOCACHE
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sd_emmc_c_clk0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_NAND_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "sd_emmc_c_clk0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sd_emmc_c_clk0_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sd_emmc_c_clk0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_NAND_CLK_CTRL,
> > + .bit_idx = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sd_emmc_c_clk0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sd_emmc_c_clk0_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sd_emmc_a_clk0_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "sd_emmc_a_clk0_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_sd_emmc_clk0_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_sd_emmc_clk0_parent_data),
> > + .flags = CLK_GET_RATE_NOCACHE
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sd_emmc_a_clk0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "sd_emmc_a_clk0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sd_emmc_a_clk0_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sd_emmc_a_clk0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
> > + .bit_idx = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sd_emmc_a_clk0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sd_emmc_a_clk0_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sd_emmc_b_clk0_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "sd_emmc_b_clk0_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_sd_emmc_clk0_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_sd_emmc_clk0_parent_data),
> > + .flags = CLK_GET_RATE_NOCACHE
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sd_emmc_b_clk0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "sd_emmc_b_clk0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sd_emmc_b_clk0_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sd_emmc_b_clk0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL,
> > + .bit_idx = 23,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sd_emmc_b_clk0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sd_emmc_b_clk0_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +/*cts_cdac_clk*/
> > +
> > +static const struct clk_parent_data t7_spicc_parent_hws[] = {
> > + { .fw_name = "xtal", },
> > + { .hw = &t7_sys_clk.hw },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div2", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div7", },
> > + { .fw_name = "hifi_pll", }
> > +};
> > +
> > +static struct clk_regmap t7_spicc0_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc0_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_spicc_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_spicc_parent_hws),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc0_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL,
> > + .shift = 0,
> > + .width = 6,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc0_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc0_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc0_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL,
> > + .bit_idx = 6,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "spicc0_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc0_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc1_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL,
> > + .mask = 0x7,
> > + .shift = 23,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc1_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_spicc_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_spicc_parent_hws),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc1_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL,
> > + .shift = 16,
> > + .width = 6,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc1_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc1_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc1_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL,
> > + .bit_idx = 22,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "spicc1_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc1_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc2_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL1,
> > + .mask = 0x7,
> > + .shift = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc2_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_spicc_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_spicc_parent_hws),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc2_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL1,
> > + .shift = 0,
> > + .width = 6,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc2_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc2_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc2_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL1,
> > + .bit_idx = 6,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "spicc2_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc2_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc3_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL1,
> > + .mask = 0x7,
> > + .shift = 23,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc3_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_spicc_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_spicc_parent_hws),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc3_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL1,
> > + .shift = 16,
> > + .width = 6,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc3_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc3_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc3_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL1,
> > + .bit_idx = 22,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "spicc3_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc3_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc4_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL2,
> > + .mask = 0x7,
> > + .shift = 7,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc4_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_spicc_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_spicc_parent_hws),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc4_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL2,
> > + .shift = 0,
> > + .width = 6,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc4_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc4_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc4_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL2,
> > + .bit_idx = 6,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "spicc4_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc4_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc5_mux = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL2,
> > + .mask = 0x7,
> > + .shift = 23,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc5_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_spicc_parent_hws,
> > + .num_parents = ARRAY_SIZE(t7_spicc_parent_hws),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc5_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL2,
> > + .shift = 16,
> > + .width = 6,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "spicc5_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc5_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_spicc5_gate = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_SPICC_CLK_CTRL2,
> > + .bit_idx = 22,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "spicc5_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_spicc5_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +/*cts_bt656*/
> > +
> > +static const struct clk_parent_data t7_pwm_parent_data[] = {
> > + { .fw_name = "xtal", },
> > + { .hw = &t7_vid_pll.hw },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div3", }
> > +};
> > +
> > +static struct clk_regmap t7_pwm_a_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_AB_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_a_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + .flags = CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_a_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_AB_CTRL,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_a_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_a_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_a_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_AB_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_a_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_a_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_b_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_AB_CTRL,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_b_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + .flags = CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_b_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_AB_CTRL,
> > + .shift = 16,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_b_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_b_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_b_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_AB_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_b_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_b_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_c_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_CD_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_c_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + .flags = CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_c_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_CD_CTRL,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_c_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_c_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_c_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_CD_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_c_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_c_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_d_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_CD_CTRL,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_d_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + .flags = CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_d_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_CD_CTRL,
> > + .shift = 16,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_d_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_d_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_d_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_CD_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_d_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_d_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_e_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_EF_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_e_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + .flags = CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_e_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_EF_CTRL,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_e_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_e_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_e_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_EF_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_e_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_e_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_f_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_EF_CTRL,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_f_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + .flags = CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_f_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_EF_CTRL,
> > + .shift = 16,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_f_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_f_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_f_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_EF_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_f_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_f_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_a_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_AB_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_a_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_a_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_AB_CTRL,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_a_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_a_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_a_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_AB_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_a_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_a_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_b_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_AB_CTRL,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_b_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_b_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_AB_CTRL,
> > + .shift = 16,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_b_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_b_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_b_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_AB_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_b_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_b_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_c_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_CD_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_c_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_c_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_CD_CTRL,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_c_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_c_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_c_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_CD_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_c_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_c_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_d_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_CD_CTRL,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_d_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_d_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_CD_CTRL,
> > + .shift = 16,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_d_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_d_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_d_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_CD_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_d_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_d_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_e_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_EF_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_e_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_e_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_EF_CTRL,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_e_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_e_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_e_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_EF_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_e_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_e_div.hw
> > + },
> > + .num_parents = 1,
> > + /*The clock feeds the GPU,it should be always on*/
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_f_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_EF_CTRL,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_f_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_f_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_EF_CTRL,
> > + .shift = 16,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_f_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_f_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_f_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_EF_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_f_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_f_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_g_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_GH_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_g_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_g_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_GH_CTRL,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_g_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_g_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_g_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_GH_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_g_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_g_div.hw
> > + },
> > + .num_parents = 1,
> > + /*This clock feeds the DDR,it should be always on.*/
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_h_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_GH_CTRL,
> > + .mask = 0x3,
> > + .shift = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_h_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_pwm_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_pwm_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_h_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_GH_CTRL,
> > + .shift = 16,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_h_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_h_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pwm_ao_h_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_PWM_CLK_AO_GH_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pwm_ao_h_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pwm_ao_h_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static u32 t7_dsi_meas_table[] = { 0, 1, 2, 3, 6, 7};
> > +
> > +static const struct clk_parent_data t7_dsi_meas_parent_data[] = {
> > + { .fw_name = "xtal", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div2", },
> > + { .fw_name = "fclk_div7", }
> > +};
> > +
> > +static struct clk_regmap t7_dsi_a_meas_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL,
> > + .mask = 0x3,
> > + .shift = 9,
> > + .table = t7_dsi_meas_table
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi_a_meas_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dsi_meas_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_dsi_meas_parent_data)
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dsi_a_meas_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi_a_meas_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dsi_a_meas_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dsi_a_meas_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi_a_meas_clk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dsi_a_meas_div.hw
> > + },
> > + .num_parents = 1,
> > + /* config it in U-boot, ignore it to avoid display abnormal */
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dsi_b_meas_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL,
> > + .mask = 0x3,
> > + .shift = 21,
> > + .table = t7_dsi_meas_table
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi_b_meas_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dsi_meas_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_dsi_meas_parent_data)
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dsi_b_meas_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL,
> > + .shift = 12,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi_b_meas_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dsi_b_meas_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dsi_b_meas_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL,
> > + .bit_idx = 20,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi_b_meas_clk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dsi_b_meas_div.hw
> > + },
> > + .num_parents = 1,
> > + /* config it in U-boot, ignore it to avoid display abnormal */
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static u32 t7_dsi_phy_table[] = { 4, 5, 6, 7};
> > +static const struct clk_parent_data t7_dsi_phy_parent_data[] = {
> > + { .fw_name = "fclk_div2", },
> > + { .fw_name = "fclk_div2p5", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div7", },
> > +};
> > +
> > +static struct clk_regmap t7_dsi0_phy_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
> > + .mask = 0x3,
> > + .shift = 12,
> > + .table = t7_dsi_phy_table
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi0_phy_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dsi_phy_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_dsi_phy_parent_data)
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dsi0_phy_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi0_phy_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dsi0_phy_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dsi0_phy_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi0_phy_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dsi0_phy_div.hw
> > + },
> > + .num_parents = 1,
> > + /* config it in U-boot, ignore it to avoid display abnormal */
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dsi1_phy_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
> > + .mask = 0x3,
> > + .shift = 25,
> > + .table = t7_dsi_phy_table
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi1_phy_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_dsi_phy_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_dsi_phy_parent_data)
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dsi1_phy_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
> > + .shift = 16,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi1_phy_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dsi1_phy_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_dsi1_phy_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "dsi1_phy_gate",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_dsi1_phy_div.hw
> > + },
> > + .num_parents = 1,
> > + /* config it in U-boot, ignore it to avoid display abnormal */
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_eth_rmii_sel = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_ETH_CLK_CTRL,
> > + .mask = 0x1,
> > + .shift = 9,
> > + .table = t7_dsi_phy_table
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "eth_rmii_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = (const struct clk_parent_data []) {
> > + { .fw_name = "fclk_div2", },
> > + { .fw_name = "gp1_pll", }
> > + },
> > + .num_parents = 2
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_eth_rmii_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_ETH_CLK_CTRL,
> > + .shift = 0,
> > + .width = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "eth_rmii_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_eth_rmii_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_eth_rmii = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_ETH_CLK_CTRL,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "eth_rmii",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_eth_rmii_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_eth_div8 = {
> > + .mult = 1,
> > + .div = 8,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "eth_div8",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "fclk_div2",
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_eth_125m = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_ETH_CLK_CTRL,
> > + .bit_idx = 7,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "eth_125m",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_eth_div8.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_saradc_mux = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = CLKCTRL_SAR_CLK_CTRL0,
> > + .mask = 0x3,
> > + .shift = 9,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "saradc_mux",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = (const struct clk_parent_data []) {
> > + { .fw_name = "xtal", },
> > + { .hw = &t7_sys_clk.hw },
> > + },
> > + .num_parents = 2,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_saradc_div = {
> > + .data = &(struct clk_regmap_div_data) {
> > + .offset = CLKCTRL_SAR_CLK_CTRL0,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "saradc_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_saradc_mux.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_saradc_gate = {
> > + .data = &(struct clk_regmap_gate_data) {
> > + .offset = CLKCTRL_SAR_CLK_CTRL0,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "saradc_clk",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_saradc_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +/* gen clk */
> > +static u32 t7_gen_clk_mux_table[] = { 0, 5, 6, 7, 19, 21, 22,
> > + 23, 24, 25, 26, 27, 28 };
> > +
> > +static const struct clk_parent_data t7_gen_clk_parent_data[] = {
> > + { .fw_name = "xtal", },
> > + { .fw_name = "gp0_pll", },
> > + { .fw_name = "gp1_pll", },
> > + { .fw_name = "hifi_pll", },
> > + { .fw_name = "fclk_div2", },
> > + { .fw_name = "fclk_div3", },
> > + { .fw_name = "fclk_div4", },
> > + { .fw_name = "fclk_div5", },
> > + { .fw_name = "fclk_div7", },
> > + { .fw_name = "mpll0", },
> > + { .fw_name = "mpll1", },
> > + { .fw_name = "mpll2", },
> > + { .fw_name = "mpll3", }
> > +};
> > +
> > +static struct clk_regmap t7_gen_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = CLKCTRL_GEN_CLK_CTRL,
> > + .mask = 0x1f,
> > + .shift = 12,
> > + .table = t7_gen_clk_mux_table,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gen_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = t7_gen_clk_parent_data,
> > + .num_parents = ARRAY_SIZE(t7_gen_clk_parent_data),
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gen_div = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = CLKCTRL_GEN_CLK_CTRL,
> > + .shift = 0,
> > + .width = 11,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gen_div",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_gen_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gen = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_GEN_CLK_CTRL,
> > + .bit_idx = 11,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "gen",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_gen_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +#define MESON_T7_SYS_GATE(_name, _reg, _bit) \
> > +struct clk_regmap _name = { \
> > + .data = &(struct clk_regmap_gate_data) { \
> > + .offset = (_reg), \
> > + .bit_idx = (_bit), \
> > + }, \
> > + .hw.init = &(struct clk_init_data) { \
> > + .name = #_name, \
> > + .ops = &clk_regmap_gate_ops, \
> > + .parent_hws = (const struct clk_hw *[]) { \
> > + &t7_sys_clk.hw \
> > + }, \
> > + .num_parents = 1, \
> > + .flags = CLK_IGNORE_UNUSED, \
> > + }, \
> > +}
> > +
> > +/*CLKCTRL_SYS_CLK_EN0_REG0*/
> > +static MESON_T7_SYS_GATE(t7_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0);
> > +static MESON_T7_SYS_GATE(t7_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1);
> > +static MESON_T7_SYS_GATE(t7_mipi_dsi_a, CLKCTRL_SYS_CLK_EN0_REG0, 2);
> > +static MESON_T7_SYS_GATE(t7_mipi_dsi_b, CLKCTRL_SYS_CLK_EN0_REG0, 3);
> > +static MESON_T7_SYS_GATE(t7_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4);
> > +static MESON_T7_SYS_GATE(t7_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6);
> > +static MESON_T7_SYS_GATE(t7_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13);
> > +static MESON_T7_SYS_GATE(t7_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14);
> > +static MESON_T7_SYS_GATE(t7_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16);
> > +static MESON_T7_SYS_GATE(t7_gdc, CLKCTRL_SYS_CLK_EN0_REG0, 17);
> > +static MESON_T7_SYS_GATE(t7_deswarp, CLKCTRL_SYS_CLK_EN0_REG0, 18);
> > +static MESON_T7_SYS_GATE(t7_ampipe_nand, CLKCTRL_SYS_CLK_EN0_REG0, 19);
> > +static MESON_T7_SYS_GATE(t7_ampipe_eth, CLKCTRL_SYS_CLK_EN0_REG0, 20);
> > +static MESON_T7_SYS_GATE(t7_am2axi0, CLKCTRL_SYS_CLK_EN0_REG0, 21);
> > +static MESON_T7_SYS_GATE(t7_am2axi1, CLKCTRL_SYS_CLK_EN0_REG0, 22);
> > +static MESON_T7_SYS_GATE(t7_am2axi2, CLKCTRL_SYS_CLK_EN0_REG0, 23);
> > +static MESON_T7_SYS_GATE(t7_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24);
> > +static MESON_T7_SYS_GATE(t7_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25);
> > +static MESON_T7_SYS_GATE(t7_sdemmcc, CLKCTRL_SYS_CLK_EN0_REG0, 26);
> > +static MESON_T7_SYS_GATE(t7_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27);
> > +static MESON_T7_SYS_GATE(t7_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28);
> > +static MESON_T7_SYS_GATE(t7_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29);
> > +static MESON_T7_SYS_GATE(t7_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30);
> > +static MESON_T7_SYS_GATE(t7_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31);
> > +
> > +/*CLKCTRL_SYS_CLK_EN0_REG1*/
> > +static MESON_T7_SYS_GATE(t7_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0);
> > +static MESON_T7_SYS_GATE(t7_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3);
> > +static MESON_T7_SYS_GATE(t7_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5);
> > +static MESON_T7_SYS_GATE(t7_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6);
> > +static MESON_T7_SYS_GATE(t7_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7);
> > +static MESON_T7_SYS_GATE(t7_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8);
> > +static MESON_T7_SYS_GATE(t7_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9);
> > +static MESON_T7_SYS_GATE(t7_uart_f, CLKCTRL_SYS_CLK_EN0_REG1, 10);
> > +static MESON_T7_SYS_GATE(t7_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11);
> > +static MESON_T7_SYS_GATE(t7_spicc2, CLKCTRL_SYS_CLK_EN0_REG1, 12);
> > +static MESON_T7_SYS_GATE(t7_spicc3, CLKCTRL_SYS_CLK_EN0_REG1, 13);
> > +static MESON_T7_SYS_GATE(t7_spicc4, CLKCTRL_SYS_CLK_EN0_REG1, 14);
> > +static MESON_T7_SYS_GATE(t7_ts_a73, CLKCTRL_SYS_CLK_EN0_REG1, 15);
> > +static MESON_T7_SYS_GATE(t7_ts_a53, CLKCTRL_SYS_CLK_EN0_REG1, 16);
> > +static MESON_T7_SYS_GATE(t7_spicc5, CLKCTRL_SYS_CLK_EN0_REG1, 17);
> > +static MESON_T7_SYS_GATE(t7_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20);
> > +static MESON_T7_SYS_GATE(t7_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21);
> > +static MESON_T7_SYS_GATE(t7_spicc1, CLKCTRL_SYS_CLK_EN0_REG1, 22);
> > +static MESON_T7_SYS_GATE(t7_pcie, CLKCTRL_SYS_CLK_EN0_REG1, 24);
> > +static MESON_T7_SYS_GATE(t7_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26);
> > +static MESON_T7_SYS_GATE(t7_pcie_phy, CLKCTRL_SYS_CLK_EN0_REG1, 27);
> > +static MESON_T7_SYS_GATE(t7_i2c_ao_a, CLKCTRL_SYS_CLK_EN0_REG1, 28);
> > +static MESON_T7_SYS_GATE(t7_i2c_ao_b, CLKCTRL_SYS_CLK_EN0_REG1, 29);
> > +static MESON_T7_SYS_GATE(t7_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30);
> > +static MESON_T7_SYS_GATE(t7_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31);
> > +
> > +/*CLKCTRL_SYS_CLK_EN0_REG2*/
> > +static MESON_T7_SYS_GATE(t7_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0);
> > +static MESON_T7_SYS_GATE(t7_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1);
> > +static MESON_T7_SYS_GATE(t7_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2);
> > +static MESON_T7_SYS_GATE(t7_i2c_m_f, CLKCTRL_SYS_CLK_EN0_REG2, 3);
> > +static MESON_T7_SYS_GATE(t7_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4);
> > +static MESON_T7_SYS_GATE(t7_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5);
> > +static MESON_T7_SYS_GATE(t7_hdmirx_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 8);
> > +static MESON_T7_SYS_GATE(t7_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11);
> > +static MESON_T7_SYS_GATE(t7_mipi_isp_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 17);
> > +static MESON_T7_SYS_GATE(t7_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18);
> > +static MESON_T7_SYS_GATE(t7_pclk_sys_cpu_apb, CLKCTRL_SYS_CLK_EN0_REG2, 19);
> > +static MESON_T7_SYS_GATE(t7_a73pclk_cpu_apb, CLKCTRL_SYS_CLK_EN0_REG2, 20);
> > +static MESON_T7_SYS_GATE(t7_dspa, CLKCTRL_SYS_CLK_EN0_REG2, 21);
> > +static MESON_T7_SYS_GATE(t7_dspb, CLKCTRL_SYS_CLK_EN0_REG2, 22);
> > +static MESON_T7_SYS_GATE(t7_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25);
> > +static MESON_T7_SYS_GATE(t7_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28);
> > +static MESON_T7_SYS_GATE(t7_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30);
> > +static MESON_T7_SYS_GATE(t7_ts_gpu, CLKCTRL_SYS_CLK_EN0_REG2, 31);
> > +
> > +/*CLKCTRL_SYS_CLK_EN0_REG3*/
> > +static MESON_T7_SYS_GATE(t7_ts_nna, CLKCTRL_SYS_CLK_EN0_REG3, 0);
> > +static MESON_T7_SYS_GATE(t7_ts_vpu, CLKCTRL_SYS_CLK_EN0_REG3, 1);
> > +static MESON_T7_SYS_GATE(t7_ts_hevc, CLKCTRL_SYS_CLK_EN0_REG3, 2);
> > +static MESON_T7_SYS_GATE(t7_pwm_ao_ab, CLKCTRL_SYS_CLK_EN0_REG3, 3);
> > +static MESON_T7_SYS_GATE(t7_pwm_ao_cd, CLKCTRL_SYS_CLK_EN0_REG3, 4);
> > +static MESON_T7_SYS_GATE(t7_pwm_ao_ef, CLKCTRL_SYS_CLK_EN0_REG3, 5);
> > +static MESON_T7_SYS_GATE(t7_pwm_ao_gh, CLKCTRL_SYS_CLK_EN0_REG3, 6);
> > +static MESON_T7_SYS_GATE(t7_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7);
> > +static MESON_T7_SYS_GATE(t7_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8);
> > +static MESON_T7_SYS_GATE(t7_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9);
> > +
> > +/* Array of all clocks provided by this provider */
> > +static struct clk_hw *t7_periphs_hw_clks[] = {
> > + [CLKID_RTC_32K_CLKIN] = &t7_rtc_32k_clkin.hw,
> > + [CLKID_RTC_32K_DIV] = &t7_rtc_32k_div.hw,
> > + [CLKID_RTC_32K_XATL] = &t7_rtc_32k_xtal.hw,
> > + [CLKID_RTC_32K_MUX] = &t7_rtc_32k_sel.hw,
> > + [CLKID_RTC_CLK] = &t7_rtc_clk.hw,
> > + [CLKID_SYS_CLK_B_MUX] = &t7_sysclk_b_sel.hw,
> > + [CLKID_SYS_CLK_B_DIV] = &t7_sysclk_b_div.hw,
> > + [CLKID_SYS_CLK_B_GATE] = &t7_sysclk_b.hw,
> > + [CLKID_SYS_CLK_A_MUX] = &t7_sysclk_a_sel.hw,
> > + [CLKID_SYS_CLK_A_DIV] = &t7_sysclk_a_div.hw,
> > + [CLKID_SYS_CLK_A_GATE] = &t7_sysclk_a.hw,
> > + [CLKID_SYS_CLK] = &t7_sys_clk.hw,
> > + [CLKID_CECA_32K_CLKIN] = &t7_ceca_32k_clkin.hw,
> > + [CLKID_CECA_32K_DIV] = &t7_ceca_32k_div.hw,
> > + [CLKID_CECA_32K_MUX_PRE] = &t7_ceca_32k_sel_pre.hw,
> > + [CLKID_CECA_32K_MUX] = &t7_ceca_32k_sel.hw,
> > + [CLKID_CECA_32K_CLKOUT] = &t7_ceca_32k_clkout.hw,
> > + [CLKID_CECB_32K_CLKIN] = &t7_cecb_32k_clkin.hw,
> > + [CLKID_CECB_32K_DIV] = &t7_cecb_32k_div.hw,
> > + [CLKID_CECB_32K_MUX_PRE] = &t7_cecb_32k_sel_pre.hw,
> > + [CLKID_CECB_32K_MUX] = &t7_cecb_32k_sel.hw,
> > + [CLKID_CECB_32K_CLKOUT] = &t7_cecb_32k_clkout.hw,
> > + [CLKID_SC_CLK_MUX] = &t7_sc_clk_mux.hw,
> > + [CLKID_SC_CLK_DIV] = &t7_sc_clk_div.hw,
> > + [CLKID_SC_CLK_GATE] = &t7_sc_clk_gate.hw,
> > + [CLKID_DSPA_CLK_B_MUX] = &t7_dspa_b_mux.hw,
> > + [CLKID_DSPA_CLK_B_DIV] = &t7_dspa_b_div.hw,
> > + [CLKID_DSPA_CLK_B_GATE] = &t7_dspa_b_gate.hw,
> > + [CLKID_DSPA_CLK_A_MUX] = &t7_dspa_a_mux.hw,
> > + [CLKID_DSPA_CLK_A_DIV] = &t7_dspa_a_div.hw,
> > + [CLKID_DSPA_CLK_A_GATE] = &t7_dspa_a_gate.hw,
> > + [CLKID_DSPA_CLK] = &t7_dspa_mux.hw,
> > + [CLKID_DSPB_CLK_B_MUX] = &t7_dspb_b_mux.hw,
> > + [CLKID_DSPB_CLK_B_DIV] = &t7_dspb_b_div.hw,
> > + [CLKID_DSPB_CLK_B_GATE] = &t7_dspb_b_gate.hw,
> > + [CLKID_DSPB_CLK_A_MUX] = &t7_dspb_a_mux.hw,
> > + [CLKID_DSPB_CLK_A_DIV] = &t7_dspb_a_div.hw,
> > + [CLKID_DSPB_CLK_A_GATE] = &t7_dspb_a_gate.hw,
> > + [CLKID_DSPB_CLK] = &t7_dspb_mux.hw,
> > + [CLKID_24M_CLK_GATE] = &t7_24M_clk_gate.hw,
> > + [CLKID_12M_CLK_DIV] = &t7_12M_clk_div.hw,
> > + [CLKID_12M_CLK_GATE] = &t7_12M_clk_gate.hw,
> > + [CLKID_25M_CLK_DIV] = &t7_25M_clk_div.hw,
> > + [CLKID_25M_CLK_GATE] = &t7_25M_clk_gate.hw,
> > + [CLKID_VID_PLL] = &t7_vid_pll_div.hw,
> > + [CLKID_VID_PLL_MUX] = &t7_vid_pll_sel.hw,
> > + [CLKID_VID_PLL] = &t7_vid_pll.hw,
> > + [CLKID_VCLK_MUX] = &t7_vclk_sel.hw,
> > + [CLKID_VCLK2_MUX] = &t7_vclk2_sel.hw,
> > + [CLKID_VCLK_INPUT] = &t7_vclk_input.hw,
> > + [CLKID_VCLK2_INPUT] = &t7_vclk2_input.hw,
> > + [CLKID_VCLK_DIV] = &t7_vclk_div.hw,
> > + [CLKID_VCLK2_DIV] = &t7_vclk2_div.hw,
> > + [CLKID_VCLK] = &t7_vclk.hw,
> > + [CLKID_VCLK2] = &t7_vclk2.hw,
> > + [CLKID_VCLK_DIV1] = &t7_vclk_div1.hw,
> > + [CLKID_VCLK_DIV2_EN] = &t7_vclk_div2_en.hw,
> > + [CLKID_VCLK_DIV4_EN] = &t7_vclk_div4_en.hw,
> > + [CLKID_VCLK_DIV6_EN] = &t7_vclk_div6_en.hw,
> > + [CLKID_VCLK_DIV12_EN] = &t7_vclk_div12_en.hw,
> > + [CLKID_VCLK2_DIV1] = &t7_vclk2_div1.hw,
> > + [CLKID_VCLK2_DIV2_EN] = &t7_vclk2_div2_en.hw,
> > + [CLKID_VCLK2_DIV4_EN] = &t7_vclk2_div4_en.hw,
> > + [CLKID_VCLK2_DIV6_EN] = &t7_vclk2_div6_en.hw,
> > + [CLKID_VCLK2_DIV12_EN] = &t7_vclk2_div12_en.hw,
> > + [CLKID_VCLK_DIV2] = &t7_vclk_div2.hw,
> > + [CLKID_VCLK_DIV4] = &t7_vclk_div4.hw,
> > + [CLKID_VCLK_DIV6] = &t7_vclk_div6.hw,
> > + [CLKID_VCLK_DIV12] = &t7_vclk_div12.hw,
> > + [CLKID_VCLK2_DIV2] = &t7_vclk2_div2.hw,
> > + [CLKID_VCLK2_DIV4] = &t7_vclk2_div4.hw,
> > + [CLKID_VCLK2_DIV6] = &t7_vclk2_div6.hw,
> > + [CLKID_VCLK2_DIV12] = &t7_vclk2_div12.hw,
> > + [CLKID_CTS_ENCI_MUX] = &t7_cts_enci_sel.hw,
> > + [CLKID_CTS_ENCP_MUX] = &t7_cts_encp_sel.hw,
> > + [CLKID_CTS_VDAC_MUX] = &t7_cts_vdac_sel.hw,
> > + [CLKID_HDMI_TX_MUX] = &t7_hdmi_tx_sel.hw,
> > + [CLKID_CTS_ENCI] = &t7_cts_enci.hw,
> > + [CLKID_CTS_ENCP] = &t7_cts_encp.hw,
> > + [CLKID_CTS_VDAC] = &t7_cts_vdac.hw,
> > + [CLKID_HDMI_TX] = &t7_hdmi_tx.hw,
> > + [CLKID_HDMITX_SYS_MUX] = &t7_hdmitx_sys_sel.hw,
> > + [CLKID_HDMITX_SYS_DIV] = &t7_hdmitx_sys_div.hw,
> > + [CLKID_HDMITX_SYS] = &t7_hdmitx_sys.hw,
> > + [CLKID_HDMITX_PRIF_MUX] = &t7_hdmitx_prif_sel.hw,
> > + [CLKID_HDMITX_PRIF_DIV] = &t7_hdmitx_prif_div.hw,
> > + [CLKID_HDMITX_PRIF] = &t7_hdmitx_prif.hw,
> > + [CLKID_HDMITX_200M_MUX] = &t7_hdmitx_200m_sel.hw,
> > + [CLKID_HDMITX_200M_DIV] = &t7_hdmitx_200m_div.hw,
> > + [CLKID_HDMITX_200M] = &t7_hdmitx_200m.hw,
> > + [CLKID_HDMITX_AUD_MUX] = &t7_hdmitx_aud_sel.hw,
> > + [CLKID_HDMITX_AUD_DIV] = &t7_hdmitx_aud_div.hw,
> > + [CLKID_HDMITX_AUD] = &t7_hdmitx_aud.hw,
> > + [CLKID_HDMIRX_5M_MUX] = &t7_hdmirx_5m_sel.hw,
> > + [CLKID_HDMIRX_5M_DIV] = &t7_hdmirx_5m_div.hw,
> > + [CLKID_HDMIRX_5M] = &t7_hdmirx_5m.hw,
> > + [CLKID_HDMIRX_2M_MUX] = &t7_hdmirx_2m_sel.hw,
> > + [CLKID_HDMIRX_2M_DIV] = &t7_hdmirx_2m_div.hw,
> > + [CLKID_HDMIRX_2M] = &t7_hdmirx_2m.hw,
> > + [CLKID_HDMIRX_CFG_MUX] = &t7_hdmirx_cfg_sel.hw,
> > + [CLKID_HDMIRX_CFG_DIV] = &t7_hdmirx_cfg_div.hw,
> > + [CLKID_HDMIRX_CFG] = &t7_hdmirx_cfg.hw,
> > + [CLKID_HDMIRX_HDCP_MUX] = &t7_hdmirx_hdcp_sel.hw,
> > + [CLKID_HDMIRX_HDCP_DIV] = &t7_hdmirx_hdcp_div.hw,
> > + [CLKID_HDMIRX_HDCP] = &t7_hdmirx_hdcp.hw,
> > + [CLKID_HDMIRX_AUD_PLL_MUX] = &t7_hdmirx_aud_pll_sel.hw,
> > + [CLKID_HDMIRX_AUD_PLL_DIV] = &t7_hdmirx_aud_pll_div.hw,
> > + [CLKID_HDMIRX_AUD_PLL] = &t7_hdmirx_aud_pll.hw,
> > + [CLKID_HDMIRX_ACR_MUX] = &t7_hdmirx_acr_sel.hw,
> > + [CLKID_HDMIRX_ACR_DIV] = &t7_hdmirx_acr_div.hw,
> > + [CLKID_HDMIRX_ACR] = &t7_hdmirx_acr.hw,
> > + [CLKID_HDMIRX_METER_MUX] = &t7_hdmirx_meter_sel.hw,
> > + [CLKID_HDMIRX_METER_DIV] = &t7_hdmirx_meter_div.hw,
> > + [CLKID_HDMIRX_METER] = &t7_hdmirx_meter.hw,
> > + [CLKID_TS_CLK_DIV] = &t7_ts_clk_div.hw,
> > + [CLKID_TS_CLK_GATE] = &t7_ts_clk_gate.hw,
> > + [CLKID_MALI_0_SEL] = &t7_mali_0_sel.hw,
> > + [CLKID_MALI_0_DIV] = &t7_mali_0_div.hw,
> > + [CLKID_MALI_0] = &t7_mali_0.hw,
> > + [CLKID_MALI_1_SEL] = &t7_mali_1_sel.hw,
> > + [CLKID_MALI_1_DIV] = &t7_mali_1_div.hw,
> > + [CLKID_MALI_1] = &t7_mali_1.hw,
> > + [CLKID_MALI_MUX] = &t7_mali_mux.hw,
> > + [CLKID_VDEC_P0_MUX] = &t7_vdec_p0_mux.hw,
> > + [CLKID_VDEC_P0_DIV] = &t7_vdec_p0_div.hw,
> > + [CLKID_VDEC_P0] = &t7_vdec_p0.hw,
> > + [CLKID_VDEC_P1_MUX] = &t7_vdec_p1_mux.hw,
> > + [CLKID_VDEC_P1_DIV] = &t7_vdec_p1_div.hw,
> > + [CLKID_VDEC_P1] = &t7_vdec_p1.hw,
> > + [CLKID_VDEC_MUX] = &t7_vdec_mux.hw,
> > + [CLKID_HCODEC_P0_MUX] = &t7_hcodec_p0_mux.hw,
> > + [CLKID_HCODEC_P0_DIV] = &t7_hcodec_p0_div.hw,
> > + [CLKID_HCODEC_P0] = &t7_hcodec_p0.hw,
> > + [CLKID_HCODEC_P1_MUX] = &t7_hcodec_p1_mux.hw,
> > + [CLKID_HCODEC_P1_DIV] = &t7_hcodec_p1_div.hw,
> > + [CLKID_HCODEC_P1] = &t7_hcodec_p1.hw,
> > + [CLKID_HCODEC_MUX] = &t7_hcodec_mux.hw,
> > + [CLKID_HEVCB_P0_MUX] = &t7_hevcb_p0_mux.hw,
> > + [CLKID_HEVCB_P0_DIV] = &t7_hevcb_p0_div.hw,
> > + [CLKID_HEVCB_P0] = &t7_hevcb_p0.hw,
> > + [CLKID_HEVCB_P1_MUX] = &t7_hevcb_p1_mux.hw,
> > + [CLKID_HEVCB_P1_DIV] = &t7_hevcb_p1_div.hw,
> > + [CLKID_HEVCB_P1] = &t7_hevcb_p1.hw,
> > + [CLKID_HEVCB_MUX] = &t7_hevcb_mux.hw,
> > + [CLKID_HEVCF_P0_MUX] = &t7_hevcf_p0_mux.hw,
> > + [CLKID_HEVCF_P0_DIV] = &t7_hevcf_p0_div.hw,
> > + [CLKID_HEVCF_P0] = &t7_hevcf_p0.hw,
> > + [CLKID_HEVCF_P1_MUX] = &t7_hevcf_p1_mux.hw,
> > + [CLKID_HEVCF_P1_DIV] = &t7_hevcf_p1_div.hw,
> > + [CLKID_HEVCF_P1] = &t7_hevcf_p1.hw,
> > + [CLKID_HEVCF_MUX] = &t7_hevcf_mux.hw,
> > + [CLKID_WAVE_A_MUX] = &t7_wave_a_sel.hw,
> > + [CLKID_WAVE_A_DIV] = &t7_wave_a_div.hw,
> > + [CLKID_WAVE_A_GATE] = &t7_wave_aclk.hw,
> > + [CLKID_WAVE_B_MUX] = &t7_wave_b_sel.hw,
> > + [CLKID_WAVE_B_DIV] = &t7_wave_b_div.hw,
> > + [CLKID_WAVE_B_GATE] = &t7_wave_bclk.hw,
> > + [CLKID_WAVE_C_MUX] = &t7_wave_c_sel.hw,
> > + [CLKID_WAVE_C_DIV] = &t7_wave_c_div.hw,
> > + [CLKID_WAVE_C_GATE] = &t7_wave_cclk.hw,
> > + [CLKID_MIPI_ISP_MUX] = &t7_mipi_isp_sel.hw,
> > + [CLKID_MIPI_ISP_DIV] = &t7_mipi_isp_div.hw,
> > + [CLKID_MIPI_ISP] = &t7_mipi_isp.hw,
> > + [CLKID_MIPI_CSI_PHY_SEL0] = &t7_mipi_csi_phy_sel0.hw,
> > + [CLKID_MIPI_CSI_PHY_DIV0] = &t7_mipi_csi_phy_div0.hw,
> > + [CLKID_MIPI_CSI_PHY0] = &t7_mipi_csi_phy0.hw,
> > + [CLKID_MIPI_CSI_PHY_SEL1] = &t7_mipi_csi_phy_sel1.hw,
> > + [CLKID_MIPI_CSI_PHY_DIV1] = &t7_mipi_csi_phy_div1.hw,
> > + [CLKID_MIPI_CSI_PHY1] = &t7_mipi_csi_phy1.hw,
> > + [CLKID_MIPI_CSI_PHY_CLK] = &t7_mipi_csi_phy_clk.hw,
> > + [CLKID_VPU_0_MUX] = &t7_vpu_0_sel.hw,
> > + [CLKID_VPU_0_DIV] = &t7_vpu_0_div.hw,
> > + [CLKID_VPU_0] = &t7_vpu_0.hw,
> > + [CLKID_VPU_1_MUX] = &t7_vpu_1_sel.hw,
> > + [CLKID_VPU_1_DIV] = &t7_vpu_1_div.hw,
> > + [CLKID_VPU_1] = &t7_vpu_1.hw,
> > + [CLKID_VPU] = &t7_vpu.hw,
> > + [CLKID_VPU_CLKB_TMP_MUX] = &t7_vpu_clkb_tmp_mux.hw,
> > + [CLKID_VPU_CLKB_TMP_DIV] = &t7_vpu_clkb_tmp_div.hw,
> > + [CLKID_VPU_CLKB_TMP] = &t7_vpu_clkb_tmp.hw,
> > + [CLKID_VPU_CLKB_DIV] = &t7_vpu_clkb_div.hw,
> > + [CLKID_VPU_CLKB] = &t7_vpu_clkb.hw,
> > + [CLKID_VPU_CLKC_P0_MUX] = &t7_vpu_clkc_p0_mux.hw,
> > + [CLKID_VPU_CLKC_P0_DIV] = &t7_vpu_clkc_p0_div.hw,
> > + [CLKID_VPU_CLKC_P0] = &t7_vpu_clkc_p0.hw,
> > + [CLKID_VPU_CLKC_P1_MUX] = &t7_vpu_clkc_p1_mux.hw,
> > + [CLKID_VPU_CLKC_P1_DIV] = &t7_vpu_clkc_p1_div.hw,
> > + [CLKID_VPU_CLKC_P1] = &t7_vpu_clkc_p1.hw,
> > + [CLKID_VPU_CLKC_MUX] = &t7_vpu_clkc_mux.hw,
> > + [CLKID_VAPB_0_MUX] = &t7_vapb_0_sel.hw,
> > + [CLKID_VAPB_0_DIV] = &t7_vapb_0_div.hw,
> > + [CLKID_VAPB_0] = &t7_vapb_0.hw,
> > + [CLKID_VAPB_1_MUX] = &t7_vapb_1_sel.hw,
> > + [CLKID_VAPB_1_DIV] = &t7_vapb_1_div.hw,
> > + [CLKID_VAPB_1] = &t7_vapb_1.hw,
> > + [CLKID_VAPB] = &t7_vapb.hw,
> > + [CLKID_GDCCLK_0_MUX] = &t7_gdcclk_0_sel.hw,
> > + [CLKID_GDCCLK_0_DIV] = &t7_gdcclk_0_div.hw,
> > + [CLKID_GDCCLK_0] = &t7_gdcclk_0.hw,
> > + [CLKID_GDCCLK_1_MUX] = &t7_gdcclk_1_sel.hw,
> > + [CLKID_GDCCLK_1_DIV] = &t7_gdcclk_1_div.hw,
> > + [CLKID_GDCCLK_1] = &t7_gdcclk_1.hw,
> > + [CLKID_GDCCLK] = &t7_gdcclk.hw,
> > + [CLKID_GDC_CLK] = &t7_gdc_clk.hw,
> > + [CLKID_DEWARPCLK_0_MUX] = &t7_dewarpclk_0_sel.hw,
> > + [CLKID_DEWARPCLK_0_DIV] = &t7_dewarpclk_0_div.hw,
> > + [CLKID_DEWARPCLK_0] = &t7_dewarpclk_0.hw,
> > + [CLKID_DEWARPCLK_1_MUX] = &t7_dewarpclk_1_sel.hw,
> > + [CLKID_DEWARPCLK_1_DIV] = &t7_dewarpclk_1_div.hw,
> > + [CLKID_DEWARPCLK_1] = &t7_dewarpclk_1.hw,
> > + [CLKID_DEWARPCLK] = &t7_dewarpclk.hw,
> > + [CLKID_DEWARP_CLK] = &t7_dewarp_clk.hw,
> > + [CLKID_ANAKIN_0_MUX] = &t7_anakin_0_sel.hw,
> > + [CLKID_ANAKIN_0_DIV] = &t7_anakin_0_div.hw,
> > + [CLKID_ANAKIN_0] = &t7_anakin_0.hw,
> > + [CLKID_ANAKIN_1_MUX] = &t7_anakin_1_sel.hw,
> > + [CLKID_ANAKIN_1_DIV] = &t7_anakin_1_div.hw,
> > + [CLKID_ANAKIN_1] = &t7_anakin_1.hw,
> > + [CLKID_ANAKIN] = &t7_anakin.hw,
> > + [CLKID_ANAKIN_CLK] = &t7_anakin_clk.hw,
> > + [CLKID_GE2D] = &t7_ge2d_gate.hw,
> > + [CLKID_VDIN_MEAS_MUX] = &t7_vdin_meas_mux.hw,
> > + [CLKID_VDIN_MEAS_DIV] = &t7_vdin_meas_div.hw,
> > + [CLKID_VDIN_MEAS_GATE] = &t7_vdin_meas_gate.hw,
> > + [CLKID_VID_LOCK_DIV] = &t7_vid_lock_div.hw,
> > + [CLKID_VID_LOCK] = &t7_vid_lock_clk.hw,
> > + [CLKID_PWM_A_MUX] = &t7_pwm_a_mux.hw,
> > + [CLKID_PWM_A_DIV] = &t7_pwm_a_div.hw,
> > + [CLKID_PWM_A_GATE] = &t7_pwm_a_gate.hw,
> > + [CLKID_PWM_B_MUX] = &t7_pwm_b_mux.hw,
> > + [CLKID_PWM_B_DIV] = &t7_pwm_b_div.hw,
> > + [CLKID_PWM_B_GATE] = &t7_pwm_b_gate.hw,
> > + [CLKID_PWM_C_MUX] = &t7_pwm_c_mux.hw,
> > + [CLKID_PWM_C_DIV] = &t7_pwm_c_div.hw,
> > + [CLKID_PWM_C_GATE] = &t7_pwm_c_gate.hw,
> > + [CLKID_PWM_D_MUX] = &t7_pwm_d_mux.hw,
> > + [CLKID_PWM_D_DIV] = &t7_pwm_d_div.hw,
> > + [CLKID_PWM_D_GATE] = &t7_pwm_d_gate.hw,
> > + [CLKID_PWM_E_MUX] = &t7_pwm_e_mux.hw,
> > + [CLKID_PWM_E_DIV] = &t7_pwm_e_div.hw,
> > + [CLKID_PWM_E_GATE] = &t7_pwm_e_gate.hw,
> > + [CLKID_PWM_F_MUX] = &t7_pwm_f_mux.hw,
> > + [CLKID_PWM_F_DIV] = &t7_pwm_f_div.hw,
> > + [CLKID_PWM_F_GATE] = &t7_pwm_f_gate.hw,
> > + [CLKID_PWM_AO_A_MUX] = &t7_pwm_ao_a_mux.hw,
> > + [CLKID_PWM_AO_A_DIV] = &t7_pwm_ao_a_div.hw,
> > + [CLKID_PWM_AO_A_GATE] = &t7_pwm_ao_a_gate.hw,
> > + [CLKID_PWM_AO_B_MUX] = &t7_pwm_ao_b_mux.hw,
> > + [CLKID_PWM_AO_B_DIV] = &t7_pwm_ao_b_div.hw,
> > + [CLKID_PWM_AO_B_GATE] = &t7_pwm_ao_b_gate.hw,
> > + [CLKID_PWM_AO_C_MUX] = &t7_pwm_ao_c_mux.hw,
> > + [CLKID_PWM_AO_C_DIV] = &t7_pwm_ao_c_div.hw,
> > + [CLKID_PWM_AO_C_GATE] = &t7_pwm_ao_c_gate.hw,
> > + [CLKID_PWM_AO_D_MUX] = &t7_pwm_ao_d_mux.hw,
> > + [CLKID_PWM_AO_D_DIV] = &t7_pwm_ao_d_div.hw,
> > + [CLKID_PWM_AO_D_GATE] = &t7_pwm_ao_d_gate.hw,
> > + [CLKID_PWM_AO_E_MUX] = &t7_pwm_ao_e_mux.hw,
> > + [CLKID_PWM_AO_E_DIV] = &t7_pwm_ao_e_div.hw,
> > + [CLKID_PWM_AO_E_GATE] = &t7_pwm_ao_e_gate.hw,
> > + [CLKID_PWM_AO_F_MUX] = &t7_pwm_ao_f_mux.hw,
> > + [CLKID_PWM_AO_F_DIV] = &t7_pwm_ao_f_div.hw,
> > + [CLKID_PWM_AO_F_GATE] = &t7_pwm_ao_f_gate.hw,
> > + [CLKID_PWM_AO_G_MUX] = &t7_pwm_ao_g_mux.hw,
> > + [CLKID_PWM_AO_G_DIV] = &t7_pwm_ao_g_div.hw,
> > + [CLKID_PWM_AO_G_GATE] = &t7_pwm_ao_g_gate.hw,
> > + [CLKID_PWM_AO_H_MUX] = &t7_pwm_ao_h_mux.hw,
> > + [CLKID_PWM_AO_H_DIV] = &t7_pwm_ao_h_div.hw,
> > + [CLKID_PWM_AO_H_GATE] = &t7_pwm_ao_h_gate.hw,
> > + [CLKID_SPICC0_MUX] = &t7_spicc0_mux.hw,
> > + [CLKID_SPICC0_DIV] = &t7_spicc0_div.hw,
> > + [CLKID_SPICC0_GATE] = &t7_spicc0_gate.hw,
> > + [CLKID_SPICC1_MUX] = &t7_spicc1_mux.hw,
> > + [CLKID_SPICC1_DIV] = &t7_spicc1_div.hw,
> > + [CLKID_SPICC1_GATE] = &t7_spicc1_gate.hw,
> > + [CLKID_SPICC2_MUX] = &t7_spicc2_mux.hw,
> > + [CLKID_SPICC2_DIV] = &t7_spicc2_div.hw,
> > + [CLKID_SPICC2_GATE] = &t7_spicc2_gate.hw,
> > + [CLKID_SPICC3_MUX] = &t7_spicc3_mux.hw,
> > + [CLKID_SPICC3_DIV] = &t7_spicc3_div.hw,
> > + [CLKID_SPICC3_GATE] = &t7_spicc3_gate.hw,
> > + [CLKID_SPICC4_MUX] = &t7_spicc4_mux.hw,
> > + [CLKID_SPICC4_DIV] = &t7_spicc4_div.hw,
> > + [CLKID_SPICC4_GATE] = &t7_spicc4_gate.hw,
> > + [CLKID_SPICC5_MUX] = &t7_spicc5_mux.hw,
> > + [CLKID_SPICC5_DIV] = &t7_spicc5_div.hw,
> > + [CLKID_SPICC5_GATE] = &t7_spicc5_gate.hw,
> > + [CLKID_SD_EMMC_C_CLK_MUX] = &t7_sd_emmc_c_clk0_sel.hw,
> > + [CLKID_SD_EMMC_C_CLK_DIV] = &t7_sd_emmc_c_clk0_div.hw,
> > + [CLKID_SD_EMMC_C_CLK] = &t7_sd_emmc_c_clk0.hw,
> > + [CLKID_SD_EMMC_A_CLK_MUX] = &t7_sd_emmc_a_clk0_sel.hw,
> > + [CLKID_SD_EMMC_A_CLK_DIV] = &t7_sd_emmc_a_clk0_div.hw,
> > + [CLKID_SD_EMMC_A_CLK] = &t7_sd_emmc_a_clk0.hw,
> > + [CLKID_SD_EMMC_B_CLK_MUX] = &t7_sd_emmc_b_clk0_sel.hw,
> > + [CLKID_SD_EMMC_B_CLK_DIV] = &t7_sd_emmc_b_clk0_div.hw,
> > + [CLKID_SD_EMMC_B_CLK] = &t7_sd_emmc_b_clk0.hw,
> > + [CLKID_DSI_A_MEAS_MUX] = &t7_dsi_a_meas_mux.hw,
> > + [CLKID_DSI_A_MEAS_DIV] = &t7_dsi_a_meas_div.hw,
> > + [CLKID_DSI_A_MEAS_GATE] = &t7_dsi_a_meas_gate.hw,
> > + [CLKID_DSI_B_MEAS_MUX] = &t7_dsi_b_meas_mux.hw,
> > + [CLKID_DSI_B_MEAS_DIV] = &t7_dsi_b_meas_div.hw,
> > + [CLKID_DSI_B_MEAS_GATE] = &t7_dsi_b_meas_gate.hw,
> > + [CLKID_DSI0_PHY_MUX] = &t7_dsi0_phy_mux.hw,
> > + [CLKID_DSI0_PHY_DIV] = &t7_dsi0_phy_div.hw,
> > + [CLKID_DSI0_PHY_GATE] = &t7_dsi0_phy_gate.hw,
> > + [CLKID_DSI1_PHY_MUX] = &t7_dsi1_phy_mux.hw,
> > + [CLKID_DSI1_PHY_DIV] = &t7_dsi1_phy_div.hw,
> > + [CLKID_DSI1_PHY_GATE] = &t7_dsi1_phy_gate.hw,
> > + [CLKID_ETH_RMII_SEL] = &t7_eth_rmii_sel.hw,
> > + [CLKID_ETH_RMII_DIV] = &t7_eth_rmii_div.hw,
> > + [CLKID_ETH_RMII] = &t7_eth_rmii.hw,
> > + [CLKID_ETH_DIV8] = &t7_eth_div8.hw,
> > + [CLKID_ETH_125M] = &t7_eth_125m.hw,
> > + [CLKID_SARADC_MUX] = &t7_saradc_mux.hw,
> > + [CLKID_SARADC_DIV] = &t7_saradc_div.hw,
> > + [CLKID_SARADC_GATE] = &t7_saradc_gate.hw,
> > + [CLKID_GEN_MUX] = &t7_gen_sel.hw,
> > + [CLKID_GEN_DIV] = &t7_gen_div.hw,
> > + [CLKID_GEN_GATE] = &t7_gen.hw,
> > + [CLKID_DDR] = &t7_ddr.hw,
> > + [CLKID_DOS] = &t7_dos.hw,
> > + [CLKID_MIPI_DSI_A] = &t7_mipi_dsi_a.hw,
> > + [CLKID_MIPI_DSI_B] = &t7_mipi_dsi_b.hw,
> > + [CLKID_ETHPHY] = &t7_ethphy.hw,
> > + [CLKID_MALI] = &t7_mali.hw,
> > + [CLKID_AOCPU] = &t7_aocpu.hw,
> > + [CLKID_AUCPU] = &t7_aucpu.hw,
> > + [CLKID_CEC] = &t7_cec.hw,
> > + [CLKID_GDC] = &t7_gdc.hw,
> > + [CLKID_DESWARP] = &t7_deswarp.hw,
> > + [CLKID_AMPIPE_NAND] = &t7_ampipe_nand.hw,
> > + [CLKID_AMPIPE_ETH] = &t7_ampipe_eth.hw,
> > + [CLKID_AM2AXI0] = &t7_am2axi0.hw,
> > + [CLKID_AM2AXI1] = &t7_am2axi1.hw,
> > + [CLKID_AM2AXI2] = &t7_am2axi2.hw,
> > + [CLKID_SD_EMMC_A] = &t7_sdemmca.hw,
> > + [CLKID_SD_EMMC_B] = &t7_sdemmcb.hw,
> > + [CLKID_SD_EMMC_C] = &t7_sdemmcc.hw,
> > + [CLKID_SMARTCARD] = &t7_smartcard.hw,
> > + [CLKID_ACODEC] = &t7_acodec.hw,
> > + [CLKID_SPIFC] = &t7_spifc.hw,
> > + [CLKID_MSR_CLK] = &t7_msr_clk.hw,
> > + [CLKID_IR_CTRL] = &t7_ir_ctrl.hw,
> > + [CLKID_AUDIO] = &t7_audio.hw,
> > + [CLKID_ETH] = &t7_eth.hw,
> > + [CLKID_UART_A] = &t7_uart_a.hw,
> > + [CLKID_UART_B] = &t7_uart_b.hw,
> > + [CLKID_UART_C] = &t7_uart_c.hw,
> > + [CLKID_UART_D] = &t7_uart_d.hw,
> > + [CLKID_UART_E] = &t7_uart_e.hw,
> > + [CLKID_UART_F] = &t7_uart_f.hw,
> > + [CLKID_AIFIFO] = &t7_aififo.hw,
> > + [CLKID_SPICC2] = &t7_spicc2.hw,
> > + [CLKID_SPICC3] = &t7_spicc3.hw,
> > + [CLKID_SPICC4] = &t7_spicc4.hw,
> > + [CLKID_TS_A73] = &t7_ts_a73.hw,
> > + [CLKID_TS_A53] = &t7_ts_a53.hw,
> > + [CLKID_SPICC5] = &t7_spicc5.hw,
> > + [CLKID_G2D] = &t7_g2d.hw,
> > + [CLKID_SPICC0] = &t7_spicc0.hw,
> > + [CLKID_SPICC1] = &t7_spicc1.hw,
> > + [CLKID_PCIE] = &t7_pcie.hw,
> > + [CLKID_USB] = &t7_usb.hw,
> > + [CLKID_PCIE_PHY] = &t7_pcie_phy.hw,
> > + [CLKID_I2C_AO_A] = &t7_i2c_ao_a.hw,
> > + [CLKID_I2C_AO_B] = &t7_i2c_ao_b.hw,
> > + [CLKID_I2C_M_A] = &t7_i2c_m_a.hw,
> > + [CLKID_I2C_M_B] = &t7_i2c_m_b.hw,
> > + [CLKID_I2C_M_C] = &t7_i2c_m_c.hw,
> > + [CLKID_I2C_M_D] = &t7_i2c_m_d.hw,
> > + [CLKID_I2C_M_E] = &t7_i2c_m_e.hw,
> > + [CLKID_I2C_M_F] = &t7_i2c_m_f.hw,
> > + [CLKID_HDMITX_APB] = &t7_hdmitx_apb.hw,
> > + [CLKID_I2C_S_A] = &t7_i2c_s_a.hw,
> > + [CLKID_HDMIRX_PCLK] = &t7_hdmirx_pclk.hw,
> > + [CLKID_MMC_APB] = &t7_mmc_apb.hw,
> > + [CLKID_MIPI_ISP_PCLK] = &t7_mipi_isp_pclk.hw,
> > + [CLKID_RSA] = &t7_rsa.hw,
> > + [CLKID_PCLK_SYS_CPU_APB] = &t7_pclk_sys_cpu_apb.hw,
> > + [CLKID_A73PCLK_CPU_APB] = &t7_a73pclk_cpu_apb.hw,
> > + [CLKID_DSPA] = &t7_dspa.hw,
> > + [CLKID_DSPB] = &t7_dspb.hw,
> > + [CLKID_VPU_INTR] = &t7_vpu_intr.hw,
> > + [CLKID_SAR_ADC] = &t7_sar_adc.hw,
> > + [CLKID_GIC] = &t7_gic.hw,
> > + [CLKID_TS_GPU] = &t7_ts_gpu.hw,
> > + [CLKID_TS_NNA] = &t7_ts_nna.hw,
> > + [CLKID_TS_VPU] = &t7_ts_vpu.hw,
> > + [CLKID_TS_HEVC] = &t7_ts_hevc.hw,
> > + [CLKID_PWM_AB] = &t7_pwm_ab.hw,
> > + [CLKID_PWM_CD] = &t7_pwm_cd.hw,
> > + [CLKID_PWM_EF] = &t7_pwm_ef.hw,
> > + [CLKID_PWM_AO_AB] = &t7_pwm_ao_ab.hw,
> > + [CLKID_PWM_AO_CD] = &t7_pwm_ao_cd.hw,
> > + [CLKID_PWM_AO_EF] = &t7_pwm_ao_ef.hw,
> > + [CLKID_PWM_AO_GH] = &t7_pwm_ao_gh.hw,
> > +};
> > +
> > +/* Convenience table to populate regmap in .probe */
> > +static struct clk_regmap *const t7_clk_regmaps[] = {
> > + &t7_rtc_32k_clkin,
> > + &t7_rtc_32k_div,
> > + &t7_rtc_32k_xtal,
> > + &t7_rtc_32k_sel,
> > + &t7_rtc_clk,
> > + &t7_sysclk_b_sel,
> > + &t7_sysclk_b_div,
> > + &t7_sysclk_b,
> > + &t7_sysclk_a_sel,
> > + &t7_sysclk_a_div,
> > + &t7_sysclk_a,
> > + &t7_sys_clk,
> > + &t7_ceca_32k_clkin,
> > + &t7_ceca_32k_div,
> > + &t7_ceca_32k_sel_pre,
> > + &t7_ceca_32k_sel,
> > + &t7_ceca_32k_clkout,
> > + &t7_cecb_32k_clkin,
> > + &t7_cecb_32k_div,
> > + &t7_cecb_32k_sel_pre,
> > + &t7_cecb_32k_sel,
> > + &t7_cecb_32k_clkout,
> > + &t7_sc_clk_mux,
> > + &t7_sc_clk_div,
> > + &t7_sc_clk_gate,
> > + &t7_dspa_a_mux,
> > + &t7_dspa_a_div,
> > + &t7_dspa_a_gate,
> > + &t7_dspa_b_mux,
> > + &t7_dspa_b_div,
> > + &t7_dspa_b_gate,
> > + &t7_dspa_mux,
> > + &t7_dspb_a_mux,
> > + &t7_dspb_a_div,
> > + &t7_dspb_a_gate,
> > + &t7_dspb_b_mux,
> > + &t7_dspb_b_div,
> > + &t7_dspb_b_gate,
> > + &t7_dspb_mux,
> > + &t7_24M_clk_gate,
> > + &t7_12M_clk_gate,
> > + &t7_25M_clk_div,
> > + &t7_25M_clk_gate,
> > + &t7_vid_pll_div,
> > + &t7_vid_pll_sel,
> > + &t7_vid_pll,
> > + &t7_vclk_sel,
> > + &t7_vclk2_sel,
> > + &t7_vclk_input,
> > + &t7_vclk2_input,
> > + &t7_vclk_div,
> > + &t7_vclk2_div,
> > + &t7_vclk,
> > + &t7_vclk2,
> > + &t7_vclk_div1,
> > + &t7_vclk_div2_en,
> > + &t7_vclk_div4_en,
> > + &t7_vclk_div6_en,
> > + &t7_vclk_div12_en,
> > + &t7_vclk2_div1,
> > + &t7_vclk2_div2_en,
> > + &t7_vclk2_div4_en,
> > + &t7_vclk2_div6_en,
> > + &t7_vclk2_div12_en,
> > + &t7_cts_enci_sel,
> > + &t7_cts_encp_sel,
> > + &t7_cts_vdac_sel,
> > + &t7_hdmi_tx_sel,
> > + &t7_cts_enci,
> > + &t7_cts_encp,
> > + &t7_cts_vdac,
> > + &t7_hdmi_tx,
> > + &t7_hdmitx_sys_sel,
> > + &t7_hdmitx_sys_div,
> > + &t7_hdmitx_sys,
> > + &t7_hdmitx_prif_sel,
> > + &t7_hdmitx_prif_div,
> > + &t7_hdmitx_prif,
> > + &t7_hdmitx_200m_sel,
> > + &t7_hdmitx_200m_div,
> > + &t7_hdmitx_200m,
> > + &t7_hdmitx_aud_sel,
> > + &t7_hdmitx_aud_div,
> > + &t7_hdmitx_aud,
> > + &t7_hdmirx_5m_sel,
> > + &t7_hdmirx_5m_div,
> > + &t7_hdmirx_5m,
> > + &t7_hdmirx_2m_sel,
> > + &t7_hdmirx_2m_div,
> > + &t7_hdmirx_2m,
> > + &t7_hdmirx_cfg_sel,
> > + &t7_hdmirx_cfg_div,
> > + &t7_hdmirx_cfg,
> > + &t7_hdmirx_hdcp_sel,
> > + &t7_hdmirx_hdcp_div,
> > + &t7_hdmirx_hdcp,
> > + &t7_hdmirx_aud_pll_sel,
> > + &t7_hdmirx_aud_pll_div,
> > + &t7_hdmirx_aud_pll,
> > + &t7_hdmirx_acr_sel,
> > + &t7_hdmirx_acr_div,
> > + &t7_hdmirx_acr,
> > + &t7_hdmirx_meter_sel,
> > + &t7_hdmirx_meter_div,
> > + &t7_hdmirx_meter,
> > + &t7_ts_clk_div,
> > + &t7_ts_clk_gate,
> > + &t7_mali_0_sel,
> > + &t7_mali_0_div,
> > + &t7_mali_0,
> > + &t7_mali_1_sel,
> > + &t7_mali_1_div,
> > + &t7_mali_1,
> > + &t7_mali_mux,
> > + &t7_vdec_p0_mux,
> > + &t7_vdec_p0_div,
> > + &t7_vdec_p0,
> > + &t7_vdec_p1_mux,
> > + &t7_vdec_p1_div,
> > + &t7_vdec_p1,
> > + &t7_vdec_mux,
> > + &t7_hcodec_p0_mux,
> > + &t7_hcodec_p0_div,
> > + &t7_hcodec_p0,
> > + &t7_hcodec_p1_mux,
> > + &t7_hcodec_p1_div,
> > + &t7_hcodec_p1,
> > + &t7_hcodec_mux,
> > + &t7_hevcb_p0_mux,
> > + &t7_hevcb_p0_div,
> > + &t7_hevcb_p0,
> > + &t7_hevcb_p1_mux,
> > + &t7_hevcb_p1_div,
> > + &t7_hevcb_p1,
> > + &t7_hevcb_mux,
> > + &t7_hevcf_p0_mux,
> > + &t7_hevcf_p0_div,
> > + &t7_hevcf_p0,
> > + &t7_hevcf_p1_mux,
> > + &t7_hevcf_p1_div,
> > + &t7_hevcf_p1,
> > + &t7_hevcf_mux,
> > + &t7_wave_a_sel,
> > + &t7_wave_a_div,
> > + &t7_wave_aclk,
> > + &t7_wave_b_sel,
> > + &t7_wave_b_div,
> > + &t7_wave_bclk,
> > + &t7_wave_c_sel,
> > + &t7_wave_c_div,
> > + &t7_wave_cclk,
> > + &t7_mipi_isp_sel,
> > + &t7_mipi_isp_div,
> > + &t7_mipi_isp,
> > + &t7_mipi_csi_phy_sel0,
> > + &t7_mipi_csi_phy_div0,
> > + &t7_mipi_csi_phy0,
> > + &t7_mipi_csi_phy_sel1,
> > + &t7_mipi_csi_phy_div1,
> > + &t7_mipi_csi_phy1,
> > + &t7_mipi_csi_phy_clk,
> > + &t7_vpu_0_sel,
> > + &t7_vpu_0_div,
> > + &t7_vpu_0,
> > + &t7_vpu_1_sel,
> > + &t7_vpu_1_div,
> > + &t7_vpu_1,
> > + &t7_vpu,
> > + &t7_vpu_clkb_tmp_mux,
> > + &t7_vpu_clkb_tmp_div,
> > + &t7_vpu_clkb_tmp,
> > + &t7_vpu_clkb_div,
> > + &t7_vpu_clkb,
> > + &t7_vpu_clkc_p0_mux,
> > + &t7_vpu_clkc_p0_div,
> > + &t7_vpu_clkc_p0,
> > + &t7_vpu_clkc_p1_mux,
> > + &t7_vpu_clkc_p1_div,
> > + &t7_vpu_clkc_p1,
> > + &t7_vpu_clkc_mux,
> > + &t7_vapb_0_sel,
> > + &t7_vapb_0_div,
> > + &t7_vapb_0,
> > + &t7_vapb_1_sel,
> > + &t7_vapb_1_div,
> > + &t7_vapb_1,
> > + &t7_vapb,
> > + &t7_gdcclk_0_sel,
> > + &t7_gdcclk_0_div,
> > + &t7_gdcclk_0,
> > + &t7_gdcclk_1_sel,
> > + &t7_gdcclk_1_div,
> > + &t7_gdcclk_1,
> > + &t7_gdcclk,
> > + &t7_gdc_clk,
> > + &t7_dewarpclk_0_sel,
> > + &t7_dewarpclk_0_div,
> > + &t7_dewarpclk_0,
> > + &t7_dewarpclk_1_sel,
> > + &t7_dewarpclk_1_div,
> > + &t7_dewarpclk_1,
> > + &t7_dewarpclk,
> > + &t7_dewarp_clk,
> > + &t7_anakin_0_sel,
> > + &t7_anakin_0_div,
> > + &t7_anakin_0,
> > + &t7_anakin_1_sel,
> > + &t7_anakin_1_div,
> > + &t7_anakin_1,
> > + &t7_anakin,
> > + &t7_anakin_clk,
> > + &t7_ge2d_gate,
> > + &t7_vdin_meas_mux,
> > + &t7_vdin_meas_div,
> > + &t7_vdin_meas_gate,
> > + &t7_vid_lock_div,
> > + &t7_vid_lock_clk,
> > + &t7_pwm_a_mux,
> > + &t7_pwm_a_div,
> > + &t7_pwm_a_gate,
> > + &t7_pwm_b_mux,
> > + &t7_pwm_b_div,
> > + &t7_pwm_b_gate,
> > + &t7_pwm_c_mux,
> > + &t7_pwm_c_div,
> > + &t7_pwm_c_gate,
> > + &t7_pwm_d_mux,
> > + &t7_pwm_d_div,
> > + &t7_pwm_d_gate,
> > + &t7_pwm_e_mux,
> > + &t7_pwm_e_div,
> > + &t7_pwm_e_gate,
> > + &t7_pwm_f_mux,
> > + &t7_pwm_f_div,
> > + &t7_pwm_f_gate,
> > + &t7_pwm_ao_a_mux,
> > + &t7_pwm_ao_a_div,
> > + &t7_pwm_ao_a_gate,
> > + &t7_pwm_ao_b_mux,
> > + &t7_pwm_ao_b_div,
> > + &t7_pwm_ao_b_gate,
> > + &t7_pwm_ao_c_mux,
> > + &t7_pwm_ao_c_div,
> > + &t7_pwm_ao_c_gate,
> > + &t7_pwm_ao_d_mux,
> > + &t7_pwm_ao_d_div,
> > + &t7_pwm_ao_d_gate,
> > + &t7_pwm_ao_e_mux,
> > + &t7_pwm_ao_e_div,
> > + &t7_pwm_ao_e_gate,
> > + &t7_pwm_ao_f_mux,
> > + &t7_pwm_ao_f_div,
> > + &t7_pwm_ao_f_gate,
> > + &t7_pwm_ao_g_mux,
> > + &t7_pwm_ao_g_div,
> > + &t7_pwm_ao_g_gate,
> > + &t7_pwm_ao_h_mux,
> > + &t7_pwm_ao_h_div,
> > + &t7_pwm_ao_h_gate,
> > + &t7_spicc0_mux,
> > + &t7_spicc0_div,
> > + &t7_spicc0_gate,
> > + &t7_spicc1_mux,
> > + &t7_spicc1_div,
> > + &t7_spicc1_gate,
> > + &t7_spicc2_mux,
> > + &t7_spicc2_div,
> > + &t7_spicc2_gate,
> > + &t7_spicc3_mux,
> > + &t7_spicc3_div,
> > + &t7_spicc3_gate,
> > + &t7_spicc4_mux,
> > + &t7_spicc4_div,
> > + &t7_spicc4_gate,
> > + &t7_spicc5_mux,
> > + &t7_spicc5_div,
> > + &t7_spicc5_gate,
> > + &t7_sd_emmc_c_clk0_sel,
> > + &t7_sd_emmc_c_clk0_div,
> > + &t7_sd_emmc_c_clk0,
> > + &t7_sd_emmc_a_clk0_sel,
> > + &t7_sd_emmc_a_clk0_div,
> > + &t7_sd_emmc_a_clk0,
> > + &t7_sd_emmc_b_clk0_sel,
> > + &t7_sd_emmc_b_clk0_div,
> > + &t7_sd_emmc_b_clk0,
> > + &t7_eth_rmii_sel,
> > + &t7_eth_rmii_div,
> > + &t7_eth_rmii,
> > + &t7_eth_125m,
> > + &t7_dsi_a_meas_mux,
> > + &t7_dsi_a_meas_div,
> > + &t7_dsi_a_meas_gate,
> > + &t7_dsi_b_meas_mux,
> > + &t7_dsi_b_meas_div,
> > + &t7_dsi_b_meas_gate,
> > + &t7_dsi0_phy_mux,
> > + &t7_dsi0_phy_div,
> > + &t7_dsi0_phy_gate,
> > + &t7_dsi1_phy_mux,
> > + &t7_dsi1_phy_div,
> > + &t7_dsi1_phy_gate,
> > + &t7_saradc_mux,
> > + &t7_saradc_div,
> > + &t7_saradc_gate,
> > + &t7_gen_sel,
> > + &t7_gen_div,
> > + &t7_gen,
> > +
> > + &t7_ddr,
> > + &t7_dos,
> > + &t7_mipi_dsi_a,
> > + &t7_mipi_dsi_b,
> > + &t7_ethphy,
> > + &t7_mali,
> > + &t7_aocpu,
> > + &t7_aucpu,
> > + &t7_cec,
> > + &t7_gdc,
> > + &t7_deswarp,
> > + &t7_ampipe_nand,
> > + &t7_ampipe_eth,
> > + &t7_am2axi0,
> > + &t7_am2axi1,
> > + &t7_am2axi2,
> > + &t7_sdemmca,
> > + &t7_sdemmcb,
> > + &t7_sdemmcc,
> > + &t7_smartcard,
> > + &t7_acodec,
> > + &t7_spifc,
> > + &t7_msr_clk,
> > + &t7_ir_ctrl,
> > + &t7_audio,
> > + &t7_eth,
> > + &t7_uart_a,
> > + &t7_uart_b,
> > + &t7_uart_c,
> > + &t7_uart_d,
> > + &t7_uart_e,
> > + &t7_uart_f,
> > + &t7_aififo,
> > + &t7_spicc2,
> > + &t7_spicc3,
> > + &t7_spicc4,
> > + &t7_ts_a73,
> > + &t7_ts_a53,
> > + &t7_spicc5,
> > + &t7_g2d,
> > + &t7_spicc0,
> > + &t7_spicc1,
> > + &t7_pcie,
> > + &t7_usb,
> > + &t7_pcie_phy,
> > + &t7_i2c_ao_a,
> > + &t7_i2c_ao_b,
> > + &t7_i2c_m_a,
> > + &t7_i2c_m_b,
> > + &t7_i2c_m_c,
> > + &t7_i2c_m_d,
> > + &t7_i2c_m_e,
> > + &t7_i2c_m_f,
> > + &t7_hdmitx_apb,
> > + &t7_i2c_s_a,
> > + &t7_hdmirx_pclk,
> > + &t7_mmc_apb,
> > + &t7_mipi_isp_pclk,
> > + &t7_rsa,
> > + &t7_pclk_sys_cpu_apb,
> > + &t7_a73pclk_cpu_apb,
> > + &t7_dspa,
> > + &t7_dspb,
> > + &t7_vpu_intr,
> > + &t7_sar_adc,
> > + &t7_gic,
> > + &t7_ts_gpu,
> > + &t7_ts_nna,
> > + &t7_ts_vpu,
> > + &t7_ts_hevc,
> > + &t7_pwm_ab,
> > + &t7_pwm_cd,
> > + &t7_pwm_ef,
> > + &t7_pwm_ao_ab,
> > + &t7_pwm_ao_cd,
> > + &t7_pwm_ao_ef,
> > + &t7_pwm_ao_gh,
> > +};
> > +
> > +static struct regmap_config clkc_regmap_config = {
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
> > +};
> > +
> > +static struct meson_clk_hw_data t7_periphs_clks = {
> > + .hws = t7_periphs_hw_clks,
> > + .num = ARRAY_SIZE(t7_periphs_hw_clks),
> > +};
> > +
> > +static int amlogic_a1_periphs_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct regmap *regmap;
> > + void __iomem *base;
> > + int ret, i;
> > +
> > + base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(base))
> > + return dev_err_probe(dev, PTR_ERR(base), "can't ioremap resource\n");
> > +
> > + regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
> > + if (IS_ERR(regmap))
> > + return dev_err_probe(dev, PTR_ERR(regmap), "can't init regmap mmio region\n");
> > +
> > + /* Populate regmap for the regmap backed clocks */
> > + for (i = 0; i < ARRAY_SIZE(t7_clk_regmaps); i++)
> > + t7_clk_regmaps[i]->map = regmap;
> > +
> > + for (i = 0; i < t7_periphs_clks.num; i++) {
> > + /* array might be sparse */
> > + if (!t7_periphs_clks.hws[i])
> > + continue;
> > +
> > + ret = devm_clk_hw_register(dev, t7_periphs_clks.hws[i]);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "clock[%d] registration failed\n", i);
> > + }
> > +
> > + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &t7_periphs_clks);
> > +}
> > +
> > +static const struct of_device_id t7_periphs_clkc_match_table[] = {
> > + { .compatible = "amlogic,t7-peripherals-clkc", },
> > + {}
> > +};
> > +MODULE_DEVICE_TABLE(of, t7_periphs_clkc_match_table);
> > +
> > +static struct platform_driver t7_periphs_clkc_driver = {
> > + .probe = amlogic_a1_periphs_probe,
> > + .driver = {
> > + .name = "t7-periphs-clkc",
> > + .of_match_table = t7_periphs_clkc_match_table,
> > + },
> > +};
> > +
> > +module_platform_driver(t7_periphs_clkc_driver);
> > +MODULE_AUTHOR("Yu Tu <yu.tu@amlogic.com>");
> > +MODULE_AUTHOR("Lucas Tanure <tanure@linux.com>");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/clk/meson/t7-peripherals.h b/drivers/clk/meson/t7-peripherals.h
> > new file mode 100644
> > index 000000000000..0ac5e0919b5e
> > --- /dev/null
> > +++ b/drivers/clk/meson/t7-peripherals.h
> > @@ -0,0 +1,131 @@
> > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> > +/*
> > + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> > + */
> > +
> > +#ifndef __T7_PERIPHERALS_H
> > +#define __T7_PERIPHERALS_H
> > +
> > +/* basic clk: 0xfe000000 */
> > +#define CLKCTRL_OSCIN_CTRL (0x0001 << 2)
> > +#define CLKCTRL_RTC_BY_OSCIN_CTRL0 (0x0002 << 2)
> > +#define CLKCTRL_RTC_BY_OSCIN_CTRL1 (0x0003 << 2)
> > +#define CLKCTRL_RTC_CTRL (0x0004 << 2)
> > +#define CLKCTRL_CHECK_CLK_RESULT (0x0005 << 2)
> > +#define CLKCTRL_MBIST_ATSPEED_CTRL (0x0006 << 2)
> > +#define CLKCTRL_LOCK_BIT_REG0 (0x0008 << 2)
> > +#define CLKCTRL_LOCK_BIT_REG1 (0x0009 << 2)
> > +#define CLKCTRL_LOCK_BIT_REG2 (0x000a << 2)
> > +#define CLKCTRL_LOCK_BIT_REG3 (0x000b << 2)
> > +#define CLKCTRL_PROT_BIT_REG0 (0x000c << 2)
> > +#define CLKCTRL_PROT_BIT_REG1 (0x000d << 2)
> > +#define CLKCTRL_PROT_BIT_REG2 (0x000e << 2)
> > +#define CLKCTRL_PROT_BIT_REG3 (0x000f << 2)
> > +#define CLKCTRL_SYS_CLK_CTRL0 (0x0010 << 2)
> > +#define CLKCTRL_SYS_CLK_EN0_REG0 (0x0011 << 2)
> > +#define CLKCTRL_SYS_CLK_EN0_REG1 (0x0012 << 2)
> > +#define CLKCTRL_SYS_CLK_EN0_REG2 (0x0013 << 2)
> > +#define CLKCTRL_SYS_CLK_EN0_REG3 (0x0014 << 2)
> > +#define CLKCTRL_SYS_CLK_EN1_REG0 (0x0015 << 2)
> > +#define CLKCTRL_SYS_CLK_EN1_REG1 (0x0016 << 2)
> > +#define CLKCTRL_SYS_CLK_EN1_REG2 (0x0017 << 2)
> > +#define CLKCTRL_SYS_CLK_EN1_REG3 (0x0018 << 2)
> > +#define CLKCTRL_SYS_CLK_VPU_EN0 (0x0019 << 2)
> > +#define CLKCTRL_SYS_CLK_VPU_EN1 (0x001a << 2)
> > +#define CLKCTRL_AXI_CLK_CTRL0 (0x001b << 2)
> > +#define CLKCTRL_TST_CTRL0 (0x0020 << 2)
> > +#define CLKCTRL_TST_CTRL1 (0x0021 << 2)
> > +#define CLKCTRL_CECA_CTRL0 (0x0022 << 2)
> > +#define CLKCTRL_CECA_CTRL1 (0x0023 << 2)
> > +#define CLKCTRL_CECB_CTRL0 (0x0024 << 2)
> > +#define CLKCTRL_CECB_CTRL1 (0x0025 << 2)
> > +#define CLKCTRL_SC_CLK_CTRL (0x0026 << 2)
> > +#define CLKCTRL_DSPA_CLK_CTRL0 (0x0027 << 2)
> > +#define CLKCTRL_DSPB_CLK_CTRL0 (0x0028 << 2)
> > +#define CLKCTRL_CLK12_24_CTRL (0x002a << 2)
> > +#define CLKCTRL_ANAKIN_CLK_CTRL (0x002b << 2)
> > +#define CLKCTRL_GDC_CLK_CTRL (0x002c << 2)
> > +#define CLKCTRL_AMLGDC_CLK_CTRL (0x002d << 2)
> > +#define CLKCTRL_VID_CLK0_CTRL (0x0030 << 2)
> > +#define CLKCTRL_VID_CLK0_CTRL2 (0x0031 << 2)
> > +#define CLKCTRL_VID_CLK0_DIV (0x0032 << 2)
> > +#define CLKCTRL_VIID_CLK0_DIV (0x0033 << 2)
> > +#define CLKCTRL_VIID_CLK0_CTRL (0x0034 << 2)
> > +#define CLKCTRL_ENC0_HDMI_CLK_CTRL (0x0035 << 2)
> > +#define CLKCTRL_ENC2_HDMI_CLK_CTRL (0x0036 << 2)
> > +#define CLKCTRL_ENC_HDMI_CLK_CTRL (0x0037 << 2)
> > +#define CLKCTRL_HDMI_CLK_CTRL (0x0038 << 2)
> > +#define CLKCTRL_VID_PLL_CLK0_DIV (0x0039 << 2)
> > +#define CLKCTRL_VPU_CLK_CTRL (0x003a << 2)
> > +#define CLKCTRL_VPU_CLKB_CTRL (0x003b << 2)
> > +#define CLKCTRL_VPU_CLKC_CTRL (0x003c << 2)
> > +#define CLKCTRL_VID_LOCK_CLK_CTRL (0x003d << 2)
> > +#define CLKCTRL_VDIN_MEAS_CLK_CTRL (0x003e << 2)
> > +#define CLKCTRL_VAPBCLK_CTRL (0x003f << 2)
> > +#define CLKCTRL_MIPIDSI_PHY_CLK_CTRL (0x0041 << 2)
> > +#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL (0x0043 << 2)
> > +#define CLKCTRL_MIPI_ISP_CLK_CTRL (0x0044 << 2)
> > +#define CLKCTRL_WAVE420L_CLK_CTRL (0x0045 << 2)
> > +#define CLKCTRL_WAVE420L_CLK_CTRL2 (0x0046 << 2)
> > +#define CLKCTRL_HTX_CLK_CTRL0 (0x0047 << 2)
> > +#define CLKCTRL_HTX_CLK_CTRL1 (0x0048 << 2)
> > +#define CLKCTRL_HRX_CLK_CTRL0 (0x004a << 2)
> > +#define CLKCTRL_HRX_CLK_CTRL1 (0x004b << 2)
> > +#define CLKCTRL_HRX_CLK_CTRL2 (0x004c << 2)
> > +#define CLKCTRL_HRX_CLK_CTRL3 (0x004d << 2)
> > +#define CLKCTRL_VDEC_CLK_CTRL (0x0050 << 2)
> > +#define CLKCTRL_VDEC2_CLK_CTRL (0x0051 << 2)
> > +#define CLKCTRL_VDEC3_CLK_CTRL (0x0052 << 2)
> > +#define CLKCTRL_VDEC4_CLK_CTRL (0x0053 << 2)
> > +#define CLKCTRL_WAVE521_CLK_CTRL (0x0054 << 2)
> > +#define CLKCTRL_WAVE521_CLK_CTRL2 (0x0055 << 2)
> > +#define CLKCTRL_TS_CLK_CTRL (0x0056 << 2)
> > +#define CLKCTRL_MALI_CLK_CTRL (0x0057 << 2)
> > +#define CLKCTRL_VIPNANOQ_CLK_CTRL (0x0058 << 2)
> > +#define CLKCTRL_ETH_CLK_CTRL (0x0059 << 2)
> > +#define CLKCTRL_NAND_CLK_CTRL (0x005a << 2)
> > +#define CLKCTRL_SD_EMMC_CLK_CTRL (0x005b << 2)
> > +#define CLKCTRL_BT656_CLK_CTRL (0x005c << 2)
> > +#define CLKCTRL_SPICC_CLK_CTRL (0x005d << 2)
> > +#define CLKCTRL_GEN_CLK_CTRL (0x005e << 2)
> > +#define CLKCTRL_SAR_CLK_CTRL0 (0x005f << 2)
> > +#define CLKCTRL_PWM_CLK_AB_CTRL (0x0060 << 2)
> > +#define CLKCTRL_PWM_CLK_CD_CTRL (0x0061 << 2)
> > +#define CLKCTRL_PWM_CLK_EF_CTRL (0x0062 << 2)
> > +#define CLKCTRL_PWM_CLK_AO_AB_CTRL (0x0068 << 2)
> > +#define CLKCTRL_PWM_CLK_AO_CD_CTRL (0x0069 << 2)
> > +#define CLKCTRL_PWM_CLK_AO_EF_CTRL (0x006a << 2)
> > +#define CLKCTRL_PWM_CLK_AO_GH_CTRL (0x006b << 2)
> > +#define CLKCTRL_SPICC_CLK_CTRL1 (0x0070 << 2)
> > +#define CLKCTRL_SPICC_CLK_CTRL2 (0x0071 << 2)
> > +#define CLKCTRL_VID_CLK1_CTRL (0x0073 << 2)
> > +#define CLKCTRL_VID_CLK1_CTRL2 (0x0074 << 2)
> > +#define CLKCTRL_VID_CLK1_DIV (0x0075 << 2)
> > +#define CLKCTRL_VIID_CLK1_DIV (0x0076 << 2)
> > +#define CLKCTRL_VIID_CLK1_CTRL (0x0077 << 2)
> > +#define CLKCTRL_VID_CLK2_CTRL (0x0078 << 2)
> > +#define CLKCTRL_VID_CLK2_CTRL2 (0x0079 << 2)
> > +#define CLKCTRL_VID_CLK2_DIV (0x007a << 2)
> > +#define CLKCTRL_VIID_CLK2_DIV (0x007b << 2)
> > +#define CLKCTRL_VIID_CLK2_CTRL (0x007c << 2)
> > +#define CLKCTRL_VID_PLL_CLK1_DIV (0x007d << 2)
> > +#define CLKCTRL_VID_PLL_CLK2_DIV (0x007e << 2)
> > +#define CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL (0x0080 << 2)
> > +#define CLKCTRL_TIMESTAMP_CTRL (0x0100 << 2)
> > +#define CLKCTRL_TIMESTAMP_CTRL1 (0x0101 << 2)
> > +#define CLKCTRL_TIMESTAMP_CTRL2 (0x0103 << 2)
> > +#define CLKCTRL_TIMESTAMP_RD0 (0x0104 << 2)
> > +#define CLKCTRL_TIMESTAMP_RD1 (0x0105 << 2)
> > +#define CLKCTRL_TIMEBASE_CTRL0 (0x0106 << 2)
> > +#define CLKCTRL_TIMEBASE_CTRL1 (0x0107 << 2)
> > +#define CLKCTRL_EFUSE_CPU_CFG01 (0x0120 << 2)
> > +#define CLKCTRL_EFUSE_CPU_CFG2 (0x0121 << 2)
> > +#define CLKCTRL_EFUSE_ENCP_CFG0 (0x0122 << 2)
> > +#define CLKCTRL_EFUSE_MALI_CFG01 (0x0123 << 2)
> > +#define CLKCTRL_EFUSE_HEVCB_CFG01 (0x0124 << 2)
> > +#define CLKCTRL_EFUSE_HEVCB_CFG2 (0x0125 << 2)
> > +#define CLKCTRL_EFUSE_LOCK (0x0126 << 2)
> > +#define CLKCTRL_EFUSE_A73_CFG01 (0x0127 << 2)
> > +#define CLKCTRL_EFUSE_A73_CFG2 (0x0128 << 2)
> > +
> > +#endif /* __T7_PERIPHERALS_H */
> > diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c
> > new file mode 100644
> > index 000000000000..bd18df5e965a
> > --- /dev/null
> > +++ b/drivers/clk/meson/t7-pll.c
> > @@ -0,0 +1,1543 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
> > +/*
> > + * Amlogic T7 PLL Clock Controller Driver
> > + *
> > + * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
> > + * Author: Yu Tu <yu.tu@amlogic.com>
> > + */
> > +#include <linux/clk-provider.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mpll.h"
> > +#include "clk-pll.h"
> > +#include "clk-regmap.h"
> > +#include "t7-pll.h"
> > +#include "meson-clkc-utils.h"
> > +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
> > +
> > +static DEFINE_SPINLOCK(meson_clk_lock);
> > +
> > +static struct clk_regmap t7_fixed_pll_dco = {
> > + .data = &(struct meson_clk_pll_data){
> > + .en = {
> > + .reg_off = ANACTRL_FIXPLL_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .m = {
> > + .reg_off = ANACTRL_FIXPLL_CTRL0,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .n = {
> > + .reg_off = ANACTRL_FIXPLL_CTRL0,
> > + .shift = 10,
> > + .width = 5,
> > + },
> > + .frac = {
> > + .reg_off = ANACTRL_FIXPLL_CTRL1,
> > + .shift = 0,
> > + .width = 19,
> > + },
> > + .l = {
> > + .reg_off = ANACTRL_FIXPLL_CTRL0,
> > + .shift = 31,
> > + .width = 1,
> > + },
> > + .rst = {
> > + .reg_off = ANACTRL_FIXPLL_CTRL0,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fixed_pll_dco",
> > + .ops = &meson_clk_pll_ro_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_fixed_pll = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = ANACTRL_FIXPLL_CTRL0,
> > + .shift = 16,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fixed_pll",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_fixed_pll_dco.hw
> > + },
> > + .num_parents = 1,
> > + /*
> > + * This clock won't ever change at runtime so
> > + * CLK_SET_RATE_PARENT is not required
> > + */
> > + .flags = CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static const struct clk_ops meson_pll_clk_no_ops = {};
> > +
> > +/*
> > + * the sys pll DCO value should be 3G~6G,
> > + * otherwise the sys pll can not lock.
> > + * od is for 32 bit.
> > + */
> > +
> > +static const struct pll_params_table t7_sys_pll_params_table[] = {
> > + PLL_PARAMS(67, 1), /*DCO=1608M OD=1608MM*/
> > + PLL_PARAMS(71, 1), /*DCO=1704MM OD=1704M*/
> > + PLL_PARAMS(75, 1), /*DCO=1800M OD=1800M*/
> > + PLL_PARAMS(126, 1), /*DCO=3024 OD=1512M*/
> > + PLL_PARAMS(116, 1), /*DCO=2784 OD=1392M*/
> > + PLL_PARAMS(118, 1), /*DCO=2832M OD=1416M*/
> > + PLL_PARAMS(100, 1), /*DCO=2400M OD=1200M*/
> > + PLL_PARAMS(79, 1), /*DCO=1896M OD=1896M*/
> > + PLL_PARAMS(80, 1), /*DCO=1920M OD=1920M*/
> > + PLL_PARAMS(84, 1), /*DCO=2016M OD=2016M*/
> > + PLL_PARAMS(92, 1), /*DCO=2208M OD=2208M*/
> > + {0, 0},
> > +};
> > +
> > +static struct clk_regmap t7_sys_pll_dco = {
> > + .data = &(struct meson_clk_pll_data){
> > + .en = {
> > + .reg_off = ANACTRL_SYS0PLL_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .m = {
> > + .reg_off = ANACTRL_SYS0PLL_CTRL0,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .n = {
> > + .reg_off = ANACTRL_SYS0PLL_CTRL0,
> > + .shift = 16,
> > + .width = 5,
> > + },
> > + .l = {
> > + .reg_off = ANACTRL_SYS0PLL_CTRL0,
> > + .shift = 31,
> > + .width = 1,
> > + },
> > + .rst = {
> > + .reg_off = ANACTRL_SYS0PLL_CTRL0,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + .table = t7_sys_pll_params_table,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sys_pll_dco",
> > + .ops = &meson_clk_pll_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + /* This clock feeds the CPU, avoid disabling it */
> > + .flags = CLK_IS_CRITICAL,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sys1_pll_dco = {
> > + .data = &(struct meson_clk_pll_data){
> > + .en = {
> > + .reg_off = ANACTRL_SYS1PLL_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .m = {
> > + .reg_off = ANACTRL_SYS1PLL_CTRL0,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .n = {
> > + .reg_off = ANACTRL_SYS1PLL_CTRL0,
> > + .shift = 16,
> > + .width = 5,
> > + },
> > + .table = t7_sys_pll_params_table,
> > + .l = {
> > + .reg_off = ANACTRL_SYS1PLL_CTRL0,
> > + .shift = 31,
> > + .width = 1,
> > + },
> > + .rst = {
> > + .reg_off = ANACTRL_SYS1PLL_CTRL0,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sys1_pll_dco",
> > + .ops = &meson_clk_pll_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + /* This clock feeds the CPU, avoid disabling it */
> > + .flags = CLK_IS_CRITICAL,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sys_pll = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = ANACTRL_SYS0PLL_CTRL0,
> > + .shift = 12,
> > + .width = 3,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sys_pll",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sys_pll_dco.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_sys1_pll = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = ANACTRL_SYS1PLL_CTRL0,
> > + .shift = 12,
> > + .width = 3,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "sys1_pll",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_sys1_pll_dco.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_fclk_div2_div = {
> > + .mult = 1,
> > + .div = 2,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div2_div",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_fixed_pll.hw },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_fclk_div2 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_FIXPLL_CTRL1,
> > + .bit_idx = 24,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div2",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_fclk_div2_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_IS_CRITICAL,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_fclk_div3_div = {
> > + .mult = 1,
> > + .div = 3,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div3_div",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_fixed_pll.hw },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_fclk_div3 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_FIXPLL_CTRL1,
> > + .bit_idx = 20,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div3",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_fclk_div3_div.hw
> > + },
> > + .num_parents = 1,
> > + /*
> > + * This clock is used by the resident firmware and is required
> > + * by the platform to operate correctly.
> > + * Until the following condition are met, we need this clock to
> > + * be marked as critical:
> > + * a) Mark the clock used by a firmware resource, if possible
> > + * b) CCF has a clock hand-off mechanism to make the sure the
> > + * clock stays on until the proper driver comes along
> > + */
> > + .flags = CLK_IS_CRITICAL,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_fclk_div4_div = {
> > + .mult = 1,
> > + .div = 4,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div4_div",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_fixed_pll.hw },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_fclk_div4 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_FIXPLL_CTRL1,
> > + .bit_idx = 21,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div4",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_fclk_div4_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_IS_CRITICAL,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_fclk_div5_div = {
> > + .mult = 1,
> > + .div = 5,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div5_div",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_fixed_pll.hw },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_fclk_div5 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_FIXPLL_CTRL1,
> > + .bit_idx = 22,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div5",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_fclk_div5_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_IS_CRITICAL,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_fclk_div7_div = {
> > + .mult = 1,
> > + .div = 7,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div7_div",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_fixed_pll.hw },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_fclk_div7 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_FIXPLL_CTRL1,
> > + .bit_idx = 23,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div7",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_fclk_div7_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_IS_CRITICAL,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_fclk_div2p5_div = {
> > + .mult = 2,
> > + .div = 5,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div2p5_div",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_fixed_pll.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_fclk_div2p5 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_FIXPLL_CTRL1,
> > + .bit_idx = 25,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "fclk_div2p5",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_fclk_div2p5_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_IS_CRITICAL,
> > + },
> > +};
> > +
> > +static const struct pll_params_table t7_gp0_pll_table[] = {
> > + PLL_PARAMS(141, 1), /* DCO = 3384M OD = 2 PLL = 846M */
> > + PLL_PARAMS(132, 1), /* DCO = 3168M OD = 2 PLL = 792M */
> > + PLL_PARAMS(248, 1), /* DCO = 5952M OD = 3 PLL = 744M */
> > + PLL_PARAMS(96, 1), /* DCO = 2304M OD = 1 PLL = 1152M */
> > + { /* sentinel */ }
> > +};
> > +
> > +/*
> > + * Internal gp0 pll emulation configuration parameters
> > + */
> > +static const struct reg_sequence t7_gp0_init_regs[] = {
> > + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 },
> > + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 },
> > + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
> > + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 },
> > + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x3927200a },
> > + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }
> > +};
> > +
> > +static struct clk_regmap t7_gp0_pll_dco = {
> > + .data = &(struct meson_clk_pll_data){
> > + .en = {
> > + .reg_off = ANACTRL_GP0PLL_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .m = {
> > + .reg_off = ANACTRL_GP0PLL_CTRL0,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .n = {
> > + .reg_off = ANACTRL_GP0PLL_CTRL0,
> > + .shift = 10,
> > + .width = 5,
> > + },
> > + .frac = {
> > + .reg_off = ANACTRL_GP0PLL_CTRL1,
> > + .shift = 0,
> > + .width = 19,
> > + },
> > + .l = {
> > + .reg_off = ANACTRL_GP0PLL_CTRL0,
> > + .shift = 31,
> > + .width = 1,
> > + },
> > + .rst = {
> > + .reg_off = ANACTRL_GP0PLL_CTRL0,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + .table = t7_gp0_pll_table,
> > + .init_regs = t7_gp0_init_regs,
> > + .init_count = ARRAY_SIZE(t7_gp0_init_regs),
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gp0_pll_dco",
> > + .ops = &meson_clk_pll_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gp0_pll = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = ANACTRL_GP0PLL_CTRL0,
> > + .shift = 16,
> > + .width = 3,
> > + .flags = (CLK_DIVIDER_POWER_OF_TWO |
> > + CLK_DIVIDER_ROUND_CLOSEST),
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gp0_pll",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_gp0_pll_dco.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static const struct pll_params_table t7_gp1_pll_table[] = {
> > + PLL_PARAMS(100, 1), /*DCO=4800M OD=1200M*/
> > + PLL_PARAMS(125, 1), /*DCO=3000M OD=1500M*/
> > + { /* sentinel */ }
> > +};
> > +
> > +static const struct reg_sequence t7_gp1_init_regs[] = {
> > + { .reg = ANACTRL_GP1PLL_CTRL1, .def = 0x1420500f },
> > + { .reg = ANACTRL_GP1PLL_CTRL2, .def = 0x00023001 },
> > + { .reg = ANACTRL_GP1PLL_CTRL3, .def = 0x0, .delay_us = 20 },
> > +};
> > +
> > +static struct clk_regmap t7_gp1_pll_dco = {
> > + .data = &(struct meson_clk_pll_data){
> > + .en = {
> > + .reg_off = ANACTRL_GP1PLL_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .m = {
> > + .reg_off = ANACTRL_GP1PLL_CTRL0,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .n = {
> > + .reg_off = ANACTRL_GP1PLL_CTRL0,
> > + .shift = 16,
> > + .width = 5,
> > + },
> > + .l = {
> > + .reg_off = ANACTRL_GP1PLL_CTRL0,
> > + .shift = 31,
> > + .width = 1,
> > + },
> > + .rst = {
> > + .reg_off = ANACTRL_GP1PLL_CTRL0,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + .table = t7_gp1_pll_table,
> > + .init_regs = t7_gp1_init_regs,
> > + .init_count = ARRAY_SIZE(t7_gp1_init_regs)
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gp1_pll_dco",
> > + .ops = &meson_clk_pll_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + /* This clock feeds the DSU, avoid disabling it */
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_gp1_pll = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = ANACTRL_GP1PLL_CTRL0,
> > + .shift = 12,
> > + .width = 3,
> > + .flags = (CLK_DIVIDER_POWER_OF_TWO |
> > + CLK_DIVIDER_ROUND_CLOSEST),
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gp1_pll",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_gp1_pll_dco.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static const struct pll_params_table t7_mclk_pll_table[] = {
> > + PLL_PARAMS(99, 1), /* DCO = 2376M OD = 1 PLL = 1152M */
> > + PLL_PARAMS(100, 1), /* DCO = 2400M */
> > + { /* sentinel */ }
> > +};
> > +
> > +static const struct reg_sequence t7_mclk_init_regs[] = {
> > + { .reg = ANACTRL_MCLK_PLL_CNTL0, .def = 0x20011064, .delay_us = 20 },
> > + { .reg = ANACTRL_MCLK_PLL_CNTL0, .def = 0x30011064 },
> > + { .reg = ANACTRL_MCLK_PLL_CNTL1, .def = 0x1470500f },
> > + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023041 },
> > + { .reg = ANACTRL_MCLK_PLL_CNTL3, .def = 0x18180000 },
> > + { .reg = ANACTRL_MCLK_PLL_CNTL4, .def = 0x00180303 },
> > + { .reg = ANACTRL_MCLK_PLL_CNTL0, .def = 0x10011064, .delay_us = 20 },
> > + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023001, .delay_us = 20 }
> > +};
> > +
> > +static struct clk_regmap t7_mclk_pll_dco = {
> > + .data = &(struct meson_clk_pll_data){
> > + .en = {
> > + .reg_off = ANACTRL_MCLK_PLL_CNTL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .m = {
> > + .reg_off = ANACTRL_MCLK_PLL_CNTL0,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .n = {
> > + .reg_off = ANACTRL_MCLK_PLL_CNTL0,
> > + .shift = 16,
> > + .width = 5,
> > + },
> > + .l = {
> > + .reg_off = ANACTRL_MCLK_PLL_CNTL0,
> > + .shift = 31,
> > + .width = 1,
> > + },
> > + .rst = {
> > + .reg_off = ANACTRL_MCLK_PLL_CNTL0,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + .table = t7_mclk_pll_table,
> > + .init_regs = t7_mclk_init_regs,
> > + .init_count = ARRAY_SIZE(t7_mclk_init_regs),
> > + //.ignore_init = false
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mclk_pll_dco",
> > + .ops = &meson_clk_pll_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED
> > + },
> > +};
> > +
> > +/* max div is 16 */
> > +static const struct clk_div_table mclk_div[] = {
> > + { .val = 0, .div = 1 },
> > + { .val = 1, .div = 2 },
> > + { .val = 2, .div = 4 },
> > + { .val = 3, .div = 8 },
> > + { .val = 4, .div = 16 },
> > + { /* sentinel */ }
> > +};
> > +
> > +static struct clk_regmap t7_mclk_pre_od = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = ANACTRL_MCLK_PLL_CNTL0,
> > + .shift = 12,
> > + .width = 3,
> > + .table = mclk_div,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mclk_pre_od",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mclk_pll_dco.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mclk_pll = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = ANACTRL_MCLK_PLL_CNTL4,
> > + .shift = 16,
> > + .width = 5,
> > + .flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST |
> > + CLK_DIVIDER_ALLOW_ZERO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mclk_pll",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mclk_pre_od.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static const struct pll_params_table t7_hifi_pll_table[] = {
> > + PLL_PARAMS(163, 1), /* DCO = 3932.16M */
> > + { /* sentinel */ }
> > +};
> > +
> > +/*
> > + * Internal hifi pll emulation configuration parameters
> > + */
> > +static const struct reg_sequence t7_hifi_init_regs[] = {
> > + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00014820 }, /*frac = 20.16M */
> > + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 },
> > + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
> > + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
> > + { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x3927200a },
> > + { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 }
> > +};
> > +
> > +static struct clk_regmap t7_hifi_pll_dco = {
> > + .data = &(struct meson_clk_pll_data){
> > + .en = {
> > + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .m = {
> > + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .n = {
> > + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> > + .shift = 10,
> > + .width = 5,
> > + },
> > + .frac = {
> > + .reg_off = ANACTRL_HIFIPLL_CTRL1,
> > + .shift = 0,
> > + .width = 19,
> > + },
> > + .l = {
> > + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> > + .shift = 31,
> > + .width = 1,
> > + },
> > + .rst = {
> > + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + .table = t7_hifi_pll_table,
> > + .init_regs = t7_hifi_init_regs,
> > + .init_count = ARRAY_SIZE(t7_hifi_init_regs),
> > + .flags = CLK_MESON_PLL_ROUND_CLOSEST,
> > + //.new_frac = 1,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hifi_pll_dco",
> > + .ops = &meson_clk_pll_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hifi_pll = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = ANACTRL_HIFIPLL_CTRL0,
> > + .shift = 16,
> > + .width = 2,
> > + .flags = (CLK_DIVIDER_POWER_OF_TWO |
> > + CLK_DIVIDER_ROUND_CLOSEST),
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hifi_pll",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hifi_pll_dco.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +/*
> > + * The Meson t7 PCIE PLL is fined tuned to deliver a very precise
> > + * 100MHz reference clock for the PCIe Analog PHY, and thus requires
> > + * a strict register sequence to enable the PLL.
> > + */
> > +static const struct reg_sequence t7_pcie_pll_init_regs[] = {
> > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x200c04c8 },
> > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x300c04c8 },
> > + { .reg = ANACTRL_PCIEPLL_CTRL1, .def = 0x30000000 },
> > + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001100 },
> > + { .reg = ANACTRL_PCIEPLL_CTRL3, .def = 0x10058e00 },
> > + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x000100c0 },
> > + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000040 },
> > + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000060, .delay_us = 20 },
> > + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x008100c0, .delay_us = 10 },
> > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x340c04c8 },
> > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x140c04c8, .delay_us = 10 },
> > + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001000 }
> > +};
> > +
> > +/* Keep a single entry table for recalc/round_rate() ops */
> > +static const struct pll_params_table t7_pcie_pll_table[] = {
> > + PLL_PARAMS(150, 1),
> > + {0, 0}
> > +};
> > +
> > +static struct clk_regmap t7_pcie_pll_dco = {
> > + .data = &(struct meson_clk_pll_data){
> > + .en = {
> > + .reg_off = ANACTRL_PCIEPLL_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .m = {
> > + .reg_off = ANACTRL_PCIEPLL_CTRL0,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .n = {
> > + .reg_off = ANACTRL_PCIEPLL_CTRL0,
> > + .shift = 10,
> > + .width = 5,
> > + },
> > + .frac = {
> > + .reg_off = ANACTRL_PCIEPLL_CTRL1,
> > + .shift = 0,
> > + .width = 12,
> > + },
> > + .l = {
> > + .reg_off = ANACTRL_PCIEPLL_CTRL0,
> > + .shift = 31,
> > + .width = 1,
> > + },
> > + .rst = {
> > + .reg_off = ANACTRL_PCIEPLL_CTRL0,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + .table = t7_pcie_pll_table,
> > + .init_regs = t7_pcie_pll_init_regs,
> > + .init_count = ARRAY_SIZE(t7_pcie_pll_init_regs),
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie_pll_dco",
> > + .ops = &meson_clk_pcie_pll_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_pcie_pll_dco_div2 = {
> > + .mult = 1,
> > + .div = 2,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie_pll_dco_div2",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pcie_pll_dco.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pcie_pll_od = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = ANACTRL_PCIEPLL_CTRL0,
> > + .shift = 16,
> > + .width = 5,
> > + .flags = CLK_DIVIDER_ROUND_CLOSEST |
> > + CLK_DIVIDER_ONE_BASED |
> > + CLK_DIVIDER_ALLOW_ZERO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie_pll_od",
> > + .ops = &clk_regmap_divider_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pcie_pll_dco_div2.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_pcie_pll = {
> > + .mult = 1,
> > + .div = 2,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie_pll",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_pcie_pll_od.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pcie_bgp = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_PCIEPLL_CTRL5,
> > + .bit_idx = 27,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie_bgp",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_pcie_pll.hw },
> > + .num_parents = 1,
> > + .flags = CLK_IGNORE_UNUSED,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_pcie_hcsl = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_PCIEPLL_CTRL5,
> > + .bit_idx = 3,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie_hcsl",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_pcie_bgp.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmi_pll_dco = {
> > + .data = &(struct meson_clk_pll_data){
> > + .en = {
> > + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> > + .shift = 28,
> > + .width = 1,
> > + },
> > + .m = {
> > + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> > + .shift = 0,
> > + .width = 8,
> > + },
> > + .n = {
> > + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> > + .shift = 10,
> > + .width = 5,
> > + },
> > + .frac = {
> > + .reg_off = ANACTRL_HDMIPLL_CTRL1,
> > + .shift = 0,
> > + .width = 19,
> > + },
> > + .l = {
> > + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> > + .shift = 31,
> > + .width = 1,
> > + },
> > + .rst = {
> > + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmi_pll_dco",
> > + .ops = &meson_clk_pll_ro_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + /*
> > + * Display directly handle hdmi pll registers ATM, we need
> > + * NOCACHE to keep our view of the clock as accurate as
> > + * possible
> > + */
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmi_pll_od = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = ANACTRL_HDMIPLL_CTRL0,
> > + .shift = 16,
> > + .width = 4,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmi_pll_od",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hdmi_pll_dco.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_hdmi_pll = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = ANACTRL_HDMIPLL_CTRL0,
> > + .shift = 20,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmi_pll",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_hdmi_pll_od.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_mpll_50m_div = {
> > + .mult = 1,
> > + .div = 80,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mpll_50m_div",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_fixed_pll_dco.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static const struct clk_parent_data t7_mpll_50m_sel[] = {
> > + { .fw_name = "xtal", },
> > + { .hw = &t7_mpll_50m_div.hw },
> > +};
> > +
> > +static struct clk_regmap t7_mpll_50m = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = ANACTRL_FIXPLL_CTRL3,
> > + .mask = 0x1,
> > + .shift = 5,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mpll_50m",
> > + .ops = &clk_regmap_mux_ro_ops,
> > + .parent_data = t7_mpll_50m_sel,
> > + .num_parents = ARRAY_SIZE(t7_mpll_50m_sel),
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_mpll_prediv = {
> > + .mult = 1,
> > + .div = 2,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mpll_prediv",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_fixed_pll_dco.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static const struct reg_sequence t7_mpll0_init_regs[] = {
> > + { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 }
> > +};
> > +
> > +static struct clk_regmap t7_mpll0_div = {
> > + .data = &(struct meson_clk_mpll_data){
> > + .sdm = {
> > + .reg_off = ANACTRL_MPLL_CTRL1,
> > + .shift = 0,
> > + .width = 14,
> > + },
> > + .sdm_en = {
> > + .reg_off = ANACTRL_MPLL_CTRL1,
> > + .shift = 30,
> > + .width = 1,
> > + },
> > + .n2 = {
> > + .reg_off = ANACTRL_MPLL_CTRL1,
> > + .shift = 20,
> > + .width = 9,
> > + },
> > + .ssen = {
> > + .reg_off = ANACTRL_MPLL_CTRL1,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + .lock = &meson_clk_lock,
> > + .init_regs = t7_mpll0_init_regs,
> > + .init_count = ARRAY_SIZE(t7_mpll0_init_regs),
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mpll0_div",
> > + .ops = &meson_clk_mpll_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mpll_prediv.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mpll0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_MPLL_CTRL1,
> > + .bit_idx = 31,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mpll0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_mpll0_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static const struct reg_sequence t7_mpll1_init_regs[] = {
> > + { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 }
> > +};
> > +
> > +static struct clk_regmap t7_mpll1_div = {
> > + .data = &(struct meson_clk_mpll_data){
> > + .sdm = {
> > + .reg_off = ANACTRL_MPLL_CTRL3,
> > + .shift = 0,
> > + .width = 14,
> > + },
> > + .sdm_en = {
> > + .reg_off = ANACTRL_MPLL_CTRL3,
> > + .shift = 30,
> > + .width = 1,
> > + },
> > + .n2 = {
> > + .reg_off = ANACTRL_MPLL_CTRL3,
> > + .shift = 20,
> > + .width = 9,
> > + },
> > + .ssen = {
> > + .reg_off = ANACTRL_MPLL_CTRL3,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + .lock = &meson_clk_lock,
> > + .init_regs = t7_mpll1_init_regs,
> > + .init_count = ARRAY_SIZE(t7_mpll1_init_regs),
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mpll1_div",
> > + .ops = &meson_clk_mpll_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mpll_prediv.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mpll1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_MPLL_CTRL3,
> > + .bit_idx = 31,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mpll1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_mpll1_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static const struct reg_sequence t7_mpll2_init_regs[] = {
> > + { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 }
> > +};
> > +
> > +static struct clk_regmap t7_mpll2_div = {
> > + .data = &(struct meson_clk_mpll_data){
> > + .sdm = {
> > + .reg_off = ANACTRL_MPLL_CTRL5,
> > + .shift = 0,
> > + .width = 14,
> > + },
> > + .sdm_en = {
> > + .reg_off = ANACTRL_MPLL_CTRL5,
> > + .shift = 30,
> > + .width = 1,
> > + },
> > + .n2 = {
> > + .reg_off = ANACTRL_MPLL_CTRL5,
> > + .shift = 20,
> > + .width = 9,
> > + },
> > + .ssen = {
> > + .reg_off = ANACTRL_MPLL_CTRL5,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + .lock = &meson_clk_lock,
> > + .init_regs = t7_mpll2_init_regs,
> > + .init_count = ARRAY_SIZE(t7_mpll2_init_regs),
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mpll2_div",
> > + .ops = &meson_clk_mpll_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mpll_prediv.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mpll2 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_MPLL_CTRL5,
> > + .bit_idx = 31,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mpll2",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_mpll2_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static const struct reg_sequence t7_mpll3_init_regs[] = {
> > + { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 }
> > +};
> > +
> > +static struct clk_regmap t7_mpll3_div = {
> > + .data = &(struct meson_clk_mpll_data){
> > + .sdm = {
> > + .reg_off = ANACTRL_MPLL_CTRL7,
> > + .shift = 0,
> > + .width = 14,
> > + },
> > + .sdm_en = {
> > + .reg_off = ANACTRL_MPLL_CTRL7,
> > + .shift = 30,
> > + .width = 1,
> > + },
> > + .n2 = {
> > + .reg_off = ANACTRL_MPLL_CTRL7,
> > + .shift = 20,
> > + .width = 9,
> > + },
> > + .ssen = {
> > + .reg_off = ANACTRL_MPLL_CTRL7,
> > + .shift = 29,
> > + .width = 1,
> > + },
> > + .lock = &meson_clk_lock,
> > + .init_regs = t7_mpll3_init_regs,
> > + .init_count = ARRAY_SIZE(t7_mpll3_init_regs),
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mpll3_div",
> > + .ops = &meson_clk_mpll_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mpll_prediv.hw
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mpll3 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_MPLL_CTRL7,
> > + .bit_idx = 31,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mpll3",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_mpll3_div.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mclk_0_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = ANACTRL_MCLK_PLL_CNTL4,
> > + .mask = 0x3,
> > + .shift = 4,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mclk_0_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = (const struct clk_parent_data []) {
> > + { .hw = &t7_mclk_pll.hw },
> > + { .fw_name = "xtal", },
> > + { .hw = &t7_mpll_50m.hw },
> > + },
> > + .num_parents = 3,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_mclk_0_div2 = {
> > + .mult = 1,
> > + .div = 2,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mclk_0_div2",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_mclk_0_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mclk_0_pre = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_MCLK_PLL_CNTL4,
> > + .bit_idx = 2,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "mclk_0_pre",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mclk_0_div2.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mclk_0 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_MCLK_PLL_CNTL4,
> > + .bit_idx = 0,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "mclk_0",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mclk_0_pre.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mclk_1_sel = {
> > + .data = &(struct clk_regmap_mux_data){
> > + .offset = ANACTRL_MCLK_PLL_CNTL4,
> > + .mask = 0x3,
> > + .shift = 12,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mclk_1_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_data = (const struct clk_parent_data []) {
> > + { .hw = &t7_mclk_pll.hw },
> > + { .fw_name = "xtal", },
> > + { .hw = &t7_mpll_50m.hw },
> > + },
> > + .num_parents = 3,
> > + },
> > +};
> > +
> > +static struct clk_fixed_factor t7_mclk_1_div2 = {
> > + .mult = 1,
> > + .div = 2,
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mclk_1_div2",
> > + .ops = &clk_fixed_factor_ops,
> > + .parent_hws = (const struct clk_hw *[]) { &t7_mclk_1_sel.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mclk_1_pre = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_MCLK_PLL_CNTL4,
> > + .bit_idx = 10,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "mclk_1_pre",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mclk_1_div2.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +static struct clk_regmap t7_mclk_1 = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = ANACTRL_MCLK_PLL_CNTL4,
> > + .bit_idx = 8,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "mclk_1",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &t7_mclk_1_pre.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +/* Array of all clocks provided by this provider */
> > +static struct clk_hw *t7_pll_hw_clks[] = {
> > + [CLKID_FIXED_PLL_DCO] = &t7_fixed_pll_dco.hw,
> > + [CLKID_FIXED_PLL] = &t7_fixed_pll.hw,
> > + [CLKID_SYS_PLL_DCO] = &t7_sys_pll_dco.hw,
> > + [CLKID_SYS_PLL] = &t7_sys_pll.hw,
> > + [CLKID_SYS1_PLL_DCO] = &t7_sys1_pll_dco.hw,
> > + [CLKID_SYS1_PLL] = &t7_sys1_pll.hw,
> > + [CLKID_FCLK_DIV2_DIV] = &t7_fclk_div2_div.hw,
> > + [CLKID_FCLK_DIV2] = &t7_fclk_div2.hw,
> > + [CLKID_FCLK_DIV3_DIV] = &t7_fclk_div3_div.hw,
> > + [CLKID_FCLK_DIV3] = &t7_fclk_div3.hw,
> > + [CLKID_FCLK_DIV4_DIV] = &t7_fclk_div4_div.hw,
> > + [CLKID_FCLK_DIV4] = &t7_fclk_div4.hw,
> > + [CLKID_FCLK_DIV5_DIV] = &t7_fclk_div5_div.hw,
> > + [CLKID_FCLK_DIV5] = &t7_fclk_div5.hw,
> > + [CLKID_FCLK_DIV7_DIV] = &t7_fclk_div7_div.hw,
> > + [CLKID_FCLK_DIV7] = &t7_fclk_div7.hw,
> > + [CLKID_FCLK_DIV2P5_DIV] = &t7_fclk_div2p5_div.hw,
> > + [CLKID_FCLK_DIV2P5] = &t7_fclk_div2p5.hw,
> > + [CLKID_GP0_PLL_DCO] = &t7_gp0_pll_dco.hw,
> > + [CLKID_GP0_PLL] = &t7_gp0_pll.hw,
> > + [CLKID_GP1_PLL_DCO] = &t7_gp1_pll_dco.hw,
> > + [CLKID_GP1_PLL] = &t7_gp1_pll.hw,
> > + [CLKID_MCLK_PLL_DCO] = &t7_mclk_pll_dco.hw,
> > + [CLKID_MCLK_PRE] = &t7_mclk_pre_od.hw,
> > + [CLKID_MCLK_PLL] = &t7_mclk_pll.hw,
> > + [CLKID_HIFI_PLL_DCO] = &t7_hifi_pll_dco.hw,
> > + [CLKID_HIFI_PLL] = &t7_hifi_pll.hw,
> > + [CLKID_PCIE_PLL_DCO] = &t7_pcie_pll_dco.hw,
> > + [CLKID_PCIE_PLL_DCO_DIV2] = &t7_pcie_pll_dco_div2.hw,
> > + [CLKID_PCIE_PLL_OD] = &t7_pcie_pll_od.hw,
> > + [CLKID_PCIE_PLL] = &t7_pcie_pll.hw,
> > + [CLKID_PCIE_BGP] = &t7_pcie_bgp.hw,
> > + [CLKID_PCIE_HCSL] = &t7_pcie_hcsl.hw,
> > + [CLKID_HDMI_PLL_DCO] = &t7_hdmi_pll_dco.hw,
> > + [CLKID_HDMI_PLL_OD] = &t7_hdmi_pll_od.hw,
> > + [CLKID_HDMI_PLL] = &t7_hdmi_pll.hw,
> > + [CLKID_MPLL_50M_DIV] = &t7_mpll_50m_div.hw,
> > + [CLKID_MPLL_50M] = &t7_mpll_50m.hw,
> > + [CLKID_MPLL_PREDIV] = &t7_mpll_prediv.hw,
> > + [CLKID_MPLL0_DIV] = &t7_mpll0_div.hw,
> > + [CLKID_MPLL0] = &t7_mpll0.hw,
> > + [CLKID_MPLL1_DIV] = &t7_mpll1_div.hw,
> > + [CLKID_MPLL1] = &t7_mpll1.hw,
> > + [CLKID_MPLL2_DIV] = &t7_mpll2_div.hw,
> > + [CLKID_MPLL2] = &t7_mpll2.hw,
> > + [CLKID_MPLL3_DIV] = &t7_mpll3_div.hw,
> > + [CLKID_MPLL3] = &t7_mpll3.hw,
> > + [CLKID_MCLK_0_SEL] = &t7_mclk_0_sel.hw,
> > + [CLKID_MCLK_0_DIV2] = &t7_mclk_0_div2.hw,
> > + [CLKID_MCLK_0_PRE] = &t7_mclk_0_pre.hw,
> > + [CLKID_MCLK_0] = &t7_mclk_0.hw,
> > + [CLKID_MCLK_1_SEL] = &t7_mclk_1_sel.hw,
> > + [CLKID_MCLK_1_DIV2] = &t7_mclk_1_div2.hw,
> > + [CLKID_MCLK_1_PRE] = &t7_mclk_1_pre.hw,
> > + [CLKID_MCLK_1] = &t7_mclk_1.hw,
> > +};
> > +
> > +static struct clk_regmap *const t7_pll_clk_regmaps[] = {
> > + &t7_fixed_pll_dco,
> > + &t7_fixed_pll,
> > + &t7_sys_pll_dco,
> > + &t7_sys_pll,
> > + &t7_sys1_pll_dco,
> > + &t7_sys1_pll,
> > + &t7_fclk_div2,
> > + &t7_fclk_div3,
> > + &t7_fclk_div4,
> > + &t7_fclk_div5,
> > + &t7_fclk_div7,
> > + &t7_fclk_div2p5,
> > + &t7_gp0_pll_dco,
> > + &t7_gp0_pll,
> > + &t7_gp1_pll_dco,
> > + &t7_gp1_pll,
> > + &t7_mclk_pll_dco,
> > + &t7_mclk_pre_od,
> > + &t7_mclk_pll,
> > + &t7_hifi_pll_dco,
> > + &t7_hifi_pll,
> > + &t7_pcie_pll_dco,
> > + &t7_pcie_pll_od,
> > + &t7_pcie_bgp,
> > + &t7_pcie_hcsl,
> > + &t7_hdmi_pll_dco,
> > + &t7_hdmi_pll_od,
> > + &t7_hdmi_pll,
> > + &t7_mpll_50m,
> > + &t7_mpll0_div,
> > + &t7_mpll0,
> > + &t7_mpll1_div,
> > + &t7_mpll1,
> > + &t7_mpll2_div,
> > + &t7_mpll2,
> > + &t7_mpll3_div,
> > + &t7_mpll3,
> > + &t7_mclk_0_sel,
> > + &t7_mclk_0_pre,
> > + &t7_mclk_0,
> > + &t7_mclk_1_sel,
> > + &t7_mclk_1_pre,
> > + &t7_mclk_1
> > +};
> > +
> > +static const struct reg_sequence t7_init_regs[] = {
> > + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
> > +};
> > +
> > +static struct regmap_config clkc_regmap_config = {
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
> > +};
> > +
> > +static struct meson_clk_hw_data t7_pll_clks = {
> > + .hws = t7_pll_hw_clks,
> > + .num = ARRAY_SIZE(t7_pll_hw_clks),
> > +};
> > +
> > +static int amlogic_t7_pll_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct regmap *regmap;
> > + void __iomem *base;
> > + int ret, i;
> > +
> > + base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(base))
> > + return dev_err_probe(dev, PTR_ERR(base), "can't ioremap resource\n");
> > +
> > + regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
> > + if (IS_ERR(regmap))
> > + return dev_err_probe(dev, PTR_ERR(regmap), "can't init regmap mmio region\n");
> > +
> > + ret = regmap_multi_reg_write(regmap, t7_init_regs, ARRAY_SIZE(t7_init_regs));
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to init registers\n");
> > +
> > + for (i = 0; i < ARRAY_SIZE(t7_pll_clk_regmaps); i++)
> > + t7_pll_clk_regmaps[i]->map = regmap;
> > +
> > + /* Register clocks */
> > + for (i = 0; i < t7_pll_clks.num; i++) {
> > + /* array might be sparse */
> > + if (!t7_pll_clks.hws[i])
> > + continue;
> > +
> > + ret = devm_clk_hw_register(dev, t7_pll_clks.hws[i]);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "clock[%d] registration failed\n", i);
> > + }
> > +
> > + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &t7_pll_clks);
> > +}
> > +
> > +static const struct of_device_id t7_pll_clkc_match_table[] = {
> > + { .compatible = "amlogic,t7-pll-clkc", },
> > + {}
> > +};
> > +MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table);
> > +
> > +static struct platform_driver t7_pll_clkc_driver = {
> > + .probe = amlogic_t7_pll_probe,
> > + .driver = {
> > + .name = "t7-pll-clkc",
> > + .of_match_table = t7_pll_clkc_match_table,
> > + },
> > +};
> > +
> > +module_platform_driver(t7_pll_clkc_driver);
> > +MODULE_AUTHOR("Yu Tu <yu.tu@amlogic.com>");
> > +MODULE_AUTHOR("Lucas Tanure <tanure@linux.com>");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/clk/meson/t7-pll.h b/drivers/clk/meson/t7-pll.h
> > new file mode 100644
> > index 000000000000..bb0d66198780
> > --- /dev/null
> > +++ b/drivers/clk/meson/t7-pll.h
> > @@ -0,0 +1,83 @@
> > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> > +/*
> > + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> > + */
> > +
> > +#ifndef __MESON_T7_PLL_H__
> > +#define __MESON_T7_PLL_H__
> > +
> > +/* ANA_CTRL - Registers
> > + * REG_BASE: REGISTER_BASE_ADDR = 0xfe008000
> > + */
> > +#define ANACTRL_SYS0PLL_CTRL0 (0x0000 << 2)
> > +#define ANACTRL_SYS0PLL_CTRL1 (0x0001 << 2)
> > +#define ANACTRL_SYS0PLL_CTRL2 (0x0002 << 2)
> > +#define ANACTRL_SYS0PLL_CTRL3 (0x0003 << 2)
> > +#define ANACTRL_SYS0PLL_STS (0x0004 << 2)
> > +#define ANACTRL_SYS1PLL_CTRL0 (0x0008 << 2)
> > +#define ANACTRL_SYS1PLL_CTRL1 (0x0009 << 2)
> > +#define ANACTRL_SYS1PLL_CTRL2 (0x000a << 2)
> > +#define ANACTRL_SYS1PLL_CTRL3 (0x000b << 2)
> > +#define ANACTRL_SYS1PLL_STS (0x000c << 2)
> > +#define ANACTRL_FIXPLL_CTRL0 (0x0010 << 2)
> > +#define ANACTRL_FIXPLL_CTRL1 (0x0011 << 2)
> > +#define ANACTRL_FIXPLL_CTRL2 (0x0012 << 2)
> > +#define ANACTRL_FIXPLL_CTRL3 (0x0013 << 2)
> > +#define ANACTRL_FIXPLL_CTRL4 (0x0014 << 2)
> > +#define ANACTRL_FIXPLL_CTRL5 (0x0015 << 2)
> > +#define ANACTRL_FIXPLL_CTRL6 (0x0016 << 2)
> > +#define ANACTRL_FIXPLL_STS (0x0017 << 2)
> > +#define ANACTRL_GP0PLL_CTRL0 (0x0020 << 2)
> > +#define ANACTRL_GP0PLL_CTRL1 (0x0021 << 2)
> > +#define ANACTRL_GP0PLL_CTRL2 (0x0022 << 2)
> > +#define ANACTRL_GP0PLL_CTRL3 (0x0023 << 2)
> > +#define ANACTRL_GP0PLL_CTRL4 (0x0024 << 2)
> > +#define ANACTRL_GP0PLL_CTRL5 (0x0025 << 2)
> > +#define ANACTRL_GP0PLL_CTRL6 (0x0026 << 2)
> > +#define ANACTRL_GP0PLL_STS (0x0027 << 2)
> > +#define ANACTRL_GP1PLL_CTRL0 (0x0030 << 2)
> > +#define ANACTRL_GP1PLL_CTRL1 (0x0031 << 2)
> > +#define ANACTRL_GP1PLL_CTRL2 (0x0032 << 2)
> > +#define ANACTRL_GP1PLL_CTRL3 (0x0033 << 2)
> > +#define ANACTRL_GP1PLL_STS (0x0037 << 2)
> > +#define ANACTRL_HIFIPLL_CTRL0 (0x0040 << 2)
> > +#define ANACTRL_HIFIPLL_CTRL1 (0x0041 << 2)
> > +#define ANACTRL_HIFIPLL_CTRL2 (0x0042 << 2)
> > +#define ANACTRL_HIFIPLL_CTRL3 (0x0043 << 2)
> > +#define ANACTRL_HIFIPLL_CTRL4 (0x0044 << 2)
> > +#define ANACTRL_HIFIPLL_CTRL5 (0x0045 << 2)
> > +#define ANACTRL_HIFIPLL_CTRL6 (0x0046 << 2)
> > +#define ANACTRL_HIFIPLL_STS (0x0047 << 2)
> > +#define ANACTRL_PCIEPLL_CTRL0 (0x0050 << 2)
> > +#define ANACTRL_PCIEPLL_CTRL1 (0x0051 << 2)
> > +#define ANACTRL_PCIEPLL_CTRL2 (0x0052 << 2)
> > +#define ANACTRL_PCIEPLL_CTRL3 (0x0053 << 2)
> > +#define ANACTRL_PCIEPLL_CTRL4 (0x0054 << 2)
> > +#define ANACTRL_PCIEPLL_CTRL5 (0x0055 << 2)
> > +#define ANACTRL_PCIEPLL_STS (0x0056 << 2)
> > +#define ANACTRL_MPLL_CTRL0 (0x0060 << 2)
> > +#define ANACTRL_MPLL_CTRL1 (0x0061 << 2)
> > +#define ANACTRL_MPLL_CTRL2 (0x0062 << 2)
> > +#define ANACTRL_MPLL_CTRL3 (0x0063 << 2)
> > +#define ANACTRL_MPLL_CTRL4 (0x0064 << 2)
> > +#define ANACTRL_MPLL_CTRL5 (0x0065 << 2)
> > +#define ANACTRL_MPLL_CTRL6 (0x0066 << 2)
> > +#define ANACTRL_MPLL_CTRL7 (0x0067 << 2)
> > +#define ANACTRL_MPLL_CTRL8 (0x0068 << 2)
> > +#define ANACTRL_MPLL_STS (0x0069 << 2)
> > +#define ANACTRL_HDMIPLL_CTRL0 (0x0070 << 2)
> > +#define ANACTRL_HDMIPLL_CTRL1 (0x0071 << 2)
> > +#define ANACTRL_HDMIPLL_CTRL2 (0x0072 << 2)
> > +#define ANACTRL_HDMIPLL_CTRL3 (0x0073 << 2)
> > +#define ANACTRL_HDMIPLL_CTRL4 (0x0074 << 2)
> > +#define ANACTRL_HDMIPLL_CTRL5 (0x0075 << 2)
> > +#define ANACTRL_HDMIPLL_CTRL6 (0x0076 << 2)
> > +#define ANACTRL_HDMIPLL_STS (0x0077 << 2)
> > +#define ANACTRL_MCLK_PLL_CNTL0 (0x00c0 << 2)
> > +#define ANACTRL_MCLK_PLL_CNTL1 (0x00c1 << 2)
> > +#define ANACTRL_MCLK_PLL_CNTL2 (0x00c2 << 2)
> > +#define ANACTRL_MCLK_PLL_CNTL3 (0x00c3 << 2)
> > +#define ANACTRL_MCLK_PLL_CNTL4 (0x00c4 << 2)
> > +#define ANACTRL_MCLK_PLL_STS (0x00c5 << 2)
> > +
> > +#endif /* __MESON_T7_PLL_H__ */
> > diff --git a/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
> > new file mode 100644
> > index 000000000000..64731385c64b
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
> > @@ -0,0 +1,410 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> > +/*
> > + * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved.
> > + * Author: Yu Tu <yu.tu@amlogic.com>
> > + */
> > +
> > +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_T7_PERIPHERALS_CLKC_H
> > +#define _DT_BINDINGS_CLOCK_AMLOGIC_T7_PERIPHERALS_CLKC_H
> > +
> > +#define CLKID_RTC_32K_CLKIN 0
> > +#define CLKID_RTC_32K_DIV 1
> > +#define CLKID_RTC_32K_XATL 2
> > +#define CLKID_RTC_32K_MUX 3
> > +#define CLKID_RTC_CLK 4
> > +#define CLKID_SYS_CLK_B_MUX 5
> > +#define CLKID_SYS_CLK_B_DIV 6
> > +#define CLKID_SYS_CLK_B_GATE 7
> > +#define CLKID_SYS_CLK_A_MUX 8
> > +#define CLKID_SYS_CLK_A_DIV 9
> > +#define CLKID_SYS_CLK_A_GATE 10
> > +#define CLKID_SYS_CLK 11
> > +#define CLKID_CECA_32K_CLKIN 12
> > +#define CLKID_CECA_32K_DIV 13
> > +#define CLKID_CECA_32K_MUX_PRE 14
> > +#define CLKID_CECA_32K_MUX 15
> > +#define CLKID_CECA_32K_CLKOUT 16
> > +#define CLKID_CECB_32K_CLKIN 17
> > +#define CLKID_CECB_32K_DIV 18
> > +#define CLKID_CECB_32K_MUX_PRE 19
> > +#define CLKID_CECB_32K_MUX 20
> > +#define CLKID_CECB_32K_CLKOUT 21
> > +#define CLKID_SC_CLK_MUX 22
> > +#define CLKID_SC_CLK_DIV 23
> > +#define CLKID_SC_CLK_GATE 24
> > +#define CLKID_DSPA_CLK_B_MUX 25
> > +#define CLKID_DSPA_CLK_B_DIV 26
> > +#define CLKID_DSPA_CLK_B_GATE 27
> > +#define CLKID_DSPA_CLK_A_MUX 28
> > +#define CLKID_DSPA_CLK_A_DIV 29
> > +#define CLKID_DSPA_CLK_A_GATE 30
> > +#define CLKID_DSPA_CLK 31
> > +#define CLKID_24M_CLK_GATE 32
> > +#define CLKID_12M_CLK_DIV 33
> > +#define CLKID_12M_CLK_GATE 34
> > +#define CLKID_25M_CLK_DIV 35
> > +#define CLKID_25M_CLK_GATE 36
> > +#define CLKID_VID_PLL_DIV 37
> > +#define CLKID_VID_PLL_MUX 38
> > +#define CLKID_VID_PLL 39
> > +#define CLKID_VCLK_MUX 40
> > +#define CLKID_VCLK2_MUX 41
> > +#define CLKID_VCLK_INPUT 42
> > +#define CLKID_VCLK2_INPUT 43
> > +#define CLKID_VCLK_DIV 44
> > +#define CLKID_VCLK2_DIV 45
> > +#define CLKID_VCLK 46
> > +#define CLKID_VCLK2 47
> > +#define CLKID_VCLK_DIV1 48
> > +#define CLKID_VCLK_DIV2_EN 49
> > +#define CLKID_VCLK_DIV4_EN 50
> > +#define CLKID_VCLK_DIV6_EN 51
> > +#define CLKID_VCLK_DIV12_EN 52
> > +#define CLKID_VCLK2_DIV1 53
> > +#define CLKID_VCLK2_DIV2_EN 54
> > +#define CLKID_VCLK2_DIV4_EN 55
> > +#define CLKID_VCLK2_DIV6_EN 56
> > +#define CLKID_VCLK2_DIV12_EN 57
> > +#define CLKID_VCLK_DIV2 58
> > +#define CLKID_VCLK_DIV4 59
> > +#define CLKID_VCLK_DIV6 60
> > +#define CLKID_VCLK_DIV12 61
> > +#define CLKID_VCLK2_DIV2 62
> > +#define CLKID_VCLK2_DIV4 63
> > +#define CLKID_VCLK2_DIV6 64
> > +#define CLKID_VCLK2_DIV12 65
> > +#define CLKID_CTS_ENCI_MUX 66
> > +#define CLKID_CTS_ENCP_MUX 67
> > +#define CLKID_CTS_VDAC_MUX 68
> > +#define CLKID_HDMI_TX_MUX 69
> > +#define CLKID_CTS_ENCI 70
> > +#define CLKID_CTS_ENCP 71
> > +#define CLKID_CTS_VDAC 72
> > +#define CLKID_HDMI_TX 73
> > +#define CLKID_HDMITX_SYS_MUX 74
> > +#define CLKID_HDMITX_SYS_DIV 75
> > +#define CLKID_HDMITX_SYS 76
> > +#define CLKID_TS_CLK_DIV 77
> > +#define CLKID_TS_CLK_GATE 78
> > +#define CLKID_MALI_0_SEL 79
> > +#define CLKID_MALI_0_DIV 80
> > +#define CLKID_MALI_0 81
> > +#define CLKID_MALI_1_SEL 82
> > +#define CLKID_MALI_1_DIV 83
> > +#define CLKID_MALI_1 84
> > +#define CLKID_MALI_MUX 85
> > +#define CLKID_VDEC_P0_MUX 86
> > +#define CLKID_VDEC_P0_DIV 87
> > +#define CLKID_VDEC_P0 88
> > +#define CLKID_VDEC_P1_MUX 89
> > +#define CLKID_VDEC_P1_DIV 90
> > +#define CLKID_VDEC_P1 91
> > +#define CLKID_VDEC_MUX 92
> > +#define CLKID_HCODEC_P0_MUX 93
> > +#define CLKID_HCODEC_P0_DIV 94
> > +#define CLKID_HCODEC_P0 95
> > +#define CLKID_HCODEC_P1_MUX 96
> > +#define CLKID_HCODEC_P1_DIV 97
> > +#define CLKID_HCODEC_P1 98
> > +#define CLKID_HCODEC_MUX 99
> > +#define CLKID_HEVCB_P0_MUX 100
> > +#define CLKID_HEVCB_P0_DIV 101
> > +#define CLKID_HEVCB_P0 102
> > +#define CLKID_HEVCB_P1_MUX 103
> > +#define CLKID_HEVCB_P1_DIV 104
> > +#define CLKID_HEVCB_P1 105
> > +#define CLKID_HEVCB_MUX 106
> > +#define CLKID_HEVCF_P0_MUX 107
> > +#define CLKID_HEVCF_P0_DIV 108
> > +#define CLKID_HEVCF_P0 109
> > +#define CLKID_HEVCF_P1_MUX 110
> > +#define CLKID_HEVCF_P1_DIV 111
> > +#define CLKID_HEVCF_P1 112
> > +#define CLKID_HEVCF_MUX 113
> > +#define CLKID_WAVE_A_MUX 114
> > +#define CLKID_WAVE_A_DIV 115
> > +#define CLKID_WAVE_A_GATE 116
> > +#define CLKID_WAVE_B_MUX 117
> > +#define CLKID_WAVE_B_DIV 118
> > +#define CLKID_WAVE_B_GATE 119
> > +#define CLKID_WAVE_C_MUX 120
> > +#define CLKID_WAVE_C_DIV 121
> > +#define CLKID_WAVE_C_GATE 122
> > +#define CLKID_VPU_0_MUX 123
> > +#define CLKID_VPU_0_DIV 124
> > +#define CLKID_VPU_0 125
> > +#define CLKID_VPU_1_MUX 126
> > +#define CLKID_VPU_1_DIV 127
> > +#define CLKID_VPU_1 128
> > +#define CLKID_VPU 129
> > +#define CLKID_VPU_CLKB_TMP_MUX 130
> > +#define CLKID_VPU_CLKB_TMP_DIV 131
> > +#define CLKID_VPU_CLKB_TMP 132
> > +#define CLKID_VPU_CLKB_DIV 133
> > +#define CLKID_VPU_CLKB 134
> > +#define CLKID_VPU_CLKC_P0_MUX 135
> > +#define CLKID_VPU_CLKC_P0_DIV 136
> > +#define CLKID_VPU_CLKC_P0 137
> > +#define CLKID_VPU_CLKC_P1_MUX 138
> > +#define CLKID_VPU_CLKC_P1_DIV 139
> > +#define CLKID_VPU_CLKC_P1 140
> > +#define CLKID_VPU_CLKC_MUX 141
> > +#define CLKID_VAPB_0_MUX 142
> > +#define CLKID_VAPB_0_DIV 143
> > +#define CLKID_VAPB_0 144
> > +#define CLKID_VAPB_1_MUX 145
> > +#define CLKID_VAPB_1_DIV 146
> > +#define CLKID_VAPB_1 147
> > +#define CLKID_VAPB 148
> > +#define CLKID_GE2D 149
> > +#define CLKID_VDIN_MEAS_MUX 150
> > +#define CLKID_VDIN_MEAS_DIV 151
> > +#define CLKID_VDIN_MEAS_GATE 152
> > +#define CLKID_DSI_A_MEAS_MUX 153
> > +#define CLKID_DSI_A_MEAS_DIV 154
> > +#define CLKID_DSI_A_MEAS_GATE 155
> > +#define CLKID_DSI_B_MEAS_MUX 156
> > +#define CLKID_DSI_B_MEAS_DIV 157
> > +#define CLKID_DSI_B_MEAS_GATE 158
> > +#define CLKID_DSI0_PHY_MUX 159
> > +#define CLKID_DSI0_PHY_DIV 160
> > +#define CLKID_DSI0_PHY_GATE 161
> > +#define CLKID_DSI1_PHY_MUX 162
> > +#define CLKID_DSI1_PHY_DIV 163
> > +#define CLKID_DSI1_PHY_GATE 164
> > +#define CLKID_VID_LOCK_DIV 165
> > +#define CLKID_VID_LOCK 166
> > +#define CLKID_PWM_A_MUX 167
> > +#define CLKID_PWM_A_DIV 168
> > +#define CLKID_PWM_A_GATE 169
> > +#define CLKID_PWM_B_MUX 170
> > +#define CLKID_PWM_B_DIV 171
> > +#define CLKID_PWM_B_GATE 172
> > +#define CLKID_PWM_C_MUX 173
> > +#define CLKID_PWM_C_DIV 174
> > +#define CLKID_PWM_C_GATE 175
> > +#define CLKID_PWM_D_MUX 176
> > +#define CLKID_PWM_D_DIV 177
> > +#define CLKID_PWM_D_GATE 178
> > +#define CLKID_PWM_E_MUX 179
> > +#define CLKID_PWM_E_DIV 180
> > +#define CLKID_PWM_E_GATE 181
> > +#define CLKID_PWM_F_MUX 182
> > +#define CLKID_PWM_F_DIV 183
> > +#define CLKID_PWM_F_GATE 184
> > +#define CLKID_PWM_AO_A_MUX 185
> > +#define CLKID_PWM_AO_A_DIV 186
> > +#define CLKID_PWM_AO_A_GATE 187
> > +#define CLKID_PWM_AO_B_MUX 188
> > +#define CLKID_PWM_AO_B_DIV 189
> > +#define CLKID_PWM_AO_B_GATE 190
> > +#define CLKID_PWM_AO_C_MUX 191
> > +#define CLKID_PWM_AO_C_DIV 192
> > +#define CLKID_PWM_AO_C_GATE 193
> > +#define CLKID_PWM_AO_D_MUX 194
> > +#define CLKID_PWM_AO_D_DIV 195
> > +#define CLKID_PWM_AO_D_GATE 196
> > +#define CLKID_PWM_AO_E_MUX 197
> > +#define CLKID_PWM_AO_E_DIV 198
> > +#define CLKID_PWM_AO_E_GATE 199
> > +#define CLKID_PWM_AO_F_MUX 200
> > +#define CLKID_PWM_AO_F_DIV 201
> > +#define CLKID_PWM_AO_F_GATE 202
> > +#define CLKID_PWM_AO_G_MUX 203
> > +#define CLKID_PWM_AO_G_DIV 204
> > +#define CLKID_PWM_AO_G_GATE 205
> > +#define CLKID_PWM_AO_H_MUX 206
> > +#define CLKID_PWM_AO_H_DIV 207
> > +#define CLKID_PWM_AO_H_GATE 208
> > +#define CLKID_SPICC0_MUX 209
> > +#define CLKID_SPICC0_DIV 210
> > +#define CLKID_SPICC0_GATE 211
> > +#define CLKID_SPICC1_MUX 212
> > +#define CLKID_SPICC1_DIV 213
> > +#define CLKID_SPICC1_GATE 214
> > +#define CLKID_SPICC2_MUX 215
> > +#define CLKID_SPICC2_DIV 216
> > +#define CLKID_SPICC2_GATE 217
> > +#define CLKID_SPICC3_MUX 218
> > +#define CLKID_SPICC3_DIV 219
> > +#define CLKID_SPICC3_GATE 220
> > +#define CLKID_SPICC4_MUX 221
> > +#define CLKID_SPICC4_DIV 222
> > +#define CLKID_SPICC4_GATE 223
> > +#define CLKID_SPICC5_MUX 224
> > +#define CLKID_SPICC5_DIV 225
> > +#define CLKID_SPICC5_GATE 226
> > +#define CLKID_SD_EMMC_C_CLK_MUX 227
> > +#define CLKID_SD_EMMC_C_CLK_DIV 228
> > +#define CLKID_SD_EMMC_C_CLK 229
> > +#define CLKID_SD_EMMC_A_CLK_MUX 230
> > +#define CLKID_SD_EMMC_A_CLK_DIV 231
> > +#define CLKID_SD_EMMC_A_CLK 232
> > +#define CLKID_SD_EMMC_B_CLK_MUX 233
> > +#define CLKID_SD_EMMC_B_CLK_DIV 234
> > +#define CLKID_SD_EMMC_B_CLK 235
> > +#define CLKID_ETH_RMII_SEL 236
> > +#define CLKID_ETH_RMII_DIV 237
> > +#define CLKID_ETH_RMII 238
> > +#define CLKID_ETH_DIV8 239
> > +#define CLKID_ETH_125M 240
> > +#define CLKID_SARADC_MUX 241
> > +#define CLKID_SARADC_DIV 242
> > +#define CLKID_SARADC_GATE 243
> > +#define CLKID_GEN_MUX 244
> > +#define CLKID_GEN_DIV 245
> > +#define CLKID_GEN_GATE 246
> > +#define CLKID_DSPB_CLK_B_MUX 247
> > +#define CLKID_DSPB_CLK_B_DIV 248
> > +#define CLKID_DSPB_CLK_B_GATE 249
> > +#define CLKID_DSPB_CLK_A_MUX 250
> > +#define CLKID_DSPB_CLK_A_DIV 251
> > +#define CLKID_DSPB_CLK_A_GATE 252
> > +#define CLKID_DSPB_CLK 253
> > +#define CLKID_MIPI_ISP_MUX 254
> > +#define CLKID_MIPI_ISP_DIV 255
> > +#define CLKID_MIPI_ISP 256
> > +#define CLKID_MIPI_CSI_PHY_SEL0 257
> > +#define CLKID_MIPI_CSI_PHY_DIV0 258
> > +#define CLKID_MIPI_CSI_PHY0 259
> > +#define CLKID_MIPI_CSI_PHY_SEL1 260
> > +#define CLKID_MIPI_CSI_PHY_DIV1 261
> > +#define CLKID_MIPI_CSI_PHY1 262
> > +#define CLKID_MIPI_CSI_PHY_CLK 263
> > +#define CLKID_GDCCLK_0_MUX 264
> > +#define CLKID_GDCCLK_0_DIV 265
> > +#define CLKID_GDCCLK_0 266
> > +#define CLKID_GDCCLK_1_MUX 267
> > +#define CLKID_GDCCLK_1_DIV 268
> > +#define CLKID_GDCCLK_1 269
> > +#define CLKID_GDCCLK 270
> > +#define CLKID_GDC_CLK 271
> > +#define CLKID_DEWARPCLK_0_MUX 272
> > +#define CLKID_DEWARPCLK_0_DIV 273
> > +#define CLKID_DEWARPCLK_0 274
> > +#define CLKID_DEWARPCLK_1_MUX 275
> > +#define CLKID_DEWARPCLK_1_DIV 276
> > +#define CLKID_DEWARPCLK_1 277
> > +#define CLKID_DEWARPCLK 278
> > +#define CLKID_DEWARP_CLK 279
> > +#define CLKID_ANAKIN_0_MUX 280
> > +#define CLKID_ANAKIN_0_DIV 281
> > +#define CLKID_ANAKIN_0 282
> > +#define CLKID_ANAKIN_1_MUX 283
> > +#define CLKID_ANAKIN_1_DIV 284
> > +#define CLKID_ANAKIN_1 285
> > +#define CLKID_ANAKIN 286
> > +#define CLKID_ANAKIN_CLK 287
> > +#define CLKID_HDMITX_PRIF_MUX 288
> > +#define CLKID_HDMITX_PRIF_DIV 289
> > +#define CLKID_HDMITX_PRIF 290
> > +#define CLKID_HDMITX_200M_MUX 291
> > +#define CLKID_HDMITX_200M_DIV 292
> > +#define CLKID_HDMITX_200M 293
> > +#define CLKID_HDMITX_AUD_MUX 294
> > +#define CLKID_HDMITX_AUD_DIV 295
> > +#define CLKID_HDMITX_AUD 296
> > +#define CLKID_HDMIRX_2M_MUX 297
> > +#define CLKID_HDMIRX_2M_DIV 298
> > +#define CLKID_HDMIRX_2M 299
> > +#define CLKID_HDMIRX_5M_MUX 300
> > +#define CLKID_HDMIRX_5M_DIV 301
> > +#define CLKID_HDMIRX_5M 302
> > +#define CLKID_HDMIRX_CFG_MUX 303
> > +#define CLKID_HDMIRX_CFG_DIV 304
> > +#define CLKID_HDMIRX_CFG 305
> > +#define CLKID_HDMIRX_HDCP_MUX 306
> > +#define CLKID_HDMIRX_HDCP_DIV 307
> > +#define CLKID_HDMIRX_HDCP 308
> > +#define CLKID_HDMIRX_AUD_PLL_MUX 309
> > +#define CLKID_HDMIRX_AUD_PLL_DIV 310
> > +#define CLKID_HDMIRX_AUD_PLL 311
> > +#define CLKID_HDMIRX_ACR_MUX 312
> > +#define CLKID_HDMIRX_ACR_DIV 313
> > +#define CLKID_HDMIRX_ACR 314
> > +#define CLKID_HDMIRX_METER_MUX 315
> > +#define CLKID_HDMIRX_METER_DIV 316
> > +#define CLKID_HDMIRX_METER 317
> > +#define CLKID_DDR 318
> > +#define CLKID_DOS 319
> > +#define CLKID_ETHPHY 320
> > +#define CLKID_MALI 321
> > +#define CLKID_TS_A53 322
> > +#define CLKID_TS_A73 323
> > +#define CLKID_CEC 324
> > +#define CLKID_SD_EMMC_A 325
> > +#define CLKID_SD_EMMC_B 326
> > +#define CLKID_SD_EMMC_C 327
> > +#define CLKID_SMARTCARD 328
> > +#define CLKID_ACODEC 329
> > +#define CLKID_SPIFC 330
> > +#define CLKID_MSR_CLK 331
> > +#define CLKID_IR_CTRL 332
> > +#define CLKID_AUDIO 333
> > +#define CLKID_ETH 334
> > +#define CLKID_UART_A 335
> > +#define CLKID_UART_B 336
> > +#define CLKID_UART_C 337
> > +#define CLKID_UART_D 338
> > +#define CLKID_UART_E 339
> > +#define CLKID_AIFIFO 340
> > +#define CLKID_TS_DDR 341
> > +#define CLKID_TS_PLL 342
> > +#define CLKID_G2D 343
> > +#define CLKID_SPICC0 344
> > +#define CLKID_SPICC1 345
> > +#define CLKID_PCIE 346
> > +#define CLKID_USB 347
> > +#define CLKID_PCIE_PHY 348
> > +#define CLKID_I2C_M_A 349
> > +#define CLKID_I2C_M_B 350
> > +#define CLKID_I2C_M_C 351
> > +#define CLKID_I2C_M_D 352
> > +#define CLKID_I2C_M_E 353
> > +#define CLKID_I2C_M_F 354
> > +#define CLKID_HDMITX_APB 355
> > +#define CLKID_I2C_S_A 356
> > +#define CLKID_USB1_TO_DDR 357
> > +#define CLKID_AOCPU 358
> > +#define CLKID_MMC_APB 359
> > +#define CLKID_RSA 360
> > +#define CLKID_AUCPU 361
> > +#define CLKID_DSPA 362
> > +#define CLKID_VPU_INTR 363
> > +#define CLKID_SAR_ADC 364
> > +#define CLKID_GIC 365
> > +#define CLKID_PWM_AB 366
> > +#define CLKID_PWM_CD 367
> > +#define CLKID_PWM_EF 368
> > +#define CLKID_PWM_GH 369
> > +#define CLKID_PWM_AO_AB 370
> > +#define CLKID_MIPI_DSI_A 371
> > +#define CLKID_MIPI_DSI_B 372
> > +#define CLKID_GDC 373
> > +#define CLKID_DESWARP 374
> > +#define CLKID_AMPIPE_NAND 375
> > +#define CLKID_AMPIPE_ETH 376
> > +#define CLKID_AM2AXI0 377
> > +#define CLKID_AM2AXI1 378
> > +#define CLKID_AM2AXI2 379
> > +#define CLKID_PWM_AO_CD 380
> > +#define CLKID_PWM_AO_EF 381
> > +#define CLKID_PWM_AO_GH 382
> > +#define CLKID_TS_NNA 383
> > +#define CLKID_TS_GPU 384
> > +#define CLKID_TS_HEVC 385
> > +#define CLKID_DSPB 386
> > +#define CLKID_SPICC2 387
> > +#define CLKID_SPICC3 388
> > +#define CLKID_SPICC4 389
> > +#define CLKID_SPICC5 390
> > +#define CLKID_I2C_AO_A 391
> > +#define CLKID_I2C_AO_B 392
> > +#define CLKID_UART_F 393
> > +#define CLKID_MIPI_ISP_PCLK 394
> > +#define CLKID_HDMIRX_PCLK 395
> > +#define CLKID_PCLK_SYS_CPU_APB 396
> > +#define CLKID_A73PCLK_CPU_APB 397
> > +#define CLKID_TS_VPU 398
> > +
> > +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_T7_PERIPHERALS_CLKC_H */
> > diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
> > new file mode 100644
> > index 000000000000..89ee62069772
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
> > @@ -0,0 +1,69 @@
> > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> > +/*
> > + * Copyright (c) 2019 Amlogic Inc. All rights reserved.
> > + */
> > +
> > +#ifndef __T7_CLKC_H
> > +#define __T7_CLKC_H
> > +
> > +/*
> > + * CLKID index values
> > + */
> > +
> > +#define CLKID_FIXED_PLL_DCO 0
> > +#define CLKID_FIXED_PLL 1
> > +#define CLKID_SYS_PLL_DCO 2
> > +#define CLKID_SYS_PLL 3
> > +#define CLKID_FCLK_DIV2_DIV 4
> > +#define CLKID_FCLK_DIV2 5
> > +#define CLKID_FCLK_DIV3_DIV 6
> > +#define CLKID_FCLK_DIV3 7
> > +#define CLKID_FCLK_DIV4_DIV 8
> > +#define CLKID_FCLK_DIV4 9
> > +#define CLKID_FCLK_DIV5_DIV 10
> > +#define CLKID_FCLK_DIV5 11
> > +#define CLKID_FCLK_DIV7_DIV 12
> > +#define CLKID_FCLK_DIV7 13
> > +#define CLKID_FCLK_DIV2P5_DIV 14
> > +#define CLKID_FCLK_DIV2P5 15
> > +#define CLKID_GP0_PLL_DCO 16
> > +#define CLKID_GP0_PLL 17
> > +#define CLKID_GP1_PLL_DCO 18
> > +#define CLKID_GP1_PLL 19
> > +#define CLKID_SYS1_PLL_DCO 20
> > +#define CLKID_SYS1_PLL 21
> > +#define CLKID_MCLK_PLL_DCO 22
> > +#define CLKID_MCLK_PRE 23
> > +#define CLKID_MCLK_PLL 24
> > +#define CLKID_HIFI_PLL_DCO 25
> > +#define CLKID_HIFI_PLL 26
> > +#define CLKID_PCIE_PLL_DCO 27
> > +#define CLKID_PCIE_PLL_DCO_DIV2 28
> > +#define CLKID_PCIE_PLL_OD 29
> > +#define CLKID_PCIE_PLL 30
> > +#define CLKID_HDMI_PLL_DCO 31
> > +#define CLKID_HDMI_PLL_OD 32
> > +#define CLKID_HDMI_PLL 33
> > +#define CLKID_MPLL_50M_DIV 34
> > +#define CLKID_MPLL_50M 35
> > +#define CLKID_MPLL_PREDIV 36
> > +#define CLKID_MPLL0_DIV 37
> > +#define CLKID_MPLL0 38
> > +#define CLKID_MPLL1_DIV 39
> > +#define CLKID_MPLL1 40
> > +#define CLKID_MPLL2_DIV 41
> > +#define CLKID_MPLL2 42
> > +#define CLKID_MPLL3_DIV 43
> > +#define CLKID_MPLL3 44
> > +#define CLKID_PCIE_BGP 45
> > +#define CLKID_PCIE_HCSL 46
> > +#define CLKID_MCLK_0_SEL 47
> > +#define CLKID_MCLK_0_DIV2 48
> > +#define CLKID_MCLK_0_PRE 49
> > +#define CLKID_MCLK_0 50
> > +#define CLKID_MCLK_1_SEL 51
> > +#define CLKID_MCLK_1_DIV2 52
> > +#define CLKID_MCLK_1_PRE 53
> > +#define CLKID_MCLK_1 54
> > +
> > +#endif /* __T7_CLKC_H */
> > --
> > 2.44.0
> >
Hi,
I have been trying to port the MMC driver to the mainline, but this
kernel panic is occurring frequently.
It doesn't seem to be from my driver. Can anybody help?
0.355428] meson-gx-mmc fe08a000.sd: host probe success!
[ 0.355850] clk: Disabling unused clocks
[ 0.356032] PM: genpd: Disabling unused power domains
[ 0.356554] ALSA device list:
[ 0.356894] No soundcards found.
[ 0.359563] SError Interrupt on CPU1, code 0x00000000bf000002 -- SError
[ 0.359575] CPU: 1 PID: 76 Comm: kworker/1:1 Not tainted
6.8.0-09794-g261238a64e1f-dirty #38
[ 0.359585] Hardware name: Khadas vim4 (DT)
[ 0.359590] Workqueue: events_freezable mmc_rescan
[ 0.359611] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 0.359620] pc : meson_mmc_request+0x1d0/0x624
[ 0.359630] lr : __mmc_start_request+0x68/0x13c
[ 0.359641] sp : ffff800082ff3b70
[ 0.359644] x29: ffff800082ff3b70 x28: 0000000000000000 x27: ffff800082327000
[ 0.359655] x26: ffff0001011d3040 x25: 0000000000000000 x24: ffff000100030405
[ 0.359666] x23: ffff800082ff3d20 x22: ffff0001031b8000 x21: 000000008840a800
[ 0.359677] x20: 0000000000000000 x19: ffff0001031b8580 x18: 0000000000000020
[ 0.359688] x17: 0000000000000080 x16: fffffdffc378e008 x15: 0000000000000000
[ 0.359698] x14: ffff0001003ca280 x13: 0000000000000000 x12: ffff800082329dc8
[ 0.359709] x11: ffff000100cc3500 x10: 0000000000000a70 x9 : ffff800082ff3b70
[ 0.359719] x8 : ffff0001003cacd0 x7 : ffff00021ef51d40 x6 : ffff80019d3c6000
[ 0.359730] x5 : 0000000000000008 x4 : 0000000000500000 x3 : 0000000088400000
[ 0.359741] x2 : 0000000000000008 x1 : ffff80008287d000 x0 : ffff80008287d000
[ 0.359753] Kernel panic - not syncing: Asynchronous SError Interrupt
[ 0.359757] CPU: 1 PID: 76 Comm: kworker/1:1 Not tainted
6.8.0-09794-g261238a64e1f-dirty #38
[ 0.359765] Hardware name: Khadas vim4 (DT)
[ 0.359769] Workqueue: events_freezable mmc_rescan
[ 0.359780] Call trace:
[ 0.359784] dump_backtrace+0x94/0xec
[ 0.359798] show_stack+0x18/0x24
[ 0.359809] dump_stack_lvl+0x38/0x90
[ 0.359818] dump_stack+0x18/0x24
[ 0.359824] panic+0x388/0x3c8
[ 0.359834] nmi_panic+0x48/0x94
[ 0.359846] arm64_serror_panic+0x6c/0x78
[ 0.359853] do_serror+0x3c/0x78
[ 0.359860] el1h_64_error_handler+0x30/0x48
[ 0.359870] el1h_64_error+0x64/0x68
[ 0.359878] meson_mmc_request+0x1d0/0x624
[ 0.359886] __mmc_start_request+0x68/0x13c
[ 0.359897] mmc_start_request+0x84/0xac
[ 0.359906] mmc_wait_for_req+0x70/0x100
[ 0.359916] mmc_wait_for_cmd+0x64/0x9c
[ 0.359925] mmc_send_if_cond_pcie+0x88/0x120
[ 0.359936] mmc_rescan+0x22c/0x31c
[ 0.359946] process_one_work+0x150/0x294
[ 0.359957] worker_thread+0x304/0x408
[ 0.359968] kthread+0x118/0x11c
[ 0.359977] ret_from_fork+0x10/0x20
[ 0.359987] SMP: stopping secondary CPUs
[ 0.360066] Kernel Offset: disabled
[ 0.360068] CPU features: 0x0,00000060,d0080000,0200421b
[ 0.360074] Memory Limit: none
[ 0.388534] ---[ end Kernel panic - not syncing: Asynchronous
SError Interrupt ]---
^ permalink raw reply
* Re: [RFC PATCH 0/2] Add gpio-usb-c-connector compatible
From: Dmitry Baryshkov @ 2024-03-30 13:39 UTC (permalink / raw)
To: Krishna Kurapati PSSNV
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman,
Conor Dooley, Miquel Raynal, Guenter Roeck, Bjorn Helgaas,
Kyle Tso, Fabrice Gasnier, Heikki Krogerus, u.kleine-koenig,
AngeloGioacchino Del Regno, devicetree, linux-usb, linux-kernel,
quic_ppratap, quic_jackp
In-Reply-To: <6f2df222-36d4-468e-99a7-9c48fae85aa9@quicinc.com>
On Sat, 30 Mar 2024 at 11:13, Krishna Kurapati PSSNV
<quic_kriskura@quicinc.com> wrote:
> On 3/29/2024 6:23 PM, Dmitry Baryshkov wrote:
> > On Fri, 29 Mar 2024 at 09:20, Krishna Kurapati
> > <quic_kriskura@quicinc.com> wrote:
> >>
> >> QDU1000 IDP [1] has a Type-c connector and supports USB 3.0.
> >> However it relies on usb-conn-gpio driver to read the vbus and id
> >> gpio's and provide role switch. However the driver currently has
> >> only gpio-b-connector compatible present in ID table. Adding that
> >> in DT would mean that the device supports Type-B connector and not
> >> Type-c connector. Thanks to Dmitry Baryshkov for pointing it out [2].
> >
> > USB-B connector is pretty simple, it really has just an ID pin and
> > VBUS input, which translates to two GPIOs being routed from the
> > _connector_ itself.
> >
> > USB-C is much more complicated, it has two CC pins and a VBus power
> > pin. It is not enough just to measure CC pin levels. Moreover,
> > properly handling USB 3.0 inside a USB-C connector requires a separate
> > 'orientation' signal to tell the host which two lanes must be used for
> > the USB SS signals. Thus it is no longer possible to route just two
> > pins from the connector to the SoC.
> >
> > Having all that in mind, I suspect that you are not describing your
> > hardware properly. I suppose that you have a Type-C port controller /
> > redriver / switch, which handles CC lines communication and then
> > provides ID / VBUS signals to the host. In such a case, please
> > describe this TCPC in the DT file and use its compatible string
> > instead of "gpio-c-connector".
> >
>
> Hi Dmitry,
>
> My bad. I must have provided more details of the HW.
>
> I presume you are referring to addition of a connector node, type-c
> switch, pmic-glink and other remote endpoints like in other SoC's like
> SM8450/ SM8550/ SM8650.
>
> This HW is slightly different. It has a Uni Phy for Super speed and
> hence no DP.
This is fine and it's irrelevant for the USB-C.
> For orientation switching, on mobile SoC's, there is a provision for
> orientation gpio given in pmic-glink node and is handled in ucsi_glink
> driver. But on this version of HW, there is a USB-C Switch with its own
> firmware taking care of orientation switching. It takes 8 SS Lines and 2
> CC lines coming from connector as input and gives out 4 SS Lines (SS
> TX1/TX2 RX1/RX2) as output which go to the SoC. So orientation switch is
> done by the USB-C-switch in between and it automatically routes
> appropriate active SS Lane from connector to the SoC.
This is also fine. As I wrote, you _have_ the Type-C port controller.
So your DT file should be describing your hardware.
> As usual like in other targets, the DP and DM lines from type-c
> connector go to the SoC directly.
>
> To handle role switch, the VBUS and ID Pin connections are given to
> SoC as well. There is a vbus controller regulator present to provide
> vbus to connected peripherals in host mode.
>
> There is no PPM entity (ADSP in mobile SoC's) and no UCSI involved
> here. Hence we rely on usb-conn-gpio to read the vbus/id and switch
> roles accordingly.
This is also fine.
You confirmed my suspicions. You have an external Type-C switch which
handles orientation (and most likely PD or non-PD power negotiation)
for you. It has GPIO outputs, etc.
But it is not a part of the connector. Instead of adding the
"gpio-usb-c-connector", add proper compatible string (see, how this is
handled e.g. by the spidev - it is a generic driver, but it requires
hardware-specific compatibles).
Your hardware description should look like:
typec {
compatible = "your,switch";
id-gpios = <&gpio 1>;
vbus-gpios = <&gpio 2>;
vbus-supplies = <®-vbus>;
ports {
#address-cells = <1>;
#size-cells = <1>;
port@0 {
endpoint {
remote-endpoint = <&usb_dwc3_hs_out>;
};
};
port@1 {
endpoint {
remote-endpoint = <&usb_uni_phy_out>;
};
};
/* No SBU port */
};
};
Note, I haven't said anything regarding the driver. You can continue
using the usb-conn-gpio driver. Just add a compatible string for you
switch.
>
> Hope this answers the query as to why we wanted to use usb-conn-gpio
> and why we were trying to add a new compatible.
>
> Regards,
> Krishna,
>
> >>
> >> This series intends to add that compatible in driver and bindings
> >> so that it can be used in QDU1000 IDP DT.
> >>
> >> [1]: https://lore.kernel.org/all/20240319091020.15137-3-quic_kbajaj@quicinc.com/
> >> [2]: https://lore.kernel.org/all/CAA8EJprXPvji8TgZu1idH7y4GtHtD4VmQABFBcRt-9BQaCberg@mail.gmail.com/
> >>
> >> Krishna Kurapati (2):
> >> dt-bindings: connector: Add gpio-usb-c-connector compatible
> >> usb: common: usb-conn-gpio: Update ID table to add usb-c connector
> >>
> >> Documentation/devicetree/bindings/connector/usb-connector.yaml | 3 +++
> >> drivers/usb/common/usb-conn-gpio.c | 1 +
> >> 2 files changed, 4 insertions(+)
> >>
> >> --
> >> 2.34.1
> >>
> >
> >
> > --
> > With best wishes
> > Dmitry
--
With best wishes
Dmitry
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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Sat, 30 Mar 2024 15:39:08 +0200
Message-ID: <CAA8EJppa4hVBSenLgxc5MYxTfzPPf4exHvh8RWTP=p8mgB_RCw@mail.gmail.com>
Subject: Re: [RFC PATCH 0/2] Add gpio-usb-c-connector compatible
To: Krishna Kurapati PSSNV <quic_kriskura@quicinc.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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On Sat, 30 Mar 2024 at 11:13, Krishna Kurapati PSSNV
<quic_kriskura@quicinc.com> wrote:
> On 3/29/2024 6:23 PM, Dmitry Baryshkov wrote:
> > On Fri, 29 Mar 2024 at 09:20, Krishna Kurapati
> > <quic_kriskura@quicinc.com> wrote:
> >>
> >> QDU1000 IDP [1] has a Type-c connector and supports USB 3.0.
> >> However it relies on usb-conn-gpio driver to read the vbus and id
> >> gpio's and provide role switch. However the driver currently has
> >> only gpio-b-connector compatible present in ID table. Adding that
> >> in DT would mean that the device supports Type-B connector and not
> >> Type-c connector. Thanks to Dmitry Baryshkov for pointing it out [2].
> >
> > USB-B connector is pretty simple, it really has just an ID pin and
> > VBUS input, which translates to two GPIOs being routed from the
> > _connector_ itself.
> >
> > USB-C is much more complicated, it has two CC pins and a VBus power
> > pin. It is not enough just to measure CC pin levels. Moreover,
> > properly handling USB 3.0 inside a USB-C connector requires a separate
> > 'orientation' signal to tell the host which two lanes must be used for
> > the USB SS signals. Thus it is no longer possible to route just two
> > pins from the connector to the SoC.
> >
> > Having all that in mind, I suspect that you are not describing your
> > hardware properly. I suppose that you have a Type-C port controller /
> > redriver / switch, which handles CC lines communication and then
> > provides ID / VBUS signals to the host. In such a case, please
> > describe this TCPC in the DT file and use its compatible string
> > instead of "gpio-c-connector".
> >
>
> Hi Dmitry,
>
> My bad. I must have provided more details of the HW.
>
> I presume you are referring to addition of a connector node, type-c
> switch, pmic-glink and other remote endpoints like in other SoC's like
> SM8450/ SM8550/ SM8650.
>
> This HW is slightly different. It has a Uni Phy for Super speed and
> hence no DP.
This is fine and it's irrelevant for the USB-C.
> For orientation switching, on mobile SoC's, there is a provision for
> orientation gpio given in pmic-glink node and is handled in ucsi_glink
> driver. But on this version of HW, there is a USB-C Switch with its own
> firmware taking care of orientation switching. It takes 8 SS Lines and 2
> CC lines coming from connector as input and gives out 4 SS Lines (SS
> TX1/TX2 RX1/RX2) as output which go to the SoC. So orientation switch is
> done by the USB-C-switch in between and it automatically routes
> appropriate active SS Lane from connector to the SoC.
This is also fine. As I wrote, you _have_ the Type-C port controller.
So your DT file should be describing your hardware.
> As usual like in other targets, the DP and DM lines from type-c
> connector go to the SoC directly.
>
> To handle role switch, the VBUS and ID Pin connections are given to
> SoC as well. There is a vbus controller regulator present to provide
> vbus to connected peripherals in host mode.
>
> There is no PPM entity (ADSP in mobile SoC's) and no UCSI involved
> here. Hence we rely on usb-conn-gpio to read the vbus/id and switch
> roles accordingly.
This is also fine.
You confirmed my suspicions. You have an external Type-C switch which
handles orientation (and most likely PD or non-PD power negotiation)
for you. It has GPIO outputs, etc.
But it is not a part of the connector. Instead of adding the
"gpio-usb-c-connector", add proper compatible string (see, how this is
handled e.g. by the spidev - it is a generic driver, but it requires
hardware-specific compatibles).
Your hardware description should look like:
typec {
compatible = "your,switch";
id-gpios = <&gpio 1>;
vbus-gpios = <&gpio 2>;
vbus-supplies = <®-vbus>;
ports {
#address-cells = <1>;
#size-cells = <1>;
port@0 {
endpoint {
remote-endpoint = <&usb_dwc3_hs_out>;
};
};
port@1 {
endpoint {
remote-endpoint = <&usb_uni_phy_out>;
};
};
/* No SBU port */
};
};
Note, I haven't said anything regarding the driver. You can continue
using the usb-conn-gpio driver. Just add a compatible string for you
switch.
>
> Hope this answers the query as to why we wanted to use usb-conn-gpio
> and why we were trying to add a new compatible.
>
> Regards,
> Krishna,
>
> >>
> >> This series intends to add that compatible in driver and bindings
> >> so that it can be used in QDU1000 IDP DT.
> >>
> >> [1]: https://lore.kernel.org/all/20240319091020.15137-3-quic_kbajaj@quicinc.com/
> >> [2]: https://lore.kernel.org/all/CAA8EJprXPvji8TgZu1idH7y4GtHtD4VmQABFBcRt-9BQaCberg@mail.gmail.com/
> >>
> >> Krishna Kurapati (2):
> >> dt-bindings: connector: Add gpio-usb-c-connector compatible
> >> usb: common: usb-conn-gpio: Update ID table to add usb-c connector
> >>
> >> Documentation/devicetree/bindings/connector/usb-connector.yaml | 3 +++
> >> drivers/usb/common/usb-conn-gpio.c | 1 +
> >> 2 files changed, 4 insertions(+)
> >>
> >> --
> >> 2.34.1
> >>
> >
> >
> > --
> > With best wishes
> > Dmitry
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [RFC PATCH 0/2] Add gpio-usb-c-connector compatible
From: Krishna Kurapati PSSNV @ 2024-03-30 9:13 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman,
Conor Dooley, Miquel Raynal, Guenter Roeck, Bjorn Helgaas,
Kyle Tso, Fabrice Gasnier, Heikki Krogerus, u.kleine-koenig,
AngeloGioacchino Del Regno, devicetree, linux-usb, linux-kernel,
quic_ppratap, quic_jackp
In-Reply-To: <CAA8EJpqx+VFW8z6oG=+pnhPN97Q3R6z+ygf85Uspve-9syQsUw@mail.gmail.com>
On 3/29/2024 6:23 PM, Dmitry Baryshkov wrote:
> On Fri, 29 Mar 2024 at 09:20, Krishna Kurapati
> <quic_kriskura@quicinc.com> wrote:
>>
>> QDU1000 IDP [1] has a Type-c connector and supports USB 3.0.
>> However it relies on usb-conn-gpio driver to read the vbus and id
>> gpio's and provide role switch. However the driver currently has
>> only gpio-b-connector compatible present in ID table. Adding that
>> in DT would mean that the device supports Type-B connector and not
>> Type-c connector. Thanks to Dmitry Baryshkov for pointing it out [2].
>
> USB-B connector is pretty simple, it really has just an ID pin and
> VBUS input, which translates to two GPIOs being routed from the
> _connector_ itself.
>
> USB-C is much more complicated, it has two CC pins and a VBus power
> pin. It is not enough just to measure CC pin levels. Moreover,
> properly handling USB 3.0 inside a USB-C connector requires a separate
> 'orientation' signal to tell the host which two lanes must be used for
> the USB SS signals. Thus it is no longer possible to route just two
> pins from the connector to the SoC.
>
> Having all that in mind, I suspect that you are not describing your
> hardware properly. I suppose that you have a Type-C port controller /
> redriver / switch, which handles CC lines communication and then
> provides ID / VBUS signals to the host. In such a case, please
> describe this TCPC in the DT file and use its compatible string
> instead of "gpio-c-connector".
>
Hi Dmitry,
My bad. I must have provided more details of the HW.
I presume you are referring to addition of a connector node, type-c
switch, pmic-glink and other remote endpoints like in other SoC's like
SM8450/ SM8550/ SM8650.
This HW is slightly different. It has a Uni Phy for Super speed and
hence no DP.
For orientation switching, on mobile SoC's, there is a provision for
orientation gpio given in pmic-glink node and is handled in ucsi_glink
driver. But on this version of HW, there is a USB-C Switch with its own
firmware taking care of orientation switching. It takes 8 SS Lines and 2
CC lines coming from connector as input and gives out 4 SS Lines (SS
TX1/TX2 RX1/RX2) as output which go to the SoC. So orientation switch is
done by the USB-C-switch in between and it automatically routes
appropriate active SS Lane from connector to the SoC.
As usual like in other targets, the DP and DM lines from type-c
connector go to the SoC directly.
To handle role switch, the VBUS and ID Pin connections are given to
SoC as well. There is a vbus controller regulator present to provide
vbus to connected peripherals in host mode.
There is no PPM entity (ADSP in mobile SoC's) and no UCSI involved
here. Hence we rely on usb-conn-gpio to read the vbus/id and switch
roles accordingly.
Hope this answers the query as to why we wanted to use usb-conn-gpio
and why we were trying to add a new compatible.
Regards,
Krishna,
>>
>> This series intends to add that compatible in driver and bindings
>> so that it can be used in QDU1000 IDP DT.
>>
>> [1]: https://lore.kernel.org/all/20240319091020.15137-3-quic_kbajaj@quicinc.com/
>> [2]: https://lore.kernel.org/all/CAA8EJprXPvji8TgZu1idH7y4GtHtD4VmQABFBcRt-9BQaCberg@mail.gmail.com/
>>
>> Krishna Kurapati (2):
>> dt-bindings: connector: Add gpio-usb-c-connector compatible
>> usb: common: usb-conn-gpio: Update ID table to add usb-c connector
>>
>> Documentation/devicetree/bindings/connector/usb-connector.yaml | 3 +++
>> drivers/usb/common/usb-conn-gpio.c | 1 +
>> 2 files changed, 4 insertions(+)
>>
>> --
>> 2.34.1
>>
>
>
> --
> With best wishes
> Dmitry
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Subject: Re: [RFC PATCH 0/2] Add gpio-usb-c-connector compatible
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
CC: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski+dt@linaro.org>,
Greg Kroah-Hartman
<gregkh@linuxfoundation.org>,
Conor Dooley <conor+dt@kernel.org>,
"Miquel
Raynal" <miquel.raynal@bootlin.com>,
Guenter Roeck <linux@roeck-us.net>,
"Bjorn Helgaas" <bhelgaas@google.com>, Kyle Tso <kyletso@google.com>,
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Heikki Krogerus
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<devicetree@vger.kernel.org>, <linux-usb@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <quic_ppratap@quicinc.com>,
<quic_jackp@quicinc.com>
References: <20240329071948.3101882-1-quic_kriskura@quicinc.com>
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From: Krishna Kurapati PSSNV <quic_kriskura@quicinc.com>
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On 3/29/2024 6:23 PM, Dmitry Baryshkov wrote:
> On Fri, 29 Mar 2024 at 09:20, Krishna Kurapati
> <quic_kriskura@quicinc.com> wrote:
>>
>> QDU1000 IDP [1] has a Type-c connector and supports USB 3.0.
>> However it relies on usb-conn-gpio driver to read the vbus and id
>> gpio's and provide role switch. However the driver currently has
>> only gpio-b-connector compatible present in ID table. Adding that
>> in DT would mean that the device supports Type-B connector and not
>> Type-c connector. Thanks to Dmitry Baryshkov for pointing it out [2].
>
> USB-B connector is pretty simple, it really has just an ID pin and
> VBUS input, which translates to two GPIOs being routed from the
> _connector_ itself.
>
> USB-C is much more complicated, it has two CC pins and a VBus power
> pin. It is not enough just to measure CC pin levels. Moreover,
> properly handling USB 3.0 inside a USB-C connector requires a separate
> 'orientation' signal to tell the host which two lanes must be used for
> the USB SS signals. Thus it is no longer possible to route just two
> pins from the connector to the SoC.
>
> Having all that in mind, I suspect that you are not describing your
> hardware properly. I suppose that you have a Type-C port controller /
> redriver / switch, which handles CC lines communication and then
> provides ID / VBUS signals to the host. In such a case, please
> describe this TCPC in the DT file and use its compatible string
> instead of "gpio-c-connector".
>
Hi Dmitry,
My bad. I must have provided more details of the HW.
I presume you are referring to addition of a connector node, type-c
switch, pmic-glink and other remote endpoints like in other SoC's like
SM8450/ SM8550/ SM8650.
This HW is slightly different. It has a Uni Phy for Super speed and
hence no DP.
For orientation switching, on mobile SoC's, there is a provision for
orientation gpio given in pmic-glink node and is handled in ucsi_glink
driver. But on this version of HW, there is a USB-C Switch with its own
firmware taking care of orientation switching. It takes 8 SS Lines and 2
CC lines coming from connector as input and gives out 4 SS Lines (SS
TX1/TX2 RX1/RX2) as output which go to the SoC. So orientation switch is
done by the USB-C-switch in between and it automatically routes
appropriate active SS Lane from connector to the SoC.
As usual like in other targets, the DP and DM lines from type-c
connector go to the SoC directly.
To handle role switch, the VBUS and ID Pin connections are given to
SoC as well. There is a vbus controller regulator present to provide
vbus to connected peripherals in host mode.
There is no PPM entity (ADSP in mobile SoC's) and no UCSI involved
here. Hence we rely on usb-conn-gpio to read the vbus/id and switch
roles accordingly.
Hope this answers the query as to why we wanted to use usb-conn-gpio
and why we were trying to add a new compatible.
Regards,
Krishna,
>>
>> This series intends to add that compatible in driver and bindings
>> so that it can be used in QDU1000 IDP DT.
>>
>> [1]: https://lore.kernel.org/all/20240319091020.15137-3-quic_kbajaj@quicinc.com/
>> [2]: https://lore.kernel.org/all/CAA8EJprXPvji8TgZu1idH7y4GtHtD4VmQABFBcRt-9BQaCberg@mail.gmail.com/
>>
>> Krishna Kurapati (2):
>> dt-bindings: connector: Add gpio-usb-c-connector compatible
>> usb: common: usb-conn-gpio: Update ID table to add usb-c connector
>>
>> Documentation/devicetree/bindings/connector/usb-connector.yaml | 3 +++
>> drivers/usb/common/usb-conn-gpio.c | 1 +
>> 2 files changed, 4 insertions(+)
>>
>> --
>> 2.34.1
>>
>
>
> --
> With best wishes
> Dmitry
^ permalink raw reply
* Re: [RFC PATCH 0/2] Add gpio-usb-c-connector compatible
From: Krishna Kurapati PSSNV @ 2024-03-30 13:45 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Herring, Krzysztof Kozlowski, Greg Kroah-Hartman,
Conor Dooley, Miquel Raynal, Guenter Roeck, Bjorn Helgaas,
Kyle Tso, Fabrice Gasnier, Heikki Krogerus, u.kleine-koenig,
AngeloGioacchino Del Regno, devicetree, linux-usb, linux-kernel,
quic_ppratap, quic_jackp
In-Reply-To: <CAA8EJppa4hVBSenLgxc5MYxTfzPPf4exHvh8RWTP=p8mgB_RCw@mail.gmail.com>
On 3/30/2024 7:09 PM, Dmitry Baryshkov wrote:
> On Sat, 30 Mar 2024 at 11:13, Krishna Kurapati PSSNV
> <quic_kriskura@quicinc.com> wrote:
>> On 3/29/2024 6:23 PM, Dmitry Baryshkov wrote:
>>> On Fri, 29 Mar 2024 at 09:20, Krishna Kurapati
>>> <quic_kriskura@quicinc.com> wrote:
>>>>
>>>> QDU1000 IDP [1] has a Type-c connector and supports USB 3.0.
>>>> However it relies on usb-conn-gpio driver to read the vbus and id
>>>> gpio's and provide role switch. However the driver currently has
>>>> only gpio-b-connector compatible present in ID table. Adding that
>>>> in DT would mean that the device supports Type-B connector and not
>>>> Type-c connector. Thanks to Dmitry Baryshkov for pointing it out [2].
>>>
>>> USB-B connector is pretty simple, it really has just an ID pin and
>>> VBUS input, which translates to two GPIOs being routed from the
>>> _connector_ itself.
>>>
>>> USB-C is much more complicated, it has two CC pins and a VBus power
>>> pin. It is not enough just to measure CC pin levels. Moreover,
>>> properly handling USB 3.0 inside a USB-C connector requires a separate
>>> 'orientation' signal to tell the host which two lanes must be used for
>>> the USB SS signals. Thus it is no longer possible to route just two
>>> pins from the connector to the SoC.
>>>
>>> Having all that in mind, I suspect that you are not describing your
>>> hardware properly. I suppose that you have a Type-C port controller /
>>> redriver / switch, which handles CC lines communication and then
>>> provides ID / VBUS signals to the host. In such a case, please
>>> describe this TCPC in the DT file and use its compatible string
>>> instead of "gpio-c-connector".
>>>
>>
>> Hi Dmitry,
>>
>> My bad. I must have provided more details of the HW.
>>
>> I presume you are referring to addition of a connector node, type-c
>> switch, pmic-glink and other remote endpoints like in other SoC's like
>> SM8450/ SM8550/ SM8650.
>>
>> This HW is slightly different. It has a Uni Phy for Super speed and
>> hence no DP.
>
> This is fine and it's irrelevant for the USB-C.
>
>> For orientation switching, on mobile SoC's, there is a provision for
>> orientation gpio given in pmic-glink node and is handled in ucsi_glink
>> driver. But on this version of HW, there is a USB-C Switch with its own
>> firmware taking care of orientation switching. It takes 8 SS Lines and 2
>> CC lines coming from connector as input and gives out 4 SS Lines (SS
>> TX1/TX2 RX1/RX2) as output which go to the SoC. So orientation switch is
>> done by the USB-C-switch in between and it automatically routes
>> appropriate active SS Lane from connector to the SoC.
>
> This is also fine. As I wrote, you _have_ the Type-C port controller.
> So your DT file should be describing your hardware.
>
>> As usual like in other targets, the DP and DM lines from type-c
>> connector go to the SoC directly.
>>
>> To handle role switch, the VBUS and ID Pin connections are given to
>> SoC as well. There is a vbus controller regulator present to provide
>> vbus to connected peripherals in host mode.
>>
>> There is no PPM entity (ADSP in mobile SoC's) and no UCSI involved
>> here. Hence we rely on usb-conn-gpio to read the vbus/id and switch
>> roles accordingly.
>
> This is also fine.
>
> You confirmed my suspicions. You have an external Type-C switch which
> handles orientation (and most likely PD or non-PD power negotiation)
> for you. It has GPIO outputs, etc.
>
> But it is not a part of the connector. Instead of adding the
> "gpio-usb-c-connector", add proper compatible string (see, how this is
> handled e.g. by the spidev - it is a generic driver, but it requires
> hardware-specific compatibles).
> Your hardware description should look like:
>
> typec {
> compatible = "your,switch";
> id-gpios = <&gpio 1>;
> vbus-gpios = <&gpio 2>;
> vbus-supplies = <®-vbus>;
>
> ports {
> #address-cells = <1>;
> #size-cells = <1>;
> port@0 {
> endpoint {
> remote-endpoint = <&usb_dwc3_hs_out>;
> };
> };
> port@1 {
> endpoint {
> remote-endpoint = <&usb_uni_phy_out>;
> };
> };
> /* No SBU port */
> };
> };
> > Note, I haven't said anything regarding the driver. You can continue
> using the usb-conn-gpio driver. Just add a compatible string for you
> switch.
>
Got it. So the "usb_conn_gpio: usb-conn-gpio" in [1] to be replaced
with something like a "typec- " naming convention and add a new
compatible to gpio-conn (something specific to qcom-qdu) and use it in
the new DT node.
Thanks for the suggestion. Is it fine if it put the whole of the above
text in v2 and push it for getting a new compatible added to connector
binding and usb-conn driver and then send v3 of DT changes or mix this
series with the DT series ?
[1]:
https://lore.kernel.org/all/20240319091020.15137-3-quic_kbajaj@quicinc.com/
Thanks,
Krishna,
>>
>> Hope this answers the query as to why we wanted to use usb-conn-gpio
>> and why we were trying to add a new compatible.
>>
>> Regards,
>> Krishna,
>>
>>>>
>>>> This series intends to add that compatible in driver and bindings
>>>> so that it can be used in QDU1000 IDP DT.
>>>>
>>>> [1]: https://lore.kernel.org/all/20240319091020.15137-3-quic_kbajaj@quicinc.com/
>>>> [2]: https://lore.kernel.org/all/CAA8EJprXPvji8TgZu1idH7y4GtHtD4VmQABFBcRt-9BQaCberg@mail.gmail.com/
>>>>
>>>> Krishna Kurapati (2):
>>>> dt-bindings: connector: Add gpio-usb-c-connector compatible
>>>> usb: common: usb-conn-gpio: Update ID table to add usb-c connector
>>>>
>>>> Documentation/devicetree/bindings/connector/usb-connector.yaml | 3 +++
>>>> drivers/usb/common/usb-conn-gpio.c | 1 +
>>>> 2 files changed, 4 insertions(+)
>>>>
>>>> --
>>>> 2.34.1
>>>>
>>>
>>>
>>> --
>>> With best wishes
>>> Dmitry
>
>
>
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Subject: Re: [RFC PATCH 0/2] Add gpio-usb-c-connector compatible
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
CC: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski
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On 3/30/2024 7:09 PM, Dmitry Baryshkov wrote:
> On Sat, 30 Mar 2024 at 11:13, Krishna Kurapati PSSNV
> <quic_kriskura@quicinc.com> wrote:
>> On 3/29/2024 6:23 PM, Dmitry Baryshkov wrote:
>>> On Fri, 29 Mar 2024 at 09:20, Krishna Kurapati
>>> <quic_kriskura@quicinc.com> wrote:
>>>>
>>>> QDU1000 IDP [1] has a Type-c connector and supports USB 3.0.
>>>> However it relies on usb-conn-gpio driver to read the vbus and id
>>>> gpio's and provide role switch. However the driver currently has
>>>> only gpio-b-connector compatible present in ID table. Adding that
>>>> in DT would mean that the device supports Type-B connector and not
>>>> Type-c connector. Thanks to Dmitry Baryshkov for pointing it out [2].
>>>
>>> USB-B connector is pretty simple, it really has just an ID pin and
>>> VBUS input, which translates to two GPIOs being routed from the
>>> _connector_ itself.
>>>
>>> USB-C is much more complicated, it has two CC pins and a VBus power
>>> pin. It is not enough just to measure CC pin levels. Moreover,
>>> properly handling USB 3.0 inside a USB-C connector requires a separate
>>> 'orientation' signal to tell the host which two lanes must be used for
>>> the USB SS signals. Thus it is no longer possible to route just two
>>> pins from the connector to the SoC.
>>>
>>> Having all that in mind, I suspect that you are not describing your
>>> hardware properly. I suppose that you have a Type-C port controller /
>>> redriver / switch, which handles CC lines communication and then
>>> provides ID / VBUS signals to the host. In such a case, please
>>> describe this TCPC in the DT file and use its compatible string
>>> instead of "gpio-c-connector".
>>>
>>
>> Hi Dmitry,
>>
>> My bad. I must have provided more details of the HW.
>>
>> I presume you are referring to addition of a connector node, type-c
>> switch, pmic-glink and other remote endpoints like in other SoC's like
>> SM8450/ SM8550/ SM8650.
>>
>> This HW is slightly different. It has a Uni Phy for Super speed and
>> hence no DP.
>
> This is fine and it's irrelevant for the USB-C.
>
>> For orientation switching, on mobile SoC's, there is a provision for
>> orientation gpio given in pmic-glink node and is handled in ucsi_glink
>> driver. But on this version of HW, there is a USB-C Switch with its own
>> firmware taking care of orientation switching. It takes 8 SS Lines and 2
>> CC lines coming from connector as input and gives out 4 SS Lines (SS
>> TX1/TX2 RX1/RX2) as output which go to the SoC. So orientation switch is
>> done by the USB-C-switch in between and it automatically routes
>> appropriate active SS Lane from connector to the SoC.
>
> This is also fine. As I wrote, you _have_ the Type-C port controller.
> So your DT file should be describing your hardware.
>
>> As usual like in other targets, the DP and DM lines from type-c
>> connector go to the SoC directly.
>>
>> To handle role switch, the VBUS and ID Pin connections are given to
>> SoC as well. There is a vbus controller regulator present to provide
>> vbus to connected peripherals in host mode.
>>
>> There is no PPM entity (ADSP in mobile SoC's) and no UCSI involved
>> here. Hence we rely on usb-conn-gpio to read the vbus/id and switch
>> roles accordingly.
>
> This is also fine.
>
> You confirmed my suspicions. You have an external Type-C switch which
> handles orientation (and most likely PD or non-PD power negotiation)
> for you. It has GPIO outputs, etc.
>
> But it is not a part of the connector. Instead of adding the
> "gpio-usb-c-connector", add proper compatible string (see, how this is
> handled e.g. by the spidev - it is a generic driver, but it requires
> hardware-specific compatibles).
> Your hardware description should look like:
>
> typec {
> compatible = "your,switch";
> id-gpios = <&gpio 1>;
> vbus-gpios = <&gpio 2>;
> vbus-supplies = <®-vbus>;
>
> ports {
> #address-cells = <1>;
> #size-cells = <1>;
> port@0 {
> endpoint {
> remote-endpoint = <&usb_dwc3_hs_out>;
> };
> };
> port@1 {
> endpoint {
> remote-endpoint = <&usb_uni_phy_out>;
> };
> };
> /* No SBU port */
> };
> };
> > Note, I haven't said anything regarding the driver. You can continue
> using the usb-conn-gpio driver. Just add a compatible string for you
> switch.
>
Got it. So the "usb_conn_gpio: usb-conn-gpio" in [1] to be replaced
with something like a "typec- " naming convention and add a new
compatible to gpio-conn (something specific to qcom-qdu) and use it in
the new DT node.
Thanks for the suggestion. Is it fine if it put the whole of the above
text in v2 and push it for getting a new compatible added to connector
binding and usb-conn driver and then send v3 of DT changes or mix this
series with the DT series ?
[1]:
https://lore.kernel.org/all/20240319091020.15137-3-quic_kbajaj@quicinc.com/
Thanks,
Krishna,
>>
>> Hope this answers the query as to why we wanted to use usb-conn-gpio
>> and why we were trying to add a new compatible.
>>
>> Regards,
>> Krishna,
>>
>>>>
>>>> This series intends to add that compatible in driver and bindings
>>>> so that it can be used in QDU1000 IDP DT.
>>>>
>>>> [1]: https://lore.kernel.org/all/20240319091020.15137-3-quic_kbajaj@quicinc.com/
>>>> [2]: https://lore.kernel.org/all/CAA8EJprXPvji8TgZu1idH7y4GtHtD4VmQABFBcRt-9BQaCberg@mail.gmail.com/
>>>>
>>>> Krishna Kurapati (2):
>>>> dt-bindings: connector: Add gpio-usb-c-connector compatible
>>>> usb: common: usb-conn-gpio: Update ID table to add usb-c connector
>>>>
>>>> Documentation/devicetree/bindings/connector/usb-connector.yaml | 3 +++
>>>> drivers/usb/common/usb-conn-gpio.c | 1 +
>>>> 2 files changed, 4 insertions(+)
>>>>
>>>> --
>>>> 2.34.1
>>>>
>>>
>>>
>>> --
>>> With best wishes
>>> Dmitry
>
>
>
^ permalink raw reply
* [PATCH v2] dt-bindings: usb: qcom,pmic-typec: update example to follow connector schema
From: Dmitry Baryshkov @ 2024-03-30 22:21 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Bryan O'Donoghue,
Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-usb, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
Update Qualcomm PMIC Type-C examples to follow the USB-C connector
schema. The USB-C connector should have three ports (USB HS @0,
SSTX/RX @1 and SBU @2 lanes). Reorder ports accordingly and add SBU port
connected to the SBU mux (e.g. FSA4480).
Fixes: 00bb478b829e ("dt-bindings: usb: Add Qualcomm PMIC Type-C")
Reported-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Update examples to follow usb-c-connector schema wrt. ports definitions.
---
Changes in v2:
- Dropped patch removing the role-switching port. We do not use it, but
it can become useful by other designs.
- Link to v1: https://lore.kernel.org/r/20240322-typec-fix-example-v1-0-6b01c347419e@linaro.org
---
.../devicetree/bindings/usb/qcom,pmic-typec.yaml | 34 +++++++++++++++++-----
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml b/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml
index d9694570c419..fe757619e535 100644
--- a/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml
@@ -192,15 +192,22 @@ examples:
port@0 {
reg = <0>;
- pmic_typec_mux_out: endpoint {
- remote-endpoint = <&usb_phy_typec_mux_in>;
+ pmic_typec_hs_in: endpoint {
+ remote-endpoint = <&usb_hs_out>;
};
};
port@1 {
reg = <1>;
- pmic_typec_role_switch_out: endpoint {
- remote-endpoint = <&usb_role_switch_in>;
+ pmic_typec_ss_in: endpoint {
+ remote-endpoint = <&usb_phy_typec_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ pmic_typec_sbu: endpoint {
+ remote-endpoint = <&usb_mux_sbu>;
};
};
};
@@ -212,8 +219,8 @@ examples:
dr_mode = "otg";
usb-role-switch;
port {
- usb_role_switch_in: endpoint {
- remote-endpoint = <&pmic_typec_role_switch_out>;
+ usb_hs_out: endpoint {
+ remote-endpoint = <&pmic_typec_hs_in>;
};
};
};
@@ -221,8 +228,19 @@ examples:
usb-phy {
orientation-switch;
port {
- usb_phy_typec_mux_in: endpoint {
- remote-endpoint = <&pmic_typec_mux_out>;
+ usb_phy_typec_ss_out: endpoint {
+ remote-endpoint = <&pmic_typec_ss_in>;
+ };
+ };
+ };
+
+ usb-mux {
+ orientation-switch;
+ mode-switch;
+
+ port {
+ usb_mux_sbu: endpoint {
+ remote-endpoint = <&pmic_typec_sbu>;
};
};
};
---
base-commit: 13ee4a7161b6fd938aef6688ff43b163f6d83e37
change-id: 20240322-typec-fix-example-3d9b1eca853d
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Sun, 31 Mar 2024 00:21:15 +0200
Subject: [PATCH v2] dt-bindings: usb: qcom,pmic-typec: update example to
follow connector schema
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To: Bjorn Andersson <andersson@kernel.org>,
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Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
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Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Luca Weiss <luca.weiss@fairphone.com>,
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Update Qualcomm PMIC Type-C examples to follow the USB-C connector
schema. The USB-C connector should have three ports (USB HS @0,
SSTX/RX @1 and SBU @2 lanes). Reorder ports accordingly and add SBU port
connected to the SBU mux (e.g. FSA4480).
Fixes: 00bb478b829e ("dt-bindings: usb: Add Qualcomm PMIC Type-C")
Reported-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Update examples to follow usb-c-connector schema wrt. ports definitions.
---
Changes in v2:
- Dropped patch removing the role-switching port. We do not use it, but
it can become useful by other designs.
- Link to v1: https://lore.kernel.org/r/20240322-typec-fix-example-v1-0-6b01c347419e@linaro.org
---
.../devicetree/bindings/usb/qcom,pmic-typec.yaml | 34 +++++++++++++++++-----
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml b/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml
index d9694570c419..fe757619e535 100644
--- a/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml
@@ -192,15 +192,22 @@ examples:
port@0 {
reg = <0>;
- pmic_typec_mux_out: endpoint {
- remote-endpoint = <&usb_phy_typec_mux_in>;
+ pmic_typec_hs_in: endpoint {
+ remote-endpoint = <&usb_hs_out>;
};
};
port@1 {
reg = <1>;
- pmic_typec_role_switch_out: endpoint {
- remote-endpoint = <&usb_role_switch_in>;
+ pmic_typec_ss_in: endpoint {
+ remote-endpoint = <&usb_phy_typec_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ pmic_typec_sbu: endpoint {
+ remote-endpoint = <&usb_mux_sbu>;
};
};
};
@@ -212,8 +219,8 @@ examples:
dr_mode = "otg";
usb-role-switch;
port {
- usb_role_switch_in: endpoint {
- remote-endpoint = <&pmic_typec_role_switch_out>;
+ usb_hs_out: endpoint {
+ remote-endpoint = <&pmic_typec_hs_in>;
};
};
};
@@ -221,8 +228,19 @@ examples:
usb-phy {
orientation-switch;
port {
- usb_phy_typec_mux_in: endpoint {
- remote-endpoint = <&pmic_typec_mux_out>;
+ usb_phy_typec_ss_out: endpoint {
+ remote-endpoint = <&pmic_typec_ss_in>;
+ };
+ };
+ };
+
+ usb-mux {
+ orientation-switch;
+ mode-switch;
+
+ port {
+ usb_mux_sbu: endpoint {
+ remote-endpoint = <&pmic_typec_sbu>;
};
};
};
---
base-commit: 13ee4a7161b6fd938aef6688ff43b163f6d83e37
change-id: 20240322-typec-fix-example-3d9b1eca853d
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
^ permalink raw reply related
* [net-next,v2] dt-bindings: net: renesas,ethertsn: Create child-node for MDIO bus
From: Niklas Söderlund @ 2024-03-30 13:12 UTC (permalink / raw)
To: Sergey Shtylyov, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, netdev, devicetree
Cc: linux-renesas-soc, Niklas Söderlund, Rob Herring
The bindings for Renesas Ethernet TSN was just merged in v6.9 and the
design for the bindings followed that of other Renesas Ethernet drivers
and thus did not force a child-node for the MDIO bus. As there
are no upstream drivers or users of this binding yet take the
opportunity to correct this and force the usage of a child-node for the
MDIO bus.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Rob Herring <robh@kernel.org>
---
* Changes since v1
- Expand on history in commit message.
Hello,
The Ethernet TSN driver is still in review and have not been merged and
no usage of the bindings are merged either. So while this breaks the
binding it effects no one. So we can correct this mistake without
breaking any use-cases before we need to support any backward
compatibility.
---
.../bindings/net/renesas,ethertsn.yaml | 33 ++++++++-----------
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/renesas,ethertsn.yaml b/Documentation/devicetree/bindings/net/renesas,ethertsn.yaml
index ea35d19be829..b4680a1d0a06 100644
--- a/Documentation/devicetree/bindings/net/renesas,ethertsn.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,ethertsn.yaml
@@ -71,16 +71,8 @@ properties:
enum: [0, 2000]
default: 0
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
-
-patternProperties:
- "^ethernet-phy@[0-9a-f]$":
- type: object
- $ref: ethernet-phy.yaml#
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
required:
@@ -94,8 +86,7 @@ required:
- resets
- phy-mode
- phy-handle
- - '#address-cells'
- - '#size-cells'
+ - mdio
additionalProperties: false
@@ -122,14 +113,18 @@ examples:
tx-internal-delay-ps = <2000>;
phy-handle = <&phy3>;
- #address-cells = <1>;
- #size-cells = <0>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
- phy3: ethernet-phy@3 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0>;
- interrupt-parent = <&gpio4>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+ reset-post-delay-us = <4000>;
+
+ phy3: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ };
};
};
--
2.44.0
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From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= <niklas.soderlund+renesas@ragnatech.se>
To: Sergey Shtylyov <s.shtylyov@omp.ru>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
netdev@vger.kernel.org,
devicetree@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org,
=?UTF-8?q?Niklas=20S=C3=B6derlund?= <niklas.soderlund+renesas@ragnatech.se>,
Rob Herring <robh@kernel.org>
Subject: [net-next,v2] dt-bindings: net: renesas,ethertsn: Create child-node for MDIO bus
Date: Sat, 30 Mar 2024 14:12:28 +0100
Message-ID: <20240330131228.1541227-1-niklas.soderlund+renesas@ragnatech.se>
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The bindings for Renesas Ethernet TSN was just merged in v6.9 and the
design for the bindings followed that of other Renesas Ethernet drivers
and thus did not force a child-node for the MDIO bus. As there
are no upstream drivers or users of this binding yet take the
opportunity to correct this and force the usage of a child-node for the
MDIO bus.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Rob Herring <robh@kernel.org>
---
* Changes since v1
- Expand on history in commit message.
Hello,
The Ethernet TSN driver is still in review and have not been merged and
no usage of the bindings are merged either. So while this breaks the
binding it effects no one. So we can correct this mistake without
breaking any use-cases before we need to support any backward
compatibility.
---
.../bindings/net/renesas,ethertsn.yaml | 33 ++++++++-----------
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/renesas,ethertsn.yaml b/Documentation/devicetree/bindings/net/renesas,ethertsn.yaml
index ea35d19be829..b4680a1d0a06 100644
--- a/Documentation/devicetree/bindings/net/renesas,ethertsn.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,ethertsn.yaml
@@ -71,16 +71,8 @@ properties:
enum: [0, 2000]
default: 0
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
-
-patternProperties:
- "^ethernet-phy@[0-9a-f]$":
- type: object
- $ref: ethernet-phy.yaml#
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
required:
@@ -94,8 +86,7 @@ required:
- resets
- phy-mode
- phy-handle
- - '#address-cells'
- - '#size-cells'
+ - mdio
additionalProperties: false
@@ -122,14 +113,18 @@ examples:
tx-internal-delay-ps = <2000>;
phy-handle = <&phy3>;
- #address-cells = <1>;
- #size-cells = <0>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
- phy3: ethernet-phy@3 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0>;
- interrupt-parent = <&gpio4>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+ reset-post-delay-us = <4000>;
+
+ phy3: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ };
};
};
--
2.44.0
^ permalink raw reply related
* Re: [PATCH v6 0/1] Add property in dwmac-stm32 documentation
From: patchwork-bot+netdevbpf @ 2024-03-29 22:50 UTC (permalink / raw)
To: Christophe Roullier
Cc: davem, edumazet, kuba, pabeni, robh+dt, krzysztof.kozlowski+dt,
conor+dt, mcoquelin.stm32, alexandre.torgue, richardcochran,
joabreu, lgirdwood, broonie, marex, netdev, devicetree,
linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20240328185337.332703-1-christophe.roullier@foss.st.com>
Hello:
This patch was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Thu, 28 Mar 2024 19:53:36 +0100 you wrote:
> Introduce property in dwmac-stm32 documentation
>
> - st,ext-phyclk: is present since 2020 in driver so need to explain
> it and avoid dtbs check issue : views/kernel/upstream/net-next/arch/arm/boot/dts/st/stm32mp157c-dk2.dtb:
> ethernet@5800a000: Unevaluated properties are not allowed
> ('st,ext-phyclk' was unexpected)
> Furthermore this property will be use in upstream of MP13 dwmac glue. (next step)
>
> [...]
Here is the summary with links:
- [v6,1/1] dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk
https://git.kernel.org/netdev/net-next/c/929107d3d2a3
You are awesome, thank you!
--
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Subject: Re: [PATCH v6 0/1] Add property in dwmac-stm32 documentation
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Hello:
This patch was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Thu, 28 Mar 2024 19:53:36 +0100 you wrote:
> Introduce property in dwmac-stm32 documentation
>
> - st,ext-phyclk: is present since 2020 in driver so need to explain
> it and avoid dtbs check issue : views/kernel/upstream/net-next/arch/arm/boot/dts/st/stm32mp157c-dk2.dtb:
> ethernet@5800a000: Unevaluated properties are not allowed
> ('st,ext-phyclk' was unexpected)
> Furthermore this property will be use in upstream of MP13 dwmac glue. (next step)
>
> [...]
Here is the summary with links:
- [v6,1/1] dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk
https://git.kernel.org/netdev/net-next/c/929107d3d2a3
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
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^ permalink raw reply
* Re: [PATCH net-next v6 17/17] net: pse-pd: Add TI TPS23881 PSE controller driver
From: Andrew Lunn @ 2024-03-30 14:52 UTC (permalink / raw)
To: Kory Maincent
Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Oleksij Rempel, Mark Brown,
Frank Rowand, Heiner Kallweit, Russell King, Thomas Petazzoni,
netdev, linux-kernel, linux-doc, devicetree, Dent Project
In-Reply-To: <20240329155657.7939ac4b@kmaincent-XPS-13-7390>
On Fri, Mar 29, 2024 at 03:56:57PM +0100, Kory Maincent wrote:
> On Thu, 28 Mar 2024 17:24:17 +0100
> Andrew Lunn <andrew@lunn.ch> wrote:
>
> > > +static int tps23881_flash_fw_part(struct i2c_client *client,
> > > + const char *fw_name,
> > > + const struct tps23881_fw_conf *fw_conf)
> >
> > Does the device actually have flash? Or is this just downloading to
> > SRAM?
>
> It is downloading to SRAM.
So maybe rename these functions.
Andrew
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Date: Sat, 30 Mar 2024 15:52:49 +0100
From: Andrew Lunn <andrew@lunn.ch>
To: Kory Maincent <kory.maincent@bootlin.com>
Cc: "David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Jonathan Corbet <corbet@lwn.net>,
Luis Chamberlain <mcgrof@kernel.org>,
Russ Weight <russ.weight@linux.dev>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Oleksij Rempel <o.rempel@pengutronix.de>,
Mark Brown <broonie@kernel.org>,
Frank Rowand <frowand.list@gmail.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, devicetree@vger.kernel.org,
Dent Project <dentproject@linuxfoundation.org>
Subject: Re: [PATCH net-next v6 17/17] net: pse-pd: Add TI TPS23881 PSE
controller driver
Message-ID: <8186fea6-c1f4-403b-b717-83c1dd3ad826@lunn.ch>
References: <20240326-feature_poe-v6-0-c1011b6ea1cb@bootlin.com>
<20240326-feature_poe-v6-17-c1011b6ea1cb@bootlin.com>
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On Fri, Mar 29, 2024 at 03:56:57PM +0100, Kory Maincent wrote:
> On Thu, 28 Mar 2024 17:24:17 +0100
> Andrew Lunn <andrew@lunn.ch> wrote:
>
> > > +static int tps23881_flash_fw_part(struct i2c_client *client,
> > > + const char *fw_name,
> > > + const struct tps23881_fw_conf *fw_conf)
> >
> > Does the device actually have flash? Or is this just downloading to
> > SRAM?
>
> It is downloading to SRAM.
So maybe rename these functions.
Andrew
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Date: Sat, 30 Mar 2024 15:52:49 +0100
From: Andrew Lunn <andrew@lunn.ch>
To: Kory Maincent <kory.maincent@bootlin.com>
Cc: "David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Jonathan Corbet <corbet@lwn.net>,
Luis Chamberlain <mcgrof@kernel.org>,
Russ Weight <russ.weight@linux.dev>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Oleksij Rempel <o.rempel@pengutronix.de>,
Mark Brown <broonie@kernel.org>,
Frank Rowand <frowand.list@gmail.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, devicetree@vger.kernel.org,
Dent Project <dentproject@linuxfoundation.org>
Subject: Re: [PATCH net-next v6 17/17] net: pse-pd: Add TI TPS23881 PSE
controller driver
Message-ID: <8186fea6-c1f4-403b-b717-83c1dd3ad826@lunn.ch>
References: <20240326-feature_poe-v6-0-c1011b6ea1cb@bootlin.com>
<20240326-feature_poe-v6-17-c1011b6ea1cb@bootlin.com>
<6bbc6b86-3947-4679-ac0b-fde50129d0f6@lunn.ch>
<20240329155657.7939ac4b@kmaincent-XPS-13-7390>
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On Fri, Mar 29, 2024 at 03:56:57PM +0100, Kory Maincent wrote:
> On Thu, 28 Mar 2024 17:24:17 +0100
> Andrew Lunn <andrew@lunn.ch> wrote:
>
> > > +static int tps23881_flash_fw_part(struct i2c_client *client,
> > > + const char *fw_name,
> > > + const struct tps23881_fw_conf *fw_conf)
> >
> > Does the device actually have flash? Or is this just downloading to
> > SRAM?
>
> It is downloading to SRAM.
So maybe rename these functions.
Andrew
^ permalink raw reply
* Re: [PATCH 3/3] drm: panel: Add LG sw43408 panel driver
From: Marijn Suijten @ 2024-03-30 10:27 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Sumit Semwal, Caleb Connolly, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, dri-devel, devicetree,
linux-kernel, linux-arm-msm, Vinod Koul, Caleb Connolly
In-Reply-To: <20240330-lg-sw43408-panel-v1-3-f5580fc9f2da@linaro.org>
On 2024-03-30 05:59:30, Dmitry Baryshkov wrote:
> From: Sumit Semwal <sumit.semwal@linaro.org>
>
> LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel, used in some Pixel3
> phones.
>
> Whatever init sequence we have for this panel isn't capable of
> initialising it completely, toggling the reset gpio ever causes the
> panel to die. Until this is resolved we avoid resetting the panel. The
Are you sure it is avoided? This patch seems to be toggling reset_gpio in
sw43408_prepare()?
> disable/unprepare functions only put the panel to sleep mode and
> disable the backlight.
>
> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
> [vinod: Add DSC support]
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> [caleb: cleanup and support turning off the panel]
> Signed-off-by: Caleb Connolly <caleb@connolly.tech>
> [DB: partially rewrote the driver and fixed DSC programming]
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> MAINTAINERS | 8 +
> drivers/gpu/drm/panel/Kconfig | 11 ++
> drivers/gpu/drm/panel/Makefile | 1 +
> drivers/gpu/drm/panel/panel-lg-sw43408.c | 322 +++++++++++++++++++++++++++++++
> 4 files changed, 342 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4b511a55101c..f4cf7ee97376 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -6755,6 +6755,14 @@ S: Maintained
> F: Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
> F: drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
>
> +DRM DRIVER FOR LG SW43408 PANELS
> +M: Sumit Semwal <sumit.semwal@linaro.org>
> +M: Caleb Connolly <caleb.connolly@linaro.org>
> +S: Maintained
> +T: git git://anongit.freedesktop.org/drm/drm-misc
> +F: Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml
> +F: drivers/gpu/drm/panel/panel-lg-sw43408.c
> +
> DRM DRIVER FOR LOGICVC DISPLAY CONTROLLER
> M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> S: Supported
> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> index d037b3b8b999..f94c702735cb 100644
> --- a/drivers/gpu/drm/panel/Kconfig
> +++ b/drivers/gpu/drm/panel/Kconfig
> @@ -335,6 +335,17 @@ config DRM_PANEL_LG_LG4573
> Say Y here if you want to enable support for LG4573 RGB panel.
> To compile this driver as a module, choose M here.
>
> +config DRM_PANEL_LG_SW43408
> + tristate "LG SW43408 panel"
> + depends on OF
> + depends on DRM_MIPI_DSI
> + depends on BACKLIGHT_CLASS_DEVICE
> + help
> + Say Y here if you want to enable support for LG sw43408 panel.
> + The panel has a 1080x2160 resolution and uses
> + 24 bit RGB per pixel. It provides a MIPI DSI interface to
> + the host and has a built-in LED backlight.
> +
> config DRM_PANEL_MAGNACHIP_D53E6EA8966
> tristate "Magnachip D53E6EA8966 DSI panel"
> depends on OF && SPI
> diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> index f156d7fa0bcc..a75687d13caf 100644
> --- a/drivers/gpu/drm/panel/Makefile
> +++ b/drivers/gpu/drm/panel/Makefile
> @@ -34,6 +34,7 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) += panel-leadtek-ltk050h3146w.o
> obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) += panel-leadtek-ltk500hd1829.o
> obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o
> obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
> +obj-$(CONFIG_DRM_PANEL_LG_SW43408) += panel-lg-sw43408.o
> obj-$(CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966) += panel-magnachip-d53e6ea8966.o
> obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
> obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o
> diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/panel/panel-lg-sw43408.c
> new file mode 100644
> index 000000000000..365d25e14d54
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c
> @@ -0,0 +1,322 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019-2024 Linaro Ltd
> + * Author: Sumit Semwal <sumit.semwal@linaro.org>
> + * Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> + */
> +
> +#include <linux/backlight.h>
> +#include <linux/delay.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/regulator/consumer.h>
> +
> +#include <video/mipi_display.h>
> +
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_probe_helper.h>
> +#include <drm/display/drm_dsc.h>
> +#include <drm/display/drm_dsc_helper.h>
> +
> +#define NUM_SUPPLIES 2
> +
> +struct sw43408_panel {
> + struct drm_panel base;
> + struct mipi_dsi_device *link;
> +
> + const struct drm_display_mode *mode;
> +
> + struct regulator_bulk_data supplies[NUM_SUPPLIES];
> +
> + struct gpio_desc *reset_gpio;
> +};
> +
> +static inline struct sw43408_panel *to_panel_info(struct drm_panel *panel)
> +{
> + return container_of(panel, struct sw43408_panel, base);
> +}
> +
> +static int sw43408_unprepare(struct drm_panel *panel)
> +{
> + struct sw43408_panel *ctx = to_panel_info(panel);
> + int ret;
> +
> + ret = mipi_dsi_dcs_set_display_off(ctx->link);
> + if (ret < 0)
> + dev_err(panel->dev, "set_display_off cmd failed ret = %d\n", ret);
> +
> + ret = mipi_dsi_dcs_enter_sleep_mode(ctx->link);
> + if (ret < 0)
> + dev_err(panel->dev, "enter_sleep cmd failed ret = %d\n", ret);
> +
> + msleep(100);
> +
> + gpiod_set_value(ctx->reset_gpio, 1);
> +
> + return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
> +}
> +
> +static int sw43408_program(struct drm_panel *panel)
> +{
> + struct sw43408_panel *ctx = to_panel_info(panel);
> + struct drm_dsc_picture_parameter_set pps;
> + u8 dsc_en = 0x11;
Yeah, this is completely strange. Bit 0, 0x1, is to enable DSC which is
normal. 0x10 however, which is bit 4, selects PPS table 2. Do you ever set
pps_identifier in struct drm_dsc_picture_parameter_set to 2? Or is the table
that you send below bogus and/or not used? Maybe the Driver IC on the other
end of the DSI link has a default PPS table with identifier 2 that works out of
the box?
> + mipi_dsi_dcs_write_seq(ctx->link, MIPI_DCS_SET_GAMMA_CURVE, 0x02);
> +
> + mipi_dsi_dcs_set_tear_on(ctx->link, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
> +
> + mipi_dsi_dcs_write_seq(ctx->link, 0x53, 0x0c, 0x30);
> + mipi_dsi_dcs_write_seq(ctx->link, 0x55, 0x00, 0x70, 0xdf, 0x00, 0x70, 0xdf);
> + mipi_dsi_dcs_write_seq(ctx->link, 0xf7, 0x01, 0x49, 0x0c);
> +
> + mipi_dsi_dcs_exit_sleep_mode(ctx->link);
> +
> + msleep(135);
> +
> + mipi_dsi_compression_mode_raw(ctx->link, &dsc_en, 1);
Even though I think we should change this function to describe the known
bit layout of command 0x7 per the VESA DSI spec, for now replace 1 with
sizeof(dsc_en)?
> +
> + mipi_dsi_dcs_write_seq(ctx->link, 0xb0, 0xac);
> + mipi_dsi_dcs_write_seq(ctx->link, 0xe5,
> + 0x00, 0x3a, 0x00, 0x3a, 0x00, 0x0e, 0x10);
> + mipi_dsi_dcs_write_seq(ctx->link, 0xb5,
> + 0x75, 0x60, 0x2d, 0x5d, 0x80, 0x00, 0x0a, 0x0b,
> + 0x00, 0x05, 0x0b, 0x00, 0x80, 0x0d, 0x0e, 0x40,
> + 0x00, 0x0c, 0x00, 0x16, 0x00, 0xb8, 0x00, 0x80,
> + 0x0d, 0x0e, 0x40, 0x00, 0x0c, 0x00, 0x16, 0x00,
> + 0xb8, 0x00, 0x81, 0x00, 0x03, 0x03, 0x03, 0x01,
> + 0x01);
> + msleep(85);
> + mipi_dsi_dcs_write_seq(ctx->link, 0xcd,
> + 0x00, 0x00, 0x00, 0x19, 0x19, 0x19, 0x19, 0x19,
> + 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
> + 0x16, 0x16);
> + mipi_dsi_dcs_write_seq(ctx->link, 0xcb, 0x80, 0x5c, 0x07, 0x03, 0x28);
> + mipi_dsi_dcs_write_seq(ctx->link, 0xc0, 0x02, 0x02, 0x0f);
> + mipi_dsi_dcs_write_seq(ctx->link, 0x55, 0x04, 0x61, 0xdb, 0x04, 0x70, 0xdb);
> + mipi_dsi_dcs_write_seq(ctx->link, 0xb0, 0xca);
> +
> + mipi_dsi_dcs_set_display_on(ctx->link);
Any specific reason to not have the (un)blanking sequence in the enable/disable
callbacks and leaving display configuration in (un)prepare?
> + msleep(50);
> +
> + ctx->link->mode_flags &= ~MIPI_DSI_MODE_LPM;
> +
> + drm_dsc_pps_payload_pack(&pps, ctx->link->dsc);
> + mipi_dsi_picture_parameter_set(ctx->link, &pps);
I'm always surprised why this is sent _after_ turning the display on (unblanking
it). Wouldn't that cause unnecessary corruption?
> +
> + ctx->link->mode_flags |= MIPI_DSI_MODE_LPM;
> +
> + return 0;
> +}
> +
> +static int sw43408_prepare(struct drm_panel *panel)
> +{
> + struct sw43408_panel *ctx = to_panel_info(panel);
> + int ret;
> +
> + ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
> + if (ret < 0)
> + return ret;
> +
> + usleep_range(5000, 6000);
> +
> + gpiod_set_value(ctx->reset_gpio, 0);
> + usleep_range(9000, 10000);
> + gpiod_set_value(ctx->reset_gpio, 1);
> + usleep_range(1000, 2000);
> + gpiod_set_value(ctx->reset_gpio, 0);
> + usleep_range(9000, 10000);
> +
> + ret = sw43408_program(panel);
> + if (ret)
> + goto poweroff;
> +
> + return 0;
> +
> +poweroff:
> + gpiod_set_value(ctx->reset_gpio, 1);
> + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
> + return ret;
> +}
> +
> +static int sw43408_get_modes(struct drm_panel *panel,
> + struct drm_connector *connector)
> +{
> + struct sw43408_panel *ctx = to_panel_info(panel);
> +
> + return drm_connector_helper_get_modes_fixed(connector, ctx->mode);
> +}
> +
> +static int sw43408_backlight_update_status(struct backlight_device *bl)
> +{
> + struct mipi_dsi_device *dsi = bl_get_data(bl);
> + uint16_t brightness = backlight_get_brightness(bl);
> +
> + return mipi_dsi_dcs_set_display_brightness_large(dsi, brightness);
> +}
> +
> +const struct backlight_ops sw43408_backlight_ops = {
> + .update_status = sw43408_backlight_update_status,
> +};
> +
> +static int sw43408_backlight_init(struct sw43408_panel *ctx)
> +{
> + struct device *dev = &ctx->link->dev;
> + const struct backlight_properties props = {
> + .type = BACKLIGHT_PLATFORM,
> + .brightness = 255,
> + .max_brightness = 255,
> + };
> +
> + ctx->base.backlight = devm_backlight_device_register(dev, dev_name(dev), dev,
> + ctx->link,
> + &sw43408_backlight_ops,
> + &props);
> +
> + if (IS_ERR(ctx->base.backlight))
> + return dev_err_probe(dev, PTR_ERR(ctx->base.backlight),
> + "Failed to create backlight\n");
> +
> + return 0;
> +}
> +
> +static const struct drm_panel_funcs sw43408_funcs = {
> + .unprepare = sw43408_unprepare,
> + .prepare = sw43408_prepare,
> + .get_modes = sw43408_get_modes,
> +};
> +
> +static const struct drm_display_mode sw43408_default_mode = {
> + .clock = 152340,
> +
> + .hdisplay = 1080,
> + .hsync_start = 1080 + 20,
> + .hsync_end = 1080 + 20 + 32,
> + .htotal = 1080 + 20 + 32 + 20,
> +
> + .vdisplay = 2160,
> + .vsync_start = 2160 + 20,
> + .vsync_end = 2160 + 20 + 4,
> + .vtotal = 2160 + 20 + 4 + 20,
> +
> + .width_mm = 62,
> + .height_mm = 124,
> +
> + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> +};
> +
> +static const struct of_device_id sw43408_of_match[] = {
> + { .compatible = "lg,sw43408", .data = &sw43408_default_mode },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, sw43408_of_match);
> +
> +static int sw43408_add(struct sw43408_panel *ctx)
> +{
> + struct device *dev = &ctx->link->dev;
> + int ret;
> +
> + ctx->supplies[0].supply = "vddi"; /* 1.88 V */
> + ctx->supplies[0].init_load_uA = 62000;
> + ctx->supplies[1].supply = "vpnl"; /* 3.0 V */
> + ctx->supplies[1].init_load_uA = 857000;
> +
> + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
> + ctx->supplies);
> + if (ret < 0)
> + return ret;
> +
> + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
> + if (IS_ERR(ctx->reset_gpio)) {
> + dev_err(dev, "cannot get reset gpio %ld\n",
> + PTR_ERR(ctx->reset_gpio));
> + return PTR_ERR(ctx->reset_gpio);
> + }
> +
> + ret = sw43408_backlight_init(ctx);
> + if (ret < 0)
> + return ret;
> +
> + ctx->base.prepare_prev_first = true;
> +
> + drm_panel_init(&ctx->base, dev, &sw43408_funcs, DRM_MODE_CONNECTOR_DSI);
> +
> + drm_panel_add(&ctx->base);
> + return ret;
> +}
> +
> +static int sw43408_probe(struct mipi_dsi_device *dsi)
> +{
> + struct sw43408_panel *ctx;
> + struct drm_dsc_config *dsc;
> + int ret;
> +
> + ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
> + if (!ctx)
> + return -ENOMEM;
> +
> + ctx->mode = of_device_get_match_data(&dsi->dev);
> + dsi->mode_flags = MIPI_DSI_MODE_LPM;
> + dsi->format = MIPI_DSI_FMT_RGB888;
> + dsi->lanes = 4;
> +
> + ctx->link = dsi;
> + mipi_dsi_set_drvdata(dsi, ctx);
> +
> + ret = sw43408_add(ctx);
> + if (ret < 0)
> + return ret;
> +
> + /* The panel is DSC panel only, set the dsc params */
> + dsc = devm_kzalloc(&dsi->dev, sizeof(*dsc), GFP_KERNEL);
We've recently decided to store struct drm_dsc_config in struct sw43408_panel
and save on an extra allocation.
> + if (!dsc)
> + return -ENOMEM;
> +
> + dsc->dsc_version_major = 0x1;
> + dsc->dsc_version_minor = 0x1;
> +
> + dsc->slice_height = 16;
> + dsc->slice_width = 540;
> + dsc->slice_count = 2;
Maybe incorporate with a comment that slice_count * slice_width == the width of
the mode?
- Marijn
> + dsc->bits_per_component = 8;
> + dsc->bits_per_pixel = 8 << 4;
> + dsc->block_pred_enable = true;
> +
> + dsi->dsc = dsc;
> +
> + return mipi_dsi_attach(dsi);
> +}
> +
> +static void sw43408_remove(struct mipi_dsi_device *dsi)
> +{
> + struct sw43408_panel *ctx = mipi_dsi_get_drvdata(dsi);
> + int ret;
> +
> + ret = sw43408_unprepare(&ctx->base);
> + if (ret < 0)
> + dev_err(&dsi->dev, "failed to unprepare panel: %d\n",
> + ret);
> +
> + ret = mipi_dsi_detach(dsi);
> + if (ret < 0)
> + dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
> +
> + drm_panel_remove(&ctx->base);
> +}
> +
> +static struct mipi_dsi_driver sw43408_driver = {
> + .driver = {
> + .name = "panel-lg-sw43408",
> + .of_match_table = sw43408_of_match,
> + },
> + .probe = sw43408_probe,
> + .remove = sw43408_remove,
> +};
> +module_mipi_dsi_driver(sw43408_driver);
> +
> +MODULE_AUTHOR("Sumit Semwal <sumit.semwal@linaro.org>");
> +MODULE_DESCRIPTION("LG SW436408 MIPI-DSI LED panel");
> +MODULE_LICENSE("GPL");
>
> --
> 2.39.2
>
^ permalink raw reply
* Re: [PATCH 2/4] dt-bindings: mfd: x-powers,axp152: add boost regulator
From: Andre Przywara @ 2024-03-30 21:40 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Chen-Yu Tsai, Lee Jones, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel,
linux-sunxi, Jernej Skrabec, Samuel Holland, Ryan Walklin,
Chris Morgan
In-Reply-To: <0b53cf44-b5ca-4ccc-9912-777b85f1bcbd@linaro.org>
On Sat, 30 Mar 2024 10:30:05 +0100
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
Hi,
> On 30/03/2024 00:50, Andre Przywara wrote:
> > The X-Powers AXP717 contains a boost regulator, that it meant to provide
> > the 5V USB VBUS voltage when the devices operates on battery.
> >
> > Add the name "boost" to the regexp describing the allowed node names,
> > to allow the regulator to be described in the devicetree.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> > Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
> > index b8e8db0d58e9c..14ab367fc8871 100644
> > --- a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
> > @@ -274,7 +274,7 @@ properties:
> > Defines the work frequency of DC-DC in kHz.
> >
> > patternProperties:
> > - "^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo)$":
> > + "^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo|boost)$":
>
> That's not an easy to read regex...
TBH regexps are the least of my problems when reading bindings ;-)
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Thanks!
> If driver does not depend on _, please consider dropping (_|-).
The drivers (checked both Linux and FreeBSD) do look for a specific
string, but it's the real old regulators that used ldo_io[01] and
rtc_ldo, all the "newer" ones use a dash. Since this binding covers all
of them, we can't drop this from this regexp, but rest assured we only
go with dashes for new and upcoming devices.
Thanks,
Andre
^ permalink raw reply
* Re: [PATCH v2 2/3] dt-bindings: power: Add mediatek larb definition
From: kernel test robot @ 2024-03-31 15:02 UTC (permalink / raw)
To: yu-chang.lee, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ulf Hansson, Matthias Brugger, AngeloGioacchino Del Regno,
MandyJH Liu
Cc: oe-kbuild-all, devicetree, linux-kernel, linux-pm,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, fan.chen, xiufeng.li,
yu-chang.lee
In-Reply-To: <20240327055732.28198-3-yu-chang.lee@mediatek.com>
Hi yu-chang.lee,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on krzk-dt/for-next linus/master v6.9-rc1 next-20240328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/yu-chang-lee/pmdomain-mediatek-add-smi_larb_reset-function-when-power-on/20240327-140007
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20240327055732.28198-3-yu-chang.lee%40mediatek.com
patch subject: [PATCH v2 2/3] dt-bindings: power: Add mediatek larb definition
compiler: loongarch64-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240331/202403312222.fjYPC06h-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403312222.fjYPC06h-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> Documentation/devicetree/bindings/power/mediatek,power-controller.yaml:128:6: [error] syntax error: expected <block end>, but found '<block mapping start>' (syntax)
>> Documentation/devicetree/bindings/power/mediatek,power-controller.yaml:129:9: [warning] wrong indentation: expected 7 but found 8 (indentation)
--
>> Documentation/devicetree/bindings/power/mediatek,power-controller.yaml:128:6: did not find expected key
>> Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml:
while parsing a block mapping
in "<unicode string>", line 64, column 5
did not find expected key
in "<unicode string>", line 128, column 6
--
>> Documentation/devicetree/bindings/power/mediatek,power-controller.yaml: ignoring, error parsing file
vim +128 Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
8
9 maintainers:
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
12
13 description: |
14 Mediatek processors include support for multiple power domains which can be
15 powered up/down by software based on different application scenes to save power.
16
17 IP cores belonging to a power domain should contain a 'power-domains'
18 property that is a phandle for SCPSYS node representing the domain.
19
20 properties:
21 $nodename:
22 pattern: '^power-controller(@[0-9a-f]+)?$'
23
24 compatible:
25 enum:
26 - mediatek,mt6795-power-controller
27 - mediatek,mt8167-power-controller
28 - mediatek,mt8173-power-controller
29 - mediatek,mt8183-power-controller
30 - mediatek,mt8186-power-controller
31 - mediatek,mt8188-power-controller
32 - mediatek,mt8192-power-controller
33 - mediatek,mt8195-power-controller
34 - mediatek,mt8365-power-controller
35
36 '#power-domain-cells':
37 const: 1
38
39 '#address-cells':
40 const: 1
41
42 '#size-cells':
43 const: 0
44
45 patternProperties:
46 "^power-domain@[0-9a-f]+$":
47 $ref: "#/$defs/power-domain-node"
48 patternProperties:
49 "^power-domain@[0-9a-f]+$":
50 $ref: "#/$defs/power-domain-node"
51 patternProperties:
52 "^power-domain@[0-9a-f]+$":
53 $ref: "#/$defs/power-domain-node"
54 patternProperties:
55 "^power-domain@[0-9a-f]+$":
56 $ref: "#/$defs/power-domain-node"
57 unevaluatedProperties: false
58 unevaluatedProperties: false
59 unevaluatedProperties: false
60 unevaluatedProperties: false
61
62 $defs:
63 power-domain-node:
64 type: object
65 description: |
66 Represents the power domains within the power controller node as documented
67 in Documentation/devicetree/bindings/power/power-domain.yaml.
68
69 properties:
70
71 '#power-domain-cells':
72 description:
73 Must be 0 for nodes representing a single PM domain and 1 for nodes
74 providing multiple PM domains.
75
76 '#address-cells':
77 const: 1
78
79 '#size-cells':
80 const: 0
81
82 reg:
83 description: |
84 Power domain index. Valid values are defined in:
85 "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.
86 "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
87 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
88 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
89 "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
90 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
91 "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
92 "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.
93 maxItems: 1
94
95 clocks:
96 description: |
97 A number of phandles to clocks that need to be enabled during domain
98 power-up sequencing.
99
100 clock-names:
101 description: |
102 List of names of clocks, in order to match the power-up sequencing
103 for each power domain we need to group the clocks by name. BASIC
104 clocks need to be enabled before enabling the corresponding power
105 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
106 SUSBYS clocks need to be enabled before releasing the bus protection,
107 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
108
109 In order to follow properly the power-up sequencing, the clocks must
110 be specified by order, adding first the BASIC clocks followed by the
111 SUSBSYS clocks.
112
113 domain-supply:
114 description: domain regulator supply.
115
116 mediatek,infracfg:
117 $ref: /schemas/types.yaml#/definitions/phandle
118 description: phandle to the device containing the INFRACFG register range.
119
120 mediatek,infracfg-nao:
121 $ref: /schemas/types.yaml#/definitions/phandle
122 description: phandle to the device containing the INFRACFG-NAO register range.
123
124 mediatek,smi:
125 $ref: /schemas/types.yaml#/definitions/phandle
126 description: phandle to the device containing the SMI register range.
127
> 128 mediatek,larb:
> 129 $ref: /schemas/types.yaml#/definitions/phandle
130 description: phandle to the device containing the LARB register range.
131
132 required:
133 - reg
134
135 required:
136 - compatible
137
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v6 0/4] fpga: xilinx-selectmap: add new driver
From: Xu Yilun @ 2024-03-31 14:50 UTC (permalink / raw)
To: Charles Perry
Cc: mdf, avandiver, bcody, Wu Hao, Xu Yilun, Tom Rix, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Michal Simek, linux-fpga,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20240321220447.3260065-1-charles.perry@savoirfairelinux.com>
On Thu, Mar 21, 2024 at 06:04:32PM -0400, Charles Perry wrote:
> Hello,
>
> This patchset adds a new driver for the 7 series FPGA's SelectMAP
> interface.
>
> The SelectMAP interface shares a common GPIO protocol with the SPI
> interface which is already in the kernel (drivers/fpga/xilinx-spi.c).
> The approach proposed in this patchset is to refactor xilinx-spi.c into
> xilinx-core.c which would handle the common GPIO protocol. This is then
> used to build two drivers, the already existing xilinx-spi.c driver and
> a newly added xilinx-selectmap.c driver.
>
> The SelectMAP driver proposed only supports 8 bit mode. This is because
> the 16 and 32 bits mode have limitations with regards to compressed
> bitstream support as well as introducing endianness considerations.
>
> I'm testing xilinx-selectmap.c on a custom i.MX6 board connected to an
> Artix 7 FPGA. Flashing a 913K bitstream takes 0.44 seconds.
>
> Changes since v5: (from Yilun review)
> * xilinx-core.h: remove private fields kernel-doc
> * xilinx-spi.c: rename conf into core in xilinx_spi_probe
> * xilinx-core.c: introduce the new gpio names in patch 4/4
> * xilinx-core.c: remove kernel-doc on xilinx_core_devm_gpiod_get()
> * xilinx-selectmap.c:
> * reorder includes in alphabetical order
> * xilinx_selectmap_probe(): remove unused resource *r variable
> * xilinx_selectmap_probe(): use a single gpio_desc* temporary
> * xilinx_selectmap_probe(): declare variables in reverse xmas tree
>
> Changes since v4: (from Yilun and Krzysztof review)
> * xilinx-core: use sizeof() instead of hardcoded immediate
> * xilinx-core: fix module compilation (EXPORT_SYMBOL_GPL, MODULE_LICENSE,
> MODULE_AUTHOR, MODULE_DESCRIPTION)
> * xilinx-core: add private/public qualifiers for struct xilinx_fpga_core
> * xilinx-spi: remove struct xilinx_spi_conf. This struct isn't needed as
> the struct spi_device* can be retrieved from the struct device*.
> * dt-bindings: remove usage of "_b" and "-b" for the new driver. We
> agreed that the spi and selectmap driver will use different bindings
> which will be handled by the driver core and that the legacy names will
> be used only for the spi compatible.
> * xilinx-core: select between prog/init and prog_b/init-b
>
> Changes since v3: (from Rob Herring review)
> * Fix an error in the DT binding example compatible.
> * Drop the renaming of "prog_b" to "prog" and "init-b" to "init".
> Patches 2 and 3 are removed.
>
> Changes since v2:
> * Inserted patch 2 and 3 which rename "prog_b" and "init-b" into "prog"
> and "init" for the SPI driver.
> * From Krzysztof Kozlowski review's:
> * Use more specific compatible names
> * Remove other missing occurences of the slave word missed in v2.
> * From Xu Yilun review's:
> * Fix vertical whitespace in get_done_gpio().
> * Combine write() and write_one_dummy_byte() together.
> * Eliminate most of the xilinx_core_probe() arguments, the driver
> needs to populate those directly into the xilinx_fpga_core struct.
> Added some documentation to struct xilinx_fpga_core to clarify
> this.
> * Removed typedefs from xilinx-core.h.
> * Moved null checks in xilinx_core_probe() to first patch.
> * Move csi_b and rdwr_b out of xilinx_selectmap_conf as they are not
> used out of the probe function.
>
> Changes since v1: (from Krzysztof Kozlowski review's)
> * Use more conventional names for gpio DT bindings
> * fix example in DT bindings
> * add mc-peripheral-props.yaml to DT bindings
> * fix various formatting mistakes
> * Remove all occurences of the "slave" word.
>
> Charles Perry (4):
> fpga: xilinx-spi: extract a common driver core
> dt-bindings: fpga: xlnx,fpga-selectmap: add DT schema
> fpga: xilinx-selectmap: add new driver
> xilinx-core: add new gpio names for prog and init
>
> .../bindings/fpga/xlnx,fpga-selectmap.yaml | 86 +++++++
> drivers/fpga/Kconfig | 12 +
> drivers/fpga/Makefile | 2 +
> drivers/fpga/xilinx-core.c | 229 ++++++++++++++++++
> drivers/fpga/xilinx-core.h | 27 +++
> drivers/fpga/xilinx-selectmap.c | 95 ++++++++
> drivers/fpga/xilinx-spi.c | 224 ++---------------
> 7 files changed, 466 insertions(+), 209 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml
> create mode 100644 drivers/fpga/xilinx-core.c
> create mode 100644 drivers/fpga/xilinx-core.h
> create mode 100644 drivers/fpga/xilinx-selectmap.c
Applied this series to for-next with a nit.
Thanks,
Yilun
>
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH v6 3/4] fpga: xilinx-selectmap: add new driver
From: Xu Yilun @ 2024-03-31 14:34 UTC (permalink / raw)
To: Charles Perry
Cc: mdf, avandiver, bcody, Wu Hao, Xu Yilun, Tom Rix, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Michal Simek, linux-fpga,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20240321220447.3260065-4-charles.perry@savoirfairelinux.com>
> +static int xilinx_selectmap_write(struct xilinx_fpga_core *core,
> + const char *buf, size_t count)
> +{
> + struct xilinx_selectmap_conf *conf = to_xilinx_selectmap_conf(core);
> + u32 i;
comparing u32 with size_t is problematic.
size_t i;
I can fix it in place.
Thanks,
Yilun
> +
> + for (i = 0; i < count; ++i)
> + writeb(buf[i], conf->base);
> +
> + return 0;
> +}
^ permalink raw reply
* Re: [PATCH] iio: industrialio-core: look for aliases to request device index
From: Jonathan Cameron @ 2024-03-31 14:20 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Dominique Martinet, David Lechner, Krzysztof Kozlowski,
Syunya Ohshio, Guido Günther, Lars-Peter Clausen,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-iio,
devicetree, linux-kernel
In-Reply-To: <20240318122953.000013f3@Huawei.com>
On Mon, 18 Mar 2024 12:29:53 +0000
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:
> On Mon, 18 Mar 2024 11:15:36 +0900
> Dominique Martinet <dominique.martinet@atmark-techno.com> wrote:
>
> > David Lechner wrote on Fri, Mar 15, 2024 at 10:53:36AM -0500:
> > > How about using udev rules to create symlinks for each device based on
> > > the label attribute? No changes to the kernel are needed.
> >
> > Right, it's definitely possible to make symlinks for each "device" -- my
> > patch comment links to such an udev script "solution":
> > https://git.toradex.com/cgit/meta-toradex-bsp-common.git/tree/recipes-core/udev/files/verdin-imx8mm/toradex-adc.sh?h=kirkstone-6.x.y
> > (the script is launched by udev here:
> > https://git.toradex.com/cgit/meta-toradex-bsp-common.git/tree/recipes-core/udev/files/verdin-imx8mm/99-toradex.rules
> > )
> >
> > My conceptual problem with this is that this makes symlinks in /dev to
> > files in /sys and it feels like we're crossing boundaries.
> > As far as I can tell there is no way for userspace to create arbitrary
> > symlinks in /sys, so I think we could have an interface more
> > user-friendly by allowing paths to be static for users with multiple
> > devices.
> > (I guess that's a weak argument given e.g. disks etc will also have an
> > unreliable name in /sys in the general case, but simple programs don't
> > interact with them in /sys and can use stable links in /dev so my
> > expectations here aren't quite the same)
> >
> >
> > Ultimately, the problem might run deeper in that we're having userspace
> > interact with the device through /sys and not the /dev char dev... As
> > far as I could see /dev/iio:deviceX only allows reading buffered values
> > and doesn't have any ioctl or other way of reading immediate values as
> > is possible in /sys though, so that'd require quite a bit of work to
> > duplicate the interface there...
>
> Don't. The sysfs interface as only control is entirely intentional and
> we do not want IOCTL based duplication.
>
> Just addressing this bit as I'm still a bit snowed under to think about this
> more generally.
>
Hi, got back to this finally...
So the problems compared to other 'alias' users is that IIO is a bit more
complex than for example LEDs. A single DT node/compatible (or equivalent) can
result in a 1+ IIO devices and 1+ triggers. Triggers can also be instantiated
via configfs (technically devices can as well but we can ignore that).
Any alias scheme needs to work for all these options. To my mind that makes
it a userspace problem, not something the kernel can deal with in generic
enough way. I think that all IIO devices have ways to stability identify them
(label, or parent devices)
There is an approximate equivalent of DT alias entries in SMBIOS but
I suspect not all ACPI platforms will provide that (it's typically used for
stable disk / network device naming on complex servers).
So I've messed around a bit and can think of various possible options to make
this simpler.
1) Use a tmpfs mount and link from that.
Now we 'could' put an alias directory somewhere under /sys/bus/iio/ that
is a mount point created via sysfs_create_mount_point() - I abused the
/sys/kernel/debug directory to test this (unmounted debugfs and mounted
a tmpfs). That would provide somewhere in sysfs that allows suitable
links. However, this is unusual so likely to be controversial.
2) Alternatively the relevant platform could create one of these somewhere
outside of sysfs and use udev rules to create the links.
3) Stick to the oddity of doing it under /dev/
4) Access the things in the first place via more stable paths?
/sys/bus/i2c/devices/i2c-0/0-0008/iio\:device?/ etc
Relying on the alias support for i2c bus numbering to make that stable should work
and if you are sure there will only be one entry (most devices) that matches
the wild card, should be easy enough to use in scripts.
My personal preference is this last option. Basically if you want stable paths
don't use /sys/bus/iio/devices/ to get them.
Jonathan
^ permalink raw reply
* RE: [PATCH v6 3/4] firmware: arm_scmi: Add SCMI v3.2 pincontrol protocol basic support
From: Peng Fan @ 2024-03-31 13:44 UTC (permalink / raw)
To: Andy Shevchenko, Peng Fan (OSS)
Cc: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Linus Walleij, Dan Carpenter,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Oleksii Moisieiev
In-Reply-To: <ZgcP4IkTQGks9ehH@surfacebook.localdomain>
Hi Andy,
> Subject: Re: [PATCH v6 3/4] firmware: arm_scmi: Add SCMI v3.2 pincontrol
> protocol basic support
>
> Sat, Mar 23, 2024 at 08:15:16PM +0800, Peng Fan (OSS) kirjoitti:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Add basic implementation of the SCMI v3.2 pincontrol protocol.
>
> ...
>
> > scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_VIRTIO) += virtio.o
> > scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_OPTEE) += optee.o
> > scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o
> > system.o voltage.o powercap.o
>
> Actually you want to have := here.
>
> > +scmi-protocols-y += pinctrl.o
>
>
>
> > scmi-module-objs := $(scmi-driver-y) $(scmi-protocols-y)
> > $(scmi-transport-y)
>
> Side note: The -objs has to be -y
>
> ...
>
> > +#include <linux/module.h>
> > +#include <linux/scmi_protocol.h>
> > +#include <linux/slab.h>
>
> This is semi-random list of headers. Please, follow IWYU principle (include
> what you use). There are a lot of inclusions I see missing (just in the context of
> this page I see bits.h, types.h, and asm/byteorder.h).
Is there any documentation about this requirement?
Some headers are already included by others.
>
> ...
>
> > +enum scmi_pinctrl_protocol_cmd {
> > + PINCTRL_ATTRIBUTES = 0x3,
> > + PINCTRL_LIST_ASSOCIATIONS = 0x4,
> > + PINCTRL_SETTINGS_GET = 0x5,
> > + PINCTRL_SETTINGS_CONFIGURE = 0x6,
> > + PINCTRL_REQUEST = 0x7,
> > + PINCTRL_RELEASE = 0x8,
> > + PINCTRL_NAME_GET = 0x9,
> > + PINCTRL_SET_PERMISSIONS = 0xa
>
> Leave trailing comma as it's not a termination.
>
> > +};
>
> ...
>
> > +static int scmi_pinctrl_attributes_get(const struct scmi_protocol_handle
> *ph,
> > + struct scmi_pinctrl_info *pi) {
> > + int ret;
> > + struct scmi_xfer *t;
> > + struct scmi_msg_pinctrl_protocol_attributes *attr;
> > +
> > + ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES, 0,
> sizeof(*attr),
> > + &t);
>
> This looks much better on a single line.
Per Cristian, scmi drivers keep 80 max chars.
>
> > + if (ret)
> > + return ret;
> > +
> > + attr = t->rx.buf;
> > +
> > + ret = ph->xops->do_xfer(ph, t);
> > + if (!ret) {
> > + pi->nr_functions = GET_FUNCTIONS_NR(attr-
> >attributes_high);
> > + pi->nr_groups = GET_GROUPS_NR(attr->attributes_low);
> > + pi->nr_pins = GET_PINS_NR(attr->attributes_low);
> > + }
> > +
> > + ph->xops->xfer_put(ph, t);
> > + return ret;
> > +}
>
> ...
>
> > + ret = ph->xops->xfer_get_init(ph, PINCTRL_ATTRIBUTES, sizeof(*tx),
> > + sizeof(*rx), &t);
>
> Possible to have on a single line (if you use relaxed 100 limit).
> Or (re)split it more logically:
>
> ret = ph->xops->xfer_get_init(ph, PINCTRL_ATTRIBUTES,
> sizeof(*tx), sizeof(*rx), &t);
>
> > + if (ret)
> > + return ret;
>
> ...
>
> > + /*
> > + * If supported overwrite short name with the extended one;
> > + * on error just carry on and use already provided short name.
> > + */
> > + if (!ret && ext_name_flag)
>
> Please, use standard pattern, i.e.
>
> if (ret)
> return ret;
>
> > + ph->hops->extended_name_get(ph, PINCTRL_NAME_GET,
> selector,
> > + (u32 *)&type, name,
>
> Why is an explicit casting needed?
The type is enum, not u32.
>
> > + SCMI_MAX_STR_SIZE);
> > + return ret;
>
> ...
>
> > + iter = ph->hops->iter_response_init(ph, &ops, size,
> > + PINCTRL_LIST_ASSOCIATIONS,
> > + sizeof(struct
> scmi_msg_pinctrl_list_assoc),
> > + &ipriv);
>
> > +
>
> Redundant blank line.
>
> > + if (IS_ERR(iter))
> > + return PTR_ERR(iter);
>
> ...
>
> > + if (p->flag == 1)
> > + attributes |= FIELD_PREP(SKIP_CONFIGS_MASK, desc_index);
> > + else if (!p->flag)
>
> Be consistent, i.e. if (p->flag == 0)
>
> > + attributes |= FIELD_PREP(CONFIG_TYPE_MASK, p-
> >config_types[0]);
>
> ...
>
> > + st->num_remaining = le32_get_bits(r->num_configs,
> > + GENMASK(31, 24));
>
> One line?
Scmi drivers use 80 max drivers.
>
> ...
>
> > + if (!p->flag) {
> > + if (p->config_types[0] !=
> > + le32_get_bits(r->configs[st->loop_idx * 2], GENMASK(7, 0)))
> > + return -EINVAL;
> > + } else if (p->flag == 1) {
> > + p->config_types[st->desc_index + st->loop_idx] =
> > + le32_get_bits(r->configs[st->loop_idx * 2],
> > + GENMASK(7, 0));
>
> With a temporary variable for r->configs[st->loop_idx * 2] the above can be
> written in much better way.
ok. Fix in v7.
>
> > + } else if (p->flag == 2) {
> > + return 0;
> > + }
>
> > + p->config_values[st->desc_index + st->loop_idx] =
> > + le32_to_cpu(r->configs[st->loop_idx * 2 + 1]);
>
> For the sake of consistency with the above suggestion also temporary for next
> config value.
>
> ...
>
> > + iter = ph->hops->iter_response_init(ph, &ops, 1,
> PINCTRL_SETTINGS_GET,
> > + sizeof(struct
> scmi_msg_settings_get),
> > + &ipriv);
>
> > +
>
> Redundant blank line.
>
> > + if (IS_ERR(iter))
> > + return PTR_ERR(iter);
>
> ...
>
> > +static int scmi_pinctrl_get_group_info(const struct scmi_protocol_handle
> *ph,
> > + u32 selector,
> > + struct scmi_group_info *group) {
> > + int ret;
>
> > + if (!group)
> > + return -EINVAL;
>
> When the above is not a dead code?
It could be removed.
>
> > + ret = scmi_pinctrl_attributes(ph, GROUP_TYPE, selector,
> > + group->name,
> > + &group->nr_pins);
> > + if (ret)
> > + return ret;
> > +
> > + if (!group->nr_pins) {
> > + dev_err(ph->dev, "Group %d has 0 elements", selector);
> > + return -ENODATA;
> > + }
> > +
> > + group->group_pins = kmalloc_array(group->nr_pins,
> > + sizeof(*group->group_pins),
> > + GFP_KERNEL);
> > + if (!group->group_pins)
> > + return -ENOMEM;
> > +
> > + ret = scmi_pinctrl_list_associations(ph, selector, GROUP_TYPE,
> > + group->nr_pins, group-
> >group_pins);
> > + if (ret) {
> > + kfree(group->group_pins);
> > + return ret;
> > + }
> > +
> > + group->present = true;
> > + return 0;
> > +}
>
> ...
>
> > + ret = scmi_pinctrl_get_group_info(ph, selector,
> > + &pi->groups[selector]);
>
> One line?
>
> > + if (ret)
> > + return ret;
>
> ...
>
> > + ret = scmi_pinctrl_attributes(ph, FUNCTION_TYPE, selector,
> > + func->name,
> > + &func->nr_groups);
>
> At least last two lines can be joined.
>
> > + if (ret)
> > + return ret;
>
> ...
>
> > + ret = scmi_pinctrl_attributes(ph, PIN_TYPE, selector,
> > + pin->name, NULL);
>
> It's pleany of room on the previous line.
>
> > + if (ret)
> > + return ret;
>
> ...
>
> > + ret = scmi_pinctrl_get_pin_info(ph, selector,
> > + &pi->pins[selector]);
>
> Ditto.
>
> > + if (ret)
> > + return ret;
>
> ...
>
> > +static int scmi_pinctrl_protocol_init(const struct
> > +scmi_protocol_handle *ph) {
> > + int ret;
> > + u32 version;
> > + struct scmi_pinctrl_info *pinfo;
> > +
> > + ret = ph->xops->version_get(ph, &version);
> > + if (ret)
> > + return ret;
> > +
> > + dev_dbg(ph->dev, "Pinctrl Version %d.%d\n",
> > + PROTOCOL_REV_MAJOR(version),
> PROTOCOL_REV_MINOR(version));
> > +
> > + pinfo = devm_kzalloc(ph->dev, sizeof(*pinfo), GFP_KERNEL);
>
> Huh?!
>
> Please, get yourself familiar with the scope of devm APIs.
Please teach me if this is wrong.
>
> > + if (!pinfo)
> > + return -ENOMEM;
> > +
> > + ret = scmi_pinctrl_attributes_get(ph, pinfo);
> > + if (ret)
> > + return ret;
> > +
> > + pinfo->pins = devm_kcalloc(ph->dev, pinfo->nr_pins,
> > + sizeof(*pinfo->pins),
> > + GFP_KERNEL);
> > + if (!pinfo->pins)
> > + return -ENOMEM;
> > +
> > + pinfo->groups = devm_kcalloc(ph->dev, pinfo->nr_groups,
> > + sizeof(*pinfo->groups),
> > + GFP_KERNEL);
> > + if (!pinfo->groups)
> > + return -ENOMEM;
> > +
> > + pinfo->functions = devm_kcalloc(ph->dev, pinfo->nr_functions,
> > + sizeof(*pinfo->functions),
> > + GFP_KERNEL);
> > + if (!pinfo->functions)
> > + return -ENOMEM;
> > +
> > + pinfo->version = version;
> > +
> > + return ph->set_priv(ph, pinfo, version); }
> > +
> > +static int scmi_pinctrl_protocol_deinit(const struct
> > +scmi_protocol_handle *ph) {
> > + int i;
> > + struct scmi_pinctrl_info *pi = ph->get_priv(ph);
> > +
> > + for (i = 0; i < pi->nr_groups; i++) {
> > + if (pi->groups[i].present) {
> > + kfree(pi->groups[i].group_pins);
> > + pi->groups[i].present = false;
> > + }
> > + }
> > +
> > + for (i = 0; i < pi->nr_functions; i++) {
> > + if (pi->functions[i].present) {
> > + kfree(pi->functions[i].groups);
>
> This is wrong in conjunction with the above.
Yeah.
>
> > + pi->functions[i].present = false;
> > + }
> > + }
> > +
> > + return 0;
> > +}
>
> ...
>
> > +static const struct scmi_protocol scmi_pinctrl = {
> > + .id = SCMI_PROTOCOL_PINCTRL,
> > + .owner = THIS_MODULE,
> > + .instance_init = &scmi_pinctrl_protocol_init,
> > + .instance_deinit = &scmi_pinctrl_protocol_deinit,
> > + .ops = &pinctrl_proto_ops,
> > + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, };
>
> > +
>
> Redundant blank line.
Fix in v7
Thanks,
Peng.
>
> > +DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(pinctrl, scmi_pinctrl)
>
>
> --
> With Best Regards,
> Andy Shevchenko
>
^ permalink raw reply
* RE: [PATCH v6 3/4] firmware: arm_scmi: Add SCMI v3.2 pincontrol protocol basic support
From: Peng Fan @ 2024-03-31 13:28 UTC (permalink / raw)
To: Cristian Marussi, Peng Fan (OSS)
Cc: Sudeep Holla, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Linus Walleij, Dan Carpenter,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Oleksii Moisieiev
In-Reply-To: <ZgWRA2V3PF_q9yRM@pluto>
Hi Cristian,
> Subject: Re: [PATCH v6 3/4] firmware: arm_scmi: Add SCMI v3.2 pincontrol
> protocol basic support
>
> On Sat, Mar 23, 2024 at 08:15:16PM +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Add basic implementation of the SCMI v3.2 pincontrol protocol.
> >
>
> Hi,
>
> a few more comments down below...
>
> > Co-developed-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
> > Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> > drivers/firmware/arm_scmi/Makefile | 1 +
> > drivers/firmware/arm_scmi/driver.c | 2 +
> > drivers/firmware/arm_scmi/pinctrl.c | 921
> ++++++++++++++++++++++++++++++++++
> > drivers/firmware/arm_scmi/protocols.h | 1 +
> > include/linux/scmi_protocol.h | 75 +++
> > 5 files changed, 1000 insertions(+)
> >
> > diff --git a/drivers/firmware/arm_scmi/Makefile
> > b/drivers/firmware/arm_scmi/Makefile
> > index a7bc4796519c..8e3874ff1544 100644
> > --- a/drivers/firmware/arm_scmi/Makefile
> > +++ b/drivers/firmware/arm_scmi/Makefile
> > @@ -11,6 +11,7 @@ scmi-transport-$(CONFIG_ARM_SCMI_HAVE_MSG) +=
> msg.o
> > scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_VIRTIO) += virtio.o
> > scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_OPTEE) += optee.o
> > scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o
> > system.o voltage.o powercap.o
> > +scmi-protocols-y += pinctrl.o
> > scmi-module-objs := $(scmi-driver-y) $(scmi-protocols-y)
> > $(scmi-transport-y)
> >
> > obj-$(CONFIG_ARM_SCMI_PROTOCOL) += scmi-core.o diff --git
> > a/drivers/firmware/arm_scmi/driver.c
> > b/drivers/firmware/arm_scmi/driver.c
> > index 415e6f510057..ac2d4b19727c 100644
> > --- a/drivers/firmware/arm_scmi/driver.c
> > +++ b/drivers/firmware/arm_scmi/driver.c
> > @@ -3142,6 +3142,7 @@ static int __init scmi_driver_init(void)
> > scmi_voltage_register();
> > scmi_system_register();
> > scmi_powercap_register();
> > + scmi_pinctrl_register();
> >
> > return platform_driver_register(&scmi_driver);
> > }
> > @@ -3159,6 +3160,7 @@ static void __exit scmi_driver_exit(void)
> > scmi_voltage_unregister();
> > scmi_system_unregister();
> > scmi_powercap_unregister();
> > + scmi_pinctrl_unregister();
> >
> > scmi_transports_exit();
> >
> > diff --git a/drivers/firmware/arm_scmi/pinctrl.c
> > b/drivers/firmware/arm_scmi/pinctrl.c
> > new file mode 100644
> > index 000000000000..87d9b89cab13
> > --- /dev/null
> > +++ b/drivers/firmware/arm_scmi/pinctrl.c
> > @@ -0,0 +1,921 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * System Control and Management Interface (SCMI) Pinctrl Protocol
> > + *
> > + * Copyright (C) 2024 EPAM
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#include <linux/module.h>
> > +#include <linux/scmi_protocol.h>
> > +#include <linux/slab.h>
> > +
> > +#include "common.h"
> > +#include "protocols.h"
> > +
> > +/* Updated only after ALL the mandatory features for that version are
> merged */
> > +#define SCMI_PROTOCOL_SUPPORTED_VERSION 0x0
> > +
>
> AFAICS, the only missing things are PINCTRL_SET_PERMISSIONS (optional
> command)
I not see users as of now, could we add it until we need it?
and the multiple-configs on SETTINGS_GET, but this latter is
> something really that we have to ask for in the request AND we did not as of
> now since we dont need it...so I would say to bump the version to 0x10000
ok.
> just to avoid needless warning as soon as a server supporting Pinctrl is met.
>
> > +#define GET_GROUPS_NR(x) le32_get_bits((x), GENMASK(31, 16))
> > +#define GET_PINS_NR(x) le32_get_bits((x), GENMASK(15, 0))
> > +#define GET_FUNCTIONS_NR(x) le32_get_bits((x), GENMASK(15, 0))
> > +
> > +#define EXT_NAME_FLAG(x) le32_get_bits((x), BIT(31))
> > +#define NUM_ELEMS(x) le32_get_bits((x), GENMASK(15, 0))
> > +
> > +#define REMAINING(x) le32_get_bits((x), GENMASK(31,
> 16))
> > +#define RETURNED(x) le32_get_bits((x), GENMASK(11, 0))
> > +
> > +#define CONFIG_FLAG_MASK GENMASK(19, 18)
> > +#define SELECTOR_MASK GENMASK(17, 16)
> > +#define SKIP_CONFIGS_MASK GENMASK(15, 8)
> > +#define CONFIG_TYPE_MASK GENMASK(7, 0)
> > +
> > +enum scmi_pinctrl_protocol_cmd {
> > + PINCTRL_ATTRIBUTES = 0x3,
> > + PINCTRL_LIST_ASSOCIATIONS = 0x4,
> > + PINCTRL_SETTINGS_GET = 0x5,
> > + PINCTRL_SETTINGS_CONFIGURE = 0x6,
> > + PINCTRL_REQUEST = 0x7,
> > + PINCTRL_RELEASE = 0x8,
> > + PINCTRL_NAME_GET = 0x9,
> > + PINCTRL_SET_PERMISSIONS = 0xa
> > +};
> > +
> > +struct scmi_msg_settings_conf {
> > + __le32 identifier;
> > + __le32 function_id;
> > + __le32 attributes;
> > + __le32 configs[];
> > +};
> > +
> > +struct scmi_msg_settings_get {
> > + __le32 identifier;
> > + __le32 attributes;
> > +};
> > +
> > +struct scmi_resp_settings_get {
> > + __le32 function_selected;
> > + __le32 num_configs;
> > + __le32 configs[];
> > +};
> > +
> > +struct scmi_msg_pinctrl_protocol_attributes {
> > + __le32 attributes_low;
> > + __le32 attributes_high;
> > +};
> > +
> > +struct scmi_msg_pinctrl_attributes {
> > + __le32 identifier;
> > + __le32 flags;
> > +};
> > +
> > +struct scmi_resp_pinctrl_attributes {
> > + __le32 attributes;
> > + u8 name[SCMI_SHORT_NAME_MAX_SIZE];
> > +};
> > +
> > +struct scmi_msg_pinctrl_list_assoc {
> > + __le32 identifier;
> > + __le32 flags;
> > + __le32 index;
> > +};
> > +
> > +struct scmi_resp_pinctrl_list_assoc {
> > + __le32 flags;
> > + __le16 array[];
> > +};
> > +
> > +struct scmi_msg_func_set {
> > + __le32 identifier;
> > + __le32 function_id;
> > + __le32 flags;
> > +};
> > +
>
> As said by Dan...drop this.
>
> > +struct scmi_msg_request {
> > + __le32 identifier;
> > + __le32 flags;
> > +};
> > +
> > +struct scmi_group_info {
> > + char name[SCMI_MAX_STR_SIZE];
> > + bool present;
> > + u32 *group_pins;
> > + u32 nr_pins;
> > +};
> > +
> > +struct scmi_function_info {
> > + char name[SCMI_MAX_STR_SIZE];
> > + bool present;
> > + u32 *groups;
> > + u32 nr_groups;
> > +};
> > +
> > +struct scmi_pin_info {
> > + char name[SCMI_MAX_STR_SIZE];
> > + bool present;
> > +};
> > +
> > +struct scmi_pinctrl_info {
> > + u32 version;
> > + int nr_groups;
> > + int nr_functions;
> > + int nr_pins;
> > + struct scmi_group_info *groups;
> > + struct scmi_function_info *functions;
> > + struct scmi_pin_info *pins;
> > +};
> > +
> > +static int scmi_pinctrl_attributes_get(const struct scmi_protocol_handle
> *ph,
> > + struct scmi_pinctrl_info *pi) {
> > + int ret;
> > + struct scmi_xfer *t;
> > + struct scmi_msg_pinctrl_protocol_attributes *attr;
> > +
> > + ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES, 0,
> sizeof(*attr),
> > + &t);
> > + if (ret)
> > + return ret;
> > +
> > + attr = t->rx.buf;
> > +
> > + ret = ph->xops->do_xfer(ph, t);
> > + if (!ret) {
> > + pi->nr_functions = GET_FUNCTIONS_NR(attr-
> >attributes_high);
> > + pi->nr_groups = GET_GROUPS_NR(attr->attributes_low);
> > + pi->nr_pins = GET_PINS_NR(attr->attributes_low);
>
> I was thinking, does make sense to allow a nr_pins == 0 setup to probe
> successfully ? Becasuse is legit for the platform to return zero groups or zero
> functions BUT zero pins is just useless (spec does not say
> anything)
>
> Maybe you could just put a dev_warn() here on if (nr_pins == 0) and bail out
> with -EINVAL...
ok, fix in v7.
>
> On the other side looking at the zero groups/function case, that is plausible
> and handled properly by the driver since a 0-bytes devm_kcalloc will return
> ZERO_SIZE_PTR (not NULL) and all the remaining references to pinfo->groups
> and pinfo->functions are guarded by a check on selector >= nr_groups (or >=
> nr_functions), and by scmi_pinctrl_validate_id() so the zero grouyps/fuctions
> scenarios should be safely handled.
>
> > + }
> > +
> > + ph->xops->xfer_put(ph, t);
> > + return ret;
> > +}
> > +
> > +static int scmi_pinctrl_count_get(const struct scmi_protocol_handle *ph,
> > + enum scmi_pinctrl_selector_type type) {
> > + struct scmi_pinctrl_info *pi = ph->get_priv(ph);
> > +
> > + switch (type) {
> > + case PIN_TYPE:
> > + return pi->nr_pins;
> > + case GROUP_TYPE:
> > + return pi->nr_groups;
> > + case FUNCTION_TYPE:
> > + return pi->nr_functions;
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +
> > +static int scmi_pinctrl_validate_id(const struct scmi_protocol_handle *ph,
> > + u32 identifier,
> > + enum scmi_pinctrl_selector_type type) {
> > + int value;
> > +
> > + value = scmi_pinctrl_count_get(ph, type);
> > + if (value < 0)
> > + return value;
> > +
> > + if (identifier >= value)
> > + return -EINVAL;
> > +
> > + return 0;
> > +}
> > +
> > +static int scmi_pinctrl_attributes(const struct scmi_protocol_handle *ph,
> > + enum scmi_pinctrl_selector_type type,
> > + u32 selector, char *name,
> > + u32 *n_elems)
> > +{
> > + int ret;
> > + struct scmi_xfer *t;
> > + struct scmi_msg_pinctrl_attributes *tx;
> > + struct scmi_resp_pinctrl_attributes *rx;
> > + u32 ext_name_flag;
>
> what about a bool
>
> > +
> > + if (!name)
> > + return -EINVAL;
> > +
> > + ret = scmi_pinctrl_validate_id(ph, selector, type);
> > + if (ret)
> > + return ret;
> > +
> > + ret = ph->xops->xfer_get_init(ph, PINCTRL_ATTRIBUTES, sizeof(*tx),
> > + sizeof(*rx), &t);
> > + if (ret)
> > + return ret;
> > +
> > + tx = t->tx.buf;
> > + rx = t->rx.buf;
> > + tx->identifier = cpu_to_le32(selector);
> > + tx->flags = cpu_to_le32(type);
> > +
> > + ret = ph->xops->do_xfer(ph, t);
> > + if (!ret) {
> > + if (n_elems)
> > + *n_elems = NUM_ELEMS(rx->attributes);
> > +
> > + strscpy(name, rx->name, SCMI_SHORT_NAME_MAX_SIZE);
> > +
> > + ext_name_flag = EXT_NAME_FLAG(rx->attributes);
> > + } else
> > + ext_name_flag = 0;
>
> and you dont need this else branch to set ext_name_flag to false, since down
> below you will check ext_flag ONLY if !ret, so it will have surely been set if the
> do_xfer did not fail.
>
> > +
> > + ph->xops->xfer_put(ph, t);
> > +
> > + /*
> > + * If supported overwrite short name with the extended one;
> > + * on error just carry on and use already provided short name.
> > + */
> > + if (!ret && ext_name_flag)
> > + ph->hops->extended_name_get(ph, PINCTRL_NAME_GET,
> selector,
> > + (u32 *)&type, name,
> > + SCMI_MAX_STR_SIZE);
> > + return ret;
> > +}
> > +
> > +struct scmi_pinctrl_ipriv {
> > + u32 selector;
> > + enum scmi_pinctrl_selector_type type;
> > + u32 *array;
> > +};
> > +
> > +static void iter_pinctrl_assoc_prepare_message(void *message,
> > + u32 desc_index,
> > + const void *priv)
> > +{
> > + struct scmi_msg_pinctrl_list_assoc *msg = message;
> > + const struct scmi_pinctrl_ipriv *p = priv;
> > +
> > + msg->identifier = cpu_to_le32(p->selector);
> > + msg->flags = cpu_to_le32(p->type);
> > + /* Set the number of OPPs to be skipped/already read */
>
> OPP ? .. maybe drop this comment that was cut/pasted from somewhere
> else :D
>
> > + msg->index = cpu_to_le32(desc_index); }
> > +
> > +static int iter_pinctrl_assoc_update_state(struct scmi_iterator_state *st,
> > + const void *response, void *priv)
> {
> > + const struct scmi_resp_pinctrl_list_assoc *r = response;
> > +
> > + st->num_returned = RETURNED(r->flags);
> > + st->num_remaining = REMAINING(r->flags);
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +iter_pinctrl_assoc_process_response(const struct scmi_protocol_handle
> *ph,
> > + const void *response,
> > + struct scmi_iterator_state *st, void *priv)
> {
> > + const struct scmi_resp_pinctrl_list_assoc *r = response;
> > + struct scmi_pinctrl_ipriv *p = priv;
> > +
> > + p->array[st->desc_index + st->loop_idx] =
> > + le16_to_cpu(r->array[st->loop_idx]);
> > +
> > + return 0;
> > +}
> > +
> > +static int scmi_pinctrl_list_associations(const struct scmi_protocol_handle
> *ph,
> > + u32 selector,
> > + enum scmi_pinctrl_selector_type
> type,
> > + u16 size, u32 *array)
> > +{
> > + int ret;
> > + void *iter;
> > + struct scmi_iterator_ops ops = {
> > + .prepare_message = iter_pinctrl_assoc_prepare_message,
> > + .update_state = iter_pinctrl_assoc_update_state,
> > + .process_response = iter_pinctrl_assoc_process_response,
> > + };
> > + struct scmi_pinctrl_ipriv ipriv = {
> > + .selector = selector,
> > + .type = type,
> > + .array = array,
> > + };
> > +
> > + if (!array || !size || type == PIN_TYPE)
> > + return -EINVAL;
> > +
> > + ret = scmi_pinctrl_validate_id(ph, selector, type);
> > + if (ret)
> > + return ret;
> > +
> > + iter = ph->hops->iter_response_init(ph, &ops, size,
> > + PINCTRL_LIST_ASSOCIATIONS,
> > + sizeof(struct
> scmi_msg_pinctrl_list_assoc),
> > + &ipriv);
> > +
> > + if (IS_ERR(iter))
> > + return PTR_ERR(iter);
> > +
> > + return ph->hops->iter_response_run(iter);
> > +}
> > +
> > +struct scmi_settings_get_ipriv {
> > + u32 selector;
> > + enum scmi_pinctrl_selector_type type;
> > + u32 flag;
> > + enum scmi_pinctrl_conf_type *config_types;
> > + u32 *config_values;
> > +};
> > +
> > +static void
> > +iter_pinctrl_settings_get_prepare_message(void *message, u32 desc_index,
> > + const void *priv)
> > +{
> > + struct scmi_msg_settings_get *msg = message;
> > + const struct scmi_settings_get_ipriv *p = priv;
> > + u32 attributes;
> > +
> > + attributes = FIELD_PREP(CONFIG_FLAG_MASK, p->flag) |
> > + FIELD_PREP(SELECTOR_MASK, p->type);
> > +
> > + if (p->flag == 1)
>
> A boolean like .get_all would be more clear..see down below why you dont
> need a flag 0|1|2
>
> > + attributes |= FIELD_PREP(SKIP_CONFIGS_MASK, desc_index);
> > + else if (!p->flag)
> > + attributes |= FIELD_PREP(CONFIG_TYPE_MASK, p-
> >config_types[0]);
> > +
> > + msg->attributes = cpu_to_le32(attributes);
> > + msg->identifier = cpu_to_le32(p->selector); }
> > +
> > +static int
> > +iter_pinctrl_settings_get_update_state(struct scmi_iterator_state *st,
> > + const void *response, void *priv) {
> > + const struct scmi_resp_settings_get *r = response;
> > + struct scmi_settings_get_ipriv *p = priv;
> > +
> > + if (p->flag == 1) {
>
> Ditto... see below the explanation
>
> > + st->num_returned = le32_get_bits(r->num_configs,
> GENMASK(7, 0));
> > + st->num_remaining = le32_get_bits(r->num_configs,
> > + GENMASK(31, 24));
> > + } else {
> > + st->num_returned = 1;
> > + st->num_remaining = 0;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +iter_pinctrl_settings_get_process_response(const struct
> scmi_protocol_handle *ph,
> > + const void *response,
> > + struct scmi_iterator_state *st,
> > + void *priv)
> > +{
> > + const struct scmi_resp_settings_get *r = response;
> > + struct scmi_settings_get_ipriv *p = priv;
> > +
> > + if (!p->flag) {
> > + if (p->config_types[0] !=
> > + le32_get_bits(r->configs[st->loop_idx * 2], GENMASK(7, 0)))
> > + return -EINVAL;
> > + } else if (p->flag == 1) {
> > + p->config_types[st->desc_index + st->loop_idx] =
> > + le32_get_bits(r->configs[st->loop_idx * 2],
> > + GENMASK(7, 0));
> > + } else if (p->flag == 2) {
> > + return 0;
> > + }
>
> Unneeded...see down below for explanation
>
> > +
> > + p->config_values[st->desc_index + st->loop_idx] =
> > + le32_to_cpu(r->configs[st->loop_idx * 2 + 1]);
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +scmi_pinctrl_settings_get(const struct scmi_protocol_handle *ph, u32
> selector,
> > + enum scmi_pinctrl_selector_type type,
> > + enum scmi_pinctrl_conf_type config_type,
> > + u32 *config_value)
> > +{
> > + int ret;
> > + void *iter;
> > + struct scmi_iterator_ops ops = {
> > + .prepare_message =
> iter_pinctrl_settings_get_prepare_message,
> > + .update_state = iter_pinctrl_settings_get_update_state,
> > + .process_response =
> iter_pinctrl_settings_get_process_response,
> > + };
> > + struct scmi_settings_get_ipriv ipriv = {
> > + .selector = selector,
> > + .type = type,
> > + .flag = 0,
> > + .config_types = &config_type,
> > + .config_values = config_value,
> > + };
> > +
>
> So this function is used to retrieve configs; as of now, just one, then it could
> be extended to fetch all the configs, and for this it uses the iterators helpers,
> BUT it is not and will not be used to just fetch the selected_function with
> flag_2 (even though is always provided), since in that case you wont get back
> a multi-part SCMI response and so there is no need to use iterators...
>
> IOW... no need here to handle flag_2 scenario and as a consequence I would
> change the ipriv flag to be be a boolean .get_all, like it was, since it is more
> readable (and so you wont need to add any comment..)
ok, so your suggestion is drop the iterators, and only support one config,
right?
Or keep iterators with get_all be passed as a function parameter?
>
> In the future could make sense to add here also a *selected_function output
> param to this function since you will always get it back for free when
> retrieving configs ... BUT for now is just not needed really...no users for this
> case till now...
>
> ...when the time will come that we will need a function_selected_get to be
> issued without retrieveing also the configs I would add a distinct routine that
> crafts properly a SETTINGS_GET with flag_2 without worrying about multi-
> part responses (and with no need for iterators support)
>
> Trying to handle all in here just complicates stuff...
>
> > + if (!config_value || type == FUNCTION_TYPE)
> > + return -EINVAL;
> > +
> > + ret = scmi_pinctrl_validate_id(ph, selector, type);
> > + if (ret)
> > + return ret;
> > +
> > + iter = ph->hops->iter_response_init(ph, &ops, 1,
> PINCTRL_SETTINGS_GET,
> > + sizeof(struct
> scmi_msg_settings_get),
> > + &ipriv);
> > +
> > + if (IS_ERR(iter))
> > + return PTR_ERR(iter);
> > +
> > + return ph->hops->iter_response_run(iter);
> > +}
> > +
> > +static int
> > +scmi_pinctrl_settings_conf(const struct scmi_protocol_handle *ph,
> > + u32 selector,
> > + enum scmi_pinctrl_selector_type type,
> > + u32 nr_configs,
> > + enum scmi_pinctrl_conf_type *config_type,
> > + u32 *config_value)
> > +{
> > + struct scmi_xfer *t;
> > + struct scmi_msg_settings_conf *tx;
> > + u32 attributes;
> > + int ret, i;
> > + u32 configs_in_chunk, conf_num = 0;
> > + u32 chunk;
> > + int max_msg_size = ph->hops->get_max_msg_size(ph);
> > +
> > + if (!config_type || !config_value || type == FUNCTION_TYPE)
> > + return -EINVAL;
> > +
> > + ret = scmi_pinctrl_validate_id(ph, selector, type);
> > + if (ret)
> > + return ret;
> > +
> > + configs_in_chunk = (max_msg_size - sizeof(*tx)) / (sizeof(__le32) * 2);
> > + while (conf_num < nr_configs) {
> > + chunk = (nr_configs - conf_num > configs_in_chunk) ?
> > + configs_in_chunk : nr_configs - conf_num;
> > +
> > + ret = ph->xops->xfer_get_init(ph,
> PINCTRL_SETTINGS_CONFIGURE,
> > + sizeof(*tx) +
> > + chunk * 2 * sizeof(__le32),
> > + 0, &t);
> > + if (ret)
> > + return ret;
> for consistency I would
> break;
>
> like below and you will exit always from the last return ret;
>
> > +
> > + tx = t->tx.buf;
> > + tx->identifier = cpu_to_le32(selector);
> > + attributes = FIELD_PREP(GENMASK(1, 0), type) |
> > + FIELD_PREP(GENMASK(9, 2), chunk);
> > + tx->attributes = cpu_to_le32(attributes);
> > +
> > + for (i = 0; i < chunk; i++) {
> > + tx->configs[i * 2] =
> > + cpu_to_le32(config_type[conf_num + i]);
> > + tx->configs[i * 2 + 1] =
> > + cpu_to_le32(config_value[conf_num + i]);
> > + }
> > +
> > + ret = ph->xops->do_xfer(ph, t);
> > +
> > + ph->xops->xfer_put(ph, t);
> > +
> > + if (ret)
> > + break;
> > +
> > + conf_num += chunk;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static int scmi_pinctrl_function_select(const struct scmi_protocol_handle
> *ph,
> > + u32 group,
> > + enum scmi_pinctrl_selector_type
> type,
> > + u32 function_id)
> > +{
> > + int ret;
> > + struct scmi_xfer *t;
> > + struct scmi_msg_settings_conf *tx;
> > + u32 attributes;
> > +
> > + ret = scmi_pinctrl_validate_id(ph, group, type);
> > + if (ret)
> > + return ret;
> > +
> > + ret = ph->xops->xfer_get_init(ph, PINCTRL_SETTINGS_CONFIGURE,
> > + sizeof(*tx), 0, &t);
> > + if (ret)
> > + return ret;
> > +
> > + tx = t->tx.buf;
> > + tx->identifier = cpu_to_le32(group);
> > + tx->function_id = cpu_to_le32(function_id);
> > + attributes = FIELD_PREP(GENMASK(1, 0), type) | BIT(10);
> > + tx->attributes = cpu_to_le32(attributes);
> > +
> > + ret = ph->xops->do_xfer(ph, t);
> > + ph->xops->xfer_put(ph, t);
> > +
> > + return ret;
> > +}
> > +
> > +static int scmi_pinctrl_request(const struct scmi_protocol_handle *ph,
> > + u32 identifier,
> > + enum scmi_pinctrl_selector_type type) {
> > + int ret;
> > + struct scmi_xfer *t;
> > + struct scmi_msg_request *tx;
> > +
> > + if (type == FUNCTION_TYPE)
> > + return -EINVAL;
> > +
> > + ret = scmi_pinctrl_validate_id(ph, identifier, type);
> > + if (ret)
> > + return ret;
> > +
> > + ret = ph->xops->xfer_get_init(ph, PINCTRL_REQUEST, sizeof(*tx), 0,
> &t);
> > + if (ret)
> > + return ret;
> > +
> > + tx = t->tx.buf;
> > + tx->identifier = cpu_to_le32(identifier);
> > + tx->flags = cpu_to_le32(type);
> > +
> > + ret = ph->xops->do_xfer(ph, t);
> > + ph->xops->xfer_put(ph, t);
> > +
> > + return ret;
> > +}
> > +
>
> ..this function ...
>
> > +static int scmi_pinctrl_pin_request(const struct scmi_protocol_handle *ph,
> > + u32 pin)
> > +{
> > + return scmi_pinctrl_request(ph, pin, PIN_TYPE); }
> > +
> > +static int scmi_pinctrl_free(const struct scmi_protocol_handle *ph,
> > + u32 identifier,
> > + enum scmi_pinctrl_selector_type type) {
> > + int ret;
> > + struct scmi_xfer *t;
> > + struct scmi_msg_request *tx;
> > +
> > + if (type == FUNCTION_TYPE)
> > + return -EINVAL;
> > +
> > + ret = scmi_pinctrl_validate_id(ph, identifier, type);
> > + if (ret)
> > + return ret;
> > +
> > + ret = ph->xops->xfer_get_init(ph, PINCTRL_RELEASE, sizeof(*tx), 0, &t);
> > + if (ret)
> > + return ret;
> > +
> > + tx = t->tx.buf;
> > + tx->identifier = cpu_to_le32(identifier);
> > + tx->flags = cpu_to_le32(type);
> > +
> > + ret = ph->xops->do_xfer(ph, t);
> > + ph->xops->xfer_put(ph, t);
> > +
> > + return ret;
> > +}
> > +
>
> ...and this are completely identical, beside the used command msg_id...please
> make it a common workhorse function by adding a param for the command...
>
> > +static int scmi_pinctrl_pin_free(const struct scmi_protocol_handle
> > +*ph, u32 pin) {
> > + return scmi_pinctrl_free(ph, pin, PIN_TYPE); }
> > +
>
> ...and convert these _request/_free functions into a pair odf simple wrapper
> invoking the common workhorse...
>
> > +static int scmi_pinctrl_get_group_info(const struct scmi_protocol_handle
> *ph,
> > + u32 selector,
> > + struct scmi_group_info *group) {
> > + int ret;
> > +
> > + if (!group)
> > + return -EINVAL;
> > +
> > + ret = scmi_pinctrl_attributes(ph, GROUP_TYPE, selector,
> > + group->name,
> > + &group->nr_pins);
> > + if (ret)
> > + return ret;
> > +
> > + if (!group->nr_pins) {
> > + dev_err(ph->dev, "Group %d has 0 elements", selector);
> > + return -ENODATA;
> > + }
> > +
> > + group->group_pins = kmalloc_array(group->nr_pins,
> > + sizeof(*group->group_pins),
> > + GFP_KERNEL);
> > + if (!group->group_pins)
> > + return -ENOMEM;
> > +
> > + ret = scmi_pinctrl_list_associations(ph, selector, GROUP_TYPE,
> > + group->nr_pins, group-
> >group_pins);
> > + if (ret) {
> > + kfree(group->group_pins);
> > + return ret;
> > + }
> > +
> > + group->present = true;
> > + return 0;
> > +}
> > +
> > +static int scmi_pinctrl_get_group_name(const struct scmi_protocol_handle
> *ph,
> > + u32 selector, const char **name) {
> > + struct scmi_pinctrl_info *pi = ph->get_priv(ph);
> > +
> > + if (!name)
> > + return -EINVAL;
> > +
> > + if (selector >= pi->nr_groups)
> > + return -EINVAL;
> > +
> > + if (!pi->groups[selector].present) {
> > + int ret;
> > +
> > + ret = scmi_pinctrl_get_group_info(ph, selector,
> > + &pi->groups[selector]);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + *name = pi->groups[selector].name;
> > +
> > + return 0;
> > +}
> > +
> > +static int scmi_pinctrl_group_pins_get(const struct scmi_protocol_handle
> *ph,
> > + u32 selector, const u32 **pins,
> > + u32 *nr_pins)
> > +{
> > + struct scmi_pinctrl_info *pi = ph->get_priv(ph);
> > +
> > + if (!pins || !nr_pins)
> > + return -EINVAL;
> > +
> > + if (selector >= pi->nr_groups)
> > + return -EINVAL;
> > +
> > + if (!pi->groups[selector].present) {
> > + int ret;
> > +
> > + ret = scmi_pinctrl_get_group_info(ph, selector,
> > + &pi->groups[selector]);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + *pins = pi->groups[selector].group_pins;
> > + *nr_pins = pi->groups[selector].nr_pins;
> > +
> > + return 0;
> > +}
> > +
> > +static int scmi_pinctrl_get_function_info(const struct
> scmi_protocol_handle *ph,
> > + u32 selector,
> > + struct scmi_function_info *func) {
> > + int ret;
> > +
> > + if (!func)
> > + return -EINVAL;
> > +
> > + ret = scmi_pinctrl_attributes(ph, FUNCTION_TYPE, selector,
> > + func->name,
> > + &func->nr_groups);
> > + if (ret)
> > + return ret;
> > +
> > + if (!func->nr_groups) {
> > + dev_err(ph->dev, "Function %d has 0 elements", selector);
> > + return -ENODATA;
> > + }
> > +
> > + func->groups = kmalloc_array(func->nr_groups, sizeof(*func->groups),
> > + GFP_KERNEL);
> > + if (!func->groups)
> > + return -ENOMEM;
> > +
> > + ret = scmi_pinctrl_list_associations(ph, selector, FUNCTION_TYPE,
> > + func->nr_groups, func->groups);
> > + if (ret) {
> > + kfree(func->groups);
> > + return ret;
> > + }
> > +
> > + func->present = true;
> > + return 0;
> > +}
> > +
> > +static int scmi_pinctrl_get_function_name(const struct
> scmi_protocol_handle *ph,
> > + u32 selector, const char **name) {
> > + struct scmi_pinctrl_info *pi = ph->get_priv(ph);
> > +
> > + if (!name)
> > + return -EINVAL;
> > +
> > + if (selector >= pi->nr_functions)
> > + return -EINVAL;
> > +
> > + if (!pi->functions[selector].present) {
> > + int ret;
> > +
> > + ret = scmi_pinctrl_get_function_info(ph, selector,
> > + &pi-
> >functions[selector]);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + *name = pi->functions[selector].name;
> > + return 0;
> > +}
> > +
> > +static int
> > +scmi_pinctrl_function_groups_get(const struct scmi_protocol_handle *ph,
> > + u32 selector, u32 *nr_groups,
> > + const u32 **groups)
> > +{
> > + struct scmi_pinctrl_info *pi = ph->get_priv(ph);
> > +
> > + if (!groups || !nr_groups)
> > + return -EINVAL;
> > +
> > + if (selector >= pi->nr_functions)
> > + return -EINVAL;
> > +
> > + if (!pi->functions[selector].present) {
> > + int ret;
> > +
> > + ret = scmi_pinctrl_get_function_info(ph, selector,
> > + &pi-
> >functions[selector]);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + *groups = pi->functions[selector].groups;
> > + *nr_groups = pi->functions[selector].nr_groups;
> > +
> > + return 0;
> > +}
> > +
> > +static int scmi_pinctrl_mux_set(const struct scmi_protocol_handle *ph,
> > + u32 selector, u32 group)
> > +{
> > + return scmi_pinctrl_function_select(ph, group, GROUP_TYPE,
> > +selector); }
> > +
> > +static int scmi_pinctrl_get_pin_info(const struct scmi_protocol_handle *ph,
> > + u32 selector, struct scmi_pin_info *pin) {
> > + int ret;
> > +
> > + if (!pin)
> > + return -EINVAL;
> > +
> > + ret = scmi_pinctrl_attributes(ph, PIN_TYPE, selector,
> > + pin->name, NULL);
> > + if (ret)
> > + return ret;
> > +
> > + pin->present = true;
> > + return 0;
> > +}
> > +
> > +static int scmi_pinctrl_get_pin_name(const struct scmi_protocol_handle
> *ph,
> > + u32 selector, const char **name) {
> > + struct scmi_pinctrl_info *pi = ph->get_priv(ph);
> > +
> > + if (!name)
> > + return -EINVAL;
> > +
> > + if (selector >= pi->nr_pins)
> > + return -EINVAL;
> > +
> > + if (!pi->pins[selector].present) {
> > + int ret;
> > +
> > + ret = scmi_pinctrl_get_pin_info(ph, selector,
> > + &pi->pins[selector]);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + *name = pi->pins[selector].name;
> > +
> > + return 0;
> > +}
> > +
> > +static int scmi_pinctrl_name_get(const struct scmi_protocol_handle *ph,
> > + u32 selector,
> > + enum scmi_pinctrl_selector_type type,
> > + const char **name)
> > +{
> > + switch (type) {
> > + case PIN_TYPE:
> > + return scmi_pinctrl_get_pin_name(ph, selector, name);
> > + case GROUP_TYPE:
> > + return scmi_pinctrl_get_group_name(ph, selector, name);
> > + case FUNCTION_TYPE:
> > + return scmi_pinctrl_get_function_name(ph, selector, name);
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +
> > +static const struct scmi_pinctrl_proto_ops pinctrl_proto_ops = {
> > + .count_get = scmi_pinctrl_count_get,
> > + .name_get = scmi_pinctrl_name_get,
> > + .group_pins_get = scmi_pinctrl_group_pins_get,
> > + .function_groups_get = scmi_pinctrl_function_groups_get,
> > + .mux_set = scmi_pinctrl_mux_set,
> > + .settings_get = scmi_pinctrl_settings_get,
> > + .settings_conf = scmi_pinctrl_settings_conf,
> > + .pin_request = scmi_pinctrl_pin_request,
> > + .pin_free = scmi_pinctrl_pin_free,
> > +};
> > +
> > +static int scmi_pinctrl_protocol_init(const struct
> > +scmi_protocol_handle *ph) {
> > + int ret;
> > + u32 version;
> > + struct scmi_pinctrl_info *pinfo;
> > +
> > + ret = ph->xops->version_get(ph, &version);
> > + if (ret)
> > + return ret;
> > +
> > + dev_dbg(ph->dev, "Pinctrl Version %d.%d\n",
> > + PROTOCOL_REV_MAJOR(version),
> PROTOCOL_REV_MINOR(version));
> > +
> > + pinfo = devm_kzalloc(ph->dev, sizeof(*pinfo), GFP_KERNEL);
> > + if (!pinfo)
> > + return -ENOMEM;
> > +
> > + ret = scmi_pinctrl_attributes_get(ph, pinfo);
> > + if (ret)
> > + return ret;
>
> ..as a I was saying is nr_pins == 0 the scmi_pinctrl_attributes_get could return
> -EINVAL here and bail out....not sure that a running setup with zero pins has
> any values (even for testing...) BUT, as said above, I wuld certainly add a
> dev_warn in scmi_pinctrl_attributes_get() when nr_pins == 0
Fix it in v7.
Thanks,
Peng.
>
> Thanks,
> Cristian
^ permalink raw reply
* [PATCH v4] dt-bindings: serial: actions,owl-uart: convert to dtschema
From: Kanak Shilledar @ 2024-03-31 13:28 UTC (permalink / raw)
Cc: krzysztof.kozlowski+dt, robh+dt, devicetree, daniel.baluta,
Kanak Shilledar, Krzysztof Kozlowski
From: Kanak Shilledar <kanakshilledar111@protonmail.com>
Convert the Actions Semi Owl UART to newer DT schema.
Created DT schema based on the .txt file which had
`compatible`, `reg` and `interrupts` as the
required properties. This binding is used by Actions S500, S700
and S900 SoC. S700 and S900 use the same UART compatible string.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kanak Shilledar <kanakshilledar111@protonmail.com>
---
Changes in v4
- added `clocks` property to fix warning of 'clocks' was unexpected
while running `make dtbs_check`. `clocks` property was not defined
in the original .txt file. `clocks` property is removed from the
required section.
- added `clocks` property in example
- extended the devicetree with clocks node
---
.../bindings/serial/actions,owl-uart.txt | 16 -------
.../bindings/serial/actions,owl-uart.yaml | 48 +++++++++++++++++++
2 files changed, 48 insertions(+), 16 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/serial/actions,owl-uart.txt
create mode 100644 Documentation/devicetree/bindings/serial/actions,owl-uart.yaml
diff --git a/Documentation/devicetree/bindings/serial/actions,owl-uart.txt b/Documentation/devicetree/bindings/serial/actions,owl-uart.txt
deleted file mode 100644
index aa873eada02d..000000000000
--- a/Documentation/devicetree/bindings/serial/actions,owl-uart.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Actions Semi Owl UART
-
-Required properties:
-- compatible : "actions,s500-uart", "actions,owl-uart" for S500
- "actions,s900-uart", "actions,owl-uart" for S900
-- reg : Offset and length of the register set for the device.
-- interrupts : Should contain UART interrupt.
-
-
-Example:
-
- uart3: serial@b0126000 {
- compatible = "actions,s500-uart", "actions,owl-uart";
- reg = <0xb0126000 0x1000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- };
diff --git a/Documentation/devicetree/bindings/serial/actions,owl-uart.yaml b/Documentation/devicetree/bindings/serial/actions,owl-uart.yaml
new file mode 100644
index 000000000000..ab1c4514ae93
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/actions,owl-uart.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/actions,owl-uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Actions Semi Owl UART
+
+maintainers:
+ - Kanak Shilledar <kanakshilledar111@protonmail.com>
+
+allOf:
+ - $ref: serial.yaml
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - actions,s500-uart
+ - actions,s900-uart
+ - const: actions,owl-uart
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/actions,s500-cmu.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ uart0: serial@b0126000 {
+ compatible = "actions,s500-uart", "actions,owl-uart";
+ reg = <0xb0126000 0x1000>;
+ clocks = <&cmu CLK_UART0>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.34.1
^ permalink raw reply related
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