* [PATCH v2 2/2] ASoC: dt-bindings: fsl-asoc-card: convert to YAML
From: Shengjiu Wang @ 2024-04-01 12:54 UTC (permalink / raw)
To: lgirdwood, broonie, robh+dt, krzysztof.kozlowski+dt, conor+dt,
shengjiu.wang, linux-sound, devicetree, linux-kernel, shawnguo,
s.hauer, kernel, festevam, imx, linux-arm-kernel
In-Reply-To: <1711976056-19884-1-git-send-email-shengjiu.wang@nxp.com>
Convert the fsl-asoc-card binding to YAML.
When testing dtbs_check, found below compatible strings
are not listed in document:
fsl,imx-sgtl5000
fsl,imx53-cpuvo-sgtl5000
fsl,imx51-babbage-sgtl5000
fsl,imx53-m53evk-sgtl5000
fsl,imx53-qsb-sgtl5000
fsl,imx53-voipac-sgtl5000
fsl,imx6-armadeus-sgtl5000
fsl,imx6-rex-sgtl5000
fsl,imx6-sabreauto-cs42888
fsl,imx6-wandboard-sgtl5000
fsl,imx6dl-nit6xlite-sgtl5000
fsl,imx6q-ba16-sgtl5000
fsl,imx6q-nitrogen6_max-sgtl5000
fsl,imx6q-nitrogen6_som2-sgtl5000
fsl,imx6q-nitrogen6x-sgtl5000
fsl,imx6q-sabrelite-sgtl5000
fsl,imx6q-sabresd-wm8962
fsl,imx6q-udoo-ac97
fsl,imx6q-ventana-sgtl5000
fsl,imx6sl-evk-wm8962
fsl,imx6sx-sdb-mqs
fsl,imx6sx-sdb-wm8962
fsl,imx7d-evk-wm8960
karo,tx53-audio-sgtl5000
tq,imx53-mba53-sgtl5000
So add them in yaml file to pass the test.
Also correct the 'dai-format' to 'format' in document.
For 'audio-routing', the items are not listed. Because
this fsl-asoc-card is generic driver, which supports several
codecs, if list all the items, there will be a long list.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
.../bindings/sound/fsl-asoc-card.txt | 117 -----------
.../bindings/sound/fsl-asoc-card.yaml | 195 ++++++++++++++++++
2 files changed, 195 insertions(+), 117 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/fsl-asoc-card.txt
create mode 100644 Documentation/devicetree/bindings/sound/fsl-asoc-card.yaml
diff --git a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt
deleted file mode 100644
index 4e8dbc5abfd1..000000000000
--- a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt
+++ /dev/null
@@ -1,117 +0,0 @@
-Freescale Generic ASoC Sound Card with ASRC support
-
-The Freescale Generic ASoC Sound Card can be used, ideally, for all Freescale
-SoCs connecting with external CODECs.
-
-The idea of this generic sound card is a bit like ASoC Simple Card. However,
-for Freescale SoCs (especially those released in recent years), most of them
-have ASRC (Documentation/devicetree/bindings/sound/fsl,asrc.txt) inside. And
-this is a specific feature that might be painstakingly controlled and merged
-into the Simple Card.
-
-So having this generic sound card allows all Freescale SoC users to benefit
-from the simplification of a new card support and the capability of the wide
-sample rates support through ASRC.
-
-Note: The card is initially designed for those sound cards who use AC'97, I2S
- and PCM DAI formats. However, it'll be also possible to support those non
- AC'97/I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, as
- long as the driver has been properly upgraded.
-
-
-The compatible list for this generic sound card currently:
- "fsl,imx-audio-ac97"
-
- "fsl,imx-audio-cs42888"
-
- "fsl,imx-audio-cs427x"
- (compatible with CS4271 and CS4272)
-
- "fsl,imx-audio-wm8962"
-
- "fsl,imx-audio-sgtl5000"
- (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt)
-
- "fsl,imx-audio-wm8960"
-
- "fsl,imx-audio-mqs"
-
- "fsl,imx-audio-wm8524"
-
- "fsl,imx-audio-tlv320aic32x4"
-
- "fsl,imx-audio-tlv320aic31xx"
-
- "fsl,imx-audio-si476x"
-
- "fsl,imx-audio-wm8958"
-
- "fsl,imx-audio-nau8822"
-
-Required properties:
-
- - compatible : Contains one of entries in the compatible list.
-
- - model : The user-visible name of this sound complex
-
- - audio-cpu : The phandle of an CPU DAI controller
-
- - audio-codec : The phandle of an audio codec
-
-Optional properties:
-
- - audio-asrc : The phandle of ASRC. It can be absent if there's no
- need to add ASRC support via DPCM.
-
- - audio-routing : A list of the connections between audio components.
- Each entry is a pair of strings, the first being the
- connection's sink, the second being the connection's
- source. There're a few pre-designed board connectors:
- * Line Out Jack
- * Line In Jack
- * Headphone Jack
- * Mic Jack
- * Ext Spk
- * AMIC (stands for Analog Microphone Jack)
- * DMIC (stands for Digital Microphone Jack)
-
- Note: The "Mic Jack" and "AMIC" are redundant while
- coexisting in order to support the old bindings
- of wm8962 and sgtl5000.
-
- - hp-det-gpio : The GPIO that detect headphones are plugged in
- - mic-det-gpio : The GPIO that detect microphones are plugged in
- - bitclock-master : Indicates dai-link bit clock master; for details see simple-card.yaml.
- - frame-master : Indicates dai-link frame master; for details see simple-card.yaml.
- - dai-format : audio format, for details see simple-card.yaml.
- - frame-inversion : dai-link uses frame clock inversion, for details see simple-card.yaml.
- - bitclock-inversion : dai-link uses bit clock inversion, for details see simple-card.yaml.
- - mclk-id : main clock id, specific for each card configuration.
-
-Optional unless SSI is selected as a CPU DAI:
-
- - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
-
- - mux-ext-port : The external port of the i.MX audio muxer
-
-Example:
-sound-cs42888 {
- compatible = "fsl,imx-audio-cs42888";
- model = "cs42888-audio";
- audio-cpu = <&esai>;
- audio-asrc = <&asrc>;
- audio-codec = <&cs42888>;
- audio-routing =
- "Line Out Jack", "AOUT1L",
- "Line Out Jack", "AOUT1R",
- "Line Out Jack", "AOUT2L",
- "Line Out Jack", "AOUT2R",
- "Line Out Jack", "AOUT3L",
- "Line Out Jack", "AOUT3R",
- "Line Out Jack", "AOUT4L",
- "Line Out Jack", "AOUT4R",
- "AIN1L", "Line In Jack",
- "AIN1R", "Line In Jack",
- "AIN2L", "Line In Jack",
- "AIN2R", "Line In Jack";
-};
diff --git a/Documentation/devicetree/bindings/sound/fsl-asoc-card.yaml b/Documentation/devicetree/bindings/sound/fsl-asoc-card.yaml
new file mode 100644
index 000000000000..42ca39eebd49
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl-asoc-card.yaml
@@ -0,0 +1,195 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl-asoc-card.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Generic ASoC Sound Card with ASRC support
+
+description:
+ The Freescale Generic ASoC Sound Card can be used, ideally,
+ for all Freescale SoCs connecting with external CODECs.
+
+ The idea of this generic sound card is a bit like ASoC Simple Card.
+ However, for Freescale SoCs (especially those released in recent years),
+ most of them have ASRC inside. And this is a specific feature that might
+ be painstakingly controlled and merged into the Simple Card.
+
+ So having this generic sound card allows all Freescale SoC users to
+ benefit from the simplification of a new card support and the capability
+ of the wide sample rates support through ASRC.
+
+ Note, The card is initially designed for those sound cards who use AC'97, I2S
+ and PCM DAI formats. However, it'll be also possible to support those non
+ AC'97/I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, as
+ long as the driver has been properly upgraded.
+
+maintainers:
+ - Shengjiu Wang <shengjiu.wang@nxp.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,imx-sgtl5000
+ - fsl,imx53-cpuvo-sgtl5000
+ - fsl,imx51-babbage-sgtl5000
+ - fsl,imx53-m53evk-sgtl5000
+ - fsl,imx53-qsb-sgtl5000
+ - fsl,imx53-voipac-sgtl5000
+ - fsl,imx6-armadeus-sgtl5000
+ - fsl,imx6-rex-sgtl5000
+ - fsl,imx6-sabreauto-cs42888
+ - fsl,imx6-wandboard-sgtl5000
+ - fsl,imx6dl-nit6xlite-sgtl5000
+ - fsl,imx6q-ba16-sgtl5000
+ - fsl,imx6q-nitrogen6_max-sgtl5000
+ - fsl,imx6q-nitrogen6_som2-sgtl5000
+ - fsl,imx6q-nitrogen6x-sgtl5000
+ - fsl,imx6q-sabrelite-sgtl5000
+ - fsl,imx6q-sabresd-wm8962
+ - fsl,imx6q-udoo-ac97
+ - fsl,imx6q-ventana-sgtl5000
+ - fsl,imx6sl-evk-wm8962
+ - fsl,imx6sx-sdb-mqs
+ - fsl,imx6sx-sdb-wm8962
+ - fsl,imx7d-evk-wm8960
+ - karo,tx53-audio-sgtl5000
+ - tq,imx53-mba53-sgtl5000
+ - enum:
+ - fsl,imx-audio-ac97
+ - fsl,imx-audio-cs42888
+ - fsl,imx-audio-mqs
+ - fsl,imx-audio-sgtl5000
+ - fsl,imx-audio-wm8960
+ - fsl,imx-audio-wm8962
+ - items:
+ - enum:
+ - fsl,imx-audio-ac97
+ - fsl,imx-audio-cs42888
+ - fsl,imx-audio-cs427x
+ - fsl,imx-audio-mqs
+ - fsl,imx-audio-nau8822
+ - fsl,imx-audio-sgtl5000
+ - fsl,imx-audio-si476x
+ - fsl,imx-audio-tlv320aic31xx
+ - fsl,imx-audio-tlv320aic32x4
+ - fsl,imx-audio-wm8524
+ - fsl,imx-audio-wm8960
+ - fsl,imx-audio-wm8962
+ - fsl,imx-audio-wm8958
+
+ model:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: The user-visible name of this sound complex
+
+ audio-asrc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The phandle of ASRC. It can be absent if there's no
+ need to add ASRC support via DPCM.
+
+ audio-codec:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of an audio codec
+
+ audio-cpu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of an CPU DAI controller
+
+ audio-routing:
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ description:
+ A list of the connections between audio components. Each entry is a
+ pair of strings, the first being the connection's sink, the second
+ being the connection's source. There're a few pre-designed board
+ connectors. "AMIC" stands for Analog Microphone Jack.
+ "DMIC" stands for Digital Microphone Jack. The "Mic Jack" and "AMIC"
+ are redundant while coexisting in order to support the old bindings
+ of wm8962 and sgtl5000.
+
+ hp-det-gpio:
+ deprecated: true
+ maxItems: 1
+ description: The GPIO that detect headphones are plugged in
+
+ hp-det-gpios:
+ maxItems: 1
+ description: The GPIO that detect headphones are plugged in
+
+ mic-det-gpio:
+ deprecated: true
+ maxItems: 1
+ description: The GPIO that detect microphones are plugged in
+
+ mic-det-gpios:
+ maxItems: 1
+ description: The GPIO that detect microphones are plugged in
+
+ bitclock-master:
+ $ref: simple-card.yaml#/definitions/bitclock-master
+ description: Indicates dai-link bit clock master.
+
+ frame-master:
+ $ref: simple-card.yaml#/definitions/frame-master
+ description: Indicates dai-link frame master.
+
+ format:
+ $ref: simple-card.yaml#/definitions/format
+ description: audio format.
+
+ frame-inversion:
+ $ref: simple-card.yaml#/definitions/frame-inversion
+ description: dai-link uses frame clock inversion.
+
+ bitclock-inversion:
+ $ref: simple-card.yaml#/definitions/bitclock-inversion
+ description: dai-link uses bit clock inversion.
+
+ mclk-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: main clock id, specific for each card configuration.
+
+ mux-int-port:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 7]
+ description: The internal port of the i.MX audio muxer (AUDMUX)
+
+ mux-ext-port:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [3, 4, 5, 6]
+ description: The external port of the i.MX audio muxer
+
+ ssi-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of an CPU DAI controller
+
+required:
+ - compatible
+ - model
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ sound-cs42888 {
+ compatible = "fsl,imx-audio-cs42888";
+ model = "cs42888-audio";
+ audio-cpu = <&esai>;
+ audio-asrc = <&asrc>;
+ audio-codec = <&cs42888>;
+ audio-routing =
+ "Line Out Jack", "AOUT1L",
+ "Line Out Jack", "AOUT1R",
+ "Line Out Jack", "AOUT2L",
+ "Line Out Jack", "AOUT2R",
+ "Line Out Jack", "AOUT3L",
+ "Line Out Jack", "AOUT3R",
+ "Line Out Jack", "AOUT4L",
+ "Line Out Jack", "AOUT4R",
+ "AIN1L", "Line In Jack",
+ "AIN1R", "Line In Jack",
+ "AIN2L", "Line In Jack",
+ "AIN2R", "Line In Jack";
+ };
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/2] ARM: dts: imx6sx-nitrogen6sx: drop incorrect cpu-dai property
From: Shengjiu Wang @ 2024-04-01 12:54 UTC (permalink / raw)
To: lgirdwood, broonie, robh+dt, krzysztof.kozlowski+dt, conor+dt,
shengjiu.wang, linux-sound, devicetree, linux-kernel, shawnguo,
s.hauer, kernel, festevam, imx, linux-arm-kernel
In-Reply-To: <1711976056-19884-1-git-send-email-shengjiu.wang@nxp.com>
drop incorrect cpu-dai property, change it to ssi-controller
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts
index cd9cbc9ccc9e..b82d91a7d76d 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts
@@ -83,7 +83,7 @@ reg_wlan: regulator-wlan {
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx6sx-nitrogen6sx-sgtl5000";
- cpu-dai = <&ssi1>;
+ ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
--
2.34.1
^ permalink raw reply related
* [PATCH v2 0/2] ASoC: dt-bindings: convert fsl-asoc-card.txt to YAML
From: Shengjiu Wang @ 2024-04-01 12:54 UTC (permalink / raw)
To: lgirdwood, broonie, robh+dt, krzysztof.kozlowski+dt, conor+dt,
shengjiu.wang, linux-sound, devicetree, linux-kernel, shawnguo,
s.hauer, kernel, festevam, imx, linux-arm-kernel
Convert fsl-asoc-card.txt to YAML. In order to pass the checking,
add some used compatible string from devicetree.
change cpu-dai in imx6sx-nitrogen6sx to ssi-controller.
changes in v2:
- update commit message for reason why add compatible strings
which are not in txt file.
- add deprecated
- add $ref for bitclock-master and others.
Shengjiu Wang (2):
ARM: dts: imx6sx-nitrogen6sx: drop incorrect cpu-dai property
ASoC: dt-bindings: fsl-asoc-card: convert to YAML
.../bindings/sound/fsl-asoc-card.txt | 117 -----------
.../bindings/sound/fsl-asoc-card.yaml | 195 ++++++++++++++++++
.../boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts | 2 +-
3 files changed, 196 insertions(+), 118 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/fsl-asoc-card.txt
create mode 100644 Documentation/devicetree/bindings/sound/fsl-asoc-card.yaml
--
2.34.1
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: arm: qcom: Document the Samsung Galaxy Z Fold5
From: Rob Herring @ 2024-04-01 13:05 UTC (permalink / raw)
To: Alexandru Marc Serdeliuc
Cc: devicetree, linux-arm-msm, Bjorn Andersson, linux-kernel,
Conor Dooley, Krzysztof Kozlowski, Konrad Dybcio
In-Reply-To: <20240331-samsung-galaxy-zfold5-q5q-v3-1-17ae8d0a9fba@yahoo.com>
On Sun, 31 Mar 2024 12:56:39 +0200, Alexandru Marc Serdeliuc wrote:
> This documents Samsung Galaxy Z Fold5 (samsung,q5q)
> which is a foldable phone by Samsung based on the sm8550 SoC.
>
> Signed-off-by: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v5 1/2] dt-bindings: backlight: Add Texas Instruments LM3509
From: Rob Herring @ 2024-04-01 13:03 UTC (permalink / raw)
To: Patrick Gansterer
Cc: dri-devel, linux-leds, devicetree, linux-kernel, linux-fbdev,
Lee Jones, Daniel Thompson, Jingoo Han, Pavel Machek,
Krzysztof Kozlowski, Conor Dooley, Helge Deller, Sam Ravnborg,
Krzysztof Kozlowski
In-Reply-To: <20240330145931.729116-2-paroga@paroga.com>
On Sat, Mar 30, 2024 at 03:59:24PM +0100, Patrick Gansterer wrote:
> Add Device Tree bindings for Texas Instruments LM3509 - a
> High Efficiency Boost for White LED's and/or OLED Displays
>
> Signed-off-by: Patrick Gansterer <paroga@paroga.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
> ---
> .../bindings/leds/backlight/ti,lm3509.yaml | 139 ++++++++++++++++++
> 1 file changed, 139 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/leds/backlight/ti,lm3509.yaml
>
> diff --git a/Documentation/devicetree/bindings/leds/backlight/ti,lm3509.yaml b/Documentation/devicetree/bindings/leds/backlight/ti,lm3509.yaml
> new file mode 100644
> index 000000000000..b67f67648852
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/leds/backlight/ti,lm3509.yaml
> @@ -0,0 +1,139 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/leds/backlight/ti,lm3509.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: TI LM3509 High Efficiency Boost for White LED's and/or OLED Displays
> +
> +maintainers:
> + - Patrick Gansterer <paroga@paroga.com>
> +
> +description:
> + The LM3509 current mode boost converter offers two separate outputs.
> + https://www.ti.com/product/LM3509
> +
> +properties:
> + compatible:
> + const: ti,lm3509
> +
> + reg:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> + reset-gpios:
> + maxItems: 1
> +
> + ti,brightness-rate-of-change-us:
> + description: Brightness Rate of Change in microseconds.
> + enum: [51, 13000, 26000, 52000]
> +
> + ti,oled-mode:
> + description: Enable OLED mode.
> + type: boolean
> +
> +patternProperties:
> + "^led@[01]$":
> + type: object
> + description: Properties for a string of connected LEDs.
> +
> + allOf:
You don't need allOf here.
> + - $ref: common.yaml#
> +
> + properties:
> + reg:
> + description:
> + The control register that is used to program the two current sinks.
> + The LM3509 has two registers (BMAIN and BSUB) and are represented
> + as 0 or 1 in this property. The two current sinks can be controlled
> + independently with both registers, or register BMAIN can be
> + configured to control both sinks with the led-sources property.
> + minimum: 0
> + maximum: 1
> +
> + label: true
> +
> + led-sources:
> + allOf:
Or here.
> + - minItems: 1
> + maxItems: 2
> + items:
> + minimum: 0
> + maximum: 1
^ permalink raw reply
* [PATCH v2 2/2] arm64: dts: qcom: sm8150: Add video clock controller node
From: Satya Priya Kakitapalli @ 2024-04-01 11:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd
Cc: Dmitry Baryshkov, Ajit Pandey, Imran Shaik, Taniya Das,
Jagadeesh Kona, linux-arm-msm, devicetree, linux-kernel,
linux-clk, Satya Priya Kakitapalli
In-Reply-To: <20240401-videocc-sm8150-dt-node-v2-0-3b87cd2add96@quicinc.com>
Add device node for video clock controller on Qualcomm
SM8150 platform.
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8155p.dtsi | 4 ++++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 13 +++++++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8155p.dtsi b/arch/arm64/boot/dts/qcom/sa8155p.dtsi
index ffb7ab695213..9e70effc72e1 100644
--- a/arch/arm64/boot/dts/qcom/sa8155p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8155p.dtsi
@@ -38,3 +38,7 @@ &rpmhpd {
*/
compatible = "qcom,sa8155p-rpmhpd";
};
+
+&videocc {
+ power-domains = <&rpmhpd SA8155P_CX>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index a35c0852b5a1..56694efa0c33 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
+#include <dt-bindings/clock/qcom,videocc-sm8150.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8150.h>
#include <dt-bindings/thermal/thermal.h>
@@ -3715,6 +3716,18 @@ usb_2_dwc3: usb@a800000 {
};
};
+ videocc: clock-controller@ab00000 {
+ compatible = "qcom,sm8150-videocc";
+ reg = <0 0x0ab00000 0 0x10000>;
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "bi_tcxo";
+ power-domains = <&rpmhpd SM8150_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
camnoc_virt: interconnect@ac00000 {
compatible = "qcom,sm8150-camnoc-virt";
reg = <0 0x0ac00000 0 0x1000>;
--
2.25.1
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: clock: qcom: Update SM8150 videocc bindings
From: Satya Priya Kakitapalli @ 2024-04-01 11:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd
Cc: Dmitry Baryshkov, Ajit Pandey, Imran Shaik, Taniya Das,
Jagadeesh Kona, linux-arm-msm, devicetree, linux-kernel,
linux-clk, Satya Priya Kakitapalli
In-Reply-To: <20240401-videocc-sm8150-dt-node-v2-0-3b87cd2add96@quicinc.com>
Update the clocks list for SM8150 to add both AHB and XO clocks,
as it needs both of them.
Fixes: 35d26e9292e2 ("dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings")
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
.../devicetree/bindings/clock/qcom,videocc.yaml | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
index 6999e36ace1b..68bac801adb0 100644
--- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
@@ -75,7 +75,6 @@ allOf:
enum:
- qcom,sc7180-videocc
- qcom,sdm845-videocc
- - qcom,sm8150-videocc
then:
properties:
clocks:
@@ -101,6 +100,22 @@ allOf:
- const: bi_tcxo
- const: bi_tcxo_ao
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sm8150-videocc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: AHB
+ - description: Board XO source
+ clock-names:
+ items:
+ - const: iface
+ - const: bi_tcxo
+
- if:
properties:
compatible:
--
2.25.1
^ permalink raw reply related
* [PATCH v2 0/2] Add DT support for video clock controller on SM8150
From: Satya Priya Kakitapalli @ 2024-04-01 11:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Michael Turquette, Stephen Boyd
Cc: Dmitry Baryshkov, Ajit Pandey, Imran Shaik, Taniya Das,
Jagadeesh Kona, linux-arm-msm, devicetree, linux-kernel,
linux-clk, Satya Priya Kakitapalli
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
Changes in v2:
- As per Dmitry's comments, there is no need to update to index based
lookup for already existing drivers, hence keeping clock-names property.
- Updated the videocc bindings to add AHB clock for the sm8150 platform.
- Link to v1: https://lore.kernel.org/r/20240313-videocc-sm8150-dt-node-v1-0-ae8ec3c822c2@quicinc.com
---
Satya Priya Kakitapalli (2):
dt-bindings: clock: qcom: Update SM8150 videocc bindings
arm64: dts: qcom: sm8150: Add video clock controller node
.../devicetree/bindings/clock/qcom,videocc.yaml | 17 ++++++++++++++++-
arch/arm64/boot/dts/qcom/sa8155p.dtsi | 4 ++++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 13 +++++++++++++
3 files changed, 33 insertions(+), 1 deletion(-)
---
base-commit: 8ffc8b1bbd505e27e2c8439d326b6059c906c9dd
change-id: 20240308-videocc-sm8150-dt-node-6f163b492f7c
Best regards,
--
Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
^ permalink raw reply
* Re: [PATCH v7 2/2] dmaengine: Loongson1: Add Loongson-1 APB DMA driver
From: Keguang Zhang @ 2024-04-01 11:09 UTC (permalink / raw)
To: Huacai Chen
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-mips, dmaengine, devicetree, linux-kernel
In-Reply-To: <CAAhV-H63wMMhVng=kn+XOHFL8sTchtGAMae0v50FEN6TO1kAhw@mail.gmail.com>
On Mon, Apr 1, 2024 at 5:06 PM Huacai Chen <chenhuacai@kernel.org> wrote:
>
> On Mon, Apr 1, 2024 at 10:45 AM Keguang Zhang <keguang.zhang@gmail.com> wrote:
> >
> > Hi Huacai,
> >
> > On Sat, Mar 30, 2024 at 9:59 PM Huacai Chen <chenhuacai@kernel.org> wrote:
> > >
> > > Hi, Keguang,
> > >
> > > On Fri, Mar 29, 2024 at 7:28 PM Keguang Zhang via B4 Relay
> > > <devnull+keguang.zhang.gmail.com@kernel.org> wrote:
> > > >
> > > > From: Keguang Zhang <keguang.zhang@gmail.com>
> > > >
> > > > This patch adds APB DMA driver for Loongson-1 SoCs.
> > > >
> > > > Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
> > > > ---
> > > > Changes in v7:
> > > > - Change the comptible to 'loongson,ls1*-apbdma'
> > > > - Update Kconfig and Makefile accordingly
> > > > - Rename the file to loongson1-apb-dma.c to keep the consistency
> > > >
> > > > Changes in v6:
> > > > - Implement .device_prep_dma_cyclic for Loongson1 audio driver,
> > > > - as well as .device_pause and .device_resume.
> > > > - Set the limitation LS1X_DMA_MAX_DESC and put all descriptors
> > > > - into one page to save memory
> > > > - Move dma_pool_zalloc() into ls1x_dma_alloc_desc()
> > > > - Drop dma_slave_config structure
> > > > - Use .remove_new instead of .remove
> > > > - Use KBUILD_MODNAME for the driver name
> > > > - Improve the debug information
> > > >
> > > > Changes in v5:
> > > > - Add DT support
> > > > - Use DT data instead of platform data
> > > > - Use chan_id of struct dma_chan instead of own id
> > > > - Use of_dma_xlate_by_chan_id() instead of ls1x_dma_filter()
> > > > - Update the author information to my official name
> > > >
> > > > Changes in v4:
> > > > - Use dma_slave_map to find the proper channel.
> > > > - Explicitly call devm_request_irq() and tasklet_kill().
> > > > - Fix namespace issue.
> > > > - Some minor fixes and cleanups.
> > > >
> > > > Changes in v3:
> > > > - Rename ls1x_dma_filter_fn to ls1x_dma_filter.
> > > >
> > > > Changes in v2:
> > > > - Change the config from 'DMA_LOONGSON1' to 'LOONGSON1_DMA',
> > > > - and rearrange it in alphabetical order in Kconfig and Makefile.
> > > > - Fix comment style.
> > > > ---
> > > > drivers/dma/Kconfig | 9 +
> > > > drivers/dma/Makefile | 1 +
> > > > drivers/dma/loongson1-apb-dma.c | 665 ++++++++++++++++++++++++++++++++++++++++
> > > > 3 files changed, 675 insertions(+)
> > > >
> > > > diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> > > > index 002a5ec80620..f7b06c4cdf3f 100644
> > > > --- a/drivers/dma/Kconfig
> > > > +++ b/drivers/dma/Kconfig
> > > > @@ -369,6 +369,15 @@ config K3_DMA
> > > > Support the DMA engine for Hisilicon K3 platform
> > > > devices.
> > > >
> > > > +config LOONGSON1_APB_DMA
> > > > + tristate "Loongson1 APB DMA support"
> > > > + depends on MACH_LOONGSON32 || COMPILE_TEST
> > > > + select DMA_ENGINE
> > > > + select DMA_VIRTUAL_CHANNELS
> > > > + help
> > > > + This selects support for the APB DMA controller in Loongson1 SoCs,
> > > > + which is required by Loongson1 NAND and audio support.
> > > Why not rename to LS1X_APB_DMA and put it just before LS2X_APB_DMA
> > > (and also the driver file name)?
> > >
> > So far all Kconfig entries of Loongson-1 drivers are named with the
> > keyword "LOONGSON1".
> > The same is true for these file names.
> > Therefore, I need to keep the consistency.
> But I see LS1X_IRQ in drivers/irqchip/Kconfig
>
Indeed, that's an exception, which was submitted by Jiaxun several years ago.
Actually, most drivers of Loongson family use the keyword "LOONGSON"
for Kconfig and "loongson" for filename.
Thus I take this keywork as the naming convention.
> Huacai
>
> >
> >
> > > Huacai
> > >
> > > > +
> > > > config LPC18XX_DMAMUX
> > > > bool "NXP LPC18xx/43xx DMA MUX for PL080"
> > > > depends on ARCH_LPC18XX || COMPILE_TEST
> > > > diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> > > > index dfd40d14e408..b26f6677978a 100644
> > > > --- a/drivers/dma/Makefile
> > > > +++ b/drivers/dma/Makefile
> > > > @@ -47,6 +47,7 @@ obj-$(CONFIG_INTEL_IDMA64) += idma64.o
> > > > obj-$(CONFIG_INTEL_IOATDMA) += ioat/
> > > > obj-y += idxd/
> > > > obj-$(CONFIG_K3_DMA) += k3dma.o
> > > > +obj-$(CONFIG_LOONGSON1_APB_DMA) += loongson1-apb-dma.o
> > > > obj-$(CONFIG_LPC18XX_DMAMUX) += lpc18xx-dmamux.o
> > > > obj-$(CONFIG_LS2X_APB_DMA) += ls2x-apb-dma.o
> > > > obj-$(CONFIG_MILBEAUT_HDMAC) += milbeaut-hdmac.o
> > > > diff --git a/drivers/dma/loongson1-apb-dma.c b/drivers/dma/loongson1-apb-dma.c
> > > > new file mode 100644
> > > > index 000000000000..d474a2601e6e
> > > > --- /dev/null
> > > > +++ b/drivers/dma/loongson1-apb-dma.c
> > > > @@ -0,0 +1,665 @@
> > > > +// SPDX-License-Identifier: GPL-2.0-or-later
> > > > +/*
> > > > + * Driver for Loongson-1 APB DMA Controller
> > > > + *
> > > > + * Copyright (C) 2015-2024 Keguang Zhang <keguang.zhang@gmail.com>
> > > > + */
> > > > +
> > > > +#include <linux/dmapool.h>
> > > > +#include <linux/dma-mapping.h>
> > > > +#include <linux/init.h>
> > > > +#include <linux/interrupt.h>
> > > > +#include <linux/iopoll.h>
> > > > +#include <linux/module.h>
> > > > +#include <linux/of.h>
> > > > +#include <linux/of_dma.h>
> > > > +#include <linux/platform_device.h>
> > > > +#include <linux/slab.h>
> > > > +
> > > > +#include "dmaengine.h"
> > > > +#include "virt-dma.h"
> > > > +
> > > > +/* Loongson-1 DMA Control Register */
> > > > +#define DMA_CTRL 0x0
> > > > +
> > > > +/* DMA Control Register Bits */
> > > > +#define DMA_STOP BIT(4)
> > > > +#define DMA_START BIT(3)
> > > > +#define DMA_ASK_VALID BIT(2)
> > > > +
> > > > +#define DMA_ADDR_MASK GENMASK(31, 6)
> > > > +
> > > > +/* DMA Next Field Bits */
> > > > +#define DMA_NEXT_VALID BIT(0)
> > > > +
> > > > +/* DMA Command Field Bits */
> > > > +#define DMA_RAM2DEV BIT(12)
> > > > +#define DMA_INT BIT(1)
> > > > +#define DMA_INT_MASK BIT(0)
> > > > +
> > > > +#define LS1X_DMA_MAX_CHANNELS 3
> > > > +
> > > > +/* Size of allocations for hardware descriptors */
> > > > +#define LS1X_DMA_DESCS_SIZE PAGE_SIZE
> > > > +#define LS1X_DMA_MAX_DESC \
> > > > + (LS1X_DMA_DESCS_SIZE / sizeof(struct ls1x_dma_hwdesc))
> > > > +
> > > > +struct ls1x_dma_hwdesc {
> > > > + u32 next; /* next descriptor address */
> > > > + u32 saddr; /* memory DMA address */
> > > > + u32 daddr; /* device DMA address */
> > > > + u32 length;
> > > > + u32 stride;
> > > > + u32 cycles;
> > > > + u32 cmd;
> > > > + u32 stats;
> > > > +};
> > > > +
> > > > +struct ls1x_dma_desc {
> > > > + struct virt_dma_desc vdesc;
> > > > + enum dma_transfer_direction dir;
> > > > + enum dma_transaction_type type;
> > > > + unsigned int bus_width;
> > > > +
> > > > + unsigned int nr_descs; /* number of descriptors */
> > > > +
> > > > + struct ls1x_dma_hwdesc *hwdesc;
> > > > + dma_addr_t hwdesc_phys;
> > > > +};
> > > > +
> > > > +struct ls1x_dma_chan {
> > > > + struct virt_dma_chan vchan;
> > > > + struct dma_pool *desc_pool;
> > > > + phys_addr_t src_addr;
> > > > + phys_addr_t dst_addr;
> > > > + enum dma_slave_buswidth src_addr_width;
> > > > + enum dma_slave_buswidth dst_addr_width;
> > > > +
> > > > + void __iomem *reg_base;
> > > > + int irq;
> > > > +
> > > > + struct ls1x_dma_desc *desc;
> > > > +
> > > > + struct ls1x_dma_hwdesc *curr_hwdesc;
> > > > + dma_addr_t curr_hwdesc_phys;
> > > > +};
> > > > +
> > > > +struct ls1x_dma {
> > > > + struct dma_device ddev;
> > > > + void __iomem *reg_base;
> > > > +
> > > > + unsigned int nr_chans;
> > > > + struct ls1x_dma_chan chan[];
> > > > +};
> > > > +
> > > > +#define to_ls1x_dma_chan(dchan) \
> > > > + container_of(dchan, struct ls1x_dma_chan, vchan.chan)
> > > > +
> > > > +#define to_ls1x_dma_desc(vd) \
> > > > + container_of(vd, struct ls1x_dma_desc, vdesc)
> > > > +
> > > > +/* macros for registers read/write */
> > > > +#define chan_readl(chan, off) \
> > > > + readl((chan)->reg_base + (off))
> > > > +
> > > > +#define chan_writel(chan, off, val) \
> > > > + writel((val), (chan)->reg_base + (off))
> > > > +
> > > > +static inline struct device *chan2dev(struct dma_chan *chan)
> > > > +{
> > > > + return &chan->dev->device;
> > > > +}
> > > > +
> > > > +static inline int ls1x_dma_query(struct ls1x_dma_chan *chan,
> > > > + dma_addr_t *hwdesc_phys)
> > > > +{
> > > > + struct dma_chan *dchan = &chan->vchan.chan;
> > > > + int val, ret;
> > > > +
> > > > + val = *hwdesc_phys & DMA_ADDR_MASK;
> > > > + val |= DMA_ASK_VALID;
> > > > + val |= dchan->chan_id;
> > > > + chan_writel(chan, DMA_CTRL, val);
> > > > + ret = readl_poll_timeout_atomic(chan->reg_base + DMA_CTRL, val,
> > > > + !(val & DMA_ASK_VALID), 0, 3000);
> > > > + if (ret)
> > > > + dev_err(chan2dev(dchan), "failed to query DMA\n");
> > > > +
> > > > + return ret;
> > > > +}
> > > > +
> > > > +static inline int ls1x_dma_start(struct ls1x_dma_chan *chan,
> > > > + dma_addr_t *hwdesc_phys)
> > > > +{
> > > > + struct dma_chan *dchan = &chan->vchan.chan;
> > > > + int val, ret;
> > > > +
> > > > + dev_dbg(chan2dev(dchan), "cookie=%d, starting hwdesc=%x\n",
> > > > + dchan->cookie, *hwdesc_phys);
> > > > +
> > > > + val = *hwdesc_phys & DMA_ADDR_MASK;
> > > > + val |= DMA_START;
> > > > + val |= dchan->chan_id;
> > > > + chan_writel(chan, DMA_CTRL, val);
> > > > + ret = readl_poll_timeout(chan->reg_base + DMA_CTRL, val,
> > > > + !(val & DMA_START), 0, 3000);
> > > > + if (ret)
> > > > + dev_err(chan2dev(dchan), "failed to start DMA\n");
> > > > +
> > > > + return ret;
> > > > +}
> > > > +
> > > > +static inline void ls1x_dma_stop(struct ls1x_dma_chan *chan)
> > > > +{
> > > > + chan_writel(chan, DMA_CTRL, chan_readl(chan, DMA_CTRL) | DMA_STOP);
> > > > +}
> > > > +
> > > > +static void ls1x_dma_free_chan_resources(struct dma_chan *dchan)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > +
> > > > + dma_free_coherent(chan2dev(dchan), sizeof(struct ls1x_dma_hwdesc),
> > > > + chan->curr_hwdesc, chan->curr_hwdesc_phys);
> > > > + vchan_free_chan_resources(&chan->vchan);
> > > > + dma_pool_destroy(chan->desc_pool);
> > > > + chan->desc_pool = NULL;
> > > > +}
> > > > +
> > > > +static int ls1x_dma_alloc_chan_resources(struct dma_chan *dchan)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > +
> > > > + chan->desc_pool = dma_pool_create(dma_chan_name(dchan),
> > > > + chan2dev(dchan),
> > > > + sizeof(struct ls1x_dma_hwdesc),
> > > > + __alignof__(struct ls1x_dma_hwdesc),
> > > > + 0);
> > > > + if (!chan->desc_pool)
> > > > + return -ENOMEM;
> > > > +
> > > > + /* allocate memory for querying current HW descriptor */
> > > > + dma_set_coherent_mask(chan2dev(dchan), DMA_BIT_MASK(32));
> > > > + chan->curr_hwdesc = dma_alloc_coherent(chan2dev(dchan),
> > > > + sizeof(struct ls1x_dma_hwdesc),
> > > > + &chan->curr_hwdesc_phys,
> > > > + GFP_KERNEL);
> > > > + if (!chan->curr_hwdesc)
> > > > + return -ENOMEM;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static void ls1x_dma_free_desc(struct virt_dma_desc *vdesc)
> > > > +{
> > > > + struct ls1x_dma_desc *desc = to_ls1x_dma_desc(vdesc);
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(vdesc->tx.chan);
> > > > +
> > > > + dma_pool_free(chan->desc_pool, desc->hwdesc, desc->hwdesc_phys);
> > > > + chan->desc = NULL;
> > > > + kfree(desc);
> > > > +}
> > > > +
> > > > +static struct ls1x_dma_desc *
> > > > +ls1x_dma_alloc_desc(struct dma_chan *dchan, int sg_len,
> > > > + enum dma_transfer_direction direction,
> > > > + enum dma_transaction_type type)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > + struct ls1x_dma_desc *desc;
> > > > +
> > > > + if (sg_len > LS1X_DMA_MAX_DESC) {
> > > > + dev_err(chan2dev(dchan), "sg_len %u exceeds limit %lu",
> > > > + sg_len, LS1X_DMA_MAX_DESC);
> > > > + return NULL;
> > > > + }
> > > > +
> > > > + desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
> > > > + if (!desc)
> > > > + return NULL;
> > > > +
> > > > + /* allocate HW descriptors */
> > > > + desc->hwdesc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT,
> > > > + &desc->hwdesc_phys);
> > > > + if (!desc->hwdesc) {
> > > > + dev_err(chan2dev(dchan), "failed to alloc HW descriptors\n");
> > > > + ls1x_dma_free_desc(&desc->vdesc);
> > > > + return NULL;
> > > > + }
> > > > +
> > > > + desc->dir = direction;
> > > > + desc->type = type;
> > > > + desc->nr_descs = sg_len;
> > > > +
> > > > + return desc;
> > > > +}
> > > > +
> > > > +static int ls1x_dma_setup_hwdescs(struct dma_chan *dchan,
> > > > + struct ls1x_dma_desc *desc,
> > > > + struct scatterlist *sgl, unsigned int sg_len)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > + dma_addr_t next_hwdesc_phys = desc->hwdesc_phys;
> > > > +
> > > > + struct scatterlist *sg;
> > > > + unsigned int dev_addr, cmd, i;
> > > > +
> > > > + switch (desc->dir) {
> > > > + case DMA_MEM_TO_DEV:
> > > > + dev_addr = chan->dst_addr;
> > > > + desc->bus_width = chan->dst_addr_width;
> > > > + cmd = DMA_RAM2DEV | DMA_INT;
> > > > + break;
> > > > + case DMA_DEV_TO_MEM:
> > > > + dev_addr = chan->src_addr;
> > > > + desc->bus_width = chan->src_addr_width;
> > > > + cmd = DMA_INT;
> > > > + break;
> > > > + default:
> > > > + dev_err(chan2dev(dchan), "unsupported DMA direction: %s\n",
> > > > + dmaengine_get_direction_text(desc->dir));
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + /* setup HW descriptors */
> > > > + for_each_sg(sgl, sg, sg_len, i) {
> > > > + dma_addr_t buf_addr = sg_dma_address(sg);
> > > > + size_t buf_len = sg_dma_len(sg);
> > > > + struct ls1x_dma_hwdesc *hwdesc = &desc->hwdesc[i];
> > > > +
> > > > + if (!is_dma_copy_aligned(dchan->device, buf_addr, 0, buf_len)) {
> > > > + dev_err(chan2dev(dchan), "buffer is not aligned!\n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + hwdesc->saddr = buf_addr;
> > > > + hwdesc->daddr = dev_addr;
> > > > + hwdesc->length = buf_len / desc->bus_width;
> > > > + hwdesc->stride = 0;
> > > > + hwdesc->cycles = 1;
> > > > + hwdesc->cmd = cmd;
> > > > +
> > > > + if (i) {
> > > > + next_hwdesc_phys += sizeof(*hwdesc);
> > > > + desc->hwdesc[i - 1].next = next_hwdesc_phys
> > > > + | DMA_NEXT_VALID;
> > > > + }
> > > > + }
> > > > +
> > > > + if (desc->type == DMA_CYCLIC)
> > > > + desc->hwdesc[i - 1].next = desc->hwdesc_phys | DMA_NEXT_VALID;
> > > > +
> > > > + for_each_sg(sgl, sg, sg_len, i) {
> > > > + struct ls1x_dma_hwdesc *hwdesc = &desc->hwdesc[i];
> > > > +
> > > > + print_hex_dump_debug("HW DESC: ", DUMP_PREFIX_OFFSET, 16, 4,
> > > > + hwdesc, sizeof(*hwdesc), false);
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static struct dma_async_tx_descriptor *
> > > > +ls1x_dma_prep_slave_sg(struct dma_chan *dchan,
> > > > + struct scatterlist *sgl, unsigned int sg_len,
> > > > + enum dma_transfer_direction direction,
> > > > + unsigned long flags, void *context)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > + struct ls1x_dma_desc *desc;
> > > > +
> > > > + dev_dbg(chan2dev(dchan), "sg_len=%u flags=0x%lx dir=%s\n",
> > > > + sg_len, flags, dmaengine_get_direction_text(direction));
> > > > +
> > > > + desc = ls1x_dma_alloc_desc(dchan, sg_len, direction, DMA_SLAVE);
> > > > + if (!desc)
> > > > + return NULL;
> > > > +
> > > > + if (ls1x_dma_setup_hwdescs(dchan, desc, sgl, sg_len)) {
> > > > + ls1x_dma_free_desc(&desc->vdesc);
> > > > + return NULL;
> > > > + }
> > > > +
> > > > + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
> > > > +}
> > > > +
> > > > +static struct dma_async_tx_descriptor *
> > > > +ls1x_dma_prep_dma_cyclic(struct dma_chan *dchan,
> > > > + dma_addr_t buf_addr, size_t buf_len, size_t period_len,
> > > > + enum dma_transfer_direction direction,
> > > > + unsigned long flags)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > + struct ls1x_dma_desc *desc;
> > > > + struct scatterlist *sgl;
> > > > + unsigned int sg_len;
> > > > + unsigned int i;
> > > > +
> > > > + dev_dbg(chan2dev(dchan),
> > > > + "buf_len=%d period_len=%zu flags=0x%lx dir=%s\n", buf_len,
> > > > + period_len, flags, dmaengine_get_direction_text(direction));
> > > > +
> > > > + sg_len = buf_len / period_len;
> > > > + desc = ls1x_dma_alloc_desc(dchan, sg_len, direction, DMA_CYCLIC);
> > > > + if (!desc)
> > > > + return NULL;
> > > > +
> > > > + /* allocate the scatterlist */
> > > > + sgl = kmalloc_array(sg_len, sizeof(*sgl), GFP_NOWAIT);
> > > > + if (!sgl)
> > > > + return NULL;
> > > > +
> > > > + sg_init_table(sgl, sg_len);
> > > > + for (i = 0; i < sg_len; ++i) {
> > > > + sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(buf_addr)),
> > > > + period_len, offset_in_page(buf_addr));
> > > > + sg_dma_address(&sgl[i]) = buf_addr;
> > > > + sg_dma_len(&sgl[i]) = period_len;
> > > > + buf_addr += period_len;
> > > > + }
> > > > +
> > > > + if (ls1x_dma_setup_hwdescs(dchan, desc, sgl, sg_len)) {
> > > > + ls1x_dma_free_desc(&desc->vdesc);
> > > > + return NULL;
> > > > + }
> > > > +
> > > > + kfree(sgl);
> > > > +
> > > > + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
> > > > +}
> > > > +
> > > > +static int ls1x_dma_slave_config(struct dma_chan *dchan,
> > > > + struct dma_slave_config *config)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > +
> > > > + chan->src_addr = config->src_addr;
> > > > + chan->src_addr_width = config->src_addr_width;
> > > > + chan->dst_addr = config->dst_addr;
> > > > + chan->dst_addr_width = config->dst_addr_width;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int ls1x_dma_pause(struct dma_chan *dchan)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > + unsigned long flags;
> > > > + int ret;
> > > > +
> > > > + spin_lock_irqsave(&chan->vchan.lock, flags);
> > > > + ret = ls1x_dma_query(chan, &chan->curr_hwdesc_phys);
> > > > + if (!ret)
> > > > + ls1x_dma_stop(chan);
> > > > + spin_unlock_irqrestore(&chan->vchan.lock, flags);
> > > > +
> > > > + return ret;
> > > > +}
> > > > +
> > > > +static int ls1x_dma_resume(struct dma_chan *dchan)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > + unsigned long flags;
> > > > + int ret;
> > > > +
> > > > + spin_lock_irqsave(&chan->vchan.lock, flags);
> > > > + ret = ls1x_dma_start(chan, &chan->curr_hwdesc_phys);
> > > > + spin_unlock_irqrestore(&chan->vchan.lock, flags);
> > > > +
> > > > + return ret;
> > > > +}
> > > > +
> > > > +static int ls1x_dma_terminate_all(struct dma_chan *dchan)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > + unsigned long flags;
> > > > + LIST_HEAD(head);
> > > > +
> > > > + spin_lock_irqsave(&chan->vchan.lock, flags);
> > > > + ls1x_dma_stop(chan);
> > > > + vchan_get_all_descriptors(&chan->vchan, &head);
> > > > + spin_unlock_irqrestore(&chan->vchan.lock, flags);
> > > > +
> > > > + vchan_dma_desc_free_list(&chan->vchan, &head);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static enum dma_status ls1x_dma_tx_status(struct dma_chan *dchan,
> > > > + dma_cookie_t cookie,
> > > > + struct dma_tx_state *state)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > + struct virt_dma_desc *vdesc;
> > > > + enum dma_status status;
> > > > + size_t bytes = 0;
> > > > + unsigned long flags;
> > > > +
> > > > + status = dma_cookie_status(dchan, cookie, state);
> > > > + if (status == DMA_COMPLETE)
> > > > + return status;
> > > > +
> > > > + spin_lock_irqsave(&chan->vchan.lock, flags);
> > > > + vdesc = vchan_find_desc(&chan->vchan, cookie);
> > > > + if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) {
> > > > + struct ls1x_dma_desc *desc = chan->desc;
> > > > + int i;
> > > > +
> > > > + if (ls1x_dma_query(chan, &chan->curr_hwdesc_phys))
> > > > + return status;
> > > > +
> > > > + /* locate the current HW descriptor */
> > > > + for (i = 0; i < desc->nr_descs; i++)
> > > > + if (desc->hwdesc[i].next == chan->curr_hwdesc->next)
> > > > + break;
> > > > +
> > > > + /* count the residues */
> > > > + for (; i < desc->nr_descs; i++)
> > > > + bytes += desc->hwdesc[i].length * desc->bus_width;
> > > > +
> > > > + dma_set_residue(state, bytes);
> > > > + }
> > > > + spin_unlock_irqrestore(&chan->vchan.lock, flags);
> > > > +
> > > > + return status;
> > > > +}
> > > > +
> > > > +static void ls1x_dma_issue_pending(struct dma_chan *dchan)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > > > + struct virt_dma_desc *vdesc;
> > > > + unsigned long flags;
> > > > +
> > > > + spin_lock_irqsave(&chan->vchan.lock, flags);
> > > > + if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
> > > > + vdesc = vchan_next_desc(&chan->vchan);
> > > > + if (!vdesc) {
> > > > + chan->desc = NULL;
> > > > + return;
> > > > + }
> > > > + chan->desc = to_ls1x_dma_desc(vdesc);
> > > > + ls1x_dma_start(chan, &chan->desc->hwdesc_phys);
> > > > + }
> > > > + spin_unlock_irqrestore(&chan->vchan.lock, flags);
> > > > +}
> > > > +
> > > > +static irqreturn_t ls1x_dma_irq_handler(int irq, void *data)
> > > > +{
> > > > + struct ls1x_dma_chan *chan = data;
> > > > + struct ls1x_dma_desc *desc = chan->desc;
> > > > + struct dma_chan *dchan = &chan->vchan.chan;
> > > > +
> > > > + if (!desc) {
> > > > + dev_warn(chan2dev(dchan),
> > > > + "IRQ %d with no active descriptor on channel %d\n",
> > > > + irq, dchan->chan_id);
> > > > + return IRQ_NONE;
> > > > + }
> > > > +
> > > > + dev_dbg(chan2dev(dchan), "DMA IRQ %d on channel %d\n", irq,
> > > > + dchan->chan_id);
> > > > +
> > > > + spin_lock(&chan->vchan.lock);
> > > > +
> > > > + if (desc->type == DMA_CYCLIC) {
> > > > + vchan_cyclic_callback(&desc->vdesc);
> > > > + } else {
> > > > + list_del(&desc->vdesc.node);
> > > > + vchan_cookie_complete(&desc->vdesc);
> > > > + chan->desc = NULL;
> > > > + }
> > > > +
> > > > + spin_unlock(&chan->vchan.lock);
> > > > + return IRQ_HANDLED;
> > > > +}
> > > > +
> > > > +static int ls1x_dma_chan_probe(struct platform_device *pdev,
> > > > + struct ls1x_dma *dma, int chan_id)
> > > > +{
> > > > + struct device *dev = &pdev->dev;
> > > > + struct ls1x_dma_chan *chan = &dma->chan[chan_id];
> > > > + char pdev_irqname[4];
> > > > + char *irqname;
> > > > + int ret;
> > > > +
> > > > + sprintf(pdev_irqname, "ch%u", chan_id);
> > > > + chan->irq = platform_get_irq_byname(pdev, pdev_irqname);
> > > > + if (chan->irq < 0)
> > > > + return -ENODEV;
> > > > +
> > > > + irqname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
> > > > + dev_name(dev), pdev_irqname);
> > > > + if (!irqname)
> > > > + return -ENOMEM;
> > > > +
> > > > + ret = devm_request_irq(dev, chan->irq, ls1x_dma_irq_handler,
> > > > + IRQF_SHARED, irqname, chan);
> > > > + if (ret)
> > > > + return dev_err_probe(dev, ret,
> > > > + "failed to request IRQ %u!\n", chan->irq);
> > > > +
> > > > + chan->reg_base = dma->reg_base;
> > > > + chan->vchan.desc_free = ls1x_dma_free_desc;
> > > > + vchan_init(&chan->vchan, &dma->ddev);
> > > > + dev_info(dev, "%s (irq %d) initialized\n", pdev_irqname, chan->irq);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static void ls1x_dma_chan_remove(struct ls1x_dma *dma, int chan_id)
> > > > +{
> > > > + struct device *dev = dma->ddev.dev;
> > > > + struct ls1x_dma_chan *chan = &dma->chan[chan_id];
> > > > +
> > > > + devm_free_irq(dev, chan->irq, chan);
> > > > + list_del(&chan->vchan.chan.device_node);
> > > > + tasklet_kill(&chan->vchan.task);
> > > > +}
> > > > +
> > > > +static int ls1x_dma_probe(struct platform_device *pdev)
> > > > +{
> > > > + struct device *dev = &pdev->dev;
> > > > + struct dma_device *ddev;
> > > > + struct ls1x_dma *dma;
> > > > + int nr_chans, ret, i;
> > > > +
> > > > + nr_chans = platform_irq_count(pdev);
> > > > + if (nr_chans <= 0)
> > > > + return nr_chans;
> > > > + if (nr_chans > LS1X_DMA_MAX_CHANNELS)
> > > > + return dev_err_probe(dev, -EINVAL,
> > > > + "nr_chans=%d exceeds the maximum\n",
> > > > + nr_chans);
> > > > +
> > > > + dma = devm_kzalloc(dev, struct_size(dma, chan, nr_chans), GFP_KERNEL);
> > > > + if (!dma)
> > > > + return -ENOMEM;
> > > > +
> > > > + /* initialize DMA device */
> > > > + dma->reg_base = devm_platform_ioremap_resource(pdev, 0);
> > > > + if (IS_ERR(dma->reg_base))
> > > > + return PTR_ERR(dma->reg_base);
> > > > +
> > > > + ddev = &dma->ddev;
> > > > + ddev->dev = dev;
> > > > + ddev->copy_align = DMAENGINE_ALIGN_4_BYTES;
> > > > + ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
> > > > + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
> > > > + ddev->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
> > > > + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
> > > > + ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
> > > > + ddev->max_sg_burst = LS1X_DMA_MAX_DESC;
> > > > + ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
> > > > + ddev->device_alloc_chan_resources = ls1x_dma_alloc_chan_resources;
> > > > + ddev->device_free_chan_resources = ls1x_dma_free_chan_resources;
> > > > + ddev->device_prep_slave_sg = ls1x_dma_prep_slave_sg;
> > > > + ddev->device_prep_dma_cyclic = ls1x_dma_prep_dma_cyclic;
> > > > + ddev->device_config = ls1x_dma_slave_config;
> > > > + ddev->device_pause = ls1x_dma_pause;
> > > > + ddev->device_resume = ls1x_dma_resume;
> > > > + ddev->device_terminate_all = ls1x_dma_terminate_all;
> > > > + ddev->device_tx_status = ls1x_dma_tx_status;
> > > > + ddev->device_issue_pending = ls1x_dma_issue_pending;
> > > > +
> > > > + dma_cap_set(DMA_SLAVE, ddev->cap_mask);
> > > > + INIT_LIST_HEAD(&ddev->channels);
> > > > +
> > > > + /* initialize DMA channels */
> > > > + for (i = 0; i < nr_chans; i++) {
> > > > + ret = ls1x_dma_chan_probe(pdev, dma, i);
> > > > + if (ret)
> > > > + return ret;
> > > > + }
> > > > + dma->nr_chans = nr_chans;
> > > > +
> > > > + ret = dmaenginem_async_device_register(ddev);
> > > > + if (ret) {
> > > > + dev_err(dev, "failed to register DMA device! %d\n", ret);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret =
> > > > + of_dma_controller_register(dev->of_node, of_dma_xlate_by_chan_id,
> > > > + ddev);
> > > > + if (ret) {
> > > > + dev_err(dev, "failed to register DMA controller! %d\n", ret);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + platform_set_drvdata(pdev, dma);
> > > > + dev_info(dev, "Loongson1 DMA driver registered\n");
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static void ls1x_dma_remove(struct platform_device *pdev)
> > > > +{
> > > > + struct ls1x_dma *dma = platform_get_drvdata(pdev);
> > > > + int i;
> > > > +
> > > > + of_dma_controller_free(pdev->dev.of_node);
> > > > +
> > > > + for (i = 0; i < dma->nr_chans; i++)
> > > > + ls1x_dma_chan_remove(dma, i);
> > > > +}
> > > > +
> > > > +static const struct of_device_id ls1x_dma_match[] = {
> > > > + { .compatible = "loongson,ls1b-apbdma" },
> > > > + { .compatible = "loongson,ls1c-apbdma" },
> > > > + { /* sentinel */ }
> > > > +};
> > > > +MODULE_DEVICE_TABLE(of, ls1x_dma_match);
> > > > +
> > > > +static struct platform_driver ls1x_dma_driver = {
> > > > + .probe = ls1x_dma_probe,
> > > > + .remove_new = ls1x_dma_remove,
> > > > + .driver = {
> > > > + .name = KBUILD_MODNAME,
> > > > + .of_match_table = ls1x_dma_match,
> > > > + },
> > > > +};
> > > > +
> > > > +module_platform_driver(ls1x_dma_driver);
> > > > +
> > > > +MODULE_AUTHOR("Keguang Zhang <keguang.zhang@gmail.com>");
> > > > +MODULE_DESCRIPTION("Loongson-1 APB DMA Controller driver");
> > > > +MODULE_LICENSE("GPL");
> > > >
> > > > --
> > > > 2.40.1
> > > >
> > > >
> >
> >
> >
> > --
> > Best regards,
> >
> > Keguang Zhang
> >
--
Best regards,
Keguang Zhang
^ permalink raw reply
* [PATCH v3] dt-bindings: PCI: ti,j721e-pci-host: Add device-id for TI's J784S4 SoC
From: Siddharth Vadapalli @ 2024-04-01 11:09 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
kishon
Cc: linux-pci, devicetree, linux-kernel, linux-arm-kernel, srk,
s-vadapalli
Add the device-id of 0xb012 for the PCIe controller on the J784S4 SoC as
described in the CTRL_MMR_PCI_DEVICE_ID register's PCI_DEVICE_ID_DEVICE_ID
field. The Register descriptions and the Technical Reference Manual for
J784S4 SoC can be found at: https://www.ti.com/lit/zip/spruj52
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
---
This patch is based on linux-next tagged next-20240328.
v2:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240115055236.1840255-1-s-vadapalli@ti.com/
Changes since v2:
- Rebased on next-20240328.
Regards,
Siddharth.
Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
index b7a534cef24d..0b1f21570ed0 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
@@ -68,6 +68,7 @@ properties:
- 0xb00d
- 0xb00f
- 0xb010
+ - 0xb012
- 0xb013
msi-map: true
--
2.40.1
^ permalink raw reply related
* Re: [PATCH 2/2] dt-bindings: iio: imu: add icm42688 inside inv_icm42600
From: Conor Dooley @ 2024-04-01 11:04 UTC (permalink / raw)
To: Jonathan Cameron
Cc: inv.git-commit, robh, krzysztof.kozlowski+dt, conor+dt, lars,
linux-iio, devicetree, Jean-Baptiste Maneyrol
In-Reply-To: <20240330161012.0b49846a@jic23-huawei>
[-- Attachment #1: Type: text/plain, Size: 1234 bytes --]
On Sat, Mar 30, 2024 at 04:10:12PM +0000, Jonathan Cameron wrote:
> On Fri, 29 Mar 2024 15:49:26 +0000
> Conor Dooley <conor@kernel.org> wrote:
>
> > On Fri, Mar 29, 2024 at 03:15:35PM +0000, inv.git-commit@tdk.com wrote:
> > > From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
> > >
> > > Add bindings for ICM-42688-P chip.
> > >
> > > Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
> >
> > My initial thought was that you're missing a sign-off, but is
> > "inv.git-commit@tdk.com" some system you have to bypass corporate email
> > garbage?
>
> Common enough setup, as long as the From: line matches the sign-off, git will
> ignore the email address used to send it when the patch is applied.
Yeah, I know how it works, I do it all the time. Even found, or rather
caused, a b4 bug where it would use the sending email in the eventual
commit rather than the author:
https://lore.kernel.org/tools/20230310192652.ymac3w2lucfdf34p@meerkat.local/
I'm just double checking that there's not a missing signoff. When I've
seen these corp-email-bypass accounts before people set a proper "from"
in git send-email so there's a name in it: "A Dev <inv.git-commit@tdk.com>"
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: usb: qcom,pmic-typec: update example to follow connector schema
From: Conor Dooley @ 2024-04-01 10:57 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio,
Bryan O'Donoghue, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, linux-usb, devicetree, linux-kernel,
Luca Weiss
In-Reply-To: <2024033109-reporter-blooming-5217@gregkh>
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On Sun, Mar 31, 2024 at 09:17:20AM +0200, Greg Kroah-Hartman wrote:
> On Sun, Mar 31, 2024 at 12:21:15AM +0200, Dmitry Baryshkov wrote:
> > Update Qualcomm PMIC Type-C examples to follow the USB-C connector
> > schema. The USB-C connector should have three ports (USB HS @0,
> > SSTX/RX @1 and SBU @2 lanes). Reorder ports accordingly and add SBU port
> > connected to the SBU mux (e.g. FSA4480).
> >
> > Fixes: 00bb478b829e ("dt-bindings: usb: Add Qualcomm PMIC Type-C")
> > Reported-by: Luca Weiss <luca.weiss@fairphone.com>
> > Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > Update examples to follow usb-c-connector schema wrt. ports definitions.
> > ---
>
> Hi,
>
> This is the friendly patch-bot of Greg Kroah-Hartman. You have sent him
> a patch that has triggered this response. He used to manually respond
> to these common problems, but in order to save his sanity (he kept
> writing the same thing over and over, yet to different people), I was
> created. Hopefully you will not take offence and will fix the problem
> in your patch and resubmit it so that it can be accepted into the Linux
> kernel tree.
>
> You are receiving this message because of the following common error(s)
> as indicated below:
>
> - You have marked a patch with a "Fixes:" tag for a commit that is in an
> older released kernel, yet you do not have a cc: stable line in the
> signed-off-by area at all, which means that the patch will not be
> applied to any older kernel releases. To properly fix this, please
> follow the documented rules in the
> Documentation/process/stable-kernel-rules.rst file for how to resolve
> this.
>
> If you wish to discuss this problem further, or you have questions about
> how to resolve this issue, please feel free to respond to this email and
> Greg will reply once he has dug out from the pending patches received
> from other developers.
I'm not sure that something updating the example like this needs to go
to stable in the first place.
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^ permalink raw reply
* Re: [PATCH] dt-bindings: PCI: rockchip,rk3399-pcie: add missing maxItems to ep-gpios
From: Conor Dooley @ 2024-04-01 10:46 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Shawn Lin, Lorenzo Pieralisi, Krzysztof Wilczyński,
Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, linux-pci, linux-rockchip, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <20240401100058.15749-1-krzysztof.kozlowski@linaro.org>
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On Mon, Apr 01, 2024 at 12:00:58PM +0200, Krzysztof Kozlowski wrote:
> Properties with GPIOs should define number of actual GPIOs, so add
> missing maxItems to ep-gpios. Otherwise multiple GPIOs could be
> provided which is not a true hardware description.
>
> Fixes: aa222f9311e1 ("dt-bindings: PCI: Convert Rockchip RK3399 PCIe to DT schema")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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* Re: [PATCH v3 3/5] dt-bindings: serial: amlogic,meson-uart: Add compatible string for A4
From: Conor Dooley @ 2024-04-01 10:45 UTC (permalink / raw)
To: xianwei.zhao
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby, devicetree, linux-kernel,
linux-arm-kernel, linux-amlogic, linux-serial
In-Reply-To: <20240401-basic_dt-v3-3-cb29ae1c16da@amlogic.com>
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On Mon, Apr 01, 2024 at 06:10:51PM +0800, Xianwei Zhao via B4 Relay wrote:
> From: Xianwei Zhao <xianwei.zhao@amlogic.com>
>
> Amlogic A4 SoCs uses the same UART controller as S4 SoCs and G12A.
> There is no need for an extra compatible line in the driver, but
> add A4 compatible line for documentation.
>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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* Re: [PATCH 2/3] drm/mipi-dsi: add mipi_dsi_compression_mode_raw()
From: Marijn Suijten @ 2024-04-01 10:38 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Sumit Semwal, Caleb Connolly, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, dri-devel, devicetree,
linux-kernel, linux-arm-msm
In-Reply-To: <20240330-lg-sw43408-panel-v1-2-f5580fc9f2da@linaro.org>
On 2024-03-30 05:59:29, Dmitry Baryshkov wrote:
> The LG SW43408 panel requires sending non-standard data as a part of the
> MIPI_DSI_COMPRESSION_MODE packet. Rather than hacking existing
> mipi_dsi_compression_mode() add mipi_dsi_compression_mode_raw(), which
> accepts raw data buffer and length.
Even though I doubt the usefulness of this _raw() command before further
understanding the panel and driver (according the the review-followup sent a few
minutes ago), let me review this a little bit.
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 34 ++++++++++++++++++++++++++--------
> include/drm/drm_mipi_dsi.h | 1 +
> 2 files changed, 27 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index ef6e416522f8..f340d1e0a9a5 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -645,29 +645,47 @@ int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
> EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size);
>
> /**
> - * mipi_dsi_compression_mode() - enable/disable DSC on the peripheral
> + * mipi_dsi_compression_mode_raw() - control DSC on the peripheral
> * @dsi: DSI peripheral device
> - * @enable: Whether to enable or disable the DSC
> + * @data: data to be sent to the device
> + * @len: size of the data buffer
> *
> - * Enable or disable Display Stream Compression on the peripheral using the
> + * Control the Display Stream Compression on the peripheral using the
+ mode?
> * default Picture Parameter Set and VESA DSC 1.1 algorithm.
This is no longer true. Both the algoritm identifier and "default Picture
Parameter Set" (which I assume means table *index*!) are described by the
custom/raw bytes that one is allowed to pass.
In fact, in the SW43408 driver that you reference in the commit message the
custom data passed to the _raw() function is used to select the second PPS
table (unless the panel interprets the input data in a non-standard way...), and
further sets the PPS for the first table only :)
> *
> * Return: 0 on success or a negative error code on failure.
> */
> -ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable)
> +ssize_t mipi_dsi_compression_mode_raw(struct mipi_dsi_device *dsi, void *data, size_t len)
> {
> - /* Note: Needs updating for non-default PPS or algorithm */
> - u8 tx[2] = { enable << 0, 0 };
> struct mipi_dsi_msg msg = {
> .channel = dsi->channel,
> .type = MIPI_DSI_COMPRESSION_MODE,
> - .tx_len = sizeof(tx),
> - .tx_buf = tx,
> + .tx_len = len,
> + .tx_buf = data,
> };
> int ret = mipi_dsi_device_transfer(dsi, &msg);
>
> return (ret < 0) ? ret : 0;
> }
> +EXPORT_SYMBOL(mipi_dsi_compression_mode_raw);
> +
> +/**
> + * mipi_dsi_compression_mode() - enable/disable DSC on the peripheral
> + * @dsi: DSI peripheral device
> + * @enable: Whether to enable or disable the DSC
> + *
> + * Enable or disable Display Stream Compression on the peripheral using the
> + * default Picture Parameter Set and VESA DSC 1.1 algorithm.
And while fixing this up, let's make it clear that this doesn't change the
PPS, just the *index* of which PPS to use (the PPS is updated with a different
command).
- Marijn
> + *
> + * Return: 0 on success or a negative error code on failure.
> + */
> +ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable)
> +{
> + /* Note: Needs updating for non-default PPS or algorithm */
> + u8 tx[2] = { enable << 0, 0 };
> +
> + return mipi_dsi_compression_mode_raw(dsi, tx, sizeof(tx));
> +}
> EXPORT_SYMBOL(mipi_dsi_compression_mode);
>
> /**
> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
> index c0aec0d4d664..321d2b019687 100644
> --- a/include/drm/drm_mipi_dsi.h
> +++ b/include/drm/drm_mipi_dsi.h
> @@ -242,6 +242,7 @@ int mipi_dsi_turn_on_peripheral(struct mipi_dsi_device *dsi);
> int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
> u16 value);
> ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable);
> +ssize_t mipi_dsi_compression_mode_raw(struct mipi_dsi_device *dsi, void *data, size_t len);
> ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
> const struct drm_dsc_picture_parameter_set *pps);
>
>
> --
> 2.39.2
>
^ permalink raw reply
* Re: [PATCH 3/3] drm: panel: Add LG sw43408 panel driver
From: Marijn Suijten @ 2024-04-01 10:29 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Sumit Semwal, Caleb Connolly, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, dri-devel, devicetree,
linux-kernel, linux-arm-msm, Vinod Koul, Caleb Connolly
In-Reply-To: <CAA8EJpowdjcN8KzGRVLrGx8L8Fi5Drs-C62VZKd5VbmDHsCg+Q@mail.gmail.com>
On 2024-03-30 16:37:08, Dmitry Baryshkov wrote:
> On Sat, 30 Mar 2024 at 12:27, Marijn Suijten
> <marijn.suijten@somainline.org> wrote:
> >
> > On 2024-03-30 05:59:30, Dmitry Baryshkov wrote:
> > > From: Sumit Semwal <sumit.semwal@linaro.org>
> > >
> > > LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel, used in some Pixel3
> > > phones.
> > >
> > > Whatever init sequence we have for this panel isn't capable of
> > > initialising it completely, toggling the reset gpio ever causes the
> > > panel to die. Until this is resolved we avoid resetting the panel. The
> >
> > Are you sure it is avoided? This patch seems to be toggling reset_gpio in
> > sw43408_prepare()?
> >
> > > disable/unprepare functions only put the panel to sleep mode and
> > > disable the backlight.
> > >
> > > Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
> > > [vinod: Add DSC support]
> > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > > [caleb: cleanup and support turning off the panel]
> > > Signed-off-by: Caleb Connolly <caleb@connolly.tech>
> > > [DB: partially rewrote the driver and fixed DSC programming]
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > ---
> > > MAINTAINERS | 8 +
> > > drivers/gpu/drm/panel/Kconfig | 11 ++
> > > drivers/gpu/drm/panel/Makefile | 1 +
> > > drivers/gpu/drm/panel/panel-lg-sw43408.c | 322 +++++++++++++++++++++++++++++++
> > > 4 files changed, 342 insertions(+)
> > >
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 4b511a55101c..f4cf7ee97376 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -6755,6 +6755,14 @@ S: Maintained
> > > F: Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
> > > F: drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
> > >
> > > +DRM DRIVER FOR LG SW43408 PANELS
> > > +M: Sumit Semwal <sumit.semwal@linaro.org>
> > > +M: Caleb Connolly <caleb.connolly@linaro.org>
> > > +S: Maintained
> > > +T: git git://anongit.freedesktop.org/drm/drm-misc
> > > +F: Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml
> > > +F: drivers/gpu/drm/panel/panel-lg-sw43408.c
> > > +
> > > DRM DRIVER FOR LOGICVC DISPLAY CONTROLLER
> > > M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> > > S: Supported
> > > diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> > > index d037b3b8b999..f94c702735cb 100644
> > > --- a/drivers/gpu/drm/panel/Kconfig
> > > +++ b/drivers/gpu/drm/panel/Kconfig
> > > @@ -335,6 +335,17 @@ config DRM_PANEL_LG_LG4573
> > > Say Y here if you want to enable support for LG4573 RGB panel.
> > > To compile this driver as a module, choose M here.
> > >
> > > +config DRM_PANEL_LG_SW43408
> > > + tristate "LG SW43408 panel"
> > > + depends on OF
> > > + depends on DRM_MIPI_DSI
> > > + depends on BACKLIGHT_CLASS_DEVICE
> > > + help
> > > + Say Y here if you want to enable support for LG sw43408 panel.
> > > + The panel has a 1080x2160 resolution and uses
> > > + 24 bit RGB per pixel. It provides a MIPI DSI interface to
> > > + the host and has a built-in LED backlight.
> > > +
> > > config DRM_PANEL_MAGNACHIP_D53E6EA8966
> > > tristate "Magnachip D53E6EA8966 DSI panel"
> > > depends on OF && SPI
> > > diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> > > index f156d7fa0bcc..a75687d13caf 100644
> > > --- a/drivers/gpu/drm/panel/Makefile
> > > +++ b/drivers/gpu/drm/panel/Makefile
> > > @@ -34,6 +34,7 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) += panel-leadtek-ltk050h3146w.o
> > > obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) += panel-leadtek-ltk500hd1829.o
> > > obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o
> > > obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
> > > +obj-$(CONFIG_DRM_PANEL_LG_SW43408) += panel-lg-sw43408.o
> > > obj-$(CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966) += panel-magnachip-d53e6ea8966.o
> > > obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
> > > obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o
> > > diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/panel/panel-lg-sw43408.c
> > > new file mode 100644
> > > index 000000000000..365d25e14d54
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c
> > > @@ -0,0 +1,322 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (C) 2019-2024 Linaro Ltd
> > > + * Author: Sumit Semwal <sumit.semwal@linaro.org>
> > > + * Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > + */
> > > +
> > > +#include <linux/backlight.h>
> > > +#include <linux/delay.h>
> > > +#include <linux/gpio/consumer.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of.h>
> > > +#include <linux/regulator/consumer.h>
> > > +
> > > +#include <video/mipi_display.h>
> > > +
> > > +#include <drm/drm_mipi_dsi.h>
> > > +#include <drm/drm_panel.h>
> > > +#include <drm/drm_probe_helper.h>
> > > +#include <drm/display/drm_dsc.h>
> > > +#include <drm/display/drm_dsc_helper.h>
> > > +
> > > +#define NUM_SUPPLIES 2
> > > +
> > > +struct sw43408_panel {
> > > + struct drm_panel base;
> > > + struct mipi_dsi_device *link;
> > > +
> > > + const struct drm_display_mode *mode;
> > > +
> > > + struct regulator_bulk_data supplies[NUM_SUPPLIES];
> > > +
> > > + struct gpio_desc *reset_gpio;
> > > +};
> > > +
> > > +static inline struct sw43408_panel *to_panel_info(struct drm_panel *panel)
> > > +{
> > > + return container_of(panel, struct sw43408_panel, base);
> > > +}
> > > +
> > > +static int sw43408_unprepare(struct drm_panel *panel)
> > > +{
> > > + struct sw43408_panel *ctx = to_panel_info(panel);
> > > + int ret;
> > > +
> > > + ret = mipi_dsi_dcs_set_display_off(ctx->link);
> > > + if (ret < 0)
> > > + dev_err(panel->dev, "set_display_off cmd failed ret = %d\n", ret);
> > > +
> > > + ret = mipi_dsi_dcs_enter_sleep_mode(ctx->link);
> > > + if (ret < 0)
> > > + dev_err(panel->dev, "enter_sleep cmd failed ret = %d\n", ret);
> > > +
> > > + msleep(100);
> > > +
> > > + gpiod_set_value(ctx->reset_gpio, 1);
> > > +
> > > + return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
> > > +}
> > > +
> > > +static int sw43408_program(struct drm_panel *panel)
> > > +{
> > > + struct sw43408_panel *ctx = to_panel_info(panel);
> > > + struct drm_dsc_picture_parameter_set pps;
> > > + u8 dsc_en = 0x11;
> >
> > Yeah, this is completely strange. Bit 0, 0x1, is to enable DSC which is
> > normal. 0x10 however, which is bit 4, selects PPS table 2. Do you ever set
> > pps_identifier in struct drm_dsc_picture_parameter_set to 2? Or is the table
> > that you send below bogus and/or not used? Maybe the Driver IC on the other
> > end of the DSI link has a default PPS table with identifier 2 that works out of
> > the box?
>
> Note, MIPI standard also requires two bytes argument. I suspect that
> LG didn't fully follow the standard here.
Have you read this command from downstream DTS, or have you tried sending 2
bytes and seen the panel breaking? The second byte is marked as reserved and
should be equal to 0; if the Driver IC is okay with sending either 1 or 2 bytes
I'd strive to stick with the defined length of 2 bytes for this DCS.
Have you played around with the PPS table? What if you change
drm_dsc_picture_paremeter_set::pps_identifier to the second table, will the
panel stop working as expected again? This could indicate that the PPS that is
sent is incorrect (even though the information in the original DSC config was
enough to set up the DPU and DSI correctly).
According to the DSI spec it is allowed to have a pre-stored/pre-programmed
PPS table, which could be used here making the current call to
mipi_dsi_picture_parameter_set() useless and "confusing"?
> Basically that's the reason why I went for the _raw function instead
> of adding PPS and codec arguments to the existing function.
>
> >
> > > + mipi_dsi_dcs_write_seq(ctx->link, MIPI_DCS_SET_GAMMA_CURVE, 0x02);
> > > +
> > > + mipi_dsi_dcs_set_tear_on(ctx->link, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
> > > +
> > > + mipi_dsi_dcs_write_seq(ctx->link, 0x53, 0x0c, 0x30);
> > > + mipi_dsi_dcs_write_seq(ctx->link, 0x55, 0x00, 0x70, 0xdf, 0x00, 0x70, 0xdf);
> > > + mipi_dsi_dcs_write_seq(ctx->link, 0xf7, 0x01, 0x49, 0x0c);
> > > +
> > > + mipi_dsi_dcs_exit_sleep_mode(ctx->link);
> > > +
> > > + msleep(135);
> > > +
> > > + mipi_dsi_compression_mode_raw(ctx->link, &dsc_en, 1);
> >
> > Even though I think we should change this function to describe the known
> > bit layout of command 0x7 per the VESA DSI spec, for now replace 1 with
> > sizeof(dsc_en)?
>
> If dsc_en were an array, it would have been a proper thing. Maybe I
> should change it to the array to remove confusion.
It should work even with a single byte, just to clarify to readers that the 3rd
argument is the byte-size of the input.
> > > + mipi_dsi_dcs_write_seq(ctx->link, 0xb0, 0xac);
> > > + mipi_dsi_dcs_write_seq(ctx->link, 0xe5,
> > > + 0x00, 0x3a, 0x00, 0x3a, 0x00, 0x0e, 0x10);
> > > + mipi_dsi_dcs_write_seq(ctx->link, 0xb5,
> > > + 0x75, 0x60, 0x2d, 0x5d, 0x80, 0x00, 0x0a, 0x0b,
> > > + 0x00, 0x05, 0x0b, 0x00, 0x80, 0x0d, 0x0e, 0x40,
> > > + 0x00, 0x0c, 0x00, 0x16, 0x00, 0xb8, 0x00, 0x80,
> > > + 0x0d, 0x0e, 0x40, 0x00, 0x0c, 0x00, 0x16, 0x00,
> > > + 0xb8, 0x00, 0x81, 0x00, 0x03, 0x03, 0x03, 0x01,
> > > + 0x01);
> > > + msleep(85);
> > > + mipi_dsi_dcs_write_seq(ctx->link, 0xcd,
> > > + 0x00, 0x00, 0x00, 0x19, 0x19, 0x19, 0x19, 0x19,
> > > + 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
> > > + 0x16, 0x16);
> > > + mipi_dsi_dcs_write_seq(ctx->link, 0xcb, 0x80, 0x5c, 0x07, 0x03, 0x28);
> > > + mipi_dsi_dcs_write_seq(ctx->link, 0xc0, 0x02, 0x02, 0x0f);
> > > + mipi_dsi_dcs_write_seq(ctx->link, 0x55, 0x04, 0x61, 0xdb, 0x04, 0x70, 0xdb);
> > > + mipi_dsi_dcs_write_seq(ctx->link, 0xb0, 0xca);
> > > +
> > > + mipi_dsi_dcs_set_display_on(ctx->link);
> >
> > Any specific reason to not have the (un)blanking sequence in the enable/disable
> > callbacks and leaving display configuration in (un)prepare?
>
> We are back to the question on when it's fine to send the commands. I
> think the current agreement is to send everything in the
> prepare/unprepare, because of some strange hosts.
For my panel drivers I'm sticking with having `post-on` commands (from
downstream) in `enable/disable`, which is typically only `set_display_on`. In
hopes of proposing a `prepare_atomic()` some time to allow mode selection.
In a short test on recent -next I am once again allowed to send DSI commands in
both .disable and .unprepare, making both functions a "clean" inverse of .enable
and .prepare respectively.
> > > + msleep(50);
> > > +
> > > + ctx->link->mode_flags &= ~MIPI_DSI_MODE_LPM;
> > > +
> > > + drm_dsc_pps_payload_pack(&pps, ctx->link->dsc);
> > > + mipi_dsi_picture_parameter_set(ctx->link, &pps);
> >
> > I'm always surprised why this is sent _after_ turning the display on (unblanking
> > it). Wouldn't that cause unnecessary corruption?
>
> No idea. I followed the dowsntream command sequences here. Most likely
> the panel is not fully on until it receives the full frame to be
> displayed.
According to the DSI spec a PPS update is allowed to happen every frame, and
(for cmdmode panels) will take effect after the next TE trigger. Unsure if a TE
event happens before the first frame, otherwise this may start taking effect
on the second frame onwards only.
If there's no corruption on the first frame there might be a pre-programmed PPS
table in slot 2, supporting the theory above.
- Marijn
^ permalink raw reply
* [PATCH v3 4/5] arm64: dts: add support for A4 based Amlogic BA400
From: Xianwei Zhao via B4 Relay @ 2024-04-01 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial, Xianwei Zhao
In-Reply-To: <20240401-basic_dt-v3-0-cb29ae1c16da@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Amlogic A4 is an application processor designed for smart audio
and IoT applications.
Add basic support for the A4 based Amlogic BA400 board, which describes
the following components: CPU, GIC, IRQ, Timer and UART.
These are capable of booting up into the serial console.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts | 42 ++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi | 66 ++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 40 +++++++++++++
4 files changed, 149 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 1ab160bf928a..9a50ec11bb8d 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
new file mode 100644
index 000000000000..ad3127e695d9
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "amlogic-a4.dtsi"
+
+/ {
+ model = "Amlogic A113L2 ba400 Development Board";
+ compatible = "amlogic,ba400", "amlogic,a4";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart_b;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 10 MiB reserved for ARM Trusted Firmware */
+ secmon_reserved: secmon@5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x05000000 0x0 0xa00000>;
+ no-map;
+ };
+ };
+};
+
+&uart_b {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi
new file mode 100644
index 000000000000..b6106ad4a072
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
+/ {
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@fff01000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xfff01000 0 0x1000>,
+ <0x0 0xfff02000 0 0x2000>,
+ <0x0 0xfff04000 0 0x2000>,
+ <0x0 0xfff06000 0 0x2000>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ apb: bus@fe000000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe000000 0x0 0x480000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
+
+ uart_b: serial@7a000 {
+ compatible = "amlogic,a4-uart",
+ "amlogic,meson-s4-uart";
+ reg = <0x0 0x7a000 0x0 0x18>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&xtal>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
new file mode 100644
index 000000000000..73ca1d7eed81
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ */
+
+#include "amlogic-a4-common.dtsi"
+/ {
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+};
--
2.37.1
^ permalink raw reply related
* [PATCH v3 5/5] arm64: dts: add support for A5 based Amlogic AV400
From: Xianwei Zhao via B4 Relay @ 2024-04-01 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial, Xianwei Zhao
In-Reply-To: <20240401-basic_dt-v3-0-cb29ae1c16da@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Amlogic A5 is an application processor designed for smart audio
and IoT applications.
Add basic support for the A5 based Amlogic AV400 board, which describes
the following components: CPU, GIC, IRQ, Timer and UART.
These are capable of booting up into the serial console.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../boot/dts/amlogic/amlogic-a5-a113x2-av400.dts | 42 ++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 40 +++++++++++++++++++++
3 files changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 9a50ec11bb8d..154c9efb26e4 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
+dtb-$(CONFIG_ARCH_MESON) += amlogic-a5-a113x2-av400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts b/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts
new file mode 100644
index 000000000000..11d8b88c1ce5
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "amlogic-a5.dtsi"
+
+/ {
+ model = "Amlogic A113X2 av400 Development Board";
+ compatible = "amlogic,av400", "amlogic,a5";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart_b;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 10 MiB reserved for ARM Trusted Firmware */
+ secmon_reserved: secmon@5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x05000000 0x0 0xa00000>;
+ no-map;
+ };
+ };
+};
+
+&uart_b {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
new file mode 100644
index 000000000000..43f68a7da2f7
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ */
+
+#include "amlogic-a4-common.dtsi"
+/ {
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ };
+ };
+};
--
2.37.1
^ permalink raw reply related
* [PATCH v3 2/5] dt-bindings: arm: amlogic: add A5 support
From: Xianwei Zhao via B4 Relay @ 2024-04-01 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial, Xianwei Zhao, Krzysztof Kozlowski
In-Reply-To: <20240401-basic_dt-v3-0-cb29ae1c16da@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Document the new A5 SoC/board device tree bindings.
Amlogic A5 is an application processor designed for smart audio
and IoT applications.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
index 520975e7cac0..e64ced44ece8 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
@@ -207,6 +207,12 @@ properties:
- amlogic,ba400
- const: amlogic,a4
+ - description: Boards with the Amlogic A5 A113X2 SoC
+ items:
+ - enum:
+ - amlogic,av400
+ - const: amlogic,a5
+
- description: Boards with the Amlogic C3 C302X/C308L SoC
items:
- enum:
--
2.37.1
^ permalink raw reply related
* [PATCH v3 1/5] dt-bindings: arm: amlogic: add A4 support
From: Xianwei Zhao via B4 Relay @ 2024-04-01 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial, Xianwei Zhao, Krzysztof Kozlowski
In-Reply-To: <20240401-basic_dt-v3-0-cb29ae1c16da@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Document the new A4 SoC/board device tree bindings.
Amlogic A4 is an application processor designed for smart audio
and IoT applications.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
index 949537cea6be..520975e7cac0 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
@@ -201,6 +201,12 @@ properties:
- amlogic,ad402
- const: amlogic,a1
+ - description: Boards with the Amlogic A4 A113L2 SoC
+ items:
+ - enum:
+ - amlogic,ba400
+ - const: amlogic,a4
+
- description: Boards with the Amlogic C3 C302X/C308L SoC
items:
- enum:
--
2.37.1
^ permalink raw reply related
* [PATCH v3 3/5] dt-bindings: serial: amlogic,meson-uart: Add compatible string for A4
From: Xianwei Zhao via B4 Relay @ 2024-04-01 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial, Xianwei Zhao
In-Reply-To: <20240401-basic_dt-v3-0-cb29ae1c16da@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Amlogic A4 SoCs uses the same UART controller as S4 SoCs and G12A.
There is no need for an extra compatible line in the driver, but
add A4 compatible line for documentation.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
index 2e189e548327..0565fb7649c5 100644
--- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
@@ -54,7 +54,9 @@ properties:
- const: amlogic,meson-gx-uart
- description: UART controller on S4 compatible SoCs
items:
- - const: amlogic,t7-uart
+ - enum:
+ - amlogic,a4-uart
+ - amlogic,t7-uart
- const: amlogic,meson-s4-uart
reg:
--
2.37.1
^ permalink raw reply related
* [PATCH v3 0/5] Baisc devicetree support for Amlogic A4 and A5
From: Xianwei Zhao via B4 Relay @ 2024-04-01 10:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial, Xianwei Zhao, Krzysztof Kozlowski
Amlogic A4 and A5 are application processors designed for smart audio
and IoT applications.
Add the new A4 SoC/board device tree bindings.
Add the new A5 SoC/board device tree bindings.
Add A4 UART compatible line for documentation.
Add basic support for the A4 based Amlogic AV400 board, which describes
the following components: CPU, GIC, IRQ, Timer and UART. These are capable of
booting up into the serial console.
Add basic support for the A5 based Amlogic AV400 board, which describes
the following components: CPU, GIC, IRQ, Timer and UART. These are capable of
booting up into the serial console.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Changes in v3:
- Keep alphabetical order.
- Add the necessary spaces.
- Link to v2: https://lore.kernel.org/r/20240320-basic_dt-v2-0-681ecfb23baf@amlogic.com
Changes in v2:
- Delete bindings for uncommitted boards.
- Add A4 UART compatible line for documentation.
- Use common dtsi for a4 and a5.
- Fix psci version 1.0, and fix some formats.
- Modify secmon reserved memory size 10M(actual using).
- Link to v1: https://lore.kernel.org/r/20240312-basic_dt-v1-0-7f11df3a0896@amlogic.com
---
Xianwei Zhao (5):
dt-bindings: arm: amlogic: add A4 support
dt-bindings: arm: amlogic: add A5 support
dt-bindings: serial: amlogic,meson-uart: Add compatible string for A4
arm64: dts: add support for A4 based Amlogic BA400
arm64: dts: add support for A5 based Amlogic AV400
Documentation/devicetree/bindings/arm/amlogic.yaml | 12 ++++
.../bindings/serial/amlogic,meson-uart.yaml | 4 +-
arch/arm64/boot/dts/amlogic/Makefile | 2 +
.../boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts | 42 ++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi | 66 ++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 40 +++++++++++++
.../boot/dts/amlogic/amlogic-a5-a113x2-av400.dts | 42 ++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 40 +++++++++++++
8 files changed, 247 insertions(+), 1 deletion(-)
---
base-commit: 7092cfae086f0bc235baca413d0bd904f182670c
change-id: 20240312-basic_dt-15e47525a413
Best regards,
--
Xianwei Zhao <xianwei.zhao@amlogic.com>
^ permalink raw reply
* [PATCH] dt-bindings: PCI: rockchip,rk3399-pcie: add missing maxItems to ep-gpios
From: Krzysztof Kozlowski @ 2024-04-01 10:00 UTC (permalink / raw)
To: Shawn Lin, Lorenzo Pieralisi, Krzysztof Wilczyński,
Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, linux-pci, linux-rockchip, devicetree,
linux-arm-kernel, linux-kernel
Cc: Krzysztof Kozlowski
Properties with GPIOs should define number of actual GPIOs, so add
missing maxItems to ep-gpios. Otherwise multiple GPIOs could be
provided which is not a true hardware description.
Fixes: aa222f9311e1 ("dt-bindings: PCI: Convert Rockchip RK3399 PCIe to DT schema")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
index 531008f0b6ac..002b728cbc71 100644
--- a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
@@ -37,6 +37,7 @@ properties:
description: This property is needed if using 24MHz OSC for RC's PHY.
ep-gpios:
+ maxItems: 1
description: pre-reset GPIO
vpcie12v-supply:
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 17/18] dt-bindings: pci: rockchip,rk3399-pcie-ep: Add ep-gpios property
From: Krzysztof Kozlowski @ 2024-04-01 9:57 UTC (permalink / raw)
To: Damien Le Moal, Manivannan Sadhasivam, Lorenzo Pieralisi,
Kishon Vijay Abraham I, Shawn Lin, Krzysztof Wilczyński,
Bjorn Helgaas, Heiko Stuebner, linux-pci, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree
Cc: linux-rockchip, linux-arm-kernel, Rick Wertenbroek,
Wilfred Mallawa, Niklas Cassel
In-Reply-To: <c75cb54a-61c7-4bc3-978e-8a28dde93b08@kernel.org>
On 01/04/2024 01:06, Damien Le Moal wrote:
> On 3/30/24 18:16, Krzysztof Kozlowski wrote:
>> On 30/03/2024 05:19, Damien Le Moal wrote:
>>> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>>>
>>> Describe the `ep-gpios` property which is used to map the PERST# input
>>> signal for endpoint mode.
>>>
>>> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>>> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
>>> ---
>>> .../devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml | 3 +++
>>> 1 file changed, 3 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
>>> index 6b62f6f58efe..9331d44d6963 100644
>>> --- a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
>>> @@ -30,6 +30,9 @@ properties:
>>> maximum: 32
>>> default: 32
>>>
>>> + ep-gpios:
>>> + description: Input GPIO configured for the PERST# signal.
>>
>> Missing maxItems. But more important: why existing property perst-gpios,
>> which you already have there in common schema, is not correct for this case?
>
> I am confused... Where do you find perst-gpios defined for the rk3399 ?
> Under Documentation/devicetree/bindings/pci/, the only schema I see using
> perst-gpios property are for the qcom (Qualcomm) controllers.
You are right, it's so far only in Qualcomm.
> The RC bindings for the rockchip rk3399 PCIe controller
> (pci/rockchip,rk3399-pcie.yaml) already define the ep-gpios property. So if
Any reason why this cannot be named like GPIO? Is there already a user
of this in Linux kernel? Commit msg says nothing about this, so that's
why I would expect name matching the signal.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [RFC PATCH 1/2] spi: dt-bindings: add Siflower Quad SPI controller
From: Krzysztof Kozlowski @ 2024-04-01 9:53 UTC (permalink / raw)
To: Qingfang Deng
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Qingfang Deng, linux-spi, devicetree, linux-kernel
In-Reply-To: <CALW65jZoU8ChPg+e-5T4+ZmS2=g8O3wL96mjaRAPbomHJhg4gg@mail.gmail.com>
On 01/04/2024 05:36, Qingfang Deng wrote:
> Hi Krzysztof,
>
> On Sun, Mar 31, 2024 at 1:42 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 29/03/2024 02:51, Qingfang Deng wrote:
>>> Add YAML devicetree bindings for Siflower Quad SPI controller.
>>
>> Describe the hardware. What is this Siflower?
>
> It's a new RISC-V SoC which hasn't been upstreamed yet.
>
>>> +properties:
>>> + compatible:
>>> + const: siflower,qspi
>>
>> Except that this was not tested, aren't you adding it for some SoC? If
>> so, then you miss here SoC part.
>
> I should add the "siflower" prefix to
> Documentation/devicetree/bindings/vendor-prefixes.yaml, right?
Isn't it already there? Then obvious you must, but that was not the
point. Please read writing-bindings document. Compatibles should be SoC
specific, not generic. "qspi" is generic.
Best regards,
Krzysztof
^ permalink raw reply
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