* Re: [PATCH] arm64: dts: rockchip: Remove unsupported node from the Pinebook Pro dts
From: Heiko Stuebner @ 2024-04-01 21:55 UTC (permalink / raw)
To: linux-rockchip, Dragan Simic
Cc: Heiko Stuebner, devicetree, krzysztof.kozlowski+dt, conor+dt,
linux-arm-kernel, robh+dt
In-Reply-To: <0f82c3f97cb798d012270d13b34d8d15305ef293.1711923520.git.dsimic@manjaro.org>
On Mon, 1 Apr 2024 00:20:56 +0200, Dragan Simic wrote:
> Remove a redundant node from the Pine64 Pinebook Pro dts, which is intended
> to provide a value for the delay in PCI Express enumeration, but that isn't
> supported without additional out-of-tree kernel patches.
>
> There were already efforts to upstream those kernel patches, because they
> reportedly make some PCI Express cards (such as LSI SAS HBAs) usable in
> Pine64 RockPro64 (which is also based on the RK3399); otherwise, those PCI
> Express cards fail to enumerate. However, providing the required background
> and explanations proved to be a tough nut to crack, which is the reason why
> those patches remain outside of the kernel mainline for now.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: Remove unsupported node from the Pinebook Pro dts
commit: 43853e843aa6c3d47ff2b0cce898318839483d05
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH 6/6] iio: adc: ad7173: Add support for AD411x devices
From: David Lechner @ 2024-04-01 21:53 UTC (permalink / raw)
To: dumitru.ceclan
Cc: Lars-Peter Clausen, Michael Hennerich, Jonathan Cameron,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-iio,
devicetree, linux-kernel, Dumitru Ceclan
In-Reply-To: <20240401-ad4111-v1-6-34618a9cc502@analog.com>
On Mon, Apr 1, 2024 at 10:10 AM Dumitru Ceclan via B4 Relay
<devnull+dumitru.ceclan.analog.com@kernel.org> wrote:
>
> From: Dumitru Ceclan <dumitru.ceclan@analog.com>
>
> Add support for AD4111/AD4112/AD4114/AD4115/AD4116.
>
> The AD411X family encompasses a series of low power, low noise, 24-bit,
> sigma-delta analog-to-digital converters that offer a versatile range of
> specifications.
>
> This family of ADCs integrates an analog front end suitable for processing
> both fully differential and single-ended, bipolar voltage inputs
> addressing a wide array of industrial and instrumentation requirements.
>
> - All ADCs have inputs with a precision voltage divider with a division
> ratio of 10.
> - AD4116 has 5 low level inputs without a voltage divider.
> - AD4111 and AD4112 support current inputs (0 mA to 20 mA) using a 50ohm
> shunt resistor.
>
> Signed-off-by: Dumitru Ceclan <dumitru.ceclan@analog.com>
> ---
...
> @@ -951,7 +1117,7 @@ static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev)
> struct device *dev = indio_dev->dev.parent;
> struct iio_chan_spec *chan_arr, *chan;
> unsigned int ain[2], chan_index = 0;
> - int ref_sel, ret, num_channels;
> + int ref_sel, ret, reg, num_channels;
>
> num_channels = device_get_child_node_count(dev);
>
Another thing that is missing in this function both for the chips
being added here and the existing chips are channels for _all_
possible inputs. The driver is adding a fixed input channel for the
temperature sensor, as it should. But all of the chips also have a
similar input channel configuration that measures the reference
voltage. Currently, there doesn't seem to be a way to make use of this
feature. I would expect a hard-coded voltage input channel that is
always added for this reference voltage similar to the temperature
channel.
The ad717x chips (except AD7173-8 and AD7176-2) also have a common
mode voltage input ("((AVDD1 − AVSS)/5)") that could work the same.
In the case of the ad717x chips though, it looks like these channels
are not "fixed" like they are in ad411x. It looks like these inputs
can be mixed and matched with AINx inputs and/or each other as
differential pairs. So if that is actually the case, I would expect
the DT bindings for ad717x to look like adi,ad4130.yaml where these
additional input sources are listed in the diff-channels property
instead of having hard-coded channels in the driver like I have
suggested above.
But, as always, fixes for ad717x should be in a separate patch series.
Still, I think adding a hard-coded channel for the reference voltage
input for ad411x chips in this patch makes sense.
^ permalink raw reply
* Re: [PATCH v2 0/3] Add sy7802 flash led driver
From: Trilok Soni @ 2024-04-01 21:45 UTC (permalink / raw)
To: git, Pavel Machek, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kees Cook, Gustavo A. R. Silva, Bjorn Andersson,
Konrad Dybcio
Cc: linux-leds, devicetree, linux-kernel, linux-hardening,
linux-arm-msm, ~postmarketos/upstreaming, phone-devel
In-Reply-To: <20240401-sy7802-v2-0-1138190a7448@apitzsch.eu>
On 4/1/2024 2:23 PM, André Apitzsch via B4 Relay wrote:
> This series introduces a driver for the Silergy SY7802 charge pump used
> in the BQ Aquaris M5 and X5 smartphones.
>
> The implementation is based on information extracted from downstream as
> the datasheet provided by a distributor of the hardware didn't include
> any information about the i2c register description.
>
> Signed-off-by: André Apitzsch <git@apitzsch.eu>
Is this the right email address? "From" shows devnull+git.apitzsch.eu@kernel.org.
> ---
> Changes in v2:
> - bindings: remove unneeded allOf
> - bindings: example: move flash-led-controller under i2c node to fix
> check error
> - Cc to phone-devel
> - Link to v1: https://lore.kernel.org/r/20240327-sy7802-v1-0-db74ab32faaf@apitzsch.eu
>
> ---
> André Apitzsch (3):
> dt-bindings: leds: Add Silergy SY7802 flash LED
> leds: sy7802: Add support for Silergy SY7802 flash LED controller
> arm64: dts: qcom: msm8939-longcheer-l9100: Add rear flash
>
> .../devicetree/bindings/leds/silergy,sy7802.yaml | 100 ++++
> .../boot/dts/qcom/msm8939-longcheer-l9100.dts | 26 +
> drivers/leds/flash/Kconfig | 11 +
> drivers/leds/flash/Makefile | 1 +
> drivers/leds/flash/leds-sy7802.c | 532 +++++++++++++++++++++
> 5 files changed, 670 insertions(+)
> ---
> base-commit: a6bd6c9333397f5a0e2667d4d82fef8c970108f2
> change-id: 20240325-sy7802-f40fc6f56525
>
> Best regards,
--
---Trilok Soni
^ permalink raw reply
* [PATCH v2 2/3] leds: sy7802: Add support for Silergy SY7802 flash LED controller
From: André Apitzsch via B4 Relay @ 2024-04-01 21:23 UTC (permalink / raw)
To: Pavel Machek, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kees Cook, Gustavo A. R. Silva, Bjorn Andersson,
Konrad Dybcio
Cc: linux-leds, devicetree, linux-kernel, linux-hardening,
linux-arm-msm, ~postmarketos/upstreaming, phone-devel,
André Apitzsch
In-Reply-To: <20240401-sy7802-v2-0-1138190a7448@apitzsch.eu>
From: André Apitzsch <git@apitzsch.eu>
Add support for SY7802 flash LED controller. It can support up to 1.8A
flash current.
Signed-off-by: André Apitzsch <git@apitzsch.eu>
---
drivers/leds/flash/Kconfig | 11 +
drivers/leds/flash/Makefile | 1 +
drivers/leds/flash/leds-sy7802.c | 532 +++++++++++++++++++++++++++++++++++++++
3 files changed, 544 insertions(+)
diff --git a/drivers/leds/flash/Kconfig b/drivers/leds/flash/Kconfig
index 809b6d98bb3e..f39f0bfe6eef 100644
--- a/drivers/leds/flash/Kconfig
+++ b/drivers/leds/flash/Kconfig
@@ -121,4 +121,15 @@ config LEDS_SGM3140
This option enables support for the SGM3140 500mA Buck/Boost Charge
Pump LED Driver.
+config LEDS_SY7802
+ tristate "LED support for the Silergy SY7802"
+ depends on I2C && OF
+ depends on GPIOLIB
+ select REGMAP_I2C
+ help
+ This option enables support for the SY7802 flash LED controller.
+ SY7802 includes torch and flash functions with programmable current.
+
+ This driver can be built as a module, it will be called "leds-sy7802".
+
endif # LEDS_CLASS_FLASH
diff --git a/drivers/leds/flash/Makefile b/drivers/leds/flash/Makefile
index 91d60a4b7952..48860eeced79 100644
--- a/drivers/leds/flash/Makefile
+++ b/drivers/leds/flash/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_LEDS_QCOM_FLASH) += leds-qcom-flash.o
obj-$(CONFIG_LEDS_RT4505) += leds-rt4505.o
obj-$(CONFIG_LEDS_RT8515) += leds-rt8515.o
obj-$(CONFIG_LEDS_SGM3140) += leds-sgm3140.o
+obj-$(CONFIG_LEDS_SY7802) += leds-sy7802.o
diff --git a/drivers/leds/flash/leds-sy7802.c b/drivers/leds/flash/leds-sy7802.c
new file mode 100644
index 000000000000..c03a571b0e08
--- /dev/null
+++ b/drivers/leds/flash/leds-sy7802.c
@@ -0,0 +1,532 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Silergy SY7802 flash LED driver with I2C interface
+ *
+ * Copyright 2024 André Apitzsch <git@apitzsch.eu>
+ */
+
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/led-class-flash.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define SY7802_MAX_LEDS 2
+#define SY7802_LED_JOINT 2
+
+#define SY7802_REG_ENABLE 0x10
+#define SY7802_REG_TORCH_BRIGHTNESS 0xa0
+#define SY7802_REG_FLASH_BRIGHTNESS 0xb0
+#define SY7802_REG_FLASH_DURATION 0xc0
+#define SY7802_REG_FLAGS 0xd0
+#define SY7802_REG_CONFIG_1 0xe0
+#define SY7802_REG_CONFIG_2 0xf0
+#define SY7802_REG_VIN_MONITOR 0x80
+#define SY7802_REG_LAST_FLASH 0x81
+#define SY7802_REG_VLED_MONITOR 0x30
+#define SY7802_REG_ADC_DELAY 0x31
+#define SY7802_REG_DEV_ID 0xff
+
+#define SY7802_MODE_OFF 0
+#define SY7802_MODE_TORCH 2
+#define SY7802_MODE_FLASH 3
+#define SY7802_MODE_MASK GENMASK(1, 0)
+
+#define SY7802_LEDS_SHIFT 3
+#define SY7802_LEDS_MASK(_id) (BIT(_id) << SY7802_LEDS_SHIFT)
+#define SY7802_LEDS_MASK_ALL (SY7802_LEDS_MASK(0) | SY7802_LEDS_MASK(1))
+
+#define SY7802_TORCH_CURRENT_SHIFT 3
+#define SY7802_TORCH_CURRENT_MASK(_id) \
+ (GENMASK(2, 0) << (SY7802_TORCH_CURRENT_SHIFT * (_id)))
+#define SY7802_TORCH_CURRENT_MASK_ALL \
+ (SY7802_TORCH_CURRENT_MASK(0) | SY7802_TORCH_CURRENT_MASK(1))
+
+#define SY7802_FLASH_CURRENT_SHIFT 4
+#define SY7802_FLASH_CURRENT_MASK(_id) \
+ (GENMASK(3, 0) << (SY7802_FLASH_CURRENT_SHIFT * (_id)))
+#define SY7802_FLASH_CURRENT_MASK_ALL \
+ (SY7802_FLASH_CURRENT_MASK(0) | SY7802_FLASH_CURRENT_MASK(1))
+
+#define SY7802_TIMEOUT_DEFAULT_US 512000U
+#define SY7802_TIMEOUT_MIN_US 32000U
+#define SY7802_TIMEOUT_MAX_US 1024000U
+#define SY7802_TIMEOUT_STEPSIZE_US 32000U
+
+#define SY7802_TORCH_BRIGHTNESS_MAX 8
+
+#define SY7802_FLASH_BRIGHTNESS_DEFAULT 14
+#define SY7802_FLASH_BRIGHTNESS_MIN 0
+#define SY7802_FLASH_BRIGHTNESS_MAX 15
+#define SY7802_FLASH_BRIGHTNESS_STEP 1
+
+#define SY7802_FLAG_TIMEOUT (1 << 0)
+#define SY7802_FLAG_THERMAL_SHUTDOWN (1 << 1)
+#define SY7802_FLAG_LED_FAULT (1 << 2)
+#define SY7802_FLAG_TX1_INTERRUPT (1 << 3)
+#define SY7802_FLAG_TX2_INTERRUPT (1 << 4)
+#define SY7802_FLAG_LED_THERMAL_FAULT (1 << 5)
+#define SY7802_FLAG_FLASH_INPUT_VOLTAGE_LOW (1 << 6)
+#define SY7802_FLAG_INPUT_VOLTAGE_LOW (1 << 7)
+
+#define SY7802_CHIP_ID 0x51
+
+static const struct reg_default sy7802_regmap_defs[] = {
+ { SY7802_REG_ENABLE, SY7802_LEDS_MASK_ALL },
+ { SY7802_REG_TORCH_BRIGHTNESS, 0x92 },
+ { SY7802_REG_FLASH_BRIGHTNESS, SY7802_FLASH_BRIGHTNESS_DEFAULT |
+ SY7802_FLASH_BRIGHTNESS_DEFAULT << SY7802_FLASH_CURRENT_SHIFT },
+ { SY7802_REG_FLASH_DURATION, 0x6f },
+ { SY7802_REG_FLAGS, 0x0 },
+ { SY7802_REG_CONFIG_1, 0x68 },
+ { SY7802_REG_CONFIG_2, 0xf0 },
+};
+
+struct sy7802_led {
+ struct led_classdev_flash flash;
+ struct sy7802 *chip;
+ u8 led_no;
+};
+
+struct sy7802 {
+ struct mutex mutex;
+ struct device *dev;
+ struct regmap *regmap;
+
+ struct gpio_desc *enable_gpio;
+ struct regulator *vin_regulator;
+
+ unsigned int fled_strobe_used;
+ unsigned int fled_torch_used;
+ unsigned int leds_active;
+ int num_leds;
+ struct sy7802_led leds[] __counted_by(num_leds);
+};
+
+static int sy7802_torch_brightness_set(struct led_classdev *lcdev, enum led_brightness level)
+{
+ struct sy7802_led *led = container_of(lcdev, struct sy7802_led, flash.led_cdev);
+ u32 led_enable_mask = led->led_no == SY7802_LED_JOINT ? SY7802_LEDS_MASK_ALL :
+ SY7802_LEDS_MASK(led->led_no);
+ u32 enable_mask = SY7802_MODE_MASK | led_enable_mask;
+ u32 val = level ? led_enable_mask : SY7802_MODE_OFF;
+ struct sy7802 *chip = led->chip;
+ u32 curr;
+ u32 mask;
+ int ret;
+
+ mutex_lock(&chip->mutex);
+
+ /*
+ * There is only one set of flash control logic, and this flag is used to check if 'strobe'
+ * is currently being used.
+ */
+ if (chip->fled_strobe_used) {
+ dev_warn(chip->dev, "Please disable strobe first [%d]\n", chip->fled_strobe_used);
+ ret = -EBUSY;
+ goto unlock;
+ }
+
+ if (level)
+ curr = chip->fled_torch_used | BIT(led->led_no);
+ else
+ curr = chip->fled_torch_used & ~BIT(led->led_no);
+
+ if (curr)
+ val |= SY7802_MODE_TORCH;
+
+ /* Torch needs to be disabled first to apply new brightness */
+ ret = regmap_update_bits(chip->regmap, SY7802_REG_ENABLE, SY7802_MODE_MASK,
+ SY7802_MODE_OFF);
+ if (ret)
+ goto unlock;
+
+ mask = led->led_no == SY7802_LED_JOINT ? SY7802_TORCH_CURRENT_MASK_ALL :
+ SY7802_TORCH_CURRENT_MASK(led->led_no);
+
+ /* Register expects brightness between 0 and MAX_BRIGHTNESS - 1 */
+ if (level)
+ level -= 1;
+
+ level |= (level << SY7802_TORCH_CURRENT_SHIFT);
+
+ ret = regmap_update_bits(chip->regmap, SY7802_REG_TORCH_BRIGHTNESS, mask, level);
+ if (ret)
+ goto unlock;
+
+ ret = regmap_update_bits(chip->regmap, SY7802_REG_ENABLE, enable_mask, val);
+ if (ret)
+ goto unlock;
+
+ chip->fled_torch_used = curr;
+
+unlock:
+ mutex_unlock(&chip->mutex);
+ return ret;
+}
+
+static int sy7802_flash_brightness_set(struct led_classdev_flash *fl_cdev, u32 brightness)
+{
+ struct sy7802_led *led = container_of(fl_cdev, struct sy7802_led, flash);
+ struct led_flash_setting *s = &fl_cdev->brightness;
+ u32 val = (brightness - s->min) / s->step;
+ struct sy7802 *chip = led->chip;
+ u32 mask;
+ int ret;
+
+ val |= (val << SY7802_FLASH_CURRENT_SHIFT);
+ mask = led->led_no == SY7802_LED_JOINT ? SY7802_FLASH_CURRENT_MASK_ALL :
+ SY7802_FLASH_CURRENT_MASK(led->led_no);
+
+ mutex_lock(&chip->mutex);
+ ret = regmap_update_bits(chip->regmap, SY7802_REG_FLASH_BRIGHTNESS, mask, val);
+ mutex_unlock(&chip->mutex);
+
+ return ret;
+}
+
+static int sy7802_strobe_set(struct led_classdev_flash *fl_cdev, bool state)
+{
+ struct sy7802_led *led = container_of(fl_cdev, struct sy7802_led, flash);
+ u32 led_enable_mask = led->led_no == SY7802_LED_JOINT ? SY7802_LEDS_MASK_ALL :
+ SY7802_LEDS_MASK(led->led_no);
+ u32 enable_mask = SY7802_MODE_MASK | led_enable_mask;
+ u32 val = state ? led_enable_mask : SY7802_MODE_OFF;
+ struct sy7802 *chip = led->chip;
+ u32 curr;
+ int ret;
+
+ mutex_lock(&chip->mutex);
+
+ /*
+ * There is only one set of flash control logic, and this flag is used to check if 'torch'
+ * is currently being used.
+ */
+ if (chip->fled_torch_used) {
+ dev_warn(chip->dev, "Please disable torch first [0x%x]\n", chip->fled_torch_used);
+ ret = -EBUSY;
+ goto unlock;
+ }
+
+ if (state)
+ curr = chip->fled_strobe_used | BIT(led->led_no);
+ else
+ curr = chip->fled_strobe_used & ~BIT(led->led_no);
+
+ if (curr)
+ val |= SY7802_MODE_FLASH;
+
+ ret = regmap_update_bits(chip->regmap, SY7802_REG_ENABLE, enable_mask, val);
+
+ if (ret)
+ goto unlock;
+
+ chip->fled_strobe_used = curr;
+
+unlock:
+ mutex_unlock(&chip->mutex);
+ return ret;
+}
+
+static int sy7802_strobe_get(struct led_classdev_flash *fl_cdev, bool *state)
+{
+ struct sy7802_led *led = container_of(fl_cdev, struct sy7802_led, flash);
+ struct sy7802 *chip = led->chip;
+
+ mutex_lock(&chip->mutex);
+ *state = !!(chip->fled_strobe_used & BIT(led->led_no));
+ mutex_unlock(&chip->mutex);
+
+ return 0;
+}
+
+static int sy7802_timeout_set(struct led_classdev_flash *fl_cdev,
+ u32 timeout)
+{
+ struct sy7802_led *led = container_of(fl_cdev, struct sy7802_led, flash);
+ struct led_flash_setting *s = &fl_cdev->timeout;
+ u32 val = (timeout - s->min) / s->step;
+ struct sy7802 *chip = led->chip;
+
+ return regmap_write(chip->regmap, SY7802_REG_FLASH_DURATION, val);
+}
+
+static int sy7802_fault_get(struct led_classdev_flash *fl_cdev, u32 *fault)
+{
+ struct sy7802_led *led = container_of(fl_cdev, struct sy7802_led, flash);
+ struct sy7802 *chip = led->chip;
+ u32 val, led_faults = 0;
+ int ret;
+
+ /* NOTE: reading register clears fault status */
+ ret = regmap_read(chip->regmap, SY7802_REG_FLAGS, &val);
+ if (ret)
+ return ret;
+
+ if (val & (SY7802_FLAG_FLASH_INPUT_VOLTAGE_LOW | SY7802_FLAG_INPUT_VOLTAGE_LOW))
+ led_faults |= LED_FAULT_INPUT_VOLTAGE;
+
+ if (val & SY7802_FLAG_THERMAL_SHUTDOWN)
+ led_faults |= LED_FAULT_OVER_TEMPERATURE;
+
+ if (val & SY7802_FLAG_TIMEOUT)
+ led_faults |= LED_FAULT_TIMEOUT;
+
+ *fault = led_faults;
+ return 0;
+}
+
+static const struct led_flash_ops sy7802_flash_ops = {
+ .flash_brightness_set = sy7802_flash_brightness_set,
+ .strobe_set = sy7802_strobe_set,
+ .strobe_get = sy7802_strobe_get,
+ .timeout_set = sy7802_timeout_set,
+ .fault_get = sy7802_fault_get,
+};
+
+static void sy7802_init_flash_brightness(struct led_classdev_flash *fl_cdev)
+{
+ struct led_flash_setting *s;
+
+ /* Init flash brightness setting */
+ s = &fl_cdev->brightness;
+ s->min = SY7802_FLASH_BRIGHTNESS_MIN;
+ s->max = SY7802_FLASH_BRIGHTNESS_MAX;
+ s->step = SY7802_FLASH_BRIGHTNESS_STEP;
+ s->val = SY7802_FLASH_BRIGHTNESS_DEFAULT;
+}
+
+static void sy7802_init_flash_timeout(struct led_classdev_flash *fl_cdev)
+{
+ struct led_flash_setting *s;
+
+ /* Init flash timeout setting */
+ s = &fl_cdev->timeout;
+ s->min = SY7802_TIMEOUT_MIN_US;
+ s->max = SY7802_TIMEOUT_MAX_US;
+ s->step = SY7802_TIMEOUT_STEPSIZE_US;
+ s->val = SY7802_TIMEOUT_DEFAULT_US;
+}
+
+static int sy7802_led_register(struct device *dev, struct sy7802_led *led,
+ struct device_node *np)
+{
+ struct led_init_data init_data = {};
+ int ret;
+
+ init_data.fwnode = of_fwnode_handle(np);
+
+ ret = devm_led_classdev_flash_register_ext(dev, &led->flash, &init_data);
+ if (ret) {
+ dev_err(dev, "Couldn't register flash %d\n", led->led_no);
+ return ret;
+ }
+
+ return ret;
+}
+
+static int sy7802_init_flash_properties(struct device *dev, struct sy7802_led *led,
+ struct device_node *np)
+{
+ struct led_classdev_flash *flash = &led->flash;
+ struct led_classdev *lcdev = &flash->led_cdev;
+ u32 sources[SY7802_MAX_LEDS];
+ int i, num, ret;
+
+ num = of_property_count_u32_elems(np, "led-sources");
+ if (num < 1) {
+ dev_err(dev, "Not specified or wrong number of led-sources\n");
+ return -EINVAL;
+ }
+
+ ret = of_property_read_u32_array(np, "led-sources", sources, num);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < num; i++) {
+ if (sources[i] >= SY7802_MAX_LEDS)
+ return -EINVAL;
+ if (led->chip->leds_active & BIT(sources[i]))
+ return -EINVAL;
+ led->chip->leds_active |= BIT(sources[i]);
+ }
+
+ /* If both channels are specified in 'led-sources', joint flash output mode is used */
+ led->led_no = num == 2 ? SY7802_LED_JOINT : sources[0];
+
+ lcdev->max_brightness = SY7802_TORCH_BRIGHTNESS_MAX;
+ lcdev->brightness_set_blocking = sy7802_torch_brightness_set;
+ lcdev->flags |= LED_DEV_CAP_FLASH;
+
+ flash->ops = &sy7802_flash_ops;
+
+ sy7802_init_flash_brightness(flash);
+ sy7802_init_flash_timeout(flash);
+
+ return 0;
+}
+
+static int sy7802_chip_check(struct sy7802 *chip)
+{
+ struct device *dev = chip->dev;
+ u32 chipid;
+ int ret;
+
+ ret = regmap_read(chip->regmap, SY7802_REG_DEV_ID, &chipid);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read chip ID\n");
+
+ if (chipid != SY7802_CHIP_ID)
+ return dev_err_probe(dev, -ENODEV, "Chip reported wrong ID: %x\n", chipid);
+
+ return 0;
+}
+
+static void sy7802_enable(struct sy7802 *chip)
+{
+ gpiod_set_value_cansleep(chip->enable_gpio, 1);
+ usleep_range(200, 300);
+}
+
+static void sy7802_disable(struct sy7802 *chip)
+{
+ gpiod_set_value_cansleep(chip->enable_gpio, 0);
+}
+
+static int sy7802_probe_dt(struct sy7802 *chip)
+{
+ struct device_node *np = dev_of_node(chip->dev), *child;
+ int i = 0;
+ int ret;
+
+ regmap_write(chip->regmap, SY7802_REG_ENABLE, SY7802_MODE_OFF);
+ regmap_write(chip->regmap, SY7802_REG_TORCH_BRIGHTNESS, LED_OFF);
+
+ for_each_available_child_of_node(np, child) {
+ struct sy7802_led *led = chip->leds + i;
+
+ led->chip = chip;
+ led->led_no = i;
+
+ ret = sy7802_init_flash_properties(chip->dev, led, child);
+ if (ret) {
+ of_node_put(child);
+ return ret;
+ }
+
+ ret = sy7802_led_register(chip->dev, led, child);
+ if (ret) {
+ of_node_put(child);
+ return ret;
+ }
+
+ i++;
+ }
+ return 0;
+}
+
+static const struct regmap_config sy7802_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0xff,
+ .cache_type = REGCACHE_MAPLE,
+ .reg_defaults = sy7802_regmap_defs,
+ .num_reg_defaults = ARRAY_SIZE(sy7802_regmap_defs),
+};
+
+static int sy7802_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct sy7802 *chip;
+ size_t count;
+ int ret;
+
+ count = device_get_child_node_count(dev);
+ if (!count || count > SY7802_MAX_LEDS)
+ return dev_err_probe(dev, -EINVAL,
+ "No child node or node count over max led number %zu\n", count);
+
+ chip = devm_kzalloc(dev, struct_size(chip, leds, count), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ chip->num_leds = count;
+
+ chip->dev = dev;
+ i2c_set_clientdata(client, chip);
+
+ chip->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
+ ret = PTR_ERR_OR_ZERO(chip->enable_gpio);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to request enable gpio\n");
+
+ chip->vin_regulator = devm_regulator_get(dev, "vin");
+ ret = PTR_ERR_OR_ZERO(chip->vin_regulator);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to request regulator\n");
+
+ ret = regulator_enable(chip->vin_regulator);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to enable regulator\n");
+
+ chip->regmap = devm_regmap_init_i2c(client, &sy7802_regmap_config);
+ if (IS_ERR(chip->regmap)) {
+ regulator_disable(chip->vin_regulator);
+ return dev_err_probe(dev, PTR_ERR(chip->regmap),
+ "Failed to allocate register map.\n");
+ }
+
+ ret = sy7802_probe_dt(chip);
+ if (ret < 0) {
+ regulator_disable(chip->vin_regulator);
+ return ret;
+ }
+
+ sy7802_enable(chip);
+
+ ret = sy7802_chip_check(chip);
+ if (ret) {
+ sy7802_disable(chip);
+ regulator_disable(chip->vin_regulator);
+ return ret;
+ }
+
+ mutex_init(&chip->mutex);
+
+ return ret;
+}
+
+static void sy7802_remove(struct i2c_client *client)
+{
+ struct sy7802 *chip = i2c_get_clientdata(client);
+
+ sy7802_disable(chip);
+
+ mutex_destroy(&chip->mutex);
+ regulator_disable(chip->vin_regulator);
+}
+
+static const struct of_device_id __maybe_unused sy7802_leds_match[] = {
+ { .compatible = "silergy,sy7802", },
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, sy7802_leds_match);
+
+static struct i2c_driver sy7802_driver = {
+ .driver = {
+ .name = "sy7802",
+ .of_match_table = of_match_ptr(sy7802_leds_match),
+ },
+ .probe = sy7802_probe,
+ .remove = sy7802_remove,
+};
+
+module_i2c_driver(sy7802_driver);
+
+MODULE_AUTHOR("André Apitzsch <git@apitzsch.eu>");
+MODULE_DESCRIPTION("Silergy SY7802 flash LED driver");
+MODULE_LICENSE("GPL");
--
2.44.0
^ permalink raw reply related
* [PATCH v2 3/3] arm64: dts: qcom: msm8939-longcheer-l9100: Add rear flash
From: André Apitzsch via B4 Relay @ 2024-04-01 21:23 UTC (permalink / raw)
To: Pavel Machek, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kees Cook, Gustavo A. R. Silva, Bjorn Andersson,
Konrad Dybcio
Cc: linux-leds, devicetree, linux-kernel, linux-hardening,
linux-arm-msm, ~postmarketos/upstreaming, phone-devel,
André Apitzsch
In-Reply-To: <20240401-sy7802-v2-0-1138190a7448@apitzsch.eu>
From: André Apitzsch <git@apitzsch.eu>
The phone has a Silergy SY7802 flash LED controller.
Signed-off-by: André Apitzsch <git@apitzsch.eu>
---
.../boot/dts/qcom/msm8939-longcheer-l9100.dts | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts b/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts
index e3404c4455cf..528737929274 100644
--- a/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts
+++ b/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts
@@ -159,6 +159,25 @@ led@2 {
};
};
};
+
+ flash-led-controller@53 {
+ compatible = "silergy,sy7802";
+ reg = <0x53>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&camera_rear_flash_default>;
+ pinctrl-names = "default";
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <0>, <1>;
+ };
+ };
};
&blsp_i2c3 {
@@ -318,6 +337,13 @@ camera_front_flash_default: camera-front-flash-default-state {
bias-disable;
};
+ camera_rear_flash_default: camera-rear-flash-default-state {
+ pins = "gpio9", "gpio16", "gpio51";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
gpio_hall_sensor_default: gpio-hall-sensor-default-state {
pins = "gpio20";
function = "gpio";
--
2.44.0
^ permalink raw reply related
* [PATCH v2 0/3] Add sy7802 flash led driver
From: André Apitzsch via B4 Relay @ 2024-04-01 21:23 UTC (permalink / raw)
To: Pavel Machek, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kees Cook, Gustavo A. R. Silva, Bjorn Andersson,
Konrad Dybcio
Cc: linux-leds, devicetree, linux-kernel, linux-hardening,
linux-arm-msm, ~postmarketos/upstreaming, phone-devel,
André Apitzsch
This series introduces a driver for the Silergy SY7802 charge pump used
in the BQ Aquaris M5 and X5 smartphones.
The implementation is based on information extracted from downstream as
the datasheet provided by a distributor of the hardware didn't include
any information about the i2c register description.
Signed-off-by: André Apitzsch <git@apitzsch.eu>
---
Changes in v2:
- bindings: remove unneeded allOf
- bindings: example: move flash-led-controller under i2c node to fix
check error
- Cc to phone-devel
- Link to v1: https://lore.kernel.org/r/20240327-sy7802-v1-0-db74ab32faaf@apitzsch.eu
---
André Apitzsch (3):
dt-bindings: leds: Add Silergy SY7802 flash LED
leds: sy7802: Add support for Silergy SY7802 flash LED controller
arm64: dts: qcom: msm8939-longcheer-l9100: Add rear flash
.../devicetree/bindings/leds/silergy,sy7802.yaml | 100 ++++
.../boot/dts/qcom/msm8939-longcheer-l9100.dts | 26 +
drivers/leds/flash/Kconfig | 11 +
drivers/leds/flash/Makefile | 1 +
drivers/leds/flash/leds-sy7802.c | 532 +++++++++++++++++++++
5 files changed, 670 insertions(+)
---
base-commit: a6bd6c9333397f5a0e2667d4d82fef8c970108f2
change-id: 20240325-sy7802-f40fc6f56525
Best regards,
--
André Apitzsch <git@apitzsch.eu>
^ permalink raw reply
* [PATCH v2 1/3] dt-bindings: leds: Add Silergy SY7802 flash LED
From: André Apitzsch via B4 Relay @ 2024-04-01 21:23 UTC (permalink / raw)
To: Pavel Machek, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kees Cook, Gustavo A. R. Silva, Bjorn Andersson,
Konrad Dybcio
Cc: linux-leds, devicetree, linux-kernel, linux-hardening,
linux-arm-msm, ~postmarketos/upstreaming, phone-devel,
André Apitzsch
In-Reply-To: <20240401-sy7802-v2-0-1138190a7448@apitzsch.eu>
From: André Apitzsch <git@apitzsch.eu>
Document Silergy SY7802 flash LED driver devicetree bindings.
Signed-off-by: André Apitzsch <git@apitzsch.eu>
---
.../devicetree/bindings/leds/silergy,sy7802.yaml | 100 +++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/Documentation/devicetree/bindings/leds/silergy,sy7802.yaml b/Documentation/devicetree/bindings/leds/silergy,sy7802.yaml
new file mode 100644
index 000000000000..46b8e5452b62
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/silergy,sy7802.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/silergy,sy7802.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Silergy SY7802 1800mA Boost Charge Pump LED Driver
+
+maintainers:
+ - André Apitzsch <git@apitzsch.eu>
+
+description: |
+ The SY7802 is a current-regulated charge pump which can regulate two current
+ levels for Flash and Torch modes.
+
+ The SY7802 is a high-current synchronous boost converter with 2-channel
+ high side current sources. Each channel is able to deliver 900mA current.
+
+properties:
+ compatible:
+ enum:
+ - silergy,sy7802
+
+ reg:
+ maxItems: 1
+
+ enable-gpios:
+ maxItems: 1
+ description: A connection to the 'EN' pin.
+
+ flash-gpios:
+ maxItems: 1
+ description: A connection to the 'FLEN' pin.
+
+ vin-supply:
+ description: Regulator providing power to the 'VIN' pin.
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^led@[0-1]$":
+ type: object
+ $ref: common.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ description: Index of the LED.
+ minimum: 0
+ maximum: 1
+
+ led-sources:
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 1
+
+ required:
+ - reg
+ - led-sources
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - enable-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash-led-controller@53 {
+ compatible = "silergy,sy7802";
+ reg = <0x53>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <0>, <1>;
+ };
+ };
+ };
--
2.44.0
^ permalink raw reply related
* Re: [PATCH 1/6] dt-bindings: adc: ad7173: add support for ad411x
From: David Lechner @ 2024-04-01 21:16 UTC (permalink / raw)
To: dumitru.ceclan
Cc: Lars-Peter Clausen, Michael Hennerich, Jonathan Cameron,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-iio,
devicetree, linux-kernel, Dumitru Ceclan
In-Reply-To: <CAMknhBHeKAQ45=5-dL1T1tv-mZcPN+bNo3vxWJYgWpEPE+8p3Q@mail.gmail.com>
On Mon, Apr 1, 2024 at 2:37 PM David Lechner <dlechner@baylibre.com> wrote:
>
> On Mon, Apr 1, 2024 at 10:10 AM Dumitru Ceclan via B4 Relay
> <devnull+dumitru.ceclan.analog.com@kernel.org> wrote:
> >
> > From: Dumitru Ceclan <dumitru.ceclan@analog.com>
> >
> > Add support for: AD4111, AD4112, AD4114, AD4115, AD4116.
> >
> > AD411x family ADCs support a VCOM pin, dedicated for single-ended usage.
> > AD4111/AD4112 support current channels, usage is implemented by
> > specifying channel reg values bigger than 15.
> >
> > Signed-off-by: Dumitru Ceclan <dumitru.ceclan@analog.com>
> > ---
...
> > @@ -125,10 +141,19 @@ patternProperties:
> >
> > properties:
> > reg:
> > + description:
> > + Reg values 16-19 are only permitted for ad4111/ad4112 current channels.
> > minimum: 0
> > - maximum: 15
> > + maximum: 19
>
> This looks wrong. Isn't reg describing the number of logical channels
> (# of channel config registers)?
>
> After reviewing the driver, I see that > 16 is used as a way of
> flagging current inputs, but still seems like the wrong way to do it.
> See suggestion below.
>
> >
> > diff-channels:
> > + description:
> > + For using current channels specify only the positive channel.
> > + (IIN2+, IIN2−) -> diff-channels = <2 0>
>
> I find this a bit confusing since 2 is already VIN2 and 0 is already
> VIN0. I think it would make more sense to assign unique channel
> numbers individually to the negative and positive current inputs.
> Also, I think it makes sense to use the same numbers that the
> registers in the datasheet use (8 - 11 for negative and 12 to 15 for
> positive).
>
> So: (IIN2+, IIN2−) -> diff-channels = <13 10>
Thinking about this a bit more...
Since the current inputs have dedicated pins and aren't mix-and-match
with multiple valid wiring configurations like the voltage inputs, do
we even need to describe them in the devicetree?
In the driver, the current channels would just be hard-coded like the
temperature channel since there isn't any application-specific
variation.
^ permalink raw reply
* [PATCH] dt-bindings: rockchip: grf: Add missing type to 'pcie-phy' node
From: Rob Herring @ 2024-04-01 20:49 UTC (permalink / raw)
To: Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
'pcie-phy' is missing any type. Add 'type: object' to indicate it's a
node.
Signed-off-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 0b87c266760c..79798c747476 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -171,6 +171,7 @@ allOf:
unevaluatedProperties: false
pcie-phy:
+ type: object
description:
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
--
2.43.0
^ permalink raw reply related
* [PATCH net-next] dt-bindings: net: snps,dwmac: Align 'snps,priority' type definition
From: Rob Herring @ 2024-04-01 20:44 UTC (permalink / raw)
To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue,
Giuseppe Cavallaro, Jose Abreu
Cc: netdev, devicetree, linux-kernel
'snps,priority' is also defined in dma/snps,dw-axi-dmac.yaml as a
uint32-array. It's preferred to have a single type for a given property
name, so update the type in snps,dwmac schema to match.
Signed-off-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/net/snps,dwmac.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index 6b0341a8e0ea..15073627c53a 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -242,7 +242,8 @@ properties:
type: boolean
description: Multicast & Broadcast Packets
snps,priority:
- $ref: /schemas/types.yaml#/definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 1
description: Bitmask of the tagged frames priorities assigned to the queue
allOf:
- if:
@@ -393,7 +394,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
description: max read outstanding req. limit
snps,priority:
- $ref: /schemas/types.yaml#/definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 1
description:
Bitmask of the tagged frames priorities assigned to the queue.
When a PFC frame is received with priorities matching the bitmask,
--
2.43.0
^ permalink raw reply related
* [PATCH v2] dt-bindings: dma: snps,dma-spear1340: Fix data{-,_}width schema
From: Rob Herring @ 2024-04-01 20:43 UTC (permalink / raw)
To: Viresh Kumar, Andy Shevchenko, Vinod Koul, Krzysztof Kozlowski,
Conor Dooley
Cc: Viresh Kumar, Serge Semin, dmaengine, devicetree, linux-kernel
'data-width' and 'data_width' properties are defined as arrays, but the
schema is defined as a matrix. That works currently since everything gets
decoded in to matrices, but that is internal to dtschema and could change.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
v2:
- Make 'minItems' explicit. This works around a bug in dtschema, and is
also preferred.
- Add tags
---
.../bindings/dma/snps,dma-spear1340.yaml | 42 +++++++++----------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml b/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml
index 5da8291a7de0..c21a4f073f6c 100644
--- a/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml
@@ -93,10 +93,10 @@ properties:
data-width:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: Data bus width per each DMA master in bytes.
+ minItems: 1
+ maxItems: 4
items:
- maxItems: 4
- items:
- enum: [4, 8, 16, 32]
+ enum: [4, 8, 16, 32]
data_width:
$ref: /schemas/types.yaml#/definitions/uint32-array
@@ -106,28 +106,28 @@ properties:
deprecated. It' usage is discouraged in favor of data-width one. Moreover
the property incorrectly permits to define data-bus width of 8 and 16
bits, which is impossible in accordance with DW DMAC IP-core data book.
+ minItems: 1
+ maxItems: 4
items:
- maxItems: 4
- items:
- enum:
- - 0 # 8 bits
- - 1 # 16 bits
- - 2 # 32 bits
- - 3 # 64 bits
- - 4 # 128 bits
- - 5 # 256 bits
- default: 0
+ enum:
+ - 0 # 8 bits
+ - 1 # 16 bits
+ - 2 # 32 bits
+ - 3 # 64 bits
+ - 4 # 128 bits
+ - 5 # 256 bits
+ default: 0
multi-block:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
LLP-based multi-block transfer supported by hardware per
each DMA channel.
+ minItems: 1
+ maxItems: 8
items:
- maxItems: 8
- items:
- enum: [0, 1]
- default: 1
+ enum: [0, 1]
+ default: 1
snps,max-burst-len:
$ref: /schemas/types.yaml#/definitions/uint32-array
@@ -138,11 +138,11 @@ properties:
will be from 1 to max-burst-len words. It's an array property with one
cell per channel in the units determined by the value set in the
CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width).
+ minItems: 1
+ maxItems: 8
items:
- maxItems: 8
- items:
- enum: [4, 8, 16, 32, 64, 128, 256]
- default: 256
+ enum: [4, 8, 16, 32, 64, 128, 256]
+ default: 256
snps,dma-protection-control:
$ref: /schemas/types.yaml#/definitions/uint32
--
2.43.0
^ permalink raw reply related
* [PATCH v3 9/9] arm64: dts: qcom: sm8150-hdk: rename Type-C HS endpoints
From: Dmitry Baryshkov @ 2024-04-01 20:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org>
Follow other Qualcomm platforms and rename pm8150b_role_switch_in to
pm8150_hs_in. Corresponding port is described as HS port rather than
role switching.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
index de670b407ef1..857ccc5de085 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
@@ -556,7 +556,7 @@ ports {
port@0 {
reg = <0>;
- pm8150b_role_switch_in: endpoint {
+ pm8150b_hs_in: endpoint {
remote-endpoint = <&usb_1_dwc3_hs>;
};
};
@@ -703,7 +703,7 @@ &usb_1_dwc3 {
};
&usb_1_dwc3_hs {
- remote-endpoint = <&pm8150b_role_switch_in>;
+ remote-endpoint = <&pm8150b_hs_in>;
};
&usb_1_dwc3_ss {
--
2.39.2
^ permalink raw reply related
* [PATCH v3 8/9] arm64: dts: qcom: x1e80100: describe USB signals properly
From: Dmitry Baryshkov @ 2024-04-01 20:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org>
Follow example of other platforms. Rename HS graph nodes to contain
'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 149 +++++++++++++++++++++++++++++++--
1 file changed, 141 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index f5a3b39ae70e..3213eccc3a3a 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -2543,6 +2543,33 @@ usb_1_ss0_qmpphy: phy@fd5000 {
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss0_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss0_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_ss0_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
};
usb_1_ss1_hsphy: phy@fd9000 {
@@ -2583,6 +2610,33 @@ usb_1_ss1_qmpphy: phy@fda000 {
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss1_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_ss1_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
};
usb_1_ss2_hsphy: phy@fde000 {
@@ -2623,6 +2677,33 @@ usb_1_ss2_qmpphy: phy@fdf000 {
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss2_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss2_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_ss2_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
};
cnoc_main: interconnect@1500000 {
@@ -3445,8 +3526,23 @@ usb_1_ss2_dwc3: usb@a000000 {
dma-coherent;
- port {
- usb_1_ss2_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss2_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss2_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -3514,8 +3610,15 @@ usb_2_dwc3: usb@a200000 {
phy-names = "usb2-phy";
maximum-speed = "high-speed";
- port {
- usb_2_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_2_dwc3_hs: endpoint {
+ };
};
};
};
@@ -3590,8 +3693,23 @@ usb_1_ss0_dwc3: usb@a600000 {
dma-coherent;
- port {
- usb_1_ss0_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss0_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss0_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -3673,8 +3791,23 @@ usb_1_ss1_dwc3: usb@a800000 {
dma-coherent;
- port {
- usb_1_ss1_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
+ };
};
};
};
--
2.39.2
^ permalink raw reply related
* [PATCH v3 7/9] arm64: dts: qcom: sc8280xp: describe USB signals properly
From: Dmitry Baryshkov @ 2024-04-01 20:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org>
Follow example of other platforms. Rename HS graph nodes to contain
'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 20 ++++----
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 ++++----
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 54 ++++++++++++++++++++--
3 files changed, 70 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index 41215567b3ae..a2627ab4db9a 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -56,7 +56,7 @@ port@0 {
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_0_role_switch>;
+ remote-endpoint = <&usb_0_dwc3_hs>;
};
};
@@ -91,7 +91,7 @@ port@0 {
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_1_role_switch>;
+ remote-endpoint = <&usb_1_dwc3_hs>;
};
};
@@ -675,6 +675,10 @@ &usb_0_dwc3 {
dr_mode = "host";
};
+&usb_0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_0_hsphy {
vdda-pll-supply = <&vreg_l9d>;
vdda18-supply = <&vreg_l1c>;
@@ -700,10 +704,6 @@ &usb_0_qmpphy_out {
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_0_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
-};
-
&usb_1 {
status = "okay";
};
@@ -712,6 +712,10 @@ &usb_1_dwc3 {
dr_mode = "host";
};
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
+};
+
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l4b>;
vdda18-supply = <&vreg_l1c>;
@@ -737,10 +741,6 @@ &usb_1_qmpphy_out {
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_1_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&xo_board_clk {
clock-frequency = <38400000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 15ae94c1602d..53252bb93d9e 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -115,7 +115,7 @@ port@0 {
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_0_role_switch>;
+ remote-endpoint = <&usb_0_dwc3_hs>;
};
};
@@ -150,7 +150,7 @@ port@0 {
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_1_role_switch>;
+ remote-endpoint = <&usb_1_dwc3_hs>;
};
};
@@ -1102,6 +1102,10 @@ &usb_0_dwc3 {
dr_mode = "host";
};
+&usb_0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_0_hsphy {
vdda-pll-supply = <&vreg_l9d>;
vdda18-supply = <&vreg_l1c>;
@@ -1127,10 +1131,6 @@ &usb_0_qmpphy_out {
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_0_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
-};
-
&usb_1 {
status = "okay";
};
@@ -1139,6 +1139,10 @@ &usb_1_dwc3 {
dr_mode = "host";
};
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
+};
+
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l4b>;
vdda18-supply = <&vreg_l1c>;
@@ -1164,10 +1168,6 @@ &usb_1_qmpphy_out {
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_1_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 9f6d98fbc28e..41caa8713cfd 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3164,6 +3164,14 @@ port@0 {
usb_0_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_0_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_0_dwc3_ss>;
+ };
+ };
+
port@2 {
reg = <2>;
@@ -3217,6 +3225,14 @@ port@0 {
usb_1_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+
port@2 {
reg = <2>;
@@ -3420,8 +3436,23 @@ usb_0_dwc3: usb@a600000 {
phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_0_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_0_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_0_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -3482,8 +3513,23 @@ usb_1_dwc3: usb@a800000 {
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_1_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ };
};
};
};
--
2.39.2
^ permalink raw reply related
* [PATCH v3 6/9] arm64: dts: qcom: sc8180x: describe USB signals properly
From: Dmitry Baryshkov @ 2024-04-01 20:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org>
Follow example of other platforms. Rename HS graph nodes to contain
'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 16 ++++----
arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 20 +++++-----
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 46 +++++++++++++++++++---
3 files changed, 58 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
index 6f2e1c732ed3..93846ff42606 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
@@ -66,7 +66,7 @@ port@0 {
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_prim_role_switch>;
+ remote-endpoint = <&usb_prim_dwc3_hs>;
};
};
@@ -101,7 +101,7 @@ port@0 {
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_sec_role_switch>;
+ remote-endpoint = <&usb_sec_dwc3_hs>;
};
};
@@ -580,6 +580,10 @@ &usb_prim_dwc3 {
dr_mode = "host";
};
+&usb_prim_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_prim_qmpphy_dp_in {
remote-endpoint = <&mdss_dp0_out>;
};
@@ -588,8 +592,8 @@ &usb_prim_qmpphy_out {
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_prim_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
+&usb_sec_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
};
&usb_sec_hsphy {
@@ -617,10 +621,6 @@ &usb_sec_qmpphy_out {
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_sec_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&usb_sec {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
index bfee60c93ccc..65d923497a05 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
@@ -71,7 +71,7 @@ port@0 {
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_prim_role_switch>;
+ remote-endpoint = <&usb_prim_dwc3_hs>;
};
};
@@ -106,7 +106,7 @@ port@0 {
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_sec_role_switch>;
+ remote-endpoint = <&usb_sec_dwc3_hs>;
};
};
@@ -648,6 +648,10 @@ &usb_prim_dwc3 {
dr_mode = "host";
};
+&usb_prim_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_prim_qmpphy_dp_in {
remote-endpoint = <&mdss_dp0_out>;
};
@@ -656,10 +660,6 @@ &usb_prim_qmpphy_out {
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_prim_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
-};
-
&usb_sec_hsphy {
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda18-supply = <&vreg_l12a_1p8>;
@@ -685,10 +685,6 @@ &usb_sec_qmpphy_out {
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_sec_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&usb_sec {
status = "okay";
};
@@ -697,6 +693,10 @@ &usb_sec_dwc3 {
dr_mode = "host";
};
+&usb_sec_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
+};
+
&wifi {
memory-region = <&wlan_mem>;
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index bae89761dae1..6346d6b6c196 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -2508,7 +2508,9 @@ port@0 {
port@1 {
reg = <1>;
- usb_prim_qmpphy_usb_ss_in: endpoint {};
+ usb_prim_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_prim_dwc3_ss>;
+ };
};
port@2 {
@@ -2553,7 +2555,9 @@ port@0 {
port@1 {
reg = <1>;
- usb_sec_qmpphy_usb_ss_in: endpoint {};
+ usb_sec_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_sec_dwc3_ss>;
+ };
};
port@2 {
@@ -2633,8 +2637,23 @@ usb_prim_dwc3: usb@a600000 {
phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_prim_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_prim_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_prim_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -2690,8 +2709,23 @@ usb_sec_dwc3: usb@a800000 {
phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_sec_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_sec_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_sec_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>;
+ };
};
};
};
--
2.39.2
^ permalink raw reply related
* [PATCH v3 5/9] arm64: dts: qcom: sc8180x: switch USB+DP QMP PHYs to new bindings
From: Dmitry Baryshkov @ 2024-04-01 20:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org>
To follow other Qualcomm platforms, update QMP USB+DP PHYs to use newer
bindings rather than old bindings which had PHYs as subdevices.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 122 ++++++++++++----------------------
1 file changed, 41 insertions(+), 81 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index a086dbe0d910..bae89761dae1 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8180x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -2472,28 +2473,25 @@ usb_sec_hsphy: phy@88e3000 {
status = "disabled";
};
- usb_prim_qmpphy: phy@88e9000 {
+ usb_prim_qmpphy: phy@88e8000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
- reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x38>,
- <0 0x088ea000 0 0x40>;
- reg-names = "reg-base", "dp_com";
+ reg = <0 0x088e8000 0 0x3000>;
+
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "aux",
- "ref_clk_src",
"ref",
- "com_aux";
+ "com_aux",
+ "usb3_pipe";
+
resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
<&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
reset-names = "phy", "common";
#clock-cells = <1>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #phy-cells = <1>;
status = "disabled";
@@ -2507,59 +2505,38 @@ port@0 {
usb_prim_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_prim_qmpphy_usb_ss_in: endpoint {};
+ };
+
port@2 {
reg = <2>;
usb_prim_qmpphy_dp_in: endpoint {};
};
};
-
- usb_prim_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088e9200 0 0x200>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x218>,
- <0 0x088e9600 0 0x200>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_prim_phy_pipe_clk_src";
- };
-
- usb_prim_dpphy: dp-phy@88ea200 {
- reg = <0 0x088ea200 0 0x200>,
- <0 0x088ea400 0 0x200>,
- <0 0x088eaa00 0 0x200>,
- <0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
};
usb_sec_qmpphy: phy@88ee000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
- reg = <0 0x088ee000 0 0x18c>,
- <0 0x088ed000 0 0x10>,
- <0 0x088ef000 0 0x40>;
- reg-names = "reg-base", "dp_com";
+ reg = <0 0x088ed000 0 0x3000>;
+
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "aux",
- "ref_clk_src",
"ref",
- "com_aux";
+ "com_aux",
+ "usb3_pipe";
resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
#clock-cells = <1>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #phy-cells = <1>;
status = "disabled";
@@ -2573,37 +2550,18 @@ port@0 {
usb_sec_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_sec_qmpphy_usb_ss_in: endpoint {};
+ };
+
port@2 {
reg = <2>;
usb_sec_qmpphy_dp_in: endpoint {};
};
};
-
- usb_sec_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088ee200 0 0x200>,
- <0 0x088ee400 0 0x200>,
- <0 0x088eec00 0 0x218>,
- <0 0x088ee600 0 0x200>,
- <0 0x088ee800 0 0x200>,
- <0 0x088eea00 0 0x100>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_sec_phy_pipe_clk_src";
- };
-
- usb_sec_dpphy: dp-phy@88ef200 {
- reg = <0 0x088ef200 0 0x200>,
- <0 0x088ef400 0 0x200>,
- <0 0x088efa00 0 0x200>,
- <0 0x088ef600 0 0x200>,
- <0 0x088ef800 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- clock-output-names = "qmp_dptx1_phy_pll_link_clk",
- "qmp_dptx1_phy_pll_vco_div_clk";
- };
};
system-cache-controller@9200000 {
@@ -2672,7 +2630,7 @@ usb_prim_dwc3: usb@a600000 {
iommus = <&apps_smmu 0x140 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>;
+ phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
port {
@@ -2729,7 +2687,7 @@ usb_sec_dwc3: usb@a800000 {
iommus = <&apps_smmu 0x160 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>;
+ phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
port {
@@ -3046,9 +3004,10 @@ mdss_dp0: displayport-controller@ae90000 {
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
- assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
+ assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
- phys = <&usb_prim_dpphy>;
+ phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
@@ -3122,9 +3081,10 @@ mdss_dp1: displayport-controller@ae98000 {
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
- assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
+ assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
- phys = <&usb_sec_dpphy>;
+ phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
@@ -3271,12 +3231,12 @@ dispcc: clock-controller@af00000 {
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>,
- <&usb_prim_dpphy 0>,
- <&usb_prim_dpphy 1>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&edp_phy 0>,
<&edp_phy 1>,
- <&usb_sec_dpphy 0>,
- <&usb_sec_dpphy 1>;
+ <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
clock-names = "bi_tcxo",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
--
2.39.2
^ permalink raw reply related
* [PATCH v3 4/9] arm64: dts: qcom: sm8250: add a link between DWC3 and QMP PHY
From: Dmitry Baryshkov @ 2024-04-01 20:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org>
The SuperSpeed signals originate from the DWC3 host controller and then
are routed through the Combo QMP PHY, where they are multiplexed with
the DisplayPort signals. Add corresponding OF graph link.
Reported-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 440bbb89bf8a..cfc07dd9d0ec 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3917,6 +3917,10 @@ port@0 {
port@1 {
reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss_out>;
+ };
};
port@2 {
@@ -4195,8 +4199,24 @@ usb_1_dwc3: usb@a600000 {
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_1_dwc3_hs_out: endpoint {};
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss_out: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ };
+ };
};
};
};
--
2.39.2
^ permalink raw reply related
* [PATCH v3 3/9] arm64: dts: qcom: sm8250: describe HS signals properly
From: Dmitry Baryshkov @ 2024-04-01 20:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org>
The OF graph should describe physical signals. There is no 'role switch'
signal between Type-C connector and the DWC3 USB controller. Instead
there is a HighSpeed signal lane between DWC3 controller and the USB-C
connector. Rename endpoints in accordance to that (this follows the
example lead by other plaforms, including QRB2210 RB1, QRB4210 RB2 and
all PMIC GLINK platforms).
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 ++++----
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index cd0db4f31d4a..44239d1e57e9 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -1356,8 +1356,8 @@ &usb_1_dwc3 {
usb-role-switch;
};
-&usb_1_role_switch_out {
- remote-endpoint = <&pm8150b_role_switch_in>;
+&usb_1_dwc3_hs_out {
+ remote-endpoint = <&pm8150b_hs_in>;
};
&usb_1_hsphy {
@@ -1465,8 +1465,8 @@ ports {
port@0 {
reg = <0>;
- pm8150b_role_switch_in: endpoint {
- remote-endpoint = <&usb_1_role_switch_out>;
+ pm8150b_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs_out>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
index 2042020eb0dd..6cc0bcb40f1f 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
@@ -659,8 +659,8 @@ ports {
port@0 {
reg = <0>;
- pm8150b_role_switch_in: endpoint {
- remote-endpoint = <&usb_1_role_switch_out>;
+ pm8150b_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs_out>;
};
};
};
@@ -723,8 +723,8 @@ &usb_1_hsphy {
status = "okay";
};
-&usb_1_role_switch_out {
- remote-endpoint = <&pm8150b_role_switch_in>;
+&usb_1_dwc3_hs_out {
+ remote-endpoint = <&pm8150b_hs_in>;
};
&ufs_mem_hc {
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 7f2333c9d17d..440bbb89bf8a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4196,7 +4196,7 @@ usb_1_dwc3: usb@a600000 {
phy-names = "usb2-phy", "usb3-phy";
port {
- usb_1_role_switch_out: endpoint {};
+ usb_1_dwc3_hs_out: endpoint {};
};
};
};
--
2.39.2
^ permalink raw reply related
* [PATCH v3 1/9] dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks
From: Dmitry Baryshkov @ 2024-04-01 20:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org>
On the affected Qualcomm platforms the display clock controller has
additional DP input clocks, describe them in DT schema.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../bindings/clock/qcom,dispcc-sm8x50.yaml | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
index 59cc88a52f6b..5831579b572e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,sm8350-dispcc
clocks:
+ minItems: 7
items:
- description: Board XO source
- description: Byte clock from DSI PHY0
@@ -35,8 +36,15 @@ properties:
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY
- description: VCO DIV clock from DP PHY
+ - description: Link clock from eDP PHY
+ - description: VCO DIV clock from eDP PHY
+ - description: Link clock from DP1 PHY
+ - description: VCO DIV clock from DP1 PHY
+ - description: Link clock from DP2 PHY
+ - description: VCO DIV clock from DP2 PHY
clock-names:
+ minItems: 7
items:
- const: bi_tcxo
- const: dsi0_phy_pll_out_byteclk
@@ -45,6 +53,12 @@ properties:
- const: dsi1_phy_pll_out_dsiclk
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
+ - const: edp_phy_pll_link_clk
+ - const: edp_phy_pll_vco_div_clk
+ - const: dptx1_phy_pll_link_clk
+ - const: dptx1_phy_pll_vco_div_clk
+ - const: dptx2_phy_pll_link_clk
+ - const: dptx2_phy_pll_vco_div_clk
'#clock-cells':
const: 1
@@ -68,6 +82,20 @@ properties:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sc8180x-dispcc
+ then:
+ properties:
+ clocks:
+ maxItems: 7
+ clock-names:
+ maxItems: 7
+
required:
- compatible
- reg
--
2.39.2
^ permalink raw reply related
* [PATCH v3 2/9] arm64: dts: qcom: sc8180x: correct dispcc clocks
From: Dmitry Baryshkov @ 2024-04-01 20:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org>
Correct the clocks being used by the display clock controller on the
SC8180X platform (to match the schema):
- Drop the sleep clock
- Add DSI clocks
- Reorder eDP / DP clocks
This changes the order of clocks, however it should be noted that the
clock list was neither correct nor followed the schema beforehand.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 32afc78d5b76..a086dbe0d910 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -3267,21 +3267,27 @@ dispcc: clock-controller@af00000 {
compatible = "qcom,sc8180x-dispcc";
reg = <0 0x0af00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&sleep_clk>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>,
<&usb_prim_dpphy 0>,
<&usb_prim_dpphy 1>,
- <&usb_sec_dpphy 0>,
- <&usb_sec_dpphy 1>,
<&edp_phy 0>,
- <&edp_phy 1>;
+ <&edp_phy 1>,
+ <&usb_sec_dpphy 0>,
+ <&usb_sec_dpphy 1>;
clock-names = "bi_tcxo",
- "sleep_clk",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
"dp_phy_pll_link_clk",
"dp_phy_pll_vco_div_clk",
- "dptx1_phy_pll_link_clk",
- "dptx1_phy_pll_vco_div_clk",
"edp_phy_pll_link_clk",
- "edp_phy_pll_vco_div_clk";
+ "edp_phy_pll_vco_div_clk",
+ "dptx1_phy_pll_link_clk",
+ "dptx1_phy_pll_vco_div_clk";
power-domains = <&rpmhpd SC8180X_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
--
2.39.2
^ permalink raw reply related
* [PATCH v3 0/9] arm64: dts: qcom: fix description of the Type-C signals
From: Dmitry Baryshkov @ 2024-04-01 20:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
Rename the HS link between usb-c-connector and the DWC3 USB controller.
Add missing graph connection between the QMP PHY and DWC3 USB
controller.
Reported-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes in v3:
- Fixed dispcc bindings / clock inputs on sc8180x (Rob Herring)
- Link to v2: https://lore.kernel.org/r/20240331-typec-fix-sm8250-v2-0-857acb6bd88e@linaro.org
Changes in v2:
- Fixed other platforms in addition to sm8250 (Bryan)
- Link to v1: https://lore.kernel.org/r/20240322-typec-fix-sm8250-v1-0-1ac22b333ea9@linaro.org
---
Dmitry Baryshkov (9):
dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks
arm64: dts: qcom: sc8180x: correct dispcc clocks
arm64: dts: qcom: sm8250: describe HS signals properly
arm64: dts: qcom: sm8250: add a link between DWC3 and QMP PHY
arm64: dts: qcom: sc8180x: switch USB+DP QMP PHYs to new bindings
arm64: dts: qcom: sc8180x: describe USB signals properly
arm64: dts: qcom: sc8280xp: describe USB signals properly
arm64: dts: qcom: x1e80100: describe USB signals properly
arm64: dts: qcom: sm8150-hdk: rename Type-C HS endpoints
.../bindings/clock/qcom,dispcc-sm8x50.yaml | 28 ++++
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 +-
.../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 16 +-
arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 20 +--
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 182 ++++++++++-----------
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 20 +--
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 +--
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 54 +++++-
arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 4 +-
.../boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 8 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++-
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 149 ++++++++++++++++-
12 files changed, 380 insertions(+), 153 deletions(-)
---
base-commit: a6bd6c9333397f5a0e2667d4d82fef8c970108f2
change-id: 20240322-typec-fix-sm8250-33c47a03a056
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
^ permalink raw reply
* Re: [PATCH] dt-bindings: pci: altera: covert to yaml
From: matthew.gerlach @ 2024-04-01 20:25 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: joyce.ooi, bhelgaas, lpieralisi, kw, robh, krzysztof.kozlowski+dt,
conor+dt, linux-pci, devicetree, linux-kernel
In-Reply-To: <bfa6150b-e27e-41c3-a1a7-41e46f52f6ea@linaro.org>
On Fri, 29 Mar 2024, Krzysztof Kozlowski wrote:
> On 29/03/2024 18:00, matthew.gerlach@linux.intel.com wrote:
>> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>
>> Covert the device tree bindings for the Altera Root
>> Port controller from text to yaml.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>
> ...
>
>> diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
>> new file mode 100644
>> index 000000000000..8f1ad1362ad1
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
>> @@ -0,0 +1,106 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +# Copyright (C) 2024, Intel Corporation
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Altera PCIe Root Port
>> +
>> +maintainers:
>> + - Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> +
>> +allOf:
>> + - $ref: /schemas/pci/pci-bus.yaml#
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - altr,pcie-root-port-1.0
>> + - altr,pcie-root-port-2.0
>> +
>> + reg:
>> + minItems: 2
>> + maxItems: 3
>> +
>> + reg-names:
>> + description:
>> + TX slave port region (Txs)
>> + Control register access region (Cra)
>> + Hard IP region if altr,pcie-root-port-2.0 (Hip)
>
> All these go to reg as description of items.
>
> Both - reg and reg-names - need constraints per variant in
> allOf:if:then:. Move allOf: to bottom of file, just like example-schema
> is showing.
I understand. I added a constraint and moved allOf: to bottom of file,
just like the example-schema is showing.
>
>
>> +
>> + items:
>> + - const: Txs
>> + - const: Cra
>> + - const: Hip
>> + minItems: 2
>> +
>> + device_type:
>> + const: pci
>
> I don't think you need it.
I removed it.
>
>> +
>> + "#address-cells":
>> + const: 3
>
> Drop
Dropped
>
>> +
>> + "#size-cells":
>> + const: 2
>
> Drop
Dropped
>
>> +
>> + interrupts:
>> + minItems: 1
>
> This should be maxItems.
I changed it to maxItems
>
>> +
>> + interrupt-map-mask:
>> + items:
>> + - const: 0
>> + - const: 0
>> + - const: 0
>> + - const: 7
>
> I guess as well.
>
>> +
>> + interrupt-map:
>> + maxItems: 4
>> +
>> + "#interrupt-cells":
>> + const: 1
>
> Drop
If I remove "#interrupt-cells", then I get the following error:
/home/mgerlach/git/linux-next/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml:
properties: '#interrupt-cells' is a dependency of 'interrupt-map'
from schema $id:
http://devicetree.org/meta-schemas/interrupts.yaml#
>
>> +
>> + msi-parent:
>> + description: Link to the hardware entity that serves as the MSI controller.
>
> Just true.
>
> Please open existing, recent PCI bindings and look how it is done.
I see a couple of examples of the following:
msi-parent: true
>
>> +
>> + bus-range:
>> + description: PCI bus numbers covered.
>
> Drop
Dropped.
>
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - device_type
>> + - "#address-cells"
>> + - "#size-cells"
>> + - interrupts
>> + - interrupt-map
>> + - interrupt-map-mask
>> + - "#interrupt-cells"
>
> This also needs cleaning.
I removed Dropped items.
>
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + pcie_0: pcie@c00000000 {
>> + compatible = "altr,pcie-root-port-1.0";
>> + reg = <0xc0000000 0x20000000>,
>> + <0xff220000 0x00004000>;
>
> Misaligned.
I fixed the alignments.
>
>> + reg-names = "Txs", "Cra";
>> + interrupt-parent = <&hps_0_arm_gic_0>;
>> + interrupts = <0 40 4>;
>
> Use defines for common constnats.
I added constants from arm_gic.h and irq.h.
>
>> + #interrupt-cells = <1>;
>> + bus-range = <0x0 0xFF>;
>
> Lowercase hex
I changed to lower case.
>
>> + device_type = "pci";
>> + msi-parent = <&msi_to_gic_gen_0>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &pcie_intc 1>,
>> + <0 0 0 2 &pcie_intc 2>,
>> + <0 0 0 3 &pcie_intc 3>,
>> + <0 0 0 4 &pcie_intc 4>;
>> + ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
>> + 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
>
> Misaligned.
>
>
> Best regards,
> Krzysztof
>
>
Thank you for the timely and thorough review. Version 2 of the patch will
be submitted soon.
Matthew Gerlach
^ permalink raw reply
* Re: [PATCH 1/6] dt-bindings: adc: ad7173: add support for ad411x
From: David Lechner @ 2024-04-01 20:22 UTC (permalink / raw)
To: dumitru.ceclan
Cc: Lars-Peter Clausen, Michael Hennerich, Jonathan Cameron,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-iio,
devicetree, linux-kernel, Dumitru Ceclan
In-Reply-To: <CAMknhBHeKAQ45=5-dL1T1tv-mZcPN+bNo3vxWJYgWpEPE+8p3Q@mail.gmail.com>
On Mon, Apr 1, 2024 at 2:37 PM David Lechner <dlechner@baylibre.com> wrote:
>
> On Mon, Apr 1, 2024 at 10:10 AM Dumitru Ceclan via B4 Relay
> <devnull+dumitru.ceclan.analog.com@kernel.org> wrote:
> >
> > From: Dumitru Ceclan <dumitru.ceclan@analog.com>
> >
> > Add support for: AD4111, AD4112, AD4114, AD4115, AD4116.
> >
> > AD411x family ADCs support a VCOM pin, dedicated for single-ended usage.
> > AD4111/AD4112 support current channels, usage is implemented by
> > specifying channel reg values bigger than 15.
> >
> > Signed-off-by: Dumitru Ceclan <dumitru.ceclan@analog.com>
> > ---
> > .../devicetree/bindings/iio/adc/adi,ad7173.yaml | 59 +++++++++++++++++++++-
> > 1 file changed, 57 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7173.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7173.yaml
> > index ea6cfcd0aff4..bba2de0a52f3 100644
> > --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7173.yaml
> > +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7173.yaml
Also, I just noticed that AD411x have only one AVDD input instead of
AVDD1 and AVDD2. So we need an if statement that says if properties:
compatible: enum: - adi,ad411x, then properties: avdd2-supply: false.
^ permalink raw reply
* [PATCH v7 8/8] iio: accel: adxl345: Add spi-3wire option
From: Lothar Rubusch @ 2024-04-01 19:49 UTC (permalink / raw)
To: lars, Michael.Hennerich, jic23, robh+dt, krzysztof.kozlowski+dt,
conor+dt
Cc: linux-iio, devicetree, linux-kernel, eraretuya, l.rubusch
In-Reply-To: <20240401194906.56810-1-l.rubusch@gmail.com>
Add a setup function implementation to the spi module to enable spi-3wire
when specified in the device-tree. If spi-3wire is not specified in the
device-tree, NULL is returned as bus pre-initialization. This behavior
is identical to the i2c initialization, hence the default initialization.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
drivers/iio/accel/adxl345.h | 1 +
drivers/iio/accel/adxl345_spi.c | 10 +++++++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h
index e859c01d4..3d5c8719d 100644
--- a/drivers/iio/accel/adxl345.h
+++ b/drivers/iio/accel/adxl345.h
@@ -31,6 +31,7 @@
#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) /* Set the g range */
#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) /* Left-justified (MSB) mode */
#define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */
+#define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6) /* 3-wire SPI mode */
#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) /* Enable a self test */
#define ADXL345_DATA_FORMAT_2G 0
diff --git a/drivers/iio/accel/adxl345_spi.c b/drivers/iio/accel/adxl345_spi.c
index 1c0513bd3..57e16b441 100644
--- a/drivers/iio/accel/adxl345_spi.c
+++ b/drivers/iio/accel/adxl345_spi.c
@@ -20,6 +20,11 @@ static const struct regmap_config adxl345_spi_regmap_config = {
.read_flag_mask = BIT(7) | BIT(6),
};
+static int adxl345_spi_setup(struct device *dev, struct regmap *regmap)
+{
+ return regmap_write(regmap, ADXL345_REG_DATA_FORMAT, ADXL345_DATA_FORMAT_SPI_3WIRE);
+}
+
static int adxl345_spi_probe(struct spi_device *spi)
{
struct regmap *regmap;
@@ -33,7 +38,10 @@ static int adxl345_spi_probe(struct spi_device *spi)
if (IS_ERR(regmap))
return dev_err_probe(&spi->dev, PTR_ERR(regmap), "Error initializing regmap\n");
- return adxl345_core_probe(&spi->dev, regmap, NULL);
+ if (spi->mode & SPI_3WIRE)
+ return adxl345_core_probe(&spi->dev, regmap, adxl345_spi_setup);
+ else
+ return adxl345_core_probe(&spi->dev, regmap, NULL);
}
static const struct adxl345_chip_info adxl345_spi_info = {
--
2.25.1
^ permalink raw reply related
* [PATCH v7 7/8] iio: accel: adxl345: Add comment to probe
From: Lothar Rubusch @ 2024-04-01 19:49 UTC (permalink / raw)
To: lars, Michael.Hennerich, jic23, robh+dt, krzysztof.kozlowski+dt,
conor+dt
Cc: linux-iio, devicetree, linux-kernel, eraretuya, l.rubusch
In-Reply-To: <20240401194906.56810-1-l.rubusch@gmail.com>
Add a comment to the probe() function to describe the passed function
pointer argument in particular.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
drivers/iio/accel/adxl345_core.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c
index 5d0f3243e..006ce66c0 100644
--- a/drivers/iio/accel/adxl345_core.c
+++ b/drivers/iio/accel/adxl345_core.c
@@ -168,6 +168,16 @@ static void adxl345_powerdown(void *regmap)
regmap_write(regmap, ADXL345_REG_POWER_CTL, ADXL345_POWER_CTL_STANDBY);
}
+/**
+ * adxl345_core_probe() - probe and setup for the adxl345 accelerometer,
+ * also covers the adlx375 accelerometer
+ * @dev: Driver model representation of the device
+ * @regmap: Regmap instance for the device
+ * @setup: Setup routine to be executed right before the standard device
+ * setup
+ *
+ * Return: 0 on success, negative errno on error
+ */
int adxl345_core_probe(struct device *dev, struct regmap *regmap,
int (*setup)(struct device*, struct regmap*))
{
--
2.25.1
^ permalink raw reply related
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