* Re: [PATCH v7 09/15] media: bcm2835-unicam: Add support for CCP2/CSI2 camera interface
From: Tomi Valkeinen @ 2024-04-02 6:00 UTC (permalink / raw)
To: Laurent Pinchart
Cc: linux-media, Dave Stevenson, David Plowman, Jean-Michel Hautbois,
Hans Verkuil, Naushir Patuck, Sakari Ailus, kernel-list,
linux-rpi-kernel, Florian Fainelli, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Conor Dooley, Krzysztof Kozlowski,
Rob Herring, devicetree
In-Reply-To: <20240401135216.GF8623@pendragon.ideasonboard.com>
On 01/04/2024 16:52, Laurent Pinchart wrote:
> On Wed, Mar 27, 2024 at 01:21:09PM +0200, Tomi Valkeinen wrote:
>> On 25/03/2024 00:08, Laurent Pinchart wrote:
>>> From: Dave Stevenson <dave.stevenson@raspberrypi.com>
>>>
>>> Add a driver for the Unicam camera receiver block on BCM283x processors.
>>> It is represented as two video device nodes: unicam-image and
>>> unicam-embedded which are connected to an internal subdev (named
>>> unicam-subdev) in order to manage streams routing.
>>
>> Shouldn't this driver call get_frame_desc somewhere to get the VC and DT
>> for the streams?
>
> Generally speaking, yes. In practice, configuring the DT from the frame
> descriptor is probably not very useful, as CSI-2 sources that transmit
> image data using a DT that doesn't correspond to the media bus code are
> not very common and I don't expect this to be needed for unicam.
Perhaps, but if the driver gets the DT from the frame descriptor, then
the driver doesn't need to have tables for the DTs.
Although when I did this with the RPi CFE driver, I also implemented a
fallback mechanism for the cases when there is no get_frame_desc, and so
I still had to keep the DT tables...
Tomi
^ permalink raw reply
* [PATCH v2 0/3] Add i.MX8Q HSIO PHY driver support
From: Richard Zhu @ 2024-04-02 5:45 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, frank.li,
conor+dt
Cc: hongxing.zhu, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, kernel, imx
v2 changes:
- Place the dt-bindings header file changes as the first one
in the patch-set, make the annotation more clear, and add
Frank's Reviewed-by tag into this patch.
i.MX8Q HSIO module has PHY and mix control regions.
This patch-set adds i.MX8Q HSIO PHY driver support, and provides
standard PHY phandles that can be used by i.MX8Q PCIe or SATA
driver later.
[PATCH v2 1/3] dt-bindings: phy: phy-imx8-pcie: Add binding for
[PATCH v2 2/3] dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY binding
[PATCH v2 3/3] phy: freescale: imx8q-hsio: Add i.MX8Q HSIO PHY driver
Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml | 143 ++++++++++++++++++++++++
drivers/phy/freescale/Kconfig | 8 ++
drivers/phy/freescale/Makefile | 1 +
drivers/phy/freescale/phy-fsl-imx8q-hsio.c | 518 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
include/dt-bindings/phy/phy-imx8-pcie.h | 29 +++++
5 files changed, 699 insertions(+)
^ permalink raw reply
* [PATCH v2 1/3] dt-bindings: phy: phy-imx8-pcie: Add binding for i.MX8Q HSIO SerDes PHY
From: Richard Zhu @ 2024-04-02 5:45 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, frank.li,
conor+dt
Cc: hongxing.zhu, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, kernel, imx
In-Reply-To: <1712036704-21064-1-git-send-email-hongxing.zhu@nxp.com>
Add binding for controller ID and HSIO configuration setting of the
i.MX8Q HSIO SerDes PHY.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
include/dt-bindings/phy/phy-imx8-pcie.h | 29 +++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h
index 8bbe2d6538d8..3292c8be3354 100644
--- a/include/dt-bindings/phy/phy-imx8-pcie.h
+++ b/include/dt-bindings/phy/phy-imx8-pcie.h
@@ -11,4 +11,33 @@
#define IMX8_PCIE_REFCLK_PAD_INPUT 1
#define IMX8_PCIE_REFCLK_PAD_OUTPUT 2
+/*
+ * i.MX8QM HSIO subsystem has three lane PHYs and three controllers:
+ * PCIEA(2 lanes capapble PCIe controller), PCIEB (only support one
+ * lane) and SATA.
+ *
+ * In the different use cases. PCIEA can be binded to PHY lane0, lane1
+ * or Lane0 and lane1. PCIEB can be binded to lane1 or lane2 PHY. SATA
+ * can only be binded to last lane2 PHY.
+ *
+ * Define i.MX8Q HSIO controller ID here to specify the controller
+ * binded to the PHY.
+ * Meanwhile, i.MX8QXP HSIO subsystem has one lane PHY and PCIEB(only
+ * support one lane) controller.
+ */
+#define IMX8Q_HSIO_PCIEA_ID 0
+#define IMX8Q_HSIO_PCIEB_ID 1
+#define IMX8Q_HSIO_SATA_ID 2
+
+/*
+ * On i.MX8QM, PCIEA is mandatory required if the HSIO is enabled.
+ * Define configurations beside PCIEA is enabled.
+ *
+ * On i.MX8QXP, HSIO module only has PCIEB and one lane PHY.
+ * The "IMX8Q_HSIO_CFG_PCIEB" can be used on i.MX8QXP platforms.
+ */
+#define IMX8Q_HSIO_CFG_SATA 1
+#define IMX8Q_HSIO_CFG_PCIEB 2
+#define IMX8Q_HSIO_CFG_PCIEBSATA 3
+
#endif /* _DT_BINDINGS_IMX8_PCIE_H */
--
2.37.1
^ permalink raw reply related
* [PATCH v2 2/3] dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY binding
From: Richard Zhu @ 2024-04-02 5:45 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, frank.li,
conor+dt
Cc: hongxing.zhu, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, kernel, imx
In-Reply-To: <1712036704-21064-1-git-send-email-hongxing.zhu@nxp.com>
Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding.
- Use the controller ID to specify which controller is binded to the
PHY.
- Introduce one HSIO configuration, mandatory required to set
"PCIE_AB_SELECT" and "PHY_X1_EPCS_SEL" during the initialization.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
.../bindings/phy/fsl,imx8q-hsio.yaml | 143 ++++++++++++++++++
1 file changed, 143 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml
new file mode 100644
index 000000000000..506551d4d94a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,imx8q-hsio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8Q SoC series HSIO SERDES PHY
+
+maintainers:
+ - Richard Zhu <hongxing.zhu@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qxp-serdes
+ - fsl,imx8qm-serdes
+ reg:
+ minItems: 4
+ maxItems: 4
+
+ "#phy-cells":
+ const: 3
+ description: |
+ The first number defines the ID of the PHY contained in the HSIO macro.
+ The second defines controller ID binded to the PHY. The third defines the
+ HSIO configuratons refer to the different use cases. They are defined in
+ dt-bindings/phy/phy-imx8-pcie.h
+
+ reg-names:
+ items:
+ - const: reg
+ - const: phy
+ - const: ctrl
+ - const: misc
+
+ clocks:
+ minItems: 5
+ maxItems: 14
+
+ clock-names:
+ minItems: 5
+ maxItems: 14
+
+ fsl,refclk-pad-mode:
+ description: |
+ Specifies the mode of the refclk pad used. It can be UNUSED(PHY
+ refclock is derived from SoC internal source), INPUT(PHY refclock
+ is provided externally via the refclk pad) or OUTPUT(PHY refclock
+ is derived from SoC internal source and provided on the refclk pad).
+ Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
+ to be used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2 ]
+
+ power-domains:
+ description: |
+ i.MX8Q HSIO SerDes power domains. i.MX8QXP has one SerDes power domains.
+ And i.MX8QM has two.
+ minItems: 1
+ maxItems: 2
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - fsl,refclk-pad-mode
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qxp-serdes
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: apb_pclk0
+ - const: pclk0
+ - const: phy0_crr
+ - const: ctl0_crr
+ - const: misc_crr
+ power-domains:
+ minItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qm-serdes
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: pclk0
+ - const: pclk1
+ - const: apb_pclk0
+ - const: apb_pclk1
+ - const: pclk2
+ - const: epcs_tx
+ - const: epcs_rx
+ - const: apb_pclk2
+ - const: phy0_crr
+ - const: phy1_crr
+ - const: ctl0_crr
+ - const: ctl1_crr
+ - const: ctl2_crr
+ - const: misc_crr
+ power-domains:
+ minItems: 2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-clock.h>
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/phy/phy-imx8-pcie.h>
+
+ serdes: phy@5f1a0000 {
+ compatible = "fsl,imx8qxp-serdes";
+ reg = <0x5f1a0000 0x10000>,
+ <0x5f120000 0x10000>,
+ <0x5f140000 0x10000>,
+ <0x5f160000 0x10000>;
+ reg-names = "reg", "phy", "ctrl", "misc";
+ clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
+ <&phyx1_lpcg IMX_LPCG_CLK_4>,
+ <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
+ <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
+ <&misc_crr5_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "apb_pclk0", "pclk0", "phy0_crr", "ctl0_crr",
+ "misc_crr";
+ power-domains = <&pd IMX_SC_R_SERDES_1>;
+ #phy-cells = <3>;
+ status = "disabled";
+ };
+...
--
2.37.1
^ permalink raw reply related
* [PATCH v2 3/3] phy: freescale: imx8q-hsio: Add i.MX8Q HSIO PHY driver support
From: Richard Zhu @ 2024-04-02 5:45 UTC (permalink / raw)
To: vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, frank.li,
conor+dt
Cc: hongxing.zhu, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, kernel, imx
In-Reply-To: <1712036704-21064-1-git-send-email-hongxing.zhu@nxp.com>
Add i.MX8Q HSIO PHY driver support.
- Add one HSIO configuration property, that used to select the
"PCIE_AB_SELECT" and "PHY_X1_EPCS_SEL" during the initialization.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/phy/freescale/Kconfig | 8 +
drivers/phy/freescale/Makefile | 1 +
drivers/phy/freescale/phy-fsl-imx8q-hsio.c | 518 +++++++++++++++++++++
3 files changed, 527 insertions(+)
create mode 100644 drivers/phy/freescale/phy-fsl-imx8q-hsio.c
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index 853958fb2c06..bcddddef1cbb 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -35,6 +35,14 @@ config PHY_FSL_IMX8M_PCIE
Enable this to add support for the PCIE PHY as found on
i.MX8M family of SOCs.
+config PHY_FSL_IMX8Q_HSIO
+ tristate "Freescale i.MX8Q HSIO PHY"
+ depends on OF && HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Enable this to add support for the HSIO PHY as found on
+ i.MX8Q family of SOCs.
+
endif
config PHY_FSL_LYNX_28G
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index cedb328bc4d2..db888c37fcf9 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
+obj-$(CONFIG_PHY_FSL_IMX8Q_HSIO) += phy-fsl-imx8q-hsio.o
obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
diff --git a/drivers/phy/freescale/phy-fsl-imx8q-hsio.c b/drivers/phy/freescale/phy-fsl-imx8q-hsio.c
new file mode 100644
index 000000000000..14fc925c4f57
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-imx8q-hsio.c
@@ -0,0 +1,518 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/pci_regs.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/pcie.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#define MAX_NUM_LANES 3
+#define LANE_NUM_CLKS 5
+
+/* Parameters for the waiting for PCIe PHY PLL to lock */
+#define PHY_INIT_WAIT_USLEEP_MAX 10
+#define PHY_INIT_WAIT_TIMEOUT (1000 * PHY_INIT_WAIT_USLEEP_MAX)
+
+/* i.MX8Q HSIO registers */
+#define CTRL0 0x0
+#define APB_RSTN_0 BIT(0)
+#define APB_RSTN_1 BIT(1)
+#define PIPE_RSTN_0_MASK GENMASK(25, 24)
+#define PIPE_RSTN_1_MASK GENMASK(27, 26)
+#define MODE_MASK GENMASK(20, 17)
+#define MODE_PCIE 0x0
+#define MODE_SATA 0x4
+#define DEVICE_TYPE_MASK GENMASK(27, 24)
+#define EPCS_TXDEEMP BIT(5)
+#define EPCS_TXDEEMP_SEL BIT(6)
+#define EPCS_PHYRESET_N BIT(7)
+#define RESET_N BIT(12)
+
+#define IOB_RXENA BIT(0)
+#define IOB_TXENA BIT(1)
+#define IOB_A_0_TXOE BIT(2)
+#define IOB_A_0_M1M0_2 BIT(4)
+#define IOB_A_0_M1M0_MASK GENMASK(4, 3)
+#define PHYX1_EPCS_SEL BIT(12)
+#define PCIE_AB_SELECT BIT(13)
+#define CLKREQN_OUT_OVERRIDE GENMASK(25, 24)
+
+#define PHY_STTS0 0x4
+#define LANE0_TX_PLL_LOCK BIT(4)
+#define LANE1_TX_PLL_LOCK BIT(12)
+
+#define CTRL2 0x8
+#define LTSSM_ENABLE BIT(4)
+#define BUTTON_RST_N BIT(21)
+#define PERST_N BIT(22)
+#define POWER_UP_RST_N BIT(23)
+
+#define PCIE_STTS0 0xc
+#define PM_REQ_CORE_RST BIT(19)
+
+#define REG48_PMA_STATUS 0x30
+#define REG48_PMA_RDY BIT(7)
+
+struct imx8q_hsio_drvdata {
+ int num_lane;
+};
+
+struct imx8q_hsio_lane {
+ const char * const *clk_names;
+ struct clk_bulk_data clks[LANE_NUM_CLKS];
+ u32 clks_cnt;
+ u32 ctrl_id;
+ u32 ctrl_off;
+ u32 idx;
+ u32 phy_off;
+ struct imx8q_hsio_priv *priv;
+ struct phy *phy;
+ enum phy_mode lane_mode;
+};
+
+struct imx8q_hsio_priv {
+ void __iomem *base;
+ struct device *dev;
+ u32 refclk_pad_mode;
+ u32 hsio_cfg;
+ struct regmap *phy;
+ struct regmap *ctrl;
+ struct regmap *misc;
+ const struct imx8q_hsio_drvdata *drvdata;
+ struct imx8q_hsio_lane lane[MAX_NUM_LANES];
+};
+
+static const char * const imx8q_hsio_lan0_pcie_clks[] = {"apb_pclk0", "pclk0",
+ "ctl0_crr", "phy0_crr", "misc_crr"};
+static const char * const imx8q_hsio_lan1_pciea_clks[] = {"apb_pclk1", "pclk1",
+ "ctl0_crr", "phy0_crr", "misc_crr"};
+static const char * const imx8q_hsio_lan1_pcieb_clks[] = {"apb_pclk1", "pclk1",
+ "ctl1_crr", "phy0_crr", "misc_crr"};
+static const char * const imx8q_hsio_lan2_pcieb_clks[] = {"apb_pclk2", "pclk2",
+ "ctl1_crr", "phy1_crr", "misc_crr"};
+static const char * const imx8q_hsio_lane_sata_clks[] = {"pclk2", "epcs_tx",
+ "epcs_rx", "phy1_crr", "misc_crr"};
+
+static const struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int imx8q_hsio_init(struct phy *phy)
+{
+ int ret, i;
+ struct imx8q_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx8q_hsio_priv *priv = lane->priv;
+ struct device *dev = priv->dev;
+
+ /* Assign clocks refer to different modes */
+ switch (lane->ctrl_id) {
+ case IMX8Q_HSIO_PCIEA_ID:
+ if (lane->idx > 1) {
+ dev_err(dev, "invalid lane ID.");
+ return -EINVAL;
+ }
+
+ lane->lane_mode = PHY_MODE_PCIE;
+ lane->ctrl_off = 0;
+ lane->phy_off = 0;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (lane->idx)
+ lane->clks[i].id = imx8q_hsio_lan1_pciea_clks[i];
+ else
+ lane->clks[i].id = imx8q_hsio_lan0_pcie_clks[i];
+ }
+ break;
+ case IMX8Q_HSIO_PCIEB_ID:
+ if (lane->idx > 2) {
+ dev_err(dev, "invalid lane ID.");
+ return -EINVAL;
+ }
+
+ lane->lane_mode = PHY_MODE_PCIE;
+ if (lane->idx == 0) {
+ /* i.MX8QXP */
+ lane->ctrl_off = 0;
+ lane->phy_off = 0;
+ } else {
+ /*
+ * On i.MX8QM, only second or third lane PHY can
+ * be binded to PCIEB.
+ */
+ lane->ctrl_off = SZ_64K;
+ if (lane->idx == 1)
+ lane->phy_off = 0;
+ else /* idx == 2, the third lane is binded to PCIEB */
+ lane->phy_off = SZ_64K;
+ }
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (lane->idx == 1)
+ lane->clks[i].id = imx8q_hsio_lan1_pcieb_clks[i];
+ else if (lane->idx == 2)
+ lane->clks[i].id = imx8q_hsio_lan2_pcieb_clks[i];
+ else /* i.MX8QXP only has PCIEB, it's idx == 0 */
+ lane->clks[i].id = imx8q_hsio_lan0_pcie_clks[i];
+
+ }
+ break;
+ case IMX8Q_HSIO_SATA_ID:
+ /* On i.MX8QM, only the third lane PHY can be binded to SATA */
+ if (lane->idx != 2) {
+ dev_err(dev, "invalid lane ID.");
+ return -EINVAL;
+ }
+ lane->ctrl_off = SZ_128K;
+ lane->lane_mode = PHY_MODE_SATA;
+ lane->phy_off = SZ_64K;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++)
+ lane->clks[i].id = imx8q_hsio_lane_sata_clks[i];
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Fetch clocks */
+ ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, lane->clks);
+ if (ret)
+ return ret;
+
+ ret = clk_bulk_prepare_enable(LANE_NUM_CLKS, lane->clks);
+ if (ret)
+ return ret;
+
+ /* allow the clocks to stabilize */
+ usleep_range(200, 500);
+ return 0;
+}
+
+static int imx8q_hsio_exit(struct phy *phy)
+{
+ struct imx8q_hsio_lane *lane = phy_get_drvdata(phy);
+
+ clk_bulk_disable_unprepare(LANE_NUM_CLKS, lane->clks);
+
+ return 0;
+}
+
+static void imx8q_hsio_pcie_phy_resets(struct phy *phy)
+{
+ struct imx8q_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx8q_hsio_priv *priv = lane->priv;
+
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + CTRL2, BUTTON_RST_N);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + CTRL2, PERST_N);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + CTRL2, POWER_UP_RST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + CTRL2, BUTTON_RST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + CTRL2, PERST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + CTRL2, POWER_UP_RST_N);
+
+ if (lane->idx == 1) {
+ /* The second lane */
+ regmap_set_bits(priv->phy, lane->phy_off + CTRL0, APB_RSTN_1);
+ regmap_set_bits(priv->phy, lane->phy_off + CTRL0, PIPE_RSTN_1_MASK);
+ } else {
+ regmap_set_bits(priv->phy, lane->phy_off + CTRL0, APB_RSTN_0);
+ regmap_set_bits(priv->phy, lane->phy_off + CTRL0, PIPE_RSTN_0_MASK);
+ }
+}
+
+static void imx8q_hsio_sata_phy_resets(struct phy *phy)
+{
+ struct imx8q_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx8q_hsio_priv *priv = lane->priv;
+
+ /* clear PHY RST, then set it */
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + CTRL0, EPCS_PHYRESET_N);
+
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + CTRL0, EPCS_PHYRESET_N);
+
+ /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + CTRL0, RESET_N);
+ udelay(1);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + CTRL0, RESET_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + CTRL0, RESET_N);
+}
+
+static void imx8q_hsio_configure_clk_pad(struct phy *phy)
+{
+ bool pll = false;
+ u32 pad_mode;
+ struct imx8q_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx8q_hsio_priv *priv = lane->priv;
+
+ pad_mode = priv->refclk_pad_mode;
+ if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) {
+ pll = true;
+ regmap_update_bits(priv->misc, CTRL0,
+ IOB_A_0_TXOE | IOB_A_0_M1M0_MASK,
+ IOB_A_0_TXOE | IOB_A_0_M1M0_2);
+ }
+
+ regmap_update_bits(priv->misc, CTRL0, IOB_RXENA, pll ? 0 : IOB_RXENA);
+ regmap_update_bits(priv->misc, CTRL0, IOB_TXENA, pll ? IOB_TXENA : 0);
+}
+
+static int imx8q_hsio_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, cond;
+ struct imx8q_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx8q_hsio_priv *priv = lane->priv;
+
+ if (lane->lane_mode == PHY_MODE_PCIE)
+ imx8q_hsio_pcie_phy_resets(phy);
+ else
+ /* SATA */
+ regmap_set_bits(priv->phy, lane->phy_off + CTRL0, APB_RSTN_0);
+
+ if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEB)
+ regmap_set_bits(priv->misc, CTRL0, PCIE_AB_SELECT);
+ if (priv->hsio_cfg & IMX8Q_HSIO_CFG_SATA)
+ regmap_set_bits(priv->misc, CTRL0, PHYX1_EPCS_SEL);
+
+ imx8q_hsio_configure_clk_pad(phy);
+
+ if (lane->lane_mode == PHY_MODE_SATA) {
+ /*
+ * It is possible, for PCIe and SATA are sharing
+ * the same clock source, HPLL or external oscillator.
+ * When PCIe is in low power modes (L1.X or L2 etc),
+ * the clock source can be turned off. In this case,
+ * if this clock source is required to be toggling by
+ * SATA, then SATA functions will be abnormal.
+ * Set the override here to avoid it.
+ */
+ regmap_set_bits(priv->misc, CTRL0, CLKREQN_OUT_OVERRIDE);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + CTRL0, EPCS_TXDEEMP);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + CTRL0, EPCS_TXDEEMP_SEL);
+
+ imx8q_hsio_sata_phy_resets(phy);
+ } else {
+ /* Toggle apb_pclk to make sure clear the PM_REQ_CORE_RST bit */
+ clk_disable_unprepare(lane->clks[0].clk);
+ mdelay(1);
+ ret = clk_prepare_enable(lane->clks[0].clk);
+ if (ret) {
+ dev_err(priv->dev, "unable to enable phy apb_pclk\n");
+ return ret;
+ }
+
+ /* Bit19 PM_REQ_CORE_RST of pcie_stts0 should be cleared. */
+ ret = regmap_read_poll_timeout(priv->ctrl,
+ lane->ctrl_off + PCIE_STTS0,
+ val, (val & PM_REQ_CORE_RST) == 0,
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT);
+ if (ret) {
+ dev_err(priv->dev, "PM_REQ_CORE_RST is set\n");
+ return ret;
+ }
+ }
+
+ /* Polling to check the PHY is ready or not. */
+ if (lane->idx == 1)
+ cond = LANE1_TX_PLL_LOCK;
+ else
+ cond = LANE0_TX_PLL_LOCK;
+
+ ret = regmap_read_poll_timeout(priv->phy, lane->phy_off + PHY_STTS0,
+ val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX, PHY_INIT_WAIT_TIMEOUT);
+ if (ret)
+ dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", lane->idx);
+ else
+ dev_info(priv->dev, "IMX8Q PHY%d PLL is locked\n", lane->idx);
+
+ if (lane->lane_mode == PHY_MODE_SATA) {
+ cond = REG48_PMA_RDY;
+ ret = read_poll_timeout(readb, val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX, PHY_INIT_WAIT_TIMEOUT,
+ false, priv->base + REG48_PMA_STATUS);
+ if (ret)
+ dev_err(priv->dev, "PHY calibration is timeout\n");
+ else
+ dev_info(priv->dev, "PHY calibration is done\n");
+ }
+
+ return ret;
+}
+
+static int imx8q_hsio_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ u32 val;
+ struct imx8q_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx8q_hsio_priv *priv = lane->priv;
+
+ if (lane->lane_mode != mode)
+ return -EINVAL;
+
+ val = (mode == PHY_MODE_PCIE) ? MODE_PCIE : MODE_SATA;
+ val = FIELD_PREP(MODE_MASK, val);
+ regmap_update_bits(priv->phy, lane->phy_off + CTRL0, MODE_MASK, val);
+
+ switch (submode) {
+ case PHY_MODE_PCIE_RC:
+ val = FIELD_PREP(DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
+ break;
+ case PHY_MODE_PCIE_EP:
+ val = FIELD_PREP(DEVICE_TYPE_MASK, PCI_EXP_TYPE_ENDPOINT);
+ break;
+ default: /* Support only PCIe EP and RC now. */
+ return 0;
+ }
+ if (submode)
+ regmap_update_bits(priv->ctrl, lane->ctrl_off + CTRL0,
+ DEVICE_TYPE_MASK, val);
+
+ return 0;
+}
+
+static int imx8q_hsio_set_speed(struct phy *phy, int speed)
+{
+ struct imx8q_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx8q_hsio_priv *priv = lane->priv;
+
+ regmap_update_bits(priv->ctrl, lane->ctrl_off + CTRL2, LTSSM_ENABLE,
+ speed ? LTSSM_ENABLE : 0);
+ return 0;
+}
+
+static const struct phy_ops imx8q_hsio_ops = {
+ .init = imx8q_hsio_init,
+ .exit = imx8q_hsio_exit,
+ .power_on = imx8q_hsio_power_on,
+ .set_mode = imx8q_hsio_set_mode,
+ .set_speed = imx8q_hsio_set_speed,
+ .owner = THIS_MODULE,
+};
+
+static const struct imx8q_hsio_drvdata imx8qxp_serdes_drvdata = {
+ .num_lane = 1,
+};
+
+static const struct imx8q_hsio_drvdata imx8qm_serdes_drvdata = {
+ .num_lane = 3,
+};
+
+static const struct of_device_id imx8q_hsio_of_match[] = {
+ {.compatible = "fsl,imx8qxp-serdes", .data = &imx8qxp_serdes_drvdata},
+ {.compatible = "fsl,imx8qm-serdes", .data = &imx8qm_serdes_drvdata},
+ { },
+};
+
+MODULE_DEVICE_TABLE(of, imx8q_hsio_of_match);
+
+static struct phy *imx8q_hsio_xlate(struct device *dev,
+ const struct of_phandle_args *args)
+{
+ struct imx8q_hsio_priv *priv = dev_get_drvdata(dev);
+ int idx = args->args[0];
+ int ctrl_id = args->args[1];
+ int hsio_cfg = args->args[2];
+
+ if (idx >= priv->drvdata->num_lane)
+ return ERR_PTR(-EINVAL);
+ priv->lane[idx].idx = idx;
+ priv->lane[idx].ctrl_id = ctrl_id;
+ priv->hsio_cfg = hsio_cfg;
+
+ return priv->lane[idx].phy;
+}
+
+static int imx8q_hsio_probe(struct platform_device *pdev)
+{
+ int i;
+ void __iomem *off;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ const struct of_device_id *of_id;
+ struct imx8q_hsio_priv *priv;
+ struct phy_provider *provider;
+
+ of_id = of_match_device(imx8q_hsio_of_match, dev);
+ if (!of_id)
+ return -EINVAL;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ priv->dev = &pdev->dev;
+ priv->drvdata = of_device_get_match_data(dev);
+
+ /* Get PHY refclk pad mode */
+ of_property_read_u32(np, "fsl,refclk-pad-mode", &priv->refclk_pad_mode);
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ off = devm_platform_ioremap_resource_byname(pdev, "phy");
+ priv->phy = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->phy))
+ return dev_err_probe(dev, PTR_ERR(priv->phy),
+ "unable to find phy csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "ctrl");
+ priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->ctrl))
+ return dev_err_probe(dev, PTR_ERR(priv->ctrl),
+ "unable to find ctrl csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "misc");
+ priv->misc = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->misc))
+ return dev_err_probe(dev, PTR_ERR(priv->misc),
+ "unable to find misc csr registers\n");
+
+ for (i = 0; i < priv->drvdata->num_lane; i++) {
+ struct imx8q_hsio_lane *lane = &priv->lane[i];
+ struct phy *phy;
+
+ memset(lane, 0, sizeof(*lane));
+
+ phy = devm_phy_create(&pdev->dev, NULL, &imx8q_hsio_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ lane->priv = priv;
+ lane->phy = phy;
+ lane->idx = i;
+ phy_set_drvdata(phy, lane);
+ }
+
+ dev_set_drvdata(dev, priv);
+ dev_set_drvdata(&pdev->dev, priv);
+
+ provider = devm_of_phy_provider_register(&pdev->dev, imx8q_hsio_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver imx8q_hsio_driver = {
+ .probe = imx8q_hsio_probe,
+ .driver = {
+ .name = "imx8q-hsio-phy",
+ .of_match_table = imx8q_hsio_of_match,
+ }
+};
+module_platform_driver(imx8q_hsio_driver);
+
+MODULE_DESCRIPTION("FSL IMX8Q HSIO SERDES PHY driver");
+MODULE_LICENSE("GPL");
--
2.37.1
^ permalink raw reply related
* Re: [PATCH v7 09/15] media: bcm2835-unicam: Add support for CCP2/CSI2 camera interface
From: Laurent Pinchart @ 2024-04-02 6:05 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: linux-media, Dave Stevenson, David Plowman, Jean-Michel Hautbois,
Hans Verkuil, Naushir Patuck, Sakari Ailus, kernel-list,
linux-rpi-kernel, Florian Fainelli, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Conor Dooley, Krzysztof Kozlowski,
Rob Herring, devicetree
In-Reply-To: <cdcf9848-eee9-44a7-b033-315b1514740d@ideasonboard.com>
On Tue, Apr 02, 2024 at 09:00:43AM +0300, Tomi Valkeinen wrote:
> On 01/04/2024 16:52, Laurent Pinchart wrote:
> > On Wed, Mar 27, 2024 at 01:21:09PM +0200, Tomi Valkeinen wrote:
> >> On 25/03/2024 00:08, Laurent Pinchart wrote:
> >>> From: Dave Stevenson <dave.stevenson@raspberrypi.com>
> >>>
> >>> Add a driver for the Unicam camera receiver block on BCM283x processors.
> >>> It is represented as two video device nodes: unicam-image and
> >>> unicam-embedded which are connected to an internal subdev (named
> >>> unicam-subdev) in order to manage streams routing.
> >>
> >> Shouldn't this driver call get_frame_desc somewhere to get the VC and DT
> >> for the streams?
> >
> > Generally speaking, yes. In practice, configuring the DT from the frame
> > descriptor is probably not very useful, as CSI-2 sources that transmit
> > image data using a DT that doesn't correspond to the media bus code are
> > not very common and I don't expect this to be needed for unicam.
>
> Perhaps, but if the driver gets the DT from the frame descriptor, then
> the driver doesn't need to have tables for the DTs.
>
> Although when I did this with the RPi CFE driver, I also implemented a
> fallback mechanism for the cases when there is no get_frame_desc, and so
> I still had to keep the DT tables...
I did the same in v9. The DT value in the existing format info table
also serves for CCP2 support, which isn't supported by
.get_frame_desc(). Even if it was, CCP2 doesn't have an explicit DT
concept (as far as I can tell), but the hardware requires the DT value
to still be programmed.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH v3 1/9] dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks
From: Krzysztof Kozlowski @ 2024-04-02 6:20 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss
In-Reply-To: <20240401-typec-fix-sm8250-v3-1-604dce3ad103@linaro.org>
On 01/04/2024 22:33, Dmitry Baryshkov wrote:
> On the affected Qualcomm platforms the display clock controller has
> additional DP input clocks, describe them in DT schema.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../bindings/clock/qcom,dispcc-sm8x50.yaml | 28 ++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 1/1] dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk
From: Christophe ROULLIER @ 2024-04-02 6:23 UTC (permalink / raw)
To: Krzysztof Kozlowski, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maxime Coquelin, Alexandre Torgue, Richard Cochran,
Jose Abreu, Liam Girdwood, Mark Brown, Marek Vasut
Cc: netdev, devicetree, linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <46b065d1-82d7-4a15-9de2-1e0bdd2a9085@linaro.org>
On 3/30/24 19:40, Krzysztof Kozlowski wrote:
> On 28/03/2024 15:08, Christophe Roullier wrote:
>> The Linux kernel dwmac-stm32 driver currently supports three DT
>> properties used to configure whether PHY clock are generated by
>> the MAC or supplied to the MAC from the PHY.
>>
>> Originally there were two properties, st,eth-clk-sel and
>> st,eth-ref-clk-sel, each used to configure MAC clocking in
>> different bus mode and for different MAC clock frequency.
>> Since it is possible to determine the MAC 'eth-ck' clock
>> frequency from the clock subsystem and PHY bus mode from
>> the 'phy-mode' property, two disparate DT properties are
>> no longer required to configure MAC clocking.
>>
>> Linux kernel commit 1bb694e20839 ("net: ethernet: stmmac: simplify phy modes management for stm32")
>> introduced a third, unified, property st,ext-phyclk. This property
>> covers both use cases of st,eth-clk-sel and st,eth-ref-clk-sel DT
>> properties, as well as a new use case for 25 MHz clock generated
>> by the MAC.
>>
>> The third property st,ext-phyclk is so far undocumented,
>> document it.
>>
>> Below table summarizes the clock requirement and clock sources for
>> supported PHY interface modes.
>> __________________________________________________________________________
>> |PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125Mhz from PHY|
>> | | | 25MHz | 50MHz | |
>>
>> ---------------------------------------------------------------------------
>> | MII | - | eth-ck | n/a | n/a |
>> | | | st,ext-phyclk | | |
>>
>> ---------------------------------------------------------------------------
>> | GMII | - | eth-ck | n/a | n/a |
>> | | | st,ext-phyclk | | |
>>
>> ---------------------------------------------------------------------------
>> | RGMII | - | eth-ck | n/a | eth-ck |
>> | | | st,ext-phyclk | | st,eth-clk-sel or|
>> | | | | | st,ext-phyclk |
>>
>> ---------------------------------------------------------------------------
>> | RMII | - | eth-ck | eth-ck | n/a |
>> | | | st,ext-phyclk | st,eth-ref-clk-sel | |
>> | | | | or st,ext-phyclk | |
>>
>> ---------------------------------------------------------------------------
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
> Can you please start testing patches *before* sending them?
Yes sorry, when I removed patch with phy-supply property (1/2), I had
conflict merge and I did not pay attention that my commit was modified :-(
>
> Best regards,
> Krzysztof
>
^ permalink raw reply
* Re: [PATCH v6 0/1] Add property in dwmac-stm32 documentation
From: Christophe ROULLIER @ 2024-04-02 6:24 UTC (permalink / raw)
To: patchwork-bot+netdevbpf
Cc: davem, edumazet, kuba, pabeni, robh+dt, krzysztof.kozlowski+dt,
conor+dt, mcoquelin.stm32, alexandre.torgue, richardcochran,
joabreu, lgirdwood, broonie, marex, netdev, devicetree,
linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <171175263052.1693.263504657362042828.git-patchwork-notify@kernel.org>
On 3/29/24 23:50, patchwork-bot+netdevbpf@kernel.org wrote:
> Hello:
>
> This patch was applied to netdev/net-next.git (main)
> by Jakub Kicinski <kuba@kernel.org>:
Thanks
>
> On Thu, 28 Mar 2024 19:53:36 +0100 you wrote:
>> Introduce property in dwmac-stm32 documentation
>>
>> - st,ext-phyclk: is present since 2020 in driver so need to explain
>> it and avoid dtbs check issue : views/kernel/upstream/net-next/arch/arm/boot/dts/st/stm32mp157c-dk2.dtb:
>> ethernet@5800a000: Unevaluated properties are not allowed
>> ('st,ext-phyclk' was unexpected)
>> Furthermore this property will be use in upstream of MP13 dwmac glue. (next step)
>>
>> [...]
> Here is the summary with links:
> - [v6,1/1] dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk
> https://git.kernel.org/netdev/net-next/c/929107d3d2a3
>
> You are awesome, thank you!
^ permalink raw reply
* Re: [PATCH RFT 01/10] arm64: dts: microchip: sparx5: fix mdio reg
From: Horatiu Vultur @ 2024-04-02 6:26 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Conor Dooley, Nicolas Ferre, Claudiu Beznea, Rob Herring,
Krzysztof Kozlowski, Lars Povlsen, Steen Hegelund, Daniel Machon,
UNGLinuxDriver, David S. Miller, Bjarni Jonasson,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20240401153740.123978-1-krzk@kernel.org>
The 04/01/2024 17:37, Krzysztof Kozlowski wrote:
Hi,
I have not tested this patch on HW but I have checked the registers info
and this change seems correct.
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
> Correct the reg address of mdio node to match unit address. Assume the
> reg is not correct and unit address was correct, because there is
> alerady node using the existing reg 0x110102d4.
>
> sparx5.dtsi:443.25-451.5: Warning (simple_bus_reg): /axi@600000000/mdio@6110102f8: simple-bus unit address format error, expected "6110102d4"
>
> Fixes: d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node")
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> ---
>
> Not tested on hardware
> ---
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> index 24075cd91420..5d820da8c69d 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> @@ -447,7 +447,7 @@ mdio2: mdio@6110102f8 {
> pinctrl-names = "default";
> #address-cells = <1>;
> #size-cells = <0>;
> - reg = <0x6 0x110102d4 0x24>;
> + reg = <0x6 0x110102f8 0x24>;
> };
>
> mdio3: mdio@61101031c {
> --
> 2.34.1
>
--
/Horatiu
^ permalink raw reply
* Re: [PATCH v3] media: dt-bindings: ovti,ov2680: Document more properties
From: Krzysztof Kozlowski @ 2024-04-02 6:28 UTC (permalink / raw)
To: Fabio Estevam, sakari.ailus
Cc: rmfrfs, laurent.pinchart, hansg, robh, krzysztof.kozlowski+dt,
conor+dt, linux-media, devicetree, Fabio Estevam
In-Reply-To: <20240401190506.3238885-1-festevam@gmail.com>
On 01/04/2024 21:05, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
>
> OV2680 has a single data lane MIPI interface.
The hardware or the driver?
>
> Document the clock-lanes and data-lanes properties to avoid
> the following dt-schema warning:
>
> imx7s-warp.dtb: camera@36: port:endpoint: Unevaluated properties are not allowed ('clock-lanes', 'data-lanes' were unexpected)
> from schema $id: http://devicetree.org/schemas/media/i2c/ovti,ov2680.yaml#
You should mention why you cannot drop the redundant clock/data-lanes
from DTS.
>
> While at it, also document the link-frequencies property as recommended
> by the following document:
>
> https://www.kernel.org/doc/html/v6.9-rc1/driver-api/media/camera-sensor.html#handling-clocks
>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 1/4] dt-bindings: panel: Add LG SW43408 MIPI-DSI panel
From: Krzysztof Kozlowski @ 2024-04-02 6:31 UTC (permalink / raw)
To: Dmitry Baryshkov, Sumit Semwal, Caleb Connolly, Neil Armstrong,
Jessica Zhang, Sam Ravnborg, David Airlie, Daniel Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm, Vinod Koul,
Caleb Connolly
In-Reply-To: <20240402-lg-sw43408-panel-v3-1-144f17a11a56@linaro.org>
On 02/04/2024 01:51, Dmitry Baryshkov wrote:
> From: Sumit Semwal <sumit.semwal@linaro.org>
>
> LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel present on Google Pixel 3
> phones.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
> [caleb: convert to yaml]
> Signed-off-by: Caleb Connolly <caleb@connolly.tech>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Tags missing.
`b4 trailers -u`
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: ata: ahci-da850: Convert to dtschema
From: Krzysztof Kozlowski @ 2024-04-02 6:41 UTC (permalink / raw)
To: Damien Le Moal, Animesh Agarwal
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-ide,
devicetree, linux-kernel
In-Reply-To: <d5429736-8305-4afe-89a8-fe62907616e1@kernel.org>
On 02/04/2024 01:40, Damien Le Moal wrote:
> On 3/27/24 15:43, Animesh Agarwal wrote:
>> Convert the ahci-da850 bindings to DT schema.
>>
>> Signed-off-by: Animesh Agarwal <animeshagarwal28@gmail.com>
>
> Krzysztof, Rob,
>
> Are you OK with this patch ?
You got Conor's review, who is DT maintainer.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: ata: ahci-da850: Convert to dtschema
From: Damien Le Moal @ 2024-04-02 6:42 UTC (permalink / raw)
To: Krzysztof Kozlowski, Animesh Agarwal
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-ide,
devicetree, linux-kernel
In-Reply-To: <971be9ec-44a2-48cb-8d67-a4d4ce3b7d46@linaro.org>
On 4/2/24 15:41, Krzysztof Kozlowski wrote:
> On 02/04/2024 01:40, Damien Le Moal wrote:
>> On 3/27/24 15:43, Animesh Agarwal wrote:
>>> Convert the ahci-da850 bindings to DT schema.
>>>
>>> Signed-off-by: Animesh Agarwal <animeshagarwal28@gmail.com>
>>
>> Krzysztof, Rob,
>>
>> Are you OK with this patch ?
>
> You got Conor's review, who is DT maintainer.
I missed the fact that Conor is a maintainer. I should have checked :)
Thanks !
>
> Best regards,
> Krzysztof
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply
* Re: [PATCH v2 06/15] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for MT8186
From: Krzysztof Kozlowski @ 2024-04-02 6:44 UTC (permalink / raw)
To: Nicolas Pitre, Daniel Lezcano, linux-pm, linux-mediatek,
devicetree
Cc: Nicolas Pitre, AngeloGioacchino Del Regno
In-Reply-To: <20240402032729.2736685-7-nico@fluxnic.net>
On 02/04/2024 05:25, Nicolas Pitre wrote:
> From: Nicolas Pitre <npitre@baylibre.com>
>
> Add LVTS thermal controller definition for MT8186.
>
> Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH] arm64: dts: debix-a: Remove i2c2 from base .dts
From: Marco Felsch @ 2024-04-02 6:54 UTC (permalink / raw)
To: Laurent Pinchart
Cc: devicetree, imx, linux-arm-kernel, Rob Herring, Conor Dooley,
Krzysztof Kozlowski, Fabio Estevam, Sascha Hauer, Jacopo Mondi,
Pengutronix Kernel Team, Jacopo Mondi, Shawn Guo
In-Reply-To: <20240325225048.1159-1-laurent.pinchart@ideasonboard.com>
On 24-03-26, Laurent Pinchart wrote:
> From: Jacopo Mondi <jacopo@jmondi.org>
>
> The I2C2 bus is used for the CSI and DSI connectors only, no devices are
> connected to it on neither the Debix Model A nor its IO board. Remove
> the bus from the board's .dts and rely on display panel or camera sensor
> overlsy to enable it when necessary.
I would rather remove the status line instead of removing the whole node
since the bus is intented to be used for CSI and DSI and therefore the
muxing should be valid. This makes it easier for overlay authors since
they don't need to check the mux setup each time.
Regards,
Marco
>
> Signed-off-by: Jacopo Mondi <jacopo@jmondi.org>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> .../boot/dts/freescale/imx8mp-debix-model-a.dts | 14 --------------
> 1 file changed, 14 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> index 5ac77eaf23d5..26c303b7c7fa 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> @@ -210,13 +210,6 @@ ldo5: LDO5 {
> };
> };
>
> -&i2c2 {
> - clock-frequency = <100000>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_i2c2>;
> - status = "okay";
> -};
> -
> &i2c3 {
> clock-frequency = <400000>;
> pinctrl-names = "default";
> @@ -392,13 +385,6 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
> >;
> };
>
> - pinctrl_i2c2: i2c2grp {
> - fsl,pins = <
> - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
> - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
> - >;
> - };
> -
> pinctrl_i2c3: i2c3grp {
> fsl,pins = <
> MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
> --
> Regards,
>
> Laurent Pinchart
>
>
>
^ permalink raw reply
* Re: [PATCH v5 00/10] Improvments for tc358775 with support for tc358765
From: Michael Walle @ 2024-04-02 7:00 UTC (permalink / raw)
To: Tony Lindgren, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, David Airlie,
Daniel Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simha BN, Sam Ravnborg
Cc: Dmitry Baryshkov, Krzysztof Kozlowski, dri-devel, devicetree
In-Reply-To: <20240225062008.33191-1-tony@atomide.com>
[-- Attachment #1: Type: text/plain, Size: 315 bytes --]
Hi DRM maintainers,
On Sun Feb 25, 2024 at 7:19 AM CET, Tony Lindgren wrote:
> Here are v5 patches to improve tc358775 driver and add support for
> tc358765.
Any news on this series? Is there anything open or can it be merged?
FWIW, I have another tc358775 improvement series based on this.
-michael
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply
* [PATCH v2 00/13] ASoC: ti: davinci-i2s: Add features to McBSP driver
From: Bastien Curutchet @ 2024-04-02 7:12 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Ujfalusi, Jaroslav Kysela, Takashi Iwai,
Bastien Curutchet
Cc: linux-sound, devicetree, linux-kernel, alsa-devel,
Thomas Petazzoni, herve.codina, christophercordahi
This series aims to add some features to McBSP driver.
Convert bindings from .txt to .yaml.
Add possibility to use an external clock as sample rate generator's
input.
Add handling of new formats (TDM, S24_LE, BP_FC).
Enable the detection of unexpected frame pulses.
Set the clock free-running mode according to SND_SOC_DAIFMT_[GATED/CONT]
configuration in DAI format.
Add ti,T1-framing[tx/rx] properties in DT. They allow to set the data
delay to two bit-clock periods.
This has been tested on a platform designed off of the DAVINCI/OMAP-L138
connected to 3 daisy-chained AD7767. An external clock drives the
sample rate generator through the CLKS pin.
The hardware I have only allowed me to test acquisition side of McBSP.
It is connected to a 6 channels TDM and acts as Bit clock provider and
Frame clock consumer.
Change log v1 -> v2:
PATCH 1 (bindings):
* Drop power-domains property's description
* Drop the unused label 'mcbsp0' in example
* Add <> around each entry of the 'dmas' property
* Add 'Reviewed-by: Rob Herring <robh@kernel.org>'
PATCH 2 (bindings):
* Drop the 'ti,enable-sync-err' flag
* Drop the 'ti,disable-free-run' flag
* Add 'Reviewed-by: Rob Herring <robh@kernel.org>'
PATCH 4:
* In probe() use dev_err for fixed error
PATCH 7 (TDM):
* set playback.max_channels to 128
* Add a check on tx_mask as the one done for rx_mask
* Allow TDM with BP_FP format
PATCH 9:
* Detection of unexpected frame pulses is enabled by default
PATCH 10:
* Free-running mode is selected by the DAI format through
SND_SOC_DAIFMT_[CONT/GATED]
PATCH 12:
* drop the 'ti,drive-dx' property
* add 'ti,T1-framing-[rx/tx]' properties
PATCH 13:
* Drop the drive_dx part
* Add support for 'T1 framing' with data delay set to 2 bit-clock
periods
Bastien Curutchet (13):
ASoC: dt-bindings: davinci-mcbsp: convert McBSP bindings to yaml
schema
ASoC: dt-bindings: davinci-mcbsp: Add optional clock
ASoC: ti: davinci-i2s: Remove the unused clk_input_pin attribute
ASoC: ti: davinci-i2s: Replace dev_err with dev_err_probe
ASoC: ti: davinci-i2s: Use external clock to drive sample rate
generator
ASoC: ti: davinci-i2s: Delete unnecessary assignment
ASoC: ti: davinci-i2s: Add TDM support
ASoC: ti: davinci-i2s: Add handling of BP_FC format
ASoC: ti: davinci-i2s: Enable unexpected frame pulses detection
ASoC: ti: davinci-i2s: Link free-run mode to
SND_SOC_DAIFMT_[GATED/CONT]
ASoC: ti: davinci-i2s: Add S24_LE to supported formats
ASoC: dt-bindings: davinci-mcbsp: Add the 'ti,T1-framing-{rx/tx}'
flags
ASoC: ti: davinci-i2s: Add T1 framing support
.../bindings/sound/davinci-mcbsp.txt | 50 ----
.../bindings/sound/davinci-mcbsp.yaml | 113 +++++++
include/linux/platform_data/davinci_asp.h | 15 -
sound/soc/ti/davinci-i2s.c | 278 ++++++++++++++----
4 files changed, 333 insertions(+), 123 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/davinci-mcbsp.txt
create mode 100644 Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml
--
2.44.0
^ permalink raw reply
* [PATCH v2 01/13] ASoC: dt-bindings: davinci-mcbsp: convert McBSP bindings to yaml schema
From: Bastien Curutchet @ 2024-04-02 7:12 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Ujfalusi, Jaroslav Kysela, Takashi Iwai,
Bastien Curutchet
Cc: linux-sound, devicetree, linux-kernel, alsa-devel,
Thomas Petazzoni, herve.codina, christophercordahi
In-Reply-To: <20240402071213.11671-1-bastien.curutchet@bootlin.com>
Convert the binding for McBSP controllers for TI SoCs from txt
to YAML schema.
Add properties 'clocks', 'clock-names', 'power-domains' and
'#sound-dai-cells' which were missing from the txt file.
Add '#sound-dai-cells' and 'clocks' in the example which were missing
from the txt file.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/sound/davinci-mcbsp.txt | 50 ----------
.../bindings/sound/davinci-mcbsp.yaml | 95 +++++++++++++++++++
2 files changed, 95 insertions(+), 50 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/davinci-mcbsp.txt
create mode 100644 Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml
diff --git a/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt b/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt
deleted file mode 100644
index 3ffc2562fb31..000000000000
--- a/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-Texas Instruments DaVinci McBSP module
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-This binding describes the "Multi-channel Buffered Serial Port" (McBSP)
-audio interface found in some TI DaVinci processors like the OMAP-L138 or AM180x.
-
-
-Required properties:
-~~~~~~~~~~~~~~~~~~~~
-- compatible :
- "ti,da850-mcbsp" : for DA850, AM180x and OPAM-L138 platforms
-
-- reg : physical base address and length of the controller memory mapped
- region(s).
-- reg-names : Should contain:
- * "mpu" for the main registers (required).
- * "dat" for the data FIFO (optional).
-
-- dmas: three element list of DMA controller phandles, DMA request line and
- TC channel ordered triplets.
-- dma-names: identifier string for each DMA request line in the dmas property.
- These strings correspond 1:1 with the ordered pairs in dmas. The dma
- identifiers must be "rx" and "tx".
-
-Optional properties:
-~~~~~~~~~~~~~~~~~~~~
-- interrupts : Interrupt numbers for McBSP
-- interrupt-names : Known interrupt names are "rx" and "tx"
-
-- pinctrl-0: Should specify pin control group used for this controller.
-- pinctrl-names: Should contain only one value - "default", for more details
- please refer to pinctrl-bindings.txt
-
-Example (AM1808):
-~~~~~~~~~~~~~~~~~
-
-mcbsp0: mcbsp@1d10000 {
- compatible = "ti,da850-mcbsp";
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp0_pins>;
-
- reg = <0x00110000 0x1000>,
- <0x00310000 0x1000>;
- reg-names = "mpu", "dat";
- interrupts = <97 98>;
- interrupt-names = "rx", "tx";
- dmas = <&edma0 3 1
- &edma0 2 1>;
- dma-names = "tx", "rx";
-};
diff --git a/Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml b/Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml
new file mode 100644
index 000000000000..139b594dd192
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/davinci-mcbsp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: McBSP Controller for TI SoCs
+
+maintainers:
+ - Bastien Curutchet <bastien.curutchet@bootlin.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,da850-mcbsp
+
+ reg:
+ minItems: 1
+ items:
+ - description: CFG registers
+ - description: data registers
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: mpu
+ - const: dat
+
+ dmas:
+ items:
+ - description: transmission DMA channel
+ - description: reception DMA channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+ interrupts:
+ items:
+ - description: RX interrupt
+ - description: TX interrupt
+
+ interrupt-names:
+ items:
+ - const: rx
+ - const: tx
+
+ clocks:
+ items:
+ - description: functional clock
+
+ clock-names:
+ items:
+ - const: fck
+
+ power-domains:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - "#sound-dai-cells"
+ - compatible
+ - reg
+ - reg-names
+ - dmas
+ - dma-names
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mcbsp0@1d10000 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,da850-mcbsp";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp0_pins>;
+
+ reg = <0x111000 0x1000>,
+ <0x311000 0x1000>;
+ reg-names = "mpu", "dat";
+ interrupts = <97>, <98>;
+ interrupt-names = "rx", "tx";
+ dmas = <&edma0 3 1>,
+ <&edma0 2 1>;
+ dma-names = "tx", "rx";
+
+ clocks = <&psc1 14>;
+ };
--
2.44.0
^ permalink raw reply related
* [PATCH v2 02/13] ASoC: dt-bindings: davinci-mcbsp: Add optional clock
From: Bastien Curutchet @ 2024-04-02 7:12 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Ujfalusi, Jaroslav Kysela, Takashi Iwai,
Bastien Curutchet
Cc: linux-sound, devicetree, linux-kernel, alsa-devel,
Thomas Petazzoni, herve.codina, christophercordahi
In-Reply-To: <20240402071213.11671-1-bastien.curutchet@bootlin.com>
The McBSP uses an internal sample rate generator to provide bit clock
or frame clock. This sample rate generator can be programmed to be
driven by McBSP's internal clock source or by an external clock source
(located on CLKS pin). The external clock source is not described in
the bindings.
Add an optional clock item that allows to select an external clock as
sample rate generator's input.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml b/Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml
index 139b594dd192..0c2b1936c6a1 100644
--- a/Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml
+++ b/Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml
@@ -50,12 +50,16 @@ properties:
- const: tx
clocks:
+ minItems: 1
items:
- description: functional clock
+ - description: external input clock for sample rate generator.
clock-names:
+ minItems: 1
items:
- const: fck
+ - const: clks
power-domains:
maxItems: 1
--
2.44.0
^ permalink raw reply related
* [PATCH v2 03/13] ASoC: ti: davinci-i2s: Remove the unused clk_input_pin attribute
From: Bastien Curutchet @ 2024-04-02 7:12 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Ujfalusi, Jaroslav Kysela, Takashi Iwai,
Bastien Curutchet
Cc: linux-sound, devicetree, linux-kernel, alsa-devel,
Thomas Petazzoni, herve.codina, christophercordahi
In-Reply-To: <20240402071213.11671-1-bastien.curutchet@bootlin.com>
The clk_input_pin attribute of davinci_mcbsp_dev struct is not set since
commit 257ade78b601 ("ASoC: davinci-i2s: Convert to use edma-pcm").
Remove the attribute.
Keep the behaviour of the MCBSP_CLKR case as MCBSP_CLKR == 0.
I can't test the BC_FP format so I added back the initial comment that
was removed by commit ec6375533748 ("ASoC: DaVinci: Added selection of
clk input pin for McBSP"). This was the last dependency to
linux/platform_data/davinci_asp.h so it is not included anymore.
Remove the enum mcbsp_clk_input_pin from davinci_asp.h as it is not used
anywhere else.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
---
include/linux/platform_data/davinci_asp.h | 15 --------------
sound/soc/ti/davinci-i2s.c | 24 ++++-------------------
2 files changed, 4 insertions(+), 35 deletions(-)
diff --git a/include/linux/platform_data/davinci_asp.h b/include/linux/platform_data/davinci_asp.h
index c8645b2ed3c0..b9c8520b4bd3 100644
--- a/include/linux/platform_data/davinci_asp.h
+++ b/include/linux/platform_data/davinci_asp.h
@@ -25,16 +25,6 @@ struct davinci_mcasp_pdata {
unsigned sram_size_capture;
struct gen_pool *sram_pool;
- /*
- * If McBSP peripheral gets the clock from an external pin,
- * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
- * and MCBSP_CLKS.
- * Depending on different hardware connections it is possible
- * to use this setting to change the behaviour of McBSP
- * driver.
- */
- int clk_input_pin;
-
/*
* This flag works when both clock and FS are outputs for the cpu
* and makes clock more accurate (FS is not symmetrical and the
@@ -91,11 +81,6 @@ enum {
MCASP_VERSION_OMAP, /* OMAP4/5 */
};
-enum mcbsp_clk_input_pin {
- MCBSP_CLKR = 0, /* as in DM365 */
- MCBSP_CLKS,
-};
-
#define INACTIVE_MODE 0
#define TX_MODE 1
#define RX_MODE 2
diff --git a/sound/soc/ti/davinci-i2s.c b/sound/soc/ti/davinci-i2s.c
index 07c8b2259208..5c906641640e 100644
--- a/sound/soc/ti/davinci-i2s.c
+++ b/sound/soc/ti/davinci-i2s.c
@@ -19,7 +19,6 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
-#include <linux/platform_data/davinci_asp.h>
#include <sound/core.h>
#include <sound/pcm.h>
@@ -159,7 +158,6 @@ struct davinci_mcbsp_dev {
unsigned int fmt;
int clk_div;
- int clk_input_pin;
bool i2s_accurate_sck;
};
@@ -239,26 +237,12 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
DAVINCI_MCBSP_PCR_CLKRM;
break;
case SND_SOC_DAIFMT_BC_FP:
- pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
/*
- * Selection of the clock input pin that is the
- * input for the Sample Rate Generator.
- * McBSP FSR and FSX are driven by the Sample Rate
- * Generator.
+ * McBSP CLKR pin is the input for the Sample Rate Generator.
+ * McBSP FSR and FSX are driven by the Sample Rate Generator.
*/
- switch (dev->clk_input_pin) {
- case MCBSP_CLKS:
- pcr |= DAVINCI_MCBSP_PCR_CLKXM |
- DAVINCI_MCBSP_PCR_CLKRM;
- break;
- case MCBSP_CLKR:
- pcr |= DAVINCI_MCBSP_PCR_SCLKME;
- break;
- default:
- dev_err(dev->dev, "bad clk_input_pin\n");
- return -EINVAL;
- }
-
+ pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
+ pcr |= DAVINCI_MCBSP_PCR_SCLKME;
break;
case SND_SOC_DAIFMT_BC_FC:
/* codec is master */
--
2.44.0
^ permalink raw reply related
* [PATCH v2 04/13] ASoC: ti: davinci-i2s: Replace dev_err with dev_err_probe
From: Bastien Curutchet @ 2024-04-02 7:12 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Ujfalusi, Jaroslav Kysela, Takashi Iwai,
Bastien Curutchet
Cc: linux-sound, devicetree, linux-kernel, alsa-devel,
Thomas Petazzoni, herve.codina, christophercordahi
In-Reply-To: <20240402071213.11671-1-bastien.curutchet@bootlin.com>
In probe(), the dev_err() is used for every returned error.
Replace dev_err() with dev_err_probe() where -EPROBE_DEFER can be
returned.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
---
sound/soc/ti/davinci-i2s.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/ti/davinci-i2s.c b/sound/soc/ti/davinci-i2s.c
index 5c906641640e..cd64f1384e18 100644
--- a/sound/soc/ti/davinci-i2s.c
+++ b/sound/soc/ti/davinci-i2s.c
@@ -708,7 +708,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
ret = edma_pcm_platform_register(&pdev->dev);
if (ret) {
- dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
+ dev_err_probe(&pdev->dev, ret, "register PCM failed\n");
goto err_unregister_component;
}
--
2.44.0
^ permalink raw reply related
* [PATCH v2 05/13] ASoC: ti: davinci-i2s: Use external clock to drive sample rate generator
From: Bastien Curutchet @ 2024-04-02 7:12 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Ujfalusi, Jaroslav Kysela, Takashi Iwai,
Bastien Curutchet
Cc: linux-sound, devicetree, linux-kernel, alsa-devel,
Thomas Petazzoni, herve.codina, christophercordahi
In-Reply-To: <20240402071213.11671-1-bastien.curutchet@bootlin.com>
McBSP's internal sample rate generator can be programed to be driven by
its internal clock or by an external clock source located on CLKS pin.
The external clock source case is not handled by the driver.
Handle an optional clock related to this external clock source. If
present, the driver uses the clock located on CLKS pin as input for the
sample rate generator. Thus, the external clock rate is used to compute
divisors. If this optional clock is not present, the sample rate
generator is driven by the McBSP's functional clock.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
---
sound/soc/ti/davinci-i2s.c | 65 ++++++++++++++++++++++++++++----------
1 file changed, 49 insertions(+), 16 deletions(-)
diff --git a/sound/soc/ti/davinci-i2s.c b/sound/soc/ti/davinci-i2s.c
index cd64f1384e18..578b4ae28b71 100644
--- a/sound/soc/ti/davinci-i2s.c
+++ b/sound/soc/ti/davinci-i2s.c
@@ -134,6 +134,7 @@ struct davinci_mcbsp_dev {
int mode;
u32 pcr;
struct clk *clk;
+ struct clk *ext_clk;
/*
* Combining both channels into 1 element will at least double the
* amount of time between servicing the dma channel, increase
@@ -364,7 +365,8 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
struct snd_interval *i = NULL;
int mcbsp_word_length, master;
- unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
+ unsigned int rcr, xcr, clk_div, freq, framesize;
+ unsigned int srgr = 0;
u32 spcr;
snd_pcm_format_t fmt;
unsigned element_cnt = 1;
@@ -385,9 +387,13 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
switch (master) {
case SND_SOC_DAIFMT_BP_FP:
- freq = clk_get_rate(dev->clk);
- srgr = DAVINCI_MCBSP_SRGR_FSGM |
- DAVINCI_MCBSP_SRGR_CLKSM;
+ if (dev->ext_clk) {
+ freq = clk_get_rate(dev->ext_clk);
+ } else {
+ freq = clk_get_rate(dev->clk);
+ srgr = DAVINCI_MCBSP_SRGR_CLKSM;
+ }
+ srgr |= DAVINCI_MCBSP_SRGR_FSGM;
srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
8 - 1);
if (dev->i2s_accurate_sck) {
@@ -691,12 +697,36 @@ static int davinci_i2s_probe(struct platform_device *pdev)
return -ENODEV;
}
- dev->clk = clk_get(&pdev->dev, NULL);
+ /*
+ * The optional is there for backward compatibility.
+ * If 'fck' is not present, the clk_get(dev, NULL) that follows may find something
+ */
+ dev->clk = devm_clk_get_optional(&pdev->dev, "fck");
if (IS_ERR(dev->clk))
- return -ENODEV;
- ret = clk_enable(dev->clk);
+ return dev_err_probe(&pdev->dev, PTR_ERR(dev->clk), "Invalid functional clock\n");
+ if (!dev->clk) {
+ dev->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(dev->clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(dev->clk),
+ "Missing functional clock\n");
+ }
+
+ dev->ext_clk = devm_clk_get_optional(&pdev->dev, "clks");
+ if (IS_ERR(dev->ext_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(dev->ext_clk), "Invalid external clock\n");
+
+ ret = clk_prepare_enable(dev->clk);
if (ret)
- goto err_put_clk;
+ return ret;
+
+ if (dev->ext_clk) {
+ dev_dbg(&pdev->dev, "External clock used for sample rate generator\n");
+ ret = clk_prepare_enable(dev->ext_clk);
+ if (ret) {
+ dev_err_probe(&pdev->dev, ret, "Failed to enable external clock\n");
+ goto err_disable_clk;
+ }
+ }
dev->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, dev);
@@ -704,7 +734,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
ret = snd_soc_register_component(&pdev->dev, &davinci_i2s_component,
&davinci_i2s_dai, 1);
if (ret != 0)
- goto err_release_clk;
+ goto err_disable_ext_clk;
ret = edma_pcm_platform_register(&pdev->dev);
if (ret) {
@@ -716,10 +746,12 @@ static int davinci_i2s_probe(struct platform_device *pdev)
err_unregister_component:
snd_soc_unregister_component(&pdev->dev);
-err_release_clk:
- clk_disable(dev->clk);
-err_put_clk:
- clk_put(dev->clk);
+err_disable_ext_clk:
+ if (dev->ext_clk)
+ clk_disable_unprepare(dev->ext_clk);
+err_disable_clk:
+ clk_disable_unprepare(dev->clk);
+
return ret;
}
@@ -729,9 +761,10 @@ static void davinci_i2s_remove(struct platform_device *pdev)
snd_soc_unregister_component(&pdev->dev);
- clk_disable(dev->clk);
- clk_put(dev->clk);
- dev->clk = NULL;
+ clk_disable_unprepare(dev->clk);
+
+ if (dev->ext_clk)
+ clk_disable_unprepare(dev->ext_clk);
}
static const struct of_device_id davinci_i2s_match[] __maybe_unused = {
--
2.44.0
^ permalink raw reply related
* [PATCH v2 06/13] ASoC: ti: davinci-i2s: Delete unnecessary assignment
From: Bastien Curutchet @ 2024-04-02 7:12 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Ujfalusi, Jaroslav Kysela, Takashi Iwai,
Bastien Curutchet
Cc: linux-sound, devicetree, linux-kernel, alsa-devel,
Thomas Petazzoni, herve.codina, christophercordahi
In-Reply-To: <20240402071213.11671-1-bastien.curutchet@bootlin.com>
In davinci_i2s_hw_params(), mcbsp_word_length is set twice to
asp_word_length[fmt].
Remove second unnecessary assignment.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
---
sound/soc/ti/davinci-i2s.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/sound/soc/ti/davinci-i2s.c b/sound/soc/ti/davinci-i2s.c
index 578b4ae28b71..a2c7c812ea50 100644
--- a/sound/soc/ti/davinci-i2s.c
+++ b/sound/soc/ti/davinci-i2s.c
@@ -479,7 +479,6 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
return -EINVAL;
}
}
- mcbsp_word_length = asp_word_length[fmt];
switch (master) {
case SND_SOC_DAIFMT_BP_FP:
--
2.44.0
^ permalink raw reply related
* [PATCH v2 07/13] ASoC: ti: davinci-i2s: Add TDM support
From: Bastien Curutchet @ 2024-04-02 7:12 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peter Ujfalusi, Jaroslav Kysela, Takashi Iwai,
Bastien Curutchet
Cc: linux-sound, devicetree, linux-kernel, alsa-devel,
Thomas Petazzoni, herve.codina, christophercordahi
In-Reply-To: <20240402071213.11671-1-bastien.curutchet@bootlin.com>
TDM is not supported by the McBSP driver. The McBSP datasheet does not
name explicitly TDM as a supported format but it is possible to configure
the McBSP to do TDM if all slots are used by McBSP.
Add TDM support. It uses single-phase frame. Slot width is used to
compute the McBSP's word length.
Implement the set_tdm_slot() hook of snd_soc_dai_ops struct. It only
supports TDM if all slots are used by McBSP.
The snd_soc_dai_driver's channels_max is updated from 2 to 128.
This was tested with BP_FC format on a platform designed off of
DAVINCI/OMAP_L138. A check is done in davinci_i2s_set_dai_fmt() to
prevent TDM to be used with BC_FC and BC_FP formats.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
---
sound/soc/ti/davinci-i2s.c | 92 +++++++++++++++++++++++++++++++++++---
1 file changed, 87 insertions(+), 5 deletions(-)
diff --git a/sound/soc/ti/davinci-i2s.c b/sound/soc/ti/davinci-i2s.c
index a2c7c812ea50..f9a67c2bc2f5 100644
--- a/sound/soc/ti/davinci-i2s.c
+++ b/sound/soc/ti/davinci-i2s.c
@@ -160,6 +160,9 @@ struct davinci_mcbsp_dev {
unsigned int fmt;
int clk_div;
bool i2s_accurate_sck;
+
+ int tdm_slots;
+ int slot_width;
};
static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -213,6 +216,63 @@ static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
toggle_clock(dev, playback);
}
+static int davinci_i2s_tdm_word_length(int tdm_slot_width)
+{
+ switch (tdm_slot_width) {
+ case 8:
+ return DAVINCI_MCBSP_WORD_8;
+ case 12:
+ return DAVINCI_MCBSP_WORD_12;
+ case 16:
+ return DAVINCI_MCBSP_WORD_16;
+ case 20:
+ return DAVINCI_MCBSP_WORD_20;
+ case 24:
+ return DAVINCI_MCBSP_WORD_24;
+ case 32:
+ return DAVINCI_MCBSP_WORD_32;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int davinci_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,
+ unsigned int tx_mask,
+ unsigned int rx_mask,
+ int slots, int slot_width)
+{
+ struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
+
+ dev_dbg(dev->dev, "slots %d, slot_width %d\n", slots, slot_width);
+
+ if (slots > 128 || !slots) {
+ dev_err(dev->dev, "Invalid number of slots\n");
+ return -EINVAL;
+ }
+
+ if (rx_mask != (1 << slots) - 1) {
+ dev_err(dev->dev, "Invalid RX mask (0x%08x) : all slots must be used by McBSP\n",
+ rx_mask);
+ return -EINVAL;
+ }
+
+ if (tx_mask != (1 << slots) - 1) {
+ dev_err(dev->dev, "Invalid TX mask (0x%08x) : all slots must be used by McBSP\n",
+ tx_mask);
+ return -EINVAL;
+ }
+
+ if (davinci_i2s_tdm_word_length(slot_width) < 0) {
+ dev_err(dev->dev, "%s: Unsupported slot_width %d\n", __func__, slot_width);
+ return -EINVAL;
+ }
+
+ dev->tdm_slots = slots;
+ dev->slot_width = slot_width;
+
+ return 0;
+}
+
#define DEFAULT_BITPERSAMPLE 16
static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
@@ -238,6 +298,11 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
DAVINCI_MCBSP_PCR_CLKRM;
break;
case SND_SOC_DAIFMT_BC_FP:
+ if (dev->tdm_slots || dev->slot_width) {
+ dev_err(dev->dev, "TDM is not supported for BC_FP format\n");
+ return -EINVAL;
+ }
+
/*
* McBSP CLKR pin is the input for the Sample Rate Generator.
* McBSP FSR and FSX are driven by the Sample Rate Generator.
@@ -246,6 +311,11 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
pcr |= DAVINCI_MCBSP_PCR_SCLKME;
break;
case SND_SOC_DAIFMT_BC_FC:
+ if (dev->tdm_slots || dev->slot_width) {
+ dev_err(dev->dev, "TDM is not supported for BC_FC format\n");
+ return -EINVAL;
+ }
+
/* codec is master */
pcr = 0;
break;
@@ -383,7 +453,13 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
master = dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
fmt = params_format(params);
- mcbsp_word_length = asp_word_length[fmt];
+ if (dev->slot_width)
+ mcbsp_word_length = davinci_i2s_tdm_word_length(dev->slot_width);
+ else
+ mcbsp_word_length = asp_word_length[fmt];
+
+ if (mcbsp_word_length < 0)
+ return mcbsp_word_length;
switch (master) {
case SND_SOC_DAIFMT_BP_FP:
@@ -483,8 +559,13 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
switch (master) {
case SND_SOC_DAIFMT_BP_FP:
case SND_SOC_DAIFMT_BP_FC:
- rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
- xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
+ if (dev->tdm_slots > 0) {
+ rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(dev->tdm_slots - 1);
+ xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(dev->tdm_slots - 1);
+ } else {
+ rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
+ xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
+ }
break;
case SND_SOC_DAIFMT_BC_FC:
case SND_SOC_DAIFMT_BC_FP:
@@ -609,19 +690,20 @@ static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
.hw_params = davinci_i2s_hw_params,
.set_fmt = davinci_i2s_set_dai_fmt,
.set_clkdiv = davinci_i2s_dai_set_clkdiv,
+ .set_tdm_slot = davinci_i2s_set_tdm_slot,
};
static struct snd_soc_dai_driver davinci_i2s_dai = {
.playback = {
.channels_min = 2,
- .channels_max = 2,
+ .channels_max = 128,
.rates = DAVINCI_I2S_RATES,
.formats = DAVINCI_I2S_FORMATS,
},
.capture = {
.channels_min = 2,
- .channels_max = 2,
+ .channels_max = 128,
.rates = DAVINCI_I2S_RATES,
.formats = DAVINCI_I2S_FORMATS,
},
--
2.44.0
^ permalink raw reply related
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