* Re: [PATCH v4 2/2] media: i2c: Add imx283 camera sensor driver
From: Umang Jain @ 2024-04-02 12:57 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Conor Dooley, Shawn Guo,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Sakari Ailus
Cc: Kieran Bingham, Rob Herring, Krzysztof Kozlowski, Sascha Hauer,
Andy Shevchenko, linux-media, devicetree, linux-arm-kernel,
linux-kernel, Laurent Pinchart
In-Reply-To: <20240402-kernel-name-extraversion-v4-2-fb776893e4ec@ideasonboard.com>
Hi,
CC'ing Laurent Pinchart as his email seems to get missed by b4
auto-to-cc (still learning grips with this tool) ..
On 02/04/24 3:37 pm, Umang Jain wrote:
> From: Kieran Bingham <kieran.bingham@ideasonboard.com>
>
> Add a v4l2 subdevice driver for the Sony IMX283 image sensor.
>
> The IMX283 is a 20MP Diagonal 15.86 mm (Type 1) CMOS Image Sensor with
> Square Pixel for Color Cameras.
>
> The following features are supported:
> - Manual exposure an gain control support
> - vblank/hblank/link freq control support
> - Test pattern support control
> - Arbitrary horizontal and vertical cropping
> - Supported resolution:
> - 5472x3648 @ 20fps (SRGGB12)
> - 5472x3648 @ 25fps (SRGGB10)
> - 2736x1824 @ 50fps (SRGGB12)
>
> Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
> Signed-off-by: Umang Jain <umang.jain@ideasonboard.com>
> ---
> MAINTAINERS | 1 +
> drivers/media/i2c/Kconfig | 10 +
> drivers/media/i2c/Makefile | 1 +
> drivers/media/i2c/imx283.c | 1605 ++++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 1617 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a2e164131650..64d3780afb99 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20374,6 +20374,7 @@ L: linux-media@vger.kernel.org
> S: Maintained
> T: git git://linuxtv.org/media_tree.git
> F: Documentation/devicetree/bindings/media/i2c/sony,imx283.yaml
> +F: drivers/media/i2c/imx283.c
>
> SONY IMX290 SENSOR DRIVER
> M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
> index e4da68835683..b84d64d37f0e 100644
> --- a/drivers/media/i2c/Kconfig
> +++ b/drivers/media/i2c/Kconfig
> @@ -163,6 +163,16 @@ config VIDEO_IMX274
> This is a V4L2 sensor driver for the Sony IMX274
> CMOS image sensor.
>
> +config VIDEO_IMX283
> + tristate "Sony IMX283 sensor support"
> + select V4L2_CCI_I2C
> + help
> + This is a V4L2 sensor driver for the Sony IMX283
> + CMOS image sensor.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called imx283.
> +
> config VIDEO_IMX290
> tristate "Sony IMX290 sensor support"
> select REGMAP_I2C
> diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
> index b82e99ca7578..bbe41e831c76 100644
> --- a/drivers/media/i2c/Makefile
> +++ b/drivers/media/i2c/Makefile
> @@ -49,6 +49,7 @@ obj-$(CONFIG_VIDEO_IMX214) += imx214.o
> obj-$(CONFIG_VIDEO_IMX219) += imx219.o
> obj-$(CONFIG_VIDEO_IMX258) += imx258.o
> obj-$(CONFIG_VIDEO_IMX274) += imx274.o
> +obj-$(CONFIG_VIDEO_IMX283) += imx283.o
> obj-$(CONFIG_VIDEO_IMX290) += imx290.o
> obj-$(CONFIG_VIDEO_IMX296) += imx296.o
> obj-$(CONFIG_VIDEO_IMX319) += imx319.o
> diff --git a/drivers/media/i2c/imx283.c b/drivers/media/i2c/imx283.c
> new file mode 100644
> index 000000000000..ace8f65aa6b3
> --- /dev/null
> +++ b/drivers/media/i2c/imx283.c
> @@ -0,0 +1,1605 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * V4L2 Support for the IMX283
> + *
> + * Diagonal 15.86 mm (Type 1) CMOS Image Sensor with Square Pixel for Color
> + * Cameras.
> + *
> + * Copyright (C) 2024 Ideas on Board Oy.
> + *
> + * Based on Sony IMX283 driver prepared by Will Whang
> + *
> + * Based on Sony imx477 camera driver
> + * Copyright (C) 2019-2020 Raspberry Pi (Trading) Ltd
> + */
> +
> +#include <linux/array_size.h>
> +#include <linux/bitops.h>
> +#include <linux/container_of.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/i2c.h>
> +#include <linux/minmax.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/property.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/types.h>
> +#include <linux/units.h>
> +#include <media/v4l2-cci.h>
> +#include <media/v4l2-ctrls.h>
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-event.h>
> +#include <media/v4l2-fwnode.h>
> +#include <media/v4l2-mediabus.h>
> +
> +/* Chip ID */
> +#define IMX283_REG_CHIP_ID CCI_REG8(0x3000)
> +#define IMX283_CHIP_ID 0x0b // Default power on state
> +
> +#define IMX283_REG_STANDBY CCI_REG8(0x3000)
> +#define IMX283_ACTIVE 0
> +#define IMX283_STANDBY BIT(0)
> +#define IMX283_STBLOGIC BIT(1)
> +#define IMX283_STBMIPI BIT(2)
> +#define IMX283_STBDV BIT(3)
> +#define IMX283_SLEEP BIT(4)
> +
> +#define IMX283_REG_CLAMP CCI_REG8(0x3001)
> +#define IMX283_CLPSQRST BIT(4)
> +
> +#define IMX283_REG_PLSTMG08 CCI_REG8(0x3003)
> +#define IMX283_PLSTMG08_VAL 0x77
> +
> +#define IMX283_REG_MDSEL1 CCI_REG8(0x3004)
> +#define IMX283_REG_MDSEL2 CCI_REG8(0x3005)
> +#define IMX283_REG_MDSEL3 CCI_REG8(0x3006)
> +#define IMX283_MDSEL3_VCROP_EN BIT(5)
> +#define IMX283_REG_MDSEL4 CCI_REG8(0x3007)
> +#define IMX283_MDSEL4_VCROP_EN (BIT(4) | BIT(6))
> +
> +#define IMX283_REG_SVR CCI_REG16_LE(0x3009)
> +
> +#define IMX283_REG_HTRIMMING CCI_REG8(0x300b)
> +#define IMX283_MDVREV BIT(0) /* VFLIP */
> +#define IMX283_HTRIMMING_EN BIT(4)
> +
> +#define IMX283_REG_VWINPOS CCI_REG16_LE(0x300f)
> +#define IMX283_REG_VWIDCUT CCI_REG16_LE(0x3011)
> +
> +#define IMX283_REG_MDSEL7 CCI_REG16_LE(0x3013)
> +
> +/* CSI Clock Configuration */
> +#define IMX283_REG_TCLKPOST CCI_REG8(0x3018)
> +#define IMX283_REG_THSPREPARE CCI_REG8(0x301a)
> +#define IMX283_REG_THSZERO CCI_REG8(0x301c)
> +#define IMX283_REG_THSTRAIL CCI_REG8(0x301e)
> +#define IMX283_REG_TCLKTRAIL CCI_REG8(0x3020)
> +#define IMX283_REG_TCLKPREPARE CCI_REG8(0x3022)
> +#define IMX283_REG_TCLKZERO CCI_REG16_LE(0x3024)
> +#define IMX283_REG_TLPX CCI_REG8(0x3026)
> +#define IMX283_REG_THSEXIT CCI_REG8(0x3028)
> +#define IMX283_REG_TCLKPRE CCI_REG8(0x302a)
> +#define IMX283_REG_SYSMODE CCI_REG8(0x3104)
> +
> +#define IMX283_REG_Y_OUT_SIZE CCI_REG16_LE(0x302f)
> +#define IMX283_REG_WRITE_VSIZE CCI_REG16_LE(0x3031)
> +#define IMX283_REG_OB_SIZE_V CCI_REG8(0x3033)
> +
> +/* HMAX internal HBLANK */
> +#define IMX283_REG_HMAX CCI_REG16_LE(0x3036)
> +#define IMX283_HMAX_MAX (BIT(16) - 1)
> +
> +/* VMAX internal VBLANK */
> +#define IMX283_REG_VMAX CCI_REG24_LE(0x3038)
> +#define IMX283_VMAX_MAX (BIT(16) - 1)
> +
> +/* SHR internal */
> +#define IMX283_REG_SHR CCI_REG16_LE(0x303b)
> +#define IMX283_SHR_MIN 11
> +
> +/*
> + * Analog gain control
> + * Gain [dB] = -20log{(2048 - value [10:0]) /2048}
> + * Range: 0dB to approximately +27dB
> + */
> +#define IMX283_REG_ANALOG_GAIN CCI_REG16_LE(0x3042)
> +#define IMX283_ANA_GAIN_MIN 0
> +#define IMX283_ANA_GAIN_MAX 1957
> +#define IMX283_ANA_GAIN_STEP 1
> +#define IMX283_ANA_GAIN_DEFAULT 0x0
> +
> +/*
> + * Digital gain control
> + * Gain [dB] = value * 6
> + * Range: 0dB to +18db
> + */
> +#define IMX283_REG_DIGITAL_GAIN CCI_REG8(0x3044)
> +#define IMX283_DGTL_GAIN_MIN 0
> +#define IMX283_DGTL_GAIN_MAX 3
> +#define IMX283_DGTL_GAIN_DEFAULT 0
> +#define IMX283_DGTL_GAIN_STEP 1
> +
> +#define IMX283_REG_HTRIMMING_START CCI_REG16_LE(0x3058)
> +#define IMX283_REG_HTRIMMING_END CCI_REG16_LE(0x305a)
> +
> +#define IMX283_REG_MDSEL18 CCI_REG16_LE(0x30f6)
> +
> +/* Master Mode Operation Control */
> +#define IMX283_REG_XMSTA CCI_REG8(0x3105)
> +#define IMX283_XMSTA BIT(0)
> +
> +#define IMX283_REG_SYNCDRV CCI_REG8(0x3107)
> +#define IMX283_SYNCDRV_XHS_XVS (0xa0 | 0x02)
> +#define IMX283_SYNCDRV_HIZ (0xa0 | 0x03)
> +
> +/* PLL Standby */
> +#define IMX283_REG_STBPL CCI_REG8(0x320b)
> +#define IMX283_STBPL_NORMAL 0x00
> +#define IMX283_STBPL_STANDBY 0x03
> +
> +/* Input Frequency Setting */
> +#define IMX283_REG_PLRD1 CCI_REG8(0x36c1)
> +#define IMX283_REG_PLRD2 CCI_REG16_LE(0x36c2)
> +#define IMX283_REG_PLRD3 CCI_REG8(0x36f7)
> +#define IMX283_REG_PLRD4 CCI_REG8(0x36f8)
> +
> +#define IMX283_REG_PLSTMG02 CCI_REG8(0x36aa)
> +#define IMX283_PLSTMG02_VAL 0x00
> +
> +#define IMX283_REG_EBD_X_OUT_SIZE CCI_REG16_LE(0x3a54)
> +
> +/* Test pattern generator */
> +#define IMX283_REG_TPG_CTRL CCI_REG8(0x3156)
> +#define IMX283_TPG_CTRL_CLKEN BIT(0)
> +#define IMX283_TPG_CTRL_PATEN BIT(4)
> +
> +#define IMX283_REG_TPG_PAT CCI_REG8(0x3157)
> +#define IMX283_TPG_PAT_ALL_000 0x00
> +#define IMX283_TPG_PAT_ALL_FFF 0x01
> +#define IMX283_TPG_PAT_ALL_555 0x02
> +#define IMX283_TPG_PAT_ALL_AAA 0x03
> +#define IMX283_TPG_PAT_H_COLOR_BARS 0x0a
> +#define IMX283_TPG_PAT_V_COLOR_BARS 0x0b
> +
> +/* Exposure control */
> +#define IMX283_EXPOSURE_MIN 52
> +#define IMX283_EXPOSURE_STEP 1
> +#define IMX283_EXPOSURE_DEFAULT 1000
> +#define IMX283_EXPOSURE_MAX 49865
> +
> +#define IMAGE_PAD 0
> +
> +#define IMX283_XCLR_MIN_DELAY_US (1 * USEC_PER_MSEC)
> +#define IMX283_XCLR_DELAY_RANGE_US (1 * USEC_PER_MSEC)
> +
> +/* IMX283 native and active pixel array size. */
> +static const struct v4l2_rect imx283_native_area = {
> + .top = 0,
> + .left = 0,
> + .width = 5592,
> + .height = 3710,
> +};
> +
> +static const struct v4l2_rect imx283_active_area = {
> + .top = 40,
> + .left = 108,
> + .width = 5472,
> + .height = 3648,
> +};
> +
> +struct imx283_reg_list {
> + unsigned int num_of_regs;
> + const struct cci_reg_sequence *regs;
> +};
> +
> +/* Mode : resolution and related config values */
> +struct imx283_mode {
> + unsigned int mode;
> +
> + /* Bits per pixel */
> + unsigned int bpp;
> +
> + /* Frame width */
> + unsigned int width;
> +
> + /* Frame height */
> + unsigned int height;
> +
> + /*
> + * Minimum horizontal timing in pixel-units
> + *
> + * Note that HMAX is written in 72MHz units, and the datasheet assumes a
> + * 720MHz link frequency. Convert datasheet values with the following:
> + *
> + * For 12 bpp modes (480Mbps) convert with:
> + * hmax = [hmax in 72MHz units] * 480 / 72
> + *
> + * For 10 bpp modes (576Mbps) convert with:
> + * hmax = [hmax in 72MHz units] * 576 / 72
> + */
> + u32 min_hmax;
> +
> + /* minimum V-timing in lines */
> + u32 min_vmax;
> +
> + /* default H-timing */
> + u32 default_hmax;
> +
> + /* default V-timing */
> + u32 default_vmax;
> +
> + /* minimum SHR */
> + u32 min_shr;
> +
> + /*
> + * Per-mode vertical crop constants used to calculate values
> + * of IMX283REG_WIDCUT and IMX283_REG_VWINPOS.
> + */
> + u32 veff;
> + u32 vst;
> + u32 vct;
> +
> + /* Horizontal and vertical binning ratio */
> + u8 hbin_ratio;
> + u8 vbin_ratio;
> +
> + /* Optical Blanking */
> + u32 horizontal_ob;
> + u32 vertical_ob;
> +
> + /* Analog crop rectangle. */
> + struct v4l2_rect crop;
> +};
> +
> +struct imx283_input_frequency {
> + unsigned int mhz;
> + unsigned int reg_count;
> + struct cci_reg_sequence regs[4];
> +};
> +
> +static const struct imx283_input_frequency imx283_frequencies[] = {
> + {
> + .mhz = 6 * HZ_PER_MHZ,
> + .reg_count = 4,
> + .regs = {
> + { IMX283_REG_PLRD1, 0x00 },
> + { IMX283_REG_PLRD2, 0x00f0 },
> + { IMX283_REG_PLRD3, 0x00 },
> + { IMX283_REG_PLRD4, 0xc0 },
> + },
> + },
> + {
> + .mhz = 12 * HZ_PER_MHZ,
> + .reg_count = 4,
> + .regs = {
> + { IMX283_REG_PLRD1, 0x01 },
> + { IMX283_REG_PLRD2, 0x00f0 },
> + { IMX283_REG_PLRD3, 0x01 },
> + { IMX283_REG_PLRD4, 0xc0 },
> + },
> + },
> + {
> + .mhz = 18 * HZ_PER_MHZ,
> + .reg_count = 4,
> + .regs = {
> + { IMX283_REG_PLRD1, 0x01 },
> + { IMX283_REG_PLRD2, 0x00a0 },
> + { IMX283_REG_PLRD3, 0x01 },
> + { IMX283_REG_PLRD4, 0x80 },
> + },
> + },
> + {
> + .mhz = 24 * HZ_PER_MHZ,
> + .reg_count = 4,
> + .regs = {
> + { IMX283_REG_PLRD1, 0x02 },
> + { IMX283_REG_PLRD2, 0x00f0 },
> + { IMX283_REG_PLRD3, 0x02 },
> + { IMX283_REG_PLRD4, 0xc0 },
> + },
> + },
> +};
> +
> +enum imx283_modes {
> + IMX283_MODE_0,
> + IMX283_MODE_1,
> + IMX283_MODE_1A,
> + IMX283_MODE_1S,
> + IMX283_MODE_2,
> + IMX283_MODE_2A,
> + IMX283_MODE_3,
> + IMX283_MODE_4,
> + IMX283_MODE_5,
> + IMX283_MODE_6,
> +};
> +
> +struct imx283_readout_mode {
> + u8 mdsel1;
> + u8 mdsel2;
> + u8 mdsel3;
> + u8 mdsel4;
> +};
> +
> +static const struct imx283_readout_mode imx283_readout_modes[] = {
> + /* All pixel scan modes */
> + [IMX283_MODE_0] = { 0x04, 0x03, 0x10, 0x00 }, /* 12 bit */
> + [IMX283_MODE_1] = { 0x04, 0x01, 0x00, 0x00 }, /* 10 bit */
> + [IMX283_MODE_1A] = { 0x04, 0x01, 0x20, 0x50 }, /* 10 bit */
> + [IMX283_MODE_1S] = { 0x04, 0x41, 0x20, 0x50 }, /* 10 bit */
> +
> + /* Horizontal / Vertical 2/2-line binning */
> + [IMX283_MODE_2] = { 0x0d, 0x11, 0x50, 0x00 }, /* 12 bit */
> + [IMX283_MODE_2A] = { 0x0d, 0x11, 0x70, 0x50 }, /* 12 bit */
> +
> + /* Horizontal / Vertical 3/3-line binning */
> + [IMX283_MODE_3] = { 0x1e, 0x18, 0x10, 0x00 }, /* 12 bit */
> +
> + /* Vertical 2/9 subsampling, horizontal 3 binning cropping */
> + [IMX283_MODE_4] = { 0x29, 0x18, 0x30, 0x50 }, /* 12 bit */
> +
> + /* Vertical 2/19 subsampling binning, horizontal 3 binning */
> + [IMX283_MODE_5] = { 0x2d, 0x18, 0x10, 0x00 }, /* 12 bit */
> +
> + /* Vertical 2 binning horizontal 2/4, subsampling 16:9 cropping */
> + [IMX283_MODE_6] = { 0x18, 0x21, 0x00, 0x09 }, /* 10 bit */
> +
> + /*
> + * New modes should make sure the offset period is complied.
> + * See imx283_exposure() for reference.
> + */
> +};
> +
> +static const struct cci_reg_sequence mipi_data_rate_1440Mbps[] = {
> + /* The default register settings provide the 1440Mbps rate */
> + { CCI_REG8(0x36c5), 0x00 }, /* Undocumented */
> + { CCI_REG8(0x3ac4), 0x00 }, /* Undocumented */
> +
> + { IMX283_REG_STBPL, 0x00 },
> + { IMX283_REG_TCLKPOST, 0xa7 },
> + { IMX283_REG_THSPREPARE, 0x6f },
> + { IMX283_REG_THSZERO, 0x9f },
> + { IMX283_REG_THSTRAIL, 0x5f },
> + { IMX283_REG_TCLKTRAIL, 0x5f },
> + { IMX283_REG_TCLKPREPARE, 0x6f },
> + { IMX283_REG_TCLKZERO, 0x017f },
> + { IMX283_REG_TLPX, 0x4f },
> + { IMX283_REG_THSEXIT, 0x47 },
> + { IMX283_REG_TCLKPRE, 0x07 },
> + { IMX283_REG_SYSMODE, 0x02 },
> +};
> +
> +static const struct cci_reg_sequence mipi_data_rate_720Mbps[] = {
> + /* Undocumented Additions "For 720MBps" Setting */
> + { CCI_REG8(0x36c5), 0x01 }, /* Undocumented */
> + { CCI_REG8(0x3ac4), 0x01 }, /* Undocumented */
> +
> + { IMX283_REG_STBPL, 0x00 },
> + { IMX283_REG_TCLKPOST, 0x77 },
> + { IMX283_REG_THSPREPARE, 0x37 },
> + { IMX283_REG_THSZERO, 0x67 },
> + { IMX283_REG_THSTRAIL, 0x37 },
> + { IMX283_REG_TCLKTRAIL, 0x37 },
> + { IMX283_REG_TCLKPREPARE, 0x37 },
> + { IMX283_REG_TCLKZERO, 0xdf },
> + { IMX283_REG_TLPX, 0x2f },
> + { IMX283_REG_THSEXIT, 0x47 },
> + { IMX283_REG_TCLKPRE, 0x0f },
> + { IMX283_REG_SYSMODE, 0x02 },
> +};
> +
> +static const s64 link_frequencies[] = {
> + 720 * HZ_PER_MHZ, /* 1440 Mbps lane data rate */
> + 360 * HZ_PER_MHZ, /* 720 Mbps data lane rate */
> +};
> +
> +static const struct imx283_reg_list link_freq_reglist[] = {
> + { /* 720 MHz */
> + .num_of_regs = ARRAY_SIZE(mipi_data_rate_1440Mbps),
> + .regs = mipi_data_rate_1440Mbps,
> + },
> + { /* 360 MHz */
> + .num_of_regs = ARRAY_SIZE(mipi_data_rate_720Mbps),
> + .regs = mipi_data_rate_720Mbps,
> + },
> +};
> +
> +#define CENTERED_RECTANGLE(rect, _width, _height) \
> + { \
> + .left = rect.left + ((rect.width - (_width)) / 2), \
> + .top = rect.top + ((rect.height - (_height)) / 2), \
> + .width = (_width), \
> + .height = (_height), \
> + }
> +
> +/* Mode configs */
> +static const struct imx283_mode supported_modes_12bit[] = {
> + {
> + /* 20MPix 21.40 fps readout mode 0 */
> + .mode = IMX283_MODE_0,
> + .bpp = 12,
> + .width = 5472,
> + .height = 3648,
> + .min_hmax = 5914, /* 887 @ 480MHz/72MHz */
> + .min_vmax = 3793, /* Lines */
> +
> + .veff = 3694,
> + .vst = 0,
> + .vct = 0,
> +
> + .hbin_ratio = 1,
> + .vbin_ratio = 1,
> +
> + /* 20.00 FPS */
> + .default_hmax = 6000, /* 900 @ 480MHz/72MHz */
> + .default_vmax = 4000,
> +
> + .min_shr = 11,
> + .horizontal_ob = 96,
> + .vertical_ob = 16,
> + .crop = CENTERED_RECTANGLE(imx283_active_area, 5472, 3648),
> + },
> + {
> + /*
> + * Readout mode 2 : 2/2 binned mode (2736x1824)
> + */
> + .mode = IMX283_MODE_2,
> + .bpp = 12,
> + .width = 2736,
> + .height = 1824,
> + .min_hmax = 2414, /* Pixels (362 * 480MHz/72MHz + padding) */
> + .min_vmax = 3840, /* Lines */
> +
> + /* 50.00 FPS */
> + .default_hmax = 2500, /* 375 @ 480MHz/72Mhz */
> + .default_vmax = 3840,
> +
> + .veff = 1824,
> + .vst = 0,
> + .vct = 0,
> +
> + .hbin_ratio = 2,
> + .vbin_ratio = 2,
> +
> + .min_shr = 12,
> + .horizontal_ob = 48,
> + .vertical_ob = 4,
> +
> + .crop = CENTERED_RECTANGLE(imx283_active_area, 5472, 3648),
> + },
> +};
> +
> +static const struct imx283_mode supported_modes_10bit[] = {
> + {
> + /* 20MPix 25.48 fps readout mode 1 */
> + .mode = IMX283_MODE_1,
> + .bpp = 10,
> + .width = 5472,
> + .height = 3648,
> + .min_hmax = 5960, /* 745 @ 576MHz / 72MHz */
> + .min_vmax = 3793,
> +
> + /* 25.00 FPS */
> + .default_hmax = 6000, /* 750 @ 576MHz / 72MHz */
> + .default_vmax = 3840,
> +
> + .min_shr = 10,
> + .horizontal_ob = 96,
> + .vertical_ob = 16,
> + .crop = CENTERED_RECTANGLE(imx283_active_area, 5472, 3648),
> + },
> +};
> +
> +static const u32 imx283_mbus_codes[] = {
> + MEDIA_BUS_FMT_SRGGB12_1X12,
> + MEDIA_BUS_FMT_SRGGB10_1X10,
> +};
> +
> +/* regulator supplies */
> +static const char *const imx283_supply_name[] = {
> + "vadd", /* Analog (2.9V) supply */
> + "vdd1", /* Supply Voltage 2 (1.8V) supply */
> + "vdd2", /* Supply Voltage 3 (1.2V) supply */
> +};
> +
> +struct imx283 {
> + struct device *dev;
> + struct regmap *cci;
> +
> + const struct imx283_input_frequency *freq;
> +
> + struct v4l2_subdev sd;
> + struct media_pad pad;
> +
> + struct clk *xclk;
> +
> + struct gpio_desc *reset_gpio;
> + struct regulator_bulk_data supplies[ARRAY_SIZE(imx283_supply_name)];
> +
> + /* V4L2 Controls */
> + struct v4l2_ctrl_handler ctrl_handler;
> + struct v4l2_ctrl *exposure;
> + struct v4l2_ctrl *vblank;
> + struct v4l2_ctrl *hblank;
> + struct v4l2_ctrl *vflip;
> +
> + unsigned long link_freq_bitmap;
> +
> + u16 hmax;
> + u32 vmax;
> +};
> +
> +static inline struct imx283 *to_imx283(struct v4l2_subdev *sd)
> +{
> + return container_of_const(sd, struct imx283, sd);
> +}
> +
> +static inline void get_mode_table(unsigned int code,
> + const struct imx283_mode **mode_list,
> + unsigned int *num_modes)
> +{
> + switch (code) {
> + case MEDIA_BUS_FMT_SRGGB12_1X12:
> + case MEDIA_BUS_FMT_SGRBG12_1X12:
> + case MEDIA_BUS_FMT_SGBRG12_1X12:
> + case MEDIA_BUS_FMT_SBGGR12_1X12:
> + *mode_list = supported_modes_12bit;
> + *num_modes = ARRAY_SIZE(supported_modes_12bit);
> + break;
> +
> + case MEDIA_BUS_FMT_SRGGB10_1X10:
> + case MEDIA_BUS_FMT_SGRBG10_1X10:
> + case MEDIA_BUS_FMT_SGBRG10_1X10:
> + case MEDIA_BUS_FMT_SBGGR10_1X10:
> + *mode_list = supported_modes_10bit;
> + *num_modes = ARRAY_SIZE(supported_modes_10bit);
> + break;
> + default:
> + *mode_list = NULL;
> + *num_modes = 0;
> + break;
> + }
> +}
> +
> +/* Calculate the Pixel Rate based on the current mode */
> +static u64 imx283_pixel_rate(struct imx283 *imx283,
> + const struct imx283_mode *mode)
> +{
> + u64 link_frequency = link_frequencies[__ffs(imx283->link_freq_bitmap)];
> + unsigned int bpp = mode->bpp;
> + const unsigned int ddr = 2; /* Double Data Rate */
> + const unsigned int lanes = 4; /* Only 4 lane support */
> + u64 numerator = link_frequency * ddr * lanes;
> +
> + do_div(numerator, bpp);
> +
> + return numerator;
> +}
> +
> +/* Convert from a variable pixel_rate to 72 MHz clock cycles */
> +static u64 imx283_internal_clock(unsigned int pixel_rate, unsigned int pixels)
> +{
> + /*
> + * Determine the following operation without overflow:
> + * pixels = 72 Mhz / pixel_rate
> + *
> + * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz)
> + * can easily overflow this calculation, so pre-divide to simplify.
> + */
> + const u32 iclk_pre = 72;
> + const u32 pclk_pre = pixel_rate / HZ_PER_MHZ;
> + u64 numerator = pixels * iclk_pre;
> +
> + do_div(numerator, pclk_pre);
> +
> + return numerator;
> +}
> +
> +/* Internal clock (72MHz) to Pixel Rate clock (Variable) */
> +static u64 imx283_iclk_to_pix(unsigned int pixel_rate, unsigned int cycles)
> +{
> + /*
> + * Determine the following operation without overflow:
> + * cycles * pixel_rate / 72 MHz
> + *
> + * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz)
> + * can easily overflow this calculation, so pre-divide to simplify.
> + */
> + const u32 iclk_pre = 72;
> + const u32 pclk_pre = pixel_rate / HZ_PER_MHZ;
> + u64 numerator = cycles * pclk_pre;
> +
> + do_div(numerator, iclk_pre);
> +
> + return numerator;
> +}
> +
> +/* Determine the exposure based on current hmax, vmax and a given SHR */
> +static u32 imx283_exposure(struct imx283 *imx283,
> + const struct imx283_mode *mode, u64 shr)
> +{
> + u32 svr = 0; /* SVR feature is not currently supported */
> + u32 offset;
> + u64 numerator;
> +
> + /* Number of clocks per internal offset period */
> + offset = mode->mode == IMX283_MODE_0 ? 209 : 157;
> + numerator = (imx283->vmax * (svr + 1) - shr) * imx283->hmax + offset;
> +
> + do_div(numerator, imx283->hmax);
> +
> + return clamp(numerator, 0, U32_MAX);
> +}
> +
> +static void imx283_exposure_limits(struct imx283 *imx283,
> + const struct imx283_mode *mode,
> + s64 *min_exposure, s64 *max_exposure)
> +{
> + u32 svr = 0; /* SVR feature is not currently supported */
> + u64 min_shr = mode->min_shr;
> + /* Global Shutter is not supported */
> + u64 max_shr = (svr + 1) * imx283->vmax - 4;
> +
> + max_shr = min(max_shr, BIT(16) - 1);
> +
> + *min_exposure = imx283_exposure(imx283, mode, max_shr);
> + *max_exposure = imx283_exposure(imx283, mode, min_shr);
> +}
> +
> +/*
> + * Integration Time [s] = [ {VMAX x (SVR + 1) – (SHR)} x HMAX + offset ]
> + * / [ 72 x 10^6 ]
> + */
> +static u32 imx283_shr(struct imx283 *imx283, const struct imx283_mode *mode,
> + u32 exposure)
> +{
> + u32 svr = 0; /* SVR feature is not currently supported */
> + u32 offset;
> + u64 temp;
> +
> + /* Number of clocks per internal offset period */
> + offset = mode->mode == IMX283_MODE_0 ? 209 : 157;
> + temp = ((u64)exposure * imx283->hmax - offset);
> + do_div(temp, imx283->hmax);
> +
> + return (imx283->vmax * (svr + 1) - temp);
> +}
> +
> +static const char * const imx283_tpg_menu[] = {
> + "Disabled",
> + "All 000h",
> + "All FFFh",
> + "All 555h",
> + "All AAAh",
> + "Horizontal color bars",
> + "Vertical color bars",
> +};
> +
> +static const int imx283_tpg_val[] = {
> + IMX283_TPG_PAT_ALL_000,
> + IMX283_TPG_PAT_ALL_000,
> + IMX283_TPG_PAT_ALL_FFF,
> + IMX283_TPG_PAT_ALL_555,
> + IMX283_TPG_PAT_ALL_AAA,
> + IMX283_TPG_PAT_H_COLOR_BARS,
> + IMX283_TPG_PAT_V_COLOR_BARS,
> +};
> +
> +static int imx283_update_test_pattern(struct imx283 *imx283, u32 pattern_index)
> +{
> + int ret;
> +
> + if (pattern_index >= ARRAY_SIZE(imx283_tpg_val))
> + return -EINVAL;
> +
> + if (!pattern_index)
> + return cci_write(imx283->cci, IMX283_REG_TPG_CTRL, 0x00, NULL);
> +
> + ret = cci_write(imx283->cci, IMX283_REG_TPG_PAT,
> + imx283_tpg_val[pattern_index], NULL);
> + if (ret)
> + return ret;
> +
> + return cci_write(imx283->cci, IMX283_REG_TPG_CTRL,
> + IMX283_TPG_CTRL_CLKEN | IMX283_TPG_CTRL_PATEN, NULL);
> +}
> +
> +static int imx283_set_ctrl(struct v4l2_ctrl *ctrl)
> +{
> + struct imx283 *imx283 = container_of(ctrl->handler, struct imx283,
> + ctrl_handler);
> + const struct imx283_mode *mode;
> + struct v4l2_mbus_framefmt *fmt;
> + const struct imx283_mode *mode_list;
> + struct v4l2_subdev_state *state;
> + unsigned int num_modes;
> + u64 shr, pixel_rate;
> + int ret = 0;
> +
> + state = v4l2_subdev_get_locked_active_state(&imx283->sd);
> + fmt = v4l2_subdev_state_get_format(state, 0);
> +
> + get_mode_table(fmt->code, &mode_list, &num_modes);
> + mode = v4l2_find_nearest_size(mode_list, num_modes, width, height,
> + fmt->width, fmt->height);
> +
> + /*
> + * The VBLANK control may change the limits of usable exposure, so check
> + * and adjust if necessary.
> + */
> + if (ctrl->id == V4L2_CID_VBLANK) {
> + /* Honour the VBLANK limits when setting exposure. */
> + s64 current_exposure, max_exposure, min_exposure;
> +
> + imx283->vmax = mode->height + ctrl->val;
> +
> + imx283_exposure_limits(imx283, mode,
> + &min_exposure, &max_exposure);
> +
> + current_exposure = imx283->exposure->val;
> + current_exposure = clamp(current_exposure, min_exposure,
> + max_exposure);
> +
> + __v4l2_ctrl_modify_range(imx283->exposure, min_exposure,
> + max_exposure, 1, current_exposure);
> + }
> +
> + /*
> + * Applying V4L2 control value only happens
> + * when power is up for streaming
> + */
> + if (!pm_runtime_get_if_active(imx283->dev, true))
> + return 0;
> +
> + switch (ctrl->id) {
> + case V4L2_CID_EXPOSURE:
> + shr = imx283_shr(imx283, mode, ctrl->val);
> + dev_dbg(imx283->dev, "V4L2_CID_EXPOSURE : %d - SHR: %lld\n",
> + ctrl->val, shr);
> + ret = cci_write(imx283->cci, IMX283_REG_SHR, shr, NULL);
> + break;
> +
> + case V4L2_CID_HBLANK:
> + pixel_rate = imx283_pixel_rate(imx283, mode);
> + imx283->hmax = imx283_internal_clock(pixel_rate, mode->width + ctrl->val);
> + dev_dbg(imx283->dev, "V4L2_CID_HBLANK : %d HMAX : %u\n",
> + ctrl->val, imx283->hmax);
> + ret = cci_write(imx283->cci, IMX283_REG_HMAX, imx283->hmax, NULL);
> + break;
> +
> + case V4L2_CID_VBLANK:
> + imx283->vmax = mode->height + ctrl->val;
> + dev_dbg(imx283->dev, "V4L2_CID_VBLANK : %d VMAX : %u\n",
> + ctrl->val, imx283->vmax);
> + ret = cci_write(imx283->cci, IMX283_REG_VMAX, imx283->vmax, NULL);
> + break;
> +
> + case V4L2_CID_ANALOGUE_GAIN:
> + ret = cci_write(imx283->cci, IMX283_REG_ANALOG_GAIN, ctrl->val, NULL);
> + break;
> +
> + case V4L2_CID_DIGITAL_GAIN:
> + ret = cci_write(imx283->cci, IMX283_REG_DIGITAL_GAIN, ctrl->val, NULL);
> + break;
> +
> + case V4L2_CID_VFLIP:
> + /*
> + * VFLIP is managed by BIT(0) of IMX283_REG_HTRIMMING address, hence
> + * both need to be set simultaneously.
> + */
> + if (ctrl->val) {
> + cci_write(imx283->cci, IMX283_REG_HTRIMMING,
> + IMX283_HTRIMMING_EN | IMX283_MDVREV, &ret);
> + } else {
> + cci_write(imx283->cci, IMX283_REG_HTRIMMING,
> + IMX283_HTRIMMING_EN, &ret);
> + }
> + break;
> +
> + case V4L2_CID_TEST_PATTERN:
> + ret = imx283_update_test_pattern(imx283, ctrl->val);
> + break;
> +
> + default:
> + dev_err(imx283->dev, "ctrl(id:0x%x, val:0x%x) is not handled\n",
> + ctrl->id, ctrl->val);
> + break;
> + }
> +
> + pm_runtime_put(imx283->dev);
> +
> + return ret;
> +}
> +
> +static const struct v4l2_ctrl_ops imx283_ctrl_ops = {
> + .s_ctrl = imx283_set_ctrl,
> +};
> +
> +static int imx283_enum_mbus_code(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_subdev_mbus_code_enum *code)
> +{
> + if (code->index >= ARRAY_SIZE(imx283_mbus_codes))
> + return -EINVAL;
> +
> + code->code = imx283_mbus_codes[code->index];
> +
> + return 0;
> +}
> +
> +static int imx283_enum_frame_size(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_subdev_frame_size_enum *fse)
> +{
> + const struct imx283_mode *mode_list;
> + unsigned int num_modes;
> +
> + get_mode_table(fse->code, &mode_list, &num_modes);
> +
> + if (fse->index >= num_modes)
> + return -EINVAL;
> +
> + fse->min_width = mode_list[fse->index].width;
> + fse->max_width = fse->min_width;
> + fse->min_height = mode_list[fse->index].height;
> + fse->max_height = fse->min_height;
> +
> + return 0;
> +}
> +
> +static void imx283_update_image_pad_format(struct imx283 *imx283,
> + const struct imx283_mode *mode,
> + struct v4l2_mbus_framefmt *format)
> +{
> + format->width = mode->width;
> + format->height = mode->height;
> + format->field = V4L2_FIELD_NONE;
> + format->colorspace = V4L2_COLORSPACE_RAW;
> + format->ycbcr_enc = V4L2_YCBCR_ENC_601;
> + format->quantization = V4L2_QUANTIZATION_FULL_RANGE;
> + format->xfer_func = V4L2_XFER_FUNC_NONE;
> +}
> +
> +static int imx283_init_state(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state)
> +{
> + struct imx283 *imx283 = to_imx283(sd);
> + struct v4l2_mbus_framefmt *format;
> + const struct imx283_mode *mode;
> + struct v4l2_rect *crop;
> +
> + /* Initialize try_fmt */
> + format = v4l2_subdev_state_get_format(state, IMAGE_PAD);
> +
> + mode = &supported_modes_12bit[0];
> + format->code = MEDIA_BUS_FMT_SRGGB12_1X12;
> + imx283_update_image_pad_format(imx283, mode, format);
> +
> + /* Initialize crop rectangle to mode default */
> + crop = v4l2_subdev_state_get_crop(state, IMAGE_PAD);
> + *crop = mode->crop;
> +
> + return 0;
> +}
> +
> +static void imx283_set_framing_limits(struct imx283 *imx283,
> + const struct imx283_mode *mode)
> +{
> + u64 pixel_rate = imx283_pixel_rate(imx283, mode);
> + u64 min_hblank, max_hblank, def_hblank;
> +
> + /* Initialise hmax and vmax for exposure calculations */
> + imx283->hmax = imx283_internal_clock(pixel_rate, mode->default_hmax);
> + imx283->vmax = mode->default_vmax;
> +
> + /*
> + * Horizontal Blanking
> + * Convert the HMAX_MAX (72MHz) to Pixel rate values for HBLANK_MAX
> + */
> + min_hblank = mode->min_hmax - mode->width;
> + max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width;
> + def_hblank = mode->default_hmax - mode->width;
> + __v4l2_ctrl_modify_range(imx283->hblank, min_hblank, max_hblank, 1,
> + def_hblank);
> + __v4l2_ctrl_s_ctrl(imx283->hblank, def_hblank);
> +
> + /* Vertical Blanking */
> + __v4l2_ctrl_modify_range(imx283->vblank, mode->min_vmax - mode->height,
> + IMX283_VMAX_MAX - mode->height, 1,
> + mode->default_vmax - mode->height);
> + __v4l2_ctrl_s_ctrl(imx283->vblank, mode->default_vmax - mode->height);
> +}
> +
> +static int imx283_set_pad_format(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_subdev_format *fmt)
> +{
> + struct v4l2_mbus_framefmt *format;
> + const struct imx283_mode *mode;
> + struct imx283 *imx283 = to_imx283(sd);
> + const struct imx283_mode *mode_list;
> + unsigned int num_modes;
> +
> + get_mode_table(fmt->format.code, &mode_list, &num_modes);
> +
> + mode = v4l2_find_nearest_size(mode_list, num_modes, width, height,
> + fmt->format.width, fmt->format.height);
> +
> + fmt->format.width = mode->width;
> + fmt->format.height = mode->height;
> + fmt->format.field = V4L2_FIELD_NONE;
> + fmt->format.colorspace = V4L2_COLORSPACE_RAW;
> + fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601;
> + fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE;
> + fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;
> +
> + format = v4l2_subdev_state_get_format(sd_state, 0);
> +
> + if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
> + imx283_set_framing_limits(imx283, mode);
> +
> + *format = fmt->format;
> +
> + return 0;
> +}
> +
> +static int imx283_standby_cancel(struct imx283 *imx283)
> +{
> + unsigned int link_freq_idx;
> + int ret = 0;
> +
> + cci_write(imx283->cci, IMX283_REG_STANDBY,
> + IMX283_STBLOGIC | IMX283_STBDV, &ret);
> +
> + /* Configure PLL clocks based on the xclk */
> + cci_multi_reg_write(imx283->cci, imx283->freq->regs,
> + imx283->freq->reg_count, &ret);
> +
> + dev_dbg(imx283->dev, "Using clk freq %ld MHz",
> + imx283->freq->mhz / HZ_PER_MHZ);
> +
> + /* Initialise communication */
> + cci_write(imx283->cci, IMX283_REG_PLSTMG08, IMX283_PLSTMG08_VAL, &ret);
> + cci_write(imx283->cci, IMX283_REG_PLSTMG02, IMX283_PLSTMG02_VAL, &ret);
> +
> + /* Enable PLL */
> + cci_write(imx283->cci, IMX283_REG_STBPL, IMX283_STBPL_NORMAL, &ret);
> +
> + /* Configure the MIPI link speed */
> + link_freq_idx = __ffs(imx283->link_freq_bitmap);
> + cci_multi_reg_write(imx283->cci, link_freq_reglist[link_freq_idx].regs,
> + link_freq_reglist[link_freq_idx].num_of_regs,
> + &ret);
> +
> + /* 1st Stabilisation period of 1 ms or more */
> + usleep_range(1000, 2000);
> +
> + /* Activate */
> + cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_ACTIVE, &ret);
> +
> + /* 2nd Stabilisation period of 19ms or more */
> + usleep_range(19000, 20000);
> +
> + cci_write(imx283->cci, IMX283_REG_CLAMP, IMX283_CLPSQRST, &ret);
> + cci_write(imx283->cci, IMX283_REG_XMSTA, 0, &ret);
> + cci_write(imx283->cci, IMX283_REG_SYNCDRV, IMX283_SYNCDRV_XHS_XVS, &ret);
> +
> + return ret;
> +}
> +
> +/* Start streaming */
> +static int imx283_start_streaming(struct imx283 *imx283,
> + struct v4l2_subdev_state *state)
> +{
> + const struct imx283_readout_mode *readout;
> + const struct imx283_mode *mode;
> + const struct v4l2_mbus_framefmt *fmt;
> + const struct imx283_mode *mode_list;
> + unsigned int num_modes;
> + u32 v_widcut;
> + s32 v_pos;
> + u32 write_v_size;
> + u32 y_out_size;
> + int ret = 0;
> +
> + fmt = v4l2_subdev_state_get_format(state, 0);
> + get_mode_table(fmt->code, &mode_list, &num_modes);
> + mode = v4l2_find_nearest_size(mode_list, num_modes, width, height,
> + fmt->width, fmt->height);
> +
> + ret = imx283_standby_cancel(imx283);
> + if (ret) {
> + dev_err(imx283->dev, "failed to cancel standby\n");
> + return ret;
> + }
> +
> + /*
> + * Set the readout mode registers.
> + * MDSEL3 and MDSEL4 are updated to enable Arbitrary Vertical Cropping.
> + */
> + readout = &imx283_readout_modes[mode->mode];
> + cci_write(imx283->cci, IMX283_REG_MDSEL1, readout->mdsel1, &ret);
> + cci_write(imx283->cci, IMX283_REG_MDSEL2, readout->mdsel2, &ret);
> + cci_write(imx283->cci, IMX283_REG_MDSEL3,
> + readout->mdsel3 | IMX283_MDSEL3_VCROP_EN, &ret);
> + cci_write(imx283->cci, IMX283_REG_MDSEL4,
> + readout->mdsel4 | IMX283_MDSEL4_VCROP_EN, &ret);
> +
> + /* Mode 1S specific entries from the Readout Drive Mode Tables */
> + if (mode->mode == IMX283_MODE_1S) {
> + cci_write(imx283->cci, IMX283_REG_MDSEL7, 0x01, &ret);
> + cci_write(imx283->cci, IMX283_REG_MDSEL18, 0x1098, &ret);
> + }
> +
> + if (ret) {
> + dev_err(imx283->dev, "failed to set readout\n");
> + return ret;
> + }
> +
> + /* Initialise SVR. Unsupported for now - Always 0 */
> + cci_write(imx283->cci, IMX283_REG_SVR, 0x00, &ret);
> +
> + dev_dbg(imx283->dev, "Mode: Size %d x %d\n", mode->width, mode->height);
> + dev_dbg(imx283->dev, "Analogue Crop (in the mode) %d,%d %dx%d\n",
> + mode->crop.left,
> + mode->crop.top,
> + mode->crop.width,
> + mode->crop.height);
> +
> + y_out_size = mode->crop.height / mode->vbin_ratio;
> + write_v_size = y_out_size + mode->vertical_ob;
> + /*
> + * cropping start position = (VWINPOS – Vst) × 2
> + * cropping width = Veff – (VWIDCUT – Vct) × 2
> + */
> + v_pos = imx283->vflip->val ?
> + ((-mode->crop.top / mode->vbin_ratio) / 2) + mode->vst :
> + ((mode->crop.top / mode->vbin_ratio) / 2) + mode->vst;
> + v_widcut = ((mode->veff - y_out_size) / 2) + mode->vct;
> +
> + cci_write(imx283->cci, IMX283_REG_Y_OUT_SIZE, y_out_size, &ret);
> + cci_write(imx283->cci, IMX283_REG_WRITE_VSIZE, write_v_size, &ret);
> + cci_write(imx283->cci, IMX283_REG_VWIDCUT, v_widcut, &ret);
> + cci_write(imx283->cci, IMX283_REG_VWINPOS, v_pos, &ret);
> +
> + cci_write(imx283->cci, IMX283_REG_OB_SIZE_V, mode->vertical_ob, &ret);
> +
> + /* TODO: Validate mode->crop is fully contained within imx283_native_area */
> + cci_write(imx283->cci, IMX283_REG_HTRIMMING_START, mode->crop.left, &ret);
> + cci_write(imx283->cci, IMX283_REG_HTRIMMING_END,
> + mode->crop.left + mode->crop.width, &ret);
> +
> + /* Disable embedded data */
> + cci_write(imx283->cci, IMX283_REG_EBD_X_OUT_SIZE, 0, &ret);
> +
> + /* Apply customized values from controls (HMAX/VMAX/SHR) */
> + ret = __v4l2_ctrl_handler_setup(imx283->sd.ctrl_handler);
> +
> + return ret;
> +}
> +
> +static int imx283_enable_streams(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state, u32 pad,
> + u64 streams_mask)
> +{
> + struct imx283 *imx283 = to_imx283(sd);
> + int ret;
> +
> + if (pad != IMAGE_PAD)
> + return -EINVAL;
> +
> + ret = pm_runtime_get_sync(imx283->dev);
> + if (ret < 0) {
> + pm_runtime_put_noidle(imx283->dev);
> + return ret;
> + }
> +
> + ret = imx283_start_streaming(imx283, state);
> + if (ret)
> + goto err_rpm_put;
> +
> + return 0;
> +
> +err_rpm_put:
> + pm_runtime_mark_last_busy(imx283->dev);
> + pm_runtime_put_autosuspend(imx283->dev);
> +
> + return ret;
> +}
> +
> +static int imx283_disable_streams(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *state, u32 pad,
> + u64 streams_mask)
> +{
> + struct imx283 *imx283 = to_imx283(sd);
> + int ret;
> +
> + if (pad != IMAGE_PAD)
> + return -EINVAL;
> +
> + ret = cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_STBLOGIC, NULL);
> + if (ret)
> + dev_err(imx283->dev, "Failed to stop stream\n");
> +
> + pm_runtime_mark_last_busy(imx283->dev);
> + pm_runtime_put_autosuspend(imx283->dev);
> +
> + return ret;
> +}
> +
> +/* Power/clock management functions */
> +static int imx283_power_on(struct imx283 *imx283)
> +{
> + int ret;
> +
> + ret = regulator_bulk_enable(ARRAY_SIZE(imx283_supply_name),
> + imx283->supplies);
> + if (ret) {
> + dev_err(imx283->dev, "failed to enable regulators\n");
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(imx283->xclk);
> + if (ret) {
> + dev_err(imx283->dev, "failed to enable clock\n");
> + goto reg_off;
> + }
> +
> + gpiod_set_value_cansleep(imx283->reset_gpio, 0);
> +
> + usleep_range(IMX283_XCLR_MIN_DELAY_US,
> + IMX283_XCLR_MIN_DELAY_US + IMX283_XCLR_DELAY_RANGE_US);
> +
> + return 0;
> +
> +reg_off:
> + regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies);
> + return ret;
> +}
> +
> +static int imx283_power_off(struct imx283 *imx283)
> +{
> + gpiod_set_value_cansleep(imx283->reset_gpio, 1);
> + regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies);
> + clk_disable_unprepare(imx283->xclk);
> +
> + return 0;
> +}
> +
> +static int imx283_runtime_resume(struct device *dev)
> +{
> + struct v4l2_subdev *sd = dev_get_drvdata(dev);
> + struct imx283 *imx283 = to_imx283(sd);
> +
> + return imx283_power_on(imx283);
> +}
> +
> +static int imx283_runtime_suspend(struct device *dev)
> +{
> + struct v4l2_subdev *sd = dev_get_drvdata(dev);
> + struct imx283 *imx283 = to_imx283(sd);
> +
> + imx283_power_off(imx283);
> +
> + return 0;
> +}
> +
> +static int imx283_get_regulators(struct imx283 *imx283)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(imx283_supply_name); i++)
> + imx283->supplies[i].supply = imx283_supply_name[i];
> +
> + return devm_regulator_bulk_get(imx283->dev,
> + ARRAY_SIZE(imx283_supply_name),
> + imx283->supplies);
> +}
> +
> +/* Verify chip ID */
> +static int imx283_identify_module(struct imx283 *imx283)
> +{
> + int ret;
> + u64 val;
> +
> + ret = cci_read(imx283->cci, IMX283_REG_CHIP_ID, &val, NULL);
> + if (ret) {
> + dev_err(imx283->dev, "failed to read chip id %x, with error %d\n",
> + IMX283_CHIP_ID, ret);
> + return ret;
> + }
> +
> + if (val != IMX283_CHIP_ID) {
> + dev_err(imx283->dev, "chip id mismatch: %x!=%llx\n",
> + IMX283_CHIP_ID, val);
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static int imx283_get_selection(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_subdev_selection *sel)
> +{
> + switch (sel->target) {
> + case V4L2_SEL_TGT_CROP: {
> + sel->r = *v4l2_subdev_state_get_crop(sd_state, 0);
> + return 0;
> + }
> +
> + case V4L2_SEL_TGT_NATIVE_SIZE:
> + sel->r = imx283_native_area;
> + return 0;
> +
> + case V4L2_SEL_TGT_CROP_DEFAULT:
> + case V4L2_SEL_TGT_CROP_BOUNDS:
> + sel->r = imx283_active_area;
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static const struct v4l2_subdev_core_ops imx283_core_ops = {
> + .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
> + .unsubscribe_event = v4l2_event_subdev_unsubscribe,
> +};
> +
> +static const struct v4l2_subdev_video_ops imx283_video_ops = {
> + .s_stream = v4l2_subdev_s_stream_helper,
> +};
> +
> +static const struct v4l2_subdev_pad_ops imx283_pad_ops = {
> + .enum_mbus_code = imx283_enum_mbus_code,
> + .get_fmt = v4l2_subdev_get_fmt,
> + .set_fmt = imx283_set_pad_format,
> + .get_selection = imx283_get_selection,
> + .enum_frame_size = imx283_enum_frame_size,
> + .enable_streams = imx283_enable_streams,
> + .disable_streams = imx283_disable_streams,
> +};
> +
> +static const struct v4l2_subdev_internal_ops imx283_internal_ops = {
> + .init_state = imx283_init_state,
> +};
> +
> +static const struct v4l2_subdev_ops imx283_subdev_ops = {
> + .core = &imx283_core_ops,
> + .video = &imx283_video_ops,
> + .pad = &imx283_pad_ops,
> +};
> +
> +/* Initialize control handlers */
> +static int imx283_init_controls(struct imx283 *imx283)
> +{
> + struct v4l2_ctrl_handler *ctrl_hdlr;
> + struct v4l2_fwnode_device_properties props;
> + struct v4l2_ctrl *link_freq;
> + const struct imx283_mode *mode = &supported_modes_12bit[0];
> + u64 min_hblank, max_hblank, def_hblank;
> + u64 pixel_rate;
> + int ret;
> +
> + ctrl_hdlr = &imx283->ctrl_handler;
> + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 16);
> + if (ret)
> + return ret;
> +
> + /*
> + * Create the controls here, but mode specific limits are setup
> + * in the imx283_set_framing_limits() call below.
> + */
> +
> + /* By default, PIXEL_RATE is read only */
> + pixel_rate = imx283_pixel_rate(imx283, mode);
> + v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,
> + V4L2_CID_PIXEL_RATE, pixel_rate,
> + pixel_rate, 1, pixel_rate);
> +
> + link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx283_ctrl_ops,
> + V4L2_CID_LINK_FREQ,
> + __fls(imx283->link_freq_bitmap),
> + __ffs(imx283->link_freq_bitmap),
> + link_frequencies);
> + if (link_freq)
> + link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
> +
> + /* Initialise vblank/hblank/exposure based on the current mode. */
> + imx283->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,
> + V4L2_CID_VBLANK,
> + mode->min_vmax - mode->height,
> + IMX283_VMAX_MAX, 1,
> + mode->default_vmax - mode->height);
> +
> + min_hblank = mode->min_hmax - mode->width;
> + max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width;
> + def_hblank = mode->default_hmax - mode->width;
> + imx283->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,
> + V4L2_CID_HBLANK, min_hblank, max_hblank,
> + 1, def_hblank);
> +
> + imx283->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,
> + V4L2_CID_EXPOSURE,
> + IMX283_EXPOSURE_MIN,
> + IMX283_EXPOSURE_MAX,
> + IMX283_EXPOSURE_STEP,
> + IMX283_EXPOSURE_DEFAULT);
> +
> + v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
> + IMX283_ANA_GAIN_MIN, IMX283_ANA_GAIN_MAX,
> + IMX283_ANA_GAIN_STEP, IMX283_ANA_GAIN_DEFAULT);
> +
> + v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
> + IMX283_DGTL_GAIN_MIN, IMX283_DGTL_GAIN_MAX,
> + IMX283_DGTL_GAIN_STEP, IMX283_DGTL_GAIN_DEFAULT);
> +
> + imx283->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_VFLIP,
> + 0, 1, 1, 0);
> + if (imx283->vflip)
> + imx283->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
> +
> + v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx283_ctrl_ops,
> + V4L2_CID_TEST_PATTERN,
> + ARRAY_SIZE(imx283_tpg_menu) - 1,
> + 0, 0, imx283_tpg_menu);
> +
> + if (ctrl_hdlr->error) {
> + ret = ctrl_hdlr->error;
> + dev_err(imx283->dev, "control init failed (%d)\n", ret);
> + goto error;
> + }
> +
> + ret = v4l2_fwnode_device_parse(imx283->dev, &props);
> + if (ret)
> + goto error;
> +
> + ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx283_ctrl_ops,
> + &props);
> + if (ret)
> + goto error;
> +
> + imx283->sd.ctrl_handler = ctrl_hdlr;
> +
> + mutex_lock(imx283->ctrl_handler.lock);
> +
> + /* Setup exposure and frame/line length limits. */
> + imx283_set_framing_limits(imx283, mode);
> +
> + mutex_unlock(imx283->ctrl_handler.lock);
> +
> + return 0;
> +
> +error:
> + v4l2_ctrl_handler_free(ctrl_hdlr);
> +
> + return ret;
> +}
> +
> +static int imx283_parse_endpoint(struct imx283 *imx283)
> +{
> + struct fwnode_handle *fwnode;
> + struct v4l2_fwnode_endpoint bus_cfg = {
> + .bus_type = V4L2_MBUS_CSI2_DPHY
> + };
> + struct fwnode_handle *ep;
> + int ret;
> +
> + fwnode = dev_fwnode(imx283->dev);
> + ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
> + if (!ep) {
> + dev_err(imx283->dev, "Failed to get next endpoint\n");
> + return -ENXIO;
> + }
> +
> + ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
> + fwnode_handle_put(ep);
> + if (ret)
> + return ret;
> +
> + if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) {
> + dev_err(imx283->dev,
> + "number of CSI2 data lanes %d is not supported\n",
> + bus_cfg.bus.mipi_csi2.num_data_lanes);
> + ret = -EINVAL;
> + goto done_endpoint_free;
> + }
> +
> + ret = v4l2_link_freq_to_bitmap(imx283->dev, bus_cfg.link_frequencies,
> + bus_cfg.nr_of_link_frequencies,
> + link_frequencies, ARRAY_SIZE(link_frequencies),
> + &imx283->link_freq_bitmap);
> +
> +done_endpoint_free:
> + v4l2_fwnode_endpoint_free(&bus_cfg);
> +
> + return ret;
> +};
> +
> +static int imx283_probe(struct i2c_client *client)
> +{
> + struct imx283 *imx283;
> + unsigned int i;
> + unsigned int xclk_freq;
> + int ret;
> +
> + imx283 = devm_kzalloc(&client->dev, sizeof(*imx283), GFP_KERNEL);
> + if (!imx283)
> + return -ENOMEM;
> +
> + imx283->dev = &client->dev;
> +
> + v4l2_i2c_subdev_init(&imx283->sd, client, &imx283_subdev_ops);
> +
> + imx283->cci = devm_cci_regmap_init_i2c(client, 16);
> + if (IS_ERR(imx283->cci)) {
> + ret = PTR_ERR(imx283->cci);
> + dev_err(imx283->dev, "failed to initialize CCI: %d\n", ret);
> + return ret;
> + }
> +
> + /* Get system clock (xclk) */
> + imx283->xclk = devm_clk_get(imx283->dev, NULL);
> + if (IS_ERR(imx283->xclk)) {
> + return dev_err_probe(imx283->dev, PTR_ERR(imx283->xclk),
> + "failed to get xclk\n");
> + }
> +
> + xclk_freq = clk_get_rate(imx283->xclk);
> + for (i = 0; i < ARRAY_SIZE(imx283_frequencies); i++) {
> + if (xclk_freq == imx283_frequencies[i].mhz) {
> + imx283->freq = &imx283_frequencies[i];
> + break;
> + }
> + }
> + if (!imx283->freq) {
> + dev_err(imx283->dev, "xclk frequency unsupported: %d Hz\n", xclk_freq);
> + return -EINVAL;
> + }
> +
> + ret = imx283_get_regulators(imx283);
> + if (ret) {
> + return dev_err_probe(imx283->dev, ret,
> + "failed to get regulators\n");
> + }
> +
> + ret = imx283_parse_endpoint(imx283);
> + if (ret) {
> + dev_err(imx283->dev, "failed to parse endpoint configuration\n");
> + return ret;
> + }
> +
> + /* Request optional enable pin */
> + imx283->reset_gpio = devm_gpiod_get_optional(imx283->dev, "reset",
> + GPIOD_OUT_LOW);
> + if (IS_ERR(imx283->reset_gpio))
> + return dev_err_probe(imx283->dev, PTR_ERR(imx283->reset_gpio),
> + "failed to get reset GPIO\n");
> +
> + /*
> + * The sensor must be powered for imx283_identify_module()
> + * to be able to read the CHIP_ID register
> + */
> + ret = imx283_power_on(imx283);
> + if (ret)
> + return ret;
> +
> + ret = imx283_identify_module(imx283);
> + if (ret)
> + goto error_power_off;
> +
> + /*
> + * Enable runtime PM with autosuspend. As the device has been powered
> + * manually, mark it as active, and increase the usage count without
> + * resuming the device.
> + */
> + pm_runtime_set_active(imx283->dev);
> + pm_runtime_get_noresume(imx283->dev);
> + pm_runtime_enable(imx283->dev);
> + pm_runtime_set_autosuspend_delay(imx283->dev, 1000);
> + pm_runtime_use_autosuspend(imx283->dev);
> +
> + /* This needs the pm runtime to be registered. */
> + ret = imx283_init_controls(imx283);
> + if (ret)
> + goto error_pm;
> +
> + /* Initialize subdev */
> + imx283->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
> + V4L2_SUBDEV_FL_HAS_EVENTS;
> + imx283->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
> + imx283->sd.internal_ops = &imx283_internal_ops;
> +
> + /* Initialize source pads */
> + imx283->pad.flags = MEDIA_PAD_FL_SOURCE;
> +
> + ret = media_entity_pads_init(&imx283->sd.entity, 1, &imx283->pad);
> + if (ret) {
> + dev_err(imx283->dev, "failed to init entity pads: %d\n", ret);
> + goto error_handler_free;
> + }
> +
> + imx283->sd.state_lock = imx283->ctrl_handler.lock;
> + ret = v4l2_subdev_init_finalize(&imx283->sd);
> + if (ret < 0) {
> + dev_err(imx283->dev, "subdev init error: %d\n", ret);
> + goto error_media_entity;
> + }
> +
> + ret = v4l2_async_register_subdev_sensor(&imx283->sd);
> + if (ret < 0) {
> + dev_err(imx283->dev, "failed to register sensor sub-device: %d\n", ret);
> + goto error_subdev_cleanup;
> + }
> +
> + /*
> + * Decrease the PM usage count. The device will get suspended after the
> + * autosuspend delay, turning the power off.
> + */
> + pm_runtime_mark_last_busy(imx283->dev);
> + pm_runtime_put_autosuspend(imx283->dev);
> +
> + return 0;
> +
> +error_subdev_cleanup:
> + v4l2_subdev_cleanup(&imx283->sd);
> +
> +error_media_entity:
> + media_entity_cleanup(&imx283->sd.entity);
> +
> +error_handler_free:
> + v4l2_ctrl_handler_free(imx283->sd.ctrl_handler);
> +
> +error_pm:
> + pm_runtime_disable(imx283->dev);
> + pm_runtime_set_suspended(imx283->dev);
> +error_power_off:
> + imx283_power_off(imx283);
> +
> + return ret;
> +}
> +
> +static void imx283_remove(struct i2c_client *client)
> +{
> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> + struct imx283 *imx283 = to_imx283(sd);
> +
> + v4l2_async_unregister_subdev(sd);
> + v4l2_subdev_cleanup(&imx283->sd);
> + media_entity_cleanup(&sd->entity);
> + v4l2_ctrl_handler_free(imx283->sd.ctrl_handler);
> +
> + pm_runtime_disable(imx283->dev);
> + if (!pm_runtime_status_suspended(imx283->dev))
> + imx283_power_off(imx283);
> + pm_runtime_set_suspended(imx283->dev);
> +}
> +
> +static DEFINE_RUNTIME_DEV_PM_OPS(imx283_pm_ops, imx283_runtime_suspend,
> + imx283_runtime_resume, NULL);
> +
> +static const struct of_device_id imx283_dt_ids[] = {
> + { .compatible = "sony,imx283" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, imx283_dt_ids);
> +
> +static struct i2c_driver imx283_i2c_driver = {
> + .driver = {
> + .name = "imx283",
> + .pm = pm_ptr(&imx283_pm_ops),
> + .of_match_table = imx283_dt_ids,
> + },
> + .probe = imx283_probe,
> + .remove = imx283_remove,
> +};
> +module_i2c_driver(imx283_i2c_driver);
> +
> +MODULE_AUTHOR("Will Whang <will@willwhang.com>");
> +MODULE_AUTHOR("Kieran Bingham <kieran.bingham@ideasonboard.com>");
> +MODULE_AUTHOR("Umang Jain <umang.jain@ideasonboard.com>");
> +MODULE_DESCRIPTION("Sony IMX283 Sensor Driver");
> +MODULE_LICENSE("GPL");
>
^ permalink raw reply
* Re: [PATCH v6 08/11] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
From: Conor Dooley @ 2024-04-02 12:56 UTC (permalink / raw)
To: Linus Walleij
Cc: Yangyu Chen, linux-riscv, Conor Dooley, Damien Le Moal,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Michael Turquette, Stephen Boyd,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
In-Reply-To: <CACRpkdY1wpGM7M5QV5rN0M6JMN_yugQJ7CEtnQjzsheD5AT23A@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1453 bytes --]
On Tue, Apr 02, 2024 at 02:31:36PM +0200, Linus Walleij wrote:
> On Sat, Mar 23, 2024 at 1:13 PM Yangyu Chen <cyy@cyyself.name> wrote:
>
> > Since SOC_FOO should be deprecated from patch [1], and cleanup for other
> > SoCs is already on the mailing list [2,3,4], we remove the use of
> > SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
> >
> > Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
> > when it has the symbol SOC_CANAAN_K210.
> >
> > [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
> > [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
> > [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
> > [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
> >
> > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Is this patch something I can just apply to the pinctrl tree?
The new symbol doesn't exist in the pinctrl tree, so the driver will
cease to be compilable. Yangyu sent a standalone version of these symbol
changes:
https://lore.kernel.org/all/tencent_DB11214C8D0D7C48829ADA128E7BB8F13108@qq.com/
That whole series needs to go through one tree though, for the same reason.
If your ack transfers to that (identical patch) I can take the whole lot
via the soc tree for v6.10.
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^ permalink raw reply
* Re: [PATCH v6 3/4] firmware: arm_scmi: Add SCMI v3.2 pincontrol protocol basic support
From: Andy Shevchenko @ 2024-04-02 13:06 UTC (permalink / raw)
To: Cristian Marussi
Cc: Peng Fan, Peng Fan (OSS), Sudeep Holla, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij, Dan Carpenter,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Oleksii Moisieiev
In-Reply-To: <Zgu4Tok43W5t8KM0@pluto>
On Tue, Apr 2, 2024 at 10:48 AM Cristian Marussi
<cristian.marussi@arm.com> wrote:
> On Sun, Mar 31, 2024 at 01:44:28PM +0000, Peng Fan wrote:
> > > Sat, Mar 23, 2024 at 08:15:16PM +0800, Peng Fan (OSS) kirjoitti:
...
> > > > +#include <linux/module.h>
> > > > +#include <linux/scmi_protocol.h>
> > > > +#include <linux/slab.h>
> > >
> > > This is semi-random list of headers. Please, follow IWYU principle (include
> > > what you use). There are a lot of inclusions I see missing (just in the context of
> > > this page I see bits.h, types.h, and asm/byteorder.h).
> >
> > Is there any documentation about this requirement?
> > Some headers are already included by others.
The documentation here is called "a common sense".
The C language is built like this and we expect that nobody will
invest into the dependency hell that we have already, that's why IWYU
principle, please follow it.
> Andy made (mostly) the same remarks on this same patch ~1-year ago on
> this same patch while it was posted by Oleksii.
>
> And I told that time that most of the remarks around devm_ usage were
> wrong due to how the SCMI core handles protocol initialization (using a
> devres group transparently).
>
> This is what I answered that time.
>
> https://lore.kernel.org/linux-arm-kernel/ZJ78hBcjAhiU+ZBO@e120937-lin/#t
>
> I wont repeat myself, but, in a nutshell the memory allocation like it
> is now is fine: a bit happens via devm_ at protocol initialization, the
> other is doe via explicit kmalloc at runtime and freed via kfree at
> remove time (if needed...i.e. checking the present flag of some structs)
This sounds like a mess. devm_ is expected to be used only for the
->probe() stage, otherwise you may consider cleanup.h (__free() macro)
to have automatic free at the paths where memory is not needed.
And the function naming doesn't suggest that you have a probe-remove
pair. Moreover, if the init-deinit part is called in the probe-remove,
the devm_ must not be mixed with non-devm ones, as it breaks the order
and leads to subtle mistakes.
> I'll made further remarks on v7 that you just posted.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* [RFC PATCH 0/6] Support ROHM BD96801 scalable PMIC
From: Matti Vaittinen @ 2024-04-02 13:07 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Liam Girdwood, Mark Brown, Matti Vaittinen, Wim Van Sebroeck,
Guenter Roeck, devicetree, linux-kernel, linux-watchdog
[-- Attachment #1: Type: text/plain, Size: 3578 bytes --]
Support ROHM BD96801 "scalable" PMIC.
The ROHM BD96801 is automotive grade PMIC, intended to be usable in
multiple solutions. The BD96801 can be used as a stand-alone, or together
with separate 'companion PMICs'. This modular approach aims to make this
PMIC suitable for various use-cases.
This RFC series is a product of a _long_ process. The product has been
re-designed a few times and this series has been sitting in my git
forgotten for long periods of time, then been re-worked when new design
has been available, after which it has again been forgotten. Last week I
finally received the word that this product should've been stabilized,
digged up my last set of patches (from Nov 2021 - cover letter
reminding me the driver development had been done during 3 years...)
I think this is valid information for reviewers as it's good to keep an
eye on obsoleted practices - even though I tried updating this series.
This is sent as an RFC because of the regulator features which can be
configured only when the PMIC is in STBY state. This is described more
detailed in the regulator patch.
Another "oddity" is that the PMIC has two physical IRQ lines. When I
last wrote this patch in 2021 I had some naming collison in debugfs for
the IRQ domains. Back then I used:
irq_domain_update_bus_token(intb_domain, DOMAIN_BUS_WIRED);
to work-around the issue. Now, when rebasing to v6.9-rc1 the naming
collision was gone and things seemed to work. However, it'd be great if
the IRQ code in MFD driver was reviewed by greater minds :)
Rest of the series ought to be business as usual.
Matti Vaittinen (6):
dt-bindings: ROHM BD96801 PMIC regulators
dt-bindings: mfd: bd96801 PMIC core
mfd: support ROHM BD96801 PMIC core
regulator: bd96801: ROHM BD96801 PMIC regulators
watchdog: ROHM BD96801 PMIC WDG driver
MAINTAINERS: Add ROHM BD96801 'scalable PMIC' entries
.../bindings/mfd/rohm,bd96801-pmic.yaml | 155 ++
.../regulator/rohm,bd96801-regulator.yaml | 69 +
MAINTAINERS | 4 +
drivers/mfd/Kconfig | 13 +
drivers/mfd/Makefile | 1 +
drivers/mfd/rohm-bd96801.c | 454 ++++
drivers/regulator/Kconfig | 12 +
drivers/regulator/Makefile | 2 +
drivers/regulator/bd96801-regulator.c | 2109 +++++++++++++++++
drivers/watchdog/Kconfig | 13 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/bd96801_wdt.c | 375 +++
include/linux/mfd/rohm-bd96801.h | 212 ++
include/linux/mfd/rohm-generic.h | 1 +
14 files changed, 3421 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml
create mode 100644 Documentation/devicetree/bindings/regulator/rohm,bd96801-regulator.yaml
create mode 100644 drivers/mfd/rohm-bd96801.c
create mode 100644 drivers/regulator/bd96801-regulator.c
create mode 100644 drivers/watchdog/bd96801_wdt.c
create mode 100644 include/linux/mfd/rohm-bd96801.h
base-commit: 4cece764965020c22cff7665b18a012006359095
--
2.43.2
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* [RFC PATCH 1/6] dt-bindings: ROHM BD96801 PMIC regulators
From: Matti Vaittinen @ 2024-04-02 13:07 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Liam Girdwood, Mark Brown, Matti Vaittinen, Wim Van Sebroeck,
Guenter Roeck, devicetree, linux-kernel, linux-watchdog
In-Reply-To: <cover.1712058690.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 3313 bytes --]
ROHM BD96801 is a highly configurable automotive grade PMIC. Introduce
DT bindings for the BD96801 regulators.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
---
.../regulator/rohm,bd96801-regulator.yaml | 69 +++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/regulator/rohm,bd96801-regulator.yaml
diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd96801-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd96801-regulator.yaml
new file mode 100644
index 000000000000..4015802a3d84
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/rohm,bd96801-regulator.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/rohm,bd96801-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD96801 Power Management Integrated Circuit regulators
+
+maintainers:
+ - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+
+description: |
+ This module is part of the ROHM BD96801 MFD device. For more details
+ see Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml.
+
+ The regulator controller is represented as a sub-node of the PMIC node
+ on the device tree.
+
+ Regulator nodes should be named to BUCK_<number> and LDO_<number>.
+ The valid names for BD96801 regulator nodes are
+ BUCK1, BUCK2, BUCK3, BUCK4, LDO5, LDO6, LDO7
+
+patternProperties:
+ "^LDO[5-7]$":
+ type: object
+ description:
+ Properties for single LDO regulator.
+ $ref: regulator.yaml#
+
+ properties:
+ regulator-name:
+ pattern: "^ldo[5-7]$"
+ description:
+ Name of the regulator. Should be "ldo5", ..., "ldo7"
+ rohm,initial-voltage-microvolt:
+ description:
+ Initial voltage for regulator. Voltage can be tuned +/-150 mV from
+ this value. NOTE, This can be modified via I2C only when PMIC is in
+ STBY state.
+ minimum: 300000
+ maximum: 3300000
+
+ "^BUCK[1-4]$":
+ type: object
+ description:
+ Properties for single BUCK regulator.
+ $ref: regulator.yaml#
+
+ properties:
+ regulator-name:
+ pattern: "^buck[1-4]$"
+ description:
+ should be "buck1", ..., "buck4"
+ rohm,initial-voltage-microvolt:
+ description:
+ Initial voltage for regulator. Voltage can be tuned +/-150 mV from
+ this value. NOTE, This can be modified via I2C only when PMIC is in
+ STBY state.
+ minimum: 500000
+ maximum: 3300000
+ rohm,keep-on-stby:
+ description:
+ Keep the regulator powered when PMIC transitions to STBY state.
+ type: boolean
+
+ required:
+ - regulator-name
+ additionalProperties: false
+additionalProperties: false
--
2.43.2
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [RFC PATCH 2/6] dt-bindings: mfd: bd96801 PMIC core
From: Matti Vaittinen @ 2024-04-02 13:08 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Liam Girdwood, Mark Brown, Matti Vaittinen, Wim Van Sebroeck,
Guenter Roeck, devicetree, linux-kernel, linux-watchdog
In-Reply-To: <cover.1712058690.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 7075 bytes --]
ROHM BD96801 is a highly configurable automotive grade PMIC. Introduce
DT bindings for the BD96801 core.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
---
.../bindings/mfd/rohm,bd96801-pmic.yaml | 155 ++++++++++++++++++
1 file changed, 155 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml
diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml
new file mode 100644
index 000000000000..0d512fe19081
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/rohm,bd96801-pmic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD96801 Scalable Power Management Integrated Circuit
+
+maintainers:
+ - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+
+description: |
+ BD96801 is an automotive grade single-chip power management IC.
+ It integrates 4 buck converters and 3 LDOs with safety features like
+ over-/under voltage and over current detection and a watchdog.
+
+properties:
+ compatible:
+ const: rohm,bd96801
+
+ reg:
+ description:
+ I2C slave address.
+ maxItems: 1
+
+ interrupts:
+ description:
+ The PMIC provides intb and errb IRQ lines. The errb IRQ line is used
+ for fatal IRQs which will cause the PMIC to shut down power outputs.
+ In many systems this will shut down the SoC contolling the PMIC and
+ connecting/handling the errb can be omitted. However, there are cases
+ where the SoC is not powered by the PMIC. In that case it may be
+ useful to connect the errb and handle errb events.
+ minItems: 1
+ maxItems: 2
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - enum: [intb, errb]
+ - const: errb
+
+ regulators:
+ $ref: ../regulator/rohm,bd96801-regulator.yaml
+ description:
+ List of child nodes that specify the regulators.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - regulators
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/leds/common.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic: pmic@60 {
+ reg = <0x60>;
+ compatible = "rohm,bd96801";
+ interrupt-parent = <&gpio1>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>, <6 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "intb", "errb";
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "buck1";
+ regulator-ramp-delay = <1250>;
+ /* 0.5V min INITIAL - 150 mV tune */
+ regulator-min-microvolt = <350000>;
+ /* 3.3V + 150mV tune */
+ regulator-max-microvolt = <3450000>;
+
+ /* These can be set only when PMIC is in STBY */
+ rohm,initial-voltage-microvolt = <500000>;
+ regulator-ov-error-microvolt = <230000>;
+ regulator-uv-error-microvolt = <230000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-warn-kelvin = <0>;
+ };
+ buck2: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <350000>;
+ regulator-max-microvolt = <3450000>;
+
+ rohm,initial-voltage-microvolt = <3000000>;
+ regulator-ov-error-microvolt = <18000>;
+ regulator-uv-error-microvolt = <18000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-warn-kelvin = <1>;
+ };
+ buck3: BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <350000>;
+ regulator-max-microvolt = <3450000>;
+
+ rohm,initial-voltage-microvolt = <600000>;
+ regulator-ov-warn-microvolt = <18000>;
+ regulator-uv-warn-microvolt = <18000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-error-kelvin = <0>;
+ };
+ buck4: BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <350000>;
+ regulator-max-microvolt = <3450000>;
+
+ rohm,initial-voltage-microvolt = <600000>;
+ regulator-ov-warn-microvolt = <18000>;
+ regulator-uv-warn-microvolt = <18000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-error-kelvin = <0>;
+ };
+ ldo5: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <3300000>;
+
+ rohm,initial-voltage-microvolt = <500000>;
+ regulator-ov-error-microvolt = <36000>;
+ regulator-uv-error-microvolt = <34000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-warn-kelvin = <0>;
+ };
+ ldo6: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <3300000>;
+
+ rohm,initial-voltage-microvolt = <300000>;
+ regulator-ov-error-microvolt = <36000>;
+ regulator-uv-error-microvolt = <34000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-warn-kelvin = <0>;
+ };
+ ldo7: LDO7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <3300000>;
+
+ rohm,initial-voltage-microvolt = <500000>;
+ regulator-ov-error-microvolt = <36000>;
+ regulator-uv-error-microvolt = <34000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-warn-kelvin = <0>;
+ };
+ };
+ };
+ };
--
2.43.2
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [RFC PATCH 3/6] mfd: support ROHM BD96801 PMIC core
From: Matti Vaittinen @ 2024-04-02 13:08 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Liam Girdwood, Mark Brown, Matti Vaittinen, Wim Van Sebroeck,
Guenter Roeck, devicetree, linux-kernel, linux-watchdog
In-Reply-To: <cover.1712058690.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 30339 bytes --]
The ROHM BD96801 PMIC is highly customizable automotive grade PMIC
which integrates regulator and watchdog funtionalities.
Provide IRQ and register accesses for regulator/watchdog drivers.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
---
drivers/mfd/Kconfig | 13 +
drivers/mfd/Makefile | 1 +
drivers/mfd/rohm-bd96801.c | 454 +++++++++++++++++++++++++++++++
include/linux/mfd/rohm-bd96801.h | 212 +++++++++++++++
include/linux/mfd/rohm-generic.h | 1 +
5 files changed, 681 insertions(+)
create mode 100644 drivers/mfd/rohm-bd96801.c
create mode 100644 include/linux/mfd/rohm-bd96801.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4b023ee229cf..947045eb3a8e 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -2089,6 +2089,19 @@ config MFD_ROHM_BD957XMUF
BD9573MUF Power Management ICs. BD9576 and BD9573 are primarily
designed to be used to power R-Car series processors.
+config MFD_ROHM_BD96801
+ tristate "ROHM BD96801 Power Management IC"
+ depends on I2C=y
+ depends on OF
+ select REGMAP_I2C
+ select REGMAP_IRQ
+ select MFD_CORE
+ help
+ Select this option to get support for the ROHM BD96801 Power
+ Management IC. The ROHM BD96801 is a highly scalable power management
+ IC for industrial and automotive use. The BD96801 can be used as a
+ master PMIC in a chained PMIC solutions with suitable companion PMICs.
+
config MFD_STM32_LPTIMER
tristate "Support for STM32 Low-Power Timer"
depends on (ARCH_STM32 && OF) || COMPILE_TEST
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index c66f07edcd0e..e792892d4a8b 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -264,6 +264,7 @@ obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o
obj-$(CONFIG_MFD_ROHM_BD71828) += rohm-bd71828.o
obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o
obj-$(CONFIG_MFD_ROHM_BD957XMUF) += rohm-bd9576.o
+obj-$(CONFIG_MFD_ROHM_BD96801) += rohm-bd96801.o
obj-$(CONFIG_MFD_STMFX) += stmfx.o
obj-$(CONFIG_MFD_KHADAS_MCU) += khadas-mcu.o
obj-$(CONFIG_MFD_ACER_A500_EC) += acer-ec-a500.o
diff --git a/drivers/mfd/rohm-bd96801.c b/drivers/mfd/rohm-bd96801.c
new file mode 100644
index 000000000000..7610d0114653
--- /dev/null
+++ b/drivers/mfd/rohm-bd96801.c
@@ -0,0 +1,454 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (C) 2022 ROHM Semiconductors
+//
+// ROHM BD96801 PMIC driver
+
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#include <linux/mfd/rohm-bd96801.h>
+#include <linux/mfd/rohm-generic.h>
+
+static const struct resource regulator_errb_irqs[] = {
+ DEFINE_RES_IRQ_NAMED(BD96801_OTP_ERR_STAT, "bd96801-otp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_DBIST_ERR_STAT, "bd96801-dbist-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_EEP_ERR_STAT, "bd96801-eep-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_ABIST_ERR_STAT, "bd96801-abist-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_PRSTB_ERR_STAT, "bd96801-prstb-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_DRMOS1_ERR_STAT, "bd96801-drmoserr1"),
+ DEFINE_RES_IRQ_NAMED(BD96801_DRMOS2_ERR_STAT, "bd96801-drmoserr2"),
+ DEFINE_RES_IRQ_NAMED(BD96801_SLAVE_ERR_STAT, "bd96801-slave-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_VREF_ERR_STAT, "bd96801-vref-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_TSD_ERR_STAT, "bd96801-tsd"),
+ DEFINE_RES_IRQ_NAMED(BD96801_UVLO_ERR_STAT, "bd96801-uvlo-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_OVLO_ERR_STAT, "bd96801-ovlo-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_OSC_ERR_STAT, "bd96801-osc-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_PON_ERR_STAT, "bd96801-pon-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_POFF_ERR_STAT, "bd96801-poff-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_CMD_SHDN_ERR_STAT, "bd96801-cmd-shdn-err"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_INT_PRSTB_WDT_ERR, "bd96801-prstb-wdt-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_INT_CHIP_IF_ERR, "bd96801-chip-if-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_INT_SHDN_ERR_STAT, "bd96801-int-shdn-err"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_PVIN_ERR_STAT, "bd96801-buck1-pvin-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVP_ERR_STAT, "bd96801-buck1-ovp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVP_ERR_STAT, "bd96801-buck1-uvp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_SHDN_ERR_STAT, "bd96801-buck1-shdn-err"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_PVIN_ERR_STAT, "bd96801-buck2-pvin-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVP_ERR_STAT, "bd96801-buck2-ovp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVP_ERR_STAT, "bd96801-buck2-uvp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_SHDN_ERR_STAT, "bd96801-buck2-shdn-err"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_PVIN_ERR_STAT, "bd96801-buck3-pvin-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVP_ERR_STAT, "bd96801-buck3-ovp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVP_ERR_STAT, "bd96801-buck3-uvp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_SHDN_ERR_STAT, "bd96801-buck3-shdn-err"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_PVIN_ERR_STAT, "bd96801-buck4-pvin-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVP_ERR_STAT, "bd96801-buck4-ovp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVP_ERR_STAT, "bd96801-buck4-uvp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_SHDN_ERR_STAT, "bd96801-buck4-shdn-err"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO5_PVIN_ERR_STAT, "bd96801-ldo5-pvin-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVP_ERR_STAT, "bd96801-ldo5-ovp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVP_ERR_STAT, "bd96801-ldo5-uvp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO5_SHDN_ERR_STAT, "bd96801-ldo5-shdn-err"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO6_PVIN_ERR_STAT, "bd96801-ldo6-pvin-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVP_ERR_STAT, "bd96801-ldo6-ovp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVP_ERR_STAT, "bd96801-ldo6-uvp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO6_SHDN_ERR_STAT, "bd96801-ldo6-shdn-err"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO7_PVIN_ERR_STAT, "bd96801-ldo7-pvin-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVP_ERR_STAT, "bd96801-ldo7-ovp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVP_ERR_STAT, "bd96801-ldo7-uvp-err"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "bd96801-ldo7-shdn-err"),
+};
+
+static const struct resource regulator_intb_irqs[] = {
+ DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "bd96801-core-thermal"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPH_STAT, "bd96801-buck1-overcurr-h"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPL_STAT, "bd96801-buck1-overcurr-l"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPN_STAT, "bd96801-buck1-overcurr-n"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVD_STAT, "bd96801-buck1-overvolt"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVD_STAT, "bd96801-buck1-undervolt"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_TW_CH_STAT, "bd96801-buck1-thermal"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPH_STAT, "bd96801-buck2-overcurr-h"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPL_STAT, "bd96801-buck2-overcurr-l"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPN_STAT, "bd96801-buck2-overcurr-n"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVD_STAT, "bd96801-buck2-overvolt"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVD_STAT, "bd96801-buck2-undervolt"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_TW_CH_STAT, "bd96801-buck2-thermal"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPH_STAT, "bd96801-buck3-overcurr-h"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPL_STAT, "bd96801-buck3-overcurr-l"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPN_STAT, "bd96801-buck3-overcurr-n"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVD_STAT, "bd96801-buck3-overvolt"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVD_STAT, "bd96801-buck3-undervolt"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_TW_CH_STAT, "bd96801-buck3-thermal"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPH_STAT, "bd96801-buck4-overcurr-h"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPL_STAT, "bd96801-buck4-overcurr-l"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPN_STAT, "bd96801-buck4-overcurr-n"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVD_STAT, "bd96801-buck4-overvolt"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVD_STAT, "bd96801-buck4-undervolt"),
+ DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_TW_CH_STAT, "bd96801-buck4-thermal"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OCPH_STAT, "bd96801-ldo5-overcurr"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVD_STAT, "bd96801-ldo5-overvolt"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVD_STAT, "bd96801-ldo5-undervolt"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OCPH_STAT, "bd96801-ldo6-overcurr"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVD_STAT, "bd96801-ldo6-overvolt"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVD_STAT, "bd96801-ldo6-undervolt"),
+
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OCPH_STAT, "bd96801-ldo7-overcurr"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVD_STAT, "bd96801-ldo7-overvolt"),
+ DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "bd96801-ldo7-undervolt"),
+};
+
+enum {
+ WDG_CELL = 0,
+ REGULATOR_CELL,
+};
+
+static struct mfd_cell bd96801_mfd_cells[] = {
+ [WDG_CELL] = { .name = "bd96801-wdt", },
+ [REGULATOR_CELL] = { .name = "bd96801-pmic", },
+};
+
+static const struct regmap_range bd96801_volatile_ranges[] = {
+ /* Status regs */
+ regmap_reg_range(BD96801_REG_WD_FEED, BD96801_REG_WD_FAILCOUNT),
+ regmap_reg_range(BD96801_REG_WD_ASK, BD96801_REG_WD_ASK),
+ regmap_reg_range(BD96801_REG_WD_STATUS, BD96801_REG_WD_STATUS),
+ regmap_reg_range(BD96801_REG_PMIC_STATE, BD96801_REG_INT_LDO7_INTB),
+ /* Registers which do not update value unless PMIC is in STBY */
+ regmap_reg_range(BD96801_REG_SSCG_CTRL, BD96801_REG_SHD_INTB),
+ regmap_reg_range(BD96801_REG_BUCK_OVP, BD96801_REG_BOOT_OVERTIME),
+ /*
+ * LDO control registers have single bit (LDO MODE) which does not
+ * change when we write it unless PMIC is in STBY. It's safer to not
+ * cache it.
+ */
+ regmap_reg_range(BD96801_LDO5_VOL_LVL_REG, BD96801_LDO7_VOL_LVL_REG),
+};
+
+static const struct regmap_access_table volatile_regs = {
+ .yes_ranges = bd96801_volatile_ranges,
+ .n_yes_ranges = ARRAY_SIZE(bd96801_volatile_ranges),
+};
+
+/*
+ * For ERRB we need main register bit mapping as bit(0) indicates active IRQ
+ * in one of the first 3 sub IRQ registers, For INTB we can use default 1 to 1
+ * mapping.
+ */
+static unsigned int bit0_offsets[] = {0, 1, 2}; /* System stat, 3 registers */
+static unsigned int bit1_offsets[] = {3}; /* Buck 1 stat */
+static unsigned int bit2_offsets[] = {4}; /* Buck 2 stat */
+static unsigned int bit3_offsets[] = {5}; /* Buck 3 stat */
+static unsigned int bit4_offsets[] = {6}; /* Buck 4 stat */
+static unsigned int bit5_offsets[] = {7}; /* LDO 5 stat */
+static unsigned int bit6_offsets[] = {8}; /* LDO 6 stat */
+static unsigned int bit7_offsets[] = {9}; /* LDO 7 stat */
+
+static struct regmap_irq_sub_irq_map errb_sub_irq_offsets[] = {
+ REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
+};
+
+static const struct regmap_irq bd96801_errb_irqs[] = {
+ /* Reg 0x52 Fatal ERRB1 */
+ REGMAP_IRQ_REG(BD96801_OTP_ERR_STAT, 0, BD96801_OTP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_DBIST_ERR_STAT, 0, BD96801_DBIST_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_EEP_ERR_STAT, 0, BD96801_EEP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_ABIST_ERR_STAT, 0, BD96801_ABIST_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_PRSTB_ERR_STAT, 0, BD96801_PRSTB_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_DRMOS1_ERR_STAT, 0, BD96801_DRMOS1_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_DRMOS2_ERR_STAT, 0, BD96801_DRMOS2_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_SLAVE_ERR_STAT, 0, BD96801_SLAVE_ERR_MASK),
+ /* 0x53 Fatal ERRB2 */
+ REGMAP_IRQ_REG(BD96801_VREF_ERR_STAT, 1, BD96801_VREF_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_TSD_ERR_STAT, 1, BD96801_TSD_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_UVLO_ERR_STAT, 1, BD96801_UVLO_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_OVLO_ERR_STAT, 1, BD96801_OVLO_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_OSC_ERR_STAT, 1, BD96801_OSC_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_PON_ERR_STAT, 1, BD96801_PON_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_POFF_ERR_STAT, 1, BD96801_POFF_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_CMD_SHDN_ERR_STAT, 1, BD96801_CMD_SHDN_ERR_MASK),
+ /* 0x54 Fatal INTB shadowed to ERRB */
+ REGMAP_IRQ_REG(BD96801_INT_PRSTB_WDT_ERR, 2, BD96801_INT_PRSTB_WDT_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_INT_CHIP_IF_ERR, 2, BD96801_INT_CHIP_IF_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_INT_SHDN_ERR_STAT, 2, BD96801_INT_SHDN_ERR_MASK),
+ /* Reg 0x55 BUCK1 ERR IRQs */
+ REGMAP_IRQ_REG(BD96801_BUCK1_PVIN_ERR_STAT, 3, BD96801_OUT_PVIN_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK1_OVP_ERR_STAT, 3, BD96801_OUT_OVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK1_UVP_ERR_STAT, 3, BD96801_OUT_UVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK1_SHDN_ERR_STAT, 3, BD96801_OUT_SHDN_ERR_MASK),
+ /* Reg 0x56 BUCK2 ERR IRQs */
+ REGMAP_IRQ_REG(BD96801_BUCK2_PVIN_ERR_STAT, 4, BD96801_OUT_PVIN_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK2_OVP_ERR_STAT, 4, BD96801_OUT_OVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK2_UVP_ERR_STAT, 4, BD96801_OUT_UVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK2_SHDN_ERR_STAT, 4, BD96801_OUT_SHDN_ERR_MASK),
+ /* Reg 0x57 BUCK3 ERR IRQs */
+ REGMAP_IRQ_REG(BD96801_BUCK3_PVIN_ERR_STAT, 5, BD96801_OUT_PVIN_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK3_OVP_ERR_STAT, 5, BD96801_OUT_OVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK3_UVP_ERR_STAT, 5, BD96801_OUT_UVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK3_SHDN_ERR_STAT, 5, BD96801_OUT_SHDN_ERR_MASK),
+ /* Reg 0x58 BUCK4 ERR IRQs */
+ REGMAP_IRQ_REG(BD96801_BUCK4_PVIN_ERR_STAT, 6, BD96801_OUT_PVIN_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK4_OVP_ERR_STAT, 6, BD96801_OUT_OVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK4_UVP_ERR_STAT, 6, BD96801_OUT_UVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK4_SHDN_ERR_STAT, 6, BD96801_OUT_SHDN_ERR_MASK),
+ /* Reg 0x59 LDO5 ERR IRQs */
+ REGMAP_IRQ_REG(BD96801_LDO5_PVIN_ERR_STAT, 7, BD96801_OUT_PVIN_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO5_OVP_ERR_STAT, 7, BD96801_OUT_OVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO5_UVP_ERR_STAT, 7, BD96801_OUT_UVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO5_SHDN_ERR_STAT, 7, BD96801_OUT_SHDN_ERR_MASK),
+ /* Reg 0x5a LDO6 ERR IRQs */
+ REGMAP_IRQ_REG(BD96801_LDO6_PVIN_ERR_STAT, 8, BD96801_OUT_PVIN_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO6_OVP_ERR_STAT, 8, BD96801_OUT_OVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO6_UVP_ERR_STAT, 8, BD96801_OUT_UVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO6_SHDN_ERR_STAT, 8, BD96801_OUT_SHDN_ERR_MASK),
+ /* Reg 0x5b LDO7 ERR IRQs */
+ REGMAP_IRQ_REG(BD96801_LDO7_PVIN_ERR_STAT, 9, BD96801_OUT_PVIN_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO7_OVP_ERR_STAT, 9, BD96801_OUT_OVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO7_UVP_ERR_STAT, 9, BD96801_OUT_UVP_ERR_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO7_SHDN_ERR_STAT, 9, BD96801_OUT_SHDN_ERR_MASK),
+};
+
+static const struct regmap_irq bd96801_intb_irqs[] = {
+ /* STATUS SYSTEM INTB */
+ REGMAP_IRQ_REG(BD96801_TW_STAT, 0, BD96801_TW_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_WDT_ERR_STAT, 0, BD96801_WDT_ERR_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_I2C_ERR_STAT, 0, BD96801_I2C_ERR_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_CHIP_IF_ERR_STAT, 0, BD96801_CHIP_IF_ERR_STAT_MASK),
+ /* STATUS BUCK1 INTB */
+ REGMAP_IRQ_REG(BD96801_BUCK1_OCPH_STAT, 1, BD96801_BUCK_OCPH_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK1_OCPL_STAT, 1, BD96801_BUCK_OCPL_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK1_OCPN_STAT, 1, BD96801_BUCK_OCPN_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK1_OVD_STAT, 1, BD96801_BUCK_OVD_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK1_UVD_STAT, 1, BD96801_BUCK_UVD_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK1_TW_CH_STAT, 1, BD96801_BUCK_TW_CH_STAT_MASK),
+ /* BUCK 2 INTB */
+ REGMAP_IRQ_REG(BD96801_BUCK2_OCPH_STAT, 2, BD96801_BUCK_OCPH_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK2_OCPL_STAT, 2, BD96801_BUCK_OCPL_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK2_OCPN_STAT, 2, BD96801_BUCK_OCPN_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK2_OVD_STAT, 2, BD96801_BUCK_OVD_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK2_UVD_STAT, 2, BD96801_BUCK_UVD_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK2_TW_CH_STAT, 2, BD96801_BUCK_TW_CH_STAT_MASK),
+ /* BUCK 3 INTB */
+ REGMAP_IRQ_REG(BD96801_BUCK3_OCPH_STAT, 3, BD96801_BUCK_OCPH_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK3_OCPL_STAT, 3, BD96801_BUCK_OCPL_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK3_OCPN_STAT, 3, BD96801_BUCK_OCPN_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK3_OVD_STAT, 3, BD96801_BUCK_OVD_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK3_UVD_STAT, 3, BD96801_BUCK_UVD_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK3_TW_CH_STAT, 3, BD96801_BUCK_TW_CH_STAT_MASK),
+ /* BUCK 4 INTB */
+ REGMAP_IRQ_REG(BD96801_BUCK4_OCPH_STAT, 4, BD96801_BUCK_OCPH_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK4_OCPL_STAT, 4, BD96801_BUCK_OCPL_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK4_OCPN_STAT, 4, BD96801_BUCK_OCPN_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK4_OVD_STAT, 4, BD96801_BUCK_OVD_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK4_UVD_STAT, 4, BD96801_BUCK_UVD_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_BUCK4_TW_CH_STAT, 4, BD96801_BUCK_TW_CH_STAT_MASK),
+ /* LDO5 INTB */
+ REGMAP_IRQ_REG(BD96801_LDO5_OCPH_STAT, 5, BD96801_LDO_OCPH_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO5_OVD_STAT, 5, BD96801_LDO_OVD_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO5_UVD_STAT, 5, BD96801_LDO_UVD_STAT_MASK),
+ /* LDO6 INTB */
+ REGMAP_IRQ_REG(BD96801_LDO6_OCPH_STAT, 6, BD96801_LDO_OCPH_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO6_OVD_STAT, 6, BD96801_LDO_OVD_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO6_UVD_STAT, 6, BD96801_LDO_UVD_STAT_MASK),
+ /* LDO7 INTB */
+ REGMAP_IRQ_REG(BD96801_LDO7_OCPH_STAT, 7, BD96801_LDO_OCPH_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO7_OVD_STAT, 7, BD96801_LDO_OVD_STAT_MASK),
+ REGMAP_IRQ_REG(BD96801_LDO7_UVD_STAT, 7, BD96801_LDO_UVD_STAT_MASK),
+};
+
+static struct regmap_irq_chip bd96801_irq_chip_errb = {
+ .name = "bd96801-irq-errb",
+ .main_status = BD96801_REG_INT_MAIN,
+ .num_main_regs = 1,
+ .irqs = &bd96801_errb_irqs[0],
+ .num_irqs = ARRAY_SIZE(bd96801_errb_irqs),
+ .status_base = BD96801_REG_INT_SYS_ERRB1,
+ .mask_base = BD96801_REG_MASK_SYS_ERRB,
+ .ack_base = BD96801_REG_INT_SYS_ERRB1,
+ .init_ack_masked = true,
+ .num_regs = 10,
+ .irq_reg_stride = 1,
+ .sub_reg_offsets = &errb_sub_irq_offsets[0],
+};
+
+static struct regmap_irq_chip bd96801_irq_chip_intb = {
+ .name = "bd96801-irq-intb",
+ .main_status = BD96801_REG_INT_MAIN,
+ .num_main_regs = 1,
+ .irqs = &bd96801_intb_irqs[0],
+ .num_irqs = ARRAY_SIZE(bd96801_intb_irqs),
+ .status_base = BD96801_REG_INT_SYS_INTB,
+ .mask_base = BD96801_REG_MASK_SYS_INTB,
+ .ack_base = BD96801_REG_INT_SYS_INTB,
+ .init_ack_masked = true,
+ .num_regs = 8,
+ .irq_reg_stride = 1,
+};
+
+static const struct regmap_config bd96801_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .volatile_table = &volatile_regs,
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static int bd96801_i2c_probe(struct i2c_client *i2c)
+{
+ int i, ret, intb_irq, errb_irq, num_regu_irqs, num_intb, num_errb = 0;
+ struct regmap_irq_chip_data *intb_irq_data, *errb_irq_data;
+ struct irq_domain *intb_domain, *errb_domain;
+ const struct fwnode_handle *fwnode;
+ struct resource *regulator_res;
+ struct regmap *regmap;
+
+ fwnode = dev_fwnode(&i2c->dev);
+ if (!fwnode) {
+ dev_err(&i2c->dev, "no fwnode\n");
+ return -EINVAL;
+ }
+
+ intb_irq = fwnode_irq_get_byname(fwnode, "intb");
+ if (intb_irq < 0)
+ return dev_err_probe(&i2c->dev, intb_irq,
+ "No INTB IRQ configured\n");
+
+ num_intb = ARRAY_SIZE(regulator_intb_irqs);
+
+ /* ERRB may be omitted if processor is powered by the PMIC */
+ errb_irq = fwnode_irq_get_byname(fwnode, "errb");
+ if (errb_irq < 0)
+ errb_irq = 0;
+
+ if (errb_irq)
+ num_errb = ARRAY_SIZE(regulator_errb_irqs);
+
+ num_regu_irqs = num_intb + num_errb;
+
+ regulator_res = kcalloc(num_regu_irqs, sizeof(*regulator_res),
+ GFP_KERNEL);
+ if (!regulator_res)
+ return -ENOMEM;
+
+ regmap = devm_regmap_init_i2c(i2c, &bd96801_regmap_config);
+ if (IS_ERR(regmap)) {
+ ret = dev_err_probe(&i2c->dev, PTR_ERR(regmap),
+ "regmap initialization failed\n");
+ goto free_out;
+ }
+ ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, intb_irq,
+ IRQF_ONESHOT, 0, &bd96801_irq_chip_intb,
+ &intb_irq_data);
+ if (ret) {
+ dev_err_probe(&i2c->dev, ret, "Failed to add INTB irq_chip\n");
+ goto free_out;
+ }
+
+ /*
+ * MFD core code is built to handle only one IRQ domain. BD96801
+ * has two domains so we do IRQ mapping here and provide the
+ * already mapped IRQ numbers to sub-devices.
+ */
+ intb_domain = regmap_irq_get_domain(intb_irq_data);
+
+ for (i = 0; i < num_intb; i++) {
+ struct resource *res = ®ulator_res[i];
+
+ *res = regulator_intb_irqs[i];
+ res->start = res->end = irq_create_mapping(intb_domain,
+ res->start);
+ }
+
+ if (num_errb) {
+ ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, errb_irq,
+ IRQF_ONESHOT, 0,
+ &bd96801_irq_chip_errb,
+ &errb_irq_data);
+ if (ret) {
+ dev_err_probe(&i2c->dev, ret,
+ "Failed to add ERRB (%d) irq_chip\n",
+ errb_irq);
+ goto free_out;
+ }
+ errb_domain = regmap_irq_get_domain(errb_irq_data);
+
+ for (i = 0; i < num_errb; i++) {
+ struct resource *res = ®ulator_res[num_intb + i];
+
+ *res = regulator_errb_irqs[i];
+ res->start = res->end = irq_create_mapping(errb_domain,
+ res->start);
+ }
+ }
+
+ bd96801_mfd_cells[REGULATOR_CELL].resources = regulator_res;
+ bd96801_mfd_cells[REGULATOR_CELL].num_resources = num_regu_irqs;
+ ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
+ bd96801_mfd_cells,
+ ARRAY_SIZE(bd96801_mfd_cells), NULL, 0, NULL);
+ if (ret)
+ dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n");
+
+free_out:
+ kfree(regulator_res);
+
+ return ret;
+}
+
+static const struct of_device_id bd96801_of_match[] = {
+ {
+ .compatible = "rohm,bd96801",
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, bd96801_of_match);
+
+static struct i2c_driver bd96801_i2c_driver = {
+ .driver = {
+ .name = "rohm-bd96801",
+ .of_match_table = bd96801_of_match,
+ },
+ .probe = bd96801_i2c_probe,
+};
+
+static int __init bd96801_i2c_init(void)
+{
+ return i2c_add_driver(&bd96801_i2c_driver);
+}
+/* Initialise early so consumer devices can complete system boot */
+subsys_initcall(bd96801_i2c_init);
+
+static void __exit bd96801_i2c_exit(void)
+{
+ i2c_del_driver(&bd96801_i2c_driver);
+}
+module_exit(bd96801_i2c_exit);
+
+MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
+MODULE_DESCRIPTION("ROHM BD96801 Power Management IC driver");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/rohm-bd96801.h b/include/linux/mfd/rohm-bd96801.h
new file mode 100644
index 000000000000..47b07171dcb2
--- /dev/null
+++ b/include/linux/mfd/rohm-bd96801.h
@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2020 ROHM Semiconductors */
+
+#ifndef __LINUX_MFD_BD96801_H__
+#define __LINUX_MFD_BD96801_H__
+
+#define BD96801_REG_SSCG_CTRL 0x09
+#define BD96801_REG_SHD_INTB 0x20
+#define BD96801_LDO5_VOL_LVL_REG 0x2c
+#define BD96801_LDO6_VOL_LVL_REG 0x2d
+#define BD96801_LDO7_VOL_LVL_REG 0x2e
+#define BD96801_REG_BUCK_OVP 0x30
+#define BD96801_REG_BUCK_OVD 0x35
+#define BD96801_REG_LDO_OVP 0x31
+#define BD96801_REG_LDO_OVD 0x36
+#define BD96801_REG_BOOT_OVERTIME 0x3a
+#define BD96801_REG_WD_TMO 0x40
+#define BD96801_REG_WD_CONF 0x41
+#define BD96801_REG_WD_FEED 0x42
+#define BD96801_REG_WD_FAILCOUNT 0x43
+#define BD96801_REG_WD_ASK 0x46
+#define BD96801_REG_WD_STATUS 0x4a
+#define BD96801_REG_PMIC_STATE 0x4f
+#define BD96801_REG_EXT_STATE 0x50
+
+#define BD96801_STATE_STBY 0x09
+
+/* IRQ register area */
+#define BD96801_REG_INT_MAIN 0x51
+
+/*
+ * The BD96801 has two physical IRQ lines, INTB and ERRB.
+ * For now we just handle the INTB.
+ *
+ * The 'main status register' is located at 0x51.
+ * The ERRB status registers are located at 0x52 ... 0x5B
+ * INTB status registers are at range 0x5c ... 0x63
+ */
+#define BD96801_REG_INT_SYS_ERRB1 0x52
+#define BD96801_REG_INT_SYS_INTB 0x5c
+#define BD96801_REG_INT_LDO7_INTB 0x63
+
+/* MASK registers */
+#define BD96801_REG_MASK_SYS_INTB 0x73
+#define BD96801_REG_MASK_SYS_ERRB 0x69
+
+#define BD96801_MAX_REGISTER 0x7a
+
+#define BD96801_OTP_ERR_MASK BIT(0)
+#define BD96801_DBIST_ERR_MASK BIT(1)
+#define BD96801_EEP_ERR_MASK BIT(2)
+#define BD96801_ABIST_ERR_MASK BIT(3)
+#define BD96801_PRSTB_ERR_MASK BIT(4)
+#define BD96801_DRMOS1_ERR_MASK BIT(5)
+#define BD96801_DRMOS2_ERR_MASK BIT(6)
+#define BD96801_SLAVE_ERR_MASK BIT(7)
+#define BD96801_VREF_ERR_MASK BIT(0)
+#define BD96801_TSD_ERR_MASK BIT(1)
+#define BD96801_UVLO_ERR_MASK BIT(2)
+#define BD96801_OVLO_ERR_MASK BIT(3)
+#define BD96801_OSC_ERR_MASK BIT(4)
+#define BD96801_PON_ERR_MASK BIT(5)
+#define BD96801_POFF_ERR_MASK BIT(6)
+#define BD96801_CMD_SHDN_ERR_MASK BIT(7)
+#define BD96801_INT_PRSTB_WDT_ERR_MASK BIT(0)
+#define BD96801_INT_CHIP_IF_ERR_MASK BIT(3)
+#define BD96801_INT_SHDN_ERR_MASK BIT(7)
+#define BD96801_OUT_PVIN_ERR_MASK BIT(0)
+#define BD96801_OUT_OVP_ERR_MASK BIT(1)
+#define BD96801_OUT_UVP_ERR_MASK BIT(2)
+#define BD96801_OUT_SHDN_ERR_MASK BIT(7)
+
+/* ERRB IRQs */
+enum {
+ /* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */
+ BD96801_OTP_ERR_STAT,
+ BD96801_DBIST_ERR_STAT,
+ BD96801_EEP_ERR_STAT,
+ BD96801_ABIST_ERR_STAT,
+ BD96801_PRSTB_ERR_STAT,
+ BD96801_DRMOS1_ERR_STAT,
+ BD96801_DRMOS2_ERR_STAT,
+ BD96801_SLAVE_ERR_STAT,
+ BD96801_VREF_ERR_STAT,
+ BD96801_TSD_ERR_STAT,
+ BD96801_UVLO_ERR_STAT,
+ BD96801_OVLO_ERR_STAT,
+ BD96801_OSC_ERR_STAT,
+ BD96801_PON_ERR_STAT,
+ BD96801_POFF_ERR_STAT,
+ BD96801_CMD_SHDN_ERR_STAT,
+ BD96801_INT_PRSTB_WDT_ERR,
+ BD96801_INT_CHIP_IF_ERR,
+ BD96801_INT_SHDN_ERR_STAT,
+
+ /* Reg 0x55 BUCK1 ERR IRQs */
+ BD96801_BUCK1_PVIN_ERR_STAT,
+ BD96801_BUCK1_OVP_ERR_STAT,
+ BD96801_BUCK1_UVP_ERR_STAT,
+ BD96801_BUCK1_SHDN_ERR_STAT,
+
+ /* Reg 0x56 BUCK2 ERR IRQs */
+ BD96801_BUCK2_PVIN_ERR_STAT,
+ BD96801_BUCK2_OVP_ERR_STAT,
+ BD96801_BUCK2_UVP_ERR_STAT,
+ BD96801_BUCK2_SHDN_ERR_STAT,
+
+ /* Reg 0x57 BUCK3 ERR IRQs */
+ BD96801_BUCK3_PVIN_ERR_STAT,
+ BD96801_BUCK3_OVP_ERR_STAT,
+ BD96801_BUCK3_UVP_ERR_STAT,
+ BD96801_BUCK3_SHDN_ERR_STAT,
+
+ /* Reg 0x58 BUCK4 ERR IRQs */
+ BD96801_BUCK4_PVIN_ERR_STAT,
+ BD96801_BUCK4_OVP_ERR_STAT,
+ BD96801_BUCK4_UVP_ERR_STAT,
+ BD96801_BUCK4_SHDN_ERR_STAT,
+
+ /* Reg 0x59 LDO5 ERR IRQs */
+ BD96801_LDO5_PVIN_ERR_STAT,
+ BD96801_LDO5_OVP_ERR_STAT,
+ BD96801_LDO5_UVP_ERR_STAT,
+ BD96801_LDO5_SHDN_ERR_STAT,
+
+ /* Reg 0x5a LDO6 ERR IRQs */
+ BD96801_LDO6_PVIN_ERR_STAT,
+ BD96801_LDO6_OVP_ERR_STAT,
+ BD96801_LDO6_UVP_ERR_STAT,
+ BD96801_LDO6_SHDN_ERR_STAT,
+
+ /* Reg 0x5b LDO7 ERR IRQs */
+ BD96801_LDO7_PVIN_ERR_STAT,
+ BD96801_LDO7_OVP_ERR_STAT,
+ BD96801_LDO7_UVP_ERR_STAT,
+ BD96801_LDO7_SHDN_ERR_STAT,
+};
+
+/* INTB IRQs */
+enum {
+ /* Reg 0x5c (System INTB) */
+ BD96801_TW_STAT,
+ BD96801_WDT_ERR_STAT,
+ BD96801_I2C_ERR_STAT,
+ BD96801_CHIP_IF_ERR_STAT,
+
+ /* Reg 0x5d (BUCK1 INTB) */
+ BD96801_BUCK1_OCPH_STAT,
+ BD96801_BUCK1_OCPL_STAT,
+ BD96801_BUCK1_OCPN_STAT,
+ BD96801_BUCK1_OVD_STAT,
+ BD96801_BUCK1_UVD_STAT,
+ BD96801_BUCK1_TW_CH_STAT,
+
+ /* Reg 0x5e (BUCK2 INTB) */
+ BD96801_BUCK2_OCPH_STAT,
+ BD96801_BUCK2_OCPL_STAT,
+ BD96801_BUCK2_OCPN_STAT,
+ BD96801_BUCK2_OVD_STAT,
+ BD96801_BUCK2_UVD_STAT,
+ BD96801_BUCK2_TW_CH_STAT,
+
+ /* Reg 0x5f (BUCK3 INTB)*/
+ BD96801_BUCK3_OCPH_STAT,
+ BD96801_BUCK3_OCPL_STAT,
+ BD96801_BUCK3_OCPN_STAT,
+ BD96801_BUCK3_OVD_STAT,
+ BD96801_BUCK3_UVD_STAT,
+ BD96801_BUCK3_TW_CH_STAT,
+
+ /* Reg 0x60 (BUCK4 INTB)*/
+ BD96801_BUCK4_OCPH_STAT,
+ BD96801_BUCK4_OCPL_STAT,
+ BD96801_BUCK4_OCPN_STAT,
+ BD96801_BUCK4_OVD_STAT,
+ BD96801_BUCK4_UVD_STAT,
+ BD96801_BUCK4_TW_CH_STAT,
+
+ /* Reg 0x61 (LDO5 INTB) */
+ BD96801_LDO5_OCPH_STAT, //bit [0]
+ BD96801_LDO5_OVD_STAT, //bit [3]
+ BD96801_LDO5_UVD_STAT, //bit [4]
+
+ /* Reg 0x62 (LDO6 INTB) */
+ BD96801_LDO6_OCPH_STAT, //bit [0]
+ BD96801_LDO6_OVD_STAT, //bit [3]
+ BD96801_LDO6_UVD_STAT, //bit [4]
+
+ /* Reg 0x63 (LDO7 INTB) */
+ BD96801_LDO7_OCPH_STAT, //bit [0]
+ BD96801_LDO7_OVD_STAT, //bit [3]
+ BD96801_LDO7_UVD_STAT, //bit [4]
+};
+
+/* IRQ MASKs */
+#define BD96801_TW_STAT_MASK BIT(0)
+#define BD96801_WDT_ERR_STAT_MASK BIT(1)
+#define BD96801_I2C_ERR_STAT_MASK BIT(2)
+#define BD96801_CHIP_IF_ERR_STAT_MASK BIT(3)
+
+#define BD96801_BUCK_OCPH_STAT_MASK BIT(0)
+#define BD96801_BUCK_OCPL_STAT_MASK BIT(1)
+#define BD96801_BUCK_OCPN_STAT_MASK BIT(2)
+#define BD96801_BUCK_OVD_STAT_MASK BIT(3)
+#define BD96801_BUCK_UVD_STAT_MASK BIT(4)
+#define BD96801_BUCK_TW_CH_STAT_MASK BIT(5)
+
+#define BD96801_LDO_OCPH_STAT_MASK BIT(0)
+#define BD96801_LDO_OVD_STAT_MASK BIT(3)
+#define BD96801_LDO_UVD_STAT_MASK BIT(4)
+
+#endif
diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h
index 4eeb22876bad..e7d4e6afe388 100644
--- a/include/linux/mfd/rohm-generic.h
+++ b/include/linux/mfd/rohm-generic.h
@@ -16,6 +16,7 @@ enum rohm_chip_type {
ROHM_CHIP_TYPE_BD71828,
ROHM_CHIP_TYPE_BD71837,
ROHM_CHIP_TYPE_BD71847,
+ ROHM_CHIP_TYPE_BD96801,
ROHM_CHIP_TYPE_AMOUNT
};
--
2.43.2
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [RFC PATCH 5/6] watchdog: ROHM BD96801 PMIC WDG driver
From: Matti Vaittinen @ 2024-04-02 13:11 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Matti Vaittinen, Wim Van Sebroeck, Guenter Roeck,
devicetree, linux-kernel, linux-watchdog
In-Reply-To: <cover.1712058690.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 12479 bytes --]
Introduce driver for WDG block on ROHM BD96801 scalable PMIC.
This driver only supports watchdog with I2C feeding and delayed
response detection. Whether the watchdog toggles PRSTB pin or
just causes an interrupt can be configured via device-tree.
The BD96801 PMIC HW supports also window watchdog (too early
feeding detection) and Q&A mode. These are not supported by
this driver.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
---
drivers/watchdog/Kconfig | 13 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/bd96801_wdt.c | 375 +++++++++++++++++++++++++++++++++
3 files changed, 389 insertions(+)
create mode 100644 drivers/watchdog/bd96801_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 6bee137cfbe0..d97e735e1faa 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -181,6 +181,19 @@ config BD957XMUF_WATCHDOG
watchdog. Alternatively say M to compile the driver as a module,
which will be called bd9576_wdt.
+config BD96801_WATCHDOG
+ tristate "ROHM BD96801 PMIC Watchdog"
+ depends on MFD_ROHM_BD96801
+ select WATCHDOG_CORE
+ help
+ Support for the watchdog in the ROHM BD96801 PMIC. Watchdog can be
+ configured to only generate IRQ or to trigger system reset via reset
+ pin.
+
+ Say Y here to include support for the ROHM BD96801 watchdog.
+ Alternatively say M to compile the driver as a module,
+ which will be called bd96801_wdt.
+
config CROS_EC_WATCHDOG
tristate "ChromeOS EC-based watchdog"
select WATCHDOG_CORE
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 3710c218f05e..31bc94436c81 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -217,6 +217,7 @@ obj-$(CONFIG_XEN_WDT) += xen_wdt.o
# Architecture Independent
obj-$(CONFIG_BD957XMUF_WATCHDOG) += bd9576_wdt.o
+obj-$(CONFIG_BD96801_WATCHDOG) += bd96801_wdt.o
obj-$(CONFIG_CROS_EC_WATCHDOG) += cros_ec_wdt.o
obj-$(CONFIG_DA9052_WATCHDOG) += da9052_wdt.o
obj-$(CONFIG_DA9055_WATCHDOG) += da9055_wdt.o
diff --git a/drivers/watchdog/bd96801_wdt.c b/drivers/watchdog/bd96801_wdt.c
new file mode 100644
index 000000000000..cb2b526ecc21
--- /dev/null
+++ b/drivers/watchdog/bd96801_wdt.c
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022 ROHM Semiconductors
+ *
+ * ROHM BD96801 watchdog driver
+ */
+
+#include <linux/kernel.h>
+#include <linux/mfd/rohm-bd96801.h>
+#include <linux/mfd/rohm-generic.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/watchdog.h>
+
+static bool nowayout;
+module_param(nowayout, bool, 0);
+MODULE_PARM_DESC(nowayout,
+ "Watchdog cannot be stopped once started (default=\"false\")");
+
+#define BD96801_WD_TMO_SHORT_MASK 0x70
+#define BD96801_WD_RATIO_MASK 0x3
+#define BD96801_WD_TYPE_MASK 0x4
+#define BD96801_WD_TYPE_SLOW 0x4
+#define BD96801_WD_TYPE_WIN 0x0
+
+#define BD96801_WD_EN_MASK 0x3
+#define BD96801_WD_IF_EN 0x1
+#define BD96801_WD_QA_EN 0x2
+#define BD96801_WD_DISABLE 0x0
+
+#define BD96801_WD_ASSERT_MASK 0x8
+#define BD96801_WD_ASSERT_RST 0x8
+#define BD96801_WD_ASSERT_IRQ 0x0
+
+#define BD96801_WD_FEED_MASK 0x1
+#define BD96801_WD_FEED 0x1
+
+/* units in uS */
+#define FASTNG_MIN 3370
+#define BD96801_WDT_DEFAULT_MARGIN 6905120
+/* Unit is seconds */
+#define DEFAULT_TIMEOUT 30
+
+/*
+ * BD96801 WDG supports window mode so the TMO consists of SHORT and LONG
+ * timeout values. SHORT time is meaningfull only in window mode where feeding
+ * period shorter than SHORT would be an error. LONG time is used to detect if
+ * feeding is not occurring within given time limit (SoC SW hangs). The LONG
+ * timeout time is a multiple of (2, 4, 8 0r 16 times) the SHORT timeout.
+ */
+
+struct wdtbd96801 {
+ struct device *dev;
+ struct regmap *regmap;
+ bool always_running;
+ struct watchdog_device wdt;
+};
+
+static int bd96801_wdt_ping(struct watchdog_device *wdt)
+{
+ struct wdtbd96801 *w = watchdog_get_drvdata(wdt);
+
+ return regmap_update_bits(w->regmap, BD96801_REG_WD_FEED,
+ BD96801_WD_FEED_MASK, BD96801_WD_FEED);
+}
+
+static int bd96801_wdt_start(struct watchdog_device *wdt)
+{
+ struct wdtbd96801 *w = watchdog_get_drvdata(wdt);
+ int ret;
+
+ ret = regmap_update_bits(w->regmap, BD96801_REG_WD_CONF,
+ BD96801_WD_EN_MASK, BD96801_WD_IF_EN);
+
+ return ret;
+}
+
+static int bd96801_wdt_stop(struct watchdog_device *wdt)
+{
+ struct wdtbd96801 *w = watchdog_get_drvdata(wdt);
+
+ if (!w->always_running)
+ return regmap_update_bits(w->regmap, BD96801_REG_WD_CONF,
+ BD96801_WD_EN_MASK, BD96801_WD_DISABLE);
+ set_bit(WDOG_HW_RUNNING, &wdt->status);
+
+ return 0;
+}
+
+static const struct watchdog_info bd96801_wdt_info = {
+ .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING |
+ WDIOF_SETTIMEOUT,
+ .identity = "BD96801 Watchdog",
+};
+
+static const struct watchdog_ops bd96801_wdt_ops = {
+ .start = bd96801_wdt_start,
+ .stop = bd96801_wdt_stop,
+ .ping = bd96801_wdt_ping,
+};
+
+static int find_closest_fast(int target, int *sel, int *val)
+{
+ int i;
+ int window = FASTNG_MIN;
+
+ for (i = 0; i < 8 && window < target; i++)
+ window <<= 1;
+
+ *val = window;
+ *sel = i;
+
+ if (i == 8)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int find_closest_slow_by_fast(int fast_val, int *target, int *slowsel)
+{
+ int sel;
+ static const int multipliers[] = {2, 4, 8, 16};
+
+ for (sel = 0; sel < ARRAY_SIZE(multipliers) &&
+ multipliers[sel] * fast_val < *target; sel++)
+ ;
+
+ if (sel == ARRAY_SIZE(multipliers))
+ return -EINVAL;
+
+ *slowsel = sel;
+ *target = multipliers[sel] * fast_val;
+
+ return 0;
+}
+
+static int find_closest_slow(int *target, int *slow_sel, int *fast_sel)
+{
+ static const int multipliers[] = {2, 4, 8, 16};
+ int i, j;
+ int val = 0;
+ int window = FASTNG_MIN;
+
+ for (i = 0; i < 8; i++) {
+ for (j = 0; j < ARRAY_SIZE(multipliers); j++) {
+ int slow;
+
+ slow = window * multipliers[j];
+ if (slow >= *target && (!val || slow < val)) {
+ val = slow;
+ *fast_sel = i;
+ *slow_sel = j;
+ }
+ }
+ window <<= 1;
+ }
+ if (!val)
+ return -EINVAL;
+
+ *target = val;
+
+ return 0;
+}
+
+static int bd96801_set_wdt_mode(struct wdtbd96801 *w, int hw_margin,
+ int hw_margin_min)
+{
+ int ret, fastng, slowng, type, reg, mask;
+ struct device *dev = w->dev;
+
+ /* convert to uS */
+ hw_margin *= 1000;
+ hw_margin_min *= 1000;
+ if (hw_margin_min) {
+ int min;
+
+ type = BD96801_WD_TYPE_WIN;
+ dev_dbg(dev, "Setting type WINDOW 0x%x\n", type);
+ ret = find_closest_fast(hw_margin_min, &fastng, &min);
+ if (ret) {
+ dev_err(dev, "bad WDT window for fast timeout\n");
+ return ret;
+ }
+
+ ret = find_closest_slow_by_fast(min, &hw_margin, &slowng);
+ if (ret) {
+ dev_err(dev, "bad WDT window\n");
+ return ret;
+ }
+ w->wdt.min_hw_heartbeat_ms = min / 1000;
+ } else {
+ type = BD96801_WD_TYPE_SLOW;
+ dev_dbg(dev, "Setting type SLOW 0x%x\n", type);
+ ret = find_closest_slow(&hw_margin, &slowng, &fastng);
+ if (ret) {
+ dev_err(dev, "bad WDT window\n");
+ return ret;
+ }
+ }
+
+ w->wdt.max_hw_heartbeat_ms = hw_margin / 1000;
+
+ fastng <<= ffs(BD96801_WD_TMO_SHORT_MASK) - 1;
+
+ reg = slowng | fastng;
+ mask = BD96801_WD_RATIO_MASK | BD96801_WD_TMO_SHORT_MASK;
+ ret = regmap_update_bits(w->regmap, BD96801_REG_WD_TMO,
+ mask, reg);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(w->regmap, BD96801_REG_WD_CONF,
+ BD96801_WD_TYPE_MASK, type);
+
+ return ret;
+}
+
+static int bd96801_set_heartbeat_from_hw(struct wdtbd96801 *w,
+ unsigned int conf_reg)
+{
+ int ret;
+ unsigned int val, sel, fast;
+
+ /*
+ * The BD96801 supports a somewhat peculiar QA-mode, which we do not
+ * support in this driver. If the QA-mode is enabled then we just
+ * warn and bail-out.
+ */
+ if ((conf_reg & BD96801_WD_EN_MASK) != BD96801_WD_IF_EN) {
+ dev_warn(w->dev, "watchdog set to Q&A mode - exiting\n");
+ return -EINVAL;
+ }
+
+ ret = regmap_read(w->regmap, BD96801_REG_WD_TMO, &val);
+ if (ret)
+ return ret;
+
+ sel = val & BD96801_WD_TMO_SHORT_MASK;
+ sel >>= ffs(BD96801_WD_TMO_SHORT_MASK) - 1;
+ fast = FASTNG_MIN << sel;
+
+ sel = (val & BD96801_WD_RATIO_MASK) + 1;
+ w->wdt.max_hw_heartbeat_ms = (fast << sel) / USEC_PER_MSEC;
+
+ if ((conf_reg & BD96801_WD_TYPE_MASK) == BD96801_WD_TYPE_WIN)
+ w->wdt.min_hw_heartbeat_ms = fast / USEC_PER_MSEC;
+
+ return 0;
+}
+
+static int init_wdg_hw(struct wdtbd96801 *w)
+{
+ u32 hw_margin[2];
+ int count, ret;
+ u32 hw_margin_max = BD96801_WDT_DEFAULT_MARGIN, hw_margin_min = 0;
+
+ count = device_property_count_u32(w->dev->parent, "rohm,hw-timeout-ms");
+ if (count < 0 && count != -EINVAL)
+ return count;
+
+ if (count > 0) {
+ if (count > ARRAY_SIZE(hw_margin))
+ return -EINVAL;
+
+ ret = device_property_read_u32_array(w->dev->parent,
+ "rohm,hw-timeout-ms",
+ &hw_margin[0], count);
+ if (ret < 0)
+ return ret;
+
+ if (count == 1)
+ hw_margin_max = hw_margin[0];
+
+ if (count == 2) {
+ hw_margin_max = hw_margin[1];
+ hw_margin_min = hw_margin[0];
+ }
+ }
+
+ ret = bd96801_set_wdt_mode(w, hw_margin_max, hw_margin_min);
+ if (ret)
+ return ret;
+
+ ret = device_property_match_string(w->dev->parent, "rohm,wdg-action",
+ "prstb");
+ if (ret >= 0) {
+ ret = regmap_update_bits(w->regmap, BD96801_REG_WD_CONF,
+ BD96801_WD_ASSERT_MASK,
+ BD96801_WD_ASSERT_RST);
+ return ret;
+ }
+
+ ret = device_property_match_string(w->dev->parent, "rohm,wdg-action",
+ "intb-only");
+ if (ret >= 0) {
+ ret = regmap_update_bits(w->regmap, BD96801_REG_WD_CONF,
+ BD96801_WD_ASSERT_MASK,
+ BD96801_WD_ASSERT_IRQ);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int bd96801_wdt_probe(struct platform_device *pdev)
+{
+ struct wdtbd96801 *w;
+ int ret;
+ unsigned int val;
+
+ w = devm_kzalloc(&pdev->dev, sizeof(*w), GFP_KERNEL);
+ if (!w)
+ return -ENOMEM;
+
+ w->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ w->dev = &pdev->dev;
+
+ w->wdt.info = &bd96801_wdt_info;
+ w->wdt.ops = &bd96801_wdt_ops;
+ w->wdt.parent = pdev->dev.parent;
+ w->wdt.timeout = DEFAULT_TIMEOUT;
+ watchdog_set_drvdata(&w->wdt, w);
+
+ w->always_running = device_property_read_bool(pdev->dev.parent,
+ "always-running");
+
+ ret = regmap_read(w->regmap, BD96801_REG_WD_CONF, &val);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "Failed to get the watchdog state\n");
+
+ /*
+ * If the WDG is already enabled we assume it is configured by boot.
+ * In this case we just update the hw-timeout based on values set to
+ * the timeout / mode registers and leave the hardware configs
+ * untouched.
+ */
+ if ((val & BD96801_WD_EN_MASK) != BD96801_WD_DISABLE) {
+ dev_dbg(&pdev->dev, "watchdog was running during probe\n");
+ ret = bd96801_set_heartbeat_from_hw(w, val);
+ if (ret)
+ return ret;
+
+ set_bit(WDOG_HW_RUNNING, &w->wdt.status);
+ } else {
+ /* If WDG is not running so we will initializate it */
+ ret = init_wdg_hw(w);
+ if (ret)
+ return ret;
+ }
+
+ watchdog_init_timeout(&w->wdt, 0, pdev->dev.parent);
+ watchdog_set_nowayout(&w->wdt, nowayout);
+ watchdog_stop_on_reboot(&w->wdt);
+
+ if (w->always_running)
+ bd96801_wdt_start(&w->wdt);
+
+ return devm_watchdog_register_device(&pdev->dev, &w->wdt);
+}
+
+static struct platform_driver bd96801_wdt = {
+ .driver = {
+ .name = "bd96801-wdt"
+ },
+ .probe = bd96801_wdt_probe,
+};
+module_platform_driver(bd96801_wdt);
+
+MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
+MODULE_DESCRIPTION("BD96801 watchdog driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:bd96801-wdt");
--
2.43.2
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [RFC PATCH 6/6] MAINTAINERS: Add ROHM BD96801 'scalable PMIC' entries
From: Matti Vaittinen @ 2024-04-02 13:12 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Liam Girdwood, Mark Brown, Matti Vaittinen, Wim Van Sebroeck,
Guenter Roeck, devicetree, linux-kernel, linux-watchdog
In-Reply-To: <cover.1712058690.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1470 bytes --]
Add maintainer entries for ROHM BD96801 a.k.a 'scalable PMIC'
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
---
MAINTAINERS | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa3b947fb080..da68144d51ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19111,17 +19111,21 @@ F: drivers/gpio/gpio-bd71828.c
F: drivers/mfd/rohm-bd71828.c
F: drivers/mfd/rohm-bd718x7.c
F: drivers/mfd/rohm-bd9576.c
+F: drivers/mfd/rohm-bd96801.c
F: drivers/regulator/bd71815-regulator.c
F: drivers/regulator/bd71828-regulator.c
F: drivers/regulator/bd718x7-regulator.c
F: drivers/regulator/bd9576-regulator.c
+F: drivers/regulator/bd96801-regulator.c
F: drivers/regulator/rohm-regulator.c
F: drivers/rtc/rtc-bd70528.c
F: drivers/watchdog/bd9576_wdt.c
+F: drivers/watchdog/bd96801_wdt.c
F: include/linux/mfd/rohm-bd71815.h
F: include/linux/mfd/rohm-bd71828.h
F: include/linux/mfd/rohm-bd718x7.h
F: include/linux/mfd/rohm-bd957x.h
+F: include/linux/mfd/rohm-bd96801.h
F: include/linux/mfd/rohm-generic.h
F: include/linux/mfd/rohm-shared.h
--
2.43.2
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* Re: [RFC PATCH 1/2] spi: dt-bindings: add Siflower Quad SPI controller
From: Krzysztof Kozlowski @ 2024-04-02 13:12 UTC (permalink / raw)
To: Mark Brown
Cc: Qingfang Deng, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Qingfang Deng, linux-spi, devicetree, linux-kernel
In-Reply-To: <c4df0a94-be48-464f-892a-7157cb30f034@sirena.org.uk>
On 02/04/2024 14:22, Mark Brown wrote:
> On Sat, Mar 30, 2024 at 06:42:11PM +0100, Krzysztof Kozlowski wrote:
>> On 29/03/2024 02:51, Qingfang Deng wrote:
>
>>> Add YAML devicetree bindings for Siflower Quad SPI controller.
>
>> Describe the hardware. What is this Siflower?
>
> That seems like a perfectly adequate description - ${VENDOR} ${FUNCTION}
> is normal enough and Quad SPI is a well known standard. We don't need a
> marketing spiel for whatever IP version is currently supported.
What we are missing here is the final product, so for example the SoC.
Is the company making exactly one and only one Quad SPI? I provided more
explanation what is missing further in the quoted email and in follow up
email/discussion.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v7 3/4] firmware: arm_scmi: Add SCMI v3.2 pincontrol protocol basic support
From: Andy Shevchenko @ 2024-04-02 13:14 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Linus Walleij, Dan Carpenter, linux-arm-kernel,
linux-kernel, devicetree, linux-gpio, Peng Fan, Oleksii Moisieiev
In-Reply-To: <20240402-pinctrl-scmi-v7-3-3ea519d12cf7@nxp.com>
On Tue, Apr 02, 2024 at 10:22:23AM +0800, Peng Fan (OSS) wrote:
...
> +#include <linux/module.h>
> +#include <linux/scmi_protocol.h>
> +#include <linux/slab.h>
Please, follow IWYU principle, a lot of headers are missed.
> +#include "common.h"
> +#include "protocols.h"
...
> + ret = scmi_pinctrl_get_pin_info(ph, selector,
> + &pi->pins[selector]);
It's netter as a single line.
> + if (ret)
> + return ret;
> + }
...
> +static int scmi_pinctrl_protocol_init(const struct scmi_protocol_handle *ph)
> +{
> + int ret;
> + u32 version;
> + struct scmi_pinctrl_info *pinfo;
> +
> + ret = ph->xops->version_get(ph, &version);
> + if (ret)
> + return ret;
> +
> + dev_dbg(ph->dev, "Pinctrl Version %d.%d\n",
> + PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version));
> +
> + pinfo = devm_kzalloc(ph->dev, sizeof(*pinfo), GFP_KERNEL);
> + if (!pinfo)
> + return -ENOMEM;
> +
> + ret = scmi_pinctrl_attributes_get(ph, pinfo);
> + if (ret)
> + return ret;
> +
> + pinfo->pins = devm_kcalloc(ph->dev, pinfo->nr_pins,
> + sizeof(*pinfo->pins), GFP_KERNEL);
> + if (!pinfo->pins)
> + return -ENOMEM;
> +
> + pinfo->groups = devm_kcalloc(ph->dev, pinfo->nr_groups,
> + sizeof(*pinfo->groups), GFP_KERNEL);
> + if (!pinfo->groups)
> + return -ENOMEM;
> +
> + pinfo->functions = devm_kcalloc(ph->dev, pinfo->nr_functions,
> + sizeof(*pinfo->functions), GFP_KERNEL);
> + if (!pinfo->functions)
> + return -ENOMEM;
> +
> + pinfo->version = version;
> +
> + return ph->set_priv(ph, pinfo, version);
Same comments as per previous version. devm_ here is simply wrong.
It breaks the order of freeing resources.
I.o.w. I see *no guarantee* that these init-deinit functions will be properly
called from the respective probe-remove. Moreover the latter one may also have
its own devm allocations (which are rightfully placed) and you get completely
out of control the resource management.
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: mfd: Add ROHM BD71828 system-power-controller property
From: Matti Vaittinen @ 2024-04-02 13:15 UTC (permalink / raw)
To: Andreas Kemnade, lee, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree, linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20240402111700.494004-2-andreas@kemnade.info>
On 4/2/24 14:16, Andreas Kemnade wrote:
> As the PMIC can power off the system, add the corresponding property.
>
> Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
FWIW
Acked-by: Matti Vaittinen <mazziesaccount@gmail.com>
> ---
> Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
> index 11089aa89ec6..0b62f854bf6b 100644
> --- a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
> +++ b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
> @@ -73,6 +73,8 @@ properties:
> used to mark the pins which should not be configured for GPIO. Please see
> the ../gpio/gpio.txt for more information.
>
> + system-power-controller: true
> +
> required:
> - compatible
> - reg
--
Matti Vaittinen
Linux kernel developer at ROHM Semiconductors
Oulu Finland
~~ When things go utterly wrong vim users can always type :help! ~~
^ permalink raw reply
* [PATCH 0/3] add FnLock LED class device to ideapad laptops
From: Gergo Koteles @ 2024-04-02 13:20 UTC (permalink / raw)
To: Ike Panhc, Hans de Goede, Ilpo Järvinen, Pavel Machek,
Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: platform-driver-x86, linux-kernel, linux-leds, devicetree,
Gergo Koteles
Hi All,
This patch series adds a new LED_FUNCTION_FNLOCK define as "fnlock" and
adds a new FnLock LED class device into the ideapad-laptop driver.
This helps to display FnLock LED status in OSD or other places.
Best regards,
Gergo
Gergo Koteles (3):
dt-bindings: leds: add LED_FUNCTION_FNLOCK
platform/x86: ideapad-laptop: add fn_lock_get/set functions
platform/x86: ideapad-laptop: add FnLock LED class device
drivers/platform/x86/ideapad-laptop.c | 133 +++++++++++++++++++++++---
include/dt-bindings/leds/common.h | 1 +
2 files changed, 123 insertions(+), 11 deletions(-)
base-commit: 39cd87c4eb2b893354f3b850f916353f2658ae6f
--
2.44.0
^ permalink raw reply
* [PATCH 1/3] dt-bindings: leds: add LED_FUNCTION_FNLOCK
From: Gergo Koteles @ 2024-04-02 13:21 UTC (permalink / raw)
To: Ike Panhc, Hans de Goede, Ilpo Järvinen, Pavel Machek,
Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: platform-driver-x86, linux-kernel, linux-leds, devicetree,
Gergo Koteles
In-Reply-To: <cover.1712063200.git.soyer@irl.hu>
Newer laptops have FnLock LED.
Add a define for this very common function.
Signed-off-by: Gergo Koteles <soyer@irl.hu>
---
include/dt-bindings/leds/common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h
index ecea167930d9..d7c980bdf383 100644
--- a/include/dt-bindings/leds/common.h
+++ b/include/dt-bindings/leds/common.h
@@ -46,6 +46,7 @@
#define LED_FUNCTION_CAPSLOCK "capslock"
#define LED_FUNCTION_SCROLLLOCK "scrolllock"
#define LED_FUNCTION_NUMLOCK "numlock"
+#define LED_FUNCTION_FNLOCK "fnlock"
/* Obsolete equivalents: "tpacpi::thinklight" (IBM/Lenovo Thinkpads),
"lp5523:kb{1,2,3,4,5,6}" (Nokia N900) */
#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight"
--
2.44.0
^ permalink raw reply related
* [PATCH 2/3] platform/x86: ideapad-laptop: add fn_lock_get/set functions
From: Gergo Koteles @ 2024-04-02 13:21 UTC (permalink / raw)
To: Ike Panhc, Hans de Goede, Ilpo Järvinen, Pavel Machek,
Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: platform-driver-x86, linux-kernel, linux-leds, devicetree,
Gergo Koteles
In-Reply-To: <cover.1712063200.git.soyer@irl.hu>
The FnLock is retrieved and set in several places in the code.
Move details into ideapad_fn_lock_get and ideapad_fn_lock_set functions.
Signed-off-by: Gergo Koteles <soyer@irl.hu>
---
drivers/platform/x86/ideapad-laptop.c | 38 +++++++++++++++++++--------
1 file changed, 27 insertions(+), 11 deletions(-)
diff --git a/drivers/platform/x86/ideapad-laptop.c b/drivers/platform/x86/ideapad-laptop.c
index 901849810ce2..529df08af548 100644
--- a/drivers/platform/x86/ideapad-laptop.c
+++ b/drivers/platform/x86/ideapad-laptop.c
@@ -513,11 +513,8 @@ static ssize_t fan_mode_store(struct device *dev,
static DEVICE_ATTR_RW(fan_mode);
-static ssize_t fn_lock_show(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int ideapad_fn_lock_get(struct ideapad_private *priv)
{
- struct ideapad_private *priv = dev_get_drvdata(dev);
unsigned long hals;
int err;
@@ -525,7 +522,27 @@ static ssize_t fn_lock_show(struct device *dev,
if (err)
return err;
- return sysfs_emit(buf, "%d\n", !!test_bit(HALS_FNLOCK_STATE_BIT, &hals));
+ return !!test_bit(HALS_FNLOCK_STATE_BIT, &hals);
+}
+
+static int ideapad_fn_lock_set(struct ideapad_private *priv, bool state)
+{
+ return exec_sals(priv->adev->handle,
+ state ? SALS_FNLOCK_ON : SALS_FNLOCK_OFF);
+}
+
+static ssize_t fn_lock_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct ideapad_private *priv = dev_get_drvdata(dev);
+ int brightness;
+
+ brightness = ideapad_fn_lock_get(priv);
+ if (brightness < 0)
+ return brightness;
+
+ return sysfs_emit(buf, "%d\n", brightness);
}
static ssize_t fn_lock_store(struct device *dev,
@@ -540,7 +557,7 @@ static ssize_t fn_lock_store(struct device *dev,
if (err)
return err;
- err = exec_sals(priv->adev->handle, state ? SALS_FNLOCK_ON : SALS_FNLOCK_OFF);
+ err = ideapad_fn_lock_set(priv, state);
if (err)
return err;
@@ -1709,7 +1726,6 @@ static void ideapad_wmi_notify(struct wmi_device *wdev, union acpi_object *data)
{
struct ideapad_wmi_private *wpriv = dev_get_drvdata(&wdev->dev);
struct ideapad_private *priv;
- unsigned long result;
mutex_lock(&ideapad_shared_mutex);
@@ -1722,11 +1738,11 @@ static void ideapad_wmi_notify(struct wmi_device *wdev, union acpi_object *data)
ideapad_input_report(priv, 128);
break;
case IDEAPAD_WMI_EVENT_FN_KEYS:
- if (priv->features.set_fn_lock_led &&
- !eval_hals(priv->adev->handle, &result)) {
- bool state = test_bit(HALS_FNLOCK_STATE_BIT, &result);
+ if (priv->features.set_fn_lock_led) {
+ int brightness = ideapad_fn_lock_get(priv);
- exec_sals(priv->adev->handle, state ? SALS_FNLOCK_ON : SALS_FNLOCK_OFF);
+ if (brightness >= 0)
+ ideapad_fn_lock_set(priv, brightness);
}
if (data->type != ACPI_TYPE_INTEGER) {
--
2.44.0
^ permalink raw reply related
* [PATCH 3/3] platform/x86: ideapad-laptop: add FnLock LED class device
From: Gergo Koteles @ 2024-04-02 13:21 UTC (permalink / raw)
To: Ike Panhc, Hans de Goede, Ilpo Järvinen, Pavel Machek,
Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: platform-driver-x86, linux-kernel, linux-leds, devicetree,
Gergo Koteles
In-Reply-To: <cover.1712063200.git.soyer@irl.hu>
Some Ideapad/Yoga Laptops have an FnLock LED in the Esc key.
Expose Fnlock as an LED class device for easier OSD support.
Signed-off-by: Gergo Koteles <soyer@irl.hu>
---
drivers/platform/x86/ideapad-laptop.c | 97 ++++++++++++++++++++++++++-
1 file changed, 96 insertions(+), 1 deletion(-)
diff --git a/drivers/platform/x86/ideapad-laptop.c b/drivers/platform/x86/ideapad-laptop.c
index 529df08af548..8a5bef4eedfe 100644
--- a/drivers/platform/x86/ideapad-laptop.c
+++ b/drivers/platform/x86/ideapad-laptop.c
@@ -152,6 +152,11 @@ struct ideapad_private {
struct led_classdev led;
unsigned int last_brightness;
} kbd_bl;
+ struct {
+ bool initialized;
+ struct led_classdev led;
+ unsigned int last_brightness;
+ } fn_lock;
};
static bool no_bt_rfkill;
@@ -531,6 +536,19 @@ static int ideapad_fn_lock_set(struct ideapad_private *priv, bool state)
state ? SALS_FNLOCK_ON : SALS_FNLOCK_OFF);
}
+static void ideapad_fn_lock_led_notify(struct ideapad_private *priv, int brightness)
+{
+ if (!priv->fn_lock.initialized)
+ return;
+
+ if (brightness == priv->fn_lock.last_brightness)
+ return;
+
+ priv->fn_lock.last_brightness = brightness;
+
+ led_classdev_notify_brightness_hw_changed(&priv->fn_lock.led, brightness);
+}
+
static ssize_t fn_lock_show(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -561,6 +579,8 @@ static ssize_t fn_lock_store(struct device *dev,
if (err)
return err;
+ ideapad_fn_lock_led_notify(priv, state);
+
return count;
}
@@ -1479,6 +1499,65 @@ static void ideapad_kbd_bl_exit(struct ideapad_private *priv)
led_classdev_unregister(&priv->kbd_bl.led);
}
+/*
+ * FnLock LED
+ */
+static enum led_brightness ideapad_fn_lock_led_cdev_get(struct led_classdev *led_cdev)
+{
+ struct ideapad_private *priv = container_of(led_cdev, struct ideapad_private, fn_lock.led);
+
+ return ideapad_fn_lock_get(priv);
+}
+
+static int ideapad_fn_lock_led_cdev_set(struct led_classdev *led_cdev,
+ enum led_brightness brightness)
+{
+ struct ideapad_private *priv = container_of(led_cdev, struct ideapad_private, fn_lock.led);
+
+ return ideapad_fn_lock_set(priv, brightness);
+}
+
+static int ideapad_fn_lock_led_init(struct ideapad_private *priv)
+{
+ int brightness, err;
+
+ if (!priv->features.fn_lock)
+ return -ENODEV;
+
+ if (WARN_ON(priv->fn_lock.initialized))
+ return -EEXIST;
+
+ priv->fn_lock.led.max_brightness = 1;
+
+ brightness = ideapad_fn_lock_get(priv);
+ if (brightness < 0)
+ return brightness;
+
+ priv->fn_lock.last_brightness = brightness;
+ priv->fn_lock.led.name = "platform::" LED_FUNCTION_FNLOCK;
+ priv->fn_lock.led.brightness_get = ideapad_fn_lock_led_cdev_get;
+ priv->fn_lock.led.brightness_set_blocking = ideapad_fn_lock_led_cdev_set;
+ priv->fn_lock.led.flags = LED_BRIGHT_HW_CHANGED;
+
+ err = led_classdev_register(&priv->platform_device->dev, &priv->fn_lock.led);
+ if (err)
+ return err;
+
+ priv->fn_lock.initialized = true;
+
+ return 0;
+}
+
+static void ideapad_fn_lock_led_exit(struct ideapad_private *priv)
+{
+ if (!priv->fn_lock.initialized)
+ return;
+
+ priv->fn_lock.initialized = false;
+
+ led_classdev_unregister(&priv->fn_lock.led);
+}
+
/*
* module init/exit
*/
@@ -1741,8 +1820,10 @@ static void ideapad_wmi_notify(struct wmi_device *wdev, union acpi_object *data)
if (priv->features.set_fn_lock_led) {
int brightness = ideapad_fn_lock_get(priv);
- if (brightness >= 0)
+ if (brightness >= 0) {
ideapad_fn_lock_set(priv, brightness);
+ ideapad_fn_lock_led_notify(priv, brightness);
+ }
}
if (data->type != ACPI_TYPE_INTEGER) {
@@ -1754,6 +1835,10 @@ static void ideapad_wmi_notify(struct wmi_device *wdev, union acpi_object *data)
dev_dbg(&wdev->dev, "WMI fn-key event: 0x%llx\n",
data->integer.value);
+ /* 0x02 FnLock, 0x03 Esc */
+ if (data->integer.value == 0x02 || data->integer.value == 0x03)
+ ideapad_fn_lock_led_notify(priv, data->integer.value == 0x02);
+
ideapad_input_report(priv,
data->integer.value | IDEAPAD_WMI_KEY);
@@ -1847,6 +1932,14 @@ static int ideapad_acpi_add(struct platform_device *pdev)
dev_info(&pdev->dev, "Keyboard backlight control not available\n");
}
+ err = ideapad_fn_lock_led_init(priv);
+ if (err) {
+ if (err != -ENODEV)
+ dev_warn(&pdev->dev, "Could not set up FnLock LED: %d\n", err);
+ else
+ dev_info(&pdev->dev, "FnLock control not available\n");
+ }
+
/*
* On some models without a hw-switch (the yoga 2 13 at least)
* VPCCMD_W_RF must be explicitly set to 1 for the wifi to work.
@@ -1903,6 +1996,7 @@ static int ideapad_acpi_add(struct platform_device *pdev)
for (i = 0; i < IDEAPAD_RFKILL_DEV_NUM; i++)
ideapad_unregister_rfkill(priv, i);
+ ideapad_fn_lock_led_exit(priv);
ideapad_kbd_bl_exit(priv);
ideapad_input_exit(priv);
@@ -1930,6 +2024,7 @@ static void ideapad_acpi_remove(struct platform_device *pdev)
for (i = 0; i < IDEAPAD_RFKILL_DEV_NUM; i++)
ideapad_unregister_rfkill(priv, i);
+ ideapad_fn_lock_led_exit(priv);
ideapad_kbd_bl_exit(priv);
ideapad_input_exit(priv);
ideapad_debugfs_exit(priv);
--
2.44.0
^ permalink raw reply related
* Re: [PATCH v7 4/4] pinctrl: Implementation of the generic scmi-pinctrl driver
From: Andy Shevchenko @ 2024-04-02 13:22 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Linus Walleij, Dan Carpenter, linux-arm-kernel,
linux-kernel, devicetree, linux-gpio, Peng Fan, Oleksii Moisieiev
In-Reply-To: <20240402-pinctrl-scmi-v7-4-3ea519d12cf7@nxp.com>
On Tue, Apr 02, 2024 at 10:22:24AM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> scmi-pinctrl driver implements pinctrl driver interface and using
> SCMI protocol to redirect messages from pinctrl subsystem SDK to
> SCMI platform firmware, which does the changes in HW.
...
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/module.h>
> +#include <linux/seq_file.h>
> +#include <linux/scmi_protocol.h>
> +#include <linux/slab.h>
Missing headers.
...
> + *p_groups = (const char * const *)func->groups;
Is this casting needed?
...
> +static int pinctrl_scmi_pinconf_get(struct pinctrl_dev *pctldev,
> + unsigned int _pin, unsigned long *config)
Why underscored parameter name?
...
> +static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx,
> + struct pinctrl_desc *desc)
> +{
> + struct pinctrl_pin_desc *pins;
> + unsigned int npins;
> + int ret, i;
> +
> + npins = pinctrl_ops->count_get(pmx->ph, PIN_TYPE);
> + /*
> + * npins will never be zero, the scmi pinctrl driver has bailed out
> + * if npins is zero.
> + */
This is fragile, but at least it is documented.
> + pins = devm_kmalloc_array(pmx->dev, npins, sizeof(*pins), GFP_KERNEL);
> + if (!pins)
> + return -ENOMEM;
> +
> + for (i = 0; i < npins; i++) {
> + pins[i].number = i;
> + ret = pinctrl_ops->name_get(pmx->ph, i, PIN_TYPE, &pins[i].name);
> + if (ret)
How does the cleanup work for the previously assigned pin names? Is it needed?
Maybe a comment?
> + return dev_err_probe(pmx->dev, ret,
> + "Can't get name for pin %d", i);
> + }
> +
> + desc->npins = npins;
> + desc->pins = pins;
> + dev_dbg(pmx->dev, "got pins %u", npins);
> +
> + return 0;
> +}
...
> +static const struct scmi_device_id scmi_id_table[] = {
> + { SCMI_PROTOCOL_PINCTRL, "pinctrl" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(scmi, scmi_id_table);
Move this closer to the user.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH net-next v6 11/17] dt-bindings: net: pse-pd: Add another way of describing several PSE PIs
From: Rob Herring @ 2024-04-02 13:26 UTC (permalink / raw)
To: Kory Maincent
Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Krzysztof Kozlowski,
Conor Dooley, Oleksij Rempel, Mark Brown, Frank Rowand,
Andrew Lunn, Heiner Kallweit, Russell King, Thomas Petazzoni,
netdev, linux-kernel, linux-doc, devicetree, Dent Project
In-Reply-To: <20240326-feature_poe-v6-11-c1011b6ea1cb@bootlin.com>
On Tue, Mar 26, 2024 at 03:04:48PM +0100, Kory Maincent wrote:
> From: Kory Maincent (Dent Project) <kory.maincent@bootlin.com>
>
> PSE PI setup may encompass multiple PSE controllers or auxiliary circuits
> that collectively manage power delivery to one Ethernet port.
> Such configurations might support a range of PoE standards and require
> the capability to dynamically configure power delivery based on the
> operational mode (e.g., PoE2 versus PoE4) or specific requirements of
> connected devices. In these instances, a dedicated PSE PI node becomes
> essential for accurately documenting the system architecture. This node
> would serve to detail the interactions between different PSE controllers,
> the support for various PoE modes, and any additional logic required to
> coordinate power delivery across the network infrastructure.
>
> The old usage of "#pse-cells" is unsuficient as it carries only the PSE PI
> index information.
>
> Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
> ---
>
> Changes in v3:
> - New patch
>
> Changes in v4:
> - Remove $def
> - Fix pairset-names item list
> - Upgrade few properties description
> - Update the commit message
>
> Changes in v5:
> - Fix yamllint error.
> - Replace underscore by dash in properties names.
> - Add polarity-supported property.
>
> Changes in v6:
> - Reorder the pairset pinout table documentation to shrink the lines size.
> - Remove pairset and polarity as required fields.
> - Add vpwr-supply regulator supply.
> ---
> .../bindings/net/pse-pd/pse-controller.yaml | 102 ++++++++++++++++++++-
> 1 file changed, 99 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/pse-pd/pse-controller.yaml b/Documentation/devicetree/bindings/net/pse-pd/pse-controller.yaml
> index 2d382faca0e6..03f7f215c162 100644
> --- a/Documentation/devicetree/bindings/net/pse-pd/pse-controller.yaml
> +++ b/Documentation/devicetree/bindings/net/pse-pd/pse-controller.yaml
> @@ -13,6 +13,7 @@ description: Binding for the Power Sourcing Equipment (PSE) as defined in the
>
> maintainers:
> - Oleksij Rempel <o.rempel@pengutronix.de>
> + - Kory Maincent <kory.maincent@bootlin.com>
>
> properties:
> $nodename:
> @@ -22,11 +23,106 @@ properties:
> description:
> Used to uniquely identify a PSE instance within an IC. Will be
> 0 on PSE nodes with only a single output and at least 1 on nodes
> - controlling several outputs.
> + controlling several outputs which are not described in the pse-pis
> + subnode. This property is deprecated, please use pse-pis instead.
> enum: [0, 1]
>
> -required:
> - - "#pse-cells"
> + pse-pis:
> + type: object
> + description:
> + Overview of the PSE PIs provided by the controller.
> +
> + properties:
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> + required:
> + - "#address-cells"
> + - "#size-cells"
> +
> + patternProperties:
> + "^pse-pi@[0-9a-f]+$":
> + type: object
> + description:
> + PSE PI for power delivery via pairsets, compliant with IEEE
> + 802.3-2022, Section 145.2.4. Each pairset comprises a positive and
> + a negative VPSE pair, adhering to the pinout configurations
> + detailed in the standard.
> + See Documentation/networking/pse-pd/pse-pi.rst for details.
> +
> + properties:
> + reg:
> + description:
> + Address describing the PSE PI index.
> + maxItems: 1
> +
> + "#pse-cells":
> + const: 0
> +
> + pairset-names:
> + $ref: /schemas/types.yaml#/definitions/string-array
> + description:
> + Names of the pairsets as per IEEE 802.3-2022, Section 145.2.4.
> + Valid values are "alternative-a" and "alternative-b". Each name
Don't state constraints in prose which are defined as schema
constraints.
> + should correspond to a phandle in the 'pairset' property
> + pointing to the power supply for that pairset.
> + minItems: 1
> + maxItems: 2
> + items:
> + enum:
> + - alternative-a
> + - alternative-b
> +
> + pairsets:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + List of phandles, each pointing to the power supply for the
> + corresponding pairset named in 'pairset-names'. This property
> + aligns with IEEE 802.3-2022, Section 33.2.3 and 145.2.4.
> + PSE Pinout Alternatives (as per IEEE 802.3-2022 Table 145\u20133)
> + |-----------|---------------|---------------|---------------|---------------|
> + | Conductor | Alternative A | Alternative A | Alternative B | Alternative B |
> + | | (MDI-X) | (MDI) | (X) | (S) |
> + |-----------|---------------|---------------|---------------|---------------|
> + | 1 | Negative VPSE | Positive VPSE | \u2014 | \u2014 |
> + | 2 | Negative VPSE | Positive VPSE | \u2014 | \u2014 |
> + | 3 | Positive VPSE | Negative VPSE | \u2014 | \u2014 |
> + | 4 | \u2014 | \u2014 | Negative VPSE | Positive VPSE |
> + | 5 | \u2014 | \u2014 | Negative VPSE | Positive VPSE |
> + | 6 | Positive VPSE | Negative VPSE | \u2014 | \u2014 |
> + | 7 | \u2014 | \u2014 | Positive VPSE | Negative VPSE |
> + | 8 | \u2014 | \u2014 | Positive VPSE | Negative VPSE |
> + minItems: 1
> + maxItems: 2
"pairsets" does not follow the normal design pattern of foos, foo-names,
and #foo-cells. You could add #foo-cells I suppose, but what would cells
convey? I don't think it's a good fit for what you need.
The other oddity is the number of entries and the names are fixed. That
is usually defined per consumer.
As each entry is just a power rail, why can't the regulator binding be
used here?
> +
> + polarity-supported:
> + $ref: /schemas/types.yaml#/definitions/string-array
> + description:
> + Polarity configuration supported by the PSE PI pairsets.
> + minItems: 1
> + maxItems: 4
> + items:
> + enum:
> + - MDI-X
> + - MDI
> + - X
> + - S
> +
> + vpwr-supply:
> + description: Regulator power supply for the PSE PI.
I don't see this being used anywhere.
> +
> + required:
> + - reg
> + - "#pse-cells"
> +
> +oneOf:
> + - required:
> + - "#pse-cells"
> + - required:
> + - pse-pis
>
> additionalProperties: true
>
>
> --
> 2.25.1
>
^ permalink raw reply
* [Patch v2 0/2] memory: tegra: Skip restricted register access from Guest
From: Sumit Gupta @ 2024-04-02 13:26 UTC (permalink / raw)
To: krzysztof.kozlowski, robh, conor+dt, maz, mark.rutland, treding,
jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu, sumitg
MC SID and Broadbast channel register access is restricted for Guest VM.
But the Tegra MC driver is considering both these regions as mandatory
and causes error on access. Change that to consider both the regions as
optional in SoC's from Tegra186 onwards. Then skip access to the
restricted registers from Guest if its region is not present in Guest DT
and hence not mapped.
Previously, the solution in [1] was not accepted. Now, handled the
problem with this alternate solution.
---
v1[1] -> v2:
- consider broadcast channel registers also as restricted along with sid.
- make sid and broadcast regions optional and access if present in dt.
- update the yaml file.
Sumit Gupta (2):
dt-bindings: make sid and broadcast reg optional
memory: tegra: make sid and broadcast regions optional
.../nvidia,tegra186-mc.yaml | 18 +++++++--------
drivers/memory/tegra/mc.c | 9 +++++++-
drivers/memory/tegra/mc.h | 18 +++++++--------
drivers/memory/tegra/tegra186.c | 22 ++++++++++---------
4 files changed, 38 insertions(+), 29 deletions(-)
[1] https://lore.kernel.org/lkml/20240206114852.8472-1-sumitg@nvidia.com/
--
2.17.1
^ permalink raw reply
* [Patch v2 1/2] dt-bindings: make sid and broadcast reg optional
From: Sumit Gupta @ 2024-04-02 13:26 UTC (permalink / raw)
To: krzysztof.kozlowski, robh, conor+dt, maz, mark.rutland, treding,
jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu, sumitg
In-Reply-To: <20240402132626.24693-1-sumitg@nvidia.com>
MC SID and Broadbast channel register access is restricted for Guest VM.
Make both the regions as optional for SoC's from Tegra186 onwards.
Tegra MC driver will skip access to the restricted registers from Guest
if the respective regions are not present in the memory-controller node
of Guest DT.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
.../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 935d63d181d9..c52c259f7ec5 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -146,17 +146,17 @@ allOf:
then:
properties:
reg:
- maxItems: 6
+ maxItems: 4
description: 5 memory controller channels and 1 for stream-id registers
reg-names:
items:
- - const: sid
- - const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
+ - const: sid
+ - const: broadcast
- if:
properties:
@@ -165,13 +165,11 @@ allOf:
then:
properties:
reg:
- minItems: 18
+ minItems: 16
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
items:
- - const: sid
- - const: broadcast
- const: ch0
- const: ch1
- const: ch2
@@ -188,6 +186,8 @@ allOf:
- const: ch13
- const: ch14
- const: ch15
+ - const: sid
+ - const: broadcast
- if:
properties:
@@ -196,13 +196,11 @@ allOf:
then:
properties:
reg:
- minItems: 18
+ minItems: 16
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
items:
- - const: sid
- - const: broadcast
- const: ch0
- const: ch1
- const: ch2
@@ -219,6 +217,8 @@ allOf:
- const: ch13
- const: ch14
- const: ch15
+ - const: sid
+ - const: broadcast
additionalProperties: false
--
2.17.1
^ permalink raw reply related
* [Patch v2 2/2] memory: tegra: make sid and broadcast regions optional
From: Sumit Gupta @ 2024-04-02 13:26 UTC (permalink / raw)
To: krzysztof.kozlowski, robh, conor+dt, maz, mark.rutland, treding,
jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu, sumitg
In-Reply-To: <20240402132626.24693-1-sumitg@nvidia.com>
MC SID and Broadbast channel register access is restricted for Guest VM.
In Tegra MC driver, consider both the regions as optional and skip
access to restricted registers from Guest if a region is not present
in Guest DT.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
drivers/memory/tegra/mc.c | 9 ++++++++-
drivers/memory/tegra/mc.h | 18 +++++++++---------
drivers/memory/tegra/tegra186.c | 22 ++++++++++++----------
3 files changed, 29 insertions(+), 20 deletions(-)
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 224b488794e5..d819dab1b223 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -899,6 +899,7 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)
static int tegra_mc_probe(struct platform_device *pdev)
{
+ struct resource *res;
struct tegra_mc *mc;
u64 mask;
int err;
@@ -923,7 +924,13 @@ static int tegra_mc_probe(struct platform_device *pdev)
/* length of MC tick in nanoseconds */
mc->tick = 30;
- mc->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (mc->soc->num_channels) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sid");
+ if (res)
+ mc->regs = devm_ioremap_resource(&pdev->dev, res);
+ } else {
+ mc->regs = devm_platform_ioremap_resource(pdev, 0);
+ }
if (IS_ERR(mc->regs))
return PTR_ERR(mc->regs);
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index c3f6655bec60..5cdb9451f364 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -112,11 +112,11 @@ icc_provider_to_tegra_mc(struct icc_provider *provider)
static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch,
unsigned long offset)
{
- if (!mc->bcast_ch_regs)
- return 0;
-
- if (ch == MC_BROADCAST_CHANNEL)
+ if (ch == MC_BROADCAST_CHANNEL) {
+ if (!mc->bcast_ch_regs)
+ return 0;
return readl_relaxed(mc->bcast_ch_regs + offset);
+ }
return readl_relaxed(mc->ch_regs[ch] + offset);
}
@@ -124,13 +124,13 @@ static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch,
static inline void mc_ch_writel(const struct tegra_mc *mc, int ch,
u32 value, unsigned long offset)
{
- if (!mc->bcast_ch_regs)
- return;
-
- if (ch == MC_BROADCAST_CHANNEL)
+ if (ch == MC_BROADCAST_CHANNEL) {
+ if (!mc->bcast_ch_regs)
+ return;
writel_relaxed(value, mc->bcast_ch_regs + offset);
- else
+ } else {
writel_relaxed(value, mc->ch_regs[ch] + offset);
+ }
}
static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
index 1b3183951bfe..7b5e9bd13ffd 100644
--- a/drivers/memory/tegra/tegra186.c
+++ b/drivers/memory/tegra/tegra186.c
@@ -26,20 +26,16 @@
static int tegra186_mc_probe(struct tegra_mc *mc)
{
struct platform_device *pdev = to_platform_device(mc->dev);
+ struct resource *res;
unsigned int i;
char name[8];
int err;
- mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
- if (IS_ERR(mc->bcast_ch_regs)) {
- if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
- dev_warn(&pdev->dev,
- "Broadcast channel is missing, please update your device-tree\n");
- mc->bcast_ch_regs = NULL;
- goto populate;
- }
-
- return PTR_ERR(mc->bcast_ch_regs);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "broadcast");
+ if (res) {
+ mc->bcast_ch_regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(mc->bcast_ch_regs))
+ return PTR_ERR(mc->bcast_ch_regs);
}
mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs),
@@ -121,6 +117,9 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
if (!tegra_dev_iommu_get_stream_id(dev, &sid))
return 0;
+ if (!mc->regs)
+ return 0;
+
while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
index, &args)) {
if (args.np == mc->dev->of_node && args.args_count != 0) {
@@ -146,6 +145,9 @@ static int tegra186_mc_resume(struct tegra_mc *mc)
#if IS_ENABLED(CONFIG_IOMMU_API)
unsigned int i;
+ if (!mc->regs)
+ return 0;
+
for (i = 0; i < mc->soc->num_clients; i++) {
const struct tegra_mc_client *client = &mc->soc->clients[i];
--
2.17.1
^ permalink raw reply related
* RE: [PATCH v7 3/4] firmware: arm_scmi: Add SCMI v3.2 pincontrol protocol basic support
From: Peng Fan @ 2024-04-02 13:27 UTC (permalink / raw)
To: Andy Shevchenko, Peng Fan (OSS)
Cc: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Linus Walleij, Dan Carpenter,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Oleksii Moisieiev
In-Reply-To: <ZgwEtxj-qi6uy_m2@smile.fi.intel.com>
Hi Andy
> Subject: Re: [PATCH v7 3/4] firmware: arm_scmi: Add SCMI v3.2 pincontrol
> protocol basic support
>
> On Tue, Apr 02, 2024 at 10:22:23AM +0800, Peng Fan (OSS) wrote:
>
> ...
>
> > +#include <linux/module.h>
> > +#include <linux/scmi_protocol.h>
> > +#include <linux/slab.h>
>
> Please, follow IWYU principle, a lot of headers are missed.
ok. I will try to figure out. BTW, is there an easy way to filter
out what is missed?
>
> > +#include "common.h"
> > +#include "protocols.h"
>
> ...
>
> > + ret = scmi_pinctrl_get_pin_info(ph, selector,
> > + &pi->pins[selector]);
>
> It's netter as a single line.
I try to follow 80 max chars per SCMI coding style. If Sudeep and Cristian
is ok, I could use a single line.
>
> > + if (ret)
> > + return ret;
> > + }
>
> ...
>
> > +static int scmi_pinctrl_protocol_init(const struct
> > +scmi_protocol_handle *ph) {
> > + int ret;
> > + u32 version;
> > + struct scmi_pinctrl_info *pinfo;
> > +
> > + ret = ph->xops->version_get(ph, &version);
> > + if (ret)
> > + return ret;
> > +
> > + dev_dbg(ph->dev, "Pinctrl Version %d.%d\n",
> > + PROTOCOL_REV_MAJOR(version),
> PROTOCOL_REV_MINOR(version));
> > +
> > + pinfo = devm_kzalloc(ph->dev, sizeof(*pinfo), GFP_KERNEL);
> > + if (!pinfo)
> > + return -ENOMEM;
> > +
> > + ret = scmi_pinctrl_attributes_get(ph, pinfo);
> > + if (ret)
> > + return ret;
> > +
> > + pinfo->pins = devm_kcalloc(ph->dev, pinfo->nr_pins,
> > + sizeof(*pinfo->pins), GFP_KERNEL);
> > + if (!pinfo->pins)
> > + return -ENOMEM;
> > +
> > + pinfo->groups = devm_kcalloc(ph->dev, pinfo->nr_groups,
> > + sizeof(*pinfo->groups), GFP_KERNEL);
> > + if (!pinfo->groups)
> > + return -ENOMEM;
> > +
> > + pinfo->functions = devm_kcalloc(ph->dev, pinfo->nr_functions,
> > + sizeof(*pinfo->functions),
> GFP_KERNEL);
> > + if (!pinfo->functions)
> > + return -ENOMEM;
> > +
> > + pinfo->version = version;
> > +
> > + return ph->set_priv(ph, pinfo, version);
>
> Same comments as per previous version. devm_ here is simply wrong.
> It breaks the order of freeing resources.
>
> I.o.w. I see *no guarantee* that these init-deinit functions will be properly
> called from the respective probe-remove. Moreover the latter one may also
> have its own devm allocations (which are rightfully placed) and you get
> completely out of control the resource management.
I see an old thread.
https://lore.kernel.org/linux-arm-kernel/ZJ78hBcjAhiU+ZBO@e120937-lin/#t
The free in deinit is not to free the ones alloced in init, it is to free the ones
alloced such as in scmi_pinctrl_get_function_info
Thanks,
Peng.
>
> > +}
>
> --
> With Best Regards,
> Andy Shevchenko
>
^ permalink raw reply
* Re: [PATCH net-next v6 14/17] dt-bindings: net: pse-pd: Add bindings for PD692x0 PSE controller
From: Rob Herring @ 2024-04-02 13:28 UTC (permalink / raw)
To: Kory Maincent
Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Krzysztof Kozlowski,
Conor Dooley, Oleksij Rempel, Mark Brown, Frank Rowand,
Andrew Lunn, Heiner Kallweit, Russell King, Thomas Petazzoni,
netdev, linux-kernel, linux-doc, devicetree, Dent Project
In-Reply-To: <20240326-feature_poe-v6-14-c1011b6ea1cb@bootlin.com>
On Tue, Mar 26, 2024 at 03:04:51PM +0100, Kory Maincent wrote:
> From: Kory Maincent (Dent Project) <kory.maincent@bootlin.com>
>
> Add the PD692x0 I2C Power Sourcing Equipment controller device tree
> bindings documentation.
>
> Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
> ---
>
> Changes in v2:
> - Enhance ports-matrix description.
> - Replace additionalProperties by unevaluatedProperties.
> - Drop i2c suffix.
>
> Changes in v3:
> - Remove ports-matrix parameter.
> - Add description of all physical ports and managers.
> - Add pse_pis subnode moving to the API of pse-controller binding.
> - Remove the MAINTAINERS section for this driver as I will be maintaining
> all pse-pd subsystem.
>
> Changes in v5:
> - Remove defs used only once.
> - Replace underscore by dash.
> - Add description.
> ---
> .../bindings/net/pse-pd/microchip,pd692x0.yaml | 158 +++++++++++++++++++++
> 1 file changed, 158 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml
> new file mode 100644
> index 000000000000..62ea4363cba3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml
> @@ -0,0 +1,158 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip PD692x0 Power Sourcing Equipment controller
> +
> +maintainers:
> + - Kory Maincent <kory.maincent@bootlin.com>
> +
> +allOf:
> + - $ref: pse-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,pd69200
> + - microchip,pd69210
> + - microchip,pd69220
> +
> + reg:
> + maxItems: 1
> +
> + managers:
> + type: object
> + description:
> + List of the PD69208T4/PD69204T4/PD69208M PSE managers. Each manager
> + have 4 or 8 physical ports according to the chip version. No need to
> + specify the SPI chip select as it is automatically detected by the
> + PD692x0 PSE controller. The PSE managers have to be described from
> + the lowest chip select to the greatest one, which is the detection
> + behavior of the PD692x0 PSE controller. The PD692x0 support up to
> + 12 PSE managers which can expose up to 96 physical ports. All
> + physical ports available on a manager have to be described in the
> + incremental order even if they are not used.
> +
> + properties:
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> + required:
> + - "#address-cells"
> + - "#size-cells"
> +
> + patternProperties:
> + "^manager@0[0-9]|1[0-2]$":
Unit-addresses are typically in hex.
Is 'manager' something specific to this device or should be common?
> + $ref: /schemas/graph.yaml#/properties/ports
This is not using the graph binding. Furthermore, I don't want to see
new cases of 'port' node names which are not graph nodes. We have it
already with ethernet switches, but 'ethernet-port' is preferred over
'port'.
Why is this one 'managers' and the other device binding 'channels'?
> + description:
> + PD69208T4/PD69204T4/PD69208M PSE manager exposing 4 or 8 physical
> + ports.
> +
> + properties:
> + reg:
> + description:
> + Incremental index of the PSE manager starting from 0, ranging
> + from lowest to highest chip select, up to 12.
> + maxItems: 1
> +
> + patternProperties:
> + '^port@[0-7]$':
> + type: object
> + required:
> + - reg
Any property you want is allowed in this node. You are missing
'additionalProperties'.
> +
> + required:
> + - reg
> +
> +required:
> + - compatible
> + - reg
> + - pse-pis
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethernet-pse@3c {
> + compatible = "microchip,pd69200";
> + reg = <0x3c>;
> +
> + managers {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + manager@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + phys0: port@0 {
> + reg = <0>;
> + };
> +
> + phys1: port@1 {
> + reg = <1>;
> + };
> +
> + phys2: port@2 {
> + reg = <2>;
> + };
> +
> + phys3: port@3 {
> + reg = <3>;
> + };
> + };
> +
> + manager@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + phys4: port@0 {
> + reg = <0>;
> + };
> +
> + phys5: port@1 {
> + reg = <1>;
> + };
> +
> + phys6: port@2 {
> + reg = <2>;
> + };
> +
> + phys7: port@3 {
> + reg = <3>;
> + };
> + };
> + };
> +
> + pse-pis {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pse_pi0: pse-pi@0 {
> + reg = <0>;
> + #pse-cells = <0>;
> + pairset-names = "alternative-a", "alternative-b";
> + pairsets = <&phys0>, <&phys1>;
It is very strange that you are describing the connections within a
device.
> + polarity-supported = "MDI", "S";
> + };
> + pse_pi1: pse-pi@1 {
> + reg = <1>;
> + #pse-cells = <0>;
> + pairset-names = "alternative-a";
> + pairsets = <&phys2>;
> + polarity-supported = "MDI";
> + };
> + };
> + };
> + };
>
> --
> 2.25.1
>
^ permalink raw reply
* Re: [PATCH net-next 1/3] dt-bindings: net: renesas,rzn1-gmac: Document RZ/N1 GMAC support
From: Geert Uytterhoeven @ 2024-04-02 13:43 UTC (permalink / raw)
To: Romain Gantois
Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Alexandre Torgue, Jose Abreu,
Maxime Coquelin, Russell King, Clément Léger,
Thomas Petazzoni, netdev, devicetree, linux-kernel,
linux-renesas-soc, linux-stm32, linux-arm-kernel
In-Reply-To: <20240402-rzn1-gmac1-v1-1-5be2b2894d8c@bootlin.com>
Hi Romain,
On Tue, Apr 2, 2024 at 2:36 PM Romain Gantois
<romain.gantois@bootlin.com> wrote:
> From: Clément Léger <clement.leger@bootlin.com>
>
> The RZ/N1 series of MPUs feature up to two Gigabit Ethernet controllers.
> These controllers are based on Synopsys IPs. They can be connected to
> RZ/N1 RGMII/RMII converters.
>
> Add a binding that describes these GMAC devices.
>
> Signed-off-by: "Clément Léger" <clement.leger@bootlin.com>
> [rgantois: commit log]
> Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml
> +examples:
> + - |
> + #include <dt-bindings/clock/r9a06g032-sysctrl.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + ethernet@44000000 {
> + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
> + reg = <0x44000000 0x2000>;
> + interrupt-parent = <&gic>;
There is no need to use interrupt-parent in examples.
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
> + clock-names = "stmmaceth";
> + clocks = <&sysctrl R9A06G032_HCLK_GMAC0>;
If you want this to be a real example, you should add power-domains.
> + snps,multicast-filter-bins = <256>;
> + snps,perfect-filter-entries = <128>;
> + tx-fifo-depth = <2048>;
> + rx-fifo-depth = <4096>;
> + pcs-handle = <&mii_conv1>;
> + phy-mode = "mii";
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: arm: ti: Add BeagleY-AI
From: Rob Herring @ 2024-04-02 13:43 UTC (permalink / raw)
To: Robert Nelson
Cc: Jason Kridner, linux-arm-kernel, Nishanth Menon, linux-kernel,
Jared McArthur, devicetree, Deepak Khatri
In-Reply-To: <20240328191205.82295-1-robertcnelson@gmail.com>
On Thu, 28 Mar 2024 14:12:04 -0500, Robert Nelson wrote:
> This board is based on ti,j722s
>
> https://beagley-ai.org/
> https://openbeagle.org/beagley-ai/beagley-ai
>
> Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
> CC: Rob Herring <robh@kernel.org>
> CC: Nishanth Menon <nm@ti.com>
> CC: Jared McArthur <j-mcarthur@ti.com>
> CC: Jason Kridner <jkridner@beagleboard.org>
> CC: Deepak Khatri <lorforlinux@beagleboard.org>
> ---
> Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
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