* [PATCH 1/3] arm64: dts: imx8dxl-ss-adma: delete unused node
From: Frank Li @ 2024-04-02 21:02 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li
In-Reply-To: <20240402-b4-dts_dxl_audio-v1-0-d26d25b84a08@nxp.com>
Delete unused node in adma subsystem.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
index 5d012c95222f5..f5dcdd9405928 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -3,6 +3,20 @@
* Copyright 2019~2020, 2022 NXP
*/
+/delete-node/ &asrc1;
+/delete-node/ &asrc1_lpcg;
+/delete-node/ &adc1;
+/delete-node/ &adc1_lpcg;
+/delete-node/ &amix;
+/delete-node/ &amix_lpcg;
+/delete-node/ &edma1;
+/delete-node/ &esai0;
+/delete-node/ &esai0_lpcg;
+/delete-node/ &sai4;
+/delete-node/ &sai4_lpcg;
+/delete-node/ &sai5;
+/delete-node/ &sai5_lpcg;
+
&audio_ipg_clk {
clock-frequency = <160000000>;
};
--
2.34.1
^ permalink raw reply related
* [PATCH 0/3] arm64: dts: imx8dxl: add audio support for imx8dxl
From: Frank Li @ 2024-04-02 21:02 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li
This patches depend on dts part in
https://lore.kernel.org/imx/20240328-asrc_8qxp-v8-0-801cd6bb5be2@nxp.com/T/#t
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Frank Li (3):
arm64: dts: imx8dxl-ss-adma: delete unused node
arm64: dts: imx8dxl-ss-adma: update audio node power domains and IRQ number
arm64: dts: imx8dxl-evk: add audio nodes
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 234 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi | 78 +++++++
2 files changed, 312 insertions(+)
---
base-commit: 2d13a7797c3970a4eea160844d8905c93065634f
change-id: 20240402-b4-dts_dxl_audio-74ba02030a72
Best regards,
---
Frank Li <Frank.Li@nxp.com>
^ permalink raw reply
* [PATCH v9 5/9] clk: mmp: Add Marvell PXA1908 clock driver
From: Duje Mihanović @ 2024-04-02 20:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tony Lindgren, Haojian Zhuang,
Duje Mihanović, Lubomir Rintel, Catalin Marinas, Will Deacon,
Kees Cook, Tony Luck, Guilherme G. Piccoli, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, Karel Balej, David Wronek,
linux-clk, linux-kernel, linux-gpio, devicetree, linux-arm-kernel
In-Reply-To: <20240402-pxa1908-lkml-v9-0-25a003e83c6f@skole.hr>
Add driver for Marvell PXA1908 clock controller blocks. The SoC has
numerous clock controller blocks, currently supporting APBC, APBCP, MPMU
and APMU.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-of-pxa1908.c | 328 +++++++++++++++++++++++++++++++++++++++
2 files changed, 329 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 441bf83080a1..69f9c3afde83 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -11,4 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o
obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o
-obj-y += clk-of-pxa1928.o
+obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-of-pxa1908.o
diff --git a/drivers/clk/mmp/clk-of-pxa1908.c b/drivers/clk/mmp/clk-of-pxa1908.c
new file mode 100644
index 000000000000..6f1f6e25a718
--- /dev/null
+++ b/drivers/clk/mmp/clk-of-pxa1908.c
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/units.h>
+
+#include <dt-bindings/clock/marvell,pxa1908.h>
+
+#include "clk.h"
+
+#define APMU_CLK_GATE_CTRL 0x40
+#define MPMU_UART_PLL 0x14
+
+#define APBC_UART0 0x0
+#define APBC_UART1 0x4
+#define APBC_GPIO 0x8
+#define APBC_PWM0 0xc
+#define APBC_PWM1 0x10
+#define APBC_PWM2 0x14
+#define APBC_PWM3 0x18
+#define APBC_SSP0 0x1c
+#define APBC_SSP1 0x20
+#define APBC_IPC_RST 0x24
+#define APBC_RTC 0x28
+#define APBC_TWSI0 0x2c
+#define APBC_KPC 0x30
+#define APBC_SWJTAG 0x40
+#define APBC_SSP2 0x4c
+#define APBC_TWSI1 0x60
+#define APBC_THERMAL 0x6c
+#define APBC_TWSI3 0x70
+
+#define APBCP_UART2 0x1c
+#define APBCP_TWSI2 0x28
+#define APBCP_AICER 0x38
+
+#define APMU_CCIC1 0x24
+#define APMU_ISP 0x38
+#define APMU_DSI1 0x44
+#define APMU_DISP1 0x4c
+#define APMU_CCIC0 0x50
+#define APMU_SDH0 0x54
+#define APMU_SDH1 0x58
+#define APMU_USB 0x5c
+#define APMU_NF 0x60
+#define APMU_VPU 0xa4
+#define APMU_GC 0xcc
+#define APMU_SDH2 0xe0
+#define APMU_GC2D 0xf4
+#define APMU_TRACE 0x108
+#define APMU_DVC_DFC_DEBUG 0x140
+
+#define MPMU_NR_CLKS 39
+#define APBC_NR_CLKS 19
+#define APBCP_NR_CLKS 4
+#define APMU_NR_CLKS 17
+
+struct pxa1908_clk_unit {
+ struct mmp_clk_unit unit;
+ void __iomem *mpmu_base;
+ void __iomem *apmu_base;
+ void __iomem *apbc_base;
+ void __iomem *apbcp_base;
+ void __iomem *apbs_base;
+ void __iomem *ciu_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+ {PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768},
+ {PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26 * HZ_PER_MHZ},
+ {PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624 * HZ_PER_MHZ},
+ {PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416 * HZ_PER_MHZ},
+ {PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499 * HZ_PER_MHZ},
+ {PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832 * HZ_PER_MHZ},
+ {PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248 * HZ_PER_MHZ},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+ {PXA1908_CLK_PLL1_D2, "pll1_d2", "pll1_624", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D4, "pll1_d4", "pll1_d2", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D6, "pll1_d6", "pll1_d2", 1, 3, 0},
+ {PXA1908_CLK_PLL1_D8, "pll1_d8", "pll1_d4", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D12, "pll1_d12", "pll1_d6", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D13, "pll1_d13", "pll1_624", 1, 13, 0},
+ {PXA1908_CLK_PLL1_D16, "pll1_d16", "pll1_d8", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D24, "pll1_d24", "pll1_d12", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D48, "pll1_d48", "pll1_d24", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D96, "pll1_d96", "pll1_d48", 1, 2, 0},
+ {PXA1908_CLK_PLL1_32, "pll1_32", "pll1_d13", 2, 3, 0},
+ {PXA1908_CLK_PLL1_208, "pll1_208", "pll1_d2", 2, 3, 0},
+ {PXA1908_CLK_PLL1_117, "pll1_117", "pll1_624", 3, 16, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+ .factor = 2,
+ .num_mask = GENMASK(12, 0),
+ .den_mask = GENMASK(12, 0),
+ .num_shift = 16,
+ .den_shift = 0,
+};
+
+static struct u32_fract uart_factor_tbl[] = {
+ {.numerator = 8125, .denominator = 1536}, /* 14.745MHz */
+};
+
+static DEFINE_SPINLOCK(pll1_lock);
+static struct mmp_param_general_gate_clk pll1_gate_clks[] = {
+ {PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CTRL, 29, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE_CTRL, 27, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE_CTRL, 26, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE_CTRL, 30, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_GATE_CTRL, 28, 0, &pll1_lock},
+};
+
+static void pxa1908_pll_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+ ARRAY_SIZE(fixed_rate_clks));
+
+ mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+ ARRAY_SIZE(fixed_factor_clks));
+
+ mmp_clk_register_factor("uart_pll", "pll1_d4",
+ CLK_SET_RATE_PARENT,
+ pxa_unit->mpmu_base + MPMU_UART_PLL,
+ &uart_factor_masks, uart_factor_tbl,
+ ARRAY_SIZE(uart_factor_tbl), NULL);
+
+}
+
+static DEFINE_SPINLOCK(pwm0_lock);
+static DEFINE_SPINLOCK(pwm2_lock);
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+
+static const char * const uart_parent_names[] = {"pll1_117", "uart_pll"};
+static const char * const ssp_parent_names[] = {"pll1_d16", "pll1_d48", "pll1_d24", "pll1_d12"};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+ {PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 3, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
+ {PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
+ {PXA1908_CLK_PWM0, "pwm0_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM0, 0x2, 2, 0, 0, &pwm0_lock},
+ {PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM1, 0x6, 2, 0, 0, NULL},
+ {PXA1908_CLK_PWM2, "pwm2_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM2, 0x2, 2, 0, 0, NULL},
+ {PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM3, 0x6, 2, 0, 0, NULL},
+ {PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 3, 0, 0, &uart0_lock},
+ {PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 3, 0, 0, &uart1_lock},
+};
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+ {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
+ {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
+ {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_SSP0, 4, 3, 0, NULL},
+ {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_SSP2, 4, 3, 0, NULL},
+};
+
+static void pxa1908_apb_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_clk_register_gate(NULL, "pwm01_apb_share", "pll1_d48",
+ CLK_SET_RATE_PARENT,
+ pxa_unit->apbc_base + APBC_PWM0,
+ 0x5, 1, 0, 0, &pwm0_lock);
+ mmp_clk_register_gate(NULL, "pwm23_apb_share", "pll1_d48",
+ CLK_SET_RATE_PARENT,
+ pxa_unit->apbc_base + APBC_PWM2,
+ 0x5, 1, 0, 0, &pwm2_lock);
+ mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+ ARRAY_SIZE(apbc_mux_clks));
+ mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+ ARRAY_SIZE(apbc_gate_clks));
+}
+
+static struct mmp_param_gate_clk apbcp_gate_clks[] = {
+ {PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
+ {PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, APBCP_TWSI2, 0x7, 0x3, 0x0, 0, NULL},
+ {PXA1908_CLK_AICER, "ripc_clk", NULL, 0, APBCP_AICER, 0x7, 0x2, 0x0, 0, NULL},
+};
+
+static struct mmp_param_mux_clk apbcp_mux_clks[] = {
+ {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
+};
+
+static void pxa1908_apb_p_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
+ ARRAY_SIZE(apbcp_mux_clks));
+ mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
+ ARRAY_SIZE(apbcp_gate_clks));
+}
+
+static DEFINE_SPINLOCK(sdh0_lock);
+static DEFINE_SPINLOCK(sdh1_lock);
+static DEFINE_SPINLOCK(sdh2_lock);
+
+static const char * const sdh_parent_names[] = {"pll1_416", "pll1_624"};
+
+static struct mmp_clk_mix_config sdh_mix_config = {
+ .reg_info = DEFINE_MIX_REG_INFO(3, 8, 2, 6, 11),
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+ {PXA1908_CLK_USB, "usb_clk", NULL, 0, APMU_USB, 0x9, 0x9, 0x1, 0, NULL},
+ {PXA1908_CLK_SDH0, "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock},
+ {PXA1908_CLK_SDH1, "sdh1_clk", "sdh1_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock},
+ {PXA1908_CLK_SDH2, "sdh2_clk", "sdh2_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock}
+};
+
+static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_register_general_gate_clks(unit, pll1_gate_clks,
+ pxa_unit->apmu_base, ARRAY_SIZE(pll1_gate_clks));
+
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;
+ mmp_clk_register_mix(NULL, "sdh0_mix_clk", sdh_parent_names,
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
+ &sdh_mix_config, &sdh0_lock);
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH1;
+ mmp_clk_register_mix(NULL, "sdh1_mix_clk", sdh_parent_names,
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
+ &sdh_mix_config, &sdh1_lock);
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH2;
+ mmp_clk_register_mix(NULL, "sdh2_mix_clk", sdh_parent_names,
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
+ &sdh_mix_config, &sdh2_lock);
+
+ mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+ ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void __init pxa1908_apbc_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->apbc_base = of_iomap(np, 0);
+ if (!pxa_unit->apbc_base) {
+ pr_err("failed to map apbc registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, APBC_NR_CLKS);
+
+ pxa1908_apb_periph_clk_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_apbc, "marvell,pxa1908-apbc", pxa1908_apbc_clk_init);
+
+static void __init pxa1908_apbcp_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->apbcp_base = of_iomap(np, 0);
+ if (!pxa_unit->apbcp_base) {
+ pr_err("failed to map apbcp registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, APBCP_NR_CLKS);
+
+ pxa1908_apb_p_periph_clk_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_apbcp, "marvell,pxa1908-apbcp", pxa1908_apbcp_clk_init);
+
+static void __init pxa1908_mpmu_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->mpmu_base = of_iomap(np, 0);
+ if (!pxa_unit->mpmu_base) {
+ pr_err("failed to map mpmu registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, MPMU_NR_CLKS);
+
+ pxa1908_pll_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_mpmu, "marvell,pxa1908-mpmu", pxa1908_mpmu_clk_init);
+
+static void __init pxa1908_apmu_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->apmu_base = of_iomap(np, 0);
+ if (!pxa_unit->apmu_base) {
+ pr_err("failed to map apmu registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, APMU_NR_CLKS);
+
+ pxa1908_axi_periph_clk_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_apmu, "marvell,pxa1908-apmu", pxa1908_apmu_clk_init);
--
2.44.0
^ permalink raw reply related
* [PATCH v9 1/9] clk: mmp: Switch to use struct u32_fract instead of custom one
From: Duje Mihanović @ 2024-04-02 20:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tony Lindgren, Haojian Zhuang,
Duje Mihanović, Lubomir Rintel, Catalin Marinas, Will Deacon,
Kees Cook, Tony Luck, Guilherme G. Piccoli, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, Karel Balej, David Wronek,
linux-clk, linux-kernel, linux-gpio, devicetree, linux-arm-kernel,
Andy Shevchenko
In-Reply-To: <20240402-pxa1908-lkml-v9-0-25a003e83c6f@skole.hr>
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The struct mmp_clk_factor_tbl repeats the generic struct u32_fract.
Kill the custom one and use the generic one instead.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Duje Mihanović <duje.mihanovic@skole.hr>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
drivers/clk/mmp/clk-frac.c | 57 ++++++++++++++++++++--------------------
drivers/clk/mmp/clk-of-mmp2.c | 26 +++++++++---------
drivers/clk/mmp/clk-of-pxa168.c | 4 +--
drivers/clk/mmp/clk-of-pxa1928.c | 6 ++---
drivers/clk/mmp/clk-of-pxa910.c | 4 +--
drivers/clk/mmp/clk.h | 10 +++----
6 files changed, 51 insertions(+), 56 deletions(-)
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
index 1b90867b60c4..6556f6ada2e8 100644
--- a/drivers/clk/mmp/clk-frac.c
+++ b/drivers/clk/mmp/clk-frac.c
@@ -26,14 +26,15 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
{
struct mmp_clk_factor *factor = to_clk_factor(hw);
u64 rate = 0, prev_rate;
+ struct u32_fract *d;
int i;
for (i = 0; i < factor->ftbl_cnt; i++) {
- prev_rate = rate;
- rate = *prate;
- rate *= factor->ftbl[i].den;
- do_div(rate, factor->ftbl[i].num * factor->masks->factor);
+ d = &factor->ftbl[i];
+ prev_rate = rate;
+ rate = (u64)(*prate) * d->denominator;
+ do_div(rate, d->numerator * factor->masks->factor);
if (rate > drate)
break;
}
@@ -52,23 +53,22 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
{
struct mmp_clk_factor *factor = to_clk_factor(hw);
struct mmp_clk_factor_masks *masks = factor->masks;
- unsigned int val, num, den;
+ struct u32_fract d;
+ unsigned int val;
u64 rate;
val = readl_relaxed(factor->base);
/* calculate numerator */
- num = (val >> masks->num_shift) & masks->num_mask;
+ d.numerator = (val >> masks->num_shift) & masks->num_mask;
/* calculate denominator */
- den = (val >> masks->den_shift) & masks->den_mask;
-
- if (!den)
+ d.denominator = (val >> masks->den_shift) & masks->den_mask;
+ if (!d.denominator)
return 0;
- rate = parent_rate;
- rate *= den;
- do_div(rate, num * factor->masks->factor);
+ rate = (u64)parent_rate * d.denominator;
+ do_div(rate, d.numerator * factor->masks->factor);
return rate;
}
@@ -82,18 +82,18 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
int i;
unsigned long val;
unsigned long flags = 0;
+ struct u32_fract *d;
u64 rate = 0;
for (i = 0; i < factor->ftbl_cnt; i++) {
- rate = prate;
- rate *= factor->ftbl[i].den;
- do_div(rate, factor->ftbl[i].num * factor->masks->factor);
+ d = &factor->ftbl[i];
+ rate = (u64)prate * d->denominator;
+ do_div(rate, d->numerator * factor->masks->factor);
if (rate > drate)
break;
}
- if (i > 0)
- i--;
+ d = i ? &factor->ftbl[i - 1] : &factor->ftbl[0];
if (factor->lock)
spin_lock_irqsave(factor->lock, flags);
@@ -101,10 +101,10 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
val = readl_relaxed(factor->base);
val &= ~(masks->num_mask << masks->num_shift);
- val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift;
+ val |= (d->numerator & masks->num_mask) << masks->num_shift;
val &= ~(masks->den_mask << masks->den_shift);
- val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift;
+ val |= (d->denominator & masks->den_mask) << masks->den_shift;
writel_relaxed(val, factor->base);
@@ -118,7 +118,8 @@ static int clk_factor_init(struct clk_hw *hw)
{
struct mmp_clk_factor *factor = to_clk_factor(hw);
struct mmp_clk_factor_masks *masks = factor->masks;
- u32 val, num, den;
+ struct u32_fract d;
+ u32 val;
int i;
unsigned long flags = 0;
@@ -128,23 +129,22 @@ static int clk_factor_init(struct clk_hw *hw)
val = readl(factor->base);
/* calculate numerator */
- num = (val >> masks->num_shift) & masks->num_mask;
+ d.numerator = (val >> masks->num_shift) & masks->num_mask;
/* calculate denominator */
- den = (val >> masks->den_shift) & masks->den_mask;
+ d.denominator = (val >> masks->den_shift) & masks->den_mask;
for (i = 0; i < factor->ftbl_cnt; i++)
- if (den == factor->ftbl[i].den && num == factor->ftbl[i].num)
+ if (d.denominator == factor->ftbl[i].denominator &&
+ d.numerator == factor->ftbl[i].numerator)
break;
if (i >= factor->ftbl_cnt) {
val &= ~(masks->num_mask << masks->num_shift);
- val |= (factor->ftbl[0].num & masks->num_mask) <<
- masks->num_shift;
+ val |= (factor->ftbl[0].numerator & masks->num_mask) << masks->num_shift;
val &= ~(masks->den_mask << masks->den_shift);
- val |= (factor->ftbl[0].den & masks->den_mask) <<
- masks->den_shift;
+ val |= (factor->ftbl[0].denominator & masks->den_mask) << masks->den_shift;
}
if (!(val & masks->enable_mask) || i >= factor->ftbl_cnt) {
@@ -168,8 +168,7 @@ static const struct clk_ops clk_factor_ops = {
struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
unsigned long flags, void __iomem *base,
struct mmp_clk_factor_masks *masks,
- struct mmp_clk_factor_tbl *ftbl,
- unsigned int ftbl_cnt, spinlock_t *lock)
+ struct u32_fract *ftbl, unsigned int ftbl_cnt, spinlock_t *lock)
{
struct mmp_clk_factor *factor;
struct clk_init_data init;
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index eaad36ee323d..a4f15cee630e 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -143,9 +143,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
.den_shift = 0,
};
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
- {.num = 8125, .den = 1536}, /*14.745MHZ */
- {.num = 3521, .den = 689}, /*19.23MHZ */
+static struct u32_fract uart_factor_tbl[] = {
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
+ { .numerator = 3521, .denominator = 689 }, /* 19.23MHZ */
};
static struct mmp_clk_factor_masks i2s_factor_masks = {
@@ -157,16 +157,16 @@ static struct mmp_clk_factor_masks i2s_factor_masks = {
.enable_mask = 0xd0000000,
};
-static struct mmp_clk_factor_tbl i2s_factor_tbl[] = {
- {.num = 24868, .den = 511}, /* 2.0480 MHz */
- {.num = 28003, .den = 793}, /* 2.8224 MHz */
- {.num = 24941, .den = 1025}, /* 4.0960 MHz */
- {.num = 28003, .den = 1586}, /* 5.6448 MHz */
- {.num = 31158, .den = 2561}, /* 8.1920 MHz */
- {.num = 16288, .den = 1845}, /* 11.2896 MHz */
- {.num = 20772, .den = 2561}, /* 12.2880 MHz */
- {.num = 8144, .den = 1845}, /* 22.5792 MHz */
- {.num = 10386, .den = 2561}, /* 24.5760 MHz */
+static struct u32_fract i2s_factor_tbl[] = {
+ { .numerator = 24868, .denominator = 511 }, /* 2.0480 MHz */
+ { .numerator = 28003, .denominator = 793 }, /* 2.8224 MHz */
+ { .numerator = 24941, .denominator = 1025 }, /* 4.0960 MHz */
+ { .numerator = 28003, .denominator = 1586 }, /* 5.6448 MHz */
+ { .numerator = 31158, .denominator = 2561 }, /* 8.1920 MHz */
+ { .numerator = 16288, .denominator = 1845 }, /* 11.2896 MHz */
+ { .numerator = 20772, .denominator = 2561 }, /* 12.2880 MHz */
+ { .numerator = 8144, .denominator = 1845 }, /* 22.5792 MHz */
+ { .numerator = 10386, .denominator = 2561 }, /* 24.5760 MHz */
};
static DEFINE_SPINLOCK(acgr_lock);
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c
index c5a7ba1deaa3..5f250427e60d 100644
--- a/drivers/clk/mmp/clk-of-pxa168.c
+++ b/drivers/clk/mmp/clk-of-pxa168.c
@@ -106,8 +106,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
.den_shift = 0,
};
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
- {.num = 8125, .den = 1536}, /*14.745MHZ */
+static struct u32_fract uart_factor_tbl[] = {
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
};
static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
diff --git a/drivers/clk/mmp/clk-of-pxa1928.c b/drivers/clk/mmp/clk-of-pxa1928.c
index 9def4b5f10e9..ebb6e278eda3 100644
--- a/drivers/clk/mmp/clk-of-pxa1928.c
+++ b/drivers/clk/mmp/clk-of-pxa1928.c
@@ -61,9 +61,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
.den_shift = 0,
};
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
- {.num = 832, .den = 234}, /*58.5MHZ */
- {.num = 1, .den = 1}, /*26MHZ */
+static struct u32_fract uart_factor_tbl[] = {
+ { .numerator = 832, .denominator = 234 }, /* 58.5MHZ */
+ { .numerator = 1, .denominator = 1 }, /* 26MHZ */
};
static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit)
diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c
index 7a38c424782e..fe65e7bdb411 100644
--- a/drivers/clk/mmp/clk-of-pxa910.c
+++ b/drivers/clk/mmp/clk-of-pxa910.c
@@ -86,8 +86,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
.den_shift = 0,
};
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
- {.num = 8125, .den = 1536}, /*14.745MHZ */
+static struct u32_fract uart_factor_tbl[] = {
+ { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */
};
static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit)
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
index 55ac05379781..c83cec169ddc 100644
--- a/drivers/clk/mmp/clk.h
+++ b/drivers/clk/mmp/clk.h
@@ -3,6 +3,7 @@
#define __MACH_MMP_CLK_H
#include <linux/clk-provider.h>
+#include <linux/math.h>
#include <linux/pm_domain.h>
#include <linux/clkdev.h>
@@ -20,16 +21,11 @@ struct mmp_clk_factor_masks {
unsigned int enable_mask;
};
-struct mmp_clk_factor_tbl {
- unsigned int num;
- unsigned int den;
-};
-
struct mmp_clk_factor {
struct clk_hw hw;
void __iomem *base;
struct mmp_clk_factor_masks *masks;
- struct mmp_clk_factor_tbl *ftbl;
+ struct u32_fract *ftbl;
unsigned int ftbl_cnt;
spinlock_t *lock;
};
@@ -37,7 +33,7 @@ struct mmp_clk_factor {
extern struct clk *mmp_clk_register_factor(const char *name,
const char *parent_name, unsigned long flags,
void __iomem *base, struct mmp_clk_factor_masks *masks,
- struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
+ struct u32_fract *ftbl, unsigned int ftbl_cnt,
spinlock_t *lock);
/* Clock type "mix" */
--
2.44.0
^ permalink raw reply related
* [PATCH v9 3/9] pinctrl: single: add marvell,pxa1908-padconf compatible
From: Duje Mihanović @ 2024-04-02 20:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tony Lindgren, Haojian Zhuang,
Duje Mihanović, Lubomir Rintel, Catalin Marinas, Will Deacon,
Kees Cook, Tony Luck, Guilherme G. Piccoli, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, Karel Balej, David Wronek,
linux-clk, linux-kernel, linux-gpio, devicetree, linux-arm-kernel
In-Reply-To: <20240402-pxa1908-lkml-v9-0-25a003e83c6f@skole.hr>
Add the "marvell,pxa1908-padconf" compatible to allow migrating to a
separate pinctrl driver later.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
drivers/pinctrl/pinctrl-single.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 19cc0db771a5..c15bf3cbabd7 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -1967,6 +1967,7 @@ static const struct pcs_soc_data pinconf_single = {
};
static const struct of_device_id pcs_of_match[] = {
+ { .compatible = "marvell,pxa1908-padconf", .data = &pinconf_single },
{ .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
{ .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 },
{ .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
--
2.44.0
^ permalink raw reply related
* [PATCH v9 7/9] arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform
From: Duje Mihanović @ 2024-04-02 20:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tony Lindgren, Haojian Zhuang,
Duje Mihanović, Lubomir Rintel, Catalin Marinas, Will Deacon,
Kees Cook, Tony Luck, Guilherme G. Piccoli, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, Karel Balej, David Wronek,
linux-clk, linux-kernel, linux-gpio, devicetree, linux-arm-kernel
In-Reply-To: <20240402-pxa1908-lkml-v9-0-25a003e83c6f@skole.hr>
Add ARCH_MMP configuration option for Marvell PXA1908 SoC.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
arch/arm64/Kconfig.platforms | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 24335565bad5..d71b0b6e75aa 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -168,6 +168,14 @@ config ARCH_MESON
This enables support for the arm64 based Amlogic SoCs
such as the s905, S905X/D, S912, A113X/D or S905X/D2
+config ARCH_MMP
+ bool "Marvell MMP SoC Family"
+ select PINCTRL
+ select PINCTRL_SINGLE
+ help
+ This enables support for Marvell MMP SoC family, currently
+ supporting PXA1908 aka IAP140.
+
config ARCH_MVEBU
bool "Marvell EBU SoC Family"
select ARMADA_AP806_SYSCON
--
2.44.0
^ permalink raw reply related
* [PATCH v9 2/9] dt-bindings: pinctrl: pinctrl-single: add marvell,pxa1908-padconf compatible
From: Duje Mihanović @ 2024-04-02 20:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tony Lindgren, Haojian Zhuang,
Duje Mihanović, Lubomir Rintel, Catalin Marinas, Will Deacon,
Kees Cook, Tony Luck, Guilherme G. Piccoli, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, Karel Balej, David Wronek,
linux-clk, linux-kernel, linux-gpio, devicetree, linux-arm-kernel
In-Reply-To: <20240402-pxa1908-lkml-v9-0-25a003e83c6f@skole.hr>
Add the "marvell,pxa1908-padconf" compatible to allow migrating to a
separate pinctrl driver later.
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
index c11495524dd2..1ce24ad8bc73 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
@@ -33,6 +33,10 @@ properties:
- ti,omap5-padconf
- ti,j7200-padconf
- const: pinctrl-single
+ - items:
+ - enum:
+ - marvell,pxa1908-padconf
+ - const: pinconf-single
reg:
maxItems: 1
--
2.44.0
^ permalink raw reply related
* [PATCH v9 4/9] dt-bindings: clock: Add Marvell PXA1908 clock bindings
From: Duje Mihanović @ 2024-04-02 20:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tony Lindgren, Haojian Zhuang,
Duje Mihanović, Lubomir Rintel, Catalin Marinas, Will Deacon,
Kees Cook, Tony Luck, Guilherme G. Piccoli, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, Karel Balej, David Wronek,
linux-clk, linux-kernel, linux-gpio, devicetree, linux-arm-kernel,
Conor Dooley
In-Reply-To: <20240402-pxa1908-lkml-v9-0-25a003e83c6f@skole.hr>
Add dt bindings and documentation for the Marvell PXA1908 clock
controller.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
.../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++++
include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++++++++++++++++++
2 files changed, 136 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
new file mode 100644
index 000000000000..4e78933232b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell PXA1908 Clock Controllers
+
+maintainers:
+ - Duje Mihanović <duje.mihanovic@skole.hr>
+
+description: |
+ The PXA1908 clock subsystem generates and supplies clock to various
+ controllers within the PXA1908 SoC. The PXA1908 contains numerous clock
+ controller blocks, with the ones currently supported being APBC, APBCP, MPMU
+ and APMU roughly corresponding to internal buses.
+
+ All these clock identifiers could be found in <include/dt-bindings/marvell,pxa1908.h>.
+
+properties:
+ compatible:
+ enum:
+ - marvell,pxa1908-apbc
+ - marvell,pxa1908-apbcp
+ - marvell,pxa1908-mpmu
+ - marvell,pxa1908-apmu
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # APMU block:
+ - |
+ clock-controller@d4282800 {
+ compatible = "marvell,pxa1908-apmu";
+ reg = <0xd4282800 0x400>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h
new file mode 100644
index 000000000000..fb15b0d0cd4c
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,pxa1908.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+#ifndef __DTS_MARVELL_PXA1908_CLOCK_H
+#define __DTS_MARVELL_PXA1908_CLOCK_H
+
+/* plls */
+#define PXA1908_CLK_CLK32 1
+#define PXA1908_CLK_VCTCXO 2
+#define PXA1908_CLK_PLL1_624 3
+#define PXA1908_CLK_PLL1_416 4
+#define PXA1908_CLK_PLL1_499 5
+#define PXA1908_CLK_PLL1_832 6
+#define PXA1908_CLK_PLL1_1248 7
+#define PXA1908_CLK_PLL1_D2 8
+#define PXA1908_CLK_PLL1_D4 9
+#define PXA1908_CLK_PLL1_D8 10
+#define PXA1908_CLK_PLL1_D16 11
+#define PXA1908_CLK_PLL1_D6 12
+#define PXA1908_CLK_PLL1_D12 13
+#define PXA1908_CLK_PLL1_D24 14
+#define PXA1908_CLK_PLL1_D48 15
+#define PXA1908_CLK_PLL1_D96 16
+#define PXA1908_CLK_PLL1_D13 17
+#define PXA1908_CLK_PLL1_32 18
+#define PXA1908_CLK_PLL1_208 19
+#define PXA1908_CLK_PLL1_117 20
+#define PXA1908_CLK_PLL1_416_GATE 21
+#define PXA1908_CLK_PLL1_624_GATE 22
+#define PXA1908_CLK_PLL1_832_GATE 23
+#define PXA1908_CLK_PLL1_1248_GATE 24
+#define PXA1908_CLK_PLL1_D2_GATE 25
+#define PXA1908_CLK_PLL1_499_EN 26
+#define PXA1908_CLK_PLL2VCO 27
+#define PXA1908_CLK_PLL2 28
+#define PXA1908_CLK_PLL2P 29
+#define PXA1908_CLK_PLL2VCODIV3 30
+#define PXA1908_CLK_PLL3VCO 31
+#define PXA1908_CLK_PLL3 32
+#define PXA1908_CLK_PLL3P 33
+#define PXA1908_CLK_PLL3VCODIV3 34
+#define PXA1908_CLK_PLL4VCO 35
+#define PXA1908_CLK_PLL4 36
+#define PXA1908_CLK_PLL4P 37
+#define PXA1908_CLK_PLL4VCODIV3 38
+
+/* apb (apbc) peripherals */
+#define PXA1908_CLK_UART0 1
+#define PXA1908_CLK_UART1 2
+#define PXA1908_CLK_GPIO 3
+#define PXA1908_CLK_PWM0 4
+#define PXA1908_CLK_PWM1 5
+#define PXA1908_CLK_PWM2 6
+#define PXA1908_CLK_PWM3 7
+#define PXA1908_CLK_SSP0 8
+#define PXA1908_CLK_SSP1 9
+#define PXA1908_CLK_IPC_RST 10
+#define PXA1908_CLK_RTC 11
+#define PXA1908_CLK_TWSI0 12
+#define PXA1908_CLK_KPC 13
+#define PXA1908_CLK_SWJTAG 14
+#define PXA1908_CLK_SSP2 15
+#define PXA1908_CLK_TWSI1 16
+#define PXA1908_CLK_THERMAL 17
+#define PXA1908_CLK_TWSI3 18
+
+/* apb (apbcp) peripherals */
+#define PXA1908_CLK_UART2 1
+#define PXA1908_CLK_TWSI2 2
+#define PXA1908_CLK_AICER 3
+
+/* axi (apmu) peripherals */
+#define PXA1908_CLK_CCIC1 1
+#define PXA1908_CLK_ISP 2
+#define PXA1908_CLK_DSI1 3
+#define PXA1908_CLK_DISP1 4
+#define PXA1908_CLK_CCIC0 5
+#define PXA1908_CLK_SDH0 6
+#define PXA1908_CLK_SDH1 7
+#define PXA1908_CLK_USB 8
+#define PXA1908_CLK_NF 9
+#define PXA1908_CLK_CORE_DEBUG 10
+#define PXA1908_CLK_VPU 11
+#define PXA1908_CLK_GC 12
+#define PXA1908_CLK_SDH2 13
+#define PXA1908_CLK_GC2D 14
+#define PXA1908_CLK_TRACE 15
+#define PXA1908_CLK_DVC_DFC_DEBUG 16
+
+#endif
--
2.44.0
^ permalink raw reply related
* [PATCH v9 6/9] dt-bindings: marvell: Document PXA1908 SoC
From: Duje Mihanović @ 2024-04-02 20:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tony Lindgren, Haojian Zhuang,
Duje Mihanović, Lubomir Rintel, Catalin Marinas, Will Deacon,
Kees Cook, Tony Luck, Guilherme G. Piccoli, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, Karel Balej, David Wronek,
linux-clk, linux-kernel, linux-gpio, devicetree, linux-arm-kernel,
Krzysztof Kozlowski
In-Reply-To: <20240402-pxa1908-lkml-v9-0-25a003e83c6f@skole.hr>
Add dt binding for the Marvell PXA1908 SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
index 4c43eaf3632e..f73bb8ec3a1a 100644
--- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
@@ -35,6 +35,11 @@ properties:
- enum:
- dell,wyse-ariel
- const: marvell,mmp3
+ - description: PXA1908 based boards
+ items:
+ - enum:
+ - samsung,coreprimevelte
+ - const: marvell,pxa1908
additionalProperties: true
--
2.44.0
^ permalink raw reply related
* [PATCH v9 0/9] Initial Marvell PXA1908 support
From: Duje Mihanović @ 2024-04-02 20:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tony Lindgren, Haojian Zhuang,
Duje Mihanović, Lubomir Rintel, Catalin Marinas, Will Deacon,
Kees Cook, Tony Luck, Guilherme G. Piccoli, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, Karel Balej, David Wronek,
linux-clk, linux-kernel, linux-gpio, devicetree, linux-arm-kernel,
Andy Shevchenko, Conor Dooley, Krzysztof Kozlowski
Hello,
This series adds initial support for the Marvell PXA1908 SoC and
"samsung,coreprimevelte", a smartphone using the SoC.
USB works and the phone can boot a rootfs from an SD card, but there are
some warnings in the dmesg:
During SMP initialization:
[ 0.006519] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU1: 0x00000000000000
[ 0.006542] CPU features: Unsupported CPU feature variation detected.
[ 0.006589] CPU1: Booted secondary processor 0x0000000001 [0x410fd032]
[ 0.010710] Detected VIPT I-cache on CPU2
[ 0.010716] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU2: 0x00000000000000
[ 0.010758] CPU2: Booted secondary processor 0x0000000002 [0x410fd032]
[ 0.014849] Detected VIPT I-cache on CPU3
[ 0.014855] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU3: 0x00000000000000
[ 0.014895] CPU3: Booted secondary processor 0x0000000003 [0x410fd032]
SMMU probing fails:
[ 0.101798] arm-smmu c0010000.iommu: probing hardware configuration...
[ 0.101809] arm-smmu c0010000.iommu: SMMUv1 with:
[ 0.101816] arm-smmu c0010000.iommu: no translation support!
A 3.14 based Marvell tree is available on GitHub
acorn-marvell/brillo_pxa_kernel, and a Samsung one on GitHub
CoderCharmander/g361f-kernel.
Andreas Färber attempted to upstream support for this SoC in 2017:
https://lore.kernel.org/lkml/20170222022929.10540-1-afaerber@suse.de/
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Changes in v9:
- Update trailers and rebase on v6.9-rc2, no changes
- Link to v8: https://lore.kernel.org/20240110-pxa1908-lkml-v8-0-fea768a59474@skole.hr
Changes in v8:
- Drop SSPA patch
- Drop broken-cd from eMMC node
- Specify S-Boot hardcoded initramfs location in device tree
- Add ARM PMU node
- Correct inverted modem memory base and size
- Update trailers
- Rebase on next-20240110
- Link to v7: https://lore.kernel.org/20231102-pxa1908-lkml-v7-0-cabb1a0cb52b@skole.hr
and https://lore.kernel.org/20231102152033.5511-1-duje.mihanovic@skole.hr
Changes in v7:
- Suppress SND_MMP_SOC_SSPA on ARM64
- Update trailers
- Rebase on v6.6-rc7
- Link to v6: https://lore.kernel.org/r/20231010-pxa1908-lkml-v6-0-b2fe09240cf8@skole.hr
Changes in v6:
- Address maintainer comments:
- Add "marvell,pxa1908-padconf" binding to pinctrl-single driver
- Drop GPIO patch as it's been pulled
- Update trailers
- Rebase on v6.6-rc5
- Link to v5: https://lore.kernel.org/r/20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr
Changes in v5:
- Address maintainer comments:
- Move *_NR_CLKS to clock driver from dt binding file
- Allocate correct number of clocks for each block instead of blindly
allocating 50 for each
- Link to v4: https://lore.kernel.org/r/20230807-pxa1908-lkml-v4-0-cb387d73b452@skole.hr
Changes in v4:
- Address maintainer comments:
- Relicense clock binding file to BSD-2
- Add pinctrl-names to SD card node
- Add vgic registers to GIC node
- Rebase on v6.5-rc5
- Link to v3: https://lore.kernel.org/r/20230804-pxa1908-lkml-v3-0-8e48fca37099@skole.hr
Changes in v3:
- Address maintainer comments:
- Drop GPIO dynamic allocation patch
- Move clock register offsets into driver (instead of bindings file)
- Add missing Tested-by trailer to u32_fract patch
- Move SoC binding to arm/mrvl/mrvl.yaml
- Add serial0 alias and stdout-path to board dts to enable UART
debugging
- Rebase on v6.5-rc4
- Link to v2: https://lore.kernel.org/r/20230727162909.6031-1-duje.mihanovic@skole.hr
Changes in v2:
- Remove earlycon patch as it's been merged into tty-next
- Address maintainer comments:
- Clarify GPIO regressions on older PXA platforms
- Add Fixes tag to commit disabling GPIO pinctrl calls for this SoC
- Add missing includes to clock driver
- Clock driver uses HZ_PER_MHZ, u32_fract and GENMASK
- Dual license clock bindings
- Change clock IDs to decimal
- Fix underscores in dt node names
- Move chosen node to top of board dts
- Clean up documentation
- Reorder commits
- Drop pxa,rev-id
- Rename muic-i2c to i2c-muic
- Reword some commits
- Move framebuffer node to chosen
- Add aliases for mmc nodes
- Rebase on v6.5-rc3
- Link to v1: https://lore.kernel.org/r/20230721210042.21535-1-duje.mihanovic@skole.hr
---
Andy Shevchenko (1):
clk: mmp: Switch to use struct u32_fract instead of custom one
Duje Mihanović (8):
dt-bindings: pinctrl: pinctrl-single: add marvell,pxa1908-padconf compatible
pinctrl: single: add marvell,pxa1908-padconf compatible
dt-bindings: clock: Add Marvell PXA1908 clock bindings
clk: mmp: Add Marvell PXA1908 clock driver
dt-bindings: marvell: Document PXA1908 SoC
arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform
arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte
MAINTAINERS: add myself as Marvell PXA1908 maintainer
.../devicetree/bindings/arm/mrvl/mrvl.yaml | 5 +
.../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 +++
.../bindings/pinctrl/pinctrl-single.yaml | 4 +
MAINTAINERS | 9 +
arch/arm64/Kconfig.platforms | 8 +
arch/arm64/boot/dts/marvell/Makefile | 3 +
.../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 336 +++++++++++++++++++++
arch/arm64/boot/dts/marvell/pxa1908.dtsi | 304 +++++++++++++++++++
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-frac.c | 57 ++--
drivers/clk/mmp/clk-of-mmp2.c | 26 +-
drivers/clk/mmp/clk-of-pxa168.c | 4 +-
drivers/clk/mmp/clk-of-pxa1908.c | 328 ++++++++++++++++++++
drivers/clk/mmp/clk-of-pxa1928.c | 6 +-
drivers/clk/mmp/clk-of-pxa910.c | 4 +-
drivers/clk/mmp/clk.h | 10 +-
drivers/pinctrl/pinctrl-single.c | 1 +
include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++
18 files changed, 1186 insertions(+), 57 deletions(-)
---
base-commit: 39cd87c4eb2b893354f3b850f916353f2658ae6f
change-id: 20230803-pxa1908-lkml-6830e8da45c7
Best regards,
--
Duje Mihanović <duje.mihanovic@skole.hr>
^ permalink raw reply
* Re: [PATCH v3 2/4] drm/mipi-dsi: use correct return type for the DSC functions
From: Marijn Suijten @ 2024-04-02 21:00 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Sumit Semwal, Caleb Connolly, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, dri-devel, devicetree,
linux-kernel, linux-arm-msm
In-Reply-To: <20240402-lg-sw43408-panel-v3-2-144f17a11a56@linaro.org>
On 2024-04-02 02:51:13, Dmitry Baryshkov wrote:
> The functions mipi_dsi_compression_mode() and
> mipi_dsi_picture_parameter_set() return 0-or-error rather than a buffer
> size. Follow example of other similar MIPI DSI functions and use int
> return type instead of size_t.
>
> Fixes: f4dea1aaa9a1 ("drm/dsi: add helpers for DSI compression mode and PPS packets")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 6 +++---
> include/drm/drm_mipi_dsi.h | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index ef6e416522f8..9874ff6d4718 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -654,7 +654,7 @@ EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size);
> *
> * Return: 0 on success or a negative error code on failure.
> */
> -ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable)
> +int mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable)
> {
> /* Note: Needs updating for non-default PPS or algorithm */
> u8 tx[2] = { enable << 0, 0 };
> @@ -679,8 +679,8 @@ EXPORT_SYMBOL(mipi_dsi_compression_mode);
> *
> * Return: 0 on success or a negative error code on failure.
> */
> -ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
> - const struct drm_dsc_picture_parameter_set *pps)
> +int mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
> + const struct drm_dsc_picture_parameter_set *pps)
> {
> struct mipi_dsi_msg msg = {
> .channel = dsi->channel,
> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
> index c0aec0d4d664..3011d33eccbd 100644
> --- a/include/drm/drm_mipi_dsi.h
> +++ b/include/drm/drm_mipi_dsi.h
> @@ -241,9 +241,9 @@ int mipi_dsi_shutdown_peripheral(struct mipi_dsi_device *dsi);
> int mipi_dsi_turn_on_peripheral(struct mipi_dsi_device *dsi);
> int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
> u16 value);
> -ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable);
> -ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
> - const struct drm_dsc_picture_parameter_set *pps);
> +int mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable);
> +int mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
> + const struct drm_dsc_picture_parameter_set *pps);
>
> ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload,
> size_t size);
>
> --
> 2.39.2
>
^ permalink raw reply
* Re: [PATCH v3 1/4] dt-bindings: panel: Add LG SW43408 MIPI-DSI panel
From: Marijn Suijten @ 2024-04-02 20:59 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Krzysztof Kozlowski, Sumit Semwal, Caleb Connolly, Neil Armstrong,
Jessica Zhang, Sam Ravnborg, David Airlie, Daniel Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, dri-devel, devicetree,
linux-kernel, linux-arm-msm, Vinod Koul, Caleb Connolly
In-Reply-To: <CAA8EJprwWd=ZtwnpTm3cVP8RBEqxCcSGyBu-bHj=iV=+X2=FyQ@mail.gmail.com>
On 2024-04-02 10:23:22, Dmitry Baryshkov wrote:
> On Tue, 2 Apr 2024 at 09:31, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
> >
> > On 02/04/2024 01:51, Dmitry Baryshkov wrote:
> > > From: Sumit Semwal <sumit.semwal@linaro.org>
> > >
> > > LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel present on Google Pixel 3
> > > phones.
> > >
> > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > > Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
> > > [caleb: convert to yaml]
> > > Signed-off-by: Caleb Connolly <caleb@connolly.tech>
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > ---
> >
> > Tags missing.
> >
> > `b4 trailers -u`
>
> Excuse me, I keep on forgetting it.
Does a similar thing exist for adding Cc: tags for all reviewers/replyers to an
earlier version, even if said reviewer didn't yet provide R-b/A-b or other tags?
I'd like to have the next revisions in my inbox as well after leaving
comments :)
Thanks! - Marijn
^ permalink raw reply
* Re: [PATCH 3/3] drm: panel: Add LG sw43408 panel driver
From: Marijn Suijten @ 2024-04-02 20:57 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Sumit Semwal, Caleb Connolly, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, dri-devel, devicetree,
linux-kernel, linux-arm-msm, Vinod Koul, Caleb Connolly
In-Reply-To: <CAA8EJprRHg2KH7H6SPF3yfg8HCT2Fe2Hg-LXU19ak78TkKWwjA@mail.gmail.com>
On 2024-04-01 22:11:48, Dmitry Baryshkov wrote:
> On Mon, 1 Apr 2024 at 13:29, Marijn Suijten
> <marijn.suijten@somainline.org> wrote:
> >
> > On 2024-03-30 16:37:08, Dmitry Baryshkov wrote:
> > > On Sat, 30 Mar 2024 at 12:27, Marijn Suijten
> > > <marijn.suijten@somainline.org> wrote:
> > > >
> > > > On 2024-03-30 05:59:30, Dmitry Baryshkov wrote:
> > > > > From: Sumit Semwal <sumit.semwal@linaro.org>
> > > > >
> > > > > LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel, used in some Pixel3
> > > > > phones.
> > > > >
> > > > > Whatever init sequence we have for this panel isn't capable of
> > > > > initialising it completely, toggling the reset gpio ever causes the
> > > > > panel to die. Until this is resolved we avoid resetting the panel. The
> > > >
> > > > Are you sure it is avoided? This patch seems to be toggling reset_gpio in
> > > > sw43408_prepare()?
> > > >
> > > > > disable/unprepare functions only put the panel to sleep mode and
> > > > > disable the backlight.
> > > > >
> > > > > Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
> > > > > [vinod: Add DSC support]
> > > > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > > > > [caleb: cleanup and support turning off the panel]
> > > > > Signed-off-by: Caleb Connolly <caleb@connolly.tech>
> > > > > [DB: partially rewrote the driver and fixed DSC programming]
> > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > > > ---
> > > > > MAINTAINERS | 8 +
> > > > > drivers/gpu/drm/panel/Kconfig | 11 ++
> > > > > drivers/gpu/drm/panel/Makefile | 1 +
> > > > > drivers/gpu/drm/panel/panel-lg-sw43408.c | 322 +++++++++++++++++++++++++++++++
> > > > > 4 files changed, 342 insertions(+)
> > > > >
> > > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > > index 4b511a55101c..f4cf7ee97376 100644
> > > > > --- a/MAINTAINERS
> > > > > +++ b/MAINTAINERS
> > > > > @@ -6755,6 +6755,14 @@ S: Maintained
> > > > > F: Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
> > > > > F: drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
> > > > >
> > > > > +DRM DRIVER FOR LG SW43408 PANELS
> > > > > +M: Sumit Semwal <sumit.semwal@linaro.org>
> > > > > +M: Caleb Connolly <caleb.connolly@linaro.org>
> > > > > +S: Maintained
> > > > > +T: git git://anongit.freedesktop.org/drm/drm-misc
> > > > > +F: Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml
> > > > > +F: drivers/gpu/drm/panel/panel-lg-sw43408.c
> > > > > +
> > > > > DRM DRIVER FOR LOGICVC DISPLAY CONTROLLER
> > > > > M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> > > > > S: Supported
> > > > > diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> > > > > index d037b3b8b999..f94c702735cb 100644
> > > > > --- a/drivers/gpu/drm/panel/Kconfig
> > > > > +++ b/drivers/gpu/drm/panel/Kconfig
> > > > > @@ -335,6 +335,17 @@ config DRM_PANEL_LG_LG4573
> > > > > Say Y here if you want to enable support for LG4573 RGB panel.
> > > > > To compile this driver as a module, choose M here.
> > > > >
> > > > > +config DRM_PANEL_LG_SW43408
> > > > > + tristate "LG SW43408 panel"
> > > > > + depends on OF
> > > > > + depends on DRM_MIPI_DSI
> > > > > + depends on BACKLIGHT_CLASS_DEVICE
> > > > > + help
> > > > > + Say Y here if you want to enable support for LG sw43408 panel.
> > > > > + The panel has a 1080x2160 resolution and uses
> > > > > + 24 bit RGB per pixel. It provides a MIPI DSI interface to
> > > > > + the host and has a built-in LED backlight.
> > > > > +
> > > > > config DRM_PANEL_MAGNACHIP_D53E6EA8966
> > > > > tristate "Magnachip D53E6EA8966 DSI panel"
> > > > > depends on OF && SPI
> > > > > diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> > > > > index f156d7fa0bcc..a75687d13caf 100644
> > > > > --- a/drivers/gpu/drm/panel/Makefile
> > > > > +++ b/drivers/gpu/drm/panel/Makefile
> > > > > @@ -34,6 +34,7 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) += panel-leadtek-ltk050h3146w.o
> > > > > obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) += panel-leadtek-ltk500hd1829.o
> > > > > obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o
> > > > > obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
> > > > > +obj-$(CONFIG_DRM_PANEL_LG_SW43408) += panel-lg-sw43408.o
> > > > > obj-$(CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966) += panel-magnachip-d53e6ea8966.o
> > > > > obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
> > > > > obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o
> > > > > diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/panel/panel-lg-sw43408.c
> > > > > new file mode 100644
> > > > > index 000000000000..365d25e14d54
> > > > > --- /dev/null
> > > > > +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c
> > > > > @@ -0,0 +1,322 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright (C) 2019-2024 Linaro Ltd
> > > > > + * Author: Sumit Semwal <sumit.semwal@linaro.org>
> > > > > + * Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > > > + */
> > > > > +
> > > > > +#include <linux/backlight.h>
> > > > > +#include <linux/delay.h>
> > > > > +#include <linux/gpio/consumer.h>
> > > > > +#include <linux/module.h>
> > > > > +#include <linux/of.h>
> > > > > +#include <linux/regulator/consumer.h>
> > > > > +
> > > > > +#include <video/mipi_display.h>
> > > > > +
> > > > > +#include <drm/drm_mipi_dsi.h>
> > > > > +#include <drm/drm_panel.h>
> > > > > +#include <drm/drm_probe_helper.h>
> > > > > +#include <drm/display/drm_dsc.h>
> > > > > +#include <drm/display/drm_dsc_helper.h>
> > > > > +
> > > > > +#define NUM_SUPPLIES 2
> > > > > +
> > > > > +struct sw43408_panel {
> > > > > + struct drm_panel base;
> > > > > + struct mipi_dsi_device *link;
> > > > > +
> > > > > + const struct drm_display_mode *mode;
> > > > > +
> > > > > + struct regulator_bulk_data supplies[NUM_SUPPLIES];
> > > > > +
> > > > > + struct gpio_desc *reset_gpio;
> > > > > +};
> > > > > +
> > > > > +static inline struct sw43408_panel *to_panel_info(struct drm_panel *panel)
> > > > > +{
> > > > > + return container_of(panel, struct sw43408_panel, base);
> > > > > +}
> > > > > +
> > > > > +static int sw43408_unprepare(struct drm_panel *panel)
> > > > > +{
> > > > > + struct sw43408_panel *ctx = to_panel_info(panel);
> > > > > + int ret;
> > > > > +
> > > > > + ret = mipi_dsi_dcs_set_display_off(ctx->link);
> > > > > + if (ret < 0)
> > > > > + dev_err(panel->dev, "set_display_off cmd failed ret = %d\n", ret);
> > > > > +
> > > > > + ret = mipi_dsi_dcs_enter_sleep_mode(ctx->link);
> > > > > + if (ret < 0)
> > > > > + dev_err(panel->dev, "enter_sleep cmd failed ret = %d\n", ret);
> > > > > +
> > > > > + msleep(100);
> > > > > +
> > > > > + gpiod_set_value(ctx->reset_gpio, 1);
> > > > > +
> > > > > + return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
> > > > > +}
> > > > > +
> > > > > +static int sw43408_program(struct drm_panel *panel)
> > > > > +{
> > > > > + struct sw43408_panel *ctx = to_panel_info(panel);
> > > > > + struct drm_dsc_picture_parameter_set pps;
> > > > > + u8 dsc_en = 0x11;
> > > >
> > > > Yeah, this is completely strange. Bit 0, 0x1, is to enable DSC which is
> > > > normal. 0x10 however, which is bit 4, selects PPS table 2. Do you ever set
> > > > pps_identifier in struct drm_dsc_picture_parameter_set to 2? Or is the table
> > > > that you send below bogus and/or not used? Maybe the Driver IC on the other
> > > > end of the DSI link has a default PPS table with identifier 2 that works out of
> > > > the box?
> > >
> > > Note, MIPI standard also requires two bytes argument. I suspect that
> > > LG didn't fully follow the standard here.
> >
> > Have you read this command from downstream DTS, or have you tried sending 2
> > bytes and seen the panel breaking? The second byte is marked as reserved and
> > should be equal to 0; if the Driver IC is okay with sending either 1 or 2 bytes
> > I'd strive to stick with the defined length of 2 bytes for this DCS.
> >
> > Have you played around with the PPS table? What if you change
> > drm_dsc_picture_paremeter_set::pps_identifier to the second table, will the
> > panel stop working as expected again? This could indicate that the PPS that is
> > sent is incorrect (even though the information in the original DSC config was
> > enough to set up the DPU and DSI correctly).
> >
> > According to the DSI spec it is allowed to have a pre-stored/pre-programmed
> > PPS table, which could be used here making the current call to
> > mipi_dsi_picture_parameter_set() useless and "confusing"?
>
> Ok, some short summary of my tests.
>
> Skipping PPS doesn't work at all, so there is no default.
>
> Adding a second zero byte doesn't seem to change anything. Dropping
> the 0x1 bit ('enable') doesn't seem to change anything.
>
> If I send COMPRESSION_MODE before sending the PPS, various combinations work.
> If I send COMPRESSION_MODE after sending the PPS, the follow combos work:
>
> pps_identifier = 0x0, COMPRESSION_MODE = 0x11
> pps_identifier = 0x1, COMPRESSION_MODE = 0x21
Thanks, this must really be an off-by-one table identifier. I presume you've
tested pps_identifier=0x2 with COMPRESSION_MODE=0x31, and that there are only 2
tables and not 3 or 4?
From this we can also assume that sending a new PPS will automatically switch
the compression mode to the pps_identifier in that PPS, COMPRESSION_MODE doesn't
seem to affect it when sent too early.
> > > Basically that's the reason why I went for the _raw function instead
> > > of adding PPS and codec arguments to the existing function.
> > >
> > > >
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, MIPI_DCS_SET_GAMMA_CURVE, 0x02);
> > > > > +
> > > > > + mipi_dsi_dcs_set_tear_on(ctx->link, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
> > > > > +
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, 0x53, 0x0c, 0x30);
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, 0x55, 0x00, 0x70, 0xdf, 0x00, 0x70, 0xdf);
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, 0xf7, 0x01, 0x49, 0x0c);
> > > > > +
> > > > > + mipi_dsi_dcs_exit_sleep_mode(ctx->link);
> > > > > +
> > > > > + msleep(135);
> > > > > +
> > > > > + mipi_dsi_compression_mode_raw(ctx->link, &dsc_en, 1);
> > > >
> > > > Even though I think we should change this function to describe the known
> > > > bit layout of command 0x7 per the VESA DSI spec, for now replace 1 with
> > > > sizeof(dsc_en)?
> > >
> > > If dsc_en were an array, it would have been a proper thing. Maybe I
> > > should change it to the array to remove confusion.
> >
> > It should work even with a single byte, just to clarify to readers that the 3rd
> > argument is the byte-size of the input.
> >
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, 0xb0, 0xac);
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, 0xe5,
> > > > > + 0x00, 0x3a, 0x00, 0x3a, 0x00, 0x0e, 0x10);
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, 0xb5,
> > > > > + 0x75, 0x60, 0x2d, 0x5d, 0x80, 0x00, 0x0a, 0x0b,
> > > > > + 0x00, 0x05, 0x0b, 0x00, 0x80, 0x0d, 0x0e, 0x40,
> > > > > + 0x00, 0x0c, 0x00, 0x16, 0x00, 0xb8, 0x00, 0x80,
> > > > > + 0x0d, 0x0e, 0x40, 0x00, 0x0c, 0x00, 0x16, 0x00,
> > > > > + 0xb8, 0x00, 0x81, 0x00, 0x03, 0x03, 0x03, 0x01,
> > > > > + 0x01);
> > > > > + msleep(85);
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, 0xcd,
> > > > > + 0x00, 0x00, 0x00, 0x19, 0x19, 0x19, 0x19, 0x19,
> > > > > + 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
> > > > > + 0x16, 0x16);
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, 0xcb, 0x80, 0x5c, 0x07, 0x03, 0x28);
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, 0xc0, 0x02, 0x02, 0x0f);
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, 0x55, 0x04, 0x61, 0xdb, 0x04, 0x70, 0xdb);
> > > > > + mipi_dsi_dcs_write_seq(ctx->link, 0xb0, 0xca);
> > > > > +
> > > > > + mipi_dsi_dcs_set_display_on(ctx->link);
> > > >
> > > > Any specific reason to not have the (un)blanking sequence in the enable/disable
> > > > callbacks and leaving display configuration in (un)prepare?
> > >
> > > We are back to the question on when it's fine to send the commands. I
> > > think the current agreement is to send everything in the
> > > prepare/unprepare, because of some strange hosts.
> >
> > For my panel drivers I'm sticking with having `post-on` commands (from
> > downstream) in `enable/disable`, which is typically only `set_display_on`. In
> > hopes of proposing a `prepare_atomic()` some time to allow mode selection.
> >
> > In a short test on recent -next I am once again allowed to send DSI commands in
> > both .disable and .unprepare, making both functions a "clean" inverse of .enable
> > and .prepare respectively.
>
> The world isn't limited to the MSM hosts.
If I'm not mistaken this was an ordering issue in the drm_bridge implementation.
But you are right that some hosts might not be all too happy with sending
commands (like unblanking?) after the cmd/video stream started, and before the
stream stops. Which, as far as I know, are what .enable and .disable do. On
the other hand, I was under the impression that this split mainly existed to do
all the heavy/required lifting up-front, and only unblank when there's a video
signal to combat any possible observed corruption?
In the end I'm just curious if there's a specific reason - that I need
to take into account when resending all my panel patches - to /not/
use .enable/.disable?
- Marijn
> > > > > + msleep(50);
> > > > > +
> > > > > + ctx->link->mode_flags &= ~MIPI_DSI_MODE_LPM;
> > > > > +
> > > > > + drm_dsc_pps_payload_pack(&pps, ctx->link->dsc);
> > > > > + mipi_dsi_picture_parameter_set(ctx->link, &pps);
> > > >
> > > > I'm always surprised why this is sent _after_ turning the display on (unblanking
> > > > it). Wouldn't that cause unnecessary corruption?
> > >
> > > No idea. I followed the dowsntream command sequences here. Most likely
> > > the panel is not fully on until it receives the full frame to be
> > > displayed.
> >
> > According to the DSI spec a PPS update is allowed to happen every frame, and
> > (for cmdmode panels) will take effect after the next TE trigger. Unsure if a TE
> > event happens before the first frame, otherwise this may start taking effect
> > on the second frame onwards only.
> >
> > If there's no corruption on the first frame there might be a pre-programmed PPS
> > table in slot 2, supporting the theory above.
>
>
>
> --
> With best wishes
> Dmitry
^ permalink raw reply
* Re: [PATCH v9 05/10] ARM: dts: bcm2835-rpi: Move duplicate firmware-clocks to bcm2835-rpi.dtsi
From: Florian Fainelli @ 2024-04-02 20:53 UTC (permalink / raw)
To: Laurent Pinchart, linux-media
Cc: Dave Stevenson, David Plowman, Jean-Michel Hautbois, Hans Verkuil,
Naushir Patuck, Sakari Ailus, kernel-list, linux-rpi-kernel,
Ray Jui, Scott Branden, bcm-kernel-feedback-list, Conor Dooley,
Krzysztof Kozlowski, Rob Herring, devicetree
In-Reply-To: <20240402000424.4650-6-laurent.pinchart@ideasonboard.com>
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On 4/1/24 17:04, Laurent Pinchart wrote:
> The Raspberry Pi firmware handles clocks on all BCM2835-derived SoCs. It
> is currently defined identically in both bcm2711-rpi.dtsi and
> bcm2835-rpi-common.dtsi. Move the definitions to the common
> bcm2835-rpi.dtsi file.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next,
thanks!
--
Florian
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^ permalink raw reply
* Re: [PATCH v9 00/10] media: Add driver for the Raspberry Pi <5 CSI-2 receiver
From: Laurent Pinchart @ 2024-04-02 20:53 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux-media, Dave Stevenson, David Plowman, Jean-Michel Hautbois,
Hans Verkuil, Naushir Patuck, Sakari Ailus, kernel-list,
linux-rpi-kernel, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Conor Dooley, Krzysztof Kozlowski,
Rob Herring, devicetree
In-Reply-To: <0f5bc6e1-a8d8-4067-bd02-b3ec570f2936@broadcom.com>
On Tue, Apr 02, 2024 at 01:46:44PM -0700, Florian Fainelli wrote:
> Hello Laurent,
>
> On 4/1/24 17:11, Laurent Pinchart wrote:
> > Hi Florian,
> >
> > I think patches 05/10 ("ARM: dts: bcm2835-rpi: Move duplicate
> > firmware-clocks to bcm2835-rpi.dtsi"), 07/10 ("ARM: dts: bcm2711-rpi:
> > Add pinctrl-based multiplexing for I2C0"), 08/10 ("ARM: dts:
> > bcm2711-rpi-cm4-io: Add RTC on I2C0") and 09/10 ("ARM: dts:
> > bcm2711-rpi-4-b: Add CAM1 regulator") are ready for you to merge. This
> > would help reducing further iterations of this series.
>
> I could not locate the base commit this series was posted against
> (58abf3672a73558149fa567eafff8d5b1cc0446b), so patch 5 unfortunately did
> not apply cleanly due to v6.9-rc1 still having a "dma-ranges" property,
> fixed that up and the rest applied fine.
The base is in the rpi/v6.9/unicam/next branch of
https://git.kernel.org/pub/scm/linux/kernel/git/pinchartl/linux.git.
This series applies on top of the 3 DT drive-by fixes I've sent
separately.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH v2 0/3] dt-bindings: arm: bcm: raspberrypi,bcm2835-firmware: Drive-by fixes
From: Florian Fainelli @ 2024-04-02 20:52 UTC (permalink / raw)
To: Laurent Pinchart, Florian Fainelli
Cc: Stefan Wahren, Ivan T. Ivanov, Peter Robinson, Dave Stevenson,
Naushir Patuck, Bartosz Golaszewski,
Broadcom internal kernel review list, Conor Dooley,
Krzysztof Kozlowski, Linus Walleij, Nicolas Saenz Julienne,
Ray Jui, Rob Herring, Scott Branden, linux-arm-kernel, devicetree,
linux-rpi-kernel, u-boot
In-Reply-To: <20240402203255.GC32172@pendragon.ideasonboard.com>
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On 4/2/24 13:32, Laurent Pinchart wrote:
> Hi Florian,
>
> On Tue, Apr 02, 2024 at 01:18:35PM -0700, Florian Fainelli wrote:
>> On 4/2/24 13:08, Laurent Pinchart wrote:
>>> On Tue, Apr 02, 2024 at 09:52:06PM +0200, Stefan Wahren wrote:
>>>> Am 02.04.24 um 10:58 schrieb Ivan T. Ivanov:
>>>>> On 2024-03-28 01:37, Laurent Pinchart wrote:
>>>>>> On Wed, Mar 27, 2024 at 07:49:38AM +0100, Stefan Wahren wrote:
>>>>>>> Hi,
>>>>>>>
>>>>>>> [add Peter and Ivan]
>>>>>>>
>>>>>>> Am 26.03.24 um 20:58 schrieb Laurent Pinchart:
>>>>>>>> Hello,
>>>>>>>>
>>>>>>>> This small series includes a few drive-by fixes for DT validation
>>>>>>>> errors.
>>>>>>>>
>>>>>>>> The first patch has been posted previously in v1 ([1], and now addresses
>>>>>>>> a small review comment. I think it's good to go.
>>>>>>>>
>>>>>>>> The next two patches address the same issue as "[PATCH 1/2] dt-bindings:
>>>>>>>> arm: bcm: raspberrypi,bcm2835-firmware: Add missing properties" ([2]),
>>>>>>>> but this time with a (hopefully) correct approach. Patch 2/3 starts by
>>>>>>>> fixing the raspberrypi-bcm2835-firmware driver, removing the need for DT
>>>>>>>> properties that are specified in bcm2835-rpi.dtsi but not documented in
>>>>>>>> the corresponding bindings. Patch 3/3 can then drop those properties,
>>>>>>>> getting rid of the warnings.
>>>>>>>
>>>>>>> since this series drops properties from the device tree, does anyone
>>>>>>> have the chance to test it with a recent U-Boot?
>>>>>>
>>>>>> I don't have U-Boot running with my RPi, so I would appreciate if
>>>>>> someone could help :-)
>>>>>
>>>>> Sorry for taking me so long to verify this.
>>>>>
>>>>> I think on RPi U-Boot side we are fine. API used when accessing Mbox
>>>>> device do not follow DM model and do not use DMA, but just access
>>>>> device directly using this nice macros phys_to_bus/bus_to_phys.
>>>>>
>>>>> I build new DTB files with this patch included and U-Boot build
>>>>> from the latest sources. No obvious issues on RPi3 and RPi4.
>>>>> Devices boot fine.
>>>
>>> Thank you for testing Ivan.
>>>
>>>> Thanks you, Laurent and Ivan
>>>>
>>>> Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
>>>
>>> Stefan, I'm quite unfamiliar with the Raspberry Pi upstreaming process
>>> (despite having sent patches for ages :-)), do I understand correctly
>>> that this patch will go through your tree, or do I need to work with
>>> someone else to get it merged upstream ?
>>
>> I will be taking those via the Broadcom SoC tree.
>
> Thank you.
>
> If there's a chance to include patches 05/10, 07/10, 08/10 and 09/10
> from [1] at the same time, that would be great :-)
>
> [1] https://lore.kernel.org/linux-media/20240402000424.4650-1-laurent.pinchart@ideasonboard.com
>
Yes, now done, thanks!
--
Florian
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* Re: [PATCH v9 07/10] ARM: dts: bcm2711-rpi: Add pinctrl-based multiplexing for I2C0
From: Florian Fainelli @ 2024-04-02 20:45 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Laurent Pinchart, linux-media
Cc: Florian Fainelli, Uwe Kleine-König, Dave Stevenson,
David Plowman, Jean-Michel Hautbois, Hans Verkuil, Naushir Patuck,
Sakari Ailus, kernel-list, linux-rpi-kernel, Ray Jui,
Scott Branden, Conor Dooley, Krzysztof Kozlowski, Rob Herring,
devicetree
In-Reply-To: <20240402000424.4650-8-laurent.pinchart@ideasonboard.com>
From: Florian Fainelli <f.fainelli@gmail.com>
On Tue, 2 Apr 2024 03:04:14 +0300, Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote:
> From: Uwe Kleine-König <uwe@kleine-koenig.org>
>
> BCM2711-based Raspberry Pi boards (4B, CM4 and 400) multiplex the I2C0
> controller over two sets of pins, GPIO0+1 and GPIO44+45. The former is
> exposed on the 40-pin header, while the latter is used for the CSI and
> DSI connectors.
>
> Add a pinctrl-based I2C bus multiplexer to bcm2711-rpi.dtsi to model
> this multiplexing. The two child buses are named i2c0_0 and i2c0_1.
>
> Note that if you modified the dts before to add devices to the i2c bus
> appearing on pins gpio0 + gpio1 (either directly in the dts or using an
> overlay), you have to put these into the i2c0_0 node introduced here
> now.
>
> Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply
* Re: [PATCH v9 08/10] ARM: dts: bcm2711-rpi-cm4-io: Add RTC on I2C0
From: Florian Fainelli @ 2024-04-02 20:46 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Laurent Pinchart, linux-media
Cc: Florian Fainelli, Uwe Kleine-König, Dave Stevenson,
David Plowman, Jean-Michel Hautbois, Hans Verkuil, Naushir Patuck,
Sakari Ailus, kernel-list, linux-rpi-kernel, Ray Jui,
Scott Branden, Conor Dooley, Krzysztof Kozlowski, Rob Herring,
devicetree
In-Reply-To: <20240402000424.4650-9-laurent.pinchart@ideasonboard.com>
From: Florian Fainelli <f.fainelli@gmail.com>
On Tue, 2 Apr 2024 03:04:15 +0300, Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote:
> From: Uwe Kleine-König <uwe@kleine-koenig.org>
>
> The cm4-io board comes with a PCF85063 on I2C0, connected to the GPIO44
> and GPIO45 pins. Add it to the device tree.
>
> Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply
* Re: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: set brcm,wp-not-connected
From: Florian Fainelli @ 2024-04-02 20:41 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Rafał Miłecki,
Florian Fainelli
Cc: Florian Fainelli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
William Zhang, Anand Gore, Kursad Oney, devicetree,
linux-arm-kernel, Rafał Miłecki
In-Reply-To: <20240328093710.28206-1-zajec5@gmail.com>
From: Florian Fainelli <f.fainelli@gmail.com>
On Thu, 28 Mar 2024 10:37:10 +0100, Rafał Miłecki <zajec5@gmail.com> wrote:
> From: Rafał Miłecki <rafal@milecki.pl>
>
> Every described BCM4908 board has WP pin not connected. This caused
> problems for drivers since day 0 but there was no property to describe
> that properly. Projects like OpenWrt were modifying Linux driver to deal
> with it.
>
> It's not clear if that is hardware limitation or just reference design
> being copied over and over but this applies to all known / supported
> BCM4908 boards. Handle it by marking WP as not connected by default.
>
> Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files")
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian
^ permalink raw reply
* Re: [PATCH v9 00/10] media: Add driver for the Raspberry Pi <5 CSI-2 receiver
From: Florian Fainelli @ 2024-04-02 20:46 UTC (permalink / raw)
To: Laurent Pinchart
Cc: linux-media, Dave Stevenson, David Plowman, Jean-Michel Hautbois,
Hans Verkuil, Naushir Patuck, Sakari Ailus, kernel-list,
linux-rpi-kernel, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Conor Dooley, Krzysztof Kozlowski,
Rob Herring, devicetree
In-Reply-To: <20240402001111.GA4761@pendragon.ideasonboard.com>
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Hello Laurent,
On 4/1/24 17:11, Laurent Pinchart wrote:
> Hi Florian,
>
> I think patches 05/10 ("ARM: dts: bcm2835-rpi: Move duplicate
> firmware-clocks to bcm2835-rpi.dtsi"), 07/10 ("ARM: dts: bcm2711-rpi:
> Add pinctrl-based multiplexing for I2C0"), 08/10 ("ARM: dts:
> bcm2711-rpi-cm4-io: Add RTC on I2C0") and 09/10 ("ARM: dts:
> bcm2711-rpi-4-b: Add CAM1 regulator") are ready for you to merge. This
> would help reducing further iterations of this series.
I could not locate the base commit this series was posted against
(58abf3672a73558149fa567eafff8d5b1cc0446b), so patch 5 unfortunately did
not apply cleanly due to v6.9-rc1 still having a "dma-ranges" property,
fixed that up and the rest applied fine.
Thanks!
--
Florian
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^ permalink raw reply
* Re: [PATCH v9 09/10] ARM: dts: bcm2711-rpi-4-b: Add CAM1 regulator
From: Florian Fainelli @ 2024-04-02 20:46 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Laurent Pinchart, linux-media
Cc: Florian Fainelli, Dave Stevenson, David Plowman,
Jean-Michel Hautbois, Hans Verkuil, Naushir Patuck, Sakari Ailus,
kernel-list, linux-rpi-kernel, Ray Jui, Scott Branden,
Conor Dooley, Krzysztof Kozlowski, Rob Herring, devicetree
In-Reply-To: <20240402000424.4650-10-laurent.pinchart@ideasonboard.com>
From: Florian Fainelli <f.fainelli@gmail.com>
On Tue, 2 Apr 2024 03:04:16 +0300, Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote:
> Add a fixed regulator to model the power supply to the camera connector.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply
* [PATCH v1 1/2] dt-bindings: mtd: amlogic,meson-nand: support fields for boot ROM code
From: Arseniy Krasnov @ 2024-04-02 20:27 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: linux-mtd, devicetree, linux-arm-kernel, linux-amlogic,
linux-kernel, oxffffaa, kernel, Arseniy Krasnov
In-Reply-To: <20240402202705.2355326-1-avkrasnov@salutedevices.com>
Boot ROM code on Meson requires that some pages on NAND must be written
in special mode: "short" ECC mode where each block is 384 bytes and
scrambling mode is on. Such pages located with the specified interval
within specified offset. Both interval and offset are located in the
device tree and used by driver if 'nand-is-boot-medium' is set for
NAND chip.
Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
---
.../bindings/mtd/amlogic,meson-nand.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml
index 57b6957c8415..f49819ee76b8 100644
--- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml
+++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml
@@ -64,11 +64,27 @@ patternProperties:
items:
maximum: 0
+ meson,boot-page-last:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The NFC driver needs this information to select ECC
+ algorithms supported by the boot ROM.
+ Only used in combination with 'nand-is-boot-medium'.
+
+ meson,boot-page-step:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The NFC driver needs this information to select ECC
+ algorithms supported by the boot ROM.
+ Only used in combination with 'nand-is-boot-medium'.
+
unevaluatedProperties: false
dependencies:
nand-ecc-strength: [nand-ecc-step-size]
nand-ecc-step-size: [nand-ecc-strength]
+ meson,boot-page-last: [nand-is-boot-medium]
+ meson,boot-page-step: [nand-is-boot-medium]
required:
--
2.35.0
^ permalink raw reply related
* [PATCH v1 2/2] mtd: rawnand: meson: support R/W mode for boot ROM
From: Arseniy Krasnov @ 2024-04-02 20:27 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: linux-mtd, devicetree, linux-arm-kernel, linux-amlogic,
linux-kernel, oxffffaa, kernel, Arseniy Krasnov
In-Reply-To: <20240402202705.2355326-1-avkrasnov@salutedevices.com>
Boot ROM code on Meson requires that some pages on NAND must be written
in special mode: "short" ECC mode where each block is 384 bytes and
scrambling mode is on. Such pages located with the specified interval
within specified offset. Both interval and offset are located in the
device tree and used by driver if 'nand-is-boot-medium' is set for
NAND chip.
Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
---
drivers/mtd/nand/raw/meson_nand.c | 88 +++++++++++++++++++++----------
1 file changed, 59 insertions(+), 29 deletions(-)
diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c
index 00ce0e5bb970..3f29dd28bd43 100644
--- a/drivers/mtd/nand/raw/meson_nand.c
+++ b/drivers/mtd/nand/raw/meson_nand.c
@@ -35,6 +35,7 @@
#define NFC_CMD_RB BIT(20)
#define NFC_CMD_SCRAMBLER_ENABLE BIT(19)
#define NFC_CMD_SCRAMBLER_DISABLE 0
+#define NFC_CMD_SHORTMODE_ENABLE 1
#define NFC_CMD_SHORTMODE_DISABLE 0
#define NFC_CMD_RB_INT BIT(14)
#define NFC_CMD_RB_INT_NO_PIN ((0xb << 10) | BIT(18) | BIT(16))
@@ -78,6 +79,8 @@
#define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N)
#define DMA_ADDR_ALIGN 8
+#define NFC_SHORT_MODE_ECC_SZ 384
+
#define ECC_CHECK_RETURN_FF (-1)
#define NAND_CE0 (0xe << 10)
@@ -125,6 +128,8 @@ struct meson_nfc_nand_chip {
u32 twb;
u32 tadl;
u32 tbers_max;
+ u32 boot_page_last;
+ u32 boot_page_step;
u32 bch_mode;
u8 *data_buf;
@@ -298,28 +303,49 @@ static void meson_nfc_cmd_seed(struct meson_nfc *nfc, u32 seed)
nfc->reg_base + NFC_REG_CMD);
}
-static void meson_nfc_cmd_access(struct nand_chip *nand, int raw, bool dir,
- int scrambler)
+static int meson_nfc_page_is_boot(struct nand_chip *nand, int page)
+{
+ const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+
+ return (nand->options & NAND_IS_BOOT_MEDIUM) &&
+ !(page % meson_chip->boot_page_step) &&
+ (page < meson_chip->boot_page_last);
+}
+
+static void meson_nfc_cmd_access(struct nand_chip *nand, bool raw, bool dir, int page)
{
+ const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
struct mtd_info *mtd = nand_to_mtd(nand);
struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
- struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
- u32 bch = meson_chip->bch_mode, cmd;
int len = mtd->writesize, pagesize, pages;
+ int scrambler;
+ u32 cmd;
- pagesize = nand->ecc.size;
+ if (nand->options & NAND_NEED_SCRAMBLING)
+ scrambler = NFC_CMD_SCRAMBLER_ENABLE;
+ else
+ scrambler = NFC_CMD_SCRAMBLER_DISABLE;
if (raw) {
len = mtd->writesize + mtd->oobsize;
cmd = len | scrambler | DMA_DIR(dir);
- writel(cmd, nfc->reg_base + NFC_REG_CMD);
- return;
- }
+ } else if (meson_nfc_page_is_boot(nand, page)) {
+ pagesize = NFC_SHORT_MODE_ECC_SZ >> 3;
+ pages = mtd->writesize / 512;
+
+ scrambler = NFC_CMD_SCRAMBLER_ENABLE;
+ cmd = CMDRWGEN(DMA_DIR(dir), scrambler, NFC_ECC_BCH8_1K,
+ NFC_CMD_SHORTMODE_ENABLE, pagesize, pages);
+ } else {
+ pagesize = nand->ecc.size >> 3;
+ pages = len / nand->ecc.size;
- pages = len / nand->ecc.size;
+ cmd = CMDRWGEN(DMA_DIR(dir), scrambler, meson_chip->bch_mode,
+ NFC_CMD_SHORTMODE_DISABLE, pagesize, pages);
+ }
- cmd = CMDRWGEN(DMA_DIR(dir), scrambler, bch,
- NFC_CMD_SHORTMODE_DISABLE, pagesize, pages);
+ if (scrambler == NFC_CMD_SCRAMBLER_ENABLE)
+ meson_nfc_cmd_seed(nfc, page);
writel(cmd, nfc->reg_base + NFC_REG_CMD);
}
@@ -743,15 +769,7 @@ static int meson_nfc_write_page_sub(struct nand_chip *nand,
if (ret)
return ret;
- if (nand->options & NAND_NEED_SCRAMBLING) {
- meson_nfc_cmd_seed(nfc, page);
- meson_nfc_cmd_access(nand, raw, DIRWRITE,
- NFC_CMD_SCRAMBLER_ENABLE);
- } else {
- meson_nfc_cmd_access(nand, raw, DIRWRITE,
- NFC_CMD_SCRAMBLER_DISABLE);
- }
-
+ meson_nfc_cmd_access(nand, raw, DIRWRITE, page);
cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG;
writel(cmd, nfc->reg_base + NFC_REG_CMD);
meson_nfc_queue_rb(nand, PSEC_TO_MSEC(sdr->tPROG_max), false);
@@ -829,15 +847,7 @@ static int meson_nfc_read_page_sub(struct nand_chip *nand,
if (ret)
return ret;
- if (nand->options & NAND_NEED_SCRAMBLING) {
- meson_nfc_cmd_seed(nfc, page);
- meson_nfc_cmd_access(nand, raw, DIRREAD,
- NFC_CMD_SCRAMBLER_ENABLE);
- } else {
- meson_nfc_cmd_access(nand, raw, DIRREAD,
- NFC_CMD_SCRAMBLER_DISABLE);
- }
-
+ meson_nfc_cmd_access(nand, raw, DIRREAD, page);
ret = meson_nfc_wait_dma_finish(nfc);
meson_nfc_check_ecc_pages_valid(nfc, nand, raw);
@@ -1436,6 +1446,26 @@ meson_nfc_nand_chip_init(struct device *dev,
if (ret)
return ret;
+ if (nand->options & NAND_IS_BOOT_MEDIUM) {
+ ret = of_property_read_u32(np, "meson,boot-page-last",
+ &meson_chip->boot_page_last);
+ if (ret) {
+ dev_err(dev, "could not retrieve 'meson,boot-page-last' property: %d",
+ ret);
+ nand_cleanup(nand);
+ return ret;
+ }
+
+ ret = of_property_read_u32(np, "meson,boot-page-step",
+ &meson_chip->boot_page_step);
+ if (ret) {
+ dev_err(dev, "could not retrieve 'meson,boot-page-step' property: %d",
+ ret);
+ nand_cleanup(nand);
+ return ret;
+ }
+ }
+
ret = mtd_device_register(mtd, NULL, 0);
if (ret) {
dev_err(dev, "failed to register MTD device: %d\n", ret);
--
2.35.0
^ permalink raw reply related
* [PATCH v1 0/2] Meson: R/W support for pages used by boot ROM
From: Arseniy Krasnov @ 2024-04-02 20:27 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: linux-mtd, devicetree, linux-arm-kernel, linux-amlogic,
linux-kernel, oxffffaa, kernel, Arseniy Krasnov
Amlogic's boot ROM code needs that some pages on NAND must be written
in special "short" ECC mode with scrambling enabled. Such pages:
1) Contain some metadata about hardware.
2) Located with some interval starting from 0 offset, until some
specified offset. Interval and second offset are set in the
device tree.
This patchset adds R/W support for such pages. To enable it we can setup
it in dts:
nand-is-boot-medium;
meson,boot-page-last = <1024>;
meson,boot-page-step = <128>;
It means that each 128th page in range 0 to 1024 pages will be accessed
in special mode ("short" ECC + scrambling). In practice this feature is
needed when we want to update first block of NAND - driver will enable
required mode by itself using value from device tree.
Arseniy Krasnov (2):
dt-bindings: mtd: amlogic,meson-nand: support fields for boot ROM code
mtd: rawnand: meson: support R/W mode for boot ROM
.../bindings/mtd/amlogic,meson-nand.yaml | 16 ++++
drivers/mtd/nand/raw/meson_nand.c | 88 +++++++++++++------
2 files changed, 75 insertions(+), 29 deletions(-)
--
2.35.0
^ permalink raw reply
* Re: [PATCH v2 0/3] dt-bindings: arm: bcm: raspberrypi,bcm2835-firmware: Drive-by fixes
From: Laurent Pinchart @ 2024-04-02 20:32 UTC (permalink / raw)
To: Florian Fainelli
Cc: Stefan Wahren, Ivan T. Ivanov, Peter Robinson, Dave Stevenson,
Naushir Patuck, Bartosz Golaszewski,
Broadcom internal kernel review list, Conor Dooley,
Florian Fainelli, Krzysztof Kozlowski, Linus Walleij,
Nicolas Saenz Julienne, Ray Jui, Rob Herring, Scott Branden,
linux-arm-kernel, devicetree, linux-rpi-kernel, u-boot
In-Reply-To: <8a64376d-f624-44c8-91bb-f6a95dc1c945@gmail.com>
Hi Florian,
On Tue, Apr 02, 2024 at 01:18:35PM -0700, Florian Fainelli wrote:
> On 4/2/24 13:08, Laurent Pinchart wrote:
> > On Tue, Apr 02, 2024 at 09:52:06PM +0200, Stefan Wahren wrote:
> >> Am 02.04.24 um 10:58 schrieb Ivan T. Ivanov:
> >>> On 2024-03-28 01:37, Laurent Pinchart wrote:
> >>>> On Wed, Mar 27, 2024 at 07:49:38AM +0100, Stefan Wahren wrote:
> >>>>> Hi,
> >>>>>
> >>>>> [add Peter and Ivan]
> >>>>>
> >>>>> Am 26.03.24 um 20:58 schrieb Laurent Pinchart:
> >>>>>> Hello,
> >>>>>>
> >>>>>> This small series includes a few drive-by fixes for DT validation
> >>>>>> errors.
> >>>>>>
> >>>>>> The first patch has been posted previously in v1 ([1], and now addresses
> >>>>>> a small review comment. I think it's good to go.
> >>>>>>
> >>>>>> The next two patches address the same issue as "[PATCH 1/2] dt-bindings:
> >>>>>> arm: bcm: raspberrypi,bcm2835-firmware: Add missing properties" ([2]),
> >>>>>> but this time with a (hopefully) correct approach. Patch 2/3 starts by
> >>>>>> fixing the raspberrypi-bcm2835-firmware driver, removing the need for DT
> >>>>>> properties that are specified in bcm2835-rpi.dtsi but not documented in
> >>>>>> the corresponding bindings. Patch 3/3 can then drop those properties,
> >>>>>> getting rid of the warnings.
> >>>>>
> >>>>> since this series drops properties from the device tree, does anyone
> >>>>> have the chance to test it with a recent U-Boot?
> >>>>
> >>>> I don't have U-Boot running with my RPi, so I would appreciate if
> >>>> someone could help :-)
> >>>
> >>> Sorry for taking me so long to verify this.
> >>>
> >>> I think on RPi U-Boot side we are fine. API used when accessing Mbox
> >>> device do not follow DM model and do not use DMA, but just access
> >>> device directly using this nice macros phys_to_bus/bus_to_phys.
> >>>
> >>> I build new DTB files with this patch included and U-Boot build
> >>> from the latest sources. No obvious issues on RPi3 and RPi4.
> >>> Devices boot fine.
> >
> > Thank you for testing Ivan.
> >
> >> Thanks you, Laurent and Ivan
> >>
> >> Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
> >
> > Stefan, I'm quite unfamiliar with the Raspberry Pi upstreaming process
> > (despite having sent patches for ages :-)), do I understand correctly
> > that this patch will go through your tree, or do I need to work with
> > someone else to get it merged upstream ?
>
> I will be taking those via the Broadcom SoC tree.
Thank you.
If there's a chance to include patches 05/10, 07/10, 08/10 and 09/10
from [1] at the same time, that would be great :-)
[1] https://lore.kernel.org/linux-media/20240402000424.4650-1-laurent.pinchart@ideasonboard.com
--
Regards,
Laurent Pinchart
^ permalink raw reply
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