* [PATCH v3 23/25] drivers: media: i2c: imx258: Add support for powerdown gpio
From: git @ 2024-04-03 15:03 UTC (permalink / raw)
To: linux-media
Cc: dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel, Luis Garcia, Ondrej Jirman
In-Reply-To: <20240403150355.189229-1-git@luigi311.com>
From: Luis Garcia <git@luigi311.com>
On some boards powerdown signal needs to be deasserted for this
sensor to be enabled.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Signed-off-by: Luis Garcia <git@luigi311.com>
---
drivers/media/i2c/imx258.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
index 30352c33f63c..163f04f6f954 100644
--- a/drivers/media/i2c/imx258.c
+++ b/drivers/media/i2c/imx258.c
@@ -679,6 +679,8 @@ struct imx258 {
unsigned int lane_mode_idx;
unsigned int csi2_flags;
+ struct gpio_desc *powerdown_gpio;
+
/*
* Mutex for serialized access:
* Protect sensor module set pad format and start/stop streaming safely.
@@ -1213,6 +1215,8 @@ static int imx258_power_on(struct device *dev)
struct imx258 *imx258 = to_imx258(sd);
int ret;
+ gpiod_set_value_cansleep(imx258->powerdown_gpio, 0);
+
ret = regulator_bulk_enable(IMX258_NUM_SUPPLIES,
imx258->supplies);
if (ret) {
@@ -1224,6 +1228,7 @@ static int imx258_power_on(struct device *dev)
ret = clk_prepare_enable(imx258->clk);
if (ret) {
dev_err(dev, "failed to enable clock\n");
+ gpiod_set_value_cansleep(imx258->powerdown_gpio, 1);
regulator_bulk_disable(IMX258_NUM_SUPPLIES, imx258->supplies);
}
@@ -1238,6 +1243,8 @@ static int imx258_power_off(struct device *dev)
clk_disable_unprepare(imx258->clk);
regulator_bulk_disable(IMX258_NUM_SUPPLIES, imx258->supplies);
+ gpiod_set_value_cansleep(imx258->powerdown_gpio, 1);
+
return 0;
}
@@ -1541,6 +1548,12 @@ static int imx258_probe(struct i2c_client *client)
if (!imx258->variant_cfg)
imx258->variant_cfg = &imx258_cfg;
+ /* request optional power down pin */
+ imx258->powerdown_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(imx258->powerdown_gpio))
+ return PTR_ERR(imx258->powerdown_gpio);
+
/* Initialize subdev */
v4l2_i2c_subdev_init(&imx258->sd, client, &imx258_subdev_ops);
--
2.42.0
^ permalink raw reply related
* [PATCH v3 21/25] drivers: media: i2c: imx258: Use macros
From: git @ 2024-04-03 15:03 UTC (permalink / raw)
To: linux-media
Cc: dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel, Luis Garcia, Ondrej Jirman
In-Reply-To: <20240403150355.189229-1-git@luigi311.com>
From: Luis Garcia <git@luigi311.com>
Use understandable macros instead of raw values.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Signed-off-by: Luis Garcia <git@luigi311.com>
---
drivers/media/i2c/imx258.c | 434 ++++++++++++++++++-------------------
1 file changed, 207 insertions(+), 227 deletions(-)
diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
index e2ecf6109516..30352c33f63c 100644
--- a/drivers/media/i2c/imx258.c
+++ b/drivers/media/i2c/imx258.c
@@ -33,8 +33,6 @@
#define IMX258_VTS_30FPS_VGA 0x034c
#define IMX258_VTS_MAX 65525
-#define IMX258_REG_VTS 0x0340
-
/* HBLANK control - read only */
#define IMX258_PPL_DEFAULT 5352
@@ -90,6 +88,53 @@
#define IMX258_PIXEL_ARRAY_WIDTH 4208U
#define IMX258_PIXEL_ARRAY_HEIGHT 3120U
+/* regs */
+#define IMX258_REG_PLL_MULT_DRIV 0x0310
+#define IMX258_REG_IVTPXCK_DIV 0x0301
+#define IMX258_REG_IVTSYCK_DIV 0x0303
+#define IMX258_REG_PREPLLCK_VT_DIV 0x0305
+#define IMX258_REG_IOPPXCK_DIV 0x0309
+#define IMX258_REG_IOPSYCK_DIV 0x030b
+#define IMX258_REG_PREPLLCK_OP_DIV 0x030d
+#define IMX258_REG_PHASE_PIX_OUTEN 0x3030
+#define IMX258_REG_PDPIX_DATA_RATE 0x3032
+#define IMX258_REG_SCALE_MODE 0x0401
+#define IMX258_REG_SCALE_MODE_EXT 0x3038
+#define IMX258_REG_AF_WINDOW_MODE 0x7bcd
+#define IMX258_REG_FRM_LENGTH_CTL 0x0350
+#define IMX258_REG_CSI_LANE_MODE 0x0114
+#define IMX258_REG_X_EVN_INC 0x0381
+#define IMX258_REG_X_ODD_INC 0x0383
+#define IMX258_REG_Y_EVN_INC 0x0385
+#define IMX258_REG_Y_ODD_INC 0x0387
+#define IMX258_REG_BINNING_MODE 0x0900
+#define IMX258_REG_BINNING_TYPE_V 0x0901
+#define IMX258_REG_FORCE_FD_SUM 0x300d
+#define IMX258_REG_DIG_CROP_X_OFFSET 0x0408
+#define IMX258_REG_DIG_CROP_Y_OFFSET 0x040a
+#define IMX258_REG_DIG_CROP_IMAGE_WIDTH 0x040c
+#define IMX258_REG_DIG_CROP_IMAGE_HEIGHT 0x040e
+#define IMX258_REG_SCALE_M 0x0404
+#define IMX258_REG_X_OUT_SIZE 0x034c
+#define IMX258_REG_Y_OUT_SIZE 0x034e
+#define IMX258_REG_X_ADD_STA 0x0344
+#define IMX258_REG_Y_ADD_STA 0x0346
+#define IMX258_REG_X_ADD_END 0x0348
+#define IMX258_REG_Y_ADD_END 0x034a
+#define IMX258_REG_EXCK_FREQ 0x0136
+#define IMX258_REG_CSI_DT_FMT 0x0112
+#define IMX258_REG_LINE_LENGTH_PCK 0x0342
+#define IMX258_REG_SCALE_M_EXT 0x303a
+#define IMX258_REG_FRM_LENGTH_LINES 0x0340
+#define IMX258_REG_FINE_INTEG_TIME 0x0200
+#define IMX258_REG_PLL_IVT_MPY 0x0306
+#define IMX258_REG_PLL_IOP_MPY 0x030e
+#define IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H 0x0820
+#define IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L 0x0822
+
+#define REG8(a, v) { a, v }
+#define REG16(a, v) { a, ((v) >> 8) & 0xff }, { (a) + 1, (v) & 0xff }
+
struct imx258_reg {
u16 address;
u8 val;
@@ -145,179 +190,139 @@ struct imx258_mode {
* lane data rate when using 2 lanes, thus allowing a maximum of 15fps.
*/
static const struct imx258_reg mipi_1267mbps_19_2mhz_2l[] = {
- { 0x0136, 0x13 },
- { 0x0137, 0x33 },
- { 0x0301, 0x0A },
- { 0x0303, 0x02 },
- { 0x0305, 0x03 },
- { 0x0306, 0x00 },
- { 0x0307, 0xC6 },
- { 0x0309, 0x0A },
- { 0x030B, 0x01 },
- { 0x030D, 0x02 },
- { 0x030E, 0x00 },
- { 0x030F, 0xD8 },
- { 0x0310, 0x00 },
-
- { 0x0114, 0x01 },
- { 0x0820, 0x09 },
- { 0x0821, 0xa6 },
- { 0x0822, 0x66 },
- { 0x0823, 0x66 },
+ REG16(IMX258_REG_EXCK_FREQ, 0x1333),
+ REG8(IMX258_REG_IVTPXCK_DIV, 10),
+ REG8(IMX258_REG_IVTSYCK_DIV, 2),
+ REG8(IMX258_REG_PREPLLCK_VT_DIV, 3),
+ REG16(IMX258_REG_PLL_IVT_MPY, 0x00C6),
+ REG8(IMX258_REG_IOPPXCK_DIV, 10),
+ REG8(IMX258_REG_IOPSYCK_DIV, 1),
+ REG8(IMX258_REG_PREPLLCK_OP_DIV, 2),
+ REG16(IMX258_REG_PLL_IOP_MPY, 0x00D8),
+ REG8(IMX258_REG_PLL_MULT_DRIV, 0),
+
+ REG8(IMX258_REG_CSI_LANE_MODE, 1),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 0x09A6),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0x6666),
};
static const struct imx258_reg mipi_1267mbps_19_2mhz_4l[] = {
- { 0x0136, 0x13 },
- { 0x0137, 0x33 },
- { 0x0301, 0x05 },
- { 0x0303, 0x02 },
- { 0x0305, 0x03 },
- { 0x0306, 0x00 },
- { 0x0307, 0xC6 },
- { 0x0309, 0x0A },
- { 0x030B, 0x01 },
- { 0x030D, 0x02 },
- { 0x030E, 0x00 },
- { 0x030F, 0xD8 },
- { 0x0310, 0x00 },
-
- { 0x0114, 0x03 },
- { 0x0820, 0x13 },
- { 0x0821, 0x4C },
- { 0x0822, 0xCC },
- { 0x0823, 0xCC },
+ REG16(IMX258_REG_EXCK_FREQ, 0x1333),
+ REG8(IMX258_REG_IVTPXCK_DIV, 5),
+ REG8(IMX258_REG_IVTSYCK_DIV, 2),
+ REG8(IMX258_REG_PREPLLCK_VT_DIV, 3),
+ REG16(IMX258_REG_PLL_IVT_MPY, 0x00C6),
+ REG8(IMX258_REG_IOPPXCK_DIV, 10),
+ REG8(IMX258_REG_IOPSYCK_DIV, 1),
+ REG8(IMX258_REG_PREPLLCK_OP_DIV, 2),
+ REG16(IMX258_REG_PLL_IOP_MPY, 0x00D8),
+ REG8(IMX258_REG_PLL_MULT_DRIV, 0),
+
+ REG8(IMX258_REG_CSI_LANE_MODE, 3),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 0x134C),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0xCCCC),
};
static const struct imx258_reg mipi_1272mbps_24mhz_2l[] = {
- { 0x0136, 0x18 },
- { 0x0137, 0x00 },
- { 0x0301, 0x0a },
- { 0x0303, 0x02 },
- { 0x0305, 0x04 },
- { 0x0306, 0x00 },
- { 0x0307, 0xD4 },
- { 0x0309, 0x0A },
- { 0x030B, 0x01 },
- { 0x030D, 0x02 },
- { 0x030E, 0x00 },
- { 0x030F, 0xD8 },
- { 0x0310, 0x00 },
-
- { 0x0114, 0x01 },
- { 0x0820, 0x13 },
- { 0x0821, 0x4C },
- { 0x0822, 0xCC },
- { 0x0823, 0xCC },
+ REG16(IMX258_REG_EXCK_FREQ, 0x1800),
+ REG8(IMX258_REG_IVTPXCK_DIV, 10),
+ REG8(IMX258_REG_IVTSYCK_DIV, 2),
+ REG8(IMX258_REG_PREPLLCK_VT_DIV, 4),
+ REG16(IMX258_REG_PLL_IVT_MPY, 0x00D4),
+ REG8(IMX258_REG_IOPPXCK_DIV, 10),
+ REG8(IMX258_REG_IOPSYCK_DIV, 1),
+ REG8(IMX258_REG_PREPLLCK_OP_DIV, 2),
+ REG16(IMX258_REG_PLL_IOP_MPY, 0x00D8),
+ REG8(IMX258_REG_PLL_MULT_DRIV, 0),
+
+ REG8(IMX258_REG_CSI_LANE_MODE, 1),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 0x134C),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0xCCCC),
};
static const struct imx258_reg mipi_1272mbps_24mhz_4l[] = {
- { 0x0136, 0x18 },
- { 0x0137, 0x00 },
- { 0x0301, 0x05 },
- { 0x0303, 0x02 },
- { 0x0305, 0x04 },
- { 0x0306, 0x00 },
- { 0x0307, 0xD4 },
- { 0x0309, 0x0A },
- { 0x030B, 0x01 },
- { 0x030D, 0x02 },
- { 0x030E, 0x00 },
- { 0x030F, 0xD8 },
- { 0x0310, 0x00 },
-
- { 0x0114, 0x03 },
- { 0x0820, 0x13 },
- { 0x0821, 0xE0 },
- { 0x0822, 0x00 },
- { 0x0823, 0x00 },
+ REG16(IMX258_REG_EXCK_FREQ, 0x1800),
+ REG8(IMX258_REG_IVTPXCK_DIV, 5),
+ REG8(IMX258_REG_IVTSYCK_DIV, 2),
+ REG8(IMX258_REG_PREPLLCK_VT_DIV, 4),
+ REG16(IMX258_REG_PLL_IVT_MPY, 0x00D4),
+ REG8(IMX258_REG_IOPPXCK_DIV, 10),
+ REG8(IMX258_REG_IOPSYCK_DIV, 1),
+ REG8(IMX258_REG_PREPLLCK_OP_DIV, 2),
+ REG16(IMX258_REG_PLL_IOP_MPY, 0x00D8),
+ REG8(IMX258_REG_PLL_MULT_DRIV, 0),
+
+ REG8(IMX258_REG_CSI_LANE_MODE, 3),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 0x13E0),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0x0000),
};
static const struct imx258_reg mipi_640mbps_19_2mhz_2l[] = {
- { 0x0136, 0x13 },
- { 0x0137, 0x33 },
- { 0x0301, 0x05 },
- { 0x0303, 0x02 },
- { 0x0305, 0x03 },
- { 0x0306, 0x00 },
- { 0x0307, 0x64 },
- { 0x0309, 0x0A },
- { 0x030B, 0x01 },
- { 0x030D, 0x02 },
- { 0x030E, 0x00 },
- { 0x030F, 0xD8 },
- { 0x0310, 0x00 },
-
- { 0x0114, 0x01 },
- { 0x0820, 0x05 },
- { 0x0821, 0x00 },
- { 0x0822, 0x00 },
- { 0x0823, 0x00 },
+ REG16(IMX258_REG_EXCK_FREQ, 0x1333),
+ REG8(IMX258_REG_IVTPXCK_DIV, 5),
+ REG8(IMX258_REG_IVTSYCK_DIV, 2),
+ REG8(IMX258_REG_PREPLLCK_VT_DIV, 3),
+ REG16(IMX258_REG_PLL_IVT_MPY, 0x0064),
+ REG8(IMX258_REG_IOPPXCK_DIV, 10),
+ REG8(IMX258_REG_IOPSYCK_DIV, 1),
+ REG8(IMX258_REG_PREPLLCK_OP_DIV, 2),
+ REG16(IMX258_REG_PLL_IOP_MPY, 0x00D8),
+ REG8(IMX258_REG_PLL_MULT_DRIV, 0),
+
+ REG8(IMX258_REG_CSI_LANE_MODE, 1),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 0x0500),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0x0000),
};
static const struct imx258_reg mipi_640mbps_19_2mhz_4l[] = {
- { 0x0136, 0x13 },
- { 0x0137, 0x33 },
- { 0x0301, 0x05 },
- { 0x0303, 0x02 },
- { 0x0305, 0x03 },
- { 0x0306, 0x00 },
- { 0x0307, 0x64 },
- { 0x0309, 0x0A },
- { 0x030B, 0x01 },
- { 0x030D, 0x02 },
- { 0x030E, 0x00 },
- { 0x030F, 0xD8 },
- { 0x0310, 0x00 },
-
- { 0x0114, 0x03 },
- { 0x0820, 0x0A },
- { 0x0821, 0x00 },
- { 0x0822, 0x00 },
- { 0x0823, 0x00 },
+ REG16(IMX258_REG_EXCK_FREQ, 0x1333),
+ REG8(IMX258_REG_IVTPXCK_DIV, 5),
+ REG8(IMX258_REG_IVTSYCK_DIV, 2),
+ REG8(IMX258_REG_PREPLLCK_VT_DIV, 3),
+ REG16(IMX258_REG_PLL_IVT_MPY, 0x0064),
+ REG8(IMX258_REG_IOPPXCK_DIV, 10),
+ REG8(IMX258_REG_IOPSYCK_DIV, 1),
+ REG8(IMX258_REG_PREPLLCK_OP_DIV, 2),
+ REG16(IMX258_REG_PLL_IOP_MPY, 0x00D8),
+ REG8(IMX258_REG_PLL_MULT_DRIV, 0),
+
+ REG8(IMX258_REG_CSI_LANE_MODE, 3),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 0x0A00),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0x0000),
};
static const struct imx258_reg mipi_642mbps_24mhz_2l[] = {
- { 0x0136, 0x18 },
- { 0x0137, 0x00 },
- { 0x0301, 0x05 },
- { 0x0303, 0x02 },
- { 0x0305, 0x04 },
- { 0x0306, 0x00 },
- { 0x0307, 0x6B },
- { 0x0309, 0x0A },
- { 0x030B, 0x01 },
- { 0x030D, 0x02 },
- { 0x030E, 0x00 },
- { 0x030F, 0xD8 },
- { 0x0310, 0x00 },
-
- { 0x0114, 0x01 },
- { 0x0820, 0x0A },
- { 0x0821, 0x00 },
- { 0x0822, 0x00 },
- { 0x0823, 0x00 },
+ REG16(IMX258_REG_EXCK_FREQ, 0x1800),
+ REG8(IMX258_REG_IVTPXCK_DIV, 5),
+ REG8(IMX258_REG_IVTSYCK_DIV, 2),
+ REG8(IMX258_REG_PREPLLCK_VT_DIV, 4),
+ REG16(IMX258_REG_PLL_IVT_MPY, 0x006B),
+ REG8(IMX258_REG_IOPPXCK_DIV, 10),
+ REG8(IMX258_REG_IOPSYCK_DIV, 1),
+ REG8(IMX258_REG_PREPLLCK_OP_DIV, 2),
+ REG16(IMX258_REG_PLL_IOP_MPY, 0x00D8),
+ REG8(IMX258_REG_PLL_MULT_DRIV, 0),
+
+ REG8(IMX258_REG_CSI_LANE_MODE, 1),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 0x0A00),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0x0000),
};
static const struct imx258_reg mipi_642mbps_24mhz_4l[] = {
- { 0x0136, 0x18 },
- { 0x0137, 0x00 },
- { 0x0301, 0x05 },
- { 0x0303, 0x02 },
- { 0x0305, 0x04 },
- { 0x0306, 0x00 },
- { 0x0307, 0x6B },
- { 0x0309, 0x0A },
- { 0x030B, 0x01 },
- { 0x030D, 0x02 },
- { 0x030E, 0x00 },
- { 0x030F, 0xD8 },
- { 0x0310, 0x00 },
-
- { 0x0114, 0x03 },
- { 0x0820, 0x0A },
- { 0x0821, 0x00 },
- { 0x0822, 0x00 },
- { 0x0823, 0x00 },
+ REG16(IMX258_REG_EXCK_FREQ, 0x1800),
+ REG8(IMX258_REG_IVTPXCK_DIV, 5),
+ REG8(IMX258_REG_IVTSYCK_DIV, 2),
+ REG8(IMX258_REG_PREPLLCK_VT_DIV, 4),
+ REG16(IMX258_REG_PLL_IVT_MPY, 0x006B),
+ REG8(IMX258_REG_IOPPXCK_DIV, 10),
+ REG8(IMX258_REG_IOPSYCK_DIV, 1),
+ REG8(IMX258_REG_PREPLLCK_OP_DIV, 2),
+ REG16(IMX258_REG_PLL_IOP_MPY, 0x00D8),
+ REG8(IMX258_REG_PLL_MULT_DRIV, 0),
+
+ REG8(IMX258_REG_CSI_LANE_MODE, 3),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H, 0x0A00),
+ REG16(IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L, 0x0000),
};
static const struct imx258_reg mode_common_regs[] = {
@@ -363,45 +368,29 @@ static const struct imx258_reg mode_common_regs[] = {
{ 0x7423, 0xD7 },
{ 0x5F04, 0x00 },
{ 0x5F05, 0xED },
- { 0x0112, 0x0A },
- { 0x0113, 0x0A },
- { 0x0342, 0x14 },
- { 0x0343, 0xE8 },
- { 0x0344, 0x00 },
- { 0x0345, 0x00 },
- { 0x0346, 0x00 },
- { 0x0347, 0x00 },
- { 0x0348, 0x10 },
- { 0x0349, 0x6F },
- { 0x034A, 0x0C },
- { 0x034B, 0x2F },
- { 0x0381, 0x01 },
- { 0x0383, 0x01 },
- { 0x0385, 0x01 },
- { 0x0387, 0x01 },
- { 0x0404, 0x00 },
- { 0x0408, 0x00 },
- { 0x0409, 0x00 },
- { 0x040A, 0x00 },
- { 0x040B, 0x00 },
- { 0x040C, 0x10 },
- { 0x040D, 0x70 },
- { 0x3038, 0x00 },
- { 0x303A, 0x00 },
- { 0x303B, 0x10 },
- { 0x300D, 0x00 },
- { 0x0350, 0x00 },
- { 0x0204, 0x00 },
- { 0x0205, 0x00 },
- { 0x020E, 0x01 },
- { 0x020F, 0x00 },
- { 0x0210, 0x01 },
- { 0x0211, 0x00 },
- { 0x0212, 0x01 },
- { 0x0213, 0x00 },
- { 0x0214, 0x01 },
- { 0x0215, 0x00 },
- { 0x7BCD, 0x00 },
+ REG16(IMX258_REG_CSI_DT_FMT, 0x0a0a),
+ REG16(IMX258_REG_LINE_LENGTH_PCK, 5352),
+ REG16(IMX258_REG_X_ADD_STA, 0),
+ REG16(IMX258_REG_Y_ADD_STA, 0),
+ REG16(IMX258_REG_X_ADD_END, 4207),
+ REG16(IMX258_REG_Y_ADD_END, 3119),
+ REG8(IMX258_REG_X_EVN_INC, 1),
+ REG8(IMX258_REG_X_ODD_INC, 1),
+ REG8(IMX258_REG_Y_EVN_INC, 1),
+ REG8(IMX258_REG_Y_ODD_INC, 1),
+ REG16(IMX258_REG_DIG_CROP_X_OFFSET, 0),
+ REG16(IMX258_REG_DIG_CROP_Y_OFFSET, 0),
+ REG16(IMX258_REG_DIG_CROP_IMAGE_WIDTH, 4208),
+ REG8(IMX258_REG_SCALE_MODE_EXT, 0),
+ REG16(IMX258_REG_SCALE_M_EXT, 16),
+ REG8(IMX258_REG_FORCE_FD_SUM, 0),
+ REG8(IMX258_REG_FRM_LENGTH_CTL, 0),
+ REG16(IMX258_REG_ANALOG_GAIN, 0),
+ REG16(IMX258_REG_GR_DIGITAL_GAIN, 256),
+ REG16(IMX258_REG_R_DIGITAL_GAIN, 256),
+ REG16(IMX258_REG_B_DIGITAL_GAIN, 256),
+ REG16(IMX258_REG_GB_DIGITAL_GAIN, 256),
+ REG8(IMX258_REG_AF_WINDOW_MODE, 0),
{ 0x94DC, 0x20 },
{ 0x94DD, 0x20 },
{ 0x94DE, 0x20 },
@@ -414,48 +403,39 @@ static const struct imx258_reg mode_common_regs[] = {
{ 0x941B, 0x50 },
{ 0x9519, 0x50 },
{ 0x951B, 0x50 },
- { 0x3030, 0x00 },
- { 0x3032, 0x00 },
- { 0x0220, 0x00 },
+ REG8(IMX258_REG_PHASE_PIX_OUTEN, 0),
+ REG8(IMX258_REG_PDPIX_DATA_RATE, 0),
+ REG8(IMX258_REG_HDR, 0),
};
static const struct imx258_reg mode_4208x3120_regs[] = {
- { 0x0900, 0x00 },
- { 0x0901, 0x11 },
- { 0x0401, 0x00 },
- { 0x0405, 0x10 },
- { 0x040E, 0x0C },
- { 0x040F, 0x30 },
- { 0x034C, 0x10 },
- { 0x034D, 0x70 },
- { 0x034E, 0x0C },
- { 0x034F, 0x30 },
+ REG8(IMX258_REG_BINNING_MODE, 0),
+ REG8(IMX258_REG_BINNING_TYPE_V, 0x11),
+ REG8(IMX258_REG_SCALE_MODE, 0),
+ REG16(IMX258_REG_SCALE_M, 16),
+ REG16(IMX258_REG_DIG_CROP_IMAGE_HEIGHT, 3120),
+ REG16(IMX258_REG_X_OUT_SIZE, 4208),
+ REG16(IMX258_REG_Y_OUT_SIZE, 3120),
};
static const struct imx258_reg mode_2104_1560_regs[] = {
- { 0x0900, 0x01 },
- { 0x0901, 0x12 },
- { 0x0401, 0x01 },
- { 0x0405, 0x20 },
- { 0x040E, 0x06 },
- { 0x040F, 0x18 },
- { 0x034C, 0x08 },
- { 0x034D, 0x38 },
- { 0x034E, 0x06 },
- { 0x034F, 0x18 },
+ REG8(IMX258_REG_BINNING_MODE, 1),
+ REG8(IMX258_REG_BINNING_TYPE_V, 0x12),
+ REG8(IMX258_REG_SCALE_MODE, 1),
+ REG16(IMX258_REG_SCALE_M, 32),
+ REG16(IMX258_REG_DIG_CROP_IMAGE_HEIGHT, 1560),
+ REG16(IMX258_REG_X_OUT_SIZE, 2104),
+ REG16(IMX258_REG_Y_OUT_SIZE, 1560),
};
static const struct imx258_reg mode_1048_780_regs[] = {
- { 0x0900, 0x01 },
- { 0x0901, 0x14 },
- { 0x0401, 0x01 },
- { 0x0405, 0x40 },
- { 0x040E, 0x03 },
- { 0x040F, 0x0C },
- { 0x034C, 0x04 },
- { 0x034D, 0x18 },
- { 0x034E, 0x03 },
- { 0x034F, 0x0C },
+ REG8(IMX258_REG_BINNING_MODE, 1),
+ REG8(IMX258_REG_BINNING_TYPE_V, 0x14),
+ REG8(IMX258_REG_SCALE_MODE, 1),
+ REG16(IMX258_REG_SCALE_M, 64),
+ REG16(IMX258_REG_DIG_CROP_IMAGE_HEIGHT, 780),
+ REG16(IMX258_REG_X_OUT_SIZE, 1048),
+ REG16(IMX258_REG_Y_OUT_SIZE, 780),
};
struct imx258_variant_cfg {
@@ -923,7 +903,7 @@ static int imx258_set_ctrl(struct v4l2_ctrl *ctrl)
}
break;
case V4L2_CID_VBLANK:
- ret = imx258_write_reg(imx258, IMX258_REG_VTS,
+ ret = imx258_write_reg(imx258, IMX258_REG_FRM_LENGTH_LINES,
IMX258_REG_VALUE_16BIT,
imx258->cur_mode->height + ctrl->val);
break;
--
2.42.0
^ permalink raw reply related
* [PATCH v3 00/25] imx258 improvement series
From: git @ 2024-04-03 15:03 UTC (permalink / raw)
To: linux-media
Cc: dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel, Luis Garcia
From: Luis Garcia <git@luigi311.com>
v3 Luis Garcia
- Add Use v4l2_link_freq_to_bitmap helper patch per Sakari Ailus
- Separate dt-bindings for powerdown per Rob Herring
- Fix dt-bindings for imx258.yaml
- Fix sign offs per Dang Huynh
- Fix versioning per Conor Dooley and Kieran Bingham
- Use scripts to validate and fix patches
- Implemented feedback from Sakari Ailus
- media: i2c: imx258: Add support for 24MHz clock
- media: i2c: imx258: Add support for running on 2 CSI data lanes
- Implemented feedback from Rob Herring
- dt-bindings: media: imx258: Add alternate compatible strings
v2 Luis Garcia
- Add use macros patch
- Add support for powerdown gpio patch
- Add support for reset gpio patch
- Dropped Add support for long exposure modes patch
- Implemented feedback from Jacopo Mondi
- media: i2c: imx258: Add regulator control
- media: i2c: imx258: Add support for 24MHz clock
- media: i2c: imx258: Add support for running on 2 CSI data lanes
- media: i2c: imx258: Add get_selection for pixel array information
- media: i2c: imx258: Issue reset before starting streaming
- media: i2c: imx258: Set pixel_rate range to the same as the value
- dt-bindings: media: imx258: Add alternate compatible strings
- media: i2c: imx258: Change register settings for variants of the sensor
- media: i2c: imx258: Make HFLIP and VFLIP controls writable
This adds a few more patches and drops one. The long exposure mode patch
was dropped due to the bug that Jacopo found. The powerdown and reset gpio
patches were added as that fixes support for the Pinephone Pro, without
them the sensor doesn't initialize correctly.
Tested on a Pinephone Pro by forcing 24 mhz clock and was able to access
all 3 resolutions. The two lower resolutions had some artifacts but that
is expected as more changes are required to fix them for the
Pinephone Pro specifically, kept all registers the same as Dave's original
patch since that works on dedicated imx258 hardware and the artifacts are
PPP specific so it shouldn't be a regression.
v1 Dave Stevenson
This is a set of patches for imx258 that allow it to work with alternate
clock frequencies, over either 2 or 4 lanes, and generally adding
flexibility to the driver.
Tested with an IMX258 module from Soho Enterprises that has a 24MHz
oscillator. Both 2 and 4 lane configurations work with correct link
frequencies and pixel rates.
Jacopo has tested on a PinePhone Pro which has an ~19.2MHz clock fed from
the SoC, He confirms that the two lower resolution modes work, but not the
full res mode. Comparing to the BSP it looks like they have some weird
clock configuration in the 4208x3120 mode (nominally 1224Mb/s/lane instead
of 1267). As it has never previously worked directly with the mainline
driver this isn't a regression but may indicate that there is a need for
support of additional link frequencies in the future.
The last patch that makes HFLIP and VFLIP configurable may be contentious
as I've retained the default configuration of inverted from the original
driver. I know this was discussed recently, but I can't recall the final
outcome.
I am relying on someone from Intel testing this out, as correcting the
cropping and supporting flips has changed the Bayer order. Seeing as this
is all above board in V4L2 terms I really hope that the layers above it
behave themselves.
Cheers
Dave
Dave Stevenson (20):
media: i2c: imx258: Remove unused defines
media: i2c: imx258: Make image geometry meet sensor requirements
media: i2c: imx258: Disable digital cropping on binned modes
media: i2c: imx258: Remove redundant I2C writes.
media: i2c: imx258: Add regulator control
media: i2c: imx258: Make V4L2_CID_VBLANK configurable.
media: i2c: imx258: Split out common registers from the mode based
ones
media: i2c: imx258: Add support for 24MHz clock
media: i2c: imx258: Add support for running on 2 CSI data lanes
media: i2c: imx258: Follow normal V4L2 behaviours for clipping
exposure
media: i2c: imx258: Add get_selection for pixel array information
media: i2c: imx258: Allow configuration of clock lane behaviour
media: i2c: imx258: Correct max FRM_LENGTH_LINES value
media: i2c: imx258: Issue reset before starting streaming
media: i2c: imx258: Set pixel_rate range to the same as the value
media: i2c: imx258: Support faster pixel rate on binned modes
dt-bindings: media: imx258: Rename to include vendor prefix
dt-bindings: media: imx258: Add alternate compatible strings
media: i2c: imx258: Change register settings for variants of the
sensor
media: i2c: imx258: Make HFLIP and VFLIP controls writable
Luis Garcia (5):
drivers: media: i2c: imx258: Use macros
dt-bindings: media: imx258: Add binding for powerdown-gpio
drivers: media: i2c: imx258: Add support for powerdown gpio
drivers: media: i2c: imx258: Add support for reset gpio
media:i2c: imx258: Use v4l2_link_freq_to_bitmap helper
.../i2c/{imx258.yaml => sony,imx258.yaml} | 15 +-
MAINTAINERS | 2 +-
drivers/media/i2c/imx258.c | 1156 +++++++++++------
3 files changed, 753 insertions(+), 420 deletions(-)
rename Documentation/devicetree/bindings/media/i2c/{imx258.yaml => sony,imx258.yaml} (86%)
--
2.42.0
^ permalink raw reply
* [PATCH v3 01/25] media: i2c: imx258: Remove unused defines
From: git @ 2024-04-03 15:03 UTC (permalink / raw)
To: linux-media
Cc: dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel, Luis Garcia
In-Reply-To: <20240403150355.189229-1-git@luigi311.com>
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
The IMX258_FLL_* defines are unused. Remove them.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
Signed-off-by: Luis Garcia <git@luigi311.com>
---
drivers/media/i2c/imx258.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
index a577afb530b7..2dbafd21dd70 100644
--- a/drivers/media/i2c/imx258.c
+++ b/drivers/media/i2c/imx258.c
@@ -29,12 +29,6 @@
#define IMX258_VTS_30FPS_VGA 0x034c
#define IMX258_VTS_MAX 0xffff
-/*Frame Length Line*/
-#define IMX258_FLL_MIN 0x08a6
-#define IMX258_FLL_MAX 0xffff
-#define IMX258_FLL_STEP 1
-#define IMX258_FLL_DEFAULT 0x0c98
-
/* HBLANK control - read only */
#define IMX258_PPL_DEFAULT 5352
--
2.42.0
^ permalink raw reply related
* [PATCH v3 02/25] media: i2c: imx258: Make image geometry meet sensor requirements
From: git @ 2024-04-03 15:03 UTC (permalink / raw)
To: linux-media
Cc: dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel, Luis Garcia
In-Reply-To: <20240403150355.189229-1-git@luigi311.com>
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
The output image is defined as being 4208x3118 pixels in size.
Y_ADD_STA register was set to 0, and Y_ADD_END to 3118, giving
3119 lines total.
The datasheet lists a requirement for Y_ADD_STA to be a multiple
of a power of 2 depending on binning/scaling mode (2 for full pixel,
4 for x2-bin/scale, 8 for (x2-bin)+(x2-subsample) or x4-bin, or 16
for (x4-bin)+(x2-subsample)).
(Y_ADD_END – Y_ADD_STA + 1) also has to be a similar power of 2.
The current configuration for the full res modes breaks that second
requirement, and we can't increase Y_ADD_STA to 1 to retain exactly
the same field of view as that then breaks the first requirement.
For the binned modes, they are worse off as 3118 is not a multiple of
4.
Increase the main mode to 4208x3120 so that it is the same FOV as the
binned modes, with Y_ADD_STA at 0.
Fix Y_ADD_STA and Y_ADD_END for the binned modes so that they meet the
sensor requirements.
This does change the Bayer order as the default configuration is for
H&V flips to be enabled, so readout is from Y_STA_END to Y_ADD_STA,
and this patch has changed Y_STA_END.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
Signed-off-by: Luis Garcia <git@luigi311.com>
---
drivers/media/i2c/imx258.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
index 2dbafd21dd70..4a7048d834c6 100644
--- a/drivers/media/i2c/imx258.c
+++ b/drivers/media/i2c/imx258.c
@@ -111,7 +111,7 @@ struct imx258_mode {
struct imx258_reg_list reg_list;
};
-/* 4208x3118 needs 1267Mbps/lane, 4 lanes */
+/* 4208x3120 needs 1267Mbps/lane, 4 lanes */
static const struct imx258_reg mipi_data_rate_1267mbps[] = {
{ 0x0301, 0x05 },
{ 0x0303, 0x02 },
@@ -148,7 +148,7 @@ static const struct imx258_reg mipi_data_rate_640mbps[] = {
{ 0x0823, 0x00 },
};
-static const struct imx258_reg mode_4208x3118_regs[] = {
+static const struct imx258_reg mode_4208x3120_regs[] = {
{ 0x0136, 0x13 },
{ 0x0137, 0x33 },
{ 0x3051, 0x00 },
@@ -210,7 +210,7 @@ static const struct imx258_reg mode_4208x3118_regs[] = {
{ 0x0348, 0x10 },
{ 0x0349, 0x6F },
{ 0x034A, 0x0C },
- { 0x034B, 0x2E },
+ { 0x034B, 0x2F },
{ 0x0381, 0x01 },
{ 0x0383, 0x01 },
{ 0x0385, 0x01 },
@@ -329,7 +329,7 @@ static const struct imx258_reg mode_2104_1560_regs[] = {
{ 0x0348, 0x10 },
{ 0x0349, 0x6F },
{ 0x034A, 0x0C },
- { 0x034B, 0x2E },
+ { 0x034B, 0x2F },
{ 0x0381, 0x01 },
{ 0x0383, 0x01 },
{ 0x0385, 0x01 },
@@ -448,7 +448,7 @@ static const struct imx258_reg mode_1048_780_regs[] = {
{ 0x0348, 0x10 },
{ 0x0349, 0x6F },
{ 0x034A, 0x0C },
- { 0x034B, 0x2E },
+ { 0x034B, 0x2F },
{ 0x0381, 0x01 },
{ 0x0383, 0x01 },
{ 0x0385, 0x01 },
@@ -562,12 +562,12 @@ static const struct imx258_link_freq_config link_freq_configs[] = {
static const struct imx258_mode supported_modes[] = {
{
.width = 4208,
- .height = 3118,
+ .height = 3120,
.vts_def = IMX258_VTS_30FPS,
.vts_min = IMX258_VTS_30FPS,
.reg_list = {
- .num_of_regs = ARRAY_SIZE(mode_4208x3118_regs),
- .regs = mode_4208x3118_regs,
+ .num_of_regs = ARRAY_SIZE(mode_4208x3120_regs),
+ .regs = mode_4208x3120_regs,
},
.link_freq_index = IMX258_LINK_FREQ_1267MBPS,
},
@@ -707,7 +707,7 @@ static int imx258_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
/* Initialize try_fmt */
try_fmt->width = supported_modes[0].width;
try_fmt->height = supported_modes[0].height;
- try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
+ try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
try_fmt->field = V4L2_FIELD_NONE;
return 0;
@@ -819,7 +819,7 @@ static int imx258_enum_mbus_code(struct v4l2_subdev *sd,
if (code->index > 0)
return -EINVAL;
- code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
+ code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
return 0;
}
@@ -831,7 +831,7 @@ static int imx258_enum_frame_size(struct v4l2_subdev *sd,
if (fse->index >= ARRAY_SIZE(supported_modes))
return -EINVAL;
- if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
+ if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
return -EINVAL;
fse->min_width = supported_modes[fse->index].width;
@@ -847,7 +847,7 @@ static void imx258_update_pad_format(const struct imx258_mode *mode,
{
fmt->format.width = mode->width;
fmt->format.height = mode->height;
- fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
+ fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
fmt->format.field = V4L2_FIELD_NONE;
}
@@ -894,7 +894,7 @@ static int imx258_set_pad_format(struct v4l2_subdev *sd,
mutex_lock(&imx258->mutex);
/* Only one raw bayer(GBRG) order is supported */
- fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
+ fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
mode = v4l2_find_nearest_size(supported_modes,
ARRAY_SIZE(supported_modes), width, height,
--
2.42.0
^ permalink raw reply related
* [PATCH v3 06/25] media: i2c: imx258: Make V4L2_CID_VBLANK configurable.
From: git @ 2024-04-03 15:03 UTC (permalink / raw)
To: linux-media
Cc: dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel, Luis Garcia
In-Reply-To: <20240403150355.189229-1-git@luigi311.com>
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
The values and ranges of V4L2_CID_VBLANK are all computed,
so there is no reason for it to be a read only control.
Remove the register values from the mode lists, add the
handler, and remove the read only flag.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Luis Garcia <git@luigi311.com>
---
drivers/media/i2c/imx258.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
index 495eaada2945..321b504c6a48 100644
--- a/drivers/media/i2c/imx258.c
+++ b/drivers/media/i2c/imx258.c
@@ -30,6 +30,8 @@
#define IMX258_VTS_30FPS_VGA 0x034c
#define IMX258_VTS_MAX 0xffff
+#define IMX258_REG_VTS 0x0340
+
/* HBLANK control - read only */
#define IMX258_PPL_DEFAULT 5352
@@ -202,8 +204,6 @@ static const struct imx258_reg mode_4208x3120_regs[] = {
{ 0x0114, 0x03 },
{ 0x0342, 0x14 },
{ 0x0343, 0xE8 },
- { 0x0340, 0x0C },
- { 0x0341, 0x50 },
{ 0x0344, 0x00 },
{ 0x0345, 0x00 },
{ 0x0346, 0x00 },
@@ -319,8 +319,6 @@ static const struct imx258_reg mode_2104_1560_regs[] = {
{ 0x0114, 0x03 },
{ 0x0342, 0x14 },
{ 0x0343, 0xE8 },
- { 0x0340, 0x06 },
- { 0x0341, 0x38 },
{ 0x0344, 0x00 },
{ 0x0345, 0x00 },
{ 0x0346, 0x00 },
@@ -436,8 +434,6 @@ static const struct imx258_reg mode_1048_780_regs[] = {
{ 0x0114, 0x03 },
{ 0x0342, 0x14 },
{ 0x0343, 0xE8 },
- { 0x0340, 0x03 },
- { 0x0341, 0x4C },
{ 0x0344, 0x00 },
{ 0x0345, 0x00 },
{ 0x0346, 0x00 },
@@ -800,6 +796,11 @@ static int imx258_set_ctrl(struct v4l2_ctrl *ctrl)
BIT(IMX258_HDR_RATIO_MAX));
}
break;
+ case V4L2_CID_VBLANK:
+ ret = imx258_write_reg(imx258, IMX258_REG_VTS,
+ IMX258_REG_VALUE_16BIT,
+ imx258->cur_mode->height + ctrl->val);
+ break;
default:
dev_info(&client->dev,
"ctrl(id:0x%x,val:0x%x) is not handled\n",
@@ -1174,9 +1175,6 @@ static int imx258_init_controls(struct imx258 *imx258)
IMX258_VTS_MAX - imx258->cur_mode->height, 1,
vblank_def);
- if (imx258->vblank)
- imx258->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
-
imx258->hblank = v4l2_ctrl_new_std(
ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_HBLANK,
IMX258_PPL_DEFAULT - imx258->cur_mode->width,
--
2.42.0
^ permalink raw reply related
* [PATCH v3 07/25] media: i2c: imx258: Split out common registers from the mode based ones
From: git @ 2024-04-03 15:03 UTC (permalink / raw)
To: linux-media
Cc: dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel, Luis Garcia
In-Reply-To: <20240403150355.189229-1-git@luigi311.com>
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
Out of all the registers that are defined for each mode, only around
10 differ between the modes.
Split the table into common and mode specific ones.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
Signed-off-by: Luis Garcia <git@luigi311.com>
---
drivers/media/i2c/imx258.c | 236 ++++---------------------------------
1 file changed, 21 insertions(+), 215 deletions(-)
diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
index 321b504c6a48..351add1bc5d5 100644
--- a/drivers/media/i2c/imx258.c
+++ b/drivers/media/i2c/imx258.c
@@ -151,7 +151,7 @@ static const struct imx258_reg mipi_data_rate_640mbps[] = {
{ 0x0823, 0x00 },
};
-static const struct imx258_reg mode_4208x3120_regs[] = {
+static const struct imx258_reg mode_common_regs[] = {
{ 0x0136, 0x13 },
{ 0x0137, 0x33 },
{ 0x3051, 0x00 },
@@ -216,27 +216,17 @@ static const struct imx258_reg mode_4208x3120_regs[] = {
{ 0x0383, 0x01 },
{ 0x0385, 0x01 },
{ 0x0387, 0x01 },
- { 0x0900, 0x00 },
- { 0x0901, 0x11 },
- { 0x0401, 0x00 },
{ 0x0404, 0x00 },
- { 0x0405, 0x10 },
{ 0x0408, 0x00 },
{ 0x0409, 0x00 },
{ 0x040A, 0x00 },
{ 0x040B, 0x00 },
{ 0x040C, 0x10 },
{ 0x040D, 0x70 },
- { 0x040E, 0x0C },
- { 0x040F, 0x30 },
{ 0x3038, 0x00 },
{ 0x303A, 0x00 },
{ 0x303B, 0x10 },
{ 0x300D, 0x00 },
- { 0x034C, 0x10 },
- { 0x034D, 0x70 },
- { 0x034E, 0x0C },
- { 0x034F, 0x30 },
{ 0x0350, 0x01 },
{ 0x0204, 0x00 },
{ 0x0205, 0x00 },
@@ -266,234 +256,43 @@ static const struct imx258_reg mode_4208x3120_regs[] = {
{ 0x0220, 0x00 },
};
+static const struct imx258_reg mode_4208x3120_regs[] = {
+ { 0x0900, 0x00 },
+ { 0x0901, 0x11 },
+ { 0x0401, 0x00 },
+ { 0x0405, 0x10 },
+ { 0x040E, 0x0C },
+ { 0x040F, 0x30 },
+ { 0x034C, 0x10 },
+ { 0x034D, 0x70 },
+ { 0x034E, 0x0C },
+ { 0x034F, 0x30 },
+};
+
static const struct imx258_reg mode_2104_1560_regs[] = {
- { 0x0136, 0x13 },
- { 0x0137, 0x33 },
- { 0x3051, 0x00 },
- { 0x3052, 0x00 },
- { 0x4E21, 0x14 },
- { 0x6B11, 0xCF },
- { 0x7FF0, 0x08 },
- { 0x7FF1, 0x0F },
- { 0x7FF2, 0x08 },
- { 0x7FF3, 0x1B },
- { 0x7FF4, 0x23 },
- { 0x7FF5, 0x60 },
- { 0x7FF6, 0x00 },
- { 0x7FF7, 0x01 },
- { 0x7FF8, 0x00 },
- { 0x7FF9, 0x78 },
- { 0x7FFA, 0x00 },
- { 0x7FFB, 0x00 },
- { 0x7FFC, 0x00 },
- { 0x7FFD, 0x00 },
- { 0x7FFE, 0x00 },
- { 0x7FFF, 0x03 },
- { 0x7F76, 0x03 },
- { 0x7F77, 0xFE },
- { 0x7FA8, 0x03 },
- { 0x7FA9, 0xFE },
- { 0x7B24, 0x81 },
- { 0x7B25, 0x00 },
- { 0x6564, 0x07 },
- { 0x6B0D, 0x41 },
- { 0x653D, 0x04 },
- { 0x6B05, 0x8C },
- { 0x6B06, 0xF9 },
- { 0x6B08, 0x65 },
- { 0x6B09, 0xFC },
- { 0x6B0A, 0xCF },
- { 0x6B0B, 0xD2 },
- { 0x6700, 0x0E },
- { 0x6707, 0x0E },
- { 0x9104, 0x00 },
- { 0x4648, 0x7F },
- { 0x7420, 0x00 },
- { 0x7421, 0x1C },
- { 0x7422, 0x00 },
- { 0x7423, 0xD7 },
- { 0x5F04, 0x00 },
- { 0x5F05, 0xED },
- { 0x0112, 0x0A },
- { 0x0113, 0x0A },
- { 0x0114, 0x03 },
- { 0x0342, 0x14 },
- { 0x0343, 0xE8 },
- { 0x0344, 0x00 },
- { 0x0345, 0x00 },
- { 0x0346, 0x00 },
- { 0x0347, 0x00 },
- { 0x0348, 0x10 },
- { 0x0349, 0x6F },
- { 0x034A, 0x0C },
- { 0x034B, 0x2F },
- { 0x0381, 0x01 },
- { 0x0383, 0x01 },
- { 0x0385, 0x01 },
- { 0x0387, 0x01 },
{ 0x0900, 0x01 },
{ 0x0901, 0x12 },
{ 0x0401, 0x01 },
- { 0x0404, 0x00 },
{ 0x0405, 0x20 },
- { 0x0408, 0x00 },
- { 0x0409, 0x00 },
- { 0x040A, 0x00 },
- { 0x040B, 0x00 },
- { 0x040C, 0x10 },
- { 0x040D, 0x70 },
{ 0x040E, 0x06 },
{ 0x040F, 0x18 },
- { 0x3038, 0x00 },
- { 0x303A, 0x00 },
- { 0x303B, 0x10 },
- { 0x300D, 0x00 },
{ 0x034C, 0x08 },
{ 0x034D, 0x38 },
{ 0x034E, 0x06 },
{ 0x034F, 0x18 },
- { 0x0350, 0x01 },
- { 0x0204, 0x00 },
- { 0x0205, 0x00 },
- { 0x020E, 0x01 },
- { 0x020F, 0x00 },
- { 0x0210, 0x01 },
- { 0x0211, 0x00 },
- { 0x0212, 0x01 },
- { 0x0213, 0x00 },
- { 0x0214, 0x01 },
- { 0x0215, 0x00 },
- { 0x7BCD, 0x01 },
- { 0x94DC, 0x20 },
- { 0x94DD, 0x20 },
- { 0x94DE, 0x20 },
- { 0x95DC, 0x20 },
- { 0x95DD, 0x20 },
- { 0x95DE, 0x20 },
- { 0x7FB0, 0x00 },
- { 0x9010, 0x3E },
- { 0x9419, 0x50 },
- { 0x941B, 0x50 },
- { 0x9519, 0x50 },
- { 0x951B, 0x50 },
- { 0x3030, 0x00 },
- { 0x3032, 0x00 },
- { 0x0220, 0x00 },
};
static const struct imx258_reg mode_1048_780_regs[] = {
- { 0x0136, 0x13 },
- { 0x0137, 0x33 },
- { 0x3051, 0x00 },
- { 0x3052, 0x00 },
- { 0x4E21, 0x14 },
- { 0x6B11, 0xCF },
- { 0x7FF0, 0x08 },
- { 0x7FF1, 0x0F },
- { 0x7FF2, 0x08 },
- { 0x7FF3, 0x1B },
- { 0x7FF4, 0x23 },
- { 0x7FF5, 0x60 },
- { 0x7FF6, 0x00 },
- { 0x7FF7, 0x01 },
- { 0x7FF8, 0x00 },
- { 0x7FF9, 0x78 },
- { 0x7FFA, 0x00 },
- { 0x7FFB, 0x00 },
- { 0x7FFC, 0x00 },
- { 0x7FFD, 0x00 },
- { 0x7FFE, 0x00 },
- { 0x7FFF, 0x03 },
- { 0x7F76, 0x03 },
- { 0x7F77, 0xFE },
- { 0x7FA8, 0x03 },
- { 0x7FA9, 0xFE },
- { 0x7B24, 0x81 },
- { 0x7B25, 0x00 },
- { 0x6564, 0x07 },
- { 0x6B0D, 0x41 },
- { 0x653D, 0x04 },
- { 0x6B05, 0x8C },
- { 0x6B06, 0xF9 },
- { 0x6B08, 0x65 },
- { 0x6B09, 0xFC },
- { 0x6B0A, 0xCF },
- { 0x6B0B, 0xD2 },
- { 0x6700, 0x0E },
- { 0x6707, 0x0E },
- { 0x9104, 0x00 },
- { 0x4648, 0x7F },
- { 0x7420, 0x00 },
- { 0x7421, 0x1C },
- { 0x7422, 0x00 },
- { 0x7423, 0xD7 },
- { 0x5F04, 0x00 },
- { 0x5F05, 0xED },
- { 0x0112, 0x0A },
- { 0x0113, 0x0A },
- { 0x0114, 0x03 },
- { 0x0342, 0x14 },
- { 0x0343, 0xE8 },
- { 0x0344, 0x00 },
- { 0x0345, 0x00 },
- { 0x0346, 0x00 },
- { 0x0347, 0x00 },
- { 0x0348, 0x10 },
- { 0x0349, 0x6F },
- { 0x034A, 0x0C },
- { 0x034B, 0x2F },
- { 0x0381, 0x01 },
- { 0x0383, 0x01 },
- { 0x0385, 0x01 },
- { 0x0387, 0x01 },
{ 0x0900, 0x01 },
{ 0x0901, 0x14 },
{ 0x0401, 0x01 },
- { 0x0404, 0x00 },
{ 0x0405, 0x40 },
- { 0x0408, 0x00 },
- { 0x0409, 0x00 },
- { 0x040A, 0x00 },
- { 0x040B, 0x00 },
- { 0x040C, 0x10 },
- { 0x040D, 0x70 },
{ 0x040E, 0x03 },
{ 0x040F, 0x0C },
- { 0x3038, 0x00 },
- { 0x303A, 0x00 },
- { 0x303B, 0x10 },
- { 0x300D, 0x00 },
{ 0x034C, 0x04 },
{ 0x034D, 0x18 },
{ 0x034E, 0x03 },
{ 0x034F, 0x0C },
- { 0x0350, 0x01 },
- { 0x0204, 0x00 },
- { 0x0205, 0x00 },
- { 0x020E, 0x01 },
- { 0x020F, 0x00 },
- { 0x0210, 0x01 },
- { 0x0211, 0x00 },
- { 0x0212, 0x01 },
- { 0x0213, 0x00 },
- { 0x0214, 0x01 },
- { 0x0215, 0x00 },
- { 0x7BCD, 0x00 },
- { 0x94DC, 0x20 },
- { 0x94DD, 0x20 },
- { 0x94DE, 0x20 },
- { 0x95DC, 0x20 },
- { 0x95DD, 0x20 },
- { 0x95DE, 0x20 },
- { 0x7FB0, 0x00 },
- { 0x9010, 0x3E },
- { 0x9419, 0x50 },
- { 0x941B, 0x50 },
- { 0x9519, 0x50 },
- { 0x951B, 0x50 },
- { 0x3030, 0x00 },
- { 0x3032, 0x00 },
- { 0x0220, 0x00 },
};
static const char * const imx258_test_pattern_menu[] = {
@@ -955,6 +754,13 @@ static int imx258_start_streaming(struct imx258 *imx258)
return ret;
}
+ ret = imx258_write_regs(imx258, mode_common_regs,
+ ARRAY_SIZE(mode_common_regs));
+ if (ret) {
+ dev_err(&client->dev, "%s failed to set common regs\n", __func__);
+ return ret;
+ }
+
/* Apply default values of current mode */
reg_list = &imx258->cur_mode->reg_list;
ret = imx258_write_regs(imx258, reg_list->regs, reg_list->num_of_regs);
--
2.42.0
^ permalink raw reply related
* [PATCH v3 08/25] media: i2c: imx258: Add support for 24MHz clock
From: git @ 2024-04-03 15:03 UTC (permalink / raw)
To: linux-media
Cc: dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel, Luis Garcia
In-Reply-To: <20240403150355.189229-1-git@luigi311.com>
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
There's no reason why only a clock of 19.2MHz is supported.
Indeed this isn't even a frequency listed in the datasheet.
Add support for 24MHz as well.
The PLL settings result in slightly different link frequencies,
so parameterise those.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Luis Garcia <git@luigi311.com>
---
drivers/media/i2c/imx258.c | 130 +++++++++++++++++++++++++++++--------
1 file changed, 102 insertions(+), 28 deletions(-)
diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
index 351add1bc5d5..e4b1b3cbbde5 100644
--- a/drivers/media/i2c/imx258.c
+++ b/drivers/media/i2c/imx258.c
@@ -76,9 +76,6 @@
#define REG_CONFIG_MIRROR_FLIP 0x03
#define REG_CONFIG_FLIP_TEST_PATTERN 0x02
-/* Input clock frequency in Hz */
-#define IMX258_INPUT_CLOCK_FREQ 19200000
-
struct imx258_reg {
u16 address;
u8 val;
@@ -115,7 +112,9 @@ struct imx258_mode {
};
/* 4208x3120 needs 1267Mbps/lane, 4 lanes */
-static const struct imx258_reg mipi_data_rate_1267mbps[] = {
+static const struct imx258_reg mipi_1267mbps_19_2mhz[] = {
+ { 0x0136, 0x13 },
+ { 0x0137, 0x33 },
{ 0x0301, 0x05 },
{ 0x0303, 0x02 },
{ 0x0305, 0x03 },
@@ -133,7 +132,29 @@ static const struct imx258_reg mipi_data_rate_1267mbps[] = {
{ 0x0823, 0xCC },
};
-static const struct imx258_reg mipi_data_rate_640mbps[] = {
+static const struct imx258_reg mipi_1272mbps_24mhz[] = {
+ { 0x0136, 0x18 },
+ { 0x0137, 0x00 },
+ { 0x0301, 0x05 },
+ { 0x0303, 0x02 },
+ { 0x0305, 0x04 },
+ { 0x0306, 0x00 },
+ { 0x0307, 0xD4 },
+ { 0x0309, 0x0A },
+ { 0x030B, 0x01 },
+ { 0x030D, 0x02 },
+ { 0x030E, 0x00 },
+ { 0x030F, 0xD8 },
+ { 0x0310, 0x00 },
+ { 0x0820, 0x13 },
+ { 0x0821, 0x4C },
+ { 0x0822, 0xCC },
+ { 0x0823, 0xCC },
+};
+
+static const struct imx258_reg mipi_640mbps_19_2mhz[] = {
+ { 0x0136, 0x13 },
+ { 0x0137, 0x33 },
{ 0x0301, 0x05 },
{ 0x0303, 0x02 },
{ 0x0305, 0x03 },
@@ -151,9 +172,27 @@ static const struct imx258_reg mipi_data_rate_640mbps[] = {
{ 0x0823, 0x00 },
};
+static const struct imx258_reg mipi_642mbps_24mhz[] = {
+ { 0x0136, 0x18 },
+ { 0x0137, 0x00 },
+ { 0x0301, 0x05 },
+ { 0x0303, 0x02 },
+ { 0x0305, 0x04 },
+ { 0x0306, 0x00 },
+ { 0x0307, 0x6B },
+ { 0x0309, 0x0A },
+ { 0x030B, 0x01 },
+ { 0x030D, 0x02 },
+ { 0x030E, 0x00 },
+ { 0x030F, 0xD8 },
+ { 0x0310, 0x00 },
+ { 0x0820, 0x0A },
+ { 0x0821, 0x00 },
+ { 0x0822, 0x00 },
+ { 0x0823, 0x00 },
+};
+
static const struct imx258_reg mode_common_regs[] = {
- { 0x0136, 0x13 },
- { 0x0137, 0x33 },
{ 0x3051, 0x00 },
{ 0x3052, 0x00 },
{ 0x4E21, 0x14 },
@@ -313,10 +352,6 @@ static const char * const imx258_supply_name[] = {
#define IMX258_NUM_SUPPLIES ARRAY_SIZE(imx258_supply_name)
-/* Configurations for supported link frequencies */
-#define IMX258_LINK_FREQ_634MHZ 633600000ULL
-#define IMX258_LINK_FREQ_320MHZ 320000000ULL
-
enum {
IMX258_LINK_FREQ_1267MBPS,
IMX258_LINK_FREQ_640MBPS,
@@ -335,25 +370,48 @@ static u64 link_freq_to_pixel_rate(u64 f)
}
/* Menu items for LINK_FREQ V4L2 control */
-static const s64 link_freq_menu_items[] = {
- IMX258_LINK_FREQ_634MHZ,
- IMX258_LINK_FREQ_320MHZ,
+/* Configurations for supported link frequencies */
+static const s64 link_freq_menu_items_19_2[] = {
+ 633600000ULL,
+ 320000000ULL,
+};
+
+static const s64 link_freq_menu_items_24[] = {
+ 636000000ULL,
+ 321000000ULL,
};
/* Link frequency configs */
-static const struct imx258_link_freq_config link_freq_configs[] = {
+static const struct imx258_link_freq_config link_freq_configs_19_2[] = {
[IMX258_LINK_FREQ_1267MBPS] = {
.pixels_per_line = IMX258_PPL_DEFAULT,
.reg_list = {
- .num_of_regs = ARRAY_SIZE(mipi_data_rate_1267mbps),
- .regs = mipi_data_rate_1267mbps,
+ .num_of_regs = ARRAY_SIZE(mipi_1267mbps_19_2mhz),
+ .regs = mipi_1267mbps_19_2mhz,
}
},
[IMX258_LINK_FREQ_640MBPS] = {
.pixels_per_line = IMX258_PPL_DEFAULT,
.reg_list = {
- .num_of_regs = ARRAY_SIZE(mipi_data_rate_640mbps),
- .regs = mipi_data_rate_640mbps,
+ .num_of_regs = ARRAY_SIZE(mipi_640mbps_19_2mhz),
+ .regs = mipi_640mbps_19_2mhz,
+ }
+ },
+};
+
+static const struct imx258_link_freq_config link_freq_configs_24[] = {
+ [IMX258_LINK_FREQ_1267MBPS] = {
+ .pixels_per_line = IMX258_PPL_DEFAULT,
+ .reg_list = {
+ .num_of_regs = ARRAY_SIZE(mipi_1272mbps_24mhz),
+ .regs = mipi_1272mbps_24mhz,
+ }
+ },
+ [IMX258_LINK_FREQ_640MBPS] = {
+ .pixels_per_line = IMX258_PPL_DEFAULT,
+ .reg_list = {
+ .num_of_regs = ARRAY_SIZE(mipi_642mbps_24mhz),
+ .regs = mipi_642mbps_24mhz,
}
},
};
@@ -410,6 +468,9 @@ struct imx258 {
/* Current mode */
const struct imx258_mode *cur_mode;
+ const struct imx258_link_freq_config *link_freq_configs;
+ const s64 *link_freq_menu_items;
+
/*
* Mutex for serialized access:
* Protect sensor module set pad format and start/stop streaming safely.
@@ -713,7 +774,7 @@ static int imx258_set_pad_format(struct v4l2_subdev *sd,
imx258->cur_mode = mode;
__v4l2_ctrl_s_ctrl(imx258->link_freq, mode->link_freq_index);
- link_freq = link_freq_menu_items[mode->link_freq_index];
+ link_freq = imx258->link_freq_menu_items[mode->link_freq_index];
pixel_rate = link_freq_to_pixel_rate(link_freq);
__v4l2_ctrl_s_ctrl_int64(imx258->pixel_rate, pixel_rate);
/* Update limits and set FPS to default */
@@ -727,7 +788,7 @@ static int imx258_set_pad_format(struct v4l2_subdev *sd,
vblank_def);
__v4l2_ctrl_s_ctrl(imx258->vblank, vblank_def);
h_blank =
- link_freq_configs[mode->link_freq_index].pixels_per_line
+ imx258->link_freq_configs[mode->link_freq_index].pixels_per_line
- imx258->cur_mode->width;
__v4l2_ctrl_modify_range(imx258->hblank, h_blank,
h_blank, 1, h_blank);
@@ -747,7 +808,7 @@ static int imx258_start_streaming(struct imx258 *imx258)
/* Setup PLL */
link_freq_index = imx258->cur_mode->link_freq_index;
- reg_list = &link_freq_configs[link_freq_index].reg_list;
+ reg_list = &imx258->link_freq_configs[link_freq_index].reg_list;
ret = imx258_write_regs(imx258, reg_list->regs, reg_list->num_of_regs);
if (ret) {
dev_err(&client->dev, "%s failed to set plls\n", __func__);
@@ -946,9 +1007,9 @@ static int imx258_init_controls(struct imx258 *imx258)
imx258->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
&imx258_ctrl_ops,
V4L2_CID_LINK_FREQ,
- ARRAY_SIZE(link_freq_menu_items) - 1,
+ ARRAY_SIZE(link_freq_menu_items_19_2) - 1,
0,
- link_freq_menu_items);
+ imx258->link_freq_menu_items);
if (imx258->link_freq)
imx258->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
@@ -964,8 +1025,10 @@ static int imx258_init_controls(struct imx258 *imx258)
if (vflip)
vflip->flags |= V4L2_CTRL_FLAG_READ_ONLY;
- pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
- pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]);
+ pixel_rate_max =
+ link_freq_to_pixel_rate(imx258->link_freq_menu_items[0]);
+ pixel_rate_min =
+ link_freq_to_pixel_rate(imx258->link_freq_menu_items[1]);
/* By default, PIXEL_RATE is read only */
imx258->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops,
V4L2_CID_PIXEL_RATE,
@@ -1086,8 +1149,19 @@ static int imx258_probe(struct i2c_client *client)
} else {
val = clk_get_rate(imx258->clk);
}
- if (val != IMX258_INPUT_CLOCK_FREQ) {
- dev_err(&client->dev, "input clock frequency not supported\n");
+
+ switch (val) {
+ case 19200000:
+ imx258->link_freq_configs = link_freq_configs_19_2;
+ imx258->link_freq_menu_items = link_freq_menu_items_19_2;
+ break;
+ case 24000000:
+ imx258->link_freq_configs = link_freq_configs_24;
+ imx258->link_freq_menu_items = link_freq_menu_items_24;
+ break;
+ default:
+ dev_err(&client->dev, "input clock frequency of %u not supported\n",
+ val);
return -EINVAL;
}
--
2.42.0
^ permalink raw reply related
* [PATCH v3 22/25] dt-bindings: media: imx258: Add binding for powerdown-gpio
From: git @ 2024-04-03 15:03 UTC (permalink / raw)
To: linux-media
Cc: dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel, Luis Garcia, Ondrej Jirman
In-Reply-To: <20240403150355.189229-1-git@luigi311.com>
From: Luis Garcia <git@luigi311.com>
Add powerdown-gpio binding as it is required for some boards
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Signed-off-by: Luis Garcia <git@luigi311.com>
---
Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
index c978abc0cdb3..33338139e6e8 100644
--- a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
@@ -36,6 +36,10 @@ properties:
reg:
maxItems: 1
+ powerdown-gpios:
+ description:
+ Reference to the GPIO connected to the PWDN pin, if any.
+
reset-gpios:
description: |-
Reference to the GPIO connected to the XCLR pin, if any.
--
2.42.0
^ permalink raw reply related
* [PATCH v3 24/25] drivers: media: i2c: imx258: Add support for reset gpio
From: git @ 2024-04-03 15:03 UTC (permalink / raw)
To: linux-media
Cc: dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel, Luis Garcia, Ondrej Jirman
In-Reply-To: <20240403150355.189229-1-git@luigi311.com>
From: Luis Garcia <git@luigi311.com>
It was documented in DT, but not implemented.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Luis Garcia <git@luigi311.com>
---
drivers/media/i2c/imx258.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
index 163f04f6f954..4c117c4829f1 100644
--- a/drivers/media/i2c/imx258.c
+++ b/drivers/media/i2c/imx258.c
@@ -680,6 +680,7 @@ struct imx258 {
unsigned int csi2_flags;
struct gpio_desc *powerdown_gpio;
+ struct gpio_desc *reset_gpio;
/*
* Mutex for serialized access:
@@ -1232,7 +1233,11 @@ static int imx258_power_on(struct device *dev)
regulator_bulk_disable(IMX258_NUM_SUPPLIES, imx258->supplies);
}
- return ret;
+ gpiod_set_value_cansleep(imx258->reset_gpio, 0);
+
+ usleep_range(400, 500);
+
+ return 0;
}
static int imx258_power_off(struct device *dev)
@@ -1243,6 +1248,7 @@ static int imx258_power_off(struct device *dev)
clk_disable_unprepare(imx258->clk);
regulator_bulk_disable(IMX258_NUM_SUPPLIES, imx258->supplies);
+ gpiod_set_value_cansleep(imx258->reset_gpio, 1);
gpiod_set_value_cansleep(imx258->powerdown_gpio, 1);
return 0;
@@ -1554,6 +1560,12 @@ static int imx258_probe(struct i2c_client *client)
if (IS_ERR(imx258->powerdown_gpio))
return PTR_ERR(imx258->powerdown_gpio);
+ /* request optional reset pin */
+ imx258->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(imx258->reset_gpio))
+ return PTR_ERR(imx258->reset_gpio);
+
/* Initialize subdev */
v4l2_i2c_subdev_init(&imx258->sd, client, &imx258_subdev_ops);
--
2.42.0
^ permalink raw reply related
* Re: [PATCH 1/6] dt-bindings: adc: ad7173: add support for ad411x
From: David Lechner @ 2024-04-03 15:14 UTC (permalink / raw)
To: Ceclan, Dumitru
Cc: dumitru.ceclan, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-iio, devicetree, linux-kernel
In-Reply-To: <dce3ae6c-6e65-4134-8927-549e9b4afd4c@gmail.com>
On Wed, Apr 3, 2024 at 5:08 AM Ceclan, Dumitru <mitrutzceclan@gmail.com> wrote:
>
> On 03/04/2024 10:45, Ceclan, Dumitru wrote:
> > On 01/04/2024 23:22, David Lechner wrote:
> >> On Mon, Apr 1, 2024 at 2:37 PM David Lechner <dlechner@baylibre.com> wrote:
> >>>
> >>> On Mon, Apr 1, 2024 at 10:10 AM Dumitru Ceclan via B4 Relay
> >>> <devnull+dumitru.ceclan.analog.com@kernel.org> wrote:
> >
> > ...
> >
> >>
> >> Also, I just noticed that AD411x have only one AVDD input instead of
> >> AVDD1 and AVDD2. So we need an if statement that says if properties:
> >> compatible: enum: - adi,ad411x, then properties: avdd2-supply: false.
> >
> > Already addressed by this:
> > "
> > # Only ad7172-4, ad7173-8 and ad7175-8 support vref2
> > - if:
> > properties:
> > compatible:
> > not:
> > contains:
> > enum:
> > - adi,ad7172-4
> > - adi,ad7173-8
> > - adi,ad7175-8
> > then:
> > properties:
> > vref2-supply: false
> > patternProperties:
> > "^channel@[0-9a-f]$":
> > properties:
> > adi,reference-select:
> > enum:
> > - vref
> > - refout-avss
> > - avdd
> > "
>
> Mistaken vref2-supply to avdd2-supply.
>
> But still, the presence of avdd2-supply does not influence anything at all.
> Driver does not use it, you cannot select it for channel conversions.
> Would a restriction like this really be required?
It is true that it is not likely to cause any problems we don't fix
this but why would we want the bindings to intentionally be incorrect
when there is an easy fix? Driver implementations should not influence
leaving something out of the bindings [1].
[1]: https://www.kernel.org/doc/html//v5.10/devicetree/bindings/writing-bindings.html#overall-design
^ permalink raw reply
* [PATCH v2 0/3] arm64: dts: rockchip: add Forlinx OK3588-C
From: Dmitry Yashin @ 2024-04-03 15:12 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree,
linux-arm-kernel, linux-kernel, Dmitry Yashin
This series add support for Forlinx RK3588 based SoM and carrier board.
Devicetree split into .dtsi (FET3588-C SoM) and .dts (OK3588-C Board).
v1 Link: https://lore.kernel.org/all/cover.1710506373.git.dmt.yashin@gmail.com/
Changes in v2:
Patch 1:
- no changes
Patch 2:
- rename dtsi to rk3588-fet3588-c.dtsi
- reorder regulator nodes
- reorder properties in sdhci
- drop regulator-always-on from vdd_gpu_s0
- enable tsadc
Patch 3:
- update dtsi include
- set more generic names for tca6424a, nau8822 and sound nodes
- reorder regulator and nodes in pinctrl
- reorder properties in gmac and sdmmc
- drop vmmc-supply from sdmmc and update max-frequency
- enable gpu (depends on for-next branch)
- enable usb_host nodes
Dmitry Yashin (3):
dt-bindings: arm: rockchip: add Forlinx FET3588-C
arm64: dts: rockchip: add Forlinx FET3588-C
arm64: dts: rockchip: add Forlinx OK3588-C
.../devicetree/bindings/arm/rockchip.yaml | 7 +
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3588-fet3588-c.dtsi | 558 ++++++++++++++++++
.../boot/dts/rockchip/rk3588-ok3588-c.dts | 409 +++++++++++++
4 files changed, 975 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
--
2.39.2
^ permalink raw reply
* [PATCH v2 1/3] dt-bindings: arm: rockchip: add Forlinx FET3588-C
From: Dmitry Yashin @ 2024-04-03 15:12 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree,
linux-arm-kernel, linux-kernel, Dmitry Yashin, Conor Dooley
In-Reply-To: <20240403151229.30577-1-dmt.yashin@gmail.com>
FET3588-C is an System on Module made by Forlinx based on Rockchip RK3588.
This SoM used by OK3588-C Board.
FET3588-C features:
- Rockchip RK3588
- LPDDR4 4/8 GB
- eMMC 32/64 GB
Add devicetree binding for Forlinx FET3588-C SoM.
Signed-off-by: Dmitry Yashin <dmt.yashin@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
(no changes since v1)
Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 99bd5e2c76a0..2e61c3980444 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -198,6 +198,13 @@ properties:
- const: firefly,rk3568-roc-pc
- const: rockchip,rk3568
+ - description: Forlinx FET3588-C SoM
+ items:
+ - enum:
+ - forlinx,ok3588-c
+ - const: forlinx,fet3588-c
+ - const: rockchip,rk3588
+
- description: FriendlyElec NanoPi R2 series boards
items:
- enum:
--
2.39.2
^ permalink raw reply related
* [PATCH v2 2/3] arm64: dts: rockchip: add Forlinx FET3588-C
From: Dmitry Yashin @ 2024-04-03 15:12 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree,
linux-arm-kernel, linux-kernel, Dmitry Yashin
In-Reply-To: <20240403151229.30577-1-dmt.yashin@gmail.com>
FET3588-C is an System on Module made by Forlinx based on Rockchip RK3588.
This SoM used by OK3588-C Board.
FET3588-C features:
- Rockchip RK3588
- LPDDR4 4/8 GB
- eMMC 32/64 GB
Add support for Forlinx FET3588-C SoM.
Signed-off-by: Dmitry Yashin <dmt.yashin@gmail.com>
---
Changes in v2:
- rename dtsi to rk3588-fet3588-c
- reorder regulator nodes
- reorder properties in sdhci
- drop regulator-always-on from vdd_gpu_s0
- enable tsadc
.../boot/dts/rockchip/rk3588-fet3588-c.dtsi | 558 ++++++++++++++++++
1 file changed, 558 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi
new file mode 100644
index 000000000000..47e64d547ea9
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi
@@ -0,0 +1,558 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3588.dtsi"
+
+/ {
+ compatible = "forlinx,fet3588-c", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_rgb_b>;
+
+ io-led {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ pcie20_avdd0v85: pcie20-avdd0v85-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie20_avdd0v85";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ vin-supply = <&vdd_0v85_s0>;
+ };
+
+ pcie20_avdd1v8: pcie20-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie20_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ pcie30_avdd0v75: pcie30-avdd0v75-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v75";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ vin-supply = <&avdd_0v75_s0>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc4v0_sys: vcc4v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc4v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+ mem-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+ mem-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+ mem-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+ mem-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m2_xfer>;
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&pinctrl {
+ leds {
+ led_rgb_b: led-rgb-b {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sdio;
+ no-sd;
+ non-removable;
+ status = "okay";
+};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ num-cs = <1>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+ system-power-controller;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "avcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "avdd_1v2_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
--
2.39.2
^ permalink raw reply related
* [PATCH v2 3/3] arm64: dts: rockchip: add Forlinx OK3588-C
From: Dmitry Yashin @ 2024-04-03 15:12 UTC (permalink / raw)
To: Heiko Stuebner, linux-rockchip
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree,
linux-arm-kernel, linux-kernel, Dmitry Yashin
In-Reply-To: <20240403151229.30577-1-dmt.yashin@gmail.com>
OK3588-C is the carrier board for FET3588-C System on Module.
OK3588-C features:
- 2x 1GbE Realtek RTL8211F Ethernet
- 1x HDMI Type A out
- 1x HDMI Type A in
- 3x USB 3.1 Type C (2x OTG and 1x serial console)
- 1x USB 2.0 Type A
- 1x USB 3.0 & USB 2.0 Combo M.2 M Key (4G/5G modem)
- 1x PCIE 2.0 M.2 E Key (1 lane)
- 1x PCIE 2.0 PCIe (1 lane)
- 1x PCIE 3.0 PCIe (4 lanes)
- 1x TF scard slot
- 5x MIPI CSI
- 2x MIP DSI
- 2x CAN2.0B
- 1x RS485
- 1x NAU8822 onboard audio
- 1x FAN connector
- 1x RTC
- 20-pin expansion header
- ADC keys
Add support for Forlinx OK3588-C board.
Signed-off-by: Dmitry Yashin <dmt.yashin@gmail.com>
---
Changes in v2:
- update dtsi include
- set more generic names for tca6424a, nau8822 and sound nodes
- reorder regulator and nodes in pinctrl
- reorder properties in gmac and sdmmc
- drop vmmc-supply from sdmmc and update max-frequency
- enable gpu (depends on for-next branch)
- enable usb_host nodes
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3588-ok3588-c.dts | 409 ++++++++++++++++++
2 files changed, 410 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 0192980ef37f..c6a7fe9522ae 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -116,6 +116,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
new file mode 100644
index 000000000000..009566d881f3
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3588-fet3588-c.dtsi"
+
+/ {
+ model = "Forlinx OK3588-C Board";
+ compatible = "forlinx,ok3588-c", "forlinx,fet3588-c", "rockchip,rk3588";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc1 = &sdmmc;
+ };
+
+ adc-keys-0 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-maskrom {
+ label = "Maskrom";
+ linux,code = <KEY_SETUP>;
+ press-threshold-microvolt = <400>;
+ };
+ };
+
+ adc-keys-1 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-volume-up {
+ label = "V+/Recovery";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <17000>;
+ };
+
+ button-volume-down {
+ label = "V-";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <417000>;
+ };
+
+ button-menu {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <890000>;
+ };
+
+ button-escape {
+ label = "ESC";
+ linux,code = <KEY_ESC>;
+ press-threshold-microvolt = <1235000>;
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 95 145 195 255>;
+ fan-supply = <&vcc12v_dcin>;
+ pwms = <&pwm2 0 50000 0>;
+ #cooling-cells = <2>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ simple-audio-card,name = "RK3588 OK3588-C Audio";
+ simple-audio-card,bitclock-master = <&masterdai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&masterdai>;
+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,pin-switches = "Headphones", "Speaker";
+ simple-audio-card,widgets =
+ "Headphones", "Headphones",
+ "Speaker", "Speaker",
+ "Microphone", "Internal Microphone",
+ "Microphone", "Headset Microphone";
+ simple-audio-card,routing =
+ "Headphones", "LHP",
+ "Headphones", "RHP",
+ "Speaker", "LSPK",
+ "Speaker", "RSPK",
+ "LMICP", "Headset Microphone",
+ "RMICP", "Internal Microphone";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0_8ch>;
+ };
+
+ masterdai: simple-audio-card,codec {
+ sound-dai = <&nau8822>;
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc1v8_sys: vcc1v8-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_pcie30: vcc3v3_pcie30-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie30";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+};
+
+&gmac0 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii-rxid";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ tx_delay = <0x44>;
+ rx_delay = <0x00>;
+ status = "okay";
+};
+
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-rxid";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_tx_bus2
+ &gmac1_rx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus>;
+ tx_delay = <0x44>;
+ rx_delay = <0x00>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ tca6424a: gpio@23 {
+ compatible = "ti,tca6424";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tca6424a_int>;
+ vcc-supply = <&vcc3v3_sys>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m2_xfer>;
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ nau8822: audio-codec@1a {
+ compatible = "nuvoton,nau8822";
+ reg = <0x1a>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@1 {
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8211f_0_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@2 {
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0x2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8211f_1_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pcie2x1l0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_0_rst>;
+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
+ status = "okay";
+};
+
+&pcie2x1l2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_2_rst>;
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_rst>;
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
+&pinctrl {
+ pcie2 {
+ pcie2_0_rst: pcie2-0-rst {
+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie2_2_rst: pcie2-2-rst {
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie3 {
+ pcie3_rst: pcie3-rst {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ rtl8211f {
+ rtl8211f_0_rst: rtl8211f-0-rst {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ rtl8211f_1_rst: rtl8211f-1-rst {
+ rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sound {
+ hp_detect: hp-detect {
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ tca6424a {
+ tca6424a_int: tca6424a-int {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&avcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
--
2.39.2
^ permalink raw reply related
* Re: [PATCH 1/6] dt-bindings: adc: ad7173: add support for ad411x
From: David Lechner @ 2024-04-03 15:22 UTC (permalink / raw)
To: Ceclan, Dumitru
Cc: dumitru.ceclan, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-iio, devicetree, linux-kernel
In-Reply-To: <0a72de29-6d25-4d2d-9824-ca407af69153@gmail.com>
On Wed, Apr 3, 2024 at 2:50 AM Ceclan, Dumitru <mitrutzceclan@gmail.com> wrote:
>
> On 02/04/2024 00:16, David Lechner wrote:
> > On Mon, Apr 1, 2024 at 2:37 PM David Lechner <dlechner@baylibre.com> wrote:
> >>
> >> On Mon, Apr 1, 2024 at 10:10 AM Dumitru Ceclan via B4 Relay
> >> <devnull+dumitru.ceclan.analog.com@kernel.org> wrote:
> >>>
> >>> From: Dumitru Ceclan <dumitru.ceclan@analog.com>
> >>>
>
> ...
>
> >>>
> >>> properties:
> >>> reg:
> >>> + description:
> >>> + Reg values 16-19 are only permitted for ad4111/ad4112 current channels.
> >>> minimum: 0
> >>> - maximum: 15
> >>> + maximum: 19
> >>
> >> This looks wrong. Isn't reg describing the number of logical channels
> >> (# of channel config registers)?
> >>
> >> After reviewing the driver, I see that > 16 is used as a way of
> >> flagging current inputs, but still seems like the wrong way to do it.
> >> See suggestion below.
> >>
> >>>
> >>> diff-channels:
> >>> + description:
> >>> + For using current channels specify only the positive channel.
> >>> + (IIN2+, IIN2−) -> diff-channels = <2 0>
> >>
> >> I find this a bit confusing since 2 is already VIN2 and 0 is already
> >> VIN0. I think it would make more sense to assign unique channel
> >> numbers individually to the negative and positive current inputs.
> >> Also, I think it makes sense to use the same numbers that the
> >> registers in the datasheet use (8 - 11 for negative and 12 to 15 for
> >> positive).
> >>
> >> So: (IIN2+, IIN2−) -> diff-channels = <13 10>
> >
> > Thinking about this a bit more...
> >
> > Since the current inputs have dedicated pins and aren't mix-and-match
> > with multiple valid wiring configurations like the voltage inputs, do
> > we even need to describe them in the devicetree?
> >
> > In the driver, the current channels would just be hard-coded like the
> > temperature channel since there isn't any application-specific
> > variation.
>
> Sure, but we still need to offer the user a way to configure which
> current inputs he wants and if they should use bipolar or unipolar coding.
From the datasheet, it looks like only positive current input is
allowed so I'm not sure bipolar applies here. But, yes, if there is
some other variation in wiring or electrical signal that needs to be
describe here, then it makes sense to allow a channel configuration
node for it.
>
> One other issue that arises is the fact that we will reserve 5
> (including temp) channels out of the 15 that the user has the option to
> configure. While the binding will configure only 11 channels for
> example, the driver probe will error out with the message "Too many
> channels specified".
>
Surely the driver could be changed to fix this, if needed. :-)
^ permalink raw reply
* [PATCH v3 25/25] media:i2c: imx258: Use v4l2_link_freq_to_bitmap helper
From: git @ 2024-04-03 15:03 UTC (permalink / raw)
To: linux-media
Cc: dave.stevenson, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel, Luis Garcia
In-Reply-To: <20240403150355.189229-1-git@luigi311.com>
From: Luis Garcia <git@luigi311.com>
Use the v4l2_link_freq_to_bitmap() helper to figure out which
driver-supported link freq can be used on a given system.
Signed-off-by: Luis Garcia <git@luigi311.com>
---
drivers/media/i2c/imx258.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
index 4c117c4829f1..038f40a1f800 100644
--- a/drivers/media/i2c/imx258.c
+++ b/drivers/media/i2c/imx258.c
@@ -674,6 +674,7 @@ struct imx258 {
/* Current mode */
const struct imx258_mode *cur_mode;
+ unsigned long link_freq_bitmap;
const struct imx258_link_freq_config *link_freq_configs;
const s64 *link_freq_menu_items;
unsigned int lane_mode_idx;
@@ -1533,6 +1534,17 @@ static int imx258_probe(struct i2c_client *client)
return ret;
}
+ ret = v4l2_link_freq_to_bitmap(&client->dev,
+ ep.link_frequencies,
+ ep.nr_of_link_frequencies,
+ imx258->link_freq_menu_items,
+ ARRAY_SIZE(link_freq_menu_items_19_2),
+ &imx258->link_freq_bitmap);
+ if (ret) {
+ dev_err(&client->dev, "Link frequency not supported\n");
+ goto error_endpoint_free;
+ }
+
/* Get number of data lanes */
switch (ep.bus.mipi_csi2.num_data_lanes) {
case 2:
--
2.42.0
^ permalink raw reply related
* Re: Fixing the devicetree of Rock 5 Model B (and possibly others)
From: Pratham Patel @ 2024-04-03 15:26 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Saravana Kannan, Dragan Simic, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, regressions, stable
On Wed Apr 3, 2024 at 7:22 PM IST, Sebastian Reichel wrote:
> Hi,
>
> On Wed, Apr 03, 2024 at 01:03:07AM +0000, Pratham Patel wrote:
> > > > > Also, can you give the output of <debugfs>/devices_deferred for the
> > > > > good vs bad case?
> > > >
> > > > I can't provide you with requested output from the bad case, since the
> > > > kernel never moves past this to an initramfs rescue shell, but following
> > > > is the output from v6.8.1 (**with aforementioned patch reverted**).
> > > >
> > > > # cat /sys/kernel/debug/devices_deferred
> > > > fc400000.usb platform: wait for supplier /phy@fed90000/usb3-port
> > > > 1-0022 typec_fusb302: cannot register tcpm port
> > > > fc000000.usb platform: wait for supplier /phy@fed80000/usb3-port
> > > >
> > > > It seems that v6.8.2 works _without needing to revert the patch_. I will
> > > > have to look into this sometime this week but it seems like
> > > > a8037ceb8964 (arm64: dts: rockchip: drop rockchip,trcm-sync-tx-only from rk3588 i2s)
> > > > seems to be the one that fixed the root issue. I will have to test it
> > > > sometime later this week.
> > >
> > > Ok, once you find the patch that fixes things, let me know too.
> >
> > Will do!
>
> FWIW the v6.8.1 kernel referenced above is definitely patched, since
> upstream's Rock 5B DT does neither describe fusb302, nor the USB
> port it is connected to.
>
> We have a few Rock 5B in Kernel CI and upstream boots perfectly
> fine:
>
> https://lava.collabora.dev/scheduler/device_type/rk3588-rock-5b
Hmm, weird then. I can confirm that v6.8.1 doesn't _always_ boot. It
boots some times but still fails a majority of times. There is a
2 out of 10 chance that v6.8.1 will not boot. If you keep rebooting
enough times, you might get it to boot but the next boot is
likely to be borked. :(
That said, v6.8.2 might still have the same issue, but the probably of a
failed boot might be _lesser_ than v6.8.1 (from what I saw). I will
verify that behaviour sometime tomorrow or day after tomorrow.
>
> So it could be one of your downstream patches, which is introducing
> this problem.
I thought so too. So I built a vanilla kernel from the release tarball
of v6.8.1, using GCC + arm64 defconfig. I also tried using LLVM just in
case but noticed the same result.
-- Pratham Patel
^ permalink raw reply
* Re: [PATCH net-next v6 11/17] dt-bindings: net: pse-pd: Add another way of describing several PSE PIs
From: Oleksij Rempel @ 2024-04-03 15:27 UTC (permalink / raw)
To: Rob Herring
Cc: Kory Maincent, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Krzysztof Kozlowski,
Conor Dooley, Mark Brown, Frank Rowand, Andrew Lunn,
Heiner Kallweit, Russell King, Thomas Petazzoni, netdev,
linux-kernel, linux-doc, devicetree, Dent Project
In-Reply-To: <20240403144448.GB3508225-robh@kernel.org>
On Wed, Apr 03, 2024 at 09:44:48AM -0500, Rob Herring wrote:
> On Tue, Apr 02, 2024 at 05:47:58PM +0200, Oleksij Rempel wrote:
> > On Tue, Apr 02, 2024 at 08:26:37AM -0500, Rob Herring wrote:
> > > > + pairsets:
> > > > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > > > + description:
> > > > + List of phandles, each pointing to the power supply for the
> > > > + corresponding pairset named in 'pairset-names'. This property
> > > > + aligns with IEEE 802.3-2022, Section 33.2.3 and 145.2.4.
> > > > + PSE Pinout Alternatives (as per IEEE 802.3-2022 Table 145\u20133)
> > > > + |-----------|---------------|---------------|---------------|---------------|
> > > > + | Conductor | Alternative A | Alternative A | Alternative B | Alternative B |
> > > > + | | (MDI-X) | (MDI) | (X) | (S) |
> > > > + |-----------|---------------|---------------|---------------|---------------|
> > > > + | 1 | Negative VPSE | Positive VPSE | \u2014 | \u2014 |
> > > > + | 2 | Negative VPSE | Positive VPSE | \u2014 | \u2014 |
> > > > + | 3 | Positive VPSE | Negative VPSE | \u2014 | \u2014 |
> > > > + | 4 | \u2014 | \u2014 | Negative VPSE | Positive VPSE |
> > > > + | 5 | \u2014 | \u2014 | Negative VPSE | Positive VPSE |
> > > > + | 6 | Positive VPSE | Negative VPSE | \u2014 | \u2014 |
> > > > + | 7 | \u2014 | \u2014 | Positive VPSE | Negative VPSE |
> > > > + | 8 | \u2014 | \u2014 | Positive VPSE | Negative VPSE |
> > > > + minItems: 1
> > > > + maxItems: 2
> > >
> > > "pairsets" does not follow the normal design pattern of foos, foo-names,
> > > and #foo-cells. You could add #foo-cells I suppose, but what would cells
> > > convey? I don't think it's a good fit for what you need.
> > >
> > > The other oddity is the number of entries and the names are fixed. That
> > > is usually defined per consumer.
> > >
> > > As each entry is just a power rail, why can't the regulator binding be
> > > used here?
> >
> > I'm not against describing it consequent with regulator till the wire
> > end, but right now I have no idea how it should be described by using
> > regulator bindings. There are maximum 2 rails going in to PSE PI on one
> > side and 4 rails with at least 5 combinations supported by standard on
> > other side. Instead of inventing anything new, I suggested to describe
> > supported output combinations by using IEEE 802.3 standard.
>
> There's 4 combinations above, what's the 5th combination? SPE?
The 5th combination is PoE4 where two rails are supplying power at same
time.
First 4 variants for PoE: one or two positive rails are attached (but
only one is used at same time) to pairs 1-2 or 3-4, or 5-6, or 7-8. Or
support all of combinations if some advanced PSE PI is present. PSE PI
is kind of MUX for regulators.
One more variant in case of PoE4: two positive rail are attached at same
time, one to 1-2, second to 5-6. May be one more variant with opposite
polarity, this will be the 6th combination.
> Seems to me you just describe the 2 rails going to the connector and
> then describe all the variations the connector supports. The PSE
> (h/w) has little to do with which variations are supported, right?
No. In case of mutli-channel PSE, it needs to know if channels are
attached to one port or to different ports. PSE is not only responsible
to enable the power, it runs classification of devices attached to the
port, so it will decide, which rail should be enabled.
> For example, MDI-X vs. MDI support is determined by the PHY, right?
Yes and No. Until PSE do not start supplying power, PHY will not be able to
start communication with the remote PHY, so it will not be able to
detect MDI/X configuration.
Polarity configuration is important for user space or user to get
information about supported pin configuration and if possible,
change the configuration.
> Or it has to be supported by both the PHY and PSE?
In most cases PSE and PHY work independently from each other, they just
share same port. Potential exception are:
- in case data line should not be shared with power lines, we need to
know what pins are used for power, this information would help to
provide PHY configuration.
- in case PHY autoneg signals disturb PoE classification, we need to
coordinate PHY and PSE states.
Regards,
Oleksij
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [PATCH v4 0/5] Pinephone video out fixes (flipping between two frames)
From: Frank Oltmanns @ 2024-04-03 15:31 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Maxime Ripard
Cc: Guido Günther, Purism Kernel Team, Ondrej Jirman,
Neil Armstrong, Jessica Zhang, Sam Ravnborg, Maarten Lankhorst,
Thomas Zimmermann, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-clk, linux-arm-kernel,
linux-sunxi, linux-kernel, dri-devel, devicetree, stable,
Diego Roversi, Erico Nunes
In-Reply-To: <20240310-pinephone-pll-fixes-v4-0-46fc80c83637@oltmanns.dev>
Dear clk and sunxi-ng maintainers,
Patches 1-4 have been reviewed and there are no pending issues. If there
is something else you need me to do to get this applied, please let me
know.
Thanks,
Frank
On 2024-03-10 at 14:21:10 +0100, Frank Oltmanns <frank@oltmanns.dev> wrote:
> On some pinephones the video output sometimes freezes (flips between two
> frames) [1]. It seems to be that the reason for this behaviour is that
> PLL-MIPI is outside its limits, and the GPU is not running at a fixed
> rate.
>
> In this patch series I propose the following changes:
> 1. sunxi-ng: Adhere to the following constraints given in the
> Allwinner A64 Manual regarding PLL-MIPI:
> * M/N <= 3
> * (PLL_VIDEO0)/M >= 24MHz
> * 500MHz <= clockrate <= 1400MHz
>
> 2. Remove two operating points from the A64 DTS OPPs, so that the GPU
> runs at a fixed rate of 432 MHz.
>
> Note, that when pinning the GPU to 432 MHz the issue [1] completely
> disappears for me. I've searched the BSP and could not find any
> indication that supports the idea of having the three OPPs. The only
> frequency I found in the BPSs for A64 is 432 MHz, which has also proven
> stable for me.
>
> I very much appreciate your feedback!
>
> [1] https://gitlab.com/postmarketOS/pmaports/-/issues/805
>
> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
> ---
> Changes in v4:
> - sunxi-ng: common: Address review comments.
> - Link to v3: https://lore.kernel.org/r/20240304-pinephone-pll-fixes-v3-0-94ab828f269a@oltmanns.dev
>
> Changes in v3:
> - dts: Pin GPU to 432 MHz.
> - nkm and a64: Move minimum and maximum rate handling to the common part
> of the sunxi-ng driver.
> - Removed st7703 patch from series.
> - Link to v2: https://lore.kernel.org/r/20240205-pinephone-pll-fixes-v2-0-96a46a2d8c9b@oltmanns.dev
>
> Changes in v2:
> - dts: Increase minimum GPU frequency to 192 MHz.
> - nkm and a64: Add minimum and maximum rate for PLL-MIPI.
> - nkm: Use the same approach for skipping invalid rates in
> ccu_nkm_find_best() as in ccu_nkm_find_best_with_parent_adj().
> - nkm: Improve names for ratio struct members and hence get rid of
> describing comments.
> - nkm and a64: Correct description in the commit messages: M/N <= 3
> - Remove patches for nm as they were not needed.
> - st7703: Rework the commit message to cover more background for the
> change.
> - Link to v1: https://lore.kernel.org/r/20231218-pinephone-pll-fixes-v1-0-e238b6ed6dc1@oltmanns.dev
>
> ---
> Frank Oltmanns (5):
> clk: sunxi-ng: common: Support minimum and maximum rate
> clk: sunxi-ng: a64: Set minimum and maximum rate for PLL-MIPI
> clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rate
> clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate
> arm64: dts: allwinner: a64: Run GPU at 432 MHz
>
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 --------
> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 14 +++++++++-----
> drivers/clk/sunxi-ng/ccu_common.c | 19 +++++++++++++++++++
> drivers/clk/sunxi-ng/ccu_common.h | 3 +++
> drivers/clk/sunxi-ng/ccu_nkm.c | 21 +++++++++++++++++++++
> drivers/clk/sunxi-ng/ccu_nkm.h | 2 ++
> 6 files changed, 54 insertions(+), 13 deletions(-)
> ---
> base-commit: dcb6c8ee6acc6c347caec1e73fb900c0f4ff9806
> change-id: 20231218-pinephone-pll-fixes-0ccdfde273e4
>
> Best regards,
^ permalink raw reply
* Re: [PATCH 1/6] dt-bindings: adc: ad7173: add support for ad411x
From: David Lechner @ 2024-04-03 15:40 UTC (permalink / raw)
To: Ceclan, Dumitru
Cc: dumitru.ceclan, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-iio, devicetree, linux-kernel
In-Reply-To: <25cb3514-1281-49a8-9e9b-40ead9b050dc@gmail.com>
On Wed, Apr 3, 2024 at 2:43 AM Ceclan, Dumitru <mitrutzceclan@gmail.com> wrote:
>
> On 01/04/2024 22:37, David Lechner wrote:
> > On Mon, Apr 1, 2024 at 10:10 AM Dumitru Ceclan via B4 Relay
> > <devnull+dumitru.ceclan.analog.com@kernel.org> wrote:
> >>
> >> From: Dumitru Ceclan <dumitru.ceclan@analog.com>
>
> ...
>
> >> properties:
> >> reg:
> >> + description:
> >> + Reg values 16-19 are only permitted for ad4111/ad4112 current channels.
> >> minimum: 0
> >> - maximum: 15
> >> + maximum: 19
> >
> > This looks wrong. Isn't reg describing the number of logical channels
> > (# of channel config registers)?
> >
> > After reviewing the driver, I see that > 16 is used as a way of
> > flagging current inputs, but still seems like the wrong way to do it.
> > See suggestion below.
> >
>
> This was a suggestion from Jonathan, maybe I implemented it wrong.
> Other alternative that came to my mind: attribute "adi,current-channel".
Having a boolean flag like this would make more sense to me if we
don't agree that the suggestion below is simpler.
> >>
> >> diff-channels:
> >> + description:
> >> + For using current channels specify only the positive channel.
> >> + (IIN2+, IIN2−) -> diff-channels = <2 0>
> >
> > I find this a bit confusing since 2 is already VIN2 and 0 is already
> > VIN0. I think it would make more sense to assign unique channel
> > numbers individually to the negative and positive current inputs.
> > Also, I think it makes sense to use the same numbers that the
> > registers in the datasheet use (8 - 11 for negative and 12 to 15 for
> > positive).
> >
> > So: (IIN2+, IIN2−) -> diff-channels = <13 10>
> >
> >
> It would mean for the user to look in the datasheet at the possible
> channel INPUT configurations values, decode the bit field into two
> integer values and place it here (0110101010) -> 13 10. This is
> cumbersome for just choosing current input 2.
It could be documented in the devicetree bindings, just as it is done
in adi,ad4130.yaml so that users of the bindings don't have to
decipher the datasheet.
>
> >> +
> >> + Family AD411x supports a dedicated VCOM voltage input.
> >> + To select it set the second channel to 16.
> >> + (VIN2, VCOM) -> diff-channels = <2 16>
> >
> > The 411x datasheets call this pin VINCOM so calling it VCOM here is a
> > bit confusing.
> >
>
> Sure, I'll rename to VINCOM.
>
> > Also, do we need to add a vincom-supply to get this voltage? Or is it
> > safe to assume it is always connected to AVSS? The datasheet seems to
> > indicate that the latter is the case. But then it also has this
> > special case (at least for AD4116, didn't check all datasheets)
> > "VIN10, VINCOM (single-ended or differential pair)". If it can be used
> > as part of a fully differential input, we probably need some extra
> > flag to indicate that case.
> >
>
> I cannot see any configuration options for these use cases. All inputs
> are routed to the same mux and routed to the differential positive and
> negative ADC inputs.
>
> "VIN10, VINCOM (single-ended or differential pair)" the only difference
> between these two use cases is if you connected VINCOM to AVSS (with
> unipolar coding) or not with bipolar encoding. The channel is still
> measuring the difference between the two selected inputs and comparing
> to the selected reference.
>
> > Similarly, do we need special handling for ADCIN15 on AD4116? It has a
> > "(pseudo differential or differential pair)" notation that other
> > inputs don't. In other words, it is more like VINCOM than it is to the
> > other ADCINxx pins. So we probably need an adcin15-supply for this pin
> > to properly get the right channel configuration. I.e. the logic in the
> > IIO driver would be if adcin15-supply is present, any channels that
> > use this input are pseudo-differential, otherwise any channels that
> > use it are fully differential.
> >
>
> I cannot seem to understand what would a adcin15-supply be needed for.
> This input, the same as all others, enters the mux and is routed to
> either positive or negative input of the ADC.
>
> The voltage on the ADCIN15 pin is not important to the user, just the
> difference in voltage between that pin and the other one selected.
>
These suggestions come from some recent discussion about
pseudo-differential vs. fully differential inputs (e.g. search the IIO
mailing list for AD7380).
So what I suggested here might be more technically correct according
to what I got out of that discussion. But for this specific case, I
agree it is good enough to just treat all inputs as always
fully-differential to keep things from getting too unwieldy.
> >> items:
> >> minimum: 0
> >> maximum: 31
> >> @@ -166,7 +191,6 @@ allOf:
> >> - $ref: /schemas/spi/spi-peripheral-props.yaml#
> >>
> >> # Only ad7172-4, ad7173-8 and ad7175-8 support vref2
> >> - # Other models have [0-3] channel registers
> >
> > Did you forget to remove
> >
> > reg:
> > maximum: 3
> >
> > from this if statement that this comment is referring to?
> >
> >
>
>
> Other way around, forgot in a previous patch to remove the comment.
> I'll move this change to a precursor patch.
>
> >> - if:
> >> properties:
> >> compatible:
> >> @@ -187,6 +211,37 @@ allOf:
> >> - vref
> >> - refout-avss
> >> - avdd
> >> +
> >> + - if:
> >> + properties:
> >> + compatible:
> >> + contains:
> >> + enum:
> >> + - adi,ad4114
> >> + - adi,ad4115
> >> + - adi,ad4116
> >> + - adi,ad7173-8
> >> + - adi,ad7175-8
> >> + then:
> >> + patternProperties:
> >> + "^channel@[0-9a-f]$":
> >> + properties:
> >> + reg:
> >> + maximum: 15
> >
> > As with the previous reg comment, this if statement should not be
> > needed since maximum should not be changed to 19.
> >
>
> We'll see what is the best approach regarding the current channels,
> perhaps the one you mentioned in the later reply with always configuring
> like the temp channel.
>
> >> +
> >> + - if:
> >> + properties:
> >> + compatible:
> >> + contains:
> >> + enum:
> >> + - adi,ad7172-2
> >> + - adi,ad7175-2
> >> + - adi,ad7176-2
> >> + - adi,ad7177-2
> >> + then:
> >> + patternProperties:
> >> + "^channel@[0-9a-f]$":
> >> + properties:
> >> reg:
> >> maximum: 3
> >
> > It looks to me like AD7172-4 actually has 8 possible channels rather
> > than 16. So it would need a special condition as well. But that is a
> > bug in the previous bindings and should therefore be fixed in a
> > separate patch.
>
> It is addressed already in the binding:
> "
> - if:
> properties:
> compatible:
> contains:
> const: adi,ad7172-4
> [...]
> maximum: 7
> "
Ah, I missed it hiding with adi,reference-select overrides.
^ permalink raw reply
* Re: [PATCH v5 02/10] dt-bindings: mailbox: Add mboxes property for CMDQ secure driver
From: Conor Dooley @ 2024-04-03 15:46 UTC (permalink / raw)
To: Shawn Sung
Cc: CK Hu, Jassi Brar, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Jason-JH . Lin, Houlong Wei, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek
In-Reply-To: <20240403102602.32155-3-shawn.sung@mediatek.com>
[-- Attachment #1: Type: text/plain, Size: 1430 bytes --]
On Wed, Apr 03, 2024 at 06:25:54PM +0800, Shawn Sung wrote:
> From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
>
> Add mboxes to define a GCE loopping thread as a secure irq handler.
> This property is only required if CMDQ secure driver is supported.
>
> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> .../bindings/mailbox/mediatek,gce-mailbox.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
> index cef9d76013985..c0d80cc770899 100644
> --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
> @@ -49,6 +49,16 @@ properties:
> items:
> - const: gce
>
> + mediatek,gce-events:
> + description:
> + The event id which is mapping to the specific hardware event signal
> + to gce. The event id is defined in the gce header
> + include/dt-bindings/gce/<chip>-gce.h of each chips.
Missing any info here about when this should be used, hint - you have it
in the commit message.
> + $ref: /schemas/types.yaml#/definitions/uint32-arrayi
Why is the ID used by the CMDQ service not fixed for each SoC?
Cheers,
Conor
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v6 2/6] interconnect: icc-clk: Remove tristate from INTERCONNECT_CLK
From: kernel test robot @ 2024-04-03 15:42 UTC (permalink / raw)
To: Varadarajan Narayanan, andersson, konrad.dybcio, mturquette,
sboyd, robh, krzysztof.kozlowski+dt, conor+dt, djakov,
dmitry.baryshkov, quic_anusha, linux-arm-msm, linux-clk,
devicetree, linux-kernel, linux-pm
Cc: oe-kbuild-all, kernel test robot
In-Reply-To: <20240402103406.3638821-3-quic_varada@quicinc.com>
Hi Varadarajan,
kernel test robot noticed the following build errors:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on robh/for-next linus/master v6.9-rc2 next-20240403]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Varadarajan-Narayanan/dt-bindings-interconnect-Add-Qualcomm-IPQ9574-support/20240402-223729
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link: https://lore.kernel.org/r/20240402103406.3638821-3-quic_varada%40quicinc.com
patch subject: [PATCH v6 2/6] interconnect: icc-clk: Remove tristate from INTERCONNECT_CLK
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20240403/202404032328.7zrla6d9-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240403/202404032328.7zrla6d9-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202404032328.7zrla6d9-lkp@intel.com/
All errors (new ones prefixed by >>):
aarch64-linux-ld: Unexpected GOT/PLT entries detected!
aarch64-linux-ld: Unexpected run-time procedure linkages detected!
aarch64-linux-ld: drivers/clk/qcom/clk-cbf-8996.o: in function `qcom_msm8996_cbf_icc_remove':
>> drivers/clk/qcom/clk-cbf-8996.c:257:(.text+0x10): undefined reference to `icc_clk_unregister'
aarch64-linux-ld: drivers/clk/qcom/clk-cbf-8996.o: in function `qcom_msm8996_cbf_icc_register':
>> drivers/clk/qcom/clk-cbf-8996.c:244:(.text+0x360): undefined reference to `icc_clk_register'
vim +257 drivers/clk/qcom/clk-cbf-8996.c
12dc71953e664f Dmitry Baryshkov 2023-05-12 234
12dc71953e664f Dmitry Baryshkov 2023-05-12 235 static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct clk_hw *cbf_hw)
12dc71953e664f Dmitry Baryshkov 2023-05-12 236 {
12dc71953e664f Dmitry Baryshkov 2023-05-12 237 struct device *dev = &pdev->dev;
12dc71953e664f Dmitry Baryshkov 2023-05-12 238 struct clk *clk = devm_clk_hw_get_clk(dev, cbf_hw, "cbf");
12dc71953e664f Dmitry Baryshkov 2023-05-12 239 const struct icc_clk_data data[] = {
12dc71953e664f Dmitry Baryshkov 2023-05-12 240 { .clk = clk, .name = "cbf", },
12dc71953e664f Dmitry Baryshkov 2023-05-12 241 };
12dc71953e664f Dmitry Baryshkov 2023-05-12 242 struct icc_provider *provider;
12dc71953e664f Dmitry Baryshkov 2023-05-12 243
12dc71953e664f Dmitry Baryshkov 2023-05-12 @244 provider = icc_clk_register(dev, CBF_MASTER_NODE, ARRAY_SIZE(data), data);
12dc71953e664f Dmitry Baryshkov 2023-05-12 245 if (IS_ERR(provider))
12dc71953e664f Dmitry Baryshkov 2023-05-12 246 return PTR_ERR(provider);
12dc71953e664f Dmitry Baryshkov 2023-05-12 247
12dc71953e664f Dmitry Baryshkov 2023-05-12 248 platform_set_drvdata(pdev, provider);
12dc71953e664f Dmitry Baryshkov 2023-05-12 249
12dc71953e664f Dmitry Baryshkov 2023-05-12 250 return 0;
12dc71953e664f Dmitry Baryshkov 2023-05-12 251 }
12dc71953e664f Dmitry Baryshkov 2023-05-12 252
abaf59c470a7c9 Uwe Kleine-König 2023-09-11 253 static void qcom_msm8996_cbf_icc_remove(struct platform_device *pdev)
12dc71953e664f Dmitry Baryshkov 2023-05-12 254 {
12dc71953e664f Dmitry Baryshkov 2023-05-12 255 struct icc_provider *provider = platform_get_drvdata(pdev);
12dc71953e664f Dmitry Baryshkov 2023-05-12 256
12dc71953e664f Dmitry Baryshkov 2023-05-12 @257 icc_clk_unregister(provider);
12dc71953e664f Dmitry Baryshkov 2023-05-12 258 }
12dc71953e664f Dmitry Baryshkov 2023-05-12 259 #define qcom_msm8996_cbf_icc_sync_state icc_sync_state
12dc71953e664f Dmitry Baryshkov 2023-05-12 260 #else
12dc71953e664f Dmitry Baryshkov 2023-05-12 261 static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct clk_hw *cbf_hw)
12dc71953e664f Dmitry Baryshkov 2023-05-12 262 {
12dc71953e664f Dmitry Baryshkov 2023-05-12 263 dev_warn(&pdev->dev, "CONFIG_INTERCONNECT is disabled, CBF clock is fixed\n");
12dc71953e664f Dmitry Baryshkov 2023-05-12 264
12dc71953e664f Dmitry Baryshkov 2023-05-12 265 return 0;
12dc71953e664f Dmitry Baryshkov 2023-05-12 266 }
abaf59c470a7c9 Uwe Kleine-König 2023-09-11 267 #define qcom_msm8996_cbf_icc_remove(pdev) { }
12dc71953e664f Dmitry Baryshkov 2023-05-12 268 #define qcom_msm8996_cbf_icc_sync_state NULL
12dc71953e664f Dmitry Baryshkov 2023-05-12 269 #endif
12dc71953e664f Dmitry Baryshkov 2023-05-12 270
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v6 1/1] dt-bindings: net: starfive,jh7110-dwmac: Add StarFive JH8100 support
From: Conor Dooley @ 2024-04-03 15:49 UTC (permalink / raw)
To: Tan Chun Hau
Cc: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Simon Horman, Bartosz Golaszewski,
Andrew Halaney, Jisheng Zhang, Uwe Kleine-König,
Russell King, Ley Foon Tan, Jee Heng Sia, netdev, devicetree,
linux-kernel, linux-stm32, linux-arm-kernel, linux-riscv
In-Reply-To: <20240403100549.78719-2-chunhau.tan@starfivetech.com>
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On Wed, Apr 03, 2024 at 03:05:49AM -0700, Tan Chun Hau wrote:
> Add StarFive JH8100 dwmac support.
> The JH8100 dwmac shares the same driver code as the JH7110 dwmac
> and has only one reset signal.
>
> Please refer to below:
>
> JH8100: reset-names = "stmmaceth";
> JH7110: reset-names = "stmmaceth", "ahb";
> JH7100: reset-names = "ahb";
>
> Example usage of JH8100 in the device tree:
>
> gmac0: ethernet@16030000 {
> compatible = "starfive,jh8100-dwmac",
> "starfive,jh7110-dwmac",
> "snps,dwmac-5.20";
> ...
> };
>
> Signed-off-by: Tan Chun Hau <chunhau.tan@starfivetech.com>
How come you didn't pick up Rob's r-b?
https://lore.kernel.org/all/20240328204202.GA308290-robh@kernel.org/
Thanks,
Conor.
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^ permalink raw reply
* Re: [PATCH v14 01/18] irqchip/sifive-plic: Convert PLIC driver into a platform driver
From: Lad, Prabhakar @ 2024-04-03 15:49 UTC (permalink / raw)
To: Anup Patel
Cc: Geert Uytterhoeven, Palmer Dabbelt, Paul Walmsley,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Frank Rowand,
Conor Dooley, Marc Zyngier, Björn Töpel, Atish Patra,
Andrew Jones, Sunil V L, Saravana Kannan, Anup Patel, linux-riscv,
linux-arm-kernel, linux-kernel, devicetree
In-Reply-To: <CAK9=C2VgiRcQjBEPmZjdcMf221omKS8ntdcenSE7G__4xYcCUA@mail.gmail.com>
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On Wed, Apr 3, 2024 at 3:17 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> On Wed, Apr 3, 2024 at 2:01 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> >
> > Hi Anup,
> >
> > On Thu, Feb 22, 2024 at 9:41 AM Anup Patel <apatel@ventanamicro.com> wrote:
> > >
> > > The PLIC driver does not require very early initialization so convert
> > > it into a platform driver.
> > >
> > > After conversion, the PLIC driver is probed after CPUs are brought-up
> > > so setup cpuhp state after context handler of all online CPUs are
> > > initialized otherwise PLIC driver crashes for platforms with multiple
> > > PLIC instances.
> > >
> > > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > > ---
> > > drivers/irqchip/irq-sifive-plic.c | 101 ++++++++++++++++++------------
> > > 1 file changed, 61 insertions(+), 40 deletions(-)
> > >
> > This patch seems to have broken things on RZ/Five SoC, after reverting
> > this patch I get to boot it back again on v6.9-rc2. Looks like there
> > is some probe order issue after switching to platform driver?
>
> Yes, this is most likely related to probe ordering based on your DT.
>
> Can you share the failing boot log and DT ?
non working case, https://paste.debian.net/1312947/
after reverting, https://paste.debian.net/1312948/
(attached is the DTB)
Cheers,
Prabhakar
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^ permalink raw reply
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