* [PATCH 06/17] arm64: dts: exynos: gs101: Add the hsi2 sysreg node
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
This has some configuration bits such as sharability that
are required by UFS.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 38ac4fb1397e..608369cec47b 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 {
clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
};
+ sysreg_hsi2: syscon@14420000 {
+ compatible = "google,gs101-hsi2-sysreg", "syscon";
+ reg = <0x14420000 0x1000>;
+ clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
+ };
+
pinctrl_hsi2: pinctrl@14440000 {
compatible = "google,gs101-pinctrl";
reg = <0x14440000 0x00001000>;
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* [PATCH 07/17] arm64: dts: exynos: gs101: Add ufs, ufs-phy and ufs regulator dt nodes
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
Enable the ufs controller, ufs phy and ufs regulator in device tree.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
.../boot/dts/exynos/google/gs101-oriole.dts | 17 +++++++++
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 35 +++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
index 6be15e990b65..986eb5c9898a 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
+++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
@@ -53,6 +53,14 @@ button-power {
wakeup-source;
};
};
+
+ ufs_0_fixed_vcc_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "ufs-vcc";
+ gpio = <&gpp0 1 0>;
+ regulator-boot-on;
+ enable-active-high;
+ };
};
&ext_24_5m {
@@ -106,6 +114,15 @@ &serial_0 {
status = "okay";
};
+&ufs_0 {
+ status = "okay";
+ vcc-supply = <&ufs_0_fixed_vcc_reg>;
+};
+
+&ufs_0_phy {
+ status = "okay";
+};
+
&usi_uart {
samsung,clkreq-on; /* needed for UART mode */
status = "okay";
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 608369cec47b..9c94829bf14c 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1277,6 +1277,41 @@ pinctrl_hsi2: pinctrl@14440000 {
interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ ufs_0_phy: phy@17e04000 {
+ compatible = "google,gs101-ufs-phy";
+ reg = <0x14704000 0x3000>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ clocks = <&ext_24_5m>;
+ clock-names = "ref_clk";
+ status = "disabled";
+ };
+
+ ufs_0: ufs@14700000 {
+ compatible = "google,gs101-ufs";
+
+ reg = <0x14700000 0x200>,
+ <0x14701100 0x200>,
+ <0x14780000 0xa000>,
+ <0x14600000 0x100>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>;
+ clock-names = "core_clk", "sclk_unipro_main", "fmp", "ufs_aclk", "ufs_pclk";
+ freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+ phys = <&ufs_0_phy>;
+ phy-names = "ufs-phy";
+ samsung,sysreg = <&sysreg_hsi2 0x710>;
+ status = "disabled";
+ };
+
cmu_apm: clock-controller@17400000 {
compatible = "google,gs101-cmu-apm";
reg = <0x17400000 0x8000>;
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
CMU_HSI2 is the clock management unit used for the hsi2 block.
HSI stands for High Speed Interface and as such it generates
clocks for PCIe, UFS and MMC card.
This patch adds support for the muxes, dividers, and gates in
cmu_hsi2.
CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK is marked as CLK_IS_CRITICAL
as disabling it leads to an immediate system hang.
CLK_GOUT_HSI2_SYSREG_HSI2_PCLK is also marked CLK_IS_CRITICAL.
A hang is not observed with fine grained clock control, but
UFS IP does not function with syscon controlling this clock
just around hsi2_sysreg register accesses.
CLK_GOUT_HSI2_GPIO_HSI2_PCLK is marked CLK_IGNORE_UNUSED until
the exynos pinctrl clock patches land then it can be removed.
Some clocks in this unit have very long names. To help with this
the clock name mangling strategy was updated to include removing
the following sub-strings.
- G4X2_DWC_PCIE_CTL_
- G4X1_DWC_PCIE_CTL_
- PCIE_SUB_CTRL_
- INST_0_
- LN05LPE_
- TM_WRAPPER_
- SF_
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
Updated regex for clock name mangling
sed \
-e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|fout_\L\1_pll|' \
\
-e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_\(.*\)|mout_\L\1_\2|' \
-e 's|^PLL_CON0_PLL_\(.*\)|mout_pll_\L\1|' \
-e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|mout_\L\1|' \
-e '/^PLL_CON[1-4]_[^_]\+_/d' \
-e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
-e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
\
-e 's|_IPCLKPORT||' \
-e 's|_RSTNSYNC||' \
-e 's|_G4X2_DWC_PCIE_CTL||' \
-e 's|_G4X1_DWC_PCIE_CTL||' \
-e 's|_PCIE_SUB_CTRL||' \
-e 's|_INST_0||g' \
-e 's|_LN05LPE||' \
-e 's|_TM_WRAPPER||' \
-e 's|_SF||' \
\
-e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_\(.*\)|dout_\L\1_\2|' \
\
-e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_\(.*\)|gout_\L\1_\2|' \
-e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
-e 's|^gout_[^_]\+_[^_]\+_cmu_\([^_]\+\)_pclk$|gout_\1_\1_pclk|' \
-e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
-e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|gout_\L\1_clk_\L\1_\2|' \
\
-e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d'
---
drivers/clk/samsung/clk-gs101.c | 558 +++++++++++++++++++++++
include/dt-bindings/clock/google,gs101.h | 63 +++
2 files changed, 621 insertions(+)
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index d065e343a85d..b9f84c7d5c22 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -22,6 +22,7 @@
#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
+#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
/* ---- CMU_TOP ------------------------------------------------------------- */
@@ -3409,6 +3410,560 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
.clk_name = "bus",
};
+/* ---- CMU_HSI2 ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_HSI2 (0x14400000) */
+#define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600
+#define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604
+#define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610
+#define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614
+#define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620
+#define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624
+#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630
+#define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634
+#define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800
+#define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK 0x2068
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK 0x206c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK 0x2070
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK 0x2074
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK 0x2078
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK 0x207c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK 0x2080
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK 0x2084
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK 0x2088
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK 0x208c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK 0x2090
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK 0x2094
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK 0x2098
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK 0x209c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK 0x20a0
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK 0x20a4
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2 0x20a8
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK 0x20ac
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK 0x20b0
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK 0x20b4
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK 0x20b8
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK 0x20bc
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK 0x20c0
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK 0x20c4
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK 0x20c8
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK 0x20cc
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x20d0
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x20d4
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x20d8
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK 0x20dc
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK 0x20e0
+#define DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1 0x3000
+#define PCH_CON_LHM_AXI_P_HSI2_PCH 0x3008
+#define PCH_CON_LHS_ACEL_D_HSI2_PCH 0x300c
+#define QCH_CON_D_TZPC_HSI2_QCH 0x3010
+#define QCH_CON_GPC_HSI2_QCH 0x3014
+#define QCH_CON_GPIO_HSI2_QCH 0x3018
+#define QCH_CON_HSI2_CMU_HSI2_QCH 0x301c
+#define QCH_CON_LHM_AXI_P_HSI2_QCH 0x3020
+#define QCH_CON_LHS_ACEL_D_HSI2_QCH 0x3024
+#define QCH_CON_MMC_CARD_QCH 0x3028
+#define QCH_CON_PCIE_GEN4_1_QCH_APB_1 0x302c
+#define QCH_CON_PCIE_GEN4_1_QCH_APB_2 0x3030
+#define QCH_CON_PCIE_GEN4_1_QCH_AXI_1 0x3034
+#define QCH_CON_PCIE_GEN4_1_QCH_AXI_2 0x3038
+#define QCH_CON_PCIE_GEN4_1_QCH_DBG_1 0x303c
+#define QCH_CON_PCIE_GEN4_1_QCH_DBG_2 0x3040
+#define QCH_CON_PCIE_GEN4_1_QCH_PCS_APB 0x3044
+#define QCH_CON_PCIE_GEN4_1_QCH_PMA_APB 0x3048
+#define QCH_CON_PCIE_GEN4_1_QCH_UDBG 0x304c
+#define QCH_CON_PCIE_IA_GEN4A_1_QCH 0x3050
+#define QCH_CON_PCIE_IA_GEN4B_1_QCH 0x3054
+#define QCH_CON_PPMU_HSI2_QCH 0x3058
+#define QCH_CON_QE_MMC_CARD_HSI2_QCH 0x305c
+#define QCH_CON_QE_PCIE_GEN4A_HSI2_QCH 0x3060
+#define QCH_CON_QE_PCIE_GEN4B_HSI2_QCH 0x3064
+#define QCH_CON_QE_UFS_EMBD_HSI2_QCH 0x3068
+#define QCH_CON_SSMT_HSI2_QCH 0x306c
+#define QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH 0x3070
+#define QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH 0x3074
+#define QCH_CON_SYSMMU_HSI2_QCH 0x3078
+#define QCH_CON_SYSREG_HSI2_QCH 0x307c
+#define QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH 0x3080
+#define QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH 0x3084
+#define QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH 0x3088
+#define QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH 0x308c
+#define QCH_CON_UFS_EMBD_QCH 0x3090
+#define QCH_CON_UFS_EMBD_QCH_FMP 0x3094
+#define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00
+
+static const unsigned long cmu_hsi2_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER,
+ PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
+ PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER,
+ PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
+ PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER,
+ PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
+ PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
+ HSI2_CMU_HSI2_CONTROLLER_OPTION,
+ CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
+ DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1,
+ PCH_CON_LHM_AXI_P_HSI2_PCH,
+ PCH_CON_LHS_ACEL_D_HSI2_PCH,
+ QCH_CON_D_TZPC_HSI2_QCH,
+ QCH_CON_GPC_HSI2_QCH,
+ QCH_CON_GPIO_HSI2_QCH,
+ QCH_CON_HSI2_CMU_HSI2_QCH,
+ QCH_CON_LHM_AXI_P_HSI2_QCH,
+ QCH_CON_LHS_ACEL_D_HSI2_QCH,
+ QCH_CON_MMC_CARD_QCH,
+ QCH_CON_PCIE_GEN4_1_QCH_APB_1,
+ QCH_CON_PCIE_GEN4_1_QCH_APB_2,
+ QCH_CON_PCIE_GEN4_1_QCH_AXI_1,
+ QCH_CON_PCIE_GEN4_1_QCH_AXI_2,
+ QCH_CON_PCIE_GEN4_1_QCH_DBG_1,
+ QCH_CON_PCIE_GEN4_1_QCH_DBG_2,
+ QCH_CON_PCIE_GEN4_1_QCH_PCS_APB,
+ QCH_CON_PCIE_GEN4_1_QCH_PMA_APB,
+ QCH_CON_PCIE_GEN4_1_QCH_UDBG,
+ QCH_CON_PCIE_IA_GEN4A_1_QCH,
+ QCH_CON_PCIE_IA_GEN4B_1_QCH,
+ QCH_CON_PPMU_HSI2_QCH,
+ QCH_CON_QE_MMC_CARD_HSI2_QCH,
+ QCH_CON_QE_PCIE_GEN4A_HSI2_QCH,
+ QCH_CON_QE_PCIE_GEN4B_HSI2_QCH,
+ QCH_CON_QE_UFS_EMBD_HSI2_QCH,
+ QCH_CON_SSMT_HSI2_QCH,
+ QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH,
+ QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH,
+ QCH_CON_SYSMMU_HSI2_QCH,
+ QCH_CON_SYSREG_HSI2_QCH,
+ QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH,
+ QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH,
+ QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH,
+ QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH,
+ QCH_CON_UFS_EMBD_QCH,
+ QCH_CON_UFS_EMBD_QCH_FMP,
+ QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2,
+};
+
+PNAME(mout_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4",
+ "dout_cmu_shared2_div2", "fout_spare_pll" };
+
+PNAME(mout_hsi2_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" };
+
+PNAME(mout_hsi2_bus_p) = { "dout_cmu_shared0_div4",
+ "dout_cmu_shared1_div4",
+ "dout_cmu_shared2_div2",
+ "dout_cmu_shared3_div2",
+ "fout_spare_pll", "oscclk", "oscclk",
+ "oscclk" };
+
+PNAME(mout_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
+ "dout_cmu_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_hsi2_bus_user_p) = { "oscclk", "dout_cmu_hsi2_bus" };
+PNAME(mout_hsi2_pcie_user_p) = { "oscclk", "dout_cmu_hsi2_pcie" };
+PNAME(mout_hsi2_ufs_embd_user_p) = { "oscclk", "dout_cmu_hsi2_ufs_embd" };
+PNAME(mout_hsi2_mmc_card_user_p) = { "oscclk", "dout_cmu_hsi2_mmc_card" };
+
+static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_HSI2_BUS_USER, "mout_hsi2_bus_user", mout_hsi2_bus_user_p,
+ PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_HSI2_MMC_CARD_USER, "mout_hsi2_mmc_card_user",
+ mout_hsi2_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
+ 4, 1),
+ MUX(CLK_MOUT_HSI2_PCIE_USER, "mout_hsi2_pcie_user",
+ mout_hsi2_pcie_user_p, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
+ 4, 1),
+ MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_hsi2_ufs_embd_user",
+ mout_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
+ 4, 1),
+};
+
+static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN,
+ "gout_hsi2_pcie_gen4_1_pcie_003_phy_refclk_in",
+ "mout_hsi2_pcie_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN,
+ "gout_hsi2_pcie_gen4_1_pcie_004_phy_refclk_in",
+ "mout_hsi2_pcie_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK,
+ "gout_hsi2_ssmt_pcie_ia_gen4a_1_aclk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK,
+ "gout_hsi2_ssmt_pcie_ia_gen4a_1_pclk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK,
+ "gout_hsi2_ssmt_pcie_ia_gen4b_1_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK,
+ "gout_hsi2_ssmt_pcie_ia_gen4b_1_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK,
+ "gout_hsi2_d_tzpc_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_GPC_HSI2_PCLK,
+ "gout_hsi2_gpc_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_GPIO_HSI2_PCLK,
+ "gout_hsi2_gpio_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+
+ /* Disabling this clock makes the system hang. Mark the clock as critical. */
+ GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK,
+ "gout_hsi2_hsi2_cmu_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
+ 21, CLK_IS_CRITICAL, 0),
+
+ GATE(CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK,
+ "gout_hsi2_lhm_axi_p_hsi2_i_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK,
+ "gout_hsi2_lhs_acel_d_hsi2_i_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_MMC_CARD_I_ACLK,
+ "gout_hsi2_mmc_card_i_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_MMC_CARD_SDCLKIN,
+ "gout_hsi2_mmc_card_sdclkin", "mout_hsi2_mmc_card_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_003_dbi_aclk_ug", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_003_mstr_aclk_ug",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_003_slv_aclk_ug", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK,
+ "gout_hsi2_pcie_gen4_1_pcie_003_i_driver_apb_clk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_004_dbi_aclk_ug", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_004_mstr_aclk_ug",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_004_slv_aclk_ug", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK,
+ "gout_hsi2_pcie_gen4_1_pcie_004_i_driver_apb_clk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK,
+ "gout_hsi2_pcie_gen4_1_pcs_pma_phy_udbg_i_apb_pclk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK,
+ "gout_hsi2_pcie_gen4_1_pcs_pma_pipe_pal_pcie_i_apb_pclk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK,
+ "gout_hsi2_pcie_gen4_1_pcs_pma_pciephy210x2_qch_i_apb_pclk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK,
+ "gout_hsi2_pcie_ia_gen4a_1_i_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK,
+ "gout_hsi2_pcie_ia_gen4b_1_i_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PPMU_HSI2_ACLK,
+ "gout_hsi2_ppmu_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PPMU_HSI2_PCLK,
+ "gout_hsi2_ppmu_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK,
+ "gout_hsi2_qe_mmc_card_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK,
+ "gout_hsi2_qe_mmc_card_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK,
+ "gout_hsi2_qe_pcie_gen4a_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK,
+ "gout_hsi2_qe_pcie_gen4a_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK,
+ "gout_hsi2_qe_pcie_gen4b_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK,
+ "gout_hsi2_qe_pcie_gen4b_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK,
+ "gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK,
+ "gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK,
+ "gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK,
+ "gout_hsi2_clk_hsi2_oscclk_clk", "oscclk",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_HSI2_ACLK,
+ "gout_hsi2_ssmt_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_HSI2_PCLK,
+ "gout_hsi2_ssmt_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2,
+ "gout_hsi2_sysmmu_hsi2_clk_s2", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK,
+ "gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
+ 21, CLK_IS_CRITICAL, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK,
+ "gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK,
+ "gout_hsi2_uasc_pcie_gen4a_dbi_1_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK,
+ "gout_hsi2_uasc_pcie_gen4a_slv_1_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK,
+ "gout_hsi2_uasc_pcie_gen4a_slv_1_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK,
+ "gout_hsi2_uasc_pcie_gen4b_dbi_1_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK,
+ "gout_hsi2_uasc_pcie_gen4b_dbi_1_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK,
+ "gout_hsi2_uasc_pcie_gen4b_slv_1_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK,
+ "gout_hsi2_uasc_pcie_gen4b_slv_1_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK,
+ "gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO,
+ "gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK,
+ "gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK,
+ "gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK,
+ "gout_hsi2_xiu_p_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+};
+
+static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
+ .mux_clks = hsi2_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks),
+ .gate_clks = hsi2_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(hsi2_gate_clks),
+ .nr_clk_ids = CLKS_NR_HSI2,
+ .clk_regs = cmu_hsi2_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_hsi2_clk_regs),
+ .clk_name = "bus",
+};
+
/* ---- platform_driver ----------------------------------------------------- */
static int __init gs101_cmu_probe(struct platform_device *pdev)
@@ -3432,6 +3987,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
}, {
.compatible = "google,gs101-cmu-peric1",
.data = &peric1_cmu_info,
+ }, {
+ .compatible = "google,gs101-cmu-hsi2",
+ .data = &hsi2_cmu_info,
}, {
},
};
diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
index 3dac3577788a..ac239ce6821b 100644
--- a/include/dt-bindings/clock/google,gs101.h
+++ b/include/dt-bindings/clock/google,gs101.h
@@ -518,4 +518,67 @@
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
+/* CMU_HSI2 */
+
+#define CLK_MOUT_HSI2_BUS_USER 1
+#define CLK_MOUT_HSI2_MMC_CARD_USER 2
+#define CLK_MOUT_HSI2_PCIE_USER 3
+#define CLK_MOUT_HSI2_UFS_EMBD_USER 4
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN 5
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN 6
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK 7
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK 8
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK 9
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK 10
+#define CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK 11
+#define CLK_GOUT_HSI2_GPC_HSI2_PCLK 12
+#define CLK_GOUT_HSI2_GPIO_HSI2_PCLK 13
+#define CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK 14
+#define CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK 15
+#define CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK 16
+#define CLK_GOUT_HSI2_MMC_CARD_I_ACLK 17
+#define CLK_GOUT_HSI2_MMC_CARD_SDCLKIN 18
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG 19
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG 20
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG 21
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK 22
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG 23
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG 24
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG 25
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK 26
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK 27
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK 28
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK 29
+#define CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK 30
+#define CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK 31
+#define CLK_GOUT_HSI2_PPMU_HSI2_ACLK 32
+#define CLK_GOUT_HSI2_PPMU_HSI2_PCLK 33
+#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK 34
+#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK 35
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK 36
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK 37
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK 38
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK 39
+#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK 40
+#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK 41
+#define CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK 42
+#define CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK 43
+#define CLK_GOUT_HSI2_SSMT_HSI2_ACLK 44
+#define CLK_GOUT_HSI2_SSMT_HSI2_PCLK 45
+#define CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2 46
+#define CLK_GOUT_HSI2_SYSREG_HSI2_PCLK 47
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK 48
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK 49
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK 50
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK 51
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK 52
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK 53
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK 54
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK 55
+#define CLK_GOUT_HSI2_UFS_EMBD_I_ACLK 56
+#define CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO 57
+#define CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK 58
+#define CLK_GOUT_HSI2_XIU_D_HSI2_ACLK 59
+#define CLK_GOUT_HSI2_XIU_P_HSI2_ACLK 60
+
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* [PATCH 09/17] phy: samsung-ufs: use exynos_get_pmu_regmap_by_phandle() to obtain PMU regmap
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
This allows us to obtain a PMU regmap that is created by the exynos-pmu
driver. Platforms such as gs101 require exynos-pmu created regmap to
issue SMC calls for PMU register accesses. Existing platforms still get
a MMIO regmap as before.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/phy/samsung/phy-samsung-ufs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 183c88e3d1ec..c567efafc30f 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -18,6 +18,7 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/soc/samsung/exynos-pmu.h>
#include "phy-samsung-ufs.h"
@@ -255,8 +256,8 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev)
goto out;
}
- phy->reg_pmu = syscon_regmap_lookup_by_phandle(
- dev->of_node, "samsung,pmu-syscon");
+ phy->reg_pmu = exynos_get_pmu_regmap_by_phandle(dev->of_node,
+ "samsung,pmu-syscon");
if (IS_ERR(phy->reg_pmu)) {
err = PTR_ERR(phy->reg_pmu);
dev_err(dev, "failed syscon remap for pmu\n");
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* [PATCH 10/17] phy: samsung-ufs: ufs: Add SoC callbacks for calibration and clk data recovery
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
Some SoCs like gs101 don't fit in well with the existing pll lock and
clock data recovery (CDR) callback used by existing exynos platforms.
Allow SoCs to specifify and implement their own calibration and CDR
functions that can be called by the generic samsung phy code.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/phy/samsung/phy-exynos7-ufs.c | 1 +
drivers/phy/samsung/phy-exynosautov9-ufs.c | 1 +
drivers/phy/samsung/phy-fsd-ufs.c | 1 +
drivers/phy/samsung/phy-samsung-ufs.c | 13 ++++++++++---
drivers/phy/samsung/phy-samsung-ufs.h | 5 +++++
5 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
index a982e7c128c5..15eec1d9e0e0 100644
--- a/drivers/phy/samsung/phy-exynos7-ufs.c
+++ b/drivers/phy/samsung/phy-exynos7-ufs.c
@@ -82,4 +82,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
.clk_list = exynos7_ufs_phy_clks,
.num_clks = ARRAY_SIZE(exynos7_ufs_phy_clks),
.cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+ .wait_for_cdr = samsung_ufs_phy_wait_for_lock_acq,
};
diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
index 49e2bcbef0b4..9c3e030f07ba 100644
--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
@@ -71,4 +71,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
.clk_list = exynosautov9_ufs_phy_clks,
.num_clks = ARRAY_SIZE(exynosautov9_ufs_phy_clks),
.cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+ .wait_for_cdr = samsung_ufs_phy_wait_for_lock_acq,
};
diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c
index d36cabd53434..f2361746db0e 100644
--- a/drivers/phy/samsung/phy-fsd-ufs.c
+++ b/drivers/phy/samsung/phy-fsd-ufs.c
@@ -60,4 +60,5 @@ const struct samsung_ufs_phy_drvdata fsd_ufs_phy = {
.clk_list = fsd_ufs_phy_clks,
.num_clks = ARRAY_SIZE(fsd_ufs_phy_clks),
.cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+ .wait_for_cdr = samsung_ufs_phy_wait_for_lock_acq,
};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index c567efafc30f..f57a2f2a415d 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -46,7 +46,7 @@ static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
}
}
-static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
+int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane)
{
struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
const unsigned int timeout_us = 100000;
@@ -98,8 +98,15 @@ static int samsung_ufs_phy_calibrate(struct phy *phy)
}
}
- if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
- err = samsung_ufs_phy_wait_for_lock_acq(phy);
+ for_each_phy_lane(ufs_phy, i) {
+ if (ufs_phy->ufs_phy_state == CFG_PRE_INIT &&
+ ufs_phy->drvdata->wait_for_cal)
+ err = ufs_phy->drvdata->wait_for_cal(phy, i);
+
+ if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS &&
+ ufs_phy->drvdata->wait_for_cdr)
+ err = ufs_phy->drvdata->wait_for_cdr(phy, i);
+ }
/**
* In Samsung ufshci, PHY need to be calibrated at different
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index e122960cfee8..7de6b574b94d 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -112,6 +112,9 @@ struct samsung_ufs_phy_drvdata {
const char * const *clk_list;
int num_clks;
u32 cdr_lock_status_offset;
+ /* SoC's specific operations */
+ int (*wait_for_cal)(struct phy *phy, u8 lane);
+ int (*wait_for_cdr)(struct phy *phy, u8 lane);
};
struct samsung_ufs_phy {
@@ -139,6 +142,8 @@ static inline void samsung_ufs_phy_ctrl_isol(
phy->isol.mask, isol ? 0 : phy->isol.en);
}
+int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);
+
extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* [PATCH 11/17] phy: samsung-ufs: ufs: Add support for gs101 UFS phy tuning
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
Add the m-phy tuning values for gs101 UFS phy and SoC callbacks
gs101_phy_wait_for_calibration() and gs101_phy_wait_for_cdr_lock().
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-gs101-ufs.c | 182 ++++++++++++++++++++++++++
drivers/phy/samsung/phy-samsung-ufs.c | 3 +
drivers/phy/samsung/phy-samsung-ufs.h | 1 +
4 files changed, 187 insertions(+)
create mode 100644 drivers/phy/samsung/phy-gs101-ufs.c
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index afb34a153e34..fea1f96d0e43 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-exynos-ufs.o
+phy-exynos-ufs-y += phy-gs101-ufs.o
phy-exynos-ufs-y += phy-samsung-ufs.o
phy-exynos-ufs-y += phy-exynos7-ufs.o
phy-exynos-ufs-y += phy-exynosautov9-ufs.o
diff --git a/drivers/phy/samsung/phy-gs101-ufs.c b/drivers/phy/samsung/phy-gs101-ufs.c
new file mode 100644
index 000000000000..17b798da5b57
--- /dev/null
+++ b/drivers/phy/samsung/phy-gs101-ufs.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS PHY driver data for Google Tensor gs101 SoC
+ *
+ * Copyright (C) 2024 Linaro Ltd
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ */
+
+#include "phy-samsung-ufs.h"
+
+#define TENSOR_GS101_PHY_CTRL 0x3ec8
+#define TENSOR_GS101_PHY_CTRL_MASK 0x1
+#define TENSOR_GS101_PHY_CTRL_EN BIT(0)
+#define PHY_GS101_LANE_OFFSET 0x200
+#define TRSV_REG338 0x338
+#define LN0_MON_RX_CAL_DONE BIT(3)
+#define TRSV_REG339 0x339
+#define LN0_MON_RX_CDR_FLD_CK_MODE_DONE BIT(3)
+#define TRSV_REG222 0x222
+#define LN0_OVRD_RX_CDR_EN BIT(4)
+#define LN0_RX_CDR_EN BIT(3)
+
+#define PHY_PMA_TRSV_ADDR(reg, lane) (PHY_APB_ADDR((reg) + \
+ ((lane) * PHY_GS101_LANE_OFFSET)))
+
+#define PHY_TRSV_REG_CFG_GS101(o, v, d) \
+ PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_GS101_LANE_OFFSET)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg tensor_gs101_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x43, 0x10, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x3C, 0x14, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x46, 0x48, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x200, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x201, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x202, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x203, 0x0a, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x204, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x205, 0x11, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x207, 0x0c, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2E1, 0xc0, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x22D, 0xb8, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x234, 0x60, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x238, 0x13, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x239, 0x48, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23A, 0x01, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23B, 0x25, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23C, 0x2a, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23D, 0x01, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23E, 0x13, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23F, 0x13, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x240, 0x4a, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x243, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x244, 0x02, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x25D, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x25E, 0x3f, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x25F, 0xff, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x273, 0x33, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x274, 0x50, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x284, 0x02, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x285, 0x02, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2A2, 0x04, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x25D, 0x01, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2FA, 0x01, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x286, 0x03, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x287, 0x03, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x288, 0x03, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x289, 0x03, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2B3, 0x04, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2B6, 0x0b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2B7, 0x0b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2B8, 0x0b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2B9, 0x0b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2BA, 0x0b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2BB, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2BC, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2BD, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x29E, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2E4, 0x1a, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2ED, 0x25, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x269, 0x1a, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2F4, 0x2f, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x34B, 0x01, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x34C, 0x23, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x34D, 0x23, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x34E, 0x45, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x34F, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x350, 0x31, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x351, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x352, 0x02, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x353, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x354, 0x01, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x43, 0x18, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x43, 0x00, PWR_MODE_ANY),
+ END_UFS_PHY_CFG,
+};
+
+static const struct samsung_ufs_phy_cfg tensor_gs101_pre_pwr_hs_config[] = {
+ PHY_TRSV_REG_CFG_GS101(0x369, 0x11, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x246, 0x03, PWR_MODE_ANY),
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg tensor_gs101_post_pwr_hs_config[] = {
+ PHY_COMN_REG_CFG(0x8, 0x60, PWR_MODE_PWM_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x222, 0x08, PWR_MODE_PWM_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x246, 0x01, PWR_MODE_ANY),
+ END_UFS_PHY_CFG,
+};
+
+static const struct samsung_ufs_phy_cfg *tensor_gs101_ufs_phy_cfgs[CFG_TAG_MAX] = {
+ [CFG_PRE_INIT] = tensor_gs101_pre_init_cfg,
+ [CFG_PRE_PWR_HS] = tensor_gs101_pre_pwr_hs_config,
+ [CFG_POST_PWR_HS] = tensor_gs101_post_pwr_hs_config,
+};
+
+static const char * const tensor_gs101_ufs_phy_clks[] = {
+ "ref_clk",
+};
+
+static int gs101_phy_wait_for_calibration(struct phy *phy, u8 lane)
+{
+ struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
+ const unsigned int timeout_us = 40000;
+ const unsigned int sleep_us = 40;
+ u32 val;
+ u32 off;
+ int err;
+
+ off = PHY_PMA_TRSV_ADDR(TRSV_REG338, lane);
+
+ err = readl_poll_timeout(ufs_phy->reg_pma + off,
+ val, (val & LN0_MON_RX_CAL_DONE),
+ sleep_us, timeout_us);
+
+ if (err) {
+ dev_err(ufs_phy->dev,
+ "failed to get phy cal done %d\n", err);
+ }
+
+ return err;
+}
+
+#define DELAY_IN_US 40
+#define RETRY_CNT 100
+static int gs101_phy_wait_for_cdr_lock(struct phy *phy, u8 lane)
+{
+ struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
+ u32 val;
+ int i;
+
+ for (i = 0; i < RETRY_CNT; i++) {
+ udelay(DELAY_IN_US);
+ val = readl(ufs_phy->reg_pma +
+ PHY_PMA_TRSV_ADDR(TRSV_REG339, lane));
+
+ if (val & LN0_MON_RX_CDR_FLD_CK_MODE_DONE)
+ return 0;
+
+ udelay(DELAY_IN_US);
+ /* Override and enable clock data recovery */
+ writel(LN0_OVRD_RX_CDR_EN, ufs_phy->reg_pma +
+ PHY_PMA_TRSV_ADDR(TRSV_REG222, lane));
+ writel(LN0_OVRD_RX_CDR_EN | LN0_RX_CDR_EN,
+ ufs_phy->reg_pma + PHY_PMA_TRSV_ADDR(TRSV_REG222, lane));
+ }
+ dev_err(ufs_phy->dev, "failed to get cdr lock\n");
+ return -ETIMEDOUT;
+}
+
+const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy = {
+ .cfgs = tensor_gs101_ufs_phy_cfgs,
+ .isol = {
+ .offset = TENSOR_GS101_PHY_CTRL,
+ .mask = TENSOR_GS101_PHY_CTRL_MASK,
+ .en = TENSOR_GS101_PHY_CTRL_EN,
+ },
+ .clk_list = tensor_gs101_ufs_phy_clks,
+ .num_clks = ARRAY_SIZE(tensor_gs101_ufs_phy_clks),
+ .wait_for_cal = gs101_phy_wait_for_calibration,
+ .wait_for_cdr = gs101_phy_wait_for_cdr_lock,
+};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index f57a2f2a415d..813bce47121d 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -310,6 +310,9 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev)
static const struct of_device_id samsung_ufs_phy_match[] = {
{
+ .compatible = "google,gs101-ufs-phy",
+ .data = &tensor_gs101_ufs_phy,
+ }, {
.compatible = "samsung,exynos7-ufs-phy",
.data = &exynos7_ufs_phy,
}, {
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 7de6b574b94d..9b7deef6e10f 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -147,5 +147,6 @@ int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);
extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
+extern const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy;
#endif /* _PHY_SAMSUNG_UFS_ */
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* [PATCH 12/17] scsi: ufs: host: ufs-exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
This option is intended to be set on platforms whose ufspr
registers are only accessible via smc call (such as gs101).
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/ufs/host/ufs-exynos.c | 4 +++-
drivers/ufs/host/ufs-exynos.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 734d40f99e31..7b68229f6264 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -1186,7 +1186,9 @@ static int exynos_ufs_init(struct ufs_hba *hba)
if (ret)
goto out;
exynos_ufs_specify_phy_time_attr(ufs);
- exynos_ufs_config_smu(ufs);
+
+ if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE))
+ exynos_ufs_config_smu(ufs);
return 0;
out:
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index a4bd6646d7f1..0fc21b6bbfcd 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -221,6 +221,7 @@ struct exynos_ufs {
#define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3)
#define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5)
+#define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6)
};
#define for_each_ufs_rx_lane(ufs, i) \
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* [PATCH 13/17] scsi: ufs: host: ufs-exynos: add EXYNOS_UFS_OPT_TIMER_TICK_SELECT option
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
This option is intended to be set for SoCs that have HCI_V2P1_CTRL
register and can select their tick source via IA_TICK_SEL bit.
Source clock selection for timer tick
0x0 = Bus clock (aclk)
0x1 = Function clock (mclk)
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/ufs/host/ufs-exynos.c | 9 +++++++++
drivers/ufs/host/ufs-exynos.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 7b68229f6264..1bfda9c75703 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -50,6 +50,8 @@
#define HCI_ERR_EN_N_LAYER 0x80
#define HCI_ERR_EN_T_LAYER 0x84
#define HCI_ERR_EN_DME_LAYER 0x88
+#define HCI_V2P1_CTRL 0x8C
+#define IA_TICK_SEL BIT(16)
#define HCI_CLKSTOP_CTRL 0xB0
#define REFCLKOUT_STOP BIT(4)
#define MPHY_APBCLK_STOP BIT(3)
@@ -1005,6 +1007,13 @@ static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs)
{
u32 val;
+ /* Select function clock (mclk) for timer tick */
+ if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) {
+ val = hci_readl(ufs, HCI_V2P1_CTRL);
+ val |= IA_TICK_SEL;
+ hci_writel(ufs, val, HCI_V2P1_CTRL);
+ }
+
val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL);
hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL);
}
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index 0fc21b6bbfcd..acf07cc54684 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -222,6 +222,7 @@ struct exynos_ufs {
#define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5)
#define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6)
+#define EXYNOS_UFS_OPT_TIMER_TICK_SELECT BIT(7)
};
#define for_each_ufs_rx_lane(ufs, i) \
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* [PATCH 14/17] scsi: ufs: host: ufs-exynos: allow max frequencies up to 267Mhz
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
Platforms such as Tensor gs101 the pclk frequency is 267Mhz.
Increase PCLK_AVAIL_MAX so we don't fail the frequency check.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/ufs/host/ufs-exynos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index acf07cc54684..7acc13914100 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -116,7 +116,7 @@ struct exynos_ufs;
#define PA_HIBERN8TIME_VAL 0x20
#define PCLK_AVAIL_MIN 70000000
-#define PCLK_AVAIL_MAX 167000000
+#define PCLK_AVAIL_MAX 267000000
struct exynos_ufs_uic_attr {
/* TX Attributes */
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* [PATCH 15/17] scsi: ufs: host: ufs-exynos: add some pa_dbg_ register offsets into drvdata
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
This allows these registers to be at different offsets or not
exist at all on some SoCs variants.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/ufs/host/ufs-exynos.c | 38 ++++++++++++++++++++++++-----------
drivers/ufs/host/ufs-exynos.h | 6 +++++-
2 files changed, 31 insertions(+), 13 deletions(-)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 1bfda9c75703..065258203836 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -308,8 +308,9 @@ static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs,
static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
{
+ struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
+ u32 val = attr->pa_dbg_opt_suite1_val;
struct ufs_hba *hba = ufs->hba;
- u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
int i;
exynos_ufs_enable_ov_tm(hba);
@@ -326,12 +327,13 @@ static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
udelay(1);
- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
+ val | (1 << 12));
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
udelay(1600);
- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val);
return 0;
}
@@ -923,14 +925,19 @@ static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
{
+ struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
struct ufs_hba *hba = ufs->hba;
- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
- DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+ if (attr->pa_dbg_clk_period_off)
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off),
+ DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS),
ufs->drv_data->uic_attr->tx_trailingclks);
- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE),
- ufs->drv_data->uic_attr->pa_dbg_option_suite);
+
+ if (attr->pa_dbg_opt_suite1_off)
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
+ attr->pa_dbg_opt_suite1_val);
}
static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
@@ -1486,10 +1493,11 @@ static int exynosauto_ufs_vh_init(struct ufs_hba *hba)
static int fsd_ufs_pre_link(struct exynos_ufs *ufs)
{
- int i;
+ struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
struct ufs_hba *hba = ufs->hba;
+ int i;
- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off),
DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
@@ -1513,7 +1521,9 @@ static int fsd_ufs_pre_link(struct exynos_ufs *ufs)
ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20);
- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), 0x2e820183);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
+ 0x2e820183);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
exynos_ufs_establish_connt(ufs);
@@ -1655,7 +1665,9 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr = {
.rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
.rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
.rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
- .pa_dbg_option_suite = 0x30103,
+ .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD,
+ .pa_dbg_opt_suite1_val = 0x30103,
+ .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE,
};
static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
@@ -1729,7 +1741,9 @@ static struct exynos_ufs_uic_attr fsd_uic_attr = {
.rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
.rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
.rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
- .pa_dbg_option_suite = 0x2E820183,
+ .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD,
+ .pa_dbg_opt_suite1_val = 0x2E820183,
+ .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE,
};
static const struct exynos_ufs_drv_data fsd_ufs_drvs = {
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index 7acc13914100..f30423223474 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -145,7 +145,11 @@ struct exynos_ufs_uic_attr {
/* Common Attributes */
unsigned int cmn_pwm_clk_ctrl;
/* Internal Attributes */
- unsigned int pa_dbg_option_suite;
+ unsigned int pa_dbg_clk_period_off;
+ unsigned int pa_dbg_opt_suite1_val;
+ unsigned int pa_dbg_opt_suite1_off;
+ unsigned int pa_dbg_opt_suite2_val;
+ unsigned int pa_dbg_opt_suite2_off;
/* Changeable Attributes */
unsigned int rx_adv_fine_gran_sup_en;
unsigned int rx_adv_fine_gran_step;
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* [PATCH 16/17] scsi: ufs: host: ufs-exynos: Add support for Tensor gs101 SoC
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
Add a dedicated compatible and drv_data with associated
hooks for gs101 SoC found on Pixel 6.
Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE
option, to skip initialisation of UFSPR registers as these are only
accessible via SMC call.
EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick
source. This has been done so as not to effect any existing platforms.
DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs
so these register offsets now come from uic_attr struct.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/ufs/host/ufs-exynos.c | 146 ++++++++++++++++++++++++++++++++++
drivers/ufs/host/ufs-exynos.h | 14 ++++
2 files changed, 160 insertions(+)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 065258203836..f3f6219f0920 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -61,6 +61,7 @@
#define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\
UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
UNIPRO_PCLK_STOP)
+/* HCI_MISC is also known as HCI_FORCE_HCS */
#define HCI_MISC 0xB4
#define REFCLK_CTRL_EN BIT(7)
#define UNIPRO_PCLK_CTRL_EN BIT(6)
@@ -138,6 +139,9 @@ enum {
/*
* UNIPRO registers
*/
+#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0 0x7888
+#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1 0x788c
+#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2 0x7890
#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8
#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC
#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0
@@ -938,6 +942,10 @@ static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
if (attr->pa_dbg_opt_suite1_off)
ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
attr->pa_dbg_opt_suite1_val);
+
+ if (attr->pa_dbg_opt_suite2_off)
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off),
+ attr->pa_dbg_opt_suite2_val);
}
static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
@@ -1592,6 +1600,96 @@ static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
return 0;
}
+static inline u32 get_mclk_period_unipro_18(struct exynos_ufs *ufs)
+{
+ return (16 * 1000 * 1000000UL / ufs->mclk_rate);
+}
+
+static int gs101_ufs_pre_link(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+ int i;
+ u32 tx_line_reset_period, rx_line_reset_period;
+
+ rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate)
+ / NSEC_PER_MSEC;
+ tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate)
+ / NSEC_PER_MSEC;
+
+ unipro_writel(ufs, get_mclk_period_unipro_18(ufs), COMP_CLK_PERIOD);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i),
+ DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i),
+ (rx_line_reset_period >> 16) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i),
+ (rx_line_reset_period >> 8) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i),
+ (rx_line_reset_period) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
+ }
+
+ for_each_ufs_tx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i),
+ DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i),
+ 0x02);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i),
+ (tx_line_reset_period >> 16) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i),
+ (tx_line_reset_period >> 8) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i),
+ (tx_line_reset_period) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7F, i), 0);
+ }
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0xA006), 0x8000);
+
+ return 0;
+}
+
+static int gs101_ufs_post_link(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+
+ exynos_ufs_enable_dbg_mode(hba);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8);
+ exynos_ufs_disable_dbg_mode(hba);
+
+ return 0;
+}
+
+static int gs101_ufs_pre_pwr_change(struct exynos_ufs *ufs,
+ struct ufs_pa_layer_attr *pwr)
+{
+ struct ufs_hba *hba = ufs->hba;
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
+ unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0);
+ unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1);
+ unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2);
+ unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
+ unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
+ unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
+
+ return 0;
+}
+
static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
.name = "exynos_ufs",
.init = exynos_ufs_init,
@@ -1719,6 +1817,34 @@ static const struct exynos_ufs_drv_data exynos_ufs_drvs = {
.post_pwr_change = exynos7_ufs_post_pwr_change,
};
+static struct exynos_ufs_uic_attr gs101_uic_attr = {
+ .tx_trailingclks = 0xff,
+ .tx_dif_p_nsec = 3000000, /* unit: ns */
+ .tx_dif_n_nsec = 1000000, /* unit: ns */
+ .tx_high_z_cnt_nsec = 20000, /* unit: ns */
+ .tx_base_unit_nsec = 100000, /* unit: ns */
+ .tx_gran_unit_nsec = 4000, /* unit: ns */
+ .tx_sleep_cnt = 1000, /* unit: ns */
+ .tx_min_activatetime = 0xa,
+ .rx_filler_enable = 0x2,
+ .rx_dif_p_nsec = 1000000, /* unit: ns */
+ .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
+ .rx_base_unit_nsec = 100000, /* unit: ns */
+ .rx_gran_unit_nsec = 4000, /* unit: ns */
+ .rx_sleep_cnt = 1280, /* unit: ns */
+ .rx_stall_cnt = 320, /* unit: ns */
+ .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
+ .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
+ .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
+ .pa_dbg_opt_suite1_val = 0x90913C1C,
+ .pa_dbg_opt_suite1_off = PA_GS101_DBG_OPTION_SUITE1,
+ .pa_dbg_opt_suite2_val = 0xE01C115F,
+ .pa_dbg_opt_suite2_off = PA_GS101_DBG_OPTION_SUITE2,
+};
+
static struct exynos_ufs_uic_attr fsd_uic_attr = {
.tx_trailingclks = 0x10,
.tx_dif_p_nsec = 3000000, /* unit: ns */
@@ -1762,7 +1888,27 @@ static const struct exynos_ufs_drv_data fsd_ufs_drvs = {
.pre_pwr_change = fsd_ufs_pre_pwr_change,
};
+static const struct exynos_ufs_drv_data gs101_ufs_drvs = {
+ .uic_attr = &gs101_uic_attr,
+ .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
+ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
+ UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
+ UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
+ UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL |
+ UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
+ .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+ EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+ EXYNOS_UFS_OPT_UFSPR_SECURE |
+ EXYNOS_UFS_OPT_TIMER_TICK_SELECT,
+ .drv_init = exynosauto_ufs_drv_init,
+ .pre_link = gs101_ufs_pre_link,
+ .post_link = gs101_ufs_post_link,
+ .pre_pwr_change = gs101_ufs_pre_pwr_change,
+};
+
static const struct of_device_id exynos_ufs_of_match[] = {
+ { .compatible = "google,gs101-ufs",
+ .data = &gs101_ufs_drvs },
{ .compatible = "samsung,exynos7-ufs",
.data = &exynos_ufs_drvs },
{ .compatible = "samsung,exynosautov9-ufs",
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index f30423223474..1646c4a9bb08 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -9,6 +9,12 @@
#ifndef _UFS_EXYNOS_H_
#define _UFS_EXYNOS_H_
+/*
+ * Component registers
+ */
+
+#define COMP_CLK_PERIOD 0x44
+
/*
* UNIPRO registers
*/
@@ -29,6 +35,14 @@
#define PA_DBG_OPTION_SUITE 0x9564
#define PA_DBG_OPTION_SUITE_DYN 0x9565
+/*
+ * Note: GS101_DBG_OPTION offsets below differ from the TRM
+ * but match the downstream driver. Following the TRM
+ * results in non-functioning UFS.
+ */
+#define PA_GS101_DBG_OPTION_SUITE1 0x956a
+#define PA_GS101_DBG_OPTION_SUITE2 0x956d
+
/*
* MIBs for Transport Layer debug registers
*/
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* [PATCH 17/17] MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101.
From: Peter Griffin @ 2024-04-04 12:25 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul, kishon,
alim.akhtar, avri.altman, bvanassche, s.nawrocki, cw00.choi, jejb,
martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker, Peter Griffin
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
Add the newly created ufs phy for GS101 to MAINTAINERS.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 491d48f7c2fa..48ac9bd64f22 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9256,6 +9256,7 @@ S: Maintained
F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
F: arch/arm64/boot/dts/exynos/google/
F: drivers/clk/samsung/clk-gs101.c
+F: drivers/phy/samsung/phy-gs101-ufs.c
F: include/dt-bindings/clock/google,gs101.h
K: [gG]oogle.?[tT]ensor
--
2.44.0.478.gd926399ef9-goog
^ permalink raw reply related
* Re: (subset) [PATCH V2 1/2] drm/bridge: adv7511: Allow IRQ to share GPIO pins
From: Dmitry Baryshkov @ 2024-04-04 12:30 UTC (permalink / raw)
To: dri-devel, Adam Ford
Cc: aford, laurent.pinchart, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Daniel Vetter, devicetree, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <20240305004859.201085-1-aford173@gmail.com>
On Mon, 04 Mar 2024 18:48:57 -0600, Adam Ford wrote:
> The IRQ registration currently assumes that the GPIO is dedicated
> to it, but that may not necessarily be the case. If the board has
> another device sharing the GPIO, it won't be registered and the
> hot-plug detect fails to function.
>
> Currently, the handler reads two registers and blindly
> assumes one of them caused the interrupt and returns IRQ_HANDLED
> unless there is an error. In order to properly do this, the IRQ
> handler needs to check if it needs to handle the IRQ and return
> IRQ_NONE if there is nothing to handle. With the check added
> and the return code properly indicating whether or not it there
> was an IRQ, the IRQF_SHARED can be set to share a GPIO IRQ.
>
> [...]
Applied to drm-misc-next, thanks!
[1/2] drm/bridge: adv7511: Allow IRQ to share GPIO pins
commit: f3d9683346d6b1d6e24f57e954385995601594d4
Best regards,
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: qcom: msm8998: set qcom,no-msa-ready-indicator for wifi
From: Marc Gonzalez @ 2024-04-04 12:30 UTC (permalink / raw)
To: Kalle Valo, Dmitry Baryshkov
Cc: Konrad Dybcio, Krzysztof Kozlowski, Jeff Johnson, ath10k,
wireless, DT, MSM, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Pierre-Hugues Husson, Arnaud Vrac, Bjorn Andersson, Jami Kettunen,
Jeffrey Hugo
In-Reply-To: <87ttkh49xi.fsf@kernel.org>
On 04/04/2024 13:57, Kalle Valo wrote:
> Dmitry Baryshkov wrote:
>
>> I'd say, we should take a step back and actually verify how this was
>> handled in the vendor kernel.
>
> One comment related to this: usually vendor driver and firmware branches
> go "hand in hand", meaning that a version of driver supports only one
> specific firmware branch. And there can be a lot of branches. So even if
> one branch might have a check for something specific, there are no
> guarantees what the other N+1 branches do :/
The consequences and ramifications of the above comment are not clear to me.
Does this mean:
"It is pointless to analyze a given version (or even several versions)
of the vendor driver downstream, because there are exist a large number
of variations of the code." ?
And thus, "it is nonsensical to try to "align" the mainline driver to
"the" vendor driver, as there is no single "vendor driver"" ?
Thus, the following patch (or one functionally-equivalent) is not acceptable?
diff --git a/drivers/net/wireless/ath/ath10k/qmi.c b/drivers/net/wireless/ath/ath10k/qmi.c
index 38e939f572a9e..fd9ac9717488a 100644
--- a/drivers/net/wireless/ath/ath10k/qmi.c
+++ b/drivers/net/wireless/ath/ath10k/qmi.c
@@ -1040,6 +1040,8 @@ static void ath10k_qmi_driver_event_work(struct work_struct *work)
switch (event->type) {
case ATH10K_QMI_EVENT_SERVER_ARRIVE:
ath10k_qmi_event_server_arrive(qmi);
+ printk(KERN_NOTICE "NOT WAITING FOR MSA_READY INDICATOR");
+ ath10k_qmi_event_msa_ready(qmi);
break;
case ATH10K_QMI_EVENT_SERVER_EXIT:
ath10k_qmi_event_server_exit(qmi);
@@ -1048,7 +1050,7 @@ static void ath10k_qmi_driver_event_work(struct work_struct *work)
ath10k_qmi_event_fw_ready_ind(qmi);
break;
case ATH10K_QMI_EVENT_MSA_READY_IND:
- ath10k_qmi_event_msa_ready(qmi);
+ printk(KERN_NOTICE "IGNORING ACTUAL MSA_READY INDICATOR");
break;
default:
ath10k_warn(ar, "invalid event type: %d", event->type);
Regards
^ permalink raw reply related
* [PATCH v2 0/2] Fix the regulator-state-standby definition
From: Andrei Simion @ 2024-04-04 12:38 UTC (permalink / raw)
To: robh, krzysztof.kozlowski+dt, conor+dt, nicolas.ferre,
alexandre.belloni, claudiu.beznea, mihai.sain
Cc: linux-arm-kernel, devicetree, linux-kernel, Andrei Simion
make dtbs_check DT_SCHEMA_FILES=microchip,mcp16502.yaml
at91-sama7g5ek.dtb: mcp16502@5b: regulators:VDD_(CORE|OTHER)|LDO[1-2]:
regulator-state-standby 'regulator-suspend-voltage' does not match any of
the regexes 'pinctrl-[0-9]+' from schema
$id: http://devicetree.org/schemas/regulator/microchip,mcp16502.yaml#
at91-sama7g54_curiosity.dtb: pmic@5b: regulators:VDD_(CORE|OTHER)|LDO[1-2]:
regulator-state-standby 'regulator-suspend-voltage' does not match any of
the regexes 'pinctrl-[0-9]+' from schema
$id: http://devicetree.org/schemas/regulator/microchip,mcp16502.yaml#
This patch series proposes to correct the typo that was entered by mistake
into devicetree definition regulator-state-standby by replacing
regulator-suspend-voltage with regulator-suspend-microvolt.
--------------------
v1 -> v2:
- drop "boot" from title
- put in commit message a snippet with the warning to explain the chang
--------------------
Andrei Simion (2):
ARM: dts: microchip: at91-sama7g5ek: Replace regulator-suspend-voltage
with the valid property
ARM: dts: microchip: at91-sama7g54_curiosity: Replace
regulator-suspend-voltage with the valid property
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts | 8 ++++----
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
--
2.34.1
^ permalink raw reply
* [PATCH v2 1/2] ARM: dts: microchip: at91-sama7g5ek: Replace regulator-suspend-voltage with the valid property
From: Andrei Simion @ 2024-04-04 12:38 UTC (permalink / raw)
To: robh, krzysztof.kozlowski+dt, conor+dt, nicolas.ferre,
alexandre.belloni, claudiu.beznea, mihai.sain
Cc: linux-arm-kernel, devicetree, linux-kernel, Andrei Simion
In-Reply-To: <20240404123824.19182-1-andrei.simion@microchip.com>
By checking the pmic node with microchip,mcp16502.yaml#
'regulator-suspend-voltage' does not match any of the
regexes 'pinctrl-[0-9]+' from schema microchip,mcp16502.yaml#
which inherits regulator.yaml# So replace regulator-suspend-voltage
with regulator-suspend-microvolt to avoid the inconsitency.
Fixes: 85b1304b9daa ("ARM: dts: at91: sama7g5ek: set regulator voltages for standby state")
Signed-off-by: Andrei Simion <andrei.simion@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
v1 -> v2:
- drop "boot" from title
- put in commit message a snippet with the warning to explain the change
---
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
index 217e9b96c61e..20b2497657ae 100644
--- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
@@ -293,7 +293,7 @@ vddcore: VDD_CORE {
regulator-state-standby {
regulator-on-in-suspend;
- regulator-suspend-voltage = <1150000>;
+ regulator-suspend-microvolt = <1150000>;
regulator-mode = <4>;
};
@@ -314,7 +314,7 @@ vddcpu: VDD_OTHER {
regulator-state-standby {
regulator-on-in-suspend;
- regulator-suspend-voltage = <1050000>;
+ regulator-suspend-microvolt = <1050000>;
regulator-mode = <4>;
};
@@ -331,7 +331,7 @@ vldo1: LDO1 {
regulator-always-on;
regulator-state-standby {
- regulator-suspend-voltage = <1800000>;
+ regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend;
};
@@ -346,7 +346,7 @@ vldo2: LDO2 {
regulator-max-microvolt = <3700000>;
regulator-state-standby {
- regulator-suspend-voltage = <1800000>;
+ regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend;
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 2/2] ARM: dts: microchip: at91-sama7g54_curiosity: Replace regulator-suspend-voltage with the valid property
From: Andrei Simion @ 2024-04-04 12:38 UTC (permalink / raw)
To: robh, krzysztof.kozlowski+dt, conor+dt, nicolas.ferre,
alexandre.belloni, claudiu.beznea, mihai.sain
Cc: linux-arm-kernel, devicetree, linux-kernel, Andrei Simion
In-Reply-To: <20240404123824.19182-1-andrei.simion@microchip.com>
By checking the pmic node with microchip,mcp16502.yaml#
'regulator-suspend-voltage' does not match any of the
regexes 'pinctrl-[0-9]+' from schema microchip,mcp16502.yaml#
which inherits regulator.yaml#. So replace regulator-suspend-voltage
with regulator-suspend-microvolt to avoid the inconsitency.
Fixes: ebd6591f8ddb ("ARM: dts: microchip: sama7g54_curiosity: Add initial device tree of the board")
Signed-off-by: Andrei Simion <andrei.simion@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
v1 -> v2:
- drop "boot" from title
- put in commit message a snippet with the warning to explain the change
---
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts
index 4f609e9e510e..009d2c832421 100644
--- a/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts
+++ b/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts
@@ -242,7 +242,7 @@ vddcore: VDD_CORE {
regulator-state-standby {
regulator-on-in-suspend;
- regulator-suspend-voltage = <1150000>;
+ regulator-suspend-microvolt = <1150000>;
regulator-mode = <4>;
};
@@ -263,7 +263,7 @@ vddcpu: VDD_OTHER {
regulator-state-standby {
regulator-on-in-suspend;
- regulator-suspend-voltage = <1050000>;
+ regulator-suspend-microvolt = <1050000>;
regulator-mode = <4>;
};
@@ -280,7 +280,7 @@ vldo1: LDO1 {
regulator-always-on;
regulator-state-standby {
- regulator-suspend-voltage = <1800000>;
+ regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend;
};
@@ -296,7 +296,7 @@ vldo2: LDO2 {
regulator-always-on;
regulator-state-standby {
- regulator-suspend-voltage = <3300000>;
+ regulator-suspend-microvolt = <3300000>;
regulator-on-in-suspend;
};
--
2.34.1
^ permalink raw reply related
* [PATCH v3] arm64: dts: ti: k3-am62p: use eFuse MAC Address for CPSW3G Port 1
From: Siddharth Vadapalli @ 2024-04-04 12:46 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
Add the "ethernet-mac-syscon" node within "wkup_conf" node corresponding to
the CTRLMMR_MAC_IDx registers within the CTRL_MMR space. Assign the
compatible "ti,am62p-cpsw-mac-efuse" to enable "syscon_regmap" operations
on these registers. The MAC Address programmed in the eFuse is accessible
through the CTRLMMR_MAC_IDx registers. The "ti,syscon-efuse" device-tree
property points to the CTRLMMR_MAC_IDx registers, allowing the CPSW driver
to fetch the MAC Address and assign it to the network interface associated
with CPSW3G MAC Port 1.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
This patch is based on linux-next tagged next-20240404.
Patch depends on:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240402105708.4114146-1-s-vadapalli@ti.com/
for the newly added "ti,am62p-cpsw-mac-efuse" compatible.
v2:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240404081845.622707-1-s-vadapalli@ti.com/
Changes since v2:
- Renamed "cpsw-mac-efuse" node as "ethernet-mac-syscon" based on
Krzysztof's suggestion.
- Renamed "cpsw_mac_efuse" label as "cpsw_mac_syscon" to match
node naming convention.
- Updated node-name in commit message to "ethernet-mac-syscon".
v1:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240402094200.4036076-1-s-vadapalli@ti.com/
Changes since v1:
- Since "wkup_conf" is modelled as a "simple-bus" rather than being
modelled as a System Controller node with the "syscon" compatible,
directly passing the reference to the "wkup_conf" node using the
"ti,syscon-efuse" device-tree property will not work.
Therefore, I posted the patch at:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240402105708.4114146-1-s-vadapalli@ti.com/
in order to add a new compatible to be used for modelling the
CTRLMMR_MAC_IDx registers as System Controller nodes, thereby
allowing the existing "ti,syscon-efuse" property to be used.
Now, "ti,syscon-efuse" points to the "cpsw_mac_efuse" node within
"wkup_conf" node, with "cpsw_mac_efuse" being a "syscon" node.
Logs verifying that the CPSW driver assigns the MAC Address from the
eFuse based on the CTRLMMR_MAC_IDx registers at 0x43000200 and 0x43000204
to the interface eth0 corresponding to CPSW3G MAC Port 1:
https://gist.github.com/Siddharth-Vadapalli-at-TI/63473d68e7a34860566c1339ce3da9f0
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
index 7337a9e13535..21020b7d3034 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -696,6 +696,7 @@ cpsw_port1: port@1 {
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 00 00 00 00];
+ ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
};
cpsw_port2: port@2 {
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
index a84756c336d0..7469b3d3a8c9 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
@@ -18,6 +18,11 @@ chipid: chipid@14 {
reg = <0x14 0x4>;
bootph-all;
};
+
+ cpsw_mac_syscon: ethernet-mac-syscon@200 {
+ compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
+ reg = <0x200 0x8>;
+ };
};
wkup_uart0: serial@2b300000 {
--
2.40.1
^ permalink raw reply related
* Re: [PATCH v19 2/9] usb: dwc3: core: Access XHCI address space temporarily to read port info
From: Greg Kroah-Hartman @ 2024-04-04 12:58 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Johan Hovold, Krishna Kurapati, Krzysztof Kozlowski, Rob Herring,
Bjorn Andersson, Wesley Cheng, Konrad Dybcio, Conor Dooley,
Thinh Nguyen, Felipe Balbi, devicetree, linux-arm-msm, linux-usb,
linux-kernel, quic_ppratap, quic_jackp, Johan Hovold
In-Reply-To: <f16e1280-8f7e-40a7-ab45-9acaeb3e90cb@linaro.org>
On Thu, Apr 04, 2024 at 10:07:27AM +0200, Krzysztof Kozlowski wrote:
> On 04/04/2024 09:21, Johan Hovold wrote:
> > On Thu, Apr 04, 2024 at 10:42:22AM +0530, Krishna Kurapati wrote:
> >
> >> +static int dwc3_get_num_ports(struct dwc3 *dwc)
> >> +{
> >> + void __iomem *base;
> >> + u8 major_revision;
> >> + u32 offset;
> >> + u32 val;
> >> +
> >> + /*
> >> + * Remap xHCI address space to access XHCI ext cap regs since it is
> >> + * needed to get information on number of ports present.
> >> + */
> >> + base = ioremap(dwc->xhci_resources[0].start,
> >> + resource_size(&dwc->xhci_resources[0]));
> >> + if (!base)
> >> + return PTR_ERR(base);
> >
> > This is obviously still broken. You need to update the return value as
> > well.
> >
> > Fix in v20.
>
> If one patchset reaches 20 versions, I think it is time to stop and
> really think from the beginning, why issues keep appearing and reviewers
> are still not happy.
>
> Maybe you did not perform extensive internal review, which you are
> encouraged to by your own internal policies, AFAIR. Before posting next
> version, please really get some internal review first.
Also get those internal reviewers to sign-off on the commits and have
that show up when you post them next. That way they are also
responsible for this patchset, it's not fair that they are making you do
all the work here :)
thanks,
greg k-h
^ permalink raw reply
* Re: [PATCH v19 2/9] usb: dwc3: core: Access XHCI address space temporarily to read port info
From: Greg Kroah-Hartman @ 2024-04-04 12:58 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Johan Hovold, Krishna Kurapati, Krzysztof Kozlowski, Rob Herring,
Bjorn Andersson, Wesley Cheng, Konrad Dybcio, Conor Dooley,
Thinh Nguyen, Felipe Balbi, devicetree, linux-arm-msm, linux-usb,
linux-kernel, quic_ppratap, quic_jackp, Johan Hovold
In-Reply-To: <2024040455-sitting-dictator-170c@gregkh>
On Thu, Apr 04, 2024 at 02:58:29PM +0200, Greg Kroah-Hartman wrote:
> On Thu, Apr 04, 2024 at 10:07:27AM +0200, Krzysztof Kozlowski wrote:
> > On 04/04/2024 09:21, Johan Hovold wrote:
> > > On Thu, Apr 04, 2024 at 10:42:22AM +0530, Krishna Kurapati wrote:
> > >
> > >> +static int dwc3_get_num_ports(struct dwc3 *dwc)
> > >> +{
> > >> + void __iomem *base;
> > >> + u8 major_revision;
> > >> + u32 offset;
> > >> + u32 val;
> > >> +
> > >> + /*
> > >> + * Remap xHCI address space to access XHCI ext cap regs since it is
> > >> + * needed to get information on number of ports present.
> > >> + */
> > >> + base = ioremap(dwc->xhci_resources[0].start,
> > >> + resource_size(&dwc->xhci_resources[0]));
> > >> + if (!base)
> > >> + return PTR_ERR(base);
> > >
> > > This is obviously still broken. You need to update the return value as
> > > well.
> > >
> > > Fix in v20.
> >
> > If one patchset reaches 20 versions, I think it is time to stop and
> > really think from the beginning, why issues keep appearing and reviewers
> > are still not happy.
> >
> > Maybe you did not perform extensive internal review, which you are
> > encouraged to by your own internal policies, AFAIR. Before posting next
> > version, please really get some internal review first.
>
> Also get those internal reviewers to sign-off on the commits and have
> that show up when you post them next. That way they are also
> responsible for this patchset, it's not fair that they are making you do
> all the work here :)
"you" meaning Krishna, sorry for any confusion here.
^ permalink raw reply
* Re: [PATCH 1/6] dt-bindings: adc: ad7173: add support for ad411x
From: Ceclan, Dumitru @ 2024-04-04 13:08 UTC (permalink / raw)
To: David Lechner
Cc: dumitru.ceclan, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-iio, devicetree, linux-kernel
In-Reply-To: <CAMknhBHhxi7mN88+peU7BGkzSP2vtipCuvM-XfQzgusqKvARsg@mail.gmail.com>
On 03/04/2024 18:22, David Lechner wrote:
> On Wed, Apr 3, 2024 at 2:50 AM Ceclan, Dumitru <mitrutzceclan@gmail.com> wrote:
>> On 02/04/2024 00:16, David Lechner wrote:
>>> On Mon, Apr 1, 2024 at 2:37 PM David Lechner <dlechner@baylibre.com> wrote:
>>>> On Mon, Apr 1, 2024 at 10:10 AM Dumitru Ceclan via B4 Relay
>>>> <devnull+dumitru.ceclan.analog.com@kernel.org> wrote:
>>>>> From: Dumitru Ceclan <dumitru.ceclan@analog.com>
>>>>>
>> ...
>>
>>>>> properties:
>>>>> reg:
>>>>> + description:
>>>>> + Reg values 16-19 are only permitted for ad4111/ad4112 current channels.
>>>>> minimum: 0
>>>>> - maximum: 15
>>>>> + maximum: 19
>>>> This looks wrong. Isn't reg describing the number of logical channels
>>>> (# of channel config registers)?
>>>>
>>>> After reviewing the driver, I see that > 16 is used as a way of
>>>> flagging current inputs, but still seems like the wrong way to do it.
>>>> See suggestion below.
>>>>
>>>>> diff-channels:
>>>>> + description:
>>>>> + For using current channels specify only the positive channel.
>>>>> + (IIN2+, IIN2−) -> diff-channels = <2 0>
>>>> I find this a bit confusing since 2 is already VIN2 and 0 is already
>>>> VIN0. I think it would make more sense to assign unique channel
>>>> numbers individually to the negative and positive current inputs.
>>>> Also, I think it makes sense to use the same numbers that the
>>>> registers in the datasheet use (8 - 11 for negative and 12 to 15 for
>>>> positive).
>>>>
>>>> So: (IIN2+, IIN2−) -> diff-channels = <13 10>
>>> Thinking about this a bit more...
>>>
>>> Since the current inputs have dedicated pins and aren't mix-and-match
>>> with multiple valid wiring configurations like the voltage inputs, do
>>> we even need to describe them in the devicetree?
>>>
>>> In the driver, the current channels would just be hard-coded like the
>>> temperature channel since there isn't any application-specific
>>> variation.
>> Sure, but we still need to offer the user a way to configure which
>> current inputs he wants and if they should use bipolar or unipolar coding.
> From the datasheet, it looks like only positive current input is
> allowed so I'm not sure bipolar applies here. But, yes, if there is
> some other variation in wiring or electrical signal that needs to be
> describe here, then it makes sense to allow a channel configuration
> node for it.
AD4111 datasheet pg.29:
When the ADC is configured for bipolar operation, the output
code is offset binary with a negative full-scale voltage resulting
in a code of 000 … 000, a zero differential input voltage resulting in
a code of 100 … 000, and a positive full-scale input voltage
resulting in a code of 111 … 111. The output code for any
analog input voltage can be represented as
Code = 2^(N – 1) × ((V_IN × 0.1/V REF) + 1)
The output code for any input current is represented as
Code = 2^(N − 1) × ((I_IN × 50 Ω/V REF) + 1)
I would say bipolar applies here, not a great idea because of the limitation on
the negative side (Input Current Range min:−0.5 max:+24 mA) so still, the option
is available.
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: qcom: msm8998: set qcom,no-msa-ready-indicator for wifi
From: Dmitry Baryshkov @ 2024-04-04 13:14 UTC (permalink / raw)
To: Marc Gonzalez
Cc: Kalle Valo, Konrad Dybcio, Krzysztof Kozlowski, Jeff Johnson,
ath10k, wireless, DT, MSM, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Pierre-Hugues Husson, Arnaud Vrac, Bjorn Andersson,
Jami Kettunen, Jeffrey Hugo
In-Reply-To: <e804b257-4dc0-45f1-a5c5-66bda51cf296@freebox.fr>
On Thu, 4 Apr 2024 at 15:30, Marc Gonzalez <mgonzalez@freebox.fr> wrote:
>
> On 04/04/2024 13:57, Kalle Valo wrote:
>
> > Dmitry Baryshkov wrote:
> >
> >> I'd say, we should take a step back and actually verify how this was
> >> handled in the vendor kernel.
> >
> > One comment related to this: usually vendor driver and firmware branches
> > go "hand in hand", meaning that a version of driver supports only one
> > specific firmware branch. And there can be a lot of branches. So even if
> > one branch might have a check for something specific, there are no
> > guarantees what the other N+1 branches do :/
>
> The consequences and ramifications of the above comment are not clear to me.
>
> Does this mean:
> "It is pointless to analyze a given version (or even several versions)
> of the vendor driver downstream, because there are exist a large number
> of variations of the code." ?
>
> And thus, "it is nonsensical to try to "align" the mainline driver to
> "the" vendor driver, as there is no single "vendor driver"" ?
>
> Thus, the following patch (or one functionally-equivalent) is not acceptable?
For reference, I tested this patch on sdm845 (db845c), qcm2290 aka
qrb2210 (rb1), sm6115 aka qrb4210 (rb2) and sm8150 platforms.
I was not able to fully test it on sda660, modem crashes without this
patch (there is no MSA_READY indication) and with the patch applied
the device hangs, most likely because of the IOMMU or clocking issue.
>
> diff --git a/drivers/net/wireless/ath/ath10k/qmi.c b/drivers/net/wireless/ath/ath10k/qmi.c
> index 38e939f572a9e..fd9ac9717488a 100644
> --- a/drivers/net/wireless/ath/ath10k/qmi.c
> +++ b/drivers/net/wireless/ath/ath10k/qmi.c
> @@ -1040,6 +1040,8 @@ static void ath10k_qmi_driver_event_work(struct work_struct *work)
> switch (event->type) {
> case ATH10K_QMI_EVENT_SERVER_ARRIVE:
> ath10k_qmi_event_server_arrive(qmi);
> + printk(KERN_NOTICE "NOT WAITING FOR MSA_READY INDICATOR");
> + ath10k_qmi_event_msa_ready(qmi);
> break;
> case ATH10K_QMI_EVENT_SERVER_EXIT:
> ath10k_qmi_event_server_exit(qmi);
> @@ -1048,7 +1050,7 @@ static void ath10k_qmi_driver_event_work(struct work_struct *work)
> ath10k_qmi_event_fw_ready_ind(qmi);
> break;
> case ATH10K_QMI_EVENT_MSA_READY_IND:
> - ath10k_qmi_event_msa_ready(qmi);
> + printk(KERN_NOTICE "IGNORING ACTUAL MSA_READY INDICATOR");
> break;
> default:
> ath10k_warn(ar, "invalid event type: %d", event->type);
>
>
>
> Regards
>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [RFC PATCH 0/6] Support ROHM BD96801 scalable PMIC
From: Matti Vaittinen @ 2024-04-04 13:15 UTC (permalink / raw)
To: Mark Brown
Cc: Matti Vaittinen, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Liam Girdwood, Wim Van Sebroeck, Guenter Roeck,
devicetree, linux-kernel, linux-watchdog
In-Reply-To: <eb03ec33-0627-4986-be04-8e35da390d6b@sirena.org.uk>
Hi Mark,
On 4/4/24 15:09, Mark Brown wrote:
> On Thu, Apr 04, 2024 at 10:26:34AM +0300, Matti Vaittinen wrote:
>
>> 1. Should we be able to have more than 1 IRQ domain / device?
>> 2. Should regmap_irq support having more than 1 HWIRQ
>
> I would expect each parent interrupt to show up as a separate remap_irq.
>
>> then it seems that reading the IRQ information from the /proc/interrupts
>> works as expected. Here I am making a wild guess that the name of the domain
>> is used as a key for some data-lookups, and having two domains with a same
>> name will either overwrite something or cause wrong domain data to be
>> fetched. (This is just guessing for now).
>
> So if we arrange to supply a name when we register multiple domains
> things should work fine?
Thanks for taking the time to look at my questions :)
I have been debugging this thing whole day today, without getting too
far :) It seems there is something beyond the name collision though.
After I tried adding '-1' to the end of the other domain name to avoid
the debugfs name collision I managed to do couple of successful runs -
after which I reported here that problem seems to be just the naming.
Soon after sending that mail I hit the oops again even though the naming
was fixed.
Further debugging shows that the desc->action->name for the last 28
'errb' IRQs get corrupted. This might point more to the IRQ requester
side - so I need to further study the BD96801 driver side as well as the
regulator_irq_helper. I'm having the creeping feeling that at the end of
the day I need to find the guilty one from the mirror :)
But yes, creating 2 regmap-IRQ controllers for one device seems to
generate naming conflict in the debugfs - so unless I'm mistaken, with
the current regmap-IRQ we can't have more than 1 regmap-IRQ entity for a
single device.
Just please give me some more time to see if I find the cause of the
corruption and I hope I can write more concrete description. For now it
was enough for me to hear having more than 1 IRQ domain / device is not
something on the "DON'T DO THIS" -list.
Yours,
-- Matti
--
Matti Vaittinen
Linux kernel developer at ROHM Semiconductors
Oulu Finland
~~ When things go utterly wrong vim users can always type :help! ~~
^ permalink raw reply
* Re: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2
From: André Draszik @ 2024-04-04 13:24 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-9-peter.griffin@linaro.org>
Hi Pete,
Thanks for this!
I haven't reviewed this, but one immediate comment...
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> [...]
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index d065e343a85d..b9f84c7d5c22 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -22,6 +22,7 @@
> #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
> #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
> #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
> +#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
Can you please keep the #defines alphabetical (hsi before misc).
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -3409,6 +3410,560 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
> .clk_name = "bus",
> };
>
> +/* ---- CMU_HSI2 ---------------------------------------------------------- */
and this code block should be earlier in the file
> [..]
> static int __init gs101_cmu_probe(struct platform_device *pdev)
> @@ -3432,6 +3987,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
> }, {
> .compatible = "google,gs101-cmu-peric1",
> .data = &peric1_cmu_info,
> + }, {
> + .compatible = "google,gs101-cmu-hsi2",
> + .data = &hsi2_cmu_info,
> }, {
and this block should move up
> },
> };
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> index 3dac3577788a..ac239ce6821b 100644
> --- a/include/dt-bindings/clock/google,gs101.h
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -518,4 +518,67 @@
> #define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
> #define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
>
> +/* CMU_HSI2 */
and all these defines, too.
Cheers,
Andre'
^ permalink raw reply
* Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
From: Lad, Prabhakar @ 2024-04-04 13:26 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Magnus Damm, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-riscv@lists.infradead.org, Prabhakar Mahadev Lad
In-Reply-To: <OSAPR01MB1587ED05696A111612424CF6863C2@OSAPR01MB1587.jpnprd01.prod.outlook.com>
Hi Biju,
Thank you for the review.
On Thu, Apr 4, 2024 at 8:44 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Wednesday, April 3, 2024 9:35 PM
> > Subject: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared to the RZ/G2L (family)
> > SoC.
> >
> > Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC controller driver. Two new
> > registers, IMSK and TMSK, are defined to handle masking on RZ/Five SoC. The implementation utilizes
> > a new data structure, `struct rzg2l_irqc_data`, to determine mask support for a specific controller
> > instance.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > - Added IRQCHIP_MATCH() for RZ/Five
> > - Retaining a copy of OF data in priv
> > - Rebased the changes
> > ---
> > drivers/irqchip/irq-renesas-rzg2l.c | 137 +++++++++++++++++++++++++++-
> > 1 file changed, 132 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
> > index f6484bf15e0b..6fa8d65605dc 100644
> > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > @@ -37,6 +37,8 @@
> > #define TSSEL_SHIFT(n) (8 * (n))
> > #define TSSEL_MASK GENMASK(7, 0)
> > #define IRQ_MASK 0x3
> > +#define IMSK 0x10010
> > +#define TMSK 0x10020
> >
> > #define TSSR_OFFSET(n) ((n) % 4)
> > #define TSSR_INDEX(n) ((n) / 4)
> > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
> > u32 titsr[2];
> > };
> >
> > +/**
> > + * struct rzg2l_irqc_of_data - OF data structure
> > + * @mask_supported: Indicates if mask registers are available */
> > +struct rzg2l_irqc_of_data {
> > + bool mask_supported;
> > +};
> > +
> > /**
> > * struct rzg2l_irqc_priv - IRQ controller private data structure
> > * @base: Controller's base address
> > + * @data: OF data pointer
> > * @fwspec: IRQ firmware specific data
> > * @lock: Lock to serialize access to hardware registers
> > * @cache: Registers cache for suspend/resume
> > */
> > static struct rzg2l_irqc_priv {
> > void __iomem *base;
> > + const struct rzg2l_irqc_of_data *data;
> > struct irq_fwspec fwspec[IRQC_NUM_IRQ];
> > raw_spinlock_t lock;
> > struct rzg2l_irqc_reg_cache cache;
> > @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
> > irq_chip_eoi_parent(d);
> > }
> >
> > +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > + unsigned int hwirq)
> > +{
> > + u32 imsk = readl_relaxed(priv->base + IMSK);
> > + u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > +
> > + writel_relaxed(imsk | bit, priv->base + IMSK); }
> > +
> > +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > + unsigned int hwirq)
> > +{
> > + u32 imsk = readl_relaxed(priv->base + IMSK);
> > + u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > +
> > + writel_relaxed(imsk & ~bit, priv->base + IMSK); }
> > +
> > +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > + unsigned int hwirq)
> > +{
> > + u32 tmsk = readl_relaxed(priv->base + TMSK);
> > + u32 bit = BIT(hwirq - IRQC_TINT_START);
> > +
> > + writel_relaxed(tmsk | bit, priv->base + TMSK); }
> > +
> > +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > + unsigned int hwirq)
> > +{
> > + u32 tmsk = readl_relaxed(priv->base + TMSK);
> > + u32 bit = BIT(hwirq - IRQC_TINT_START);
> > +
> > + writel_relaxed(tmsk & ~bit, priv->base + TMSK); }
> > +
> > +/* Must be called while priv->lock is held */ static void
> > +rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
> > +{
> > + if (!priv->data->mask_supported)
> > + return;
> > +
> > + if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > + rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
> > + else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > + rzg2l_irqc_mask_tint_interrupt(priv, hwirq); }
> > +
> > +static void rzg2l_irqc_mask(struct irq_data *d) {
> > + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > +
> > + raw_spin_lock(&priv->lock);
> > + rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
> > + raw_spin_unlock(&priv->lock);
> > + irq_chip_mask_parent(d);
> > +}
> > +
> > +/* Must be called while priv->lock is held */ static void
> > +rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int
> > +hwirq) {
> > + if (!priv->data->mask_supported)
> > + return;
> > +
> > + if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > + rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
> > + else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > + rzg2l_irqc_unmask_tint_interrupt(priv, hwirq); }
> > +
> > +static void rzg2l_irqc_unmask(struct irq_data *d) {
> > + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > +
> > + raw_spin_lock(&priv->lock);
> > + rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
> > + raw_spin_unlock(&priv->lock);
> > + irq_chip_unmask_parent(d);
> > +}
> > +
> > static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) {
> > + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > unsigned int hw_irq = irqd_to_hwirq(d);
> >
> > if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> > - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > u32 offset = hw_irq - IRQC_TINT_START;
> > u32 tssr_offset = TSSR_OFFSET(offset);
> > u8 tssr_index = TSSR_INDEX(offset);
> > u32 reg;
> >
> > raw_spin_lock(&priv->lock);
> > + if (enable)
> > + rzg2l_irqc_unmask_once(priv, hw_irq);
> > + else
> > + rzg2l_irqc_mask_once(priv, hw_irq);
> > reg = readl_relaxed(priv->base + TSSR(tssr_index));
> > if (enable)
> > reg |= TIEN << TSSEL_SHIFT(tssr_offset); @@ -157,6 +253,13 @@ static void
> > rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
> > reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
> > writel_relaxed(reg, priv->base + TSSR(tssr_index));
> > raw_spin_unlock(&priv->lock);
> > + } else {
> > + raw_spin_lock(&priv->lock);
> > + if (enable)
> > + rzg2l_irqc_unmask_once(priv, hw_irq);
> > + else
> > + rzg2l_irqc_mask_once(priv, hw_irq);
> > + raw_spin_unlock(&priv->lock);
> > }
> > }
> >
> > @@ -324,8 +427,8 @@ static struct syscore_ops rzg2l_irqc_syscore_ops = { static const struct
> > irq_chip irqc_chip = {
> > .name = "rzg2l-irqc",
> > .irq_eoi = rzg2l_irqc_eoi,
> > - .irq_mask = irq_chip_mask_parent,
> > - .irq_unmask = irq_chip_unmask_parent,
> > + .irq_mask = rzg2l_irqc_mask,
> > + .irq_unmask = rzg2l_irqc_unmask,
>
> I feel this will be clean, if we have
>
> static const struct irq_chip rzg2l_irqc_chip = {
> .name = "rzg2l-irqc",
> ...
> .irq_mask = irq_chip_mask_parent,
> .irq_unmask = irq_chip_unmask_parent,
> ....
> };
>
> static const struct irq_chip rzfive_irqc_chip = {
> .name = "rzfive-irqc",
> ...
> .irq_mask = rzfive_irqc_mask,
> .irq_unmask = rzfive_irqc_unmask,
> ....
> };
>
> And passing this in rzg2l_irqc_init() and rzfive_irqc_init(), see below
>
> return rzg2l_irqc_init_helper(node, parent, & rzg2l_irqc_chip);
> return rzg2l_irqc_init_helper(node, parent, & rzfive_irqc_chip);
>
If we do the above we are stuck with "struct irq_chip" as data, for
further upcoming SoCs (for example RZ/V2H) which have more features we
need to pass custom data to handle these features.
>
> > .irq_disable = rzg2l_irqc_irq_disable,
> > .irq_enable = rzg2l_irqc_irq_enable,
> > .irq_get_irqchip_state = irq_chip_get_parent_state,
> > @@ -401,7 +504,16 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
> > return 0;
> > }
> >
> > -static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
> > +static const struct rzg2l_irqc_of_data rzg2l_irqc_mask_supported_data = {
> > + .mask_supported = true,
> > +};
> > +
> > +static const struct rzg2l_irqc_of_data rzg2l_irqc_default_data = {
> > + .mask_supported = false,
> > +};
> > +
> > +static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent,
> > + const struct rzg2l_irqc_of_data *of_data)
>
> Maybe rename this as rzg2l_irqc_init_helper()
OK.
> > {
> > struct irq_domain *irq_domain, *parent_domain;
> > struct platform_device *pdev;
> > @@ -422,6 +534,8 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node
> > *parent)
> > if (!rzg2l_irqc_data)
> > return -ENOMEM;
> >
> > + rzg2l_irqc_data->data = of_data;
> > +
> > rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
> > if (IS_ERR(rzg2l_irqc_data->base))
> > return PTR_ERR(rzg2l_irqc_data->base); @@ -472,8 +586,21 @@ static int
> > rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
> > return ret;
> > }
> >
> > +static int __init rzg2l_irqc_default_init(struct device_node *node,
> > + struct device_node *parent)
> > +{
> > + return rzg2l_irqc_init(node, parent, &rzg2l_irqc_default_data); }
> > +
> > +static int __init rzg2l_irqc_mask_supported_init(struct device_node *node,
> > + struct device_node *parent)
> > +{
> > + return rzg2l_irqc_init(node, parent, &rzg2l_irqc_mask_supported_data);
> > +}
> > +
> > IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
> > -IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
> Retain this name
>
OK.
> > +IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_default_init)
> > +IRQCHIP_MATCH("renesas,r9a07g043f-irqc",
> > +rzg2l_irqc_mask_supported_init)
> Maybe rename this as rzfive_irqc_init ??
>
OK.
Cheers,
Prabhakar
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