* [PATCH v2 5/5] ARM: dts: aspeed: drop unused ref_voltage ADC property
From: Krzysztof Kozlowski @ 2024-04-05 6:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20240405064624.18997-1-krzysztof.kozlowski@linaro.org>
Aspeed ADC "ref_voltage" property is neither documented nor used.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v2:
1. None
---
arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts | 1 -
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts | 2 --
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 2 --
3 files changed, 5 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts
index 7b540880cef9..3c8925034a8c 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts
@@ -813,7 +813,6 @@ bmc_ast2600_cpu: temperature-sensor@35 {
};
&adc0 {
- ref_voltage = <2500>;
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts
index 9a6757dd203f..998598c15fd0 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts
@@ -211,7 +211,6 @@ &i2c13 {
};
&adc0 {
- ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
@@ -220,7 +219,6 @@ &pinctrl_adc4_default &pinctrl_adc5_default
};
&adc1 {
- ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc10_default
&pinctrl_adc11_default &pinctrl_adc12_default
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 1bd555a6c3ba..b4d003cbae8b 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -596,7 +596,6 @@ i2c-mux@72 {
};
&adc0 {
- ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
@@ -605,7 +604,6 @@ &pinctrl_adc4_default &pinctrl_adc5_default
};
&adc1 {
- ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default>;
};
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 1/4] ARM: dts: aspeed: greatlakes: correct Mellanox multi-host property
From: Krzysztof Kozlowski @ 2024-04-05 6:48 UTC (permalink / raw)
To: Andrew Jeffery, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <65060691d4649c4a8da46e5ba762a3c905ade690.camel@codeconstruct.com.au>
On 05/04/2024 01:21, Andrew Jeffery wrote:
>>>
>>> Acked-by: Andrew Jeffery <andrew@codeconstruct.com.au>
>>>
>>> I'm working to stay on top of things a bit more now than I have in the
>>> recent past, so hopefully I won't miss patches again in the future.
>>
>> Stephen reported conflict, although trivial, but maybe better if you
>> take them?
>>
>
> Yeah, happy to.
>
>> I can rebase and resend.
I dropped these patches (and one more) from my tree, rebased and resent
everything as v2.
Thanks!
Best regards,
Krzysztof
^ permalink raw reply
* Re: [RFC PATCH 0/2] Add Qualcomm PCIe ECAM root complex driver
From: Krzysztof Kozlowski @ 2024-04-05 6:50 UTC (permalink / raw)
To: Mayank Rana, linux-pci, lpieralisi, kw, robh, bhelgaas, andersson,
manivannan.sadhasivam, krzysztof.kozlowski+dt, conor+dt,
devicetree
Cc: linux-arm-msm, quic_ramkri, quic_nkela, quic_shazhuss,
quic_msarkar, quic_nitegupt
In-Reply-To: <1d2d231a-ab2e-4552-9e72-2655d778f3b8@quicinc.com>
On 05/04/2024 01:02, Mayank Rana wrote:
> Hi Krzysztof
>
> On 4/4/2024 12:33 PM, Krzysztof Kozlowski wrote:
>> On 04/04/2024 21:11, Mayank Rana wrote:
>>> On some of Qualcomm platform, firmware takes care of system resources
>>> related to PCIe PHY and controller as well bringing up PCIe link and
>>> having static iATU configuration for PCIe controller to work into
>>> ECAM compliant mode. Hence add Qualcomm PCIe ECAM root complex driver.
>>>
>>> Tested:
>>> - Validated NVME functionality with PCIe0 and PCIe1 on SA877p-ride platform
>>>
>>
>> RFC means code is not ready, right? Please get internal review done and
>> send it when it is ready. I am not sure if you expect any reviews. Some
>> people send RFC and do not expect reviews. Some expect. I have no clue
>> and I do not want to waste my time. Please clarify what you expect from
>> maintainers regarding this contribution.
>>
>> Best regards,
>> Krzysztof
>>
> Thanks for initial comments.
> yes, this is work in progress. There are still more functionalities
> planned to be added as part of this driver. Although purpose of sending
> initial change here to get feedback and review comments in terms of
> usage of generic Qualcomm PCIe ECAM driver, and usage of MSI
> functionality with it. I missed mentioning this as part of cover letter.
> So please help to review and provide feedback.
Thanks for explanation. Work in progress as not ready to be merged? Then
I am sorry, I am not going to provide review of unfinished work. I have
many more *finished* patches to review first. You can help with these
too....
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH] dt-bindings: mfd: syscon: Add ti,am62p-cpsw-mac-efuse compatible
From: Krzysztof Kozlowski @ 2024-04-05 6:55 UTC (permalink / raw)
To: Siddharth Vadapalli, Krzysztof Kozlowski
Cc: lee, robh, krzk+dt, conor+dt, devicetree, linux-kernel,
linux-arm-kernel, srk
In-Reply-To: <94bae793-ba4f-467f-917d-213fa3cd6faa@ti.com>
On 05/04/2024 07:21, Siddharth Vadapalli wrote:
>>>> bindings in the changelog or cover letter.
>>>
>>> Thank you for clarifying. I will post the DTS patches corresponding to
>>> this patch and reference this patch in the DTS patch series.
>>
>> I have posted the DTS patch at:
>> https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240404081845.622707-1-s-vadapalli@ti.com/
>> indicating the dependency on this bindings patch.
>
> Hello Krzysztof,
>
> Do I have to post a v2 for this patch? You had Acked it initially but I
No, I acked it. All this unnecessary talk was because you did not post a
user, but it is not a requirement, at least when we expect such user.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v6 10/23] drivers: crypto: meson: avoid kzalloc in engine thread
From: Herbert Xu @ 2024-04-05 6:55 UTC (permalink / raw)
To: Alexey Romanov
Cc: neil.armstrong, clabbe, davem, robh+dt, krzysztof.kozlowski+dt,
conor+dt, khilman, jbrunet, martin.blumenstingl, vadim.fedorenko,
linux-crypto, linux-amlogic, linux-kernel, devicetree,
linux-arm-kernel, kernel
In-Reply-To: <20240326153219.2915080-11-avromanov@salutedevices.com>
On Tue, Mar 26, 2024 at 06:32:06PM +0300, Alexey Romanov wrote:
>
> /*
> * struct meson_cipher_tfm_ctx - context for a skcipher TFM
> - * @key: pointer to key data
> + * @keyiv: key data
> * @keylen: len of the key
> * @keymode: The keymode(type and size of key) associated with this TFM
> * @mc: pointer to the private data of driver handling this TFM
> * @fallback_tfm: pointer to the fallback TFM
> */
> struct meson_cipher_tfm_ctx {
> - u32 *key;
> - u32 keylen;
> + u8 keyiv[AES_MAX_KEY_SIZE + AES_BLOCK_SIZE] ____cacheline_aligned;
> + u32 keylen ____cacheline_aligned;
This doesn't do anything to guarantee that tfm_ctx is aligned.
You either need to align this by hand, or you could use the
crypto_skcipher_ctx_dma helper if DMA alignment is what you're
actually looking for.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH v6 11/23] drivers: crypto: meson: introduce hasher
From: Herbert Xu @ 2024-04-05 6:56 UTC (permalink / raw)
To: Alexey Romanov
Cc: neil.armstrong, clabbe, davem, robh+dt, krzysztof.kozlowski+dt,
conor+dt, khilman, jbrunet, martin.blumenstingl, vadim.fedorenko,
linux-crypto, linux-amlogic, linux-kernel, devicetree,
linux-arm-kernel, kernel
In-Reply-To: <20240326153219.2915080-12-avromanov@salutedevices.com>
On Tue, Mar 26, 2024 at 06:32:07PM +0300, Alexey Romanov wrote:
> Introduce support for SHA1/SHA224/SHA256 hash algos.
> Tested via tcrypt and custom tests.
>
> Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
> ---
> drivers/crypto/amlogic/Makefile | 2 +-
> drivers/crypto/amlogic/amlogic-gxl-core.c | 25 +-
> drivers/crypto/amlogic/amlogic-gxl-hasher.c | 460 ++++++++++++++++++++
> drivers/crypto/amlogic/amlogic-gxl.h | 51 +++
> 4 files changed, 536 insertions(+), 2 deletions(-)
> create mode 100644 drivers/crypto/amlogic/amlogic-gxl-hasher.c
Where are the import/export functions?
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: mfd: Add ROHM BD71879
From: Krzysztof Kozlowski @ 2024-04-05 6:56 UTC (permalink / raw)
To: Andreas Kemnade, lee, robh+dt, krzysztof.kozlowski+dt, conor+dt,
mazziesaccount, devicetree, linux-kernel
In-Reply-To: <20240404195423.666446-2-andreas@kemnade.info>
On 04/04/2024 21:54, Andreas Kemnade wrote:
> As this chip was seen in several devices in the wild, add it.
>
> Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
> Suggested-by: Matti Vaittinen <mazziesaccount@gmail.com>
> ---
> .../devicetree/bindings/mfd/rohm,bd71828-pmic.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: mfd: Add ROHM BD71879
From: Matti Vaittinen @ 2024-04-05 6:58 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andreas Kemnade
Cc: lee, robh+dt, krzysztof.kozlowski+dt, conor+dt, devicetree,
linux-kernel
In-Reply-To: <35a9399e-819a-400c-b321-099f8bc9df90@linaro.org>
On 4/5/24 09:35, Krzysztof Kozlowski wrote:
> On 05/04/2024 08:01, Matti Vaittinen wrote:
>> On 4/4/24 15:04, Krzysztof Kozlowski wrote:
>>> On 04/04/2024 12:30, Andreas Kemnade wrote:
>>>> On Thu, 4 Apr 2024 08:59:54 +0200
>>>> Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>>> On 02/04/2024 21:35, Andreas Kemnade wrote:
>>>>>> As this chip was seen in several devices in the wild, add it.
>>>>>>
>>>>>> Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
>>>>>> Suggested-by: Matti Vaittinen <mazziesaccount@gmail.com>
>>>>>> ---
>>>>>> Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml | 4 +++-
>>>>>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
>>>>>> index 0b62f854bf6b..e4df09e8961c 100644
>>>>>> --- a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
>>>>>> +++ b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
>>>>>> @@ -17,7 +17,9 @@ description: |
>>>>>>
...
Compatibility means that software can use fallback
> compatible as matching mechanism and everything will work fine or with
> reduced set of features, but still working.
Thanks to both of you Andreas and Krzysztof!
Then I'm fine with this.
Yours,
-- Matti
--
Matti Vaittinen
Linux kernel developer at ROHM Semiconductors
Oulu Finland
~~ When things go utterly wrong vim users can always type :help! ~~
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: omap-mcpdm: Convert to DT schema
From: Krzysztof Kozlowski @ 2024-04-05 6:58 UTC (permalink / raw)
To: Mighty
Cc: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, alsa-devel, devicetree, linux-kernel
In-Reply-To: <20240404160649.967-1-bavishimithil@gmail.com>
On 04/04/2024 18:06, Mighty wrote:
> From: Mithil Bavishi <bavishimithil@gmail.com>
>
> Convert the OMAP4+ McPDM bindings to DT schema.
>
> Signed-off-by: Mighty <bavishimithil@gmail.com>
This does not match SoB. Can you respond to comments you receive?
Subject: nothing improved.
Rest... also did not improve. so you ignored entire feedback?
This is a friendly reminder during the review process.
It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.
Thank you.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 2/2] mfd: rohm-bd71828: Add software-compatible variant BD71879
From: Krzysztof Kozlowski @ 2024-04-05 7:00 UTC (permalink / raw)
To: Andreas Kemnade, lee, robh+dt, krzysztof.kozlowski+dt, conor+dt,
mazziesaccount, devicetree, linux-kernel
In-Reply-To: <20240404195423.666446-3-andreas@kemnade.info>
On 04/04/2024 21:54, Andreas Kemnade wrote:
> Add the BD71879 PMIC which is software-compatible to the BD71828, so reuse
> the same device_type enum.
>
> Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
> Suggested-by: Matti Vaittinen <mazziesaccount@gmail.com>
> Acked-by: Matti Vaittinen <mazziesaccount@gmail.com>
> ---
Now you can drop this patch. The benefit of the compatibility is to drop
this code.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: arm64: marvell: add solidrun cn9130 som based boards
From: Krzysztof Kozlowski @ 2024-04-05 7:03 UTC (permalink / raw)
To: Josua Mayer, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Rob Herring
Cc: Yazan Shhady, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20240404-cn9130-som-v2-1-3af2229c7d2d@solid-run.com>
On 04/04/2024 17:35, Josua Mayer wrote:
> Add bindings for SolidRun boards based on CN9130 SoM.
>
> Three boards are added in total:
> - Clearfog Base
> - Clearfog Pro
> - SolidWAN
> The Clearfog boards are identical to the older Armada 388 based boards,
> upgraded with a new SoM and SoC.
> However the feature set and performance characteristics are different,
> therefore compatible strings from armada 388 versions are not included.
>
> SolidWAN uses the same SoM adding a southbridge on the carrier.
>
> Since 2019 there are bindings in-tree for two boards based on cn9130 and
> 9131. These are extremely verbose by listing cn9132, cn9131, cn9130,
> ap807-quad, ap807 for the SoC alone.
> CN9130 SoC combines an application processor (ap807) and a
> communication processor (cp115) in a single package.
>
> The communication processor (short CP) is also available separately as a
> southbridge. It only functions in combination with the CN9130 SoC.
> Complete systems adding one or two southbridges are by convention called
> CN9131 and CN9132 respectively.
> Despite different naming all systems are built around the same SoC.
> Therefore marvell,cn9131 and marvell,cn9132 can be omitted. The number
> of CPs is part of a board's BoM and can be reflected in the board
> compatible string instead.
>
> Existing bindings also describe cn9130 as a specialisation of
> ap807-quad. Usually board-level compatibles stop at the SoC without
> going into silicon versions or individual dies.
> There is no programming model at this layer, and in particular not for
> parts of an SoC. Therefore the ap compatibles can also be omitted.
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 2/3] dt-bindings: arm64: marvell: add solidrun cn9132 CEX-7 evaluation board
From: Krzysztof Kozlowski @ 2024-04-05 7:04 UTC (permalink / raw)
To: Josua Mayer, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Rob Herring
Cc: Yazan Shhady, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20240404-cn9130-som-v2-2-3af2229c7d2d@solid-run.com>
On 04/04/2024 17:35, Josua Mayer wrote:
> Add bindings for the SolidRun CN9132 COM-Express Type 7 evaluation board.
> The CEX is based on CN9130 SoC and includes two southbridges.
>
> Because CN9132 and 9131 are just names for different designs around the
> same SoC, there no soc compatibles beside marvell,cn9130 are needed.
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 09/17] phy: samsung-ufs: use exynos_get_pmu_regmap_by_phandle() to obtain PMU regmap
From: André Draszik @ 2024-04-05 7:04 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-10-peter.griffin@linaro.org>
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> This allows us to obtain a PMU regmap that is created by the exynos-pmu
> driver. Platforms such as gs101 require exynos-pmu created regmap to
> issue SMC calls for PMU register accesses. Existing platforms still get
> a MMIO regmap as before.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/phy/samsung/phy-samsung-ufs.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
> index 183c88e3d1ec..c567efafc30f 100644
> --- a/drivers/phy/samsung/phy-samsung-ufs.c
> +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> @@ -18,6 +18,7 @@
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> +#include <linux/soc/samsung/exynos-pmu.h>
You can now drop the include of linux/mfd/syscon.h
Once done, feel free to add
Reviewed-by: André Draszik <andre.draszik@linaro.org>
>
> #include "phy-samsung-ufs.h"
>
> @@ -255,8 +256,8 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev)
> goto out;
> }
>
> - phy->reg_pmu = syscon_regmap_lookup_by_phandle(
> - dev->of_node, "samsung,pmu-syscon");
> + phy->reg_pmu = exynos_get_pmu_regmap_by_phandle(dev->of_node,
> + "samsung,pmu-syscon");
> if (IS_ERR(phy->reg_pmu)) {
> err = PTR_ERR(phy->reg_pmu);
> dev_err(dev, "failed syscon remap for pmu\n");
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: add description for solidrun cn9130 som and clearfog boards
From: Krzysztof Kozlowski @ 2024-04-05 7:05 UTC (permalink / raw)
To: Josua Mayer, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Rob Herring
Cc: Yazan Shhady, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20240404-cn9130-som-v2-3-3af2229c7d2d@solid-run.com>
On 04/04/2024 17:35, Josua Mayer wrote:
> Add description for the SolidRun CN9130 SoM, and Clearfog Base / Pro
> reference boards.
>
> The SoM has been designed as a pin-compatible replacement for the older
> Armada 388 based SoM. Therefore it supports the same boards and a
> similar feature set.
>
> Most notable upgrades:
> - 4x Cortex-A72
> - 10Gbps SFP
> - Both eMMC and SD supported at the same time
>
> The developer first supporting this product at SolidRun decided to use
> different filenames for the DTBs: Armada 388 uses the full
> "clearfog" string while cn9130 uses the abbreviation "cf".
> This name is already hard-coded in pre-installed vendor u-boot and can
> not be changed easily.
>
> NOTICE IN CASE ANYBODY WANTS TO SELF-UPGRADE:
> CN9130 SoM has a different footprint from Armada 388 SoM.
> Components on the carrier board below the SoM may collide causing
> damage, such as on Clearfog Base.
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [RESEND PATCH v9 2/4] dt-bindings: stm32: update DT bingding for stm32mp25
From: Krzysztof Kozlowski @ 2024-04-05 7:12 UTC (permalink / raw)
To: gabriel.fernandez, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Philipp Zabel
Cc: linux-clk, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel
In-Reply-To: <20240402125312.277052-3-gabriel.fernandez@foss.st.com>
On 02/04/2024 14:53, gabriel.fernandez@foss.st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
>
> Now RCC driver use '.index' of clk_parent_data struct to define a parent.
> The majority of parents are SCMI clocks, then dt-bindings must be fixed.
>
> Fixes: b5be49db3d47 ("dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform")
And except what Rob said, this does not look as a fix. How ABI break
could be a fix and what is even to fix here? Please describe the
observable bug, how it manifests itself and what is exactly the fix for
that bug.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 01/17] dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
From: André Draszik @ 2024-04-05 7:15 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-2-peter.griffin@linaro.org>
Hi Pete,
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> Add dt schema documentation and clock IDs for the High Speed Interface
> 2 (HSI2) clock management unit. This CMU feeds high speed interfaces
> such as PCIe and UFS.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/clock/google,gs101-clock.yaml | 30 +++++++++++++++++--
> 1 file changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-
> clock.yaml
> index 1d2bcea41c85..a202fd5d1ead 100644
> --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -32,14 +32,15 @@ properties:
> - google,gs101-cmu-misc
> - google,gs101-cmu-peric0
> - google,gs101-cmu-peric1
> + - google,gs101-cmu-hsi2
Can you keep this alphabetical and add hsi before misc please.
>
> clocks:
> minItems: 1
> - maxItems: 3
> + maxItems: 5
>
> clock-names:
> minItems: 1
> - maxItems: 3
> + maxItems: 5
>
> "#clock-cells":
> const: 1
> @@ -112,6 +113,31 @@ allOf:
> - const: bus
> - const: ip
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - google,gs101-cmu-hsi2
this block should also come before misc please.
Once done, feel free to add
Reviewed-by: André Draszik <andre.draszik@linaro.org>
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (24.576 MHz)
> + - description: High Speed Interface bus clock (from CMU_TOP)
> + - description: High Speed Interface pcie clock (from CMU_TOP)
> + - description: High Speed Interface ufs clock (from CMU_TOP)
> + - description: High Speed Interface mmc clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: bus
> + - const: pcie
> + - const: ufs_embd
> + - const: mmc_card
> +
> additionalProperties: false
>
> examples:
^ permalink raw reply
* Re: [PATCH 02/17] dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible
From: André Draszik @ 2024-04-05 7:19 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-3-peter.griffin@linaro.org>
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> Update dt schema to include the gs101 hsi2 sysreg compatible.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: André Draszik <andre.draszik@linaro.org>
^ permalink raw reply
* Re: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2
From: André Draszik @ 2024-04-05 7:23 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-9-peter.griffin@linaro.org>
Hi Pete,
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> index 3dac3577788a..ac239ce6821b 100644
> --- a/include/dt-bindings/clock/google,gs101.h
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -518,4 +518,67 @@
> #define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
> #define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
>
> +/* CMU_HSI2 */
You need to add these defines as part of the patch that is updating the
binding (patch 1 this series).
Cheers,
Andre'
^ permalink raw reply
* Re: [PATCH] dt-bindings: timer: renesas,tmu: Add R-Car V4M support
From: Wolfram Sang @ 2024-04-05 7:28 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Daniel Lezcano, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Laurent Pinchart, devicetree, linux-renesas-soc,
linux-kernel
In-Reply-To: <8a39386b1a33db6e83e852b3b365bc1adeb25242.1712068574.git.geert+renesas@glider.be>
[-- Attachment #1: Type: text/plain, Size: 291 bytes --]
On Tue, Apr 02, 2024 at 04:37:02PM +0200, Geert Uytterhoeven wrote:
> Document support for the Timer Unit (TMU) in the Renesas R-Car V4M
> (R8A779H0) SoC.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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^ permalink raw reply
* Re: [PATCH 06/17] arm64: dts: exynos: gs101: Add the hsi2 sysreg node
From: André Draszik @ 2024-04-05 7:33 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-7-peter.griffin@linaro.org>
Hi Pete,
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> This has some configuration bits such as sharability that
> are required by UFS.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 38ac4fb1397e..608369cec47b 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 {
> clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> };
>
> + sysreg_hsi2: syscon@14420000 {
> + compatible = "google,gs101-hsi2-sysreg", "syscon";
> + reg = <0x14420000 0x1000>;
Should the length not be 0x10000?
Cheers,
Andre'
^ permalink raw reply
* Re: [PATCH] dt-bindings: timer: renesas,cmt: Add R-Car V4M support
From: Wolfram Sang @ 2024-04-05 7:27 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Daniel Lezcano, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Laurent Pinchart, devicetree, linux-renesas-soc,
linux-kernel
In-Reply-To: <3e8a7a93261d8ad264dec2fa2784fe1bbfc4a23c.1712068536.git.geert+renesas@glider.be>
[-- Attachment #1: Type: text/plain, Size: 324 bytes --]
On Tue, Apr 02, 2024 at 04:36:05PM +0200, Geert Uytterhoeven wrote:
> Document support for the Compare Match Timer Type0 (CMT0) and Type1
> (CMT1) in the Renesas R-Car V4M (R8A779H0) SoC.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller
From: André Draszik @ 2024-04-05 7:38 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-6-peter.griffin@linaro.org>
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> Enable the cmu_hsi2 clock management unit. It feeds some of
> the high speed interfaces such as PCIe and UFS.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index eddb6b326fde..38ac4fb1397e 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
> interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
> };
>
> + cmu_hsi2: clock-controller@14400000 {
> + compatible = "google,gs101-cmu-hsi2";
> + reg = <0x14400000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&ext_24_5m>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> + clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> + };
This doesn't build because you didn't add the clock ids in the binding patch.
Other than that,
Reviewed-by: André Draszik <andre.draszik@linaro.org>
> +
> pinctrl_hsi2: pinctrl@14440000 {
> compatible = "google,gs101-pinctrl";
> reg = <0x14440000 0x00001000>;
^ permalink raw reply
* [PATCH 0/2] clk: rockchip: clk-rk3568.c: Add missing USB480M_PHY mux
From: Sascha Hauer @ 2024-04-05 7:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-rockchip, Sascha Hauer, David Jander
This series adds a missing clock for the Rockchip RK3568.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
David Jander (1):
clk: rockchip: clk-rk3568.c: Add missing USB480M_PHY mux
Sascha Hauer (1):
dt-bindings: clock: rockchip: add USB480M_PHY mux
drivers/clk/rockchip/clk-rk3568.c | 4 ++++
include/dt-bindings/clock/rk3568-cru.h | 1 +
2 files changed, 5 insertions(+)
---
base-commit: 39cd87c4eb2b893354f3b850f916353f2658ae6f
change-id: 20240405-clk-rk3568-usb480m-phy-mux-ea78af0c1ec5
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
^ permalink raw reply
* [PATCH 1/2] dt-bindings: clock: rockchip: add USB480M_PHY mux
From: Sascha Hauer @ 2024-04-05 7:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-rockchip, Sascha Hauer
In-Reply-To: <20240405-clk-rk3568-usb480m-phy-mux-v1-0-6c89de20a6ff@pengutronix.de>
The USB480M clock can source from a MUX that selects the clock to come
from either of the USB-phy internal 480MHz PLLs. These clocks are
provided by the USB phy driver. This adds the define for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/dt-bindings/clock/rk3568-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h
index d29890865150d..5263085c5b238 100644
--- a/include/dt-bindings/clock/rk3568-cru.h
+++ b/include/dt-bindings/clock/rk3568-cru.h
@@ -78,6 +78,7 @@
#define CPLL_333M 9
#define ARMCLK 10
#define USB480M 11
+#define USB480M_PHY 12
#define ACLK_CORE_NIU2BUS 18
#define CLK_CORE_PVTM 19
#define CLK_CORE_PVTM_CORE 20
--
2.39.2
^ permalink raw reply related
* [PATCH 2/2] clk: rockchip: clk-rk3568.c: Add missing USB480M_PHY mux
From: Sascha Hauer @ 2024-04-05 7:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-rockchip, Sascha Hauer, David Jander
In-Reply-To: <20240405-clk-rk3568-usb480m-phy-mux-v1-0-6c89de20a6ff@pengutronix.de>
From: David Jander <david@protonic.nl>
The USB480M clock can source from a MUX that selects the clock to come
from either of the USB-phy internal 480MHz PLLs. These clocks are
provided by the USB phy driver.
Signed-off-by: David Jander <david@protonic.nl>
Link: https://lore.kernel.org/r/20240404-clk-rockchip-rk3568-add-usb480m-phy-mux-v1-1-e8542afd58b9@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/rockchip/clk-rk3568.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 8cb21d10beca2..2d44bcaef046b 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -215,6 +215,7 @@ static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
+PNAME(mux_usb480m_phy_p) = { "clk_usbphy0_480m", "clk_usbphy1_480m"};
PNAME(mux_armclk_p) = { "apll", "gpll" };
PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
@@ -485,6 +486,9 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
RK3568_MODE_CON0, 14, 2, MFLAGS),
+ MUX(USB480M_PHY, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
+ RK3568_MISC_CON2, 15, 1, MFLAGS),
+
/* PD_CORE */
COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
--
2.39.2
^ permalink raw reply related
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