* [PATCH 3/4] arm64: dts: qcom: Add Motorola Moto E 2015 LTE (surnia)
From: Nikita Travkin @ 2024-04-05 14:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Nikita Travkin,
Wiktor Strzębała, Valérie Roux, Stephan Gerhold
In-Reply-To: <20240405-msm8916-moto-init-v1-0-502b58176d34@trvn.ru>
From: Wiktor Strzębała <wiktorek140@gmail.com>
Motorola Moto E 2015 LTE is an msm8916 based smartphone.
Supported features:
- eMMC and SD;
- Buttons;
- Touchscreen;
- USB;
- Fuel Gauge;
- Sound.
Signed-off-by: Wiktor Strzębała <wiktorek140@gmail.com>
[Valérie: Sound and modem]
Co-developed-by: Valérie Roux <undev@unixgirl.xyz>
Signed-off-by: Valérie Roux <undev@unixgirl.xyz>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
[Nikita: Use common dtsi]
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/msm8916-motorola-surnia.dts | 83 ++++++++++++++++++++++
2 files changed, 84 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 8d3fc7cb7a4d..acf3ee316fba 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-harpia.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-surnia.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb
diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts b/arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts
new file mode 100644
index 000000000000..eecf78ba45bb
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8916-motorola-common.dtsi"
+
+/ {
+ model = "Motorola Moto E 2015 LTE";
+ compatible = "motorola,surnia", "qcom,msm8916";
+ chassis-type = "handset";
+};
+
+&blsp_i2c4 {
+ status = "okay";
+
+ battery@36 {
+ compatible = "maxim,max17050";
+ reg = <0x36>;
+
+ interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&battery_alert_default>;
+ pinctrl-names = "default";
+
+ maxim,rsns-microohm = <10000>;
+ maxim,over-heat-temp = <600>;
+ maxim,cold-temp = <(-200)>;
+ maxim,dead-volt = <3200>;
+ maxim,over-volt = <4500>;
+
+ };
+};
+
+&pm8916_codec {
+ qcom,micbias1-ext-cap;
+ qcom,micbias2-ext-cap;
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+};
+
+&sound {
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC3", "MIC BIAS External1";
+};
+
+&touchscreen {
+ interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&pm8916_l16>;
+
+ pinctrl-0 = <&ts_int_default>;
+ pinctrl-names = "default";
+};
+
+&tlmm {
+ battery_alert_default: battery-alert-default-state {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sdc2_cd_default: sdc2-cd-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts_int_default: ts-int-default-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
--
2.44.0
^ permalink raw reply related
* [PATCH 4/4] arm64: dts: qcom: Add Motorola Moto G 2015 (osprey)
From: Nikita Travkin @ 2024-04-05 14:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Nikita Travkin,
Martijn Braam, Stephan Gerhold
In-Reply-To: <20240405-msm8916-moto-init-v1-0-502b58176d34@trvn.ru>
From: Martijn Braam <martijn@brixit.nl>
Motorola Moto G 2015 is an msm8916 based smartphone.
Supported features:
- eMMC and SD;
- Buttons;
- Touchscreen;
- USB;
- Fuel Gauge;
- Sound.
Signed-off-by: Martijn Braam <martijn@brixit.nl>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
[Nikita: Use common dtsi]
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/msm8916-motorola-osprey.dts | 105 +++++++++++++++++++++
2 files changed, 106 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index acf3ee316fba..ff23afb1b0db 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-harpia.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-osprey.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-surnia.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts b/arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts
new file mode 100644
index 000000000000..ec5589fc69bd
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8916-motorola-common.dtsi"
+
+/ {
+ model = "Motorola Moto G 2015";
+ compatible = "motorola,osprey", "qcom,msm8916";
+ chassis-type = "handset";
+
+ reg_touch_vdda: regulator-touch-vdda {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_vdda";
+ gpio = <&tlmm 114 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-0 = <&touch_vdda_default>;
+ pinctrl-names = "default";
+ startup-delay-us = <300>;
+ vin-supply = <&pm8916_l16>;
+ };
+};
+
+&blsp_i2c1 {
+ status = "okay";
+
+ battery@36 {
+ compatible = "maxim,max17050";
+ reg = <0x36>;
+
+ interrupts-extended = <&tlmm 49 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&battery_alert_default>;
+ pinctrl-names = "default";
+
+ maxim,rsns-microohm = <10000>;
+ maxim,over-heat-temp = <600>;
+ maxim,cold-temp = <(-200)>;
+ maxim,dead-volt = <3200>;
+ maxim,over-volt = <4500>;
+
+ };
+};
+
+&blsp_i2c6 {
+ /* magnetometer@c */
+};
+
+&pm8916_codec {
+ qcom,micbias1-ext-cap;
+ qcom,micbias2-ext-cap;
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+};
+
+&sound {
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC3", "MIC BIAS External1";
+};
+
+&touchscreen {
+ interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <®_touch_vdda>;
+
+ pinctrl-0 = <&ts_int_default>;
+ pinctrl-names = "default";
+};
+
+&tlmm {
+ battery_alert_default: battery-alert-default-state {
+ pins = "gpio49";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sdc2_cd_default: sdc2-cd-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts_int_default: ts-int-default-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ touch_vdda_default: touch-vdda-default-state {
+ pins = "gpio114";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
--
2.44.0
^ permalink raw reply related
* Re: [PATCH v8 1/4] ASoc: PCM6240: Create PCM6240 Family driver code
From: Mark Brown @ 2024-04-05 14:09 UTC (permalink / raw)
To: Shenghao Ding
Cc: linux-kernel, lgirdwood, robh+dt, krzysztof.kozlowski+dt,
conor+dt, linux-sound, devicetree, perex, tiwai, 13916275206,
mohit.chawla, soyer, jkhuang3, tiwai, pdjuandi, manisha.agrawal,
aviel, hnagalla, praneeth, Baojun.Xu
In-Reply-To: <20240403003159.389-2-shenghao-ding@ti.com>
[-- Attachment #1: Type: text/plain, Size: 1759 bytes --]
On Wed, Apr 03, 2024 at 08:31:55AM +0800, Shenghao Ding wrote:
> +static const char *const pcmdev_ctrl_name[] = {
> + "%s-i2c-%d-dev%d-ch%d-ana-gain",
> + "%s-i2c-%d-dev%d-ch%d-digi-gain",
> + "%s-i2c-%d-dev%d-ch%d-fine-gain",
> +};
> +
> +static const char *const pcmdev_ctrl_name_with_prefix[] = {
> + "%s-dev%d-ch%d-ana-gain",
> + "%s-dev%d-ch%d-digi-gain",
> + "%s-dev%d-ch%d-fine-gain",
> +};
These still don't look like idiomatic ALSA control names, if nothing
else volume controls should end with Volume but the whole all lower case
with -s thing really isn't idiomatic.
> +static int pcmdev_put_volsw(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol, int vol_ctrl_type)
> +{
> + err = pcmdev_dev_update_bits(pcm_dev, dev_no, reg, val_mask, val);
> + if (err) {
> + dev_err(pcm_dev->dev, "%s: update_bits err = %d\n",
> + __func__, err);
> + err = 0;
> + }
Why don't we report errors to users?
> + case PCMDEVICE_CMD_DELAY: {
> + unsigned int delay_time = 0;
> +
> + if (subblk_offset + 2 > sublocksize) {
> + dev_err(pcm_dev->dev,
> + "%s: deley out of boundary\n",
> + __func__);
> + break;
> + }
> + delay_time = get_unaligned_be16(&data[2]) * 1000;
> + usleep_range(delay_time, delay_time + 50);
> + subblk_offset += 2;
> + }
> + break;
> + case PCMDEVICE_CMD_FIELD_W:
> + if (subblk_offset + 6 > sublocksize) {
> + dev_err(pcm_dev->dev,
> + "%s: bit write out of memory\n", __func__);
> + break;
> + }
> + ret = pcmdev_dev_update_bits(pcm_dev, chn,
> + PCMDEVICE_REG(data[subblk_offset + 3],
> + data[subblk_offset + 4]), data[subblk_offset + 1],
> + data[subblk_offset + 5]);
The indentation here is all messed up, things not indented for the case
blocks and so on.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [RESEND v7 21/37] dt-bindings: serial: renesas,scif: Add scif-sh7751.
From: Geert Uytterhoeven @ 2024-04-05 14:02 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, Damien Le Moal, Niklas Cassel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Thomas Gleixner, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Greg Kroah-Hartman,
Jiri Slaby, Magnus Damm, Daniel Lezcano, Rich Felker,
John Paul Adrian Glaubitz, Lee Jones, Helge Deller,
Heiko Stuebner, Shawn Guo, Sebastian Reichel, Chris Morgan,
Linus Walleij, Arnd Bergmann, David Rientjes, Hyeonggon Yoo,
Vlastimil Babka, Baoquan He, Andrew Morton, Guenter Roeck,
Kefeng Wang, Stephen Rothwell, Javier Martinez Canillas, Guo Ren,
Azeem Shaikh, Max Filippov, Jonathan Corbet, Jacky Huang,
Herve Codina, Manikanta Guntupalli, Anup Patel, Biju Das,
Uwe Kleine-König, Sam Ravnborg, Sergey Shtylyov,
Laurent Pinchart, linux-ide, devicetree, linux-kernel,
linux-renesas-soc, linux-clk, dri-devel, linux-pci, linux-serial,
linux-fbdev, Lad, Prabhakar
In-Reply-To: <f3af315d575fbec431bad9bfaf9790450ab31ad9.1712207606.git.ysato@users.sourceforge.jp>
Hi Sato-san,
On Thu, Apr 4, 2024 at 7:15 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Add Renesas SH7751 SCIF.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> @@ -18,6 +18,7 @@ properties:
> - items:
> - enum:
> - renesas,scif-r7s72100 # RZ/A1H
> + - renesas,scif-sh7751 # SH7751
> - const: renesas,scif # generic SCIF compatible UART
>
> - items:
If this is applied after "[PATCH v2 2/2] dt-bindings: serial:
renesas,scif: Validate 'interrupts' and 'interrupt-names'"[1], an extra
"- renesas,scif-sh7751" line should be added to the 4-interrupt section
(below "- renesas,scif-r7s72100").
[1] https://lore.kernel.org/all/20240307114217.34784-3-prabhakar.mahadev-lad.rj@bp.renesas.com/
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 03/18] PCI: endpoint: Introduce pci_epc_mem_map()/unmap()
From: Niklas Cassel @ 2024-04-05 14:10 UTC (permalink / raw)
To: Damien Le Moal
Cc: Manivannan Sadhasivam, Lorenzo Pieralisi, Kishon Vijay Abraham I,
Shawn Lin, Krzysztof Wilczyński, Bjorn Helgaas,
Heiko Stuebner, linux-pci, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, linux-rockchip, linux-arm-kernel,
Rick Wertenbroek, Wilfred Mallawa
In-Reply-To: <20240330041928.1555578-4-dlemoal@kernel.org>
On Sat, Mar 30, 2024 at 01:19:13PM +0900, Damien Le Moal wrote:
> Introduce the function pci_epc_mem_map() to facilitate controller memory
> address allocation and mapping to a RC PCI address region in endpoint
> function drivers.
>
> This function first uses pci_epc_map_align() to determine the controller
> memory address alignment (offset and size) constraints. The result of
> this function is used to allocate a controller physical memory region
> using pci_epc_mem_alloc_addr() and map it to the RC PCI address
> space with pci_epc_map_addr(). Since pci_epc_map_align() may indicate
> that a mapping can be smaller than the requested size, pci_epc_mem_map()
> may only partially map the RC PCI address region specified and return
> a smaller size for the effective mapping.
>
> The counterpart of pci_epc_mem_map() to unmap and free the controller
> memory address region is pci_epc_mem_unmap().
>
> Both functions operate using struct pci_epc_map data structure which is
> extended to contain the physical and virtual addresses of the allocated
> controller memory. Endpoint function drivers can use struct pci_epc_map
> to implement read/write accesses within the mapped RC PCI address region
> using the ->virt_addr and ->size fields.
>
> This commit contains contributions from Rick Wertenbroek
> <rick.wertenbroek@gmail.com>.
>
> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
> ---
> drivers/pci/endpoint/pci-epc-core.c | 68 +++++++++++++++++++++++++++++
> include/linux/pci-epc.h | 6 +++
> 2 files changed, 74 insertions(+)
>
> diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
> index 37758ca91d7f..0095b54bdf9e 100644
> --- a/drivers/pci/endpoint/pci-epc-core.c
> +++ b/drivers/pci/endpoint/pci-epc-core.c
> @@ -530,6 +530,74 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> }
> EXPORT_SYMBOL_GPL(pci_epc_map_addr);
>
> +/**
> + * pci_epc_mem_map() - allocate and map CPU address to PCI address
> + * @epc: the EPC device on which the CPU address is to be allocated and mapped
> + * @func_no: the physical endpoint function number in the EPC device
> + * @vfunc_no: the virtual endpoint function number in the physical function
> + * @pci_addr: PCI address to which the CPU address should be mapped
> + * @size: the number of bytes to map starting from @pci_addr
> + * @map: where to return the mapping information
> + *
> + * Allocate a controller physical address region and map it to a RC PCI address
> + * region, taking into account the controller physical address mapping
> + * constraints (if any). Returns the effective size of the mapping, which may
> + * be less than @size, or a negative error code in case of error.
> + */
> +ssize_t pci_epc_mem_map(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> + u64 pci_addr, size_t size, struct pci_epc_map *map)
> +{
> + int ret;
> +
> + ret = pci_epc_map_align(epc, func_no, vfunc_no, pci_addr, size, map);
> + if (ret)
> + return ret;
> +
> + map->virt_base = pci_epc_mem_alloc_addr(epc, &map->phys_base,
> + map->map_size);
> + if (!map->virt_base)
> + return -ENOMEM;
> +
> + map->phys_addr = map->phys_base + map->map_ofst;
> + map->virt_addr = map->virt_base + map->map_ofst;
> +
> + ret = pci_epc_map_addr(epc, func_no, vfunc_no, map->phys_base,
> + map->map_pci_addr, map->map_size);
> + if (ret) {
> + pci_epc_mem_free_addr(epc, map->phys_base, map->virt_base,
> + map->map_size);
> + return ret;
> + }
> +
> + return map->pci_size;
map->pci_size is of type size_t.
pci_epc_mem_map returns a type of ssize_t.
This means that on ILP32 you will truncate the result, and will only be
able to map a region of max size 2GB.
Could we perhaps change this function to return an int instead?
(0 on success). The mapped size can still be accessed in map->pci_size.
Kind regards,
Niklas
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_mem_map);
> +
> +/**
> + * pci_epc_mem_unmap() - unmap from PCI address and free a CPU address region
> + * @epc: the EPC device on which the CPU address is allocated and mapped
> + * @func_no: the physical endpoint function number in the EPC device
> + * @vfunc_no: the virtual endpoint function number in the physical function
> + * @map: the mapping information
> + *
> + * Allocate and map local CPU address to a PCI address, accounting for the
> + * controller local CPU address alignment constraints.
> + */
> +void pci_epc_mem_unmap(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> + struct pci_epc_map *map)
> +{
> + if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
> + return;
> +
> + if (!map || !map->pci_size)
> + return;
> +
> + pci_epc_unmap_addr(epc, func_no, vfunc_no, map->phys_base);
> + pci_epc_mem_free_addr(epc, map->phys_base, map->virt_base,
> + map->map_size);
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_mem_unmap);
> +
> /**
> * pci_epc_clear_bar() - reset the BAR
> * @epc: the EPC device for which the BAR has to be cleared
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index 8cfb4aaf2628..86397a500b54 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -304,4 +304,10 @@ void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
> phys_addr_t *phys_addr, size_t size);
> void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
> void __iomem *virt_addr, size_t size);
> +
> +ssize_t pci_epc_mem_map(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> + u64 pci_addr, size_t size, struct pci_epc_map *map);
> +void pci_epc_mem_unmap(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> + struct pci_epc_map *map);
> +
> #endif /* __LINUX_PCI_EPC_H */
> --
> 2.44.0
>
^ permalink raw reply
* Re: [PATCH v3 21/25] drivers: media: i2c: imx258: Use macros
From: Tommaso Merciai @ 2024-04-05 14:11 UTC (permalink / raw)
To: Luis Garcia
Cc: Sakari Ailus, linux-media, dave.stevenson, jacopo.mondi, mchehab,
robh, krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, devicetree, imx, linux-arm-kernel, linux-kernel, pavel,
phone-devel, Ondrej Jirman
In-Reply-To: <082190a8-7ac5-4240-9a16-6b9168c67d57@luigi311.com>
Hi Luis,
On Fri, Apr 05, 2024 at 04:33:38AM -0600, Luis Garcia wrote:
> On 4/4/24 00:46, Sakari Ailus wrote:
> > On Wed, Apr 03, 2024 at 01:17:26PM -0600, Luigi311 wrote:
> >> On 4/3/24 10:23, Sakari Ailus wrote:
> >>> Hi Luis,
> >>>
> >>> On Wed, Apr 03, 2024 at 09:03:50AM -0600, git@luigi311.com wrote:
> >>>> From: Luis Garcia <git@luigi311.com>
> >>>>
> >>>> Use understandable macros instead of raw values.
> >>>>
> >>>> Signed-off-by: Ondrej Jirman <megi@xff.cz>
> >>>> Signed-off-by: Luis Garcia <git@luigi311.com>
> >>>> ---
> >>>> drivers/media/i2c/imx258.c | 434 ++++++++++++++++++-------------------
> >>>> 1 file changed, 207 insertions(+), 227 deletions(-)
> >>>>
> >>>> diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
> >>>> index e2ecf6109516..30352c33f63c 100644
> >>>> --- a/drivers/media/i2c/imx258.c
> >>>> +++ b/drivers/media/i2c/imx258.c
> >>>> @@ -33,8 +33,6 @@
> >>>> #define IMX258_VTS_30FPS_VGA 0x034c
> >>>> #define IMX258_VTS_MAX 65525
> >>>>
> >>>> -#define IMX258_REG_VTS 0x0340
> >>>> -
> >>>> /* HBLANK control - read only */
> >>>> #define IMX258_PPL_DEFAULT 5352
> >>>>
> >>>> @@ -90,6 +88,53 @@
> >>>> #define IMX258_PIXEL_ARRAY_WIDTH 4208U
> >>>> #define IMX258_PIXEL_ARRAY_HEIGHT 3120U
> >>>>
> >>>> +/* regs */
> >>>> +#define IMX258_REG_PLL_MULT_DRIV 0x0310
> >>>> +#define IMX258_REG_IVTPXCK_DIV 0x0301
> >>>> +#define IMX258_REG_IVTSYCK_DIV 0x0303
> >>>> +#define IMX258_REG_PREPLLCK_VT_DIV 0x0305
> >>>> +#define IMX258_REG_IOPPXCK_DIV 0x0309
> >>>> +#define IMX258_REG_IOPSYCK_DIV 0x030b
> >>>> +#define IMX258_REG_PREPLLCK_OP_DIV 0x030d
> >>>> +#define IMX258_REG_PHASE_PIX_OUTEN 0x3030
> >>>> +#define IMX258_REG_PDPIX_DATA_RATE 0x3032
> >>>> +#define IMX258_REG_SCALE_MODE 0x0401
> >>>> +#define IMX258_REG_SCALE_MODE_EXT 0x3038
> >>>> +#define IMX258_REG_AF_WINDOW_MODE 0x7bcd
> >>>> +#define IMX258_REG_FRM_LENGTH_CTL 0x0350
> >>>> +#define IMX258_REG_CSI_LANE_MODE 0x0114
> >>>> +#define IMX258_REG_X_EVN_INC 0x0381
> >>>> +#define IMX258_REG_X_ODD_INC 0x0383
> >>>> +#define IMX258_REG_Y_EVN_INC 0x0385
> >>>> +#define IMX258_REG_Y_ODD_INC 0x0387
> >>>> +#define IMX258_REG_BINNING_MODE 0x0900
> >>>> +#define IMX258_REG_BINNING_TYPE_V 0x0901
> >>>> +#define IMX258_REG_FORCE_FD_SUM 0x300d
> >>>> +#define IMX258_REG_DIG_CROP_X_OFFSET 0x0408
> >>>> +#define IMX258_REG_DIG_CROP_Y_OFFSET 0x040a
> >>>> +#define IMX258_REG_DIG_CROP_IMAGE_WIDTH 0x040c
> >>>> +#define IMX258_REG_DIG_CROP_IMAGE_HEIGHT 0x040e
> >>>> +#define IMX258_REG_SCALE_M 0x0404
> >>>> +#define IMX258_REG_X_OUT_SIZE 0x034c
> >>>> +#define IMX258_REG_Y_OUT_SIZE 0x034e
> >>>> +#define IMX258_REG_X_ADD_STA 0x0344
> >>>> +#define IMX258_REG_Y_ADD_STA 0x0346
> >>>> +#define IMX258_REG_X_ADD_END 0x0348
> >>>> +#define IMX258_REG_Y_ADD_END 0x034a
> >>>> +#define IMX258_REG_EXCK_FREQ 0x0136
> >>>> +#define IMX258_REG_CSI_DT_FMT 0x0112
> >>>> +#define IMX258_REG_LINE_LENGTH_PCK 0x0342
> >>>> +#define IMX258_REG_SCALE_M_EXT 0x303a
> >>>> +#define IMX258_REG_FRM_LENGTH_LINES 0x0340
> >>>> +#define IMX258_REG_FINE_INTEG_TIME 0x0200
> >>>> +#define IMX258_REG_PLL_IVT_MPY 0x0306
> >>>> +#define IMX258_REG_PLL_IOP_MPY 0x030e
> >>>> +#define IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H 0x0820
> >>>> +#define IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L 0x0822
> >>>> +
> >>>> +#define REG8(a, v) { a, v }
> >>>> +#define REG16(a, v) { a, ((v) >> 8) & 0xff }, { (a) + 1, (v) & 0xff }
> >>>
> >>> The patch is nice but these macros are better replaced by the V4L2 CCI
> >>> helper that also offers register access functions. Could you add a patch to
> >>> convert the driver to use it (maybe after this one)?
> >>>
> >>
> >> Ohh perfect, using something else would be great. Ill go ahead and see
> >> if I can get that working.
> >
> > Thanks. It may be easier to just do it in this one actually. Up to you.
> >
>
> I've made the swap but looks like its not playing nice with my ppp,
> its causing a crash and showing a call trace as soon as it does its
> first read to check the identity. I went in and dropped the cci_read
> and left it with the original implementation and I'm getting a very
> similar crash with cci_write too so it looks like its not liking
> how I'm implementing it. Looking at the few other drivers that were
> swapped over to use that, I don't seem to be missing anything. It's
> a big change so its not really something I can describe what I've
> changed but I do have the change on my github here
> https://github.com/luigi311/linux/commit/840593acb20eee87ce361e6929edf51eefbbe737
I checked your commit to switch to cci helper.
I think you are missing the right cci regmap initialization.
Please take care to use: devm_cci_regmap_init_i2c
/**
* devm_cci_regmap_init_i2c() - Create regmap to use with cci_*() register
* access functions
*
* @client: i2c_client to create the regmap for
* @reg_addr_bits: register address width to use (8 or 16)
*
* Note the memory for the created regmap is devm() managed, tied to the client.
*
* Return: %0 on success or a negative error code on failure.
*/
Check drivers/media/i2c/imx290.c:1530
Hope this help :)
Note:
Somewhere into the github commit you are reading 16bit reg and storing
that into 64bit val. Take care! :)
Thanks & Regards,
Tommaso
> if you can provide some guidance, if not I can skip this change
> all together and we can do a separate attempt at swapping over to it.
>
^ permalink raw reply
* Re: [PATCH v4 5/7] PCI: dwc: rcar-gen4: Add .ltssm_enable() for other SoC support
From: Geert Uytterhoeven @ 2024-04-05 14:13 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
In-Reply-To: <20240403053304.3695096-6-yoshihiro.shimoda.uh@renesas.com>
Hi Shimoda-san,
On Wed, Apr 3, 2024 at 7:33 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> This driver can reuse other R-Car Gen4 SoCs support like r8a779g0 and
> r8a779h0. However, r8a779g0 and r8a779h0 require other initializing
> settings that differ than r8a779f0. So, add a new function pointer
> .ltssm_enable() for it. No behavior changes.
>
> After applied this patch, probing SoCs by rcar_gen4_pcie_of_match[]
> will be changed like below:
>
> - r8a779f0 as "renesas,r8a779f0-pcie" and "renesas,r8a779f0-pcie-ep"
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks for your patch!
> --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -513,6 +536,14 @@ static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie_ep = {
> };
>
> static const struct of_device_id rcar_gen4_pcie_of_match[] = {
> + {
> + .compatible = "renesas,r8a779f0-pcie",
> + .data = &platdata_r8a779f0_pcie,
> + },
> + {
> + .compatible = "renesas,r8a779f04-pcie-ep",
renesas,r8a779f0-pcie-ep
> + .data = &platdata_r8a779f0_pcie_ep,
> + },
> {
> .compatible = "renesas,rcar-gen4-pcie",
> .data = &platdata_rcar_gen4_pcie,
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v15 2/8] phy: Add HDMI configuration options
From: Vinod Koul @ 2024-04-05 14:24 UTC (permalink / raw)
To: Maxime Ripard
Cc: Alexander Stein, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, David Airlie,
Daniel Vetter, Maarten Lankhorst, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kishon Vijay Abraham I,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Sandor Yu, dri-devel, devicetree, linux-kernel, linux-phy, imx,
linux-arm-kernel, linux, Dmitry Baryshkov
In-Reply-To: <20240306-inquisitive-funny-bull-017550@houat>
On 06-03-24, 15:48, Maxime Ripard wrote:
> Hi Alexander,
>
> On Wed, Mar 06, 2024 at 11:16:19AM +0100, Alexander Stein wrote:
> > From: Sandor Yu <Sandor.yu@nxp.com>
> >
> > Allow HDMI PHYs to be configured through the generic
> > functions through a custom structure added to the generic union.
> >
> > The parameters added here are based on HDMI PHY
> > implementation practices. The current set of parameters
> > should cover the potential users.
> >
> > Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Acked-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > include/linux/phy/phy-hdmi.h | 24 ++++++++++++++++++++++++
> > include/linux/phy/phy.h | 7 ++++++-
> > 2 files changed, 30 insertions(+), 1 deletion(-)
> > create mode 100644 include/linux/phy/phy-hdmi.h
> >
> > diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h
> > new file mode 100644
> > index 0000000000000..b7de88e9090f0
> > --- /dev/null
> > +++ b/include/linux/phy/phy-hdmi.h
> > @@ -0,0 +1,24 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright 2022 NXP
> > + */
> > +
> > +#ifndef __PHY_HDMI_H_
> > +#define __PHY_HDMI_H_
> > +
> > +#include <linux/hdmi.h>
> > +/**
> > + * struct phy_configure_opts_hdmi - HDMI configuration set
> > + * @pixel_clk_rate: Pixel clock of video modes in KHz.
> > + * @bpc: Maximum bits per color channel.
> > + * @color_space: Colorspace in enum hdmi_colorspace.
> > + *
> > + * This structure is used to represent the configuration state of a HDMI phy.
> > + */
> > +struct phy_configure_opts_hdmi {
> > + unsigned int pixel_clk_rate;
> > + unsigned int bpc;
> > + enum hdmi_colorspace color_space;
> > +};
>
> Does the PHY actually care about the pixel clock rate, color space and
> formats, or does it only care about the character rate?
Nope it should not
--
~Vinod
^ permalink raw reply
* Re: [RESEND v7 13/37] dt-bindings: clock: sh7750-cpg: Add renesas,sh7750-cpg header.
From: Geert Uytterhoeven @ 2024-04-05 12:40 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, Damien Le Moal, Niklas Cassel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Thomas Gleixner, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Greg Kroah-Hartman,
Jiri Slaby, Magnus Damm, Daniel Lezcano, Rich Felker,
John Paul Adrian Glaubitz, Lee Jones, Helge Deller,
Heiko Stuebner, Shawn Guo, Sebastian Reichel, Chris Morgan,
Linus Walleij, Arnd Bergmann, David Rientjes, Hyeonggon Yoo,
Vlastimil Babka, Baoquan He, Andrew Morton, Guenter Roeck,
Kefeng Wang, Stephen Rothwell, Javier Martinez Canillas, Guo Ren,
Azeem Shaikh, Max Filippov, Jonathan Corbet, Jacky Huang,
Herve Codina, Manikanta Guntupalli, Anup Patel, Biju Das,
Uwe Kleine-König, Sam Ravnborg, Sergey Shtylyov,
Laurent Pinchart, linux-ide, devicetree, linux-kernel,
linux-renesas-soc, linux-clk, dri-devel, linux-pci, linux-serial,
linux-fbdev
In-Reply-To: <1db8627e4ca50b9d2d27e95d245518cac1cd62dc.1712207606.git.ysato@users.sourceforge.jp>
Hi Sato-san,
Thanks for the update!
On Thu, Apr 4, 2024 at 7:15 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
>
> SH7750 CPG Clock output define.
(from my comments on v6) Please improve the patch description.
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> index 000000000000..04c10b0834ee
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
The actual bindings LGTM.
> +examples:
> + - |
> + #include <dt-bindings/clock/sh7750-cpg.h>
> + cpg: clock-controller@ffc00000 {
> + #clock-cells = <1>;
> + #power-domain-cells = <0>;
> + compatible = "renesas,sh7751r-cpg";
> + clocks = <&extal>;
> + clock-names = "extal";
> + reg = <0xffc00000 20>, <0xfe0a0000 16>;
> + reg-names = "FRQCR", "CLKSTP00";
> + renesas,mode = <0>;
> + };
Please read
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 0/2] Enable JPEG encoding on rk3588
From: Link Mauve @ 2024-04-05 14:21 UTC (permalink / raw)
To: Nicolas Dufresne
Cc: Emmanuel Gil Peyrot, linux-kernel, Ezequiel Garcia, Philipp Zabel,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Joerg Roedel, Will Deacon,
Robin Murphy, Sebastian Reichel, Cristian Ciocaltea, Dragan Simic,
Shreeya Patel, Chris Morgan, Andy Yan, Nicolas Frattaroli,
linux-media, linux-rockchip, devicetree, linux-arm-kernel, iommu
In-Reply-To: <bbcb66e9499120a86b367e7abdac2d8e2e704bfb.camel@ndufresne.ca>
On Thu, Apr 04, 2024 at 01:41:15PM -0400, Nicolas Dufresne wrote:
> Hi,
Hi,
>
> Le mercredi 27 mars 2024 à 14:41 +0100, Emmanuel Gil Peyrot a écrit :
> > Only the JPEG encoder is available for now, although there are patches
> > for the undocumented VP8 encoder floating around[0].
>
> [0] seems like a broken link. The VP8 encoder RFC is for RK3399 (and Hantro H1
> posted by ST more recently). The TRM says "VEPU121(JPEG encoder only)", which
> suggest that the H.264 and VP8 encoders usually found on the VEPU121 are
> removed. As Rockchip have remove the synthesize register while modifying the H1
> IP, it is difficult to verify. Confusingly the H.264 specific registers are
> documented in the TRM around VEPU121.
Ah, the link became, and was indeed ST’s series:
https://patchwork.kernel.org/project/linux-rockchip/list/?series=789885&archive=both
But the TRM part 1 says the VEPU121 supports H.264 encoding (page 367),
and it’s likely they didn’t remove just VP8 support since the codec
features are pretty close to H.264’s.
>
> >
> > This has been tested on a rock-5b, resulting in four /dev/video*
> > encoders. The userspace program I’ve been using to test them is
> > Onix[1], using the jpeg-encoder example, it will pick one of these four
> > at random (but displays the one it picked):
> > % ffmpeg -i <input image> -pix_fmt yuvj420p temp.yuv
> > % jpeg-encoder temp.yuv <width> <height> NV12 <quality> output.jpeg
>
> I don't like that we exposing each identical cores a separate video nodes. I
> think we should aim for 1 device, and then multi-plex and schedule de cores from
> inside the Linux kernel.
I agree, but this should be handled in the driver not in the device
tree, and it can be done later.
>
> Not doing this now means we'll never have an optimal hardware usage
> distribution. Just consider two userspace software wanting to do jpeg encoding.
> If they both take a guess, they may endup using a single core. Where with proper
> scheduling in V4L2, the kernel will be able to properly distribute the load. I
> insist on this, since if we merge you changes it becomes an ABI and we can't
> change it anymore.
Will it really become ABI just like that? Userspace should always
discover the video nodes and their capabilities and not hardcode e.g. a
specific /dev/videoN file for a specific codec. I would argue that this
series would let userspace do JPEG encoding right away, even if in a
less optimal way than if the driver would round-robin them through a
single video node, but that can always be added in a future version.
>
> I understand that this impose a rework of the mem2mem framework so that we can
> run multiple jobs, but this will be needed anyway on RK3588, since the rkvdec2,
> which we don't have a driver yet is also multi-core, but you need to use 2 cores
> when the resolution is close to 8K.
I think the mediatek JPEG driver already supports that, would it be ok
to do it the same way?
>
> Nicolas
>
> >
> > [0] https://patchwork.kernel.org/project/linux-rockchip/list/?series=789885
> > [1] https://crates.io/crates/onix
> >
> > Changes since v1:
> > - Dropped patches 1 and 4.
> > - Use the proper compatible form, since this device should be fully
> > compatible with the VEPU of rk356x.
> > - Describe where the VEPU121 name comes from, and list other encoders
> > and decoders present in this SoC.
> > - Properly test the device tree changes, I previously couldn’t since I
> > was using a too recent version of python-jsonschema…
> >
> > Emmanuel Gil Peyrot (2):
> > media: dt-binding: media: Document rk3588’s VEPU121
> > arm64: dts: rockchip: Add VEPU121 to rk3588
> >
> > .../bindings/media/rockchip,rk3568-vepu.yaml | 8 +-
> > arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++
> > 2 files changed, 86 insertions(+), 2 deletions(-)
> >
>
--
Link Mauve
^ permalink raw reply
* Re: [PATCH v5 5/5] PCI: dwc: Add common send PME_Turn_Off message method
From: Frank Li @ 2024-04-05 14:31 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Bjorn Helgaas, Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, imx, linux-pci, linux-kernel, devicetree
In-Reply-To: <20240405062426.GB2953@thinkpad>
On Fri, Apr 05, 2024 at 11:54:26AM +0530, Manivannan Sadhasivam wrote:
> On Tue, Mar 19, 2024 at 12:07:15PM -0400, Frank Li wrote:
>
> PCI: dwc: Add generic MSG TLP support for sending PME_Turn_Off during system suspend
>
> > Reserve space at end of first IORESOURCE_MEM window as message TLP MMIO
> > window. This space's size is 'region_align'.
> >
> > Set outbound ATU map memory write to send PCI message. So one MMIO write
> > can trigger a PCI message, such as PME_Turn_Off.
> >
> > Add common dwc_pme_turn_off() function.
> >
> > Call dwc_pme_turn_off() to send out PME_Turn_Off message in general
> > dw_pcie_suspend_noirq() if there are not platform callback pme_turn_off()
> > exist.
> >
>
> How about:
>
> "Instead of relying on the vendor specific implementations to send the
> PME_Turn_Off message, let's introduce a generic way of sending the message using
> the MSG TLP.
>
> This is achieved by reserving a region for MSG TLP of size 'pci->region_align',
> at the end of the first IORESOURCE_MEM window of the host bridge. And then
> sending the PME_Turn_Off message during system suspend with the help of iATU.
>
> It should be noted that this generic implementation is optional for the glue
> drivers and can be overridden by a custom 'pme_turn_off' callback."
>
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pcie-designware-host.c | 94 ++++++++++++++++++++++-
> > drivers/pci/controller/dwc/pcie-designware.h | 3 +
> > 2 files changed, 93 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> > index 267687ab33cbc..d5723fce7a894 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > @@ -393,6 +393,31 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
> > return 0;
> > }
> >
> > +static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
> > +{
> > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > + struct resource_entry *win;
> > + struct resource *res;
> > +
> > + win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
> > + if (win) {
> > + res = devm_kzalloc(pci->dev, sizeof(*res), GFP_KERNEL);
> > + if (!res)
> > + return;
> > +
> > + /* Reserve last region_align block as message TLP space */
> > + res->start = win->res->end - pci->region_align + 1;
> > + res->end = win->res->end;
>
> Don't you need to adjust the host bridge window size and end address?
Needn't. request_resource will reserve it from bridge window. Like malloc,
if you malloc to get a region of memory, which will never get by malloc
again utill you call free.
>
> > + res->name = "msg";
> > + res->flags = win->res->flags | IORESOURCE_BUSY;
> > +
>
> Shouldn't this resource be added back to the host bridge?
No, this resource will reserver for msg only for whole bridge life cycle.
Genenally alloc resource only happen at PCI devices probe. All pci space
will be fixed after system probe.
>
> > + if (!request_resource(win->res, res))
>
> Why can't you use devm_ helper to manage the resource, since the lifetime of the
> resource is till dw_pcie_host_deinit()?
>
> > + pp->msg_res = res;
> > + else
> > + devm_kfree(pci->dev, res);
> > + }
> > +}
> > +
> > int dw_pcie_host_init(struct dw_pcie_rp *pp)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > @@ -479,6 +504,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> >
> > dw_pcie_iatu_detect(pci);
> >
> > + /* Need call after dw_pcie_iatu_detect() before dw_pcie_setup_rc() */
>
> It'd be better to add the reason also i.,e
>
> /*
> * Allocate the resource for MSG TLP before programming the iATU
> * outbound window in dw_pcie_setup_rc(). Since the allocation depends
> * on the value of 'region_align', this has to be done after
> * dw_pcie_iatu_detect().
> */
>
> > + if (pp->use_atu_msg)
>
> Who is setting this flag?
>
> > + dw_pcie_host_request_msg_tlp_res(pp);
> > +
> > ret = dw_pcie_edma_detect(pci);
> > if (ret)
> > goto err_free_msi;
> > @@ -536,6 +565,11 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
> >
> > dw_pcie_edma_remove(pci);
> >
> > + if (pp->msg_res) {
> > + release_resource(pp->msg_res);
> > + devm_kfree(pci->dev, pp->msg_res);
> > + }
> > +
> > if (pp->has_msi_ctrl)
> > dw_pcie_free_msi(pp);
> >
> > @@ -697,6 +731,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > atu.pci_addr = entry->res->start - entry->offset;
> > atu.size = resource_size(entry->res);
> >
> > + /* MSG TLB window resource reserve at one of end of IORESOURCE_MEM resource */
> > + if (pp->msg_res && pp->msg_res->parent == entry->res)
> > + atu.size -= resource_size(pp->msg_res);
>
> If you adjust the bridge window above, then this won't be needed.
>
> > +
> > ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > if (ret) {
> > dev_err(pci->dev, "Failed to set MEM range %pr\n",
> > @@ -728,6 +766,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
> > pci->num_ob_windows);
> >
> > + pp->msg_atu_index = i;
> > +
> > i = 0;
> > resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
> > if (resource_type(entry->res) != IORESOURCE_MEM)
> > @@ -833,11 +873,54 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
> > }
> > EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
> >
> > +/* Using message outbound ATU to send out PME_Turn_Off message for dwc PCIe controller */
> > +static int dw_pcie_pme_turn_off(struct dw_pcie *pci)
> > +{
> > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > + void __iomem *m;
>
> *mem
>
> > + int ret;
> > +
> > + if (pci->num_ob_windows <= pci->pp.msg_atu_index)
> > + return -EINVAL;
> > +
> > + if (!pci->pp.msg_res)
> > + return -EINVAL;
> > +
> > + atu.code = PCIE_MSG_CODE_PME_TURN_OFF;
> > + atu.routing = PCIE_MSG_TYPE_R_BC;
> > + atu.type = PCIE_ATU_TYPE_MSG;
> > + atu.size = resource_size(pci->pp.msg_res);
> > + atu.index = pci->pp.msg_atu_index;
> > +
> > + if (!atu.size) {
> > + dev_dbg(pci->dev,
> > + "atu memory map windows is zero, please check 'msg' reg in dts\n");
>
> You are already checking the existence of the 'pci->pp.msg_res' region above. So
> shouldn't that be sufficient enough? Can the size be 0, if the region exist?
>
> - Mani
>
> > + return -ENOMEM;
> > + }
> > +
> > + atu.cpu_addr = pci->pp.msg_res->start;
> > +
> > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > + if (ret)
> > + return ret;
> > +
> > + m = ioremap(atu.cpu_addr, pci->region_align);
> > + if (!m)
> > + return -ENOMEM;
> > +
> > + /* A dummy write is converted to a Msg TLP */
> > + writel(0, m);
> > +
> > + iounmap(m);
> > +
> > + return 0;
> > +}
> > +
> > int dw_pcie_suspend_noirq(struct dw_pcie *pci)
> > {
> > u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > u32 val;
> > - int ret;
> > + int ret = 0;
> >
> > /*
> > * If L1SS is supported, then do not put the link into L2 as some
> > @@ -849,10 +932,13 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
> > if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT)
> > return 0;
> >
> > - if (!pci->pp.ops->pme_turn_off)
> > - return 0;
> > + if (pci->pp.ops->pme_turn_off)
> > + pci->pp.ops->pme_turn_off(&pci->pp);
> > + else
> > + ret = dw_pcie_pme_turn_off(pci);
> >
> > - pci->pp.ops->pme_turn_off(&pci->pp);
> > + if (ret)
> > + return ret;
> >
> > ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
> > PCIE_PME_TO_L2_TIMEOUT_US/10,
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 703b50bc5e0f1..dca5de4c6e877 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -341,6 +341,9 @@ struct dw_pcie_rp {
> > struct pci_host_bridge *bridge;
> > raw_spinlock_t lock;
> > DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
> > + bool use_atu_msg;
> > + int msg_atu_index;
> > + struct resource *msg_res;
> > };
> >
> > struct dw_pcie_ep_ops {
> >
> > --
> > 2.34.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* Re: [PATCH v5 02/10] dt-bindings: mailbox: Add mboxes property for CMDQ secure driver
From: Jason-JH Lin (林睿祥) @ 2024-04-05 14:33 UTC (permalink / raw)
To: conor@kernel.org
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
Houlong Wei (魏厚龙),
devicetree@vger.kernel.org, Shawn Sung (宋孝謙),
CK Hu (胡俊光), conor+dt@kernel.org,
robh@kernel.org, linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
jassisinghbrar@gmail.com, angelogioacchino.delregno@collabora.com
In-Reply-To: <20240404-lankiness-devouring-d4d012b22cb9@spud>
On Thu, 2024-04-04 at 15:52 +0100, Conor Dooley wrote:
> On Thu, Apr 04, 2024 at 04:31:06AM +0000, Jason-JH Lin (林睿祥) wrote:
> > Hi Conor,
> >
> > Thanks for the reviews.
> >
> > On Wed, 2024-04-03 at 16:46 +0100, Conor Dooley wrote:
> > > On Wed, Apr 03, 2024 at 06:25:54PM +0800, Shawn Sung wrote:
> > > > From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
> > > >
> > > > Add mboxes to define a GCE loopping thread as a secure irq
> > > > handler.
> > > > This property is only required if CMDQ secure driver is
> > > > supported.
> > > >
> > > > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> > > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > > ---
> > > > .../bindings/mailbox/mediatek,gce-mailbox.yaml | 10
> > > > ++++++++++
> > > > 1 file changed, 10 insertions(+)
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/mailbox/mediatek,gce-
> > > > mailbox.yaml
> > > > b/Documentation/devicetree/bindings/mailbox/mediatek,gce-
> > > > mailbox.yaml
> > > > index cef9d76013985..c0d80cc770899 100644
> > > > --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-
> > > > mailbox.yaml
> > > > +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-
> > > > mailbox.yaml
> > > > @@ -49,6 +49,16 @@ properties:
> > > > items:
> > > > - const: gce
> > > >
> > > > + mediatek,gce-events:
> > > > + description:
> > > > + The event id which is mapping to the specific hardware
> > > > event
> > > > signal
> > > > + to gce. The event id is defined in the gce header
> > > > + include/dt-bindings/gce/<chip>-gce.h of each chips.
> > >
> > > Missing any info here about when this should be used, hint - you
> > > have
> > > it
> > > in the commit message.
> > >
> > > > + $ref: /schemas/types.yaml#/definitions/uint32-arrayi
> > >
> > > Why is the ID used by the CMDQ service not fixed for each SoC?
> > >
> >
> > I forgot to sync with Shawn about this:
> > https://lore.kernel.org/all/20240124011459.12204-1-jason-
> > jh.lin@mediatek.com
> >
> > I'll fix it at the next version.
>
> When I say "fixed" I don't mean "this is wrong, please fix it", I
> mean
> "why is the value not static for a particular SoC". This needs to be
> explained in the patch (and the description for the event here needs
> to
> explain what the gce-mailbox is reserving an event for).
>
Oh, I see. Thanks for noticing me.
We do want to reserve a static event ID for gce-mailbox to different
SoCs. There are 2 mainly reasons to why we set it in DTS:
1. There are 1024 events IDs for GCE to use to execute instructions in
the specific event happened. These events could be signaled by HW or SW
and their value would be different in different SoC because of HW event
IDs distribution range from 0 to 1023.
If we set a static event ID: 855 for mt8188, it might be conflict the
event ID original set in mt8195.
2. If we defined the event ID in DTS, we might know how many SW or HW
event IDs are used.
If someone wants to use a new event ID for a new feature, they could
find out the used event IDs in DTS easily and avoid the event ID
conflicting.
The reason why we define a event ID is we want to get a SW signal from
secure world. We design a GCE looping thread in gce-mailbox driver to
wait for the GCE execute done event for each cmdq secure packets from
secure world.
Regards,
Jason-JH.Lin
> Thanks,
> Conor.
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: add description for solidrun cn9130 som and clearfog boards
From: Josua Mayer @ 2024-04-05 14:36 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring
Cc: Yazan Shhady, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <84bf0db5-856a-401b-8225-fd62f381beb6@linaro.org>
Hi Krzysztof,
Am 05.04.24 um 09:05 schrieb Krzysztof Kozlowski:
> On 04/04/2024 17:35, Josua Mayer wrote:
>> Add description for the SolidRun CN9130 SoM, and Clearfog Base / Pro
>> reference boards.
>>
>> The SoM has been designed as a pin-compatible replacement for the older
>> Armada 388 based SoM. Therefore it supports the same boards and a
>> similar feature set.
>>
>> Most notable upgrades:
>> - 4x Cortex-A72
>> - 10Gbps SFP
>> - Both eMMC and SD supported at the same time
>>
>> The developer first supporting this product at SolidRun decided to use
>> different filenames for the DTBs: Armada 388 uses the full
>> "clearfog" string while cn9130 uses the abbreviation "cf".
>> This name is already hard-coded in pre-installed vendor u-boot and can
>> not be changed easily.
>>
>> NOTICE IN CASE ANYBODY WANTS TO SELF-UPGRADE:
>> CN9130 SoM has a different footprint from Armada 388 SoM.
>> Components on the carrier board below the SoM may collide causing
>> damage, such as on Clearfog Base.
>>
>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>> ---
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Thanks!
Meanwhile I found two instances of status-property in wrong place,
and also some small changes I prefer to make for v3
(discovered while working on cn9131 board).
Do you prefer in this case to drop your review tag,
or alternatively to keep it, but add separate patch in v3?
^ permalink raw reply
* Re: [PATCH 1/1] arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960/wm8962 and sai[0,1,4,5]
From: Frank Li @ 2024-04-05 14:46 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
In-Reply-To: <efc9c624-6a31-4299-a604-8aad1d0cd878@linaro.org>
On Fri, Apr 05, 2024 at 08:41:59AM +0200, Krzysztof Kozlowski wrote:
> On 04/04/2024 18:19, Frank Li wrote:
> > imx8qxp-mek use two kind audio codec, wm8960 and wm8962. Using dummy gpio
> > i2c bus mux to connect both i2c devices. One will probe failure and other
> > will probe success when devices driver check whoami. So one dtb can cover
> > both board configuration.
>
> I don't understand it. Either you add real device or not. If one board
> has two devices, then why do you need to check for failures?
>
> Anyway, don't add fake stuff to DTS.
NAK can't resolve the problem. It should be common problem for long time
cycle boards. Some chipes will be out life cycle. such as some sensor. So
chips on boards have been replace by some pin to pin compatible sensor. For
example:
old boards: use sensor A with address 0x1a
new bench: use sensor B with address 0x1b.
You can treat it as two kind boards, RevA or RevB. But most user want to
use one dtb to handle such small differences. For this case, it should be
simple. Just add a super set.
i2c
{
sensorA@1a
{
}
sensorB@1b
{
}
}
It also depend on whoami check by i2c devices. Only A or B will probe.
wm8960 and wm8962 are more complex example. wm8960 is out of life. But
wm8962 and wm8960 have the same i2c address. The current i2c frame can't
allow the same i2c address in one i2c bus.
You are feel to NAK my method, but I hope you also provide constructive
solution to help resolve the problem.
Frank
>
> NAK.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 210 ++++++++++++++++++
> > 1 file changed, 210 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > index 8360bb851ac03..adff87c7cf305 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > @@ -30,6 +30,13 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
> > enable-active-high;
> > };
> >
> > + reg_audio: regulator-wm8962 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "3v3_aud";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + };
> > +
> > gpio-sbu-mux {
> > compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
> > pinctrl-names = "default";
> > @@ -44,6 +51,105 @@ usb3_data_ss: endpoint {
> > };
> > };
> > };
> > +
> > + sound-wm8960 {
> > + compatible = "fsl,imx-audio-wm8960";
> > + model = "wm8960-audio";
> > + audio-cpu = <&sai1>;
> > + audio-codec = <&wm8960>;
> > + hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
> > + audio-routing =
> > + "Headphone Jack", "HP_L",
> > + "Headphone Jack", "HP_R",
> > + "Ext Spk", "SPK_LP",
> > + "Ext Spk", "SPK_LN",
> > + "Ext Spk", "SPK_RP",
> > + "Ext Spk", "SPK_RN",
> > + "LINPUT1", "Mic Jack",
> > + "Mic Jack", "MICB";
> > + };
> > +
> > + sound-wm8962 {
> > + compatible = "fsl,imx-audio-wm8962";
> > + model = "wm8962-audio";
> > + audio-cpu = <&sai1>;
> > + audio-codec = <&wm8962>;
> > + hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
> > + audio-routing =
> > + "Headphone Jack", "HPOUTL",
> > + "Headphone Jack", "HPOUTR",
> > + "Ext Spk", "SPKOUTL",
> > + "Ext Spk", "SPKOUTR",
> > + "AMIC", "MICBIAS",
> > + "IN3R", "AMIC",
> > + "IN1R", "AMIC";
> > + };
> > +
> > + /*
> > + * This dummy i2c mux. GPIO actually will not impact selection. At actual boards, only 1
> > + * device connectted. I2C client driver will check ID when probe. Only matched ID's driver
> > + * probe successfully.
>
> NAK
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: omap-mcpdm: Convert to DT schema
From: Mithil @ 2024-04-05 14:48 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, alsa-devel, devicetree, linux-kernel
In-Reply-To: <78091796-fd0a-42dd-a4da-f7bed3025bf9@linaro.org>
So sorry about the 2nd patch being sent as a new mail, here is a new
patch with the changes as suggested
> Please use subject prefixes matching the subsystem
Changed the patch name to match the folder history.
> Is it your full name?
Fixed it, my apologies.
> Filename like compatible.
Fixed.
> Please open existing bindings and look how it is done there.
Changed it, is it fine now?
> Same problem. Drop useless description but provide maxItems.
Removed descriptions for interrupts and hwmods.
> It does not look like you tested the bindings, at least after quick
> look. Please run `make dt_binding_check`
I did run it and it didnt produce any errors henceforth i submitted
the patch.
> Node names should be generic
Changed as said.
From c24a42724e870822d50ac6857ba9f32d0dce02ae Mon Sep 17 00:00:00 2001
From: Mithil Bavishi <bavishimithil@gmail.com>
Date: Mon, 1 Apr 2024 21:10:15 +0530
Subject: [PATCH v2] dt-bindings: omap-mcpdm: Convert to DT schema
Convert the OMAP4+ McPDM bindings to DT schema.
Signed-off-by: Mithil Bavishi <bavishimithil@gmail.com>
---
.../devicetree/bindings/sound/omap-mcpdm.txt | 30 ----------
.../bindings/sound/ti,omap-mcpdm.yaml | 59 +++++++++++++++++++
2 files changed, 59 insertions(+), 30 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/omap-mcpdm.txt
create mode 100644 Documentation/devicetree/bindings/sound/ti,omap-mcpdm.yaml
diff --git a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt
b/Documentation/devicetree/bindings/sound/omap-mcpdm.txt
deleted file mode 100644
index ff98a0cb5..000000000
--- a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-* Texas Instruments OMAP4+ McPDM
-
-Required properties:
-- compatible: "ti,omap4-mcpdm"
-- reg: Register location and size as an array:
- <MPU access base address, size>,
- <L3 interconnect address, size>;
-- interrupts: Interrupt number for McPDM
-- ti,hwmods: Name of the hwmod associated to the McPDM
-- clocks: phandle for the pdmclk provider, likely <&twl6040>
-- clock-names: Must be "pdmclk"
-
-Example:
-
-mcpdm: mcpdm@40132000 {
- compatible = "ti,omap4-mcpdm";
- reg = <0x40132000 0x7f>, /* MPU private access */
- <0x49032000 0x7f>; /* L3 Interconnect */
- interrupts = <0 112 0x4>;
- interrupt-parent = <&gic>;
- ti,hwmods = "mcpdm";
-};
-
-In board DTS file the pdmclk needs to be added:
-
-&mcpdm {
- clocks = <&twl6040>;
- clock-names = "pdmclk";
- status = "okay";
-};
diff --git a/Documentation/devicetree/bindings/sound/ti,omap-mcpdm.yaml
b/Documentation/devicetree/bindings/sound/ti,omap-mcpdm.yaml
new file mode 100644
index 000000000..4d5d37e98
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ti,omap-mcpdm.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,omap-mcpdm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OMAP McPDM
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ OMAP ALSA SoC DAI driver using McPDM port used by TWL6040
+
+properties:
+ compatible:
+ const: ti,omap4-mcpdm
+
+ reg:
+ description:
+ Register location and size as an array
+ <MPU access base address, size>,
+ <L3 interconnect address, size>;
+
+ interrupts:
+ maxItems: 1
+
+ ti,hwmods:
+ maxItems: 1
+
+ clocks:
+ description: phandle for the pdmclk provider, likely <&twl6040>
+
+ clock-names:
+ description: Must be "pdmclk"
+
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - ti,hwmods
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ mcpdm@0 {
+ compatible = "ti,omap4-mcpdm";
+ reg = <0x40132000 0x7f>, /* MPU private access */
+ <0x49032000 0x7f>; /* L3 Interconnect */
+ interrupts = <0 112 0x4>;
+ interrupt-parent = <&gic>;
+ ti,hwmods = "mcpdm";
+ clocks = <&twl6040>;
+ clock-names = "pdmclk";
+ };
--
2.34.1
Best regards,
Mithil
On Fri, Apr 5, 2024 at 12:28 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 04/04/2024 18:06, Mighty wrote:
> > From: Mithil Bavishi <bavishimithil@gmail.com>
> >
> > Convert the OMAP4+ McPDM bindings to DT schema.
> >
> > Signed-off-by: Mighty <bavishimithil@gmail.com>
>
> This does not match SoB. Can you respond to comments you receive?
>
> Subject: nothing improved.
>
> Rest... also did not improve. so you ignored entire feedback?
>
> This is a friendly reminder during the review process.
>
> It seems my or other reviewer's previous comments were not fully
> addressed. Maybe the feedback got lost between the quotes, maybe you
> just forgot to apply it. Please go back to the previous discussion and
> either implement all requested changes or keep discussing them.
>
> Thank you.
>
> Best regards,
> Krzysztof
>
^ permalink raw reply related
* Re: [PATCH v15 6/8] phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ
From: Vinod Koul @ 2024-04-05 14:52 UTC (permalink / raw)
To: Alexander Stein
Cc: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, David Airlie, Daniel Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kishon Vijay Abraham I,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Sandor Yu, dri-devel, devicetree, linux-kernel, linux-phy, imx,
linux-arm-kernel, linux
In-Reply-To: <20240306101625.795732-7-alexander.stein@ew.tq-group.com>
On 06-03-24, 11:16, Alexander Stein wrote:
> From: Sandor Yu <Sandor.yu@nxp.com>
>
> Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ.
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> DisplayPort or HDMI PHY mode is configured in the driver.
>
> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
> drivers/phy/freescale/Kconfig | 10 +
> drivers/phy/freescale/Makefile | 1 +
> drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1402 ++++++++++++++++++
> 3 files changed, 1413 insertions(+)
> create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c
>
> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> index 853958fb2c063..abacbe8ba8f46 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -35,6 +35,16 @@ config PHY_FSL_IMX8M_PCIE
> Enable this to add support for the PCIE PHY as found on
> i.MX8M family of SOCs.
>
> +config PHY_FSL_IMX8MQ_HDPTX
> + tristate "Freescale i.MX8MQ DP/HDMI PHY support"
> + depends on OF && HAS_IOMEM
> + depends on COMMON_CLK
> + select GENERIC_PHY
> + select CDNS_MHDP_HELPER
> + help
> + Enable this to support the Cadence HDPTX DP/HDMI PHY driver
> + on i.MX8MQ SOC.
> +
> endif
>
> config PHY_FSL_LYNX_28G
> diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
> index cedb328bc4d28..17546a4da840a 100644
> --- a/drivers/phy/freescale/Makefile
> +++ b/drivers/phy/freescale/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_PHY_FSL_IMX8MQ_HDPTX) += phy-fsl-imx8mq-hdptx.o
> obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
> obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
> obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
> diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c
> new file mode 100644
> index 0000000000000..3bf92718f826a
> --- /dev/null
> +++ b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c
> @@ -0,0 +1,1402 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Cadence DP/HDMI PHY driver
> + *
> + * Copyright (C) 2022-2024 NXP Semiconductor, Inc.
> + */
> +#include <asm/unaligned.h>
> +#include <drm/bridge/cdns-mhdp-helper.h>
> +#include <linux/clk.h>
> +#include <linux/kernel.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define ADDR_PHY_AFE 0x80000
> +
> +/* PHY registers */
> +#define CMN_SSM_BIAS_TMR 0x0022
> +#define CMN_PLLSM0_PLLEN_TMR 0x0029
> +#define CMN_PLLSM0_PLLPRE_TMR 0x002a
> +#define CMN_PLLSM0_PLLVREF_TMR 0x002b
> +#define CMN_PLLSM0_PLLLOCK_TMR 0x002c
> +#define CMN_PLLSM0_USER_DEF_CTRL 0x002f
> +#define CMN_PSM_CLK_CTRL 0x0061
> +#define CMN_CDIAG_REFCLK_CTRL 0x0062
> +#define CMN_PLL0_VCOCAL_START 0x0081
> +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084
> +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085
> +#define CMN_PLL0_INTDIV 0x0094
> +#define CMN_PLL0_FRACDIV 0x0095
> +#define CMN_PLL0_HIGH_THR 0x0096
> +#define CMN_PLL0_DSM_DIAG 0x0097
> +#define CMN_PLL0_SS_CTRL2 0x0099
> +#define CMN_ICAL_INIT_TMR 0x00c4
> +#define CMN_ICAL_ITER_TMR 0x00c5
> +#define CMN_RXCAL_INIT_TMR 0x00d4
> +#define CMN_RXCAL_ITER_TMR 0x00d5
> +#define CMN_TXPUCAL_CTRL 0x00e0
> +#define CMN_TXPUCAL_INIT_TMR 0x00e4
> +#define CMN_TXPUCAL_ITER_TMR 0x00e5
> +#define CMN_TXPDCAL_CTRL 0x00f0
> +#define CMN_TXPDCAL_INIT_TMR 0x00f4
> +#define CMN_TXPDCAL_ITER_TMR 0x00f5
> +#define CMN_ICAL_ADJ_INIT_TMR 0x0102
> +#define CMN_ICAL_ADJ_ITER_TMR 0x0103
> +#define CMN_RX_ADJ_INIT_TMR 0x0106
> +#define CMN_RX_ADJ_ITER_TMR 0x0107
> +#define CMN_TXPU_ADJ_CTRL 0x0108
> +#define CMN_TXPU_ADJ_INIT_TMR 0x010a
> +#define CMN_TXPU_ADJ_ITER_TMR 0x010b
> +#define CMN_TXPD_ADJ_CTRL 0x010c
> +#define CMN_TXPD_ADJ_INIT_TMR 0x010e
> +#define CMN_TXPD_ADJ_ITER_TMR 0x010f
> +#define CMN_DIAG_PLL0_FBH_OVRD 0x01c0
> +#define CMN_DIAG_PLL0_FBL_OVRD 0x01c1
> +#define CMN_DIAG_PLL0_OVRD 0x01c2
> +#define CMN_DIAG_PLL0_TEST_MODE 0x01c4
> +#define CMN_DIAG_PLL0_V2I_TUNE 0x01c5
> +#define CMN_DIAG_PLL0_CP_TUNE 0x01c6
> +#define CMN_DIAG_PLL0_LF_PROG 0x01c7
> +#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01c8
> +#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01c9
> +#define CMN_DIAG_PLL0_INCLK_CTRL 0x01ca
> +#define CMN_DIAG_PLL0_PXL_DIVH 0x01cb
> +#define CMN_DIAG_PLL0_PXL_DIVL 0x01cc
> +#define CMN_DIAG_HSCLK_SEL 0x01e0
> +#define CMN_DIAG_PER_CAL_ADJ 0x01ec
> +#define CMN_DIAG_CAL_CTRL 0x01ed
> +#define CMN_DIAG_ACYA 0x01ff
> +#define XCVR_PSM_RCTRL 0x4001
> +#define XCVR_PSM_CAL_TMR 0x4002
> +#define XCVR_PSM_A0IN_TMR 0x4003
> +#define TX_TXCC_CAL_SCLR_MULT_0 0x4047
> +#define TX_TXCC_CPOST_MULT_00_0 0x404c
> +#define XCVR_DIAG_PLLDRC_CTRL 0x40e0
> +#define XCVR_DIAG_HSCLK_SEL 0x40e1
> +#define XCVR_DIAG_BIDI_CTRL 0x40e8
> +#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40f2
> +#define TX_PSC_A0 0x4100
> +#define TX_PSC_A1 0x4101
> +#define TX_PSC_A2 0x4102
> +#define TX_PSC_A3 0x4103
> +#define TX_RCVDET_EN_TMR 0x4122
> +#define TX_RCVDET_ST_TMR 0x4123
> +#define TX_DIAG_TX_CTRL 0x41e0
> +#define TX_DIAG_TX_DRV 0x41e1
> +#define TX_DIAG_BGREF_PREDRV_DELAY 0x41e7
> +#define TX_DIAG_ACYA_0 0x41ff
> +#define TX_DIAG_ACYA_1 0x43ff
> +#define TX_DIAG_ACYA_2 0x45ff
> +#define TX_DIAG_ACYA_3 0x47ff
> +#define TX_ANA_CTRL_REG_1 0x5020
> +#define TX_ANA_CTRL_REG_2 0x5021
> +#define TX_DIG_CTRL_REG_1 0x5023
> +#define TX_DIG_CTRL_REG_2 0x5024
> +#define TXDA_CYA_AUXDA_CYA 0x5025
> +#define TX_ANA_CTRL_REG_3 0x5026
> +#define TX_ANA_CTRL_REG_4 0x5027
> +#define TX_ANA_CTRL_REG_5 0x5029
> +#define RX_PSC_A0 0x8000
> +#define RX_PSC_CAL 0x8006
> +#define PHY_HDP_MODE_CTRL 0xc008
> +#define PHY_HDP_CLK_CTL 0xc009
> +#define PHY_ISO_CMN_CTRL 0xc010
> +#define PHY_PMA_CMN_CTRL1 0xc800
> +#define PHY_PMA_ISO_CMN_CTRL 0xc810
> +#define PHY_PMA_ISO_PLL_CTRL1 0xc812
> +#define PHY_PMA_ISOLATION_CTRL 0xc81f
> +
> +/* PHY_HDP_CLK_CTL */
> +#define PLL_DATA_RATE_CLK_DIV_MASK GENMASK(15, 8)
> +#define PLL_DATA_RATE_CLK_DIV_HBR 0x24
> +#define PLL_DATA_RATE_CLK_DIV_HBR2 0x12
> +#define PLL_CLK_EN_ACK BIT(3)
> +#define PLL_CLK_EN BIT(2)
> +#define PLL_READY BIT(1)
> +#define PLL_EN BIT(0)
> +
> +/* PHY_PMA_CMN_CTRL1 */
> +#define CMA_REF_CLK_DIG_DIV_MASK GENMASK(13, 12)
> +#define CMA_REF_CLK_SEL_MASK GENMASK(6, 4)
> +#define CMA_REF_CLK_RCV_EN_MASK BIT(3)
> +#define CMA_REF_CLK_RCV_EN 1
> +#define CMN_READY BIT(0)
> +
> +/* PHY_PMA_ISO_PLL_CTRL1 */
> +#define CMN_PLL0_CLK_DATART_DIV_MASK GENMASK(7, 0)
> +
> +/* TX_DIAG_TX_DRV */
> +#define TX_DRIVER_PROG_BOOST_ENABLE BIT(10)
> +#define TX_DRIVER_PROG_BOOST_LEVEL_MASK GENMASK(9, 8)
> +#define TX_DRIVER_LDO_BG_DEPENDENT_REF_ENABLE BIT(7)
> +#define TX_DRIVER_LDO_BANDGAP_REF_ENABLE BIT(6)
> +
> +/* TX_TXCC_CAL_SCLR_MULT_0 */
> +#define SCALED_RESISTOR_CALIBRATION_CODE_ADD BIT(8)
> +#define RESISTOR_CAL_MULT_VAL_32_128 BIT(5)
> +
> +/* CMN_CDIAG_REFCLK_CTRL */
> +#define DIG_REF_CLK_DIV_SCALER_MASK GENMASK(14, 12)
> +#define REFCLK_TERMINATION_EN_OVERRIDE_EN BIT(7)
> +#define REFCLK_TERMINATION_EN_OVERRIDE BIT(6)
> +
> +/* CMN_DIAG_HSCLK_SEL */
> +#define HSCLK1_SEL_MASK GENMASK(5, 4)
> +#define HSCLK0_SEL_MASK GENMASK(1, 0)
> +#define HSCLK_PLL0_DIV2 1
> +
> +/* XCVR_DIAG_HSCLK_SEL */
> +#define HSCLK_SEL_MODE3_MASK GENMASK(13, 12)
> +#define HSCLK_SEL_MODE3_HSCLK1 1
> +
> +/* CMN_PLL0_VCOCAL_START */
> +#define VCO_CALIB_CODE_START_POINT_VAL_MASK GENMASK(8, 0)
> +
> +/* CMN_DIAG_PLL0_FBH_OVRD */
> +#define PLL_FEEDBACK_DIV_HI_OVERRIDE_EN BIT(15)
> +
> +/* CMN_DIAG_PLL0_FBL_OVRD */
> +#define PLL_FEEDBACK_DIV_LO_OVERRIDE_EN BIT(15)
> +
> +/* CMN_DIAG_PLL0_PXL_DIVH */
> +#define PLL_PCLK_DIV_EN BIT(15)
> +
> +/* XCVR_DIAG_PLLDRC_CTRL */
> +#define DPLL_CLK_SEL_MODE3 BIT(14)
> +#define DPLL_DATA_RATE_DIV_MODE3_MASK GENMASK(13, 12)
> +
> +/* TX_DIAG_TX_CTRL */
> +#define TX_IF_SUBRATE_MODE3_MASK GENMASK(7, 6)
> +
> +/* PHY_HDP_MODE_CTRL */
> +#define POWER_STATE_A3_ACK BIT(7)
> +#define POWER_STATE_A2_ACK BIT(6)
> +#define POWER_STATE_A1_ACK BIT(5)
> +#define POWER_STATE_A0_ACK BIT(4)
> +#define POWER_STATE_A3 BIT(3)
> +#define POWER_STATE_A2 BIT(2)
> +#define POWER_STATE_A1 BIT(1)
> +#define POWER_STATE_A0 BIT(0)
> +
> +/* PHY_PMA_ISO_CMN_CTRL */
> +#define CMN_MACRO_PWR_EN_ACK BIT(5)
> +
> +#define KEEP_ALIVE 0x18
> +
> +#define REF_CLK_27MHZ 27000000
> +
> +/* HDMI TX clock control settings */
> +struct hdptx_hdmi_ctrl {
> + u32 pixel_clk_freq_min;
> + u32 pixel_clk_freq_max;
> + u32 feedback_factor;
> + u32 data_range_kbps_min;
> + u32 data_range_kbps_max;
> + u32 cmnda_pll0_ip_div;
> + u32 cmn_ref_clk_dig_div;
> + u32 ref_clk_divider_scaler;
> + u32 pll_fb_div_total;
> + u32 cmnda_pll0_fb_div_low;
> + u32 cmnda_pll0_fb_div_high;
> + u32 pixel_div_total;
> + u32 cmnda_pll0_pxdiv_low;
> + u32 cmnda_pll0_pxdiv_high;
> + u32 vco_freq_min;
> + u32 vco_freq_max;
> + u32 vco_ring_select;
> + u32 cmnda_hs_clk_0_sel;
> + u32 cmnda_hs_clk_1_sel;
> + u32 hsclk_div_at_xcvr;
> + u32 hsclk_div_tx_sub_rate;
> + u32 cmnda_pll0_hs_sym_div_sel;
> + u32 cmnda_pll0_clk_freq_min;
> + u32 cmnda_pll0_clk_freq_max;
> +};
> +
> +struct cdns_hdptx_phy {
> + struct cdns_mhdp_base base;
> +
> + void __iomem *regs; /* DPTX registers base */
> + struct mutex mbox_mutex; /* mutex to protect mailbox */
> + struct device *dev;
> + struct phy *phy;
> + struct clk *ref_clk, *apb_clk;
> + u32 ref_clk_rate;
> + bool power_up;
> + union {
> + struct phy_configure_opts_hdmi hdmi;
> + struct phy_configure_opts_dp dp;
> + };
> +};
> +
> +/* HDMI TX clock control settings, pixel clock is output */
> +static const struct hdptx_hdmi_ctrl pixel_clk_output_ctrl_table[] = {
> +/*Minclk Maxclk Fdbak DR_min DR_max ip_d dig DS Totl */
> +{ 27000, 27000, 1000, 270000, 270000, 0x03, 0x1, 0x1, 240, 0x0bc, 0x030, 80, 0x026, 0x026, 2160000, 2160000, 0, 2, 2, 2, 4, 0x3, 27000, 27000},
> +{ 27000, 27000, 1250, 337500, 337500, 0x03, 0x1, 0x1, 300, 0x0ec, 0x03c, 100, 0x030, 0x030, 2700000, 2700000, 0, 2, 2, 2, 4, 0x3, 33750, 33750},
> +{ 27000, 27000, 1500, 405000, 405000, 0x03, 0x1, 0x1, 360, 0x11c, 0x048, 120, 0x03a, 0x03a, 3240000, 3240000, 0, 2, 2, 2, 4, 0x3, 40500, 40500},
> +{ 27000, 27000, 2000, 540000, 540000, 0x03, 0x1, 0x1, 240, 0x0bc, 0x030, 80, 0x026, 0x026, 2160000, 2160000, 0, 2, 2, 2, 4, 0x2, 54000, 54000},
> +{ 54000, 54000, 1000, 540000, 540000, 0x03, 0x1, 0x1, 480, 0x17c, 0x060, 80, 0x026, 0x026, 4320000, 4320000, 1, 2, 2, 2, 4, 0x3, 54000, 54000},
> +{ 54000, 54000, 1250, 675000, 675000, 0x04, 0x1, 0x1, 400, 0x13c, 0x050, 50, 0x017, 0x017, 2700000, 2700000, 0, 1, 1, 2, 4, 0x2, 67500, 67500},
> +{ 54000, 54000, 1500, 810000, 810000, 0x04, 0x1, 0x1, 480, 0x17c, 0x060, 60, 0x01c, 0x01c, 3240000, 3240000, 0, 2, 2, 2, 2, 0x2, 81000, 81000},
> +{ 54000, 54000, 2000, 1080000, 1080000, 0x03, 0x1, 0x1, 240, 0x0bc, 0x030, 40, 0x012, 0x012, 2160000, 2160000, 0, 2, 2, 2, 1, 0x1, 108000, 108000},
> +{ 74250, 74250, 1000, 742500, 742500, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 80, 0x026, 0x026, 5940000, 5940000, 1, 2, 2, 2, 4, 0x3, 74250, 74250},
> +{ 74250, 74250, 1250, 928125, 928125, 0x04, 0x1, 0x1, 550, 0x1b4, 0x06e, 50, 0x017, 0x017, 3712500, 3712500, 1, 1, 1, 2, 4, 0x2, 92812, 92812},
> +{ 74250, 74250, 1500, 1113750, 1113750, 0x04, 0x1, 0x1, 660, 0x20c, 0x084, 60, 0x01c, 0x01c, 4455000, 4455000, 1, 2, 2, 2, 2, 0x2, 111375, 111375},
> +{ 74250, 74250, 2000, 1485000, 1485000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 40, 0x012, 0x012, 2970000, 2970000, 0, 2, 2, 2, 1, 0x1, 148500, 148500},
> +{ 99000, 99000, 1000, 990000, 990000, 0x03, 0x1, 0x1, 440, 0x15c, 0x058, 40, 0x012, 0x012, 3960000, 3960000, 1, 2, 2, 2, 2, 0x2, 99000, 99000},
> +{ 99000, 99000, 1250, 1237500, 1237500, 0x03, 0x1, 0x1, 275, 0x0d8, 0x037, 25, 0x00b, 0x00a, 2475000, 2475000, 0, 1, 1, 2, 2, 0x1, 123750, 123750},
> +{ 99000, 99000, 1500, 1485000, 1485000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 30, 0x00d, 0x00d, 2970000, 2970000, 0, 2, 2, 2, 1, 0x1, 148500, 148500},
> +{ 99000, 99000, 2000, 1980000, 1980000, 0x03, 0x1, 0x1, 440, 0x15c, 0x058, 40, 0x012, 0x012, 3960000, 3960000, 1, 2, 2, 2, 1, 0x1, 198000, 198000},
> +{148500, 148500, 1000, 1485000, 1485000, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 40, 0x012, 0x012, 5940000, 5940000, 1, 2, 2, 2, 2, 0x2, 148500, 148500},
> +{148500, 148500, 1250, 1856250, 1856250, 0x04, 0x1, 0x1, 550, 0x1b4, 0x06e, 25, 0x00b, 0x00a, 3712500, 3712500, 1, 1, 1, 2, 2, 0x1, 185625, 185625},
> +{148500, 148500, 1500, 2227500, 2227500, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 30, 0x00d, 0x00d, 4455000, 4455000, 1, 1, 1, 2, 2, 0x1, 222750, 222750},
> +{148500, 148500, 2000, 2970000, 2970000, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 40, 0x012, 0x012, 5940000, 5940000, 1, 2, 2, 2, 1, 0x1, 297000, 297000},
> +{198000, 198000, 1000, 1980000, 1980000, 0x03, 0x1, 0x1, 220, 0x0ac, 0x02c, 10, 0x003, 0x003, 1980000, 1980000, 0, 1, 1, 2, 1, 0x0, 198000, 198000},
> +{198000, 198000, 1250, 2475000, 2475000, 0x03, 0x1, 0x1, 550, 0x1b4, 0x06e, 25, 0x00b, 0x00a, 4950000, 4950000, 1, 1, 1, 2, 2, 0x1, 247500, 247500},
> +{198000, 198000, 1500, 2970000, 2970000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 15, 0x006, 0x005, 2970000, 2970000, 0, 1, 1, 2, 1, 0x0, 297000, 297000},
> +{198000, 198000, 2000, 3960000, 3960000, 0x03, 0x1, 0x1, 440, 0x15c, 0x058, 20, 0x008, 0x008, 3960000, 3960000, 1, 1, 1, 2, 1, 0x0, 396000, 396000},
> +{297000, 297000, 1000, 2970000, 2970000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 10, 0x003, 0x003, 2970000, 2970000, 0, 1, 1, 2, 1, 0x0, 297000, 297000},
> +{297000, 297000, 1500, 4455000, 4455000, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 15, 0x006, 0x005, 4455000, 4455000, 1, 1, 1, 2, 1, 0x0, 445500, 445500},
> +{297000, 297000, 2000, 5940000, 5940000, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 20, 0x008, 0x008, 5940000, 5940000, 1, 1, 1, 2, 1, 0x0, 594000, 594000},
> +{594000, 594000, 1000, 5940000, 5940000, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 10, 0x003, 0x003, 5940000, 5940000, 1, 1, 1, 2, 1, 0x0, 594000, 594000},
> +{594000, 594000, 750, 4455000, 4455000, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 10, 0x003, 0x003, 4455000, 4455000, 1, 1, 1, 2, 1, 0x0, 445500, 445500},
> +{594000, 594000, 625, 3712500, 3712500, 0x04, 0x1, 0x1, 550, 0x1b4, 0x06e, 10, 0x003, 0x003, 3712500, 3712500, 1, 1, 1, 2, 1, 0x0, 371250, 371250},
> +{594000, 594000, 500, 2970000, 2970000, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 10, 0x003, 0x003, 5940000, 5940000, 1, 1, 1, 2, 2, 0x1, 297000, 297000},
> +};
> +
> +/* HDMI TX PLL tuning settings */
> +struct hdptx_hdmi_pll_tuning {
> + u32 vco_freq_bin;
> + u32 vco_freq_min;
> + u32 vco_freq_max;
> + u32 volt_to_current_coarse;
> + u32 volt_to_current;
> + u32 ndac_ctrl;
> + u32 pmos_ctrl;
> + u32 ptat_ndac_ctrl;
> + u32 feedback_div_total;
> + u32 charge_pump_gain;
> + u32 coarse_code;
> + u32 v2i_code;
> + u32 vco_cal_code;
> +};
> +
> +/* HDMI TX PLL tuning settings, pixel clock is output */
> +static const struct hdptx_hdmi_pll_tuning pixel_clk_output_pll_table[] = {
> +/*bin VCO_freq min/max coar cod NDAC PMOS PTAT div-T P-Gain Coa V2I CAL */
> +{ 1, 1980000, 1980000, 0x4, 0x3, 0x0, 0x09, 0x09, 220, 0x42, 160, 5, 183 },
> +{ 2, 2160000, 2160000, 0x4, 0x3, 0x0, 0x09, 0x09, 240, 0x42, 166, 6, 208 },
> +{ 3, 2475000, 2475000, 0x5, 0x3, 0x1, 0x00, 0x07, 275, 0x42, 167, 6, 209 },
> +{ 4, 2700000, 2700000, 0x5, 0x3, 0x1, 0x00, 0x07, 300, 0x42, 188, 6, 230 },
> +{ 4, 2700000, 2700000, 0x5, 0x3, 0x1, 0x00, 0x07, 400, 0x4c, 188, 6, 230 },
> +{ 5, 2970000, 2970000, 0x6, 0x3, 0x1, 0x00, 0x07, 330, 0x42, 183, 6, 225 },
> +{ 6, 3240000, 3240000, 0x6, 0x3, 0x1, 0x00, 0x07, 360, 0x42, 203, 7, 256 },
> +{ 6, 3240000, 3240000, 0x6, 0x3, 0x1, 0x00, 0x07, 480, 0x4c, 203, 7, 256 },
> +{ 7, 3712500, 3712500, 0x4, 0x3, 0x0, 0x07, 0x0F, 550, 0x4c, 212, 7, 257 },
> +{ 8, 3960000, 3960000, 0x5, 0x3, 0x0, 0x07, 0x0F, 440, 0x42, 184, 6, 226 },
> +{ 9, 4320000, 4320000, 0x5, 0x3, 0x1, 0x07, 0x0F, 480, 0x42, 205, 7, 258 },
> +{ 10, 4455000, 4455000, 0x5, 0x3, 0x0, 0x07, 0x0F, 495, 0x42, 219, 7, 272 },
> +{ 10, 4455000, 4455000, 0x5, 0x3, 0x0, 0x07, 0x0F, 660, 0x4c, 219, 7, 272 },
> +{ 11, 4950000, 4950000, 0x6, 0x3, 0x1, 0x00, 0x07, 550, 0x42, 213, 7, 258 },
> +{ 12, 5940000, 5940000, 0x7, 0x3, 0x1, 0x00, 0x07, 660, 0x42, 244, 8, 292 },
> +};
> +
> +enum dp_link_rate {
> + RATE_1_6 = 162000,
> + RATE_2_1 = 216000,
> + RATE_2_4 = 243000,
> + RATE_2_7 = 270000,
> + RATE_3_2 = 324000,
> + RATE_4_3 = 432000,
> + RATE_5_4 = 540000,
> +};
> +
> +#define MAX_LINK_RATE RATE_5_4
> +
> +struct phy_pll_reg {
> + u16 val[7];
> + u32 addr;
> +};
> +
> +static const struct phy_pll_reg phy_pll_27m_cfg[] = {
> + /* 1.62 2.16 2.43 2.7 3.24 4.32 5.4 register address */
> + {{ 0x010e, 0x010e, 0x010e, 0x010e, 0x010e, 0x010e, 0x010e }, CMN_PLL0_VCOCAL_INIT_TMR },
> + {{ 0x001b, 0x001b, 0x001b, 0x001b, 0x001b, 0x001b, 0x001b }, CMN_PLL0_VCOCAL_ITER_TMR },
> + {{ 0x30b9, 0x3087, 0x3096, 0x30b4, 0x30b9, 0x3087, 0x30b4 }, CMN_PLL0_VCOCAL_START },
> + {{ 0x0077, 0x009f, 0x00b3, 0x00c7, 0x0077, 0x009f, 0x00c7 }, CMN_PLL0_INTDIV },
> + {{ 0xf9da, 0xf7cd, 0xf6c7, 0xf5c1, 0xf9da, 0xf7cd, 0xf5c1 }, CMN_PLL0_FRACDIV },
> + {{ 0x001e, 0x0028, 0x002d, 0x0032, 0x001e, 0x0028, 0x0032 }, CMN_PLL0_HIGH_THR },
> + {{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_PLL0_DSM_DIAG },
> + {{ 0x0000, 0x1000, 0x1000, 0x1000, 0x0000, 0x1000, 0x1000 }, CMN_PLLSM0_USER_DEF_CTRL },
> + {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_OVRD },
> + {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBH_OVRD },
> + {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBL_OVRD },
> + {{ 0x0006, 0x0007, 0x0007, 0x0007, 0x0006, 0x0007, 0x0007 }, CMN_DIAG_PLL0_V2I_TUNE },
> + {{ 0x0043, 0x0043, 0x0043, 0x0042, 0x0043, 0x0043, 0x0042 }, CMN_DIAG_PLL0_CP_TUNE },
> + {{ 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008 }, CMN_DIAG_PLL0_LF_PROG },
> + {{ 0x0100, 0x0001, 0x0001, 0x0001, 0x0100, 0x0001, 0x0001 }, CMN_DIAG_PLL0_PTATIS_TUNE1 },
> + {{ 0x0007, 0x0001, 0x0001, 0x0001, 0x0007, 0x0001, 0x0001 }, CMN_DIAG_PLL0_PTATIS_TUNE2 },
> + {{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_DIAG_PLL0_TEST_MODE},
> + {{ 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016 }, CMN_PSM_CLK_CTRL }
> +};
> +
> +static int dp_link_rate_index(u32 rate)
> +{
> + switch (rate) {
> + case RATE_1_6:
> + return 0;
> + case RATE_2_1:
> + return 1;
> + case RATE_2_4:
> + return 2;
> + case RATE_2_7:
> + return 3;
> + case RATE_3_2:
> + return 4;
> + case RATE_4_3:
> + return 5;
> + case RATE_5_4:
> + return 6;
> + default:
> + return -1;
??
> + }
> +}
> +
> +static int cdns_phy_reg_write(struct cdns_hdptx_phy *cdns_phy, u32 addr, u32 val)
> +{
> + return cdns_mhdp_reg_write(&cdns_phy->base, ADDR_PHY_AFE + (addr << 2), val);
> +}
> +
> +static u32 cdns_phy_reg_read(struct cdns_hdptx_phy *cdns_phy, u32 addr)
> +{
> + u32 reg32;
> +
> + cdns_mhdp_reg_read(&cdns_phy->base, ADDR_PHY_AFE + (addr << 2), ®32);
> +
> + return reg32;
> +}
> +
> +static void hdptx_dp_aux_cfg(struct cdns_hdptx_phy *cdns_phy)
> +{
> + /* Power up Aux */
> + cdns_phy_reg_write(cdns_phy, TXDA_CYA_AUXDA_CYA, 1);
> +
> + cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_1, 0x3);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_2, 36);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0100);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0300);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_3, 0x0000);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2008);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2018);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa018);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030c);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_5, 0x0000);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_4, 0x1001);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa098);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa198);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030d);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030f);
> +}
> +
> +/* PMA common configuration for 27MHz */
> +static void hdptx_dp_phy_pma_cmn_cfg_27mhz(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 num_lanes = cdns_phy->dp.lanes;
> + u16 val;
> + int k;
> +
> + /* Enable PMA input ref clk(CMN_REF_CLK_RCV_EN) */
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> + val &= ~CMA_REF_CLK_RCV_EN_MASK;
> + val |= FIELD_PREP(CMA_REF_CLK_RCV_EN_MASK, CMA_REF_CLK_RCV_EN);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> +
> + /* Startup state machine registers */
> + cdns_phy_reg_write(cdns_phy, CMN_SSM_BIAS_TMR, 0x0087);
> + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLEN_TMR, 0x001b);
> + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLPRE_TMR, 0x0036);
> + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLVREF_TMR, 0x001b);
> + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLLOCK_TMR, 0x006c);
> +
> + /* Current calibration registers */
> + cdns_phy_reg_write(cdns_phy, CMN_ICAL_INIT_TMR, 0x0044);
> + cdns_phy_reg_write(cdns_phy, CMN_ICAL_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_ITER_TMR, 0x0006);
> +
> + /* Resistor calibration registers */
> + cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_RXCAL_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_RXCAL_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_ITER_TMR, 0x0006);
> +
> + for (k = 0; k < num_lanes; k = k + 1) {
> + /* Power state machine registers */
> + cdns_phy_reg_write(cdns_phy, XCVR_PSM_CAL_TMR | (k << 9), 0x016d);
> + cdns_phy_reg_write(cdns_phy, XCVR_PSM_A0IN_TMR | (k << 9), 0x016d);
> + /* Transceiver control and diagnostic registers */
> + cdns_phy_reg_write(cdns_phy, XCVR_DIAG_LANE_FCM_EN_MGN_TMR | (k << 9), 0x00a2);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_BGREF_PREDRV_DELAY | (k << 9), 0x0097);
> + /* Transmitter receiver detect registers */
> + cdns_phy_reg_write(cdns_phy, TX_RCVDET_EN_TMR | (k << 9), 0x0a8c);
> + cdns_phy_reg_write(cdns_phy, TX_RCVDET_ST_TMR | (k << 9), 0x0036);
> + }
> +
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_0, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_1, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_2, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_3, 1);
> +}
> +
> +static void hdptx_dp_phy_pma_cmn_pll0_27mhz(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 num_lanes = cdns_phy->dp.lanes;
> + u32 link_rate = cdns_phy->dp.link_rate;
> + u16 val;
> + int index, i, k;
> +
> + /* DP PLL data rate 0/1 clock divider value */
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val &= ~PLL_DATA_RATE_CLK_DIV_MASK;
> + if (link_rate <= RATE_2_7)
> + val |= FIELD_PREP(PLL_DATA_RATE_CLK_DIV_MASK,
> + PLL_DATA_RATE_CLK_DIV_HBR);
> + else
> + val |= FIELD_PREP(PLL_DATA_RATE_CLK_DIV_MASK,
> + PLL_DATA_RATE_CLK_DIV_HBR2);
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> +
> + /* High speed clock 0/1 div */
> + val = cdns_phy_reg_read(cdns_phy, CMN_DIAG_HSCLK_SEL);
> + val &= ~(HSCLK1_SEL_MASK | HSCLK0_SEL_MASK);
> + if (link_rate <= RATE_2_7) {
> + val |= FIELD_PREP(HSCLK1_SEL_MASK, HSCLK_PLL0_DIV2);
> + val |= FIELD_PREP(HSCLK0_SEL_MASK, HSCLK_PLL0_DIV2);
> + }
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_HSCLK_SEL, val);
> +
> + for (k = 0; k < num_lanes; k++) {
> + val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)));
> + val &= ~HSCLK_SEL_MODE3_MASK;
> + if (link_rate <= RATE_2_7)
> + val |= FIELD_PREP(HSCLK_SEL_MODE3_MASK, HSCLK_SEL_MODE3_HSCLK1);
> + cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)), val);
> + }
> +
> + /* DP PHY PLL 27MHz configuration */
> + index = dp_link_rate_index(link_rate);
> + for (i = 0; i < ARRAY_SIZE(phy_pll_27m_cfg); i++)
> + cdns_phy_reg_write(cdns_phy, phy_pll_27m_cfg[i].addr,
> + phy_pll_27m_cfg[i].val[index]);
> +
> + /* Transceiver control and diagnostic registers */
> + for (k = 0; k < num_lanes; k++) {
> + val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)));
> + val &= ~(DPLL_DATA_RATE_DIV_MODE3_MASK | DPLL_CLK_SEL_MODE3);
> + if (link_rate <= RATE_2_7)
> + val |= FIELD_PREP(DPLL_DATA_RATE_DIV_MODE3_MASK, 2);
> + else
> + val |= FIELD_PREP(DPLL_DATA_RATE_DIV_MODE3_MASK, 1);
> + cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), val);
> + }
> +
> + for (k = 0; k < num_lanes; k = k + 1) {
> + /* Power state machine registers */
> + cdns_phy_reg_write(cdns_phy, (XCVR_PSM_RCTRL | (k << 9)), 0xbefc);
> + cdns_phy_reg_write(cdns_phy, (TX_PSC_A0 | (k << 9)), 0x6799);
> + cdns_phy_reg_write(cdns_phy, (TX_PSC_A1 | (k << 9)), 0x6798);
> + cdns_phy_reg_write(cdns_phy, (TX_PSC_A2 | (k << 9)), 0x0098);
> + cdns_phy_reg_write(cdns_phy, (TX_PSC_A3 | (k << 9)), 0x0098);
> + /* Receiver calibration power state definition register */
> + val = cdns_phy_reg_read(cdns_phy, RX_PSC_CAL | (k << 9));
> + val &= 0xffbb;
> + cdns_phy_reg_write(cdns_phy, (RX_PSC_CAL | (k << 9)), val);
> + val = cdns_phy_reg_read(cdns_phy, RX_PSC_A0 | (k << 9));
> + val &= 0xffbb;
> + cdns_phy_reg_write(cdns_phy, (RX_PSC_A0 | (k << 9)), val);
> + }
> +}
> +
> +static void hdptx_dp_phy_ref_clock_type(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 val;
> +
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> + val &= ~CMA_REF_CLK_SEL_MASK;
> + /*
> + * single ended reference clock (val |= 0x0030);
> + * differential clock (val |= 0x0000);
> + *
> + * for differential clock on the refclk_p and
> + * refclk_m off chip pins: CMN_DIAG_ACYA[8]=1'b1
> + * cdns_phy_reg_write(cdns_phy, CMN_DIAG_ACYA, 0x0100);
> + */
> + val |= FIELD_PREP(CMA_REF_CLK_SEL_MASK, 3);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> +}
> +
> +static int wait_for_ack(struct cdns_hdptx_phy *cdns_phy, u32 reg, u32 mask,
> + const char *err_msg)
> +{
> + u32 val, i;
> +
> + for (i = 0; i < 10; i++) {
> + val = cdns_phy_reg_read(cdns_phy, reg);
> + if (val & mask)
> + return 0;
> + msleep(20);
> + }
> +
> + dev_err(cdns_phy->dev, "%s\n", err_msg);
> + return -ETIMEDOUT;
> +}
> +
> +static int wait_for_ack_clear(struct cdns_hdptx_phy *cdns_phy, u32 reg, u32 mask,
> + const char *err_msg)
> +{
> + u32 val, i;
> +
> + for (i = 0; i < 10; i++) {
> + val = cdns_phy_reg_read(cdns_phy, reg);
> + if (!(val & mask))
> + return 0;
> + msleep(20);
> + }
> +
> + dev_err(cdns_phy->dev, "%s\n", err_msg);
> + return -ETIMEDOUT;
> +}
> +
> +static int hdptx_dp_phy_power_up(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 val;
> + int ret = 0;
> +
> + /* Enable HDP PLL's for high speed clocks */
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val |= PLL_EN;
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> + ret = wait_for_ack(cdns_phy, PHY_HDP_CLK_CTL, PLL_READY,
> + "Wait PLL Ack failed");
> + if (ret < 0)
> + return ret;
> +
> + /* Enable HDP PLL's data rate and full rate clocks out of PMA. */
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val |= PLL_CLK_EN;
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> + ret = wait_for_ack(cdns_phy, PHY_HDP_CLK_CTL, PLL_CLK_EN_ACK,
> + "Wait PLL clock enable ACK failed");
> + if (ret < 0)
> + return ret;
> +
> + /* Configure PHY in A2 Mode */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A2);
> + ret = wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A2_ACK,
> + "Wait A2 Ack failed");
> + if (ret < 0)
> + return ret;
> +
> + /* Configure PHY in A0 mode (PHY must be in the A0 power
> + * state in order to transmit data)
> + */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A0);
> + ret = wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A0_ACK,
> + "Wait A0 Ack failed");
> + if (ret < 0)
> + return ret;
> +
> + cdns_phy->power_up = true;
> +
> + return ret;
> +}
> +
> +static int hdptx_dp_phy_power_down(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u16 val;
> + int ret;
> +
> + if (!cdns_phy->power_up)
> + return 0;
> +
> + /* Place the PHY lanes in the A3 power state. */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A3);
> + ret = wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A3_ACK,
> + "Wait A3 Ack failed");
> + if (ret)
> + return ret;
> +
> + /* Disable HDP PLL's data rate and full rate clocks out of PMA. */
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val &= ~PLL_CLK_EN;
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> + ret = wait_for_ack_clear(cdns_phy, PHY_HDP_CLK_CTL, PLL_CLK_EN_ACK,
> + "Wait PLL clock Ack clear failed");
> + if (ret)
> + return ret;
> +
> + /* Disable HDP PLL's for high speed clocks */
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val &= ~PLL_EN;
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> + ret = wait_for_ack_clear(cdns_phy, PHY_HDP_CLK_CTL, PLL_READY,
> + "Wait PLL Ack clear failed");
> + if (ret)
> + return ret;
> +
> + cdns_phy->power_up = false;
> + return 0;
> +}
> +
> +static int cdns_hdptx_dp_configure(struct phy *phy,
> + union phy_configure_opts *opts)
> +{
> + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> + int ret;
> +
> + cdns_phy->dp.link_rate = opts->dp.link_rate;
> + cdns_phy->dp.lanes = opts->dp.lanes;
> +
> + if (cdns_phy->dp.link_rate > MAX_LINK_RATE) {
> + dev_err(cdns_phy->dev, "Link Rate(%d) Not supported\n", cdns_phy->dp.link_rate);
> + return false;
> + }
> +
> + /* Disable phy clock if PHY in power up state */
> + hdptx_dp_phy_power_down(cdns_phy);
> +
> + if (cdns_phy->ref_clk_rate == REF_CLK_27MHZ) {
> + hdptx_dp_phy_pma_cmn_cfg_27mhz(cdns_phy);
> + hdptx_dp_phy_pma_cmn_pll0_27mhz(cdns_phy);
> + } else {
> + dev_err(cdns_phy->dev, "Not support ref clock rate\n");
> + }
> +
> + /* PHY power up */
> + ret = hdptx_dp_phy_power_up(cdns_phy);
> +
> + return ret;
return hdptx_dp_phy_power_up() ?
> +}
> +
> +static bool hdptx_phy_check_alive(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 alive, newalive;
> + u8 retries_left = 50;
> +
> + alive = readl(cdns_phy->regs + KEEP_ALIVE);
> +
> + while (retries_left--) {
> + udelay(2);
> +
> + newalive = readl(cdns_phy->regs + KEEP_ALIVE);
> + if (alive == newalive)
> + continue;
> + return true;
> + }
> + return false;
> +}
> +
> +static int hdptx_clk_enable(struct cdns_hdptx_phy *cdns_phy)
> +{
> + struct device *dev = cdns_phy->dev;
> + u32 ref_clk_rate;
> + int ret;
> +
> + cdns_phy->ref_clk = devm_clk_get(dev, "ref");
> + if (IS_ERR(cdns_phy->ref_clk)) {
> + dev_err(dev, "phy ref clock not found\n");
> + return PTR_ERR(cdns_phy->ref_clk);
> + }
> +
> + cdns_phy->apb_clk = devm_clk_get(dev, "apb");
> + if (IS_ERR(cdns_phy->apb_clk)) {
> + dev_err(dev, "phy apb clock not found\n");
> + return PTR_ERR(cdns_phy->apb_clk);
> + }
> +
> + ret = clk_prepare_enable(cdns_phy->ref_clk);
> + if (ret) {
> + dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
> + return ret;
> + }
> +
> + ref_clk_rate = clk_get_rate(cdns_phy->ref_clk);
> + if (!ref_clk_rate) {
> + dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
> + goto err_ref_clk;
> + }
> +
> + if (ref_clk_rate == REF_CLK_27MHZ) {
> + cdns_phy->ref_clk_rate = ref_clk_rate;
> + } else {
> + dev_err(cdns_phy->dev, "Not support Ref Clock Rate(%dHz)\n", ref_clk_rate);
> + goto err_ref_clk;
> + }
> +
> + ret = clk_prepare_enable(cdns_phy->apb_clk);
> + if (ret) {
> + dev_err(cdns_phy->dev, "Failed to prepare apb clock\n");
> + goto err_ref_clk;
> + }
> +
> + return 0;
> +
> +err_ref_clk:
> + clk_disable_unprepare(cdns_phy->ref_clk);
> + return -EINVAL;
> +}
> +
> +static void hdptx_clk_disable(struct cdns_hdptx_phy *cdns_phy)
> +{
> + clk_disable_unprepare(cdns_phy->apb_clk);
> + clk_disable_unprepare(cdns_phy->ref_clk);
> +}
> +
> +static void hdptx_hdmi_arc_config(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u16 txpu_calib_code;
> + u16 txpd_calib_code;
> + u16 txpu_adj_calib_code;
> + u16 txpd_adj_calib_code;
> + u16 prev_calib_code;
> + u16 new_calib_code;
> + u16 rdata;
> +
> + /* Power ARC */
> + cdns_phy_reg_write(cdns_phy, TXDA_CYA_AUXDA_CYA, 0x0001);
> +
> + prev_calib_code = cdns_phy_reg_read(cdns_phy, TX_DIG_CTRL_REG_2);
> + txpu_calib_code = cdns_phy_reg_read(cdns_phy, CMN_TXPUCAL_CTRL);
> + txpd_calib_code = cdns_phy_reg_read(cdns_phy, CMN_TXPDCAL_CTRL);
> + txpu_adj_calib_code = cdns_phy_reg_read(cdns_phy, CMN_TXPU_ADJ_CTRL);
> + txpd_adj_calib_code = cdns_phy_reg_read(cdns_phy, CMN_TXPD_ADJ_CTRL);
> +
> + new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2)
> + + txpu_adj_calib_code + txpd_adj_calib_code;
> +
> + if (new_calib_code != prev_calib_code) {
> + rdata = cdns_phy_reg_read(cdns_phy, TX_ANA_CTRL_REG_1);
> + rdata &= 0xdfff;
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, rdata);
> + cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_2, new_calib_code);
> + mdelay(10);
> + rdata |= 0x2000;
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, rdata);
> + usleep_range(150, 250);
> + }
> +
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0100);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0300);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_3, 0x0000);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2008);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2018);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2098);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030c);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_5, 0x0010);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_4, 0x4001);
> + mdelay(5);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2198);
> + mdelay(5);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030d);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030f);
> +}
> +
> +static void hdptx_hdmi_phy_set_vswing(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 k;
> + const u32 num_lanes = 4;
> +
> + for (k = 0; k < num_lanes; k++) {
> + cdns_phy_reg_write(cdns_phy, (TX_DIAG_TX_DRV | (k << 9)),
> + TX_DRIVER_PROG_BOOST_ENABLE |
> + FIELD_PREP(TX_DRIVER_PROG_BOOST_LEVEL_MASK, 3) |
> + TX_DRIVER_LDO_BG_DEPENDENT_REF_ENABLE |
> + TX_DRIVER_LDO_BANDGAP_REF_ENABLE);
> + cdns_phy_reg_write(cdns_phy, (TX_TXCC_CPOST_MULT_00_0 | (k << 9)), 0x0);
> + cdns_phy_reg_write(cdns_phy, (TX_TXCC_CAL_SCLR_MULT_0 | (k << 9)),
> + SCALED_RESISTOR_CALIBRATION_CODE_ADD |
> + RESISTOR_CAL_MULT_VAL_32_128);
> + }
> +}
> +
> +static int hdptx_hdmi_feedback_factor(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 feedback_factor;
> +
> + switch (cdns_phy->hdmi.color_space) {
> + case HDMI_COLORSPACE_YUV422:
> + feedback_factor = 1000;
> + break;
> +
> + case HDMI_COLORSPACE_YUV420:
> + switch (cdns_phy->hdmi.bpc) {
switch should use the same case, pls do read the coding style doc, it
helps!
> + case 8:
> + feedback_factor = 500;
> + break;
> + case 10:
> + feedback_factor = 625;
> + break;
> + case 12:
> + feedback_factor = 750;
> + break;
> + case 16:
> + feedback_factor = 1000;
> + break;
> + default:
> + dev_dbg(cdns_phy->dev, "Invalid ColorDepth\n");
> + return 0;
> + }
> + break;
> +
> + default:
> + /* Assume RGB/YUV444 */
> + switch (cdns_phy->hdmi.bpc) {
> + case 10:
> + feedback_factor = 1250;
> + break;
> + case 12:
> + feedback_factor = 1500;
> + break;
> + case 16:
> + feedback_factor = 2000;
> + break;
> + default:
> + feedback_factor = 1000;
> + }
> + }
> +
> + return feedback_factor;
> +}
> +
> +static int hdptx_hdmi_phy_config(struct cdns_hdptx_phy *cdns_phy,
> + const struct hdptx_hdmi_ctrl *p_ctrl_table,
> + const struct hdptx_hdmi_pll_tuning *p_pll_table,
> + bool pclk_in)
> +{
> + const u32 num_lanes = 4;
> + u32 val, k;
> + int ret;
> +
> + /* enable PHY isolation mode only for CMN */
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISOLATION_CTRL, 0xd000);
> +
> + /* set cmn_pll0_clk_datart1_div/cmn_pll0_clk_datart0_div dividers */
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_ISO_PLL_CTRL1);
> + val &= ~CMN_PLL0_CLK_DATART_DIV_MASK;
> + val |= FIELD_PREP(CMN_PLL0_CLK_DATART_DIV_MASK, 0x12);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_PLL_CTRL1, val);
> +
> + /* assert PHY reset from isolation register */
> + cdns_phy_reg_write(cdns_phy, PHY_ISO_CMN_CTRL, 0x0000);
> + /* assert PMA CMN reset */
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_CMN_CTRL, 0x0000);
> +
> + /* register XCVR_DIAG_BIDI_CTRL */
> + for (k = 0; k < num_lanes; k++)
> + cdns_phy_reg_write(cdns_phy, XCVR_DIAG_BIDI_CTRL | (k << 9), 0x00ff);
> +
> + /* Describing Task phy_cfg_hdp */
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> + val &= ~CMA_REF_CLK_RCV_EN_MASK;
> + val |= FIELD_PREP(CMA_REF_CLK_RCV_EN_MASK, CMA_REF_CLK_RCV_EN);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> +
> + /* PHY Registers */
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> + val &= ~CMA_REF_CLK_DIG_DIV_MASK;
> + val |= FIELD_PREP(CMA_REF_CLK_DIG_DIV_MASK, p_ctrl_table->cmn_ref_clk_dig_div);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> +
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val &= ~PLL_DATA_RATE_CLK_DIV_MASK;
> + val |= FIELD_PREP(PLL_DATA_RATE_CLK_DIV_MASK,
> + PLL_DATA_RATE_CLK_DIV_HBR2);
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> +
> + /* Common control module control and diagnostic registers */
> + val = cdns_phy_reg_read(cdns_phy, CMN_CDIAG_REFCLK_CTRL);
> + val &= ~DIG_REF_CLK_DIV_SCALER_MASK;
> + val |= FIELD_PREP(DIG_REF_CLK_DIV_SCALER_MASK, p_ctrl_table->ref_clk_divider_scaler);
> + val |= REFCLK_TERMINATION_EN_OVERRIDE_EN | REFCLK_TERMINATION_EN_OVERRIDE;
> + cdns_phy_reg_write(cdns_phy, CMN_CDIAG_REFCLK_CTRL, val);
> +
> + /* High speed clock used */
> + val = cdns_phy_reg_read(cdns_phy, CMN_DIAG_HSCLK_SEL);
> + val &= ~(HSCLK1_SEL_MASK | HSCLK0_SEL_MASK);
> + val |= FIELD_PREP(HSCLK1_SEL_MASK, (p_ctrl_table->cmnda_hs_clk_1_sel >> 1));
> + val |= FIELD_PREP(HSCLK0_SEL_MASK, (p_ctrl_table->cmnda_hs_clk_0_sel >> 1));
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_HSCLK_SEL, val);
> +
> + for (k = 0; k < num_lanes; k++) {
> + val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)));
> + val &= ~HSCLK_SEL_MODE3_MASK;
> + val |= FIELD_PREP(HSCLK_SEL_MODE3_MASK,
> + (p_ctrl_table->cmnda_hs_clk_0_sel >> 1));
> + cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)), val);
> + }
> +
> + /* PLL 0 control state machine registers */
> + val = p_ctrl_table->vco_ring_select << 12;
> + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_USER_DEF_CTRL, val);
> +
> + if (pclk_in) {
> + val = 0x30a0;
> + } else {
> + val = cdns_phy_reg_read(cdns_phy, CMN_PLL0_VCOCAL_START);
> + val &= ~VCO_CALIB_CODE_START_POINT_VAL_MASK;
> + val |= FIELD_PREP(VCO_CALIB_CODE_START_POINT_VAL_MASK,
> + p_pll_table->vco_cal_code);
> + }
> + cdns_phy_reg_write(cdns_phy, CMN_PLL0_VCOCAL_START, val);
> +
> + cdns_phy_reg_write(cdns_phy, CMN_PLL0_VCOCAL_INIT_TMR, 0x0064);
> + cdns_phy_reg_write(cdns_phy, CMN_PLL0_VCOCAL_ITER_TMR, 0x000a);
> +
> + /* Common functions control and diagnostics registers */
> + val = p_ctrl_table->cmnda_pll0_hs_sym_div_sel << 8;
> + val |= p_ctrl_table->cmnda_pll0_ip_div;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_INCLK_CTRL, val);
> +
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_OVRD, 0x0000);
> +
> + val = p_ctrl_table->cmnda_pll0_fb_div_high;
> + val |= PLL_FEEDBACK_DIV_HI_OVERRIDE_EN;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_FBH_OVRD, val);
> +
> + val = p_ctrl_table->cmnda_pll0_fb_div_low;
> + val |= PLL_FEEDBACK_DIV_LO_OVERRIDE_EN;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_FBL_OVRD, val);
> +
> + if (!pclk_in) {
> + val = p_ctrl_table->cmnda_pll0_pxdiv_low;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_PXL_DIVL, val);
> +
> + val = p_ctrl_table->cmnda_pll0_pxdiv_high;
> + val |= PLL_PCLK_DIV_EN;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_PXL_DIVH, val);
> + }
> +
> + val = p_pll_table->volt_to_current_coarse;
> + val |= (p_pll_table->volt_to_current) << 4;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_V2I_TUNE, val);
> +
> + val = p_pll_table->charge_pump_gain;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_CP_TUNE, val);
> +
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_LF_PROG, 0x0008);
> +
> + val = p_pll_table->pmos_ctrl;
> + val |= (p_pll_table->ndac_ctrl) << 8;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_PTATIS_TUNE1, val);
> +
> + val = p_pll_table->ptat_ndac_ctrl;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_PTATIS_TUNE2, val);
> +
> + if (pclk_in)
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_TEST_MODE, 0x0022);
> + else
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_TEST_MODE, 0x0020);
> +
> + cdns_phy_reg_write(cdns_phy, CMN_PSM_CLK_CTRL, 0x0016);
> +
> + /* Transceiver control and diagnostic registers */
> + for (k = 0; k < num_lanes; k++) {
> + val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)));
> + val &= ~DPLL_CLK_SEL_MODE3;
> + cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), val);
> + }
> +
> + for (k = 0; k < num_lanes; k++) {
> + val = cdns_phy_reg_read(cdns_phy, (TX_DIAG_TX_CTRL | (k << 9)));
> + val &= ~TX_IF_SUBRATE_MODE3_MASK;
> + val |= FIELD_PREP(TX_IF_SUBRATE_MODE3_MASK,
> + (p_ctrl_table->hsclk_div_tx_sub_rate >> 1));
> + cdns_phy_reg_write(cdns_phy, (TX_DIAG_TX_CTRL | (k << 9)), val);
> + }
> +
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> + val &= ~CMA_REF_CLK_SEL_MASK;
> + /*
> + * single ended reference clock (val |= 0x0030);
> + * differential clock (val |= 0x0000);
> + * for differential clock on the refclk_p and
> + * refclk_m off chip pins: CMN_DIAG_ACYA[8]=1'b1
> + * cdns_phy_reg_write(cdns_phy, CMN_DIAG_ACYA, 0x0100);
> + */
> + val |= FIELD_PREP(CMA_REF_CLK_SEL_MASK, 3);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> +
> + /* Deassert PHY reset */
> + cdns_phy_reg_write(cdns_phy, PHY_ISO_CMN_CTRL, 0x0001);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_CMN_CTRL, 0x0003);
> +
> + /* Power state machine registers */
> + for (k = 0; k < num_lanes; k++)
> + cdns_phy_reg_write(cdns_phy, XCVR_PSM_RCTRL | (k << 9), 0xfefc);
> +
> + /* Assert cmn_macro_pwr_en */
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_CMN_CTRL, 0x0013);
> +
> + /* wait for cmn_macro_pwr_en_ack */
> + ret = wait_for_ack(cdns_phy, PHY_PMA_ISO_CMN_CTRL, CMN_MACRO_PWR_EN_ACK,
> + "MA output macro power up failed");
> + if (ret < 0)
> + return ret;
> +
> + /* wait for cmn_ready */
> + ret = wait_for_ack(cdns_phy, PHY_PMA_CMN_CTRL1, CMN_READY,
> + "PMA output ready failed");
> + if (ret < 0)
> + return ret;
> +
> + for (k = 0; k < num_lanes; k++) {
> + cdns_phy_reg_write(cdns_phy, TX_PSC_A0 | (k << 9), 0x6791);
> + cdns_phy_reg_write(cdns_phy, TX_PSC_A1 | (k << 9), 0x6790);
> + cdns_phy_reg_write(cdns_phy, TX_PSC_A2 | (k << 9), 0x0090);
> + cdns_phy_reg_write(cdns_phy, TX_PSC_A3 | (k << 9), 0x0090);
> +
> + val = cdns_phy_reg_read(cdns_phy, RX_PSC_CAL | (k << 9));
> + val &= 0xffbb;
> + cdns_phy_reg_write(cdns_phy, RX_PSC_CAL | (k << 9), val);
> +
> + val = cdns_phy_reg_read(cdns_phy, RX_PSC_A0 | (k << 9));
> + val &= 0xffbb;
> + cdns_phy_reg_write(cdns_phy, RX_PSC_A0 | (k << 9), val);
> + }
> +
> + return 0;
> +}
> +
> +static int hdptx_hdmi_phy_cfg(struct cdns_hdptx_phy *cdns_phy, u32 rate)
> +{
> + const struct hdptx_hdmi_ctrl *p_ctrl_table;
> + const struct hdptx_hdmi_pll_tuning *p_pll_table;
> + const u32 refclk_freq_khz = cdns_phy->ref_clk_rate / 1000;
> + const bool pclk_in = false;
> + u32 pixel_freq = rate;
> + u32 vco_freq, char_freq;
> + u32 div_total, feedback_factor;
> + u32 i;
> +
> + feedback_factor = hdptx_hdmi_feedback_factor(cdns_phy);
> +
> + char_freq = pixel_freq * feedback_factor / 1000;
> +
> + dev_dbg(cdns_phy->dev,
> + "Pixel clock: (%d KHz), character clock: %d, bpc is (%0d-bit)\n",
> + pixel_freq, char_freq, cdns_phy->hdmi.bpc);
> +
> + /* Get right row from the ctrl_table table.
> + * Check if 'pixel_freq_khz' value matches the PIXEL_CLK_FREQ column.
> + * Consider only the rows with FEEDBACK_FACTOR column matching feedback_factor.
> + */
> + for (i = 0; i < ARRAY_SIZE(pixel_clk_output_ctrl_table); i++) {
> + if (feedback_factor == pixel_clk_output_ctrl_table[i].feedback_factor &&
> + pixel_freq == pixel_clk_output_ctrl_table[i].pixel_clk_freq_min) {
> + p_ctrl_table = &pixel_clk_output_ctrl_table[i];
> + break;
> + }
> + }
> + if (i == ARRAY_SIZE(pixel_clk_output_ctrl_table)) {
> + dev_warn(cdns_phy->dev,
> + "Pixel clk (%d KHz) not supported, bpc is (%0d-bit)\n",
> + pixel_freq, cdns_phy->hdmi.bpc);
> + return -EINVAL;
> + }
> +
> + div_total = p_ctrl_table->pll_fb_div_total;
> + vco_freq = refclk_freq_khz * div_total / p_ctrl_table->cmnda_pll0_ip_div;
> +
> + /* Get right row from the pixel_clk_output_pll_table table.
> + * Check if vco_freq_khz and feedback_div_total
> + * column matching with pixel_clk_output_pll_table.
> + */
> + for (i = 0; i < ARRAY_SIZE(pixel_clk_output_pll_table); i++) {
> + if (vco_freq == pixel_clk_output_pll_table[i].vco_freq_min &&
> + div_total == pixel_clk_output_pll_table[i].feedback_div_total) {
> + p_pll_table = &pixel_clk_output_pll_table[i];
> + break;
> + }
> + }
> + if (i == ARRAY_SIZE(pixel_clk_output_pll_table)) {
> + dev_warn(cdns_phy->dev, "VCO (%d KHz) not supported\n", vco_freq);
> + return -EINVAL;
> + }
> + dev_dbg(cdns_phy->dev, "VCO frequency is (%d KHz)\n", vco_freq);
> +
> + return hdptx_hdmi_phy_config(cdns_phy, p_ctrl_table, p_pll_table, pclk_in);
> +}
> +
> +static int hdptx_hdmi_phy_power_up(struct cdns_hdptx_phy *cdns_phy)
> +{
> + int ret = 0;
superfluous init
> +
> + /* set Power State to A2 */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A2);
> +
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_0, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_1, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_2, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_3, 1);
> +
> + ret = wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A2_ACK,
> + "Wait A2 Ack failed");
> + if (ret < 0)
> + return ret;
> +
> + /* Power up ARC */
> + hdptx_hdmi_arc_config(cdns_phy);
> +
> + /* Configure PHY in A0 mode (PHY must be in the A0 power
> + * state in order to transmit data)
> + */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A0);
> +
> + return wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A0_ACK,
> + "Wait A0 Ack failed");
> +}
> +
> +static int hdptx_hdmi_phy_power_down(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 val;
> +
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_MODE_CTRL);
> + val &= ~(POWER_STATE_A0 | POWER_STATE_A1 | POWER_STATE_A2 | POWER_STATE_A3);
> + /* PHY_DP_MODE_CTL set to A3 power state */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, val | POWER_STATE_A3);
> +
> + return wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A3_ACK,
> + "Wait A3 Ack failed");
> +}
> +
> +static int cdns_hdptx_phy_on(struct phy *phy)
> +{
> + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> +
> + if (phy->attrs.mode == PHY_MODE_DP)
> + return hdptx_dp_phy_power_up(cdns_phy);
> + else
> + return hdptx_hdmi_phy_power_up(cdns_phy);
> +}
> +
> +static int cdns_hdptx_phy_off(struct phy *phy)
> +{
> + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> +
> + if (phy->attrs.mode == PHY_MODE_DP)
> + return hdptx_dp_phy_power_down(cdns_phy);
> + else
> + return hdptx_hdmi_phy_power_down(cdns_phy);
> + return 0;
> +}
> +
> +static int
> +cdns_hdptx_phy_valid(struct phy *phy, enum phy_mode mode,
> + int submode, union phy_configure_opts *opts)
> +{
> + u32 rate = opts->hdmi.pixel_clk_rate;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(pixel_clk_output_ctrl_table); i++)
> + if (rate == pixel_clk_output_ctrl_table[i].pixel_clk_freq_min)
> + return 0;
> +
> + return -EINVAL;
> +}
> +
> +static int cdns_hdptx_phy_init(struct phy *phy)
> +{
> + return 0;
> +}
> +
> +static int cdns_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> +{
> + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> + int ret = 0;
> +
> + if (mode == PHY_MODE_DP) {
> + hdptx_dp_phy_ref_clock_type(cdns_phy);
> +
> + /* PHY power up */
> + ret = hdptx_dp_phy_power_up(cdns_phy);
> + if (ret < 0)
> + return ret;
> +
> + hdptx_dp_aux_cfg(cdns_phy);
> + } else if (mode != PHY_MODE_HDMI) {
> + dev_err(&phy->dev, "Invalid PHY mode: %u\n", mode);
> + return -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> +static int cdns_hdptx_hdmi_configure(struct phy *phy,
> + union phy_configure_opts *opts)
> +{
> + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> + int ret;
> +
> + cdns_phy->hdmi.pixel_clk_rate = opts->hdmi.pixel_clk_rate;
> + cdns_phy->hdmi.color_space = opts->hdmi.color_space;
> + cdns_phy->hdmi.bpc = opts->hdmi.bpc;
> +
> + /* Check HDMI FW alive before HDMI PHY init */
> + ret = hdptx_phy_check_alive(cdns_phy);
> + if (!ret) {
> + dev_err(cdns_phy->dev, "NO HDMI FW running\n");
> + return -ENXIO;
> + }
> +
> + /* Configure PHY */
> + if (hdptx_hdmi_phy_cfg(cdns_phy, cdns_phy->hdmi.pixel_clk_rate) < 0) {
> + dev_err(cdns_phy->dev, "failed to set phy pclock\n");
> + return -EINVAL;
> + }
> +
> + ret = hdptx_hdmi_phy_power_up(cdns_phy);
> + if (ret < 0)
> + return ret;
> +
> + hdptx_hdmi_phy_set_vswing(cdns_phy);
> +
> + return 0;
> +}
> +
> +static int cdns_hdptx_configure(struct phy *phy,
> + union phy_configure_opts *opts)
> +{
> + if (phy->attrs.mode == PHY_MODE_DP)
> + return cdns_hdptx_dp_configure(phy, opts);
> + else
> + return cdns_hdptx_hdmi_configure(phy, opts);
> +}
> +
> +static const struct phy_ops cdns_hdptx_phy_ops = {
> + .init = cdns_hdptx_phy_init,
> + .set_mode = cdns_hdptx_phy_set_mode,
> + .configure = cdns_hdptx_configure,
> + .power_on = cdns_hdptx_phy_on,
> + .power_off = cdns_hdptx_phy_off,
> + .validate = cdns_hdptx_phy_valid,
> + .owner = THIS_MODULE,
> +};
> +
> +static int cdns_hdptx_phy_probe(struct platform_device *pdev)
> +{
> + struct cdns_hdptx_phy *cdns_phy;
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct resource *res;
> + struct phy *phy;
> + int ret;
> +
> + cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
> + if (!cdns_phy)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, cdns_phy);
> + cdns_phy->dev = dev;
> + mutex_init(&cdns_phy->mbox_mutex);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENODEV;
> + cdns_phy->regs = devm_ioremap(dev, res->start, resource_size(res));
> + if (IS_ERR(cdns_phy->regs))
> + return PTR_ERR(cdns_phy->regs);
> +
> + phy = devm_phy_create(dev, node, &cdns_hdptx_phy_ops);
> + if (IS_ERR(phy))
> + return PTR_ERR(phy);
> +
> + cdns_phy->phy = phy;
> + phy_set_drvdata(phy, cdns_phy);
> +
> + /* init base struct for access mhdp mailbox */
> + cdns_phy->base.dev = cdns_phy->dev;
> + cdns_phy->base.regs = cdns_phy->regs;
> + cdns_phy->base.mbox_mutex = &cdns_phy->mbox_mutex;
> +
> + ret = hdptx_clk_enable(cdns_phy);
> + if (ret) {
> + dev_err(dev, "Init clk fail\n");
> + return -EINVAL;
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider)) {
> + ret = PTR_ERR(phy_provider);
> + goto clk_disable;
> + }
> +
> + dev_dbg(dev, "probe success!\n");
> +
> + return 0;
> +
> +clk_disable:
> + hdptx_clk_disable(cdns_phy);
> +
> + return -EINVAL;
> +}
> +
> +static int cdns_hdptx_phy_remove(struct platform_device *pdev)
> +{
> + struct cdns_hdptx_phy *cdns_phy = platform_get_drvdata(pdev);
> +
> + hdptx_clk_disable(cdns_phy);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id cdns_hdptx_phy_of_match[] = {
> + {.compatible = "fsl,imx8mq-hdptx-phy" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, cdns_hdptx_phy_of_match);
> +
> +static struct platform_driver cdns_hdptx_phy_driver = {
> + .probe = cdns_hdptx_phy_probe,
> + .remove = cdns_hdptx_phy_remove,
> + .driver = {
> + .name = "cdns-hdptx-phy",
> + .of_match_table = cdns_hdptx_phy_of_match,
> + }
> +};
> +module_platform_driver(cdns_hdptx_phy_driver);
> +
> +MODULE_AUTHOR("Sandor Yu <sandor.yu@nxp.com>");
> +MODULE_DESCRIPTION("Cadence HDP-TX DP/HDMI PHY driver");
> +MODULE_LICENSE("GPL");
> --
> 2.34.1
--
~Vinod
^ permalink raw reply
* [PATCH v2] dt-bindings: PCI: altera: Convert to YAML
From: matthew.gerlach @ 2024-04-05 14:53 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, robh, krzysztof.kozlowski+dt, conor+dt,
linux-pci, devicetree, linux-kernel
Cc: Matthew Gerlach
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Convert the device tree bindings for the Altera Root Port PCIe controller
from text to YAML.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v2:
- Move allOf: to bottom of file, just like example-schema is showing
- add constraint for reg and reg-names
- remove unneeded device_type
- drop #address-cells and #size-cells
- change minItems to maxItems for interrupts:
- change msi-parent to just "msi-parent: true"
- cleaned up required:
- make subject consistent with other commits coverting to YAML
- s/overt/onvert/g
---
.../devicetree/bindings/pci/altera-pcie.txt | 50 ---------
.../bindings/pci/altr,pcie-root-port.yaml | 106 ++++++++++++++++++
2 files changed, 106 insertions(+), 50 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
create mode 100644 Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt
deleted file mode 100644
index 816b244a221e..000000000000
--- a/Documentation/devicetree/bindings/pci/altera-pcie.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-* Altera PCIe controller
-
-Required properties:
-- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
-- reg: a list of physical base address and length for TXS and CRA.
- For "altr,pcie-root-port-2.0", additional HIP base address and length.
-- reg-names: must include the following entries:
- "Txs": TX slave port region
- "Cra": Control register access region
- "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
-- interrupts: specifies the interrupt source of the parent interrupt
- controller. The format of the interrupt specifier depends
- on the parent interrupt controller.
-- device_type: must be "pci"
-- #address-cells: set to <3>
-- #size-cells: set to <2>
-- #interrupt-cells: set to <1>
-- ranges: describes the translation of addresses for root ports and
- standard PCI regions.
-- interrupt-map-mask and interrupt-map: standard PCI properties to define the
- mapping of the PCIe interface to interrupt numbers.
-
-Optional properties:
-- msi-parent: Link to the hardware entity that serves as the MSI controller
- for this PCIe controller.
-- bus-range: PCI bus numbers covered
-
-Example
- pcie_0: pcie@c00000000 {
- compatible = "altr,pcie-root-port-1.0";
- reg = <0xc0000000 0x20000000>,
- <0xff220000 0x00004000>;
- reg-names = "Txs", "Cra";
- interrupt-parent = <&hps_0_arm_gic_0>;
- interrupts = <0 40 4>;
- interrupt-controller;
- #interrupt-cells = <1>;
- bus-range = <0x0 0xFF>;
- device_type = "pci";
- msi-parent = <&msi_to_gic_gen_0>;
- #address-cells = <3>;
- #size-cells = <2>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_0 1>,
- <0 0 0 2 &pcie_0 2>,
- <0 0 0 3 &pcie_0 3>,
- <0 0 0 4 &pcie_0 4>;
- ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
- 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
- };
diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
new file mode 100644
index 000000000000..999dcda05f55
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2024, Intel Corporation
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera PCIe Root Port
+
+maintainers:
+ - Matthew Gerlach <matthew.gerlach@linux.intel.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - altr,pcie-root-port-1.0
+ - altr,pcie-root-port-2.0
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-map-mask:
+ items:
+ - const: 0
+ - const: 0
+ - const: 0
+ - const: 7
+
+ interrupt-map:
+ maxItems: 4
+
+ "#interrupt-cells":
+ const: 1
+
+ msi-parent: true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - device_type
+ - interrupts
+ - interrupt-map
+ - interrupt-map-mask
+
+unevaluatedProperties: false
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - altr,pcie-root-port-1.0
+ then:
+ properties:
+ reg:
+ items:
+ - description: TX slave port region
+ - description: Control register access region
+
+ reg-names:
+ items:
+ - const: Txs
+ - const: Cra
+
+ else:
+ properties:
+ reg:
+ items:
+ - description: Hard IP region
+ - description: TX slave port region
+ - description: Control register access region
+
+ reg-names:
+ items:
+ - const: Hip
+ - const: Txs
+ - const: Cra
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ pcie_0: pcie@c00000000 {
+ compatible = "altr,pcie-root-port-1.0";
+ reg = <0xc0000000 0x20000000>,
+ <0xff220000 0x00004000>;
+ reg-names = "Txs", "Cra";
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ bus-range = <0x0 0xff>;
+ device_type = "pci";
+ msi-parent = <&msi_to_gic_gen_0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 1>,
+ <0 0 0 2 &pcie_intc 2>,
+ <0 0 0 3 &pcie_intc 3>,
+ <0 0 0 4 &pcie_intc 4>;
+ ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
+ 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
+ };
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 1/1] arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960/wm8962 and sai[0,1,4,5]
From: Frank Li @ 2024-04-05 14:56 UTC (permalink / raw)
To: Francesco Dolcini
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
In-Reply-To: <20240405063648.GA4562@francesco-nb>
On Fri, Apr 05, 2024 at 08:36:48AM +0200, Francesco Dolcini wrote:
> Hello Frank,
>
> On Thu, Apr 04, 2024 at 12:19:13PM -0400, Frank Li wrote:
> > imx8qxp-mek use two kind audio codec, wm8960 and wm8962. Using dummy gpio
> > i2c bus mux to connect both i2c devices. One will probe failure and other
> > will probe success when devices driver check whoami. So one dtb can cover
> > both board configuration.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 210 ++++++++++++++++++
> > 1 file changed, 210 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > index 8360bb851ac03..adff87c7cf305 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > @@ -44,6 +51,105 @@ usb3_data_ss: endpoint {
>
> [...]
>
> > + /*
> > + * This dummy i2c mux. GPIO actually will not impact selection. At actual boards, only 1
> > + * device connectted. I2C client driver will check ID when probe. Only matched ID's driver
> > + * probe successfully.
> > + */
> > + i2cvmux: i2cmux {
> > + compatible = "i2c-mux-gpio";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + mux-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; /* use an unused gpio */
>
> There is for sure people that have more experience and competency that
> me and it would be interesting to hear their feedback, but this
> looks like a bad hack, and you are just playing with the driver
> behavior to ensure that you get what you need.
We want to use one dtb to handle differecne bench boards because some chips
are out of life-cycle. I don't think it is 'hack' although not
straightforward.
check woiam is quite common at i2c drivers. All used method is quite
common, I just change it from difference point.
>
> Francesco
>
>
^ permalink raw reply
* [PATCH v2 01/11] iio: buffer-dma: add iio_dmaengine_buffer_setup()
From: Nuno Sa @ 2024-04-05 14:59 UTC (permalink / raw)
To: linux-iio, devicetree
Cc: Dragos Bogdan, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Olivier Moysan
In-Reply-To: <20240405-iio-backend-axi-dac-v2-0-293bab7d5552@analog.com>
This brings the DMA buffer API more in line with what we have in the
triggered buffer. There's no need of having both
devm_iio_dmaengine_buffer_setup() and devm_iio_dmaengine_buffer_alloc().
Hence we introduce the new iio_dmaengine_buffer_setup() that together
with devm_iio_dmaengine_buffer_setup() should be all we need.
Note that as part of this change iio_dmaengine_buffer_alloc() is again
static and the axi-adc was updated accordingly.
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
---
drivers/iio/adc/adi-axi-adc.c | 16 +-------
drivers/iio/buffer/industrialio-buffer-dmaengine.c | 48 +++++++++-------------
include/linux/iio/buffer-dmaengine.h | 5 ++-
3 files changed, 24 insertions(+), 45 deletions(-)
diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c
index 4156639b3c8b..184b36dca6d0 100644
--- a/drivers/iio/adc/adi-axi-adc.c
+++ b/drivers/iio/adc/adi-axi-adc.c
@@ -124,26 +124,12 @@ static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back,
struct iio_dev *indio_dev)
{
struct adi_axi_adc_state *st = iio_backend_get_priv(back);
- struct iio_buffer *buffer;
const char *dma_name;
- int ret;
if (device_property_read_string(st->dev, "dma-names", &dma_name))
dma_name = "rx";
- buffer = iio_dmaengine_buffer_alloc(st->dev, dma_name);
- if (IS_ERR(buffer)) {
- dev_err(st->dev, "Could not get DMA buffer, %ld\n",
- PTR_ERR(buffer));
- return ERR_CAST(buffer);
- }
-
- indio_dev->modes |= INDIO_BUFFER_HARDWARE;
- ret = iio_device_attach_buffer(indio_dev, buffer);
- if (ret)
- return ERR_PTR(ret);
-
- return buffer;
+ return iio_dmaengine_buffer_setup(st->dev, indio_dev, dma_name);
}
static void axi_adc_free_buffer(struct iio_backend *back,
diff --git a/drivers/iio/buffer/industrialio-buffer-dmaengine.c b/drivers/iio/buffer/industrialio-buffer-dmaengine.c
index a18c1da292af..97f3116566f5 100644
--- a/drivers/iio/buffer/industrialio-buffer-dmaengine.c
+++ b/drivers/iio/buffer/industrialio-buffer-dmaengine.c
@@ -159,7 +159,7 @@ static const struct iio_dev_attr *iio_dmaengine_buffer_attrs[] = {
* Once done using the buffer iio_dmaengine_buffer_free() should be used to
* release it.
*/
-struct iio_buffer *iio_dmaengine_buffer_alloc(struct device *dev,
+static struct iio_buffer *iio_dmaengine_buffer_alloc(struct device *dev,
const char *channel)
{
struct dmaengine_buffer *dmaengine_buffer;
@@ -210,7 +210,6 @@ struct iio_buffer *iio_dmaengine_buffer_alloc(struct device *dev,
kfree(dmaengine_buffer);
return ERR_PTR(ret);
}
-EXPORT_SYMBOL_NS_GPL(iio_dmaengine_buffer_alloc, IIO_DMAENGINE_BUFFER);
/**
* iio_dmaengine_buffer_free() - Free dmaengine buffer
@@ -230,39 +229,33 @@ void iio_dmaengine_buffer_free(struct iio_buffer *buffer)
}
EXPORT_SYMBOL_NS_GPL(iio_dmaengine_buffer_free, IIO_DMAENGINE_BUFFER);
-static void __devm_iio_dmaengine_buffer_free(void *buffer)
-{
- iio_dmaengine_buffer_free(buffer);
-}
-
-/**
- * devm_iio_dmaengine_buffer_alloc() - Resource-managed iio_dmaengine_buffer_alloc()
- * @dev: Parent device for the buffer
- * @channel: DMA channel name, typically "rx".
- *
- * This allocates a new IIO buffer which internally uses the DMAengine framework
- * to perform its transfers. The parent device will be used to request the DMA
- * channel.
- *
- * The buffer will be automatically de-allocated once the device gets destroyed.
- */
-static struct iio_buffer *devm_iio_dmaengine_buffer_alloc(struct device *dev,
- const char *channel)
+struct iio_buffer *iio_dmaengine_buffer_setup(struct device *dev,
+ struct iio_dev *indio_dev,
+ const char *channel)
{
struct iio_buffer *buffer;
int ret;
buffer = iio_dmaengine_buffer_alloc(dev, channel);
if (IS_ERR(buffer))
- return buffer;
+ return ERR_CAST(buffer);
- ret = devm_add_action_or_reset(dev, __devm_iio_dmaengine_buffer_free,
- buffer);
- if (ret)
+ indio_dev->modes |= INDIO_BUFFER_HARDWARE;
+
+ ret = iio_device_attach_buffer(indio_dev, buffer);
+ if (ret) {
+ iio_dmaengine_buffer_free(buffer);
return ERR_PTR(ret);
+ }
return buffer;
}
+EXPORT_SYMBOL_NS_GPL(iio_dmaengine_buffer_setup, IIO_DMAENGINE_BUFFER);
+
+static void __devm_iio_dmaengine_buffer_free(void *buffer)
+{
+ iio_dmaengine_buffer_free(buffer);
+}
/**
* devm_iio_dmaengine_buffer_setup() - Setup a DMA buffer for an IIO device
@@ -281,13 +274,12 @@ int devm_iio_dmaengine_buffer_setup(struct device *dev,
{
struct iio_buffer *buffer;
- buffer = devm_iio_dmaengine_buffer_alloc(dev, channel);
+ buffer = iio_dmaengine_buffer_setup(dev, indio_dev, channel);
if (IS_ERR(buffer))
return PTR_ERR(buffer);
- indio_dev->modes |= INDIO_BUFFER_HARDWARE;
-
- return iio_device_attach_buffer(indio_dev, buffer);
+ return devm_add_action_or_reset(dev, __devm_iio_dmaengine_buffer_free,
+ buffer);
}
EXPORT_SYMBOL_NS_GPL(devm_iio_dmaengine_buffer_setup, IIO_DMAENGINE_BUFFER);
diff --git a/include/linux/iio/buffer-dmaengine.h b/include/linux/iio/buffer-dmaengine.h
index cbb8ba957fad..acb60f9a3fff 100644
--- a/include/linux/iio/buffer-dmaengine.h
+++ b/include/linux/iio/buffer-dmaengine.h
@@ -10,9 +10,10 @@
struct iio_dev;
struct device;
-struct iio_buffer *iio_dmaengine_buffer_alloc(struct device *dev,
- const char *channel);
void iio_dmaengine_buffer_free(struct iio_buffer *buffer);
+struct iio_buffer *iio_dmaengine_buffer_setup(struct device *dev,
+ struct iio_dev *indio_dev,
+ const char *channel);
int devm_iio_dmaengine_buffer_setup(struct device *dev,
struct iio_dev *indio_dev,
const char *channel);
--
2.44.0
^ permalink raw reply related
* [PATCH v2 08/11] iio: core: add get_iio_backend() callback
From: Nuno Sa @ 2024-04-05 15:00 UTC (permalink / raw)
To: linux-iio, devicetree
Cc: Dragos Bogdan, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Olivier Moysan
In-Reply-To: <20240405-iio-backend-axi-dac-v2-0-293bab7d5552@analog.com>
This new callback is intended for IIO frontends that have more than one
backend and these somehow extend some channels. In these cases, if the
backend framework is responsible for handling some IIO userspace
interface directly, it needs to be capable to get the right backend from
an iio device. Hence, we need to callback into the frontend so it can
give us the right backend given a specific channel.
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
---
include/linux/iio/iio.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h
index e370a7bb3300..83158c93330f 100644
--- a/include/linux/iio/iio.h
+++ b/include/linux/iio/iio.h
@@ -526,6 +526,8 @@ struct iio_info {
int (*hwfifo_set_watermark)(struct iio_dev *indio_dev, unsigned val);
int (*hwfifo_flush_to_buffer)(struct iio_dev *indio_dev,
unsigned count);
+ struct iio_backend *(*get_iio_backend)(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan);
};
/**
--
2.44.0
^ permalink raw reply related
* [PATCH v2 02/11] iio: buffer-dma: Rename iio_dma_buffer_data_available()
From: Nuno Sa @ 2024-04-05 15:00 UTC (permalink / raw)
To: linux-iio, devicetree
Cc: Dragos Bogdan, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Olivier Moysan, Paul Cercueil
In-Reply-To: <20240405-iio-backend-axi-dac-v2-0-293bab7d5552@analog.com>
From: Paul Cercueil <paul@crapouillou.net>
Change its name to iio_dma_buffer_usage(), as this function can be used
both for the .data_available and the .space_available callbacks.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
---
drivers/iio/buffer/industrialio-buffer-dma.c | 11 ++++++-----
drivers/iio/buffer/industrialio-buffer-dmaengine.c | 2 +-
include/linux/iio/buffer-dma.h | 2 +-
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/iio/buffer/industrialio-buffer-dma.c b/drivers/iio/buffer/industrialio-buffer-dma.c
index 5610ba67925e..404f9867bdc5 100644
--- a/drivers/iio/buffer/industrialio-buffer-dma.c
+++ b/drivers/iio/buffer/industrialio-buffer-dma.c
@@ -547,13 +547,14 @@ int iio_dma_buffer_read(struct iio_buffer *buffer, size_t n,
EXPORT_SYMBOL_GPL(iio_dma_buffer_read);
/**
- * iio_dma_buffer_data_available() - DMA buffer data_available callback
+ * iio_dma_buffer_usage() - DMA buffer data_available and
+ * space_available callback
* @buf: Buffer to check for data availability
*
- * Should be used as the data_available callback for iio_buffer_access_ops
- * struct for DMA buffers.
+ * Should be used as the data_available and space_available callbacks for
+ * iio_buffer_access_ops struct for DMA buffers.
*/
-size_t iio_dma_buffer_data_available(struct iio_buffer *buf)
+size_t iio_dma_buffer_usage(struct iio_buffer *buf)
{
struct iio_dma_buffer_queue *queue = iio_buffer_to_queue(buf);
struct iio_dma_buffer_block *block;
@@ -586,7 +587,7 @@ size_t iio_dma_buffer_data_available(struct iio_buffer *buf)
return data_available;
}
-EXPORT_SYMBOL_GPL(iio_dma_buffer_data_available);
+EXPORT_SYMBOL_GPL(iio_dma_buffer_usage);
/**
* iio_dma_buffer_set_bytes_per_datum() - DMA buffer set_bytes_per_datum callback
diff --git a/drivers/iio/buffer/industrialio-buffer-dmaengine.c b/drivers/iio/buffer/industrialio-buffer-dmaengine.c
index 97f3116566f5..df05d66afff9 100644
--- a/drivers/iio/buffer/industrialio-buffer-dmaengine.c
+++ b/drivers/iio/buffer/industrialio-buffer-dmaengine.c
@@ -117,7 +117,7 @@ static const struct iio_buffer_access_funcs iio_dmaengine_buffer_ops = {
.request_update = iio_dma_buffer_request_update,
.enable = iio_dma_buffer_enable,
.disable = iio_dma_buffer_disable,
- .data_available = iio_dma_buffer_data_available,
+ .data_available = iio_dma_buffer_usage,
.release = iio_dmaengine_buffer_release,
.modes = INDIO_BUFFER_HARDWARE,
diff --git a/include/linux/iio/buffer-dma.h b/include/linux/iio/buffer-dma.h
index 18d3702fa95d..52a838ec0e57 100644
--- a/include/linux/iio/buffer-dma.h
+++ b/include/linux/iio/buffer-dma.h
@@ -132,7 +132,7 @@ int iio_dma_buffer_disable(struct iio_buffer *buffer,
struct iio_dev *indio_dev);
int iio_dma_buffer_read(struct iio_buffer *buffer, size_t n,
char __user *user_buffer);
-size_t iio_dma_buffer_data_available(struct iio_buffer *buffer);
+size_t iio_dma_buffer_usage(struct iio_buffer *buffer);
int iio_dma_buffer_set_bytes_per_datum(struct iio_buffer *buffer, size_t bpd);
int iio_dma_buffer_set_length(struct iio_buffer *buffer, unsigned int length);
int iio_dma_buffer_request_update(struct iio_buffer *buffer);
--
2.44.0
^ permalink raw reply related
* [PATCH v2 00/11] iio: dac: support IIO backends on the output direction
From: Nuno Sa @ 2024-04-05 14:59 UTC (permalink / raw)
To: linux-iio, devicetree
Cc: Dragos Bogdan, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Olivier Moysan, Paul Cercueil, Alexandru Ardelean
Hi Jonathan,
Here it goes version 2 of the output backend series. The main points in
here:
- The refactoring the DMA BUF api for setup. I pretty much like how it
turned out. Note that Paul's patch ("iio: buffer-dmaengine: Support
specifying buffer direction") had to be updated accordingly.
- Introduction of the struct iio_info callback for getting the backend.
I'm not sure about this one as we have no user for it and we may not
have one for sometime. I like how the "default" implementation for
getting the backend turned out and it should cover 99% of the cases. It
will only fail if the iio parent device is not the same device where we
bound the backend.
- As mentioned above, we now get the backend from the iio device
matching the IIO parent device with the device used when getting the
backend. This should cover almost all the cases I think. Should be very
unlikely to use a different device in devm_iio_backend_get() and
devm_iio_device_alloc().
For the bindings, I still did not addressed Rob's point about dma-names.
I did reply [1] but still no feedback.
Anyways, full log:
v1:
* https://lore.kernel.org/all/20240328-iio-backend-axi-dac-v1-0-afc808b3fde3@analog.com/
v2:
* Patch 1:
- New patch.
* Patch 4:
- Make things consistent with the triggered buffer case.
* Patch 6:
- Fixed description as it's an output device;
- Avoid duplicating the "bindings" word in the commit title.
* Patch 7:
- Renamed vdd_3_3-supply -> vdd-3p3-supply;
- Added IRQ and vref properties;
- Avoid duplicating the "bindings" word in the commit title.
* Patch 8:
- New patch.
* Patch 9:
- Fixed some typos in kerneldocs;
- Add iio_backend_from_indio_dev_parent(). Default way of getting backends
from IIO devices;
- Explicitly differentiate frontends and backends ext_info in
iio_backend_extend_chan_spec().
- Spell out CW as CONTINUOUS_WAVE;
- Add _hz suffix in set_sample_rate().
* Patch 10:
- Rephrase comment in axi_dac_set_sample_rate() when DDS is disabled;
- Use the new iio_dmaengine_buffer_setup_ext() API;
- Passed tone as 0,1 value being 1 second tone.
* Patch 11:
- Fixed mixed spaces with tabs in ABI file and dac -> DAC;
- Add COMPILE_TEST to kconfig;
- Dropped operating mode enum. Use defines;
- Add comments for IIO enum operating mode and the value we need to
set on the device;
- Add spaces around {} in the reg_sequence;
- Always use Mu instead of mixture of Mu and MU;
- Don't error out if we do not recognize the part id;
- Make sure to deal with other errors than TIMEOUT in ad9739a_init().
[1]: https://lore.kernel.org/linux-iio/04e2a0569953792673319f7fcab3fe03e6670c03.camel@gmail.com/
---
Nuno Sa (7):
iio: buffer-dma: add iio_dmaengine_buffer_setup()
dt-bindings: iio: dac: add docs for AXI DAC IP
dt-bindings: iio: dac: add docs for AD9739A
iio: core: add get_iio_backend() callback
iio: backend: add new functionality
iio: dac: add support for AXI DAC IP core
iio: dac: support the ad9739a RF DAC
Paul Cercueil (4):
iio: buffer-dma: Rename iio_dma_buffer_data_available()
iio: buffer-dma: Enable buffer write support
iio: buffer-dmaengine: Support specifying buffer direction
iio: buffer-dmaengine: Enable write support
Documentation/ABI/testing/sysfs-bus-iio-ad9739a | 19 +
.../devicetree/bindings/iio/dac/adi,ad9739a.yaml | 94 +++
.../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 62 ++
MAINTAINERS | 17 +
drivers/iio/adc/adi-axi-adc.c | 16 +-
drivers/iio/buffer/industrialio-buffer-dma.c | 100 +++-
drivers/iio/buffer/industrialio-buffer-dmaengine.c | 83 +--
drivers/iio/dac/Kconfig | 37 ++
drivers/iio/dac/Makefile | 2 +
drivers/iio/dac/ad9739a.c | 454 +++++++++++++++
drivers/iio/dac/adi-axi-dac.c | 635 +++++++++++++++++++++
drivers/iio/industrialio-backend.c | 179 ++++++
include/linux/iio/backend.h | 49 ++
include/linux/iio/buffer-dma.h | 4 +-
include/linux/iio/buffer-dmaengine.h | 24 +-
include/linux/iio/iio.h | 2 +
16 files changed, 1698 insertions(+), 79 deletions(-)
---
base-commit: 6020ca4de8e5404b20f15a6d9873cd6eb5f6d8d6
change-id: 20240405-iio-backend-axi-dac-be99373b036b
--
Thanks!
- Nuno Sá
^ permalink raw reply
* [PATCH v2 09/11] iio: backend: add new functionality
From: Nuno Sa @ 2024-04-05 15:00 UTC (permalink / raw)
To: linux-iio, devicetree
Cc: Dragos Bogdan, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Olivier Moysan
In-Reply-To: <20240405-iio-backend-axi-dac-v2-0-293bab7d5552@analog.com>
This adds the needed backend ops for supporting a backend inerfacing
with an high speed dac. The new ops are:
* data_source_set();
* set_sampling_freq();
* extend_chan_spec();
* ext_info_set();
* ext_info_get().
Also to note the new helpers that are meant to be used by the backends
when extending an IIO channel (adding extended info):
* iio_backend_ext_info_set();
* iio_backend_ext_info_get().
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
---
drivers/iio/industrialio-backend.c | 179 +++++++++++++++++++++++++++++++++++++
include/linux/iio/backend.h | 49 ++++++++++
2 files changed, 228 insertions(+)
diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-backend.c
index 2fea2bbbe47f..ac554798897f 100644
--- a/drivers/iio/industrialio-backend.c
+++ b/drivers/iio/industrialio-backend.c
@@ -29,6 +29,7 @@
*
* Copyright (C) 2023-2024 Analog Devices Inc.
*/
+#include "asm-generic/errno-base.h"
#define dev_fmt(fmt) "iio-backend: " fmt
#include <linux/cleanup.h>
@@ -43,10 +44,12 @@
#include <linux/types.h>
#include <linux/iio/backend.h>
+#include <linux/iio/iio.h>
struct iio_backend {
struct list_head entry;
const struct iio_backend_ops *ops;
+ struct device *frontend_dev;
struct device *dev;
struct module *owner;
void *priv;
@@ -186,6 +189,44 @@ int iio_backend_data_format_set(struct iio_backend *back, unsigned int chan,
}
EXPORT_SYMBOL_NS_GPL(iio_backend_data_format_set, IIO_BACKEND);
+/**
+ * iio_backend_data_source_set - Select data source
+ * @back: Backend device
+ * @chan: Channel number
+ * @data: Data source
+ *
+ * A given backend may have different sources to stream/sync data. This allows
+ * to choose that source.
+ *
+ * RETURNS:
+ * 0 on success, negative error number on failure.
+ */
+int iio_backend_data_source_set(struct iio_backend *back, unsigned int chan,
+ enum iio_backend_data_source data)
+{
+ if (data >= IIO_BACKEND_DATA_SOURCE_MAX)
+ return -EINVAL;
+
+ return iio_backend_op_call(back, data_source_set, chan, data);
+}
+EXPORT_SYMBOL_NS_GPL(iio_backend_data_source_set, IIO_BACKEND);
+
+/**
+ * iio_backend_set_sampling_freq - Set channel sampling rate
+ * @back: Backend device
+ * @chan: Channel number
+ * @sample_rate_hz: Sample rate
+ *
+ * RETURNS:
+ * 0 on success, negative error number on failure.
+ */
+int iio_backend_set_sampling_freq(struct iio_backend *back, unsigned int chan,
+ u64 sample_rate_hz)
+{
+ return iio_backend_op_call(back, set_sample_rate, chan, sample_rate_hz);
+}
+EXPORT_SYMBOL_NS_GPL(iio_backend_set_sampling_freq, IIO_BACKEND);
+
static void iio_backend_free_buffer(void *arg)
{
struct iio_backend_buffer_pair *pair = arg;
@@ -231,6 +272,142 @@ int devm_iio_backend_request_buffer(struct device *dev,
}
EXPORT_SYMBOL_NS_GPL(devm_iio_backend_request_buffer, IIO_BACKEND);
+static struct iio_backend *iio_backend_from_indio_dev_parent(const struct device *dev)
+{
+ struct iio_backend *back = ERR_PTR(-ENODEV), *iter;
+
+ /*
+ * We deliberately go through all backends even after finding a match.
+ * The reason is that we want to catch frontend devices which have more
+ * than one backend in which case returning the first we find is bogus.
+ * For those cases, frontends need to explicitly define
+ * get_iio_backend() in struct iio_info.
+ */
+ guard(mutex)(&iio_back_lock);
+ list_for_each_entry(iter, &iio_back_list, entry) {
+ if (dev == iter->frontend_dev) {
+ if (!IS_ERR(back)) {
+ dev_warn(dev,
+ "Multiple backends! get_iio_backend() needs to be implemented");
+ return ERR_PTR(-ENODEV);
+ }
+
+ back = iter;
+ }
+ }
+
+ return back;
+}
+
+/**
+ * iio_backend_ext_info_get - IIO ext_info read callback
+ * @indio_dev: IIO device
+ * @private: Data private to the driver
+ * @chan: IIO channel
+ * @buf: Buffer where to place the attribute data
+ *
+ * This helper is intended to be used by backends that extend an IIO channel
+ * (through iio_backend_extend_chan_spec()) with extended info. In that case,
+ * backends are not supposed to give their own callbacks (as they would not have
+ * a way to get the backend from indio_dev). This is the getter.
+ *
+ * RETURNS:
+ * Number of bytes written to buf, negative error number on failure.
+ */
+ssize_t iio_backend_ext_info_get(struct iio_dev *indio_dev, uintptr_t private,
+ const struct iio_chan_spec *chan, char *buf)
+{
+ struct iio_backend *back;
+
+ if (indio_dev->info->get_iio_backend)
+ back = indio_dev->info->get_iio_backend(indio_dev, chan);
+ else
+ back = iio_backend_from_indio_dev_parent(indio_dev->dev.parent);
+ if (IS_ERR(back))
+ return PTR_ERR(back);
+
+ return iio_backend_op_call(back, ext_info_get, private, chan, buf);
+}
+EXPORT_SYMBOL_NS_GPL(iio_backend_ext_info_get, IIO_BACKEND);
+
+/**
+ * iio_backend_ext_info_set - IIO ext_info write callback
+ * @indio_dev: IIO device
+ * @private: Data private to the driver
+ * @chan: IIO channel
+ * @buf: Buffer holding the sysfs attribute
+ * @len: Buffer length
+ *
+ * This helper is intended to be used by backends that extend an IIO channel
+ * (trough iio_backend_extend_chan_spec()) with extended info. In that case,
+ * backends are not supposed to give their own callbacks (as they would not have
+ * a way to get the backend from indio_dev). This is the setter.
+ *
+ * RETURNS:
+ * Buffer length on success, negative error number on failure.
+ */
+ssize_t iio_backend_ext_info_set(struct iio_dev *indio_dev, uintptr_t private,
+ const struct iio_chan_spec *chan,
+ const char *buf, size_t len)
+{
+ struct iio_backend *back;
+
+ if (indio_dev->info->get_iio_backend)
+ back = indio_dev->info->get_iio_backend(indio_dev, chan);
+ else
+ back = iio_backend_from_indio_dev_parent(indio_dev->dev.parent);
+ if (IS_ERR(back))
+ return PTR_ERR(back);
+
+ return iio_backend_op_call(back, ext_info_set, private, chan, buf, len);
+}
+EXPORT_SYMBOL_NS_GPL(iio_backend_ext_info_set, IIO_BACKEND);
+
+/**
+ * iio_backend_extend_chan_spec - Extend an IIO channel
+ * @indio_dev: IIO device
+ * @back: Backend device
+ * @chan: IIO channel
+ *
+ * Some backends may have their own functionalities and hence capable of
+ * extending a frontend's channel.
+ *
+ * RETURNS:
+ * 0 on success, negative error number on failure.
+ */
+int iio_backend_extend_chan_spec(struct iio_dev *indio_dev,
+ struct iio_backend *back,
+ struct iio_chan_spec *chan)
+{
+ const struct iio_chan_spec_ext_info *frontend_ext_info = chan->ext_info;
+ const struct iio_chan_spec_ext_info *back_ext_info;
+ int ret;
+
+ ret = iio_backend_op_call(back, extend_chan_spec, chan);
+ if (ret)
+ return ret;
+ /*
+ * Let's keep things simple for now. Don't allow to overwrite the
+ * frontend's extended info. If ever needed, we can support appending
+ * it.
+ */
+ if (frontend_ext_info && chan->ext_info != frontend_ext_info)
+ return -EOPNOTSUPP;
+ if (!chan->ext_info)
+ return 0;
+
+ /* Don't allow backends to get creative and force their own handlers */
+ for (back_ext_info = chan->ext_info; back_ext_info->name; back_ext_info++) {
+ if (back_ext_info->read != iio_backend_ext_info_get)
+ return -EINVAL;
+ if (back_ext_info->write != iio_backend_ext_info_set)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(iio_backend_extend_chan_spec, IIO_BACKEND);
+
static void iio_backend_release(void *arg)
{
struct iio_backend *back = arg;
@@ -263,6 +440,8 @@ static int __devm_iio_backend_get(struct device *dev, struct iio_backend *back)
"Could not link to supplier(%s)\n",
dev_name(back->dev));
+ back->frontend_dev = dev;
+
dev_dbg(dev, "Found backend(%s) device\n", dev_name(back->dev));
return 0;
diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h
index a6d79381866e..9d144631134d 100644
--- a/include/linux/iio/backend.h
+++ b/include/linux/iio/backend.h
@@ -4,6 +4,7 @@
#include <linux/types.h>
+struct iio_chan_spec;
struct fwnode_handle;
struct iio_backend;
struct device;
@@ -15,6 +16,26 @@ enum iio_backend_data_type {
IIO_BACKEND_DATA_TYPE_MAX
};
+enum iio_backend_data_source {
+ IIO_BACKEND_INTERNAL_CONTINUOS_WAVE,
+ IIO_BACKEND_EXTERNAL,
+ IIO_BACKEND_DATA_SOURCE_MAX
+};
+
+/**
+ * IIO_BACKEND_EX_INFO - Helper for an IIO extended channel attribute
+ * @_name: Attribute name
+ * @_shared: Whether the attribute is shared between all channels
+ * @_what: Data private to the driver
+ */
+#define IIO_BACKEND_EX_INFO(_name, _shared, _what) { \
+ .name = (_name), \
+ .shared = (_shared), \
+ .read = iio_backend_ext_info_get, \
+ .write = iio_backend_ext_info_set, \
+ .private = (_what), \
+}
+
/**
* struct iio_backend_data_fmt - Backend data format
* @type: Data type.
@@ -35,8 +56,13 @@ struct iio_backend_data_fmt {
* @chan_enable: Enable one channel.
* @chan_disable: Disable one channel.
* @data_format_set: Configure the data format for a specific channel.
+ * @data_source_set: Configure the data source for a specific channel.
+ * @set_sample_rate: Configure the sampling rate for a specific channel.
* @request_buffer: Request an IIO buffer.
* @free_buffer: Free an IIO buffer.
+ * @extend_chan_spec: Extend an IIO channel.
+ * @ext_info_set: Extended info setter.
+ * @ext_info_get: Extended info getter.
**/
struct iio_backend_ops {
int (*enable)(struct iio_backend *back);
@@ -45,10 +71,21 @@ struct iio_backend_ops {
int (*chan_disable)(struct iio_backend *back, unsigned int chan);
int (*data_format_set)(struct iio_backend *back, unsigned int chan,
const struct iio_backend_data_fmt *data);
+ int (*data_source_set)(struct iio_backend *back, unsigned int chan,
+ enum iio_backend_data_source data);
+ int (*set_sample_rate)(struct iio_backend *back, unsigned int chan,
+ u64 sample_rate_hz);
struct iio_buffer *(*request_buffer)(struct iio_backend *back,
struct iio_dev *indio_dev);
void (*free_buffer)(struct iio_backend *back,
struct iio_buffer *buffer);
+ int (*extend_chan_spec)(struct iio_backend *back,
+ struct iio_chan_spec *chan);
+ int (*ext_info_set)(struct iio_backend *back, uintptr_t private,
+ const struct iio_chan_spec *chan,
+ const char *buf, size_t len);
+ int (*ext_info_get)(struct iio_backend *back, uintptr_t private,
+ const struct iio_chan_spec *chan, char *buf);
};
int iio_backend_chan_enable(struct iio_backend *back, unsigned int chan);
@@ -56,10 +93,22 @@ int iio_backend_chan_disable(struct iio_backend *back, unsigned int chan);
int devm_iio_backend_enable(struct device *dev, struct iio_backend *back);
int iio_backend_data_format_set(struct iio_backend *back, unsigned int chan,
const struct iio_backend_data_fmt *data);
+int iio_backend_data_source_set(struct iio_backend *back, unsigned int chan,
+ enum iio_backend_data_source data);
+int iio_backend_set_sampling_freq(struct iio_backend *back, unsigned int chan,
+ u64 sample_rate_hz);
int devm_iio_backend_request_buffer(struct device *dev,
struct iio_backend *back,
struct iio_dev *indio_dev);
+ssize_t iio_backend_ext_info_set(struct iio_dev *indio_dev, uintptr_t private,
+ const struct iio_chan_spec *chan,
+ const char *buf, size_t len);
+ssize_t iio_backend_ext_info_get(struct iio_dev *indio_dev, uintptr_t private,
+ const struct iio_chan_spec *chan, char *buf);
+int iio_backend_extend_chan_spec(struct iio_dev *indio_dev,
+ struct iio_backend *back,
+ struct iio_chan_spec *chan);
void *iio_backend_get_priv(const struct iio_backend *conv);
struct iio_backend *devm_iio_backend_get(struct device *dev, const char *name);
struct iio_backend *
--
2.44.0
^ permalink raw reply related
* [PATCH v2 10/11] iio: dac: add support for AXI DAC IP core
From: Nuno Sa @ 2024-04-05 15:00 UTC (permalink / raw)
To: linux-iio, devicetree
Cc: Dragos Bogdan, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Olivier Moysan
In-Reply-To: <20240405-iio-backend-axi-dac-v2-0-293bab7d5552@analog.com>
Support the Analog Devices Generic AXI DAC IP core. The IP core is used
for interfacing with digital-to-analog (DAC) converters that require either
a high-speed serial interface (JESD204B/C) or a source synchronous parallel
interface (LVDS/CMOS). Typically (for such devices) SPI will be used for
configuration only, while this IP core handles the streaming of data into
memory via DMA.
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
---
MAINTAINERS | 1 +
drivers/iio/dac/Kconfig | 21 ++
drivers/iio/dac/Makefile | 1 +
drivers/iio/dac/adi-axi-dac.c | 635 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 658 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 76e872e320d7..505f28dc6da6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1413,6 +1413,7 @@ L: linux-iio@vger.kernel.org
S: Supported
W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml
+F: drivers/iio/dac/adi-axi-dac.c
ANALOG DEVICES INC DMA DRIVERS
M: Lars-Peter Clausen <lars@metafoo.de>
diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig
index 34eb40bb9529..7c0a8caa9a34 100644
--- a/drivers/iio/dac/Kconfig
+++ b/drivers/iio/dac/Kconfig
@@ -131,6 +131,27 @@ config AD5624R_SPI
Say yes here to build support for Analog Devices AD5624R, AD5644R and
AD5664R converters (DAC). This driver uses the common SPI interface.
+config ADI_AXI_DAC
+ tristate "Analog Devices Generic AXI DAC IP core driver"
+ select IIO_BUFFER
+ select IIO_BUFFER_DMAENGINE
+ select REGMAP_MMIO
+ select IIO_BACKEND
+ help
+ Say yes here to build support for Analog Devices Generic
+ AXI DAC IP core. The IP core is used for interfacing with
+ digital-to-analog (DAC) converters that require either a high-speed
+ serial interface (JESD204B/C) or a source synchronous parallel
+ interface (LVDS/CMOS).
+ Typically (for such devices) SPI will be used for configuration only,
+ while this IP core handles the streaming of data into memory via DMA.
+
+ Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip
+ If unsure, say N (but it's safe to say "Y").
+
+ To compile this driver as a module, choose M here: the
+ module will be called adi-axi-dac.
+
config LTC2688
tristate "Analog Devices LTC2688 DAC spi driver"
depends on SPI
diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile
index 55bf89739d14..6bcaa65434b2 100644
--- a/drivers/iio/dac/Makefile
+++ b/drivers/iio/dac/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_AD5696_I2C) += ad5696-i2c.o
obj-$(CONFIG_AD7293) += ad7293.o
obj-$(CONFIG_AD7303) += ad7303.o
obj-$(CONFIG_AD8801) += ad8801.o
+obj-$(CONFIG_ADI_AXI_DAC) += adi-axi-dac.o
obj-$(CONFIG_CIO_DAC) += cio-dac.o
obj-$(CONFIG_DPOT_DAC) += dpot-dac.o
obj-$(CONFIG_DS4424) += ds4424.o
diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c
new file mode 100644
index 000000000000..9047c5aec0ff
--- /dev/null
+++ b/drivers/iio/dac/adi-axi-dac.c
@@ -0,0 +1,635 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Analog Devices Generic AXI DAC IP core
+ * Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip
+ *
+ * Copyright 2016-2024 Analog Devices Inc.
+ */
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/limits.h>
+#include <linux/kstrtox.h>
+#include <linux/math.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/units.h>
+
+#include <linux/fpga/adi-axi-common.h>
+#include <linux/iio/backend.h>
+#include <linux/iio/buffer-dmaengine.h>
+#include <linux/iio/buffer.h>
+#include <linux/iio/iio.h>
+
+/*
+ * Register definitions:
+ * https://wiki.analog.com/resources/fpga/docs/axi_dac_ip#register_map
+ */
+
+/* Base controls */
+#define AXI_DAC_REG_CONFIG 0x0c
+#define AXI_DDS_DISABLE BIT(6)
+
+ /* DAC controls */
+#define AXI_DAC_REG_RSTN 0x0040
+#define AXI_DAC_RSTN_CE_N BIT(2)
+#define AXI_DAC_RSTN_MMCM_RSTN BIT(1)
+#define AXI_DAC_RSTN_RSTN BIT(0)
+#define AXI_DAC_REG_CNTRL_1 0x0044
+#define AXI_DAC_SYNC BIT(0)
+#define AXI_DAC_REG_CNTRL_2 0x0048
+#define ADI_DAC_R1_MODE BIT(4)
+#define AXI_DAC_DRP_STATUS 0x0074
+#define AXI_DAC_DRP_LOCKED BIT(17)
+/* DAC Channel controls */
+#define AXI_DAC_REG_CHAN_CNTRL_1(c) (0x0400 + (c) * 0x40)
+#define AXI_DAC_REG_CHAN_CNTRL_3(c) (0x0408 + (c) * 0x40)
+#define AXI_DAC_SCALE_SIGN BIT(15)
+#define AXI_DAC_SCALE_INT BIT(14)
+#define AXI_DAC_SCALE GENMASK(14, 0)
+#define AXI_DAC_REG_CHAN_CNTRL_2(c) (0x0404 + (c) * 0x40)
+#define AXI_DAC_REG_CHAN_CNTRL_4(c) (0x040c + (c) * 0x40)
+#define AXI_DAC_PHASE GENMASK(31, 16)
+#define AXI_DAC_FREQUENCY GENMASK(15, 0)
+#define AXI_DAC_REG_CHAN_CNTRL_7(c) (0x0418 + (c) * 0x40)
+#define AXI_DAC_DATA_SEL GENMASK(3, 0)
+
+/* 360 degrees in rad */
+#define AXI_DAC_2_PI_MEGA 6283190
+enum {
+ AXI_DAC_DATA_INTERNAL_TONE,
+ AXI_DAC_DATA_DMA = 2,
+};
+
+struct axi_dac_state {
+ struct regmap *regmap;
+ struct device *dev;
+ /*
+ * lock to protect multiple accesses to the device registers and global
+ * data/variables.
+ */
+ struct mutex lock;
+ u64 dac_clk;
+ u32 reg_config;
+ bool int_tone;
+};
+
+static int axi_dac_enable(struct iio_backend *back)
+{
+ struct axi_dac_state *st = iio_backend_get_priv(back);
+ unsigned int __val;
+ int ret;
+
+ guard(mutex)(&st->lock);
+ ret = regmap_set_bits(st->regmap, AXI_DAC_REG_RSTN,
+ AXI_DAC_RSTN_MMCM_RSTN);
+ if (ret)
+ return ret;
+ /*
+ * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all
+ * designs really use it but if they don't we still get the lock bit
+ * set. So let's do it all the time so the code is generic.
+ */
+ ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS, __val,
+ __val & AXI_DAC_DRP_LOCKED, 100, 1000);
+ if (ret)
+ return ret;
+
+ return regmap_set_bits(st->regmap, AXI_DAC_REG_RSTN,
+ AXI_DAC_RSTN_RSTN | AXI_DAC_RSTN_MMCM_RSTN);
+}
+
+static void axi_dac_disable(struct iio_backend *back)
+{
+ struct axi_dac_state *st = iio_backend_get_priv(back);
+
+ guard(mutex)(&st->lock);
+ regmap_write(st->regmap, AXI_DAC_REG_RSTN, 0);
+}
+
+static struct iio_buffer *axi_dac_request_buffer(struct iio_backend *back,
+ struct iio_dev *indio_dev)
+{
+ struct axi_dac_state *st = iio_backend_get_priv(back);
+ const char *dma_name;
+
+ if (device_property_read_string(st->dev, "dma-names", &dma_name))
+ dma_name = "tx";
+
+ return iio_dmaengine_buffer_setup_ext(st->dev, indio_dev, dma_name,
+ IIO_BUFFER_DIRECTION_OUT);
+}
+
+static void axi_dac_free_buffer(struct iio_backend *back,
+ struct iio_buffer *buffer)
+{
+ iio_dmaengine_buffer_free(buffer);
+}
+
+enum {
+ AXI_DAC_FREQ_TONE_1,
+ AXI_DAC_FREQ_TONE_2,
+ AXI_DAC_SCALE_TONE_1,
+ AXI_DAC_SCALE_TONE_2,
+ AXI_DAC_PHASE_TONE_1,
+ AXI_DAC_PHASE_TONE_2,
+};
+
+static int __axi_dac_frequency_get(struct axi_dac_state *st, unsigned int chan,
+ unsigned int tone_2, unsigned int *freq)
+{
+ u32 reg, raw;
+ int ret;
+
+ if (!st->dac_clk) {
+ dev_err(st->dev, "Sampling rate is 0...\n");
+ return -EINVAL;
+ }
+
+ if (tone_2)
+ reg = AXI_DAC_REG_CHAN_CNTRL_4(chan);
+ else
+ reg = AXI_DAC_REG_CHAN_CNTRL_2(chan);
+
+ ret = regmap_read(st->regmap, reg, &raw);
+ if (ret)
+ return ret;
+
+ raw = FIELD_GET(AXI_DAC_FREQUENCY, raw);
+ *freq = DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16));
+
+ return 0;
+}
+
+static int axi_dac_frequency_get(struct axi_dac_state *st,
+ const struct iio_chan_spec *chan, char *buf,
+ unsigned int tone_2)
+{
+ unsigned int freq;
+ int ret;
+
+ scoped_guard(mutex, &st->lock) {
+ ret = __axi_dac_frequency_get(st, chan->channel, tone_2, &freq);
+ if (ret)
+ return ret;
+ }
+
+ return sysfs_emit(buf, "%u\n", freq);
+}
+
+static int axi_dac_scale_get(struct axi_dac_state *st,
+ const struct iio_chan_spec *chan, char *buf,
+ unsigned int tone_2)
+{
+ unsigned int scale, sign;
+ int ret, vals[2];
+ u32 reg, raw;
+
+ if (tone_2)
+ reg = AXI_DAC_REG_CHAN_CNTRL_3(chan->channel);
+ else
+ reg = AXI_DAC_REG_CHAN_CNTRL_1(chan->channel);
+
+ ret = regmap_read(st->regmap, reg, &raw);
+ if (ret)
+ return ret;
+
+ sign = FIELD_GET(AXI_DAC_SCALE_SIGN, raw);
+ raw = FIELD_GET(AXI_DAC_SCALE, raw);
+ scale = DIV_ROUND_CLOSEST_ULL((u64)raw * MEGA, AXI_DAC_SCALE_INT);
+
+ vals[0] = scale / MEGA;
+ vals[1] = scale % MEGA;
+
+ if (sign) {
+ vals[0] *= -1;
+ if (!vals[0])
+ vals[1] *= -1;
+ }
+
+ return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals),
+ vals);
+}
+
+static int axi_dac_phase_get(struct axi_dac_state *st,
+ const struct iio_chan_spec *chan, char *buf,
+ unsigned int tone_2)
+{
+ u32 reg, raw, phase;
+ int ret, vals[2];
+
+ if (tone_2)
+ reg = AXI_DAC_REG_CHAN_CNTRL_4(chan->channel);
+ else
+ reg = AXI_DAC_REG_CHAN_CNTRL_2(chan->channel);
+
+ ret = regmap_read(st->regmap, reg, &raw);
+ if (ret)
+ return ret;
+
+ raw = FIELD_GET(AXI_DAC_PHASE, raw);
+ phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX);
+
+ vals[0] = phase / MEGA;
+ vals[1] = phase % MEGA;
+
+ return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals),
+ vals);
+}
+
+static int __axi_dac_frequency_set(struct axi_dac_state *st, unsigned int chan,
+ u64 sample_rate, unsigned int freq,
+ unsigned int tone_2)
+{
+ u32 reg;
+ u16 raw;
+ int ret;
+
+ if (!sample_rate || freq > sample_rate / 2) {
+ dev_err(st->dev, "Invalid frequency(%u) dac_clk(%llu)\n",
+ freq, sample_rate);
+ return -EINVAL;
+ }
+
+ if (tone_2)
+ reg = AXI_DAC_REG_CHAN_CNTRL_4(chan);
+ else
+ reg = AXI_DAC_REG_CHAN_CNTRL_2(chan);
+
+ raw = DIV64_U64_ROUND_CLOSEST((u64)freq * BIT(16), sample_rate);
+
+ ret = regmap_update_bits(st->regmap, reg, AXI_DAC_FREQUENCY, raw);
+ if (ret)
+ return ret;
+
+ /* synchronize channels */
+ return regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC);
+}
+
+static int axi_dac_frequency_set(struct axi_dac_state *st,
+ const struct iio_chan_spec *chan,
+ const char *buf, size_t len, unsigned int tone_2)
+{
+ unsigned int freq;
+ int ret;
+
+ ret = kstrtou32(buf, 10, &freq);
+ if (ret)
+ return ret;
+
+ guard(mutex)(&st->lock);
+ ret = __axi_dac_frequency_set(st, chan->channel, st->dac_clk, freq,
+ tone_2);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
+static int axi_dac_scale_set(struct axi_dac_state *st,
+ const struct iio_chan_spec *chan,
+ const char *buf, size_t len, unsigned int tone_2)
+{
+ int integer, frac, scale;
+ u32 raw = 0, reg;
+ int ret;
+
+ ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac);
+ if (ret)
+ return ret;
+
+ scale = integer * MEGA + frac;
+ if (scale <= -2 * (int)MEGA || scale >= 2 * (int)MEGA)
+ return -EINVAL;
+
+ /* format is 1.1.14 (sign, integer and fractional bits) */
+ if (scale < 0) {
+ raw = FIELD_PREP(AXI_DAC_SCALE_SIGN, 1);
+ scale *= -1;
+ }
+
+ raw |= div_u64((u64)scale * AXI_DAC_SCALE_INT, MEGA);
+
+ if (tone_2)
+ reg = AXI_DAC_REG_CHAN_CNTRL_3(chan->channel);
+ else
+ reg = AXI_DAC_REG_CHAN_CNTRL_1(chan->channel);
+
+ guard(mutex)(&st->lock);
+ ret = regmap_write(st->regmap, reg, raw);
+ if (ret)
+ return ret;
+
+ /* synchronize channels */
+ ret = regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
+static int axi_dac_phase_set(struct axi_dac_state *st,
+ const struct iio_chan_spec *chan,
+ const char *buf, size_t len, unsigned int tone_2)
+{
+ int integer, frac, phase;
+ u32 raw, reg;
+ int ret;
+
+ ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac);
+ if (ret)
+ return ret;
+
+ phase = integer * MEGA + frac;
+ if (phase < 0 || phase > AXI_DAC_2_PI_MEGA)
+ return -EINVAL;
+
+ raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA);
+
+ if (tone_2)
+ reg = AXI_DAC_REG_CHAN_CNTRL_4(chan->channel);
+ else
+ reg = AXI_DAC_REG_CHAN_CNTRL_2(chan->channel);
+
+ guard(mutex)(&st->lock);
+ ret = regmap_update_bits(st->regmap, reg, AXI_DAC_PHASE,
+ FIELD_PREP(AXI_DAC_PHASE, raw));
+ if (ret)
+ return ret;
+
+ /* synchronize channels */
+ ret = regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
+static int axi_dac_ext_info_set(struct iio_backend *back, uintptr_t private,
+ const struct iio_chan_spec *chan,
+ const char *buf, size_t len)
+{
+ struct axi_dac_state *st = iio_backend_get_priv(back);
+
+ switch (private) {
+ case AXI_DAC_FREQ_TONE_1:
+ case AXI_DAC_FREQ_TONE_2:
+ return axi_dac_frequency_set(st, chan, buf, len,
+ private - AXI_DAC_FREQ_TONE_1);
+ case AXI_DAC_SCALE_TONE_1:
+ case AXI_DAC_SCALE_TONE_2:
+ return axi_dac_scale_set(st, chan, buf, len,
+ private - AXI_DAC_SCALE_TONE_1);
+ case AXI_DAC_PHASE_TONE_1:
+ case AXI_DAC_PHASE_TONE_2:
+ return axi_dac_phase_set(st, chan, buf, len,
+ private - AXI_DAC_PHASE_TONE_2);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int axi_dac_ext_info_get(struct iio_backend *back, uintptr_t private,
+ const struct iio_chan_spec *chan, char *buf)
+{
+ struct axi_dac_state *st = iio_backend_get_priv(back);
+
+ switch (private) {
+ case AXI_DAC_FREQ_TONE_1:
+ case AXI_DAC_FREQ_TONE_2:
+ return axi_dac_frequency_get(st, chan, buf,
+ private - AXI_DAC_FREQ_TONE_1);
+ case AXI_DAC_SCALE_TONE_1:
+ case AXI_DAC_SCALE_TONE_2:
+ return axi_dac_scale_get(st, chan, buf,
+ private - AXI_DAC_SCALE_TONE_1);
+ case AXI_DAC_PHASE_TONE_1:
+ case AXI_DAC_PHASE_TONE_2:
+ return axi_dac_phase_get(st, chan, buf,
+ private - AXI_DAC_PHASE_TONE_1);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static const struct iio_chan_spec_ext_info axi_dac_ext_info[] = {
+ IIO_BACKEND_EX_INFO("frequency0", IIO_SEPARATE, AXI_DAC_FREQ_TONE_1),
+ IIO_BACKEND_EX_INFO("frequency1", IIO_SEPARATE, AXI_DAC_FREQ_TONE_2),
+ IIO_BACKEND_EX_INFO("scale0", IIO_SEPARATE, AXI_DAC_SCALE_TONE_1),
+ IIO_BACKEND_EX_INFO("scale1", IIO_SEPARATE, AXI_DAC_SCALE_TONE_2),
+ IIO_BACKEND_EX_INFO("phase0", IIO_SEPARATE, AXI_DAC_PHASE_TONE_1),
+ IIO_BACKEND_EX_INFO("phase1", IIO_SEPARATE, AXI_DAC_PHASE_TONE_2),
+ {}
+};
+
+static int axi_dac_extend_chan(struct iio_backend *back,
+ struct iio_chan_spec *chan)
+{
+ struct axi_dac_state *st = iio_backend_get_priv(back);
+
+ if (chan->type != IIO_ALTVOLTAGE)
+ return -EINVAL;
+ if (st->reg_config & AXI_DDS_DISABLE)
+ /* nothing to extend */
+ return 0;
+
+ chan->ext_info = axi_dac_ext_info;
+
+ return 0;
+}
+
+static int axi_dac_data_source_set(struct iio_backend *back, unsigned int chan,
+ enum iio_backend_data_source data)
+{
+ struct axi_dac_state *st = iio_backend_get_priv(back);
+
+ switch (data) {
+ case IIO_BACKEND_INTERNAL_CONTINUOS_WAVE:
+ return regmap_update_bits(st->regmap,
+ AXI_DAC_REG_CHAN_CNTRL_7(chan),
+ AXI_DAC_DATA_SEL,
+ AXI_DAC_DATA_INTERNAL_TONE);
+ case IIO_BACKEND_EXTERNAL:
+ return regmap_update_bits(st->regmap,
+ AXI_DAC_REG_CHAN_CNTRL_7(chan),
+ AXI_DAC_DATA_SEL, AXI_DAC_DATA_DMA);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int axi_dac_set_sample_rate(struct iio_backend *back, unsigned int chan,
+ u64 sample_rate)
+{
+ struct axi_dac_state *st = iio_backend_get_priv(back);
+ unsigned int freq;
+ int ret, tone;
+
+ if (!sample_rate)
+ return -EINVAL;
+ if (st->reg_config & AXI_DDS_DISABLE)
+ /* sample_rate has no meaning if DDS is disabled */
+ return 0;
+
+ guard(mutex)(&st->lock);
+ /*
+ * If dac_clk is 0 then this must be the first time we're being notified
+ * about the interface sample rate. Hence, just update our internal
+ * variable and bail... If it's not 0, then we get the current DDS
+ * frequency (for the old rate) and update the registers for the new
+ * sample rate.
+ */
+ if (!st->dac_clk) {
+ st->dac_clk = sample_rate;
+ return 0;
+ }
+
+ for (tone = 0; tone <= AXI_DAC_FREQ_TONE_2; tone++) {
+ ret = __axi_dac_frequency_get(st, chan, tone, &freq);
+ if (ret)
+ return ret;
+
+ ret = __axi_dac_frequency_set(st, chan, sample_rate, tone, freq);
+ if (ret)
+ return ret;
+ }
+
+ st->dac_clk = sample_rate;
+
+ return 0;
+}
+
+static const struct iio_backend_ops axi_dac_generic = {
+ .enable = axi_dac_enable,
+ .disable = axi_dac_disable,
+ .request_buffer = axi_dac_request_buffer,
+ .free_buffer = axi_dac_free_buffer,
+ .extend_chan_spec = axi_dac_extend_chan,
+ .ext_info_set = axi_dac_ext_info_set,
+ .ext_info_get = axi_dac_ext_info_get,
+ .data_source_set = axi_dac_data_source_set,
+ .set_sample_rate = axi_dac_set_sample_rate,
+};
+
+static const struct regmap_config axi_dac_regmap_config = {
+ .val_bits = 32,
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x0800,
+};
+
+static int axi_dac_probe(struct platform_device *pdev)
+{
+ const unsigned int *expected_ver;
+ struct axi_dac_state *st;
+ void __iomem *base;
+ unsigned int ver;
+ struct clk *clk;
+ int ret;
+
+ st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return -ENOMEM;
+
+ expected_ver = device_get_match_data(&pdev->dev);
+ if (!expected_ver)
+ return -ENODEV;
+
+ clk = devm_clk_get_enabled(&pdev->dev, NULL);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ st->dev = &pdev->dev;
+ st->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &axi_dac_regmap_config);
+ if (IS_ERR(st->regmap))
+ return PTR_ERR(st->regmap);
+
+ /*
+ * Force disable the core. Up to the frontend to enable us. And we can
+ * still read/write registers...
+ */
+ ret = regmap_write(st->regmap, AXI_DAC_REG_RSTN, 0);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver);
+ if (ret)
+ return ret;
+
+ if (ADI_AXI_PCORE_VER_MAJOR(ver) != ADI_AXI_PCORE_VER_MAJOR(*expected_ver)) {
+ dev_err(&pdev->dev,
+ "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
+ ADI_AXI_PCORE_VER_MAJOR(*expected_ver),
+ ADI_AXI_PCORE_VER_MINOR(*expected_ver),
+ ADI_AXI_PCORE_VER_PATCH(*expected_ver),
+ ADI_AXI_PCORE_VER_MAJOR(ver),
+ ADI_AXI_PCORE_VER_MINOR(ver),
+ ADI_AXI_PCORE_VER_PATCH(ver));
+ return -ENODEV;
+ }
+
+ /* Let's get the core read only configuration */
+ ret = regmap_read(st->regmap, AXI_DAC_REG_CONFIG, &st->reg_config);
+ if (ret)
+ return ret;
+
+ /*
+ * In some designs, setting the R1_MODE bit to 0 (which is the default
+ * value) causes all channels of the frontend to be routed to the same
+ * DMA (so they are sampled together). This is for things like
+ * Multiple-Input and Multiple-Output (MIMO). As most of the times we
+ * want independent channels let's override the core's default value and
+ * set the R1_MODE bit.
+ */
+ ret = regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_2, ADI_DAC_R1_MODE);
+ if (ret)
+ return ret;
+
+ mutex_init(&st->lock);
+ ret = devm_iio_backend_register(&pdev->dev, &axi_dac_generic, st);
+ if (ret)
+ return ret;
+
+ dev_info(&pdev->dev, "AXI DAC IP core (%d.%.2d.%c) probed\n",
+ ADI_AXI_PCORE_VER_MAJOR(ver),
+ ADI_AXI_PCORE_VER_MINOR(ver),
+ ADI_AXI_PCORE_VER_PATCH(ver));
+
+ return 0;
+}
+
+static unsigned int axi_dac_9_1_b_info = ADI_AXI_PCORE_VER(9, 1, 'b');
+
+static const struct of_device_id axi_dac_of_match[] = {
+ { .compatible = "adi,axi-dac-9.1.b", .data = &axi_dac_9_1_b_info },
+ {}
+};
+MODULE_DEVICE_TABLE(of, axi_dac_of_match);
+
+static struct platform_driver axi_dac_driver = {
+ .driver = {
+ .name = "adi-axi-dac",
+ .of_match_table = axi_dac_of_match,
+ },
+ .probe = axi_dac_probe,
+};
+module_platform_driver(axi_dac_driver);
+
+MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
+MODULE_DESCRIPTION("Analog Devices Generic AXI DAC IP core driver");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS(IIO_DMAENGINE_BUFFER);
+MODULE_IMPORT_NS(IIO_BACKEND);
--
2.44.0
^ permalink raw reply related
* [PATCH v2 05/11] iio: buffer-dmaengine: Enable write support
From: Nuno Sa @ 2024-04-05 15:00 UTC (permalink / raw)
To: linux-iio, devicetree
Cc: Dragos Bogdan, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Olivier Moysan, Paul Cercueil, Alexandru Ardelean
In-Reply-To: <20240405-iio-backend-axi-dac-v2-0-293bab7d5552@analog.com>
From: Paul Cercueil <paul@crapouillou.net>
Use the iio_dma_buffer_write() and iio_dma_buffer_space_available()
functions provided by the buffer-dma core, to enable write support in
the buffer-dmaengine code.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Alexandru Ardelean <ardeleanalex@gmail.com>
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
---
drivers/iio/buffer/industrialio-buffer-dmaengine.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iio/buffer/industrialio-buffer-dmaengine.c b/drivers/iio/buffer/industrialio-buffer-dmaengine.c
index 051e1758e020..e5492572b248 100644
--- a/drivers/iio/buffer/industrialio-buffer-dmaengine.c
+++ b/drivers/iio/buffer/industrialio-buffer-dmaengine.c
@@ -123,12 +123,14 @@ static void iio_dmaengine_buffer_release(struct iio_buffer *buf)
static const struct iio_buffer_access_funcs iio_dmaengine_buffer_ops = {
.read = iio_dma_buffer_read,
+ .write = iio_dma_buffer_write,
.set_bytes_per_datum = iio_dma_buffer_set_bytes_per_datum,
.set_length = iio_dma_buffer_set_length,
.request_update = iio_dma_buffer_request_update,
.enable = iio_dma_buffer_enable,
.disable = iio_dma_buffer_disable,
.data_available = iio_dma_buffer_usage,
+ .space_available = iio_dma_buffer_usage,
.release = iio_dmaengine_buffer_release,
.modes = INDIO_BUFFER_HARDWARE,
--
2.44.0
^ permalink raw reply related
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