* [PATCH v2 02/11] spi: dt-bindings: cdns,qspi-nor: sort compatibles alphabetically
From: Théo Lebrun @ 2024-04-05 15:02 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vaishnav Achath, Thomas Bogendoerfer, Rob Herring
Cc: linux-spi, devicetree, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Thomas Petazzoni,
Tawfik Bayouk, Théo Lebrun
In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com>
Compatibles are ordered by date of addition.
Switch to (deterministic) alphabetical ordering.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index 5509c126b1cf..e53d443c6f93 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -79,13 +79,13 @@ properties:
- items:
- enum:
- amd,pensando-elba-qspi
- - mobileye,eyeq5-ospi
- - ti,k2g-qspi
- - ti,am654-ospi
- intel,lgm-qspi
- - xlnx,versal-ospi-1.0
- intel,socfpga-qspi
+ - mobileye,eyeq5-ospi
- starfive,jh7110-qspi
+ - ti,am654-ospi
+ - ti,k2g-qspi
+ - xlnx,versal-ospi-1.0
- const: cdns,qspi-nor
- const: cdns,qspi-nor
--
2.44.0
^ permalink raw reply related
* [PATCH v2 03/11] spi: cadence-qspi: allow building for MIPS
From: Théo Lebrun @ 2024-04-05 15:02 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vaishnav Achath, Thomas Bogendoerfer, Rob Herring
Cc: linux-spi, devicetree, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Thomas Petazzoni,
Tawfik Bayouk, Théo Lebrun
In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com>
The Cadence QSPI Controller driver is used on Mobileye EyeQ5 platform.
Allow building on MIPS.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
drivers/spi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bc7021da2fe9..548af3d9e30d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -246,7 +246,7 @@ config SPI_CADENCE
config SPI_CADENCE_QUADSPI
tristate "Cadence Quad SPI controller"
- depends on OF && (ARM || ARM64 || X86 || RISCV || COMPILE_TEST)
+ depends on OF && (ARM || ARM64 || X86 || RISCV || MIPS || COMPILE_TEST)
help
Enable support for the Cadence Quad SPI Flash controller.
--
2.44.0
^ permalink raw reply related
* [PATCH v2 04/11] spi: cadence-qspi: store device data pointer in private struct
From: Théo Lebrun @ 2024-04-05 15:02 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vaishnav Achath, Thomas Bogendoerfer, Rob Herring
Cc: linux-spi, devicetree, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Thomas Petazzoni,
Tawfik Bayouk, Théo Lebrun
In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com>
Avoid of_device_get_match_data() call on each IRQ and each read
operation. Store pointer in `struct cqspi_st` device instance.
End-to-end performance measurements improve with this patch. On a given
octal flash, reading 235M over UBIFS is ~3.4% faster. During that read,
the average cqspi_exec_mem_op() call goes from 85.4µs to 80.7µs
according to ftrace. The worst case goes from 622.4µs to 615.2µs.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
drivers/spi/spi-cadence-quadspi.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 350b3dab3a05..abc1c35929cc 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -102,6 +102,8 @@ struct cqspi_st {
bool apb_ahb_hazard;
bool is_jh7110; /* Flag for StarFive JH7110 SoC */
+
+ const struct cqspi_driver_platdata *ddata;
};
struct cqspi_driver_platdata {
@@ -334,11 +336,8 @@ static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
{
struct cqspi_st *cqspi = dev;
+ const struct cqspi_driver_platdata *ddata = cqspi->ddata;
unsigned int irq_status;
- struct device *device = &cqspi->pdev->dev;
- const struct cqspi_driver_platdata *ddata;
-
- ddata = of_device_get_match_data(device);
/* Read interrupt status */
irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
@@ -1358,16 +1357,13 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
const struct spi_mem_op *op)
{
struct cqspi_st *cqspi = f_pdata->cqspi;
- struct device *dev = &cqspi->pdev->dev;
- const struct cqspi_driver_platdata *ddata;
+ const struct cqspi_driver_platdata *ddata = cqspi->ddata;
loff_t from = op->addr.val;
size_t len = op->data.nbytes;
u_char *buf = op->data.buf.in;
u64 dma_align = (u64)(uintptr_t)buf;
int ret;
- ddata = of_device_get_match_data(dev);
-
ret = cqspi_read_setup(f_pdata, op);
if (ret)
return ret;
@@ -1822,7 +1818,8 @@ static int cqspi_probe(struct platform_device *pdev)
/* write completion is supported by default */
cqspi->wr_completion = true;
- ddata = of_device_get_match_data(dev);
+ ddata = of_device_get_match_data(dev);
+ cqspi->ddata = ddata;
if (ddata) {
if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
--
2.44.0
^ permalink raw reply related
* [PATCH v2 05/11] spi: cadence-qspi: add FIFO depth detection quirk
From: Théo Lebrun @ 2024-04-05 15:02 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vaishnav Achath, Thomas Bogendoerfer, Rob Herring
Cc: linux-spi, devicetree, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Thomas Petazzoni,
Tawfik Bayouk, Théo Lebrun
In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com>
Use hardware ability to read the FIFO depth thanks to
CQSPI_REG_SRAMPARTITION that is partially read-only. Keep current
behavior identical for existing compatibles.
Hide feature behind a flag. If unset and detected value is different
from the devicetree-provided value, warn.
Move probe cqspi->ddata assignment prior to cqspi_of_get_pdata() call.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
drivers/spi/spi-cadence-quadspi.c | 38 ++++++++++++++++++++++++++++++++------
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index abc1c35929cc..04a473fafe43 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -42,6 +42,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX);
#define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)
#define CQSPI_SLOW_SRAM BIT(4)
#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
+#define CQSPI_DETECT_FIFO_DEPTH BIT(6)
/* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0)
@@ -1500,13 +1501,15 @@ static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
{
+ const struct cqspi_driver_platdata *ddata = cqspi->ddata;
struct device *dev = &cqspi->pdev->dev;
struct device_node *np = dev->of_node;
u32 id[2];
cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
- if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
+ if (!(ddata && ddata->quirks & CQSPI_DETECT_FIFO_DEPTH) &&
+ of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
dev_err(dev, "couldn't determine fifo-depth\n");
return -ENXIO;
}
@@ -1538,8 +1541,6 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
{
u32 reg;
- cqspi_controller_enable(cqspi, 0);
-
/* Configure the remap address register, no remap */
writel(0, cqspi->iobase + CQSPI_REG_REMAP);
@@ -1573,8 +1574,29 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
reg |= CQSPI_REG_CONFIG_DMA_MASK;
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
}
+}
- cqspi_controller_enable(cqspi, 1);
+static void cqspi_controller_detect_fifo_depth(struct cqspi_st *cqspi)
+{
+ const struct cqspi_driver_platdata *ddata = cqspi->ddata;
+ struct device *dev = &cqspi->pdev->dev;
+ u32 reg, fifo_depth;
+
+ /*
+ * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N
+ * the FIFO depth.
+ */
+ writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
+ reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION);
+ fifo_depth = reg + 1;
+
+ if (ddata && ddata->quirks & CQSPI_DETECT_FIFO_DEPTH) {
+ cqspi->fifo_depth = fifo_depth;
+ dev_dbg(dev, "using FIFO depth of %u\n", fifo_depth);
+ } else if (fifo_depth != cqspi->fifo_depth) {
+ dev_warn(dev, "detected FIFO depth (%u) different from config (%u)\n",
+ fifo_depth, cqspi->fifo_depth);
+ }
}
static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
@@ -1727,6 +1749,7 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->pdev = pdev;
cqspi->host = host;
cqspi->is_jh7110 = false;
+ cqspi->ddata = ddata = of_device_get_match_data(dev);
platform_set_drvdata(pdev, cqspi);
/* Obtain configuration from OF. */
@@ -1818,8 +1841,6 @@ static int cqspi_probe(struct platform_device *pdev)
/* write completion is supported by default */
cqspi->wr_completion = true;
- ddata = of_device_get_match_data(dev);
- cqspi->ddata = ddata;
if (ddata) {
if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
@@ -1861,7 +1882,10 @@ static int cqspi_probe(struct platform_device *pdev)
}
cqspi_wait_idle(cqspi);
+ cqspi_controller_enable(cqspi, 0);
+ cqspi_controller_detect_fifo_depth(cqspi);
cqspi_controller_init(cqspi);
+ cqspi_controller_enable(cqspi, 1);
cqspi->current_cs = -1;
cqspi->sclk = 0;
@@ -1944,7 +1968,9 @@ static int cqspi_runtime_resume(struct device *dev)
clk_prepare_enable(cqspi->clk);
cqspi_wait_idle(cqspi);
+ cqspi_controller_enable(cqspi, 0);
cqspi_controller_init(cqspi);
+ cqspi_controller_enable(cqspi, 1);
cqspi->current_cs = -1;
cqspi->sclk = 0;
--
2.44.0
^ permalink raw reply related
* [PATCH v2 06/11] spi: cadence-qspi: minimise register accesses on each op if !DTR
From: Théo Lebrun @ 2024-04-05 15:02 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vaishnav Achath, Thomas Bogendoerfer, Rob Herring
Cc: linux-spi, devicetree, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Thomas Petazzoni,
Tawfik Bayouk, Théo Lebrun
In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com>
cqspi_enable_dtr() is called for each operation, commands or not, reads
or writes. It writes CQSPI_REG_CONFIG then waits for idle (three
successful reads). Skip that in the no-DTR case if DTR is already
disabled.
It cannot be skipped in the DTR case as cqspi_setup_opcode_ext() writes
to a register and we must wait for idle state.
According to ftrace, the average cqspi_exec_mem_op() call goes from
85.4µs to 83.6µs when reading 235M over UBIFS on an octal flash.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
drivers/spi/spi-cadence-quadspi.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 04a473fafe43..55d20d565fe5 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -492,8 +492,11 @@ static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
if (ret)
return ret;
} else {
- reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
- reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
+ unsigned int mask = CQSPI_REG_CONFIG_DTR_PROTO | CQSPI_REG_CONFIG_DUAL_OPCODE;
+ /* Shortcut if DTR is already disabled. */
+ if ((reg & mask) == 0)
+ return 0;
+ reg &= ~mask;
}
writel(reg, reg_base + CQSPI_REG_CONFIG);
--
2.44.0
^ permalink raw reply related
* [PATCH v2 07/11] spi: cadence-qspi: add no-IRQ mode to indirect reads
From: Théo Lebrun @ 2024-04-05 15:02 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vaishnav Achath, Thomas Bogendoerfer, Rob Herring
Cc: linux-spi, devicetree, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Thomas Petazzoni,
Tawfik Bayouk, Théo Lebrun
In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com>
Support reads through polling, without any IRQ. The main reason is
performance; profiling shows that the first IRQ comes quickly on our
specific hardware. Once this IRQ arrives, we poll until all data is
retrieved. Avoid initial sleep to reduce IRQ count.
Hide this behavior behind a quirk flag.
This is confirmed through micro-benchmarks, but also end-to-end
performance tests. Mobileye EyeQ5, octal flash, reading 235M on a UBIFS
filesystem:
- No optimizations, ~10.34s, ~22.7 MB/s, 199230 IRQs
- CQSPI_SLOW_SRAM, ~10.34s, ~22.7 MB/s, 70284 IRQs
- CQSPI_RD_NO_IRQ, ~9.37s, ~25.1 MB/s, 521 IRQs
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
drivers/spi/spi-cadence-quadspi.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 55d20d565fe5..ebb8c35f50fd 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -43,6 +43,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX);
#define CQSPI_SLOW_SRAM BIT(4)
#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
#define CQSPI_DETECT_FIFO_DEPTH BIT(6)
+#define CQSPI_RD_NO_IRQ BIT(7)
/* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0)
@@ -703,6 +704,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
const size_t n_rx)
{
struct cqspi_st *cqspi = f_pdata->cqspi;
+ bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ);
struct device *dev = &cqspi->pdev->dev;
void __iomem *reg_base = cqspi->iobase;
void __iomem *ahb_base = cqspi->ahb_base;
@@ -726,17 +728,20 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
* all the read interrupts disabled for max performance.
*/
- if (!cqspi->slow_sram)
+ if (use_irq && cqspi->slow_sram)
+ writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
+ else if (use_irq)
writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
else
- writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
+ writel(0, reg_base + CQSPI_REG_IRQMASK);
reinit_completion(&cqspi->transfer_complete);
writel(CQSPI_REG_INDIRECTRD_START_MASK,
reg_base + CQSPI_REG_INDIRECTRD);
while (remaining > 0) {
- if (!wait_for_completion_timeout(&cqspi->transfer_complete,
+ if (use_irq &&
+ !wait_for_completion_timeout(&cqspi->transfer_complete,
msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
ret = -ETIMEDOUT;
@@ -778,7 +783,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
bytes_to_read = cqspi_get_rd_sram_level(cqspi);
}
- if (remaining > 0) {
+ if (use_irq && remaining > 0) {
reinit_completion(&cqspi->transfer_complete);
if (cqspi->slow_sram)
writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
--
2.44.0
^ permalink raw reply related
* [PATCH v2 08/11] spi: cadence-qspi: add early busywait to cqspi_wait_for_bit()
From: Théo Lebrun @ 2024-04-05 15:02 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vaishnav Achath, Thomas Bogendoerfer, Rob Herring
Cc: linux-spi, devicetree, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Thomas Petazzoni,
Tawfik Bayouk, Théo Lebrun
In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com>
If the CQSPI_BUSYWAIT_EARLY quirk flag is on, call
readl_relaxed_poll_timeout() with no sleep at the start of
cqspi_wait_for_bit(). If its short timeout expires, a sleeping
readl_relaxed_poll_timeout() call takes the relay.
Behavior is hidden behind a quirk flag to keep the previous behavior the
same on all platforms.
The reason is to avoid hrtimer interrupts on the system. All read
operations take less than 100µs.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
drivers/spi/spi-cadence-quadspi.c | 34 +++++++++++++++++++++++++---------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index ebb8c35f50fd..230aad490e03 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -44,6 +44,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX);
#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
#define CQSPI_DETECT_FIFO_DEPTH BIT(6)
#define CQSPI_RD_NO_IRQ BIT(7)
+#define CQSPI_BUSYWAIT_EARLY BIT(8)
/* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0)
@@ -110,7 +111,7 @@ struct cqspi_st {
struct cqspi_driver_platdata {
u32 hwcaps_mask;
- u8 quirks;
+ u16 quirks;
int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata,
u_char *rxbuf, loff_t from_addr, size_t n_rx);
u32 (*get_dma_status)(struct cqspi_st *cqspi);
@@ -121,6 +122,7 @@ struct cqspi_driver_platdata {
/* Operation timeout value */
#define CQSPI_TIMEOUT_MS 500
#define CQSPI_READ_TIMEOUT_MS 10
+#define CQSPI_BUSYWAIT_TIMEOUT_US 500
/* Runtime_pm autosuspend delay */
#define CQSPI_AUTOSUSPEND_TIMEOUT 2000
@@ -299,13 +301,27 @@ struct cqspi_driver_platdata {
#define CQSPI_REG_VERSAL_DMA_VAL 0x602
-static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
+static int cqspi_wait_for_bit(const struct cqspi_driver_platdata *ddata,
+ void __iomem *reg, const u32 mask, bool clr,
+ bool busywait)
{
+ u64 timeout_us = CQSPI_TIMEOUT_MS * USEC_PER_MSEC;
u32 val;
+ if (busywait && ddata && ddata->quirks & CQSPI_BUSYWAIT_EARLY) {
+ int ret = readl_relaxed_poll_timeout(reg, val,
+ (((clr ? ~val : val) & mask) == mask),
+ 0, CQSPI_BUSYWAIT_TIMEOUT_US);
+
+ if (ret != -ETIMEDOUT)
+ return ret;
+
+ timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US;
+ }
+
return readl_relaxed_poll_timeout(reg, val,
(((clr ? ~val : val) & mask) == mask),
- 10, CQSPI_TIMEOUT_MS * 1000);
+ 10, timeout_us);
}
static bool cqspi_is_idle(struct cqspi_st *cqspi)
@@ -435,8 +451,8 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
writel(reg, reg_base + CQSPI_REG_CMDCTRL);
/* Polling for completion. */
- ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
- CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
+ ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL,
+ CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1, true);
if (ret) {
dev_err(&cqspi->pdev->dev,
"Flash command execution timed out.\n");
@@ -791,8 +807,8 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
}
/* Check indirect done status */
- ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
- CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
+ ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD,
+ CQSPI_REG_INDIRECTRD_DONE_MASK, 0, true);
if (ret) {
dev_err(dev, "Indirect read completion error (%i)\n", ret);
goto failrd;
@@ -1092,8 +1108,8 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
}
/* Check indirect done status */
- ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
- CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
+ ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR,
+ CQSPI_REG_INDIRECTWR_DONE_MASK, 0, false);
if (ret) {
dev_err(dev, "Indirect write completion error (%i)\n", ret);
goto failwr;
--
2.44.0
^ permalink raw reply related
* [PATCH v2 09/11] spi: cadence-qspi: add mobileye,eyeq5-ospi compatible
From: Théo Lebrun @ 2024-04-05 15:02 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vaishnav Achath, Thomas Bogendoerfer, Rob Herring
Cc: linux-spi, devicetree, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Thomas Petazzoni,
Tawfik Bayouk, Théo Lebrun
In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com>
Declare a new mobileye,eyeq5-ospi compatible. Exploit quirk flags:
detect FIFO depth through SRAMPARTITION register; avoid IRQs during
read operations.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
drivers/spi/spi-cadence-quadspi.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 230aad490e03..11f54f507787 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -2059,6 +2059,13 @@ static const struct cqspi_driver_platdata pensando_cdns_qspi = {
.quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE,
};
+static const struct cqspi_driver_platdata mobileye_eyeq5_ospi = {
+ .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
+ .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION |
+ CQSPI_DETECT_FIFO_DEPTH | CQSPI_RD_NO_IRQ |
+ CQSPI_BUSYWAIT_EARLY,
+};
+
static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
@@ -2092,6 +2099,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "amd,pensando-elba-qspi",
.data = &pensando_cdns_qspi,
},
+ {
+ .compatible = "mobileye,eyeq5-ospi",
+ .data = &mobileye_eyeq5_ospi,
+ },
{ /* end of table */ }
};
--
2.44.0
^ permalink raw reply related
* [PATCH v2 10/11] MIPS: mobileye: eyeq5: Add SPI-NOR controller node
From: Théo Lebrun @ 2024-04-05 15:02 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vaishnav Achath, Thomas Bogendoerfer, Rob Herring
Cc: linux-spi, devicetree, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Thomas Petazzoni,
Tawfik Bayouk, Théo Lebrun
In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com>
Add Cadence Quad SPI controller node to EyeQ5 SoC devicetree.
Octal is supported.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index 8d4f65ec912d..1543c2b9bcb6 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -158,6 +158,21 @@ timer {
clocks = <&core0_clk>;
};
};
+
+ ospi: spi@2100000 {
+ compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor";
+ reg = <0 0x2100000 0x0 0x1000>,
+ <0 0x10000000 0x0 0x8000000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks EQ5C_DIV_OSPI>;
+ assigned-clocks = <&clocks EQ5C_DIV_OSPI>;
+ assigned-clock-rates = <167000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ };
};
};
--
2.44.0
^ permalink raw reply related
* [PATCH v2 11/11] MIPS: mobileye: eyeq5: add octal flash node to eval board DTS
From: Théo Lebrun @ 2024-04-05 15:02 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vaishnav Achath, Thomas Bogendoerfer, Rob Herring
Cc: linux-spi, devicetree, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Thomas Petazzoni,
Tawfik Bayouk, Théo Lebrun
In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com>
Add SPI-NOR octal flash node to evaluation board devicetree.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
index 6898b2d8267d..0e5fee7b680c 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
+++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
@@ -21,3 +21,18 @@ memory@0 {
<0x8 0x02000000 0x0 0x7E000000>;
};
};
+
+&ospi {
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* chip select */
+
+ spi-max-frequency = <40000000>;
+ spi-rx-bus-width = <8>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <400>;
+ cdns,tsd2d-ns = <400>;
+ cdns,tchsh-ns = <125>;
+ cdns,tslch-ns = <50>;
+ };
+};
--
2.44.0
^ permalink raw reply related
* Re: [PATCH v15 2/8] phy: Add HDMI configuration options
From: Dmitry Baryshkov @ 2024-04-05 15:09 UTC (permalink / raw)
To: Vinod Koul
Cc: Maxime Ripard, Alexander Stein, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
David Airlie, Daniel Vetter, Maarten Lankhorst, Thomas Zimmermann,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kishon Vijay Abraham I, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Sandor Yu, dri-devel,
devicetree, linux-kernel, linux-phy, imx, linux-arm-kernel, linux
In-Reply-To: <ZhAJridEyhUeFVr0@matsya>
On Fri, Apr 05, 2024 at 07:54:46PM +0530, Vinod Koul wrote:
> On 06-03-24, 15:48, Maxime Ripard wrote:
> > Hi Alexander,
> >
> > On Wed, Mar 06, 2024 at 11:16:19AM +0100, Alexander Stein wrote:
> > > From: Sandor Yu <Sandor.yu@nxp.com>
> > >
> > > Allow HDMI PHYs to be configured through the generic
> > > functions through a custom structure added to the generic union.
> > >
> > > The parameters added here are based on HDMI PHY
> > > implementation practices. The current set of parameters
> > > should cover the potential users.
> > >
> > > Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > Acked-by: Vinod Koul <vkoul@kernel.org>
> > > ---
> > > include/linux/phy/phy-hdmi.h | 24 ++++++++++++++++++++++++
> > > include/linux/phy/phy.h | 7 ++++++-
> > > 2 files changed, 30 insertions(+), 1 deletion(-)
> > > create mode 100644 include/linux/phy/phy-hdmi.h
> > >
> > > diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h
> > > new file mode 100644
> > > index 0000000000000..b7de88e9090f0
> > > --- /dev/null
> > > +++ b/include/linux/phy/phy-hdmi.h
> > > @@ -0,0 +1,24 @@
> > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > +/*
> > > + * Copyright 2022 NXP
> > > + */
> > > +
> > > +#ifndef __PHY_HDMI_H_
> > > +#define __PHY_HDMI_H_
> > > +
> > > +#include <linux/hdmi.h>
> > > +/**
> > > + * struct phy_configure_opts_hdmi - HDMI configuration set
> > > + * @pixel_clk_rate: Pixel clock of video modes in KHz.
> > > + * @bpc: Maximum bits per color channel.
> > > + * @color_space: Colorspace in enum hdmi_colorspace.
> > > + *
> > > + * This structure is used to represent the configuration state of a HDMI phy.
> > > + */
> > > +struct phy_configure_opts_hdmi {
> > > + unsigned int pixel_clk_rate;
> > > + unsigned int bpc;
> > > + enum hdmi_colorspace color_space;
> > > +};
> >
> > Does the PHY actually care about the pixel clock rate, color space and
> > formats, or does it only care about the character rate?
>
> Nope it should not
After taking a look at the Cadence PHY driver, I share the feeling that
hdptx_hdmi_feedback_factor() should be reworked into drm_display helper
and then the struct phy_configure_opts_hdmi can be limited to having a
single unsigned long char_freq or bit_rate field.
I'm not sure whether we need anything corresponding to the TMDS Bit
Clock Ratio control. As far as I understand, it can be deduced from the
Bit Rate.
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 2/2] Input: edt-ft5x06 - add ft5426
From: Andy Shevchenko @ 2024-04-05 15:13 UTC (permalink / raw)
To: Andreas Kemnade
Cc: dmitry.torokhov, robh+dt, krzysztof.kozlowski+dt, conor+dt,
o.rempel, u.kleine-koenig, hdegoede, ye.xingchen, p.puschmann,
linux-input, devicetree, linux-kernel, caleb.connolly
In-Reply-To: <20240404222009.670685-3-andreas@kemnade.info>
On Fri, Apr 5, 2024 at 1:20 AM Andreas Kemnade <andreas@kemnade.info> wrote:
>
> As ft5426 seems to be compatible with this driver, add it.
> Debug output during identification: Model "generic ft5x06 (79)", Rev. "
...
> @@ -1484,6 +1484,7 @@ static const struct of_device_id edt_ft5x06_of_match[] = {
> { .compatible = "edt,edt-ft5206", .data = &edt_ft5x06_data },
> { .compatible = "edt,edt-ft5306", .data = &edt_ft5x06_data },
> { .compatible = "edt,edt-ft5406", .data = &edt_ft5x06_data },
> + { .compatible = "focaltech,ft5426", .data = &edt_ft5506_data },
Why a different vendor prefix?
In case you need to use this one, keep the list sorted, currently this
splits the edt,* ones.
> { .compatible = "edt,edt-ft5506", .data = &edt_ft5506_data },
> { .compatible = "evervision,ev-ft5726", .data = &edt_ft5506_data },
> /* Note focaltech vendor prefix for compatibility with ft6236.c */
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v2 02/18] PCI: endpoint: Introduce pci_epc_map_align()
From: Niklas Cassel @ 2024-04-05 15:18 UTC (permalink / raw)
To: Damien Le Moal
Cc: Kishon Vijay Abraham I, Manivannan Sadhasivam, Lorenzo Pieralisi,
Kishon Vijay Abraham I, Shawn Lin, Krzysztof Wilczyński,
Bjorn Helgaas, Heiko Stuebner, linux-pci, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-rockchip,
linux-arm-kernel, Rick Wertenbroek, Wilfred Mallawa
In-Reply-To: <9b3cfd8a-640d-4645-83a9-ddaa34cd09cd@kernel.org>
On Fri, Apr 05, 2024 at 09:43:42PM +0900, Damien Le Moal wrote:
> On 4/5/24 21:20, Niklas Cassel wrote:
> >
> > Now I understand that rockchip is the first one that does not have a fixed
> > alignment.
> > So for that platform, map_align() will be different from ep->page_size.
> > (For all DWC based drivers the outbound iATU alignment requirement is
> > the same as the page size.)
>
> Yes. So we can have a generic map_align() implementation that all these drivers
> can use as there .map_align method. No need to expose page size to the epc/epf
> core code.
I don't follow.
ep->page_size is used by pci_epc_multi_mem_init(), pci_epc_mem_alloc_addr()
and pci_epc_mem_free_addr(), so it is used by EPC core.
pci_epc_mem_alloc_addr() currently uses it to align up an allocation to the
page size, so that an allocation from the PCI window/memory space is a multiple
of page_size. How can we avoid exposing the page size to EPC core?
For a DWC-based driver, the mapping part requires that the start address of
the mapping should be aligned to the page size.
But e.g.
drivers/pci/controller/pcie-rockchip-ep.c, sets page size (smallest allocation):
to 1 MB:
windows[i].page_size = SZ_1M;
But the mapping part for rockchip-ep appears to have different requirements.
>
> > However, it would be nice if:
> > 1) We could have a default implementation of map_align() that by default uses
> > ep->page_size. Platforms that have non-fixed alignment requirements could
> > define their own map_align().
>
> See above. The default implementation can be a helper function defined in epc
> core that the drivers can use for their .map_align() method.
Sounds good.
> > 2) We fix dw_pcie_ep_raise_msi_irq() and dw_pcie_ep_raise_msix_irq() to use
> > the new pci_epc_map_align().
>
> Why ? That is completely internal to the controller driver.
Well, dw_pcie_ep_raise_msi_irq() and dw_pcie_ep_raise_msix_irq() currently does
some clearing of lower bits of the address before using .map_addr() to map the
an aligned outbound address. It will then write to the mapped address + some
offset.
Since it is already using .map_addr(), it seems like the perfect use case for
pci_epc_map_align(), as the function then would not need to do any clearing
of lower bits before mapping, nor writing to an offset within the mapping.
It would just use pci_epc_map_align() and then write to map->pci_addr.
> > 3) It is getting too complicated with all these...
> > epc_features->align, ep->page_size, map_align(), and .alignment in host driver.
> > I think that we need to document each of these in Documentation/PCI/endpoint/
>
> test host driver .alignment needs to be nuked. That one is nonsense.
> ep->page_size needs to stay internal to the driver. .map_align method is enough
> to handle any PCI address mapping constraint and will indicate memory size to
> allocate, offset into it etc. And for the BARs alignment, .align feature is not
> exactly great as it is not clear, but it is enough I think. So we could just
> rename it to be clear. And even maybe remove it from features. I do not see why
> an EPF needs to care about it given that epc core funstions are used to setup
> the bars.
+1 on renaming it to bar_alignment or inbound_alignment or similar.
I don't think that we can remove it from epc_features. It is used by
pci_epf_alloc_space() which uses epc_features->align to ensure that
when an EPF driver allocates the backing memory for a BAR, the backing
memory is aligned to bar_alignment. (An allocation of size X is guaranteed
to be aligned to X.)
> > 4) It would be nice if we could set page_size correctly for all the PCI device
> > and vendor IDs that have defined an .alignment in drivers/misc/pci_endpoint_test.c
> > in the correct EPC driver. That way, we should be able to completely remove all
> > .alignment specified in drivers/misc/pci_endpoint_test.c.
>
> The host side should be allowed to use any PCI address alignment it wants. So no
> alignment communicated at all. It is the EP side that needs to deal with alignment.
I think we are saying the same thing.
But in order to remove all .alignment uses in drivers/misc/pci_endpoint_test.c,
we will need to add modify the corresponding EPC driver to either:
- Define the ep->page_size, so that the generic map_align() implementation will
work.
(If you grep for page_size in drivers/pci/controller, you will see that
very few EPC drivers currently set ep->page_size, even though the PCI device
and vendor IDs for those same controllers have specified an alignment in
drivers/misc/pci_endpoint_test.c)
- Define a custom map_align() implementation.
> > 5) Unfortunately drivers/misc/pci_endpoint_test.c defines a default alignment
> > of 4K:
> > https://github.com/torvalds/linux/blob/v6.9-rc2/drivers/misc/pci_endpoint_test.c#L968
> > https://github.com/torvalds/linux/blob/v6.9-rc2/drivers/misc/pci_endpoint_test.c#L820
> >
> > It would be nice if we could get rid of this as well. Or perhaps add an option
> > to pci_test so that it does not use this 4k alignment, such that we can verify
> > that pci_epc_map_align() is actually working.
>
> Exactly. Get rid of any default alignment, add a test parameter to define one so
> that we can test different alignment+size combinations.
>
> > In my opinion 4) is the biggest win with this series, because it means that
> > we define the alignment in the EPC driver, instead of needing to define it in
> > each and every host side driver. But right now, this great improvement is not
> > really visible for someone looking quickly at the current series.
>
> Yes. Once in place, we can rework the test driver alignment stuff to make it
> optional instead of mandatory because of bad handling on the EP side :)
Perhaps it would be nice to have 5) implemented for this initial series,
so that it is possible to test that this new API is behaving as intended?
Kind regards,
Niklas
^ permalink raw reply
* Re: [PATCH v17 11/35] virt: gunyah: Translate gh_rm_hyp_resource into gunyah_resource
From: Elliot Berman @ 2024-04-05 15:18 UTC (permalink / raw)
To: Pavan Kondeti
Cc: Alex Elder, Srinivas Kandagatla, Murali Nalajal, Trilok Soni,
Srivatsa Vaddagiri, Carl van Schaik, Philip Derrin,
Prakruthi Deepak Heragu, Jonathan Corbet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Catalin Marinas, Will Deacon,
Konrad Dybcio, Bjorn Andersson, Dmitry Baryshkov, Fuad Tabba,
Sean Christopherson, Andrew Morton, linux-arm-msm, linux-doc,
linux-kernel, devicetree, linux-arm-kernel, linux-mm
In-Reply-To: <ff6a3fb2-5f1a-4baa-b42a-a7767e92885a@quicinc.com>
On Fri, Apr 05, 2024 at 08:40:40AM +0530, Pavan Kondeti wrote:
> On Thu, Feb 22, 2024 at 03:16:34PM -0800, Elliot Berman wrote:
> > When booting a Gunyah virtual machine, the host VM may gain capabilities
> > to interact with resources for the guest virtual machine. Examples of
> > such resources are vCPUs or message queues. To use those resources, we
> > need to translate the RM response into a gunyah_resource structure which
> > are useful to Linux drivers. Presently, Linux drivers need only to know
> > the type of resource, the capability ID, and an interrupt.
> >
> > On ARM64 systems, the interrupt reported by Gunyah is the GIC interrupt
> > ID number and always a SPI or extended SPI.
> >
> > Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
> > ---
> > arch/arm64/include/asm/gunyah.h | 36 ++++++++++++++++++++++
> > drivers/virt/gunyah/rsc_mgr.c | 67 +++++++++++++++++++++++++++++++++++++++++
> > drivers/virt/gunyah/rsc_mgr.h | 5 +++
> > include/linux/gunyah.h | 2 ++
> > 4 files changed, 110 insertions(+)
> >
> > diff --git a/arch/arm64/include/asm/gunyah.h b/arch/arm64/include/asm/gunyah.h
> > new file mode 100644
> > index 0000000000000..0cd3debe22b64
> > --- /dev/null
> > +++ b/arch/arm64/include/asm/gunyah.h
> > @@ -0,0 +1,36 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> > + */
> > +#ifndef _ASM_GUNYAH_H
> > +#define _ASM_GUNYAH_H
> > +
> > +#include <linux/irq.h>
> > +#include <linux/irqdomain.h>
> > +
> > +static inline int arch_gunyah_fill_irq_fwspec_params(u32 virq,
> > + struct irq_fwspec *fwspec)
> > +{
> > + /* Assume that Gunyah gave us an SPI or ESPI; defensively check it */
> > + if (WARN(virq < 32, "Unexpected virq: %d\n", virq)) {
> > + return -EINVAL;
> > + } else if (virq <= 1019) {
> > + fwspec->param_count = 3;
> > + fwspec->param[0] = 0; /* GIC_SPI */
> > + fwspec->param[1] = virq - 32; /* virq 32 -> SPI 0 */
> > + fwspec->param[2] = IRQ_TYPE_EDGE_RISING;
> > + } else if (WARN(virq < 4096, "Unexpected virq: %d\n", virq)) {
> > + return -EINVAL;
> > + } else if (virq < 5120) {
> > + fwspec->param_count = 3;
> > + fwspec->param[0] = 2; /* GIC_ESPI */
> > + fwspec->param[1] = virq - 4096; /* virq 4096 -> ESPI 0 */
> > + fwspec->param[2] = IRQ_TYPE_EDGE_RISING;
> > + } else {
> > + WARN(1, "Unexpected virq: %d\n", virq);
> > + return -EINVAL;
> > + }
> > + return 0;
> > +}
> > +
>
> __get_intid_range() in gic-v3 driver looks more pleasing. Other than
> that the logic for the translation looks good to me.
Agreed, updated for v18.
static inline int arch_gunyah_fill_irq_fwspec_params(u32 virq,
struct irq_fwspec *fwspec)
{
/* Assume that Gunyah gave us an SPI or ESPI; defensively check it */
switch (virq) {
case 32 ... 1019:
fwspec->param_count = 3;
fwspec->param[0] = 0; /* GIC_SPI */
fwspec->param[1] = virq - 32; /* virq 32 -> SPI 0 */
fwspec->param[2] = IRQ_TYPE_EDGE_RISING;
break;
case 4096 ... 5119:
fwspec->param_count = 3;
fwspec->param[0] = 2; /* GIC_ESPI */
fwspec->param[1] = virq - 4096; /* virq 4096 -> ESPI 0 */
fwspec->param[2] = IRQ_TYPE_EDGE_RISING;
break;
default:
WARN(1, "Unexpected virq: %d\n", virq)
return -EINVAL;
}
return 0;
}
^ permalink raw reply
* Re: [PATCH 0/5] Add parsing for Zimop ISA extension
From: Andrew Jones @ 2024-04-05 15:26 UTC (permalink / raw)
To: Clément Léger
Cc: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Anup Patel,
Shuah Khan, Atish Patra, linux-doc, linux-riscv, linux-kernel,
devicetree, kvm, kvm-riscv, linux-kselftest
In-Reply-To: <20240404103254.1752834-1-cleger@rivosinc.com>
On Thu, Apr 04, 2024 at 12:32:46PM +0200, Clément Léger wrote:
> The Zimop ISA extension was ratified recently. This series adds support
> for parsing it from riscv,isa, hwprobe export and kvm support for
> Guest/VM.
I'm not sure we need this. Zimop by itself isn't useful, so I don't know
if we need to advertise it at all. When an extension comes along that
redefines some MOPs, then we'll advertise that extension, but the fact
Zimop is used for that extension is really just an implementation detail.
Thanks,
drew
>
> Clément Léger (5):
> dt-bindings: riscv: add Zimop ISA extension description
> riscv: add ISA extension parsing for Zimop
> riscv: hwprobe: export Zimop ISA extension
> RISC-V: KVM: Allow Zimop extension for Guest/VM
> KVM: riscv: selftests: Add Zimop extension to get-reg-list test
>
> Documentation/arch/riscv/hwprobe.rst | 4 ++++
> Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kernel/cpufeature.c | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++
> 9 files changed, 20 insertions(+)
>
> --
> 2.43.0
>
>
> --
> kvm-riscv mailing list
> kvm-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kvm-riscv
^ permalink raw reply
* [PATCH 0/6] Remove stmmac tx-sched-sp property from documentation and DT
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
This patch serie remove this property both from the "snps,dwmac.yaml"
documentation and from some device-tree boards files where was still used.
Flavio Suligoi (6):
dt-bindings: net: snps,dwmac: remove tx-sched-sp property
arm64: dts: imx8mp-beacon: remove tx-sched-sp property
arm64: dts: imx8mp-evk: remove tx-sched-sp property
arm64: dts: imx8mp-verdin: remove tx-sched-sp property
arm64: dts: qcom: sa8540p-ride: remove tx-sched-sp property
dts: qcom: sa8775p-ride: remove tx-sched-sp property
.../devicetree/bindings/net/snps,dwmac.yaml | 14 --------------
.../boot/dts/freescale/imx8mp-beacon-som.dtsi | 1 -
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 1 -
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 1 -
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 2 --
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 2 --
6 files changed, 21 deletions(-)
--
2.34.1
^ permalink raw reply
* [PATCH 2/6] arm64: dts: imx8mp-beacon: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi
index 8be251b69378..34339dc4a635 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi
@@ -106,7 +106,6 @@ queue4 {
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
--
2.34.1
^ permalink raw reply related
* [PATCH 1/6] dt-bindings: net: snps,dwmac: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
.../devicetree/bindings/net/snps,dwmac.yaml | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index 15073627c53a..21cc27e75f50 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -328,9 +328,6 @@ properties:
snps,tx-sched-dwrr:
type: boolean
description: Deficit Weighted Round Robin
- snps,tx-sched-sp:
- type: boolean
- description: Strict priority
allOf:
- if:
required:
@@ -339,7 +336,6 @@ properties:
properties:
snps,tx-sched-wfq: false
snps,tx-sched-dwrr: false
- snps,tx-sched-sp: false
- if:
required:
- snps,tx-sched-wfq
@@ -347,7 +343,6 @@ properties:
properties:
snps,tx-sched-wrr: false
snps,tx-sched-dwrr: false
- snps,tx-sched-sp: false
- if:
required:
- snps,tx-sched-dwrr
@@ -355,15 +350,6 @@ properties:
properties:
snps,tx-sched-wrr: false
snps,tx-sched-wfq: false
- snps,tx-sched-sp: false
- - if:
- required:
- - snps,tx-sched-sp
- then:
- properties:
- snps,tx-sched-wrr: false
- snps,tx-sched-wfq: false
- snps,tx-sched-dwrr: false
patternProperties:
"^queue[0-9]$":
description: Each subnode represents a queue.
--
2.34.1
^ permalink raw reply related
* [PATCH 3/6] arm64: dts: imx8mp-evk: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 8be5b2a57f27..bb1003363e3e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -251,7 +251,6 @@ ethphy0: ethernet-phy@1 {
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
--
2.34.1
^ permalink raw reply related
* [PATCH 6/6] dts: qcom: sa8775p-ride: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:28 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index 26ad05bd3b3f..2e1770e07f45 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -334,7 +334,6 @@ queue3 {
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
@@ -404,7 +403,6 @@ queue3 {
mtl_tx_setup1: tx-queues-config {
snps,tx-queues-to-use = <4>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
--
2.34.1
^ permalink raw reply related
* [PATCH 4/6] arm64: dts: imx8mp-verdin: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
index f033d4310305..5b1b36a7ad38 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
@@ -260,7 +260,6 @@ queue4 {
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
--
2.34.1
^ permalink raw reply related
* [PATCH 5/6] arm64: dts: qcom: sa8540p-ride: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 177b9dad6ff7..11663cf81e45 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -225,7 +225,6 @@ queue3 {
ethernet0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
@@ -302,7 +301,6 @@ queue3 {
ethernet1_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 00/11] spi: cadence-qspi: add Mobileye EyeQ5 support
From: Théo Lebrun @ 2024-04-05 15:30 UTC (permalink / raw)
To: Théo Lebrun, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vaishnav Achath, Thomas Bogendoerfer, Rob Herring
Cc: linux-spi, devicetree, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Thomas Petazzoni,
Tawfik Bayouk, Krzysztof Kozlowski
In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com>
On Fri Apr 5, 2024 at 5:02 PM CEST, Théo Lebrun wrote:
[...]
> Changes in v2:
> - Rebase upon v6.9-rc2.
> - Fix dt-bindings commit subject tags.
> - Take Reviewed-by: Krzysztof Kozlowski on dt-bindings commit.
> - Add dt-bindings commit to order compatibles alphabetically.
> adding EyeQ5 compatible can be taken alone easily.
> - Drop patch taken upstream:
> - Add To: Rob Herring, following get_maintainer.pl recommendation.
> - Link to v1: https://lore.kernel.org/r/20240308-cdns-qspi-mbly-v1-0-a503856dd205@bootlin.com
>
> Krzysztof: unsure if you want this. It is second so that commit
> spi: cadence-qspi: switch from legacy names to modern ones
Sorry for the weird formatting; b4 saw those two lines as trailers and
moved them last I guess. Proper formatting is:
Changes in v2:
- Rebase upon v6.9-rc2.
- Fix dt-bindings commit subject tags.
- Take Reviewed-by: Krzysztof Kozlowski on dt-bindings commit.
- Add dt-bindings commit to order compatibles alphabetically.
Krzysztof: unsure if you want this. It is second so that commit
adding EyeQ5 compatible can be taken alone easily.
- Drop patch taken upstream:
spi: cadence-qspi: switch from legacy names to modern ones
- Add To: Rob Herring, following get_maintainer.pl recommendation.
- Link to v1: https://lore.kernel.org/r/20240308-cdns-qspi-mbly-v1-0-a503856dd205@bootlin.com
Thanks,
--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH v6 05/16] dt-bindings: net: wireless: describe the ath12k PCI module
From: Jeff Johnson @ 2024-04-05 15:44 UTC (permalink / raw)
To: Bartosz Golaszewski, Kalle Valo
Cc: Marcel Holtmann, Luiz Augusto von Dentz, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Liam Girdwood, Mark Brown, Catalin Marinas, Will Deacon,
Bjorn Helgaas, Saravana Kannan, Geert Uytterhoeven, Arnd Bergmann,
Neil Armstrong, Marek Szyprowski, Alex Elder, Srini Kandagatla,
Greg Kroah-Hartman, Abel Vesa, Manivannan Sadhasivam,
Lukas Wunner, Dmitry Baryshkov, linux-bluetooth, netdev,
devicetree, linux-kernel, linux-wireless, linux-arm-msm,
linux-arm-kernel, linux-pci, linux-pm, Bartosz Golaszewski
In-Reply-To: <CAMRc=MdzhGxLNcNLWvRfqr0S9pey-iw964=AcYx_yDXgyDDjMA@mail.gmail.com>
On 4/5/2024 2:52 AM, Bartosz Golaszewski wrote:
> In addition to what Krzysztof already said about you seamingly
> confusing the maintenance of the driver vs maintenance of the
> device-tree bindings (IOW: structured hardware description) and in
> response to your question: I don't see any functional change to any
> dt-bindings neither from you nor from Jeff. Are you convinced you can
> maintain and properly review any changes?
Speaking just for myself, I know Bartosz is far more capable in this regard
than I am, so I'd expect him to be listed as a maintainer before me.
/jeff
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: usb: Document the Microchip USB2514 hub
From: Krzysztof Kozlowski @ 2024-04-05 15:45 UTC (permalink / raw)
To: Fabio Estevam, gregkh
Cc: robh, krzk+dt, conor+dt, linux-usb, devicetree, Fabio Estevam
In-Reply-To: <20240405120147.880933-1-festevam@gmail.com>
On 05/04/2024 14:01, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
>
> Document the Microchip USB2412, USB2417, and USB2514 USB hubs.
>
> The existing usb251xb.yaml describes Microchip USB251x hubs that are
> connected under I2C bus. Here, the hub is under the USB bus and use
> the on-board-hub interface instead.
>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply
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