* [PATCH] arm64: dts: meson: fix S4 power-controller node
From: Xianwei Zhao via B4 Relay @ 2024-04-08 3:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: devicetree, linux-arm-kernel, linux-amlogic, linux-kernel,
Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
The power-controller module works well by adding its parent
node secure-monitor.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index ce90b35686a2..24d00dce4969 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -65,10 +65,13 @@ xtal: xtal-clk {
#clock-cells = <0>;
};
- pwrc: power-controller {
- compatible = "amlogic,meson-s4-pwrc";
- #power-domain-cells = <1>;
- status = "okay";
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gxbb-sm";
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson-s4-pwrc";
+ #power-domain-cells = <1>;
+ };
};
soc {
---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240408-fix-secpwr-s4-a99ff960d0ae
Best regards,
--
Xianwei Zhao <xianwei.zhao@amlogic.com>
^ permalink raw reply related
* Re: [PATCH v1 2/3] dt-bindings: arm: mediatek: mmsys: Add OF graph support for board path
From: Chen-Yu Tsai @ 2024-04-08 3:20 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, robh, krzysztof.kozlowski+dt, conor+dt, p.zabel,
airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
matthias.bgg, shawn.sung, yu-chang.lee, ck.hu, jitao.shi,
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, kernel
In-Reply-To: <20240404081635.91412-3-angelogioacchino.delregno@collabora.com>
On Thu, Apr 4, 2024 at 4:16 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Document OF graph on MMSYS/VDOSYS: this supports up to three DDP paths
> per HW instance (so potentially up to six displays for multi-vdo SoCs).
>
> The MMSYS or VDOSYS is always the first component in the DDP pipeline,
> so it only supports an output port with multiple endpoints - where each
> endpoint defines the starting point for one of the (currently three)
> possible hardware paths.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../bindings/arm/mediatek/mediatek,mmsys.yaml | 23 +++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index b3c6888c1457..90758bb5bcb1 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -93,6 +93,29 @@ properties:
> '#reset-cells':
> const: 1
>
> + port:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Output port node. This port connects the MMSYS/VDOSYS output to
> + the first component of one display pipeline, for example one of
> + the available OVL or RDMA blocks.
> + Some MediaTek SoCs support up to three display outputs per MMSYS.
> + properties:
> + endpoint@0:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: Output to the primary display pipeline
> +
> + endpoint@1:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: Output to the secondary display pipeline
> +
> + endpoint@2:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: Output to the tertiary display pipeline
> +
> + required:
> + - endpoint@0
> +
Technically the mmsys device serves as an glue layer for the display
pipeline, providing things like clock control and signal routing; the
device itself is not part of the pipeline, and probably shouldn't be
part of the graph?
ChenYu
> required:
> - compatible
> - reg
> --
> 2.44.0
>
^ permalink raw reply
* Re: [EXT] Re: [PATCH 1/1] dt-bindings: media: imx-jpeg: add clocks,clock-names,slot to fix warning
From: Mirela Rabulea @ 2024-04-08 3:15 UTC (permalink / raw)
To: Krzysztof Kozlowski, Frank Li, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
open list:NXP i.MX 8QXP/8QM JPEG V4L2 DRIVER,
open list:NXP i.MX 8QXP/8QM JPEG V4L2 DRIVER,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
In-Reply-To: <af602862-5120-4717-adb6-694ada09e8d8@linaro.org>
Hi Krzysztof,
On 04.04.2024 09:26, Krzysztof Kozlowski wrote:
> Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button
>
>
> On 04/04/2024 05:52, Frank Li wrote:
>> Fix below DTB_CHECK warning.
>>
>> make CHECK_DTBS=y freescale/imx8qxp-mek.dtb
>> DTC_CHK arch/arm64/boot/dts/freescale/imx8qxp-mek.dtb
>> arch/arm64/boot/dts/freescale/imx8qxp-mek.dtb: jpegdec@58400000: 'assigned-clock-rates', 'assigned-clocks', 'clock-names', 'clocks', 'slot' do not match any of the regexes: 'pinctrl-[0-9]+'
>> from schema $id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
> No, that's not the reason to add properties. Add them if they are valid.
>
>
>
>> + slot:
>> + description: Certain slot number is used.
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + minimum: 0
>> + maximum: 3
> NAK. Every time.
>
> Fix your DTS instead.
>
> Please read the feedback instead of pushing this stuff for the third time!
>
> https://lore.kernel.org/all/bbb1875b-7980-46aa-80b4-dbaf2a2d5755@linaro.org/
>
> Can NXP take responsibility for this piece of code?
Thanks for feedback.
For the clocks issue, I looked at the patches sent previously by
Alexander Stein and Fabio Estevam, and the current one:
https://lore.kernel.org/linux-devicetree/?q=dfblob%3A3d9d1db3704+dfblob%3A7899e17aff3
As I also said in the past, I think Fabio's patch was more complete, so
I took his _v3, I tried to incorporate all the feedback given, and I
sent a subsequent _v4, here (bindings & dtb):
https://lore.kernel.org/linux-devicetree/20240408030734.1191069-1-mirela.rabulea@nxp.com/
For the slots issue, I will consult with Ming and get back.
Thanks for your patience, and sorry for the inconvenience.
Regards,
Mirela
>
> Best regards,
> Krzysztof
>
^ permalink raw reply
* Re: [PATCH 2/2] dt-bindings: spmi: hisilicon,hisi-spmi-controller: clean up example
From: Stephen Boyd @ 2024-04-08 3:08 UTC (permalink / raw)
To: Johan Hovold
Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-kernel, devicetree, Johan Hovold
In-Reply-To: <20231130173757.13011-3-johan+linaro@kernel.org>
Quoting Johan Hovold (2023-11-30 09:37:57)
> Clean up the binding example by dropping the unnecessary parent bus
> node, using a define for the second register value of the PMIC child and
> increasing indentation to four spaces.
>
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---
Applied to spmi-next
^ permalink raw reply
* [PATCH v4 2/2] arm64: dts: imx8-ss-img: Remove JPEG clock-names
From: Mirela Rabulea @ 2024-04-08 3:07 UTC (permalink / raw)
To: shawnguo, robh+dt, krzysztof.kozlowski+dt, festevam, festevam,
alexander.stein, Frank.li, ming.qian
Cc: conor+dt, devicetree, linux-arm-kernel, s.hauer, kernel, mchehab,
hverkuil, linux-media, imx, linux-kernel
In-Reply-To: <20240408030734.1191069-1-mirela.rabulea@nxp.com>
From: Fabio Estevam <festevam@gmail.com>
Per nxp,imx8-jpeg.yaml, the clock-names entry is not valid.
Remove them.
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
Changes since v3:
- Just added "imx8-ss-img:" in the subject
Changes since v2:
- Newly introduced.
arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
index e7783cc2d830..77d2928997b4 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
@@ -21,7 +21,6 @@ jpegdec: jpegdec@58400000 {
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
- clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;
@@ -35,7 +34,6 @@ jpegenc: jpegenc@58450000 {
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
- clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;
--
2.25.1
^ permalink raw reply related
* [PATCH v4 1/2] dt-bindings: media: imx8-jpeg: Add clocks entries
From: Mirela Rabulea @ 2024-04-08 3:07 UTC (permalink / raw)
To: shawnguo, robh+dt, krzysztof.kozlowski+dt, festevam, festevam,
alexander.stein, Frank.li, ming.qian
Cc: conor+dt, devicetree, linux-arm-kernel, s.hauer, kernel, mchehab,
hverkuil, linux-media, imx, linux-kernel
From: Fabio Estevam <festevam@gmail.com>
The JPEG decoder/encoder present in iMX8QXP and iMX8QM SoCs need
the PER and IPG clocks to be functional, so add the clock entries.
This also fixes the following schema warning:
imx8qm-apalis-eval.dtb: jpegdec@58400000: 'assigned-clock-rates', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
---
Changes since v3:
- Add items for clocks (per Krzysztof's feddback)
- Add description for clocks (per Conor's feddback to the other similar patch from Alexander)
- Add "media:" to the subject
- Add Mirela's signed-off
- For the similar patches that were sent for this issue, should Co-developed-by/Signed-off-by be added? Alexander Stein? Frank Li?
Changes since v2:
- Remove clock-names. (Mirela)
.../devicetree/bindings/media/nxp,imx8-jpeg.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
index 3d9d1db37040..cc040feb77d7 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
@@ -31,6 +31,14 @@ properties:
reg:
maxItems: 1
+ clocks:
+ description:
+ The JPEG decoder/encoder requires two clocks for it's wrapper (AXI and APB),
+ and one clock for it's core engine (AXI, same source as for the wrapper)
+ items:
+ - description: AXI DMA engine clock for fetching JPEG bitstream from memory (per)
+ - description: IP bus clock for register access (ipg)
+
interrupts:
description: |
There are 4 slots available in the IP, which the driver may use
@@ -49,6 +57,7 @@ properties:
required:
- compatible
- reg
+ - clocks
- interrupts
- power-domains
@@ -56,12 +65,15 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/firmware/imx/rsrc.h>
jpegdec: jpegdec@58400000 {
compatible = "nxp,imx8qxp-jpgdec";
reg = <0x58400000 0x00050000 >;
+ clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
+ <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
@@ -76,6 +88,8 @@ examples:
jpegenc: jpegenc@58450000 {
compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
reg = <0x58450000 0x00050000 >;
+ clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
+ <&img_jpeg__lpcg IMX_LPCG_CLK_4>;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
--
2.25.1
^ permalink raw reply related
* Re: [PATCH 1/2] dt-bindings: spmi: hisilicon,hisi-spmi-controller: fix binding references
From: Stephen Boyd @ 2024-04-08 3:07 UTC (permalink / raw)
To: Johan Hovold
Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-kernel, devicetree, Johan Hovold
In-Reply-To: <20231130173757.13011-2-johan+linaro@kernel.org>
Quoting Johan Hovold (2023-11-30 09:37:56)
> Fix up the free text binding references which were not updated when
> moving the bindings out of staging and which had a leading current
> directory component, respectively.
>
> Fixes: 9bd9e0de1cf5 ("mfd: hi6421-spmi-pmic: move driver from staging")
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---
Applied to spmi-next
^ permalink raw reply
* Re: [RFC PATCH v2 1/5] clk: meson: axg: move reset controller's code to separate module
From: Stephen Boyd @ 2024-04-08 2:39 UTC (permalink / raw)
To: Jan Dakinevich, Jerome Brunet, Philipp Zabel
Cc: Neil Armstrong, Jerome Brunet, Michael Turquette, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kevin Hilman,
Martin Blumenstingl, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <1j7chfiz8e.fsf@starbuckisacylon.baylibre.com>
Quoting Jerome Brunet (2024-04-02 07:52:38)
>
> On Thu 28 Mar 2024 at 04:08, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
>
> > This code will by reused by A1 SoC.
>
> Could expand a bit please ?
>
> >
> > Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>
> In general, I like the idea.
>
> We do have a couple a reset registers lost in middle of clocks and this
> change makes it possible to re-use the code instead duplicating it.
>
> The exported function would be used by audio clock controllers, but the
> module created would be purely about reset.
>
> One may wonder how it ended up in the clock tree, especially since the
> kernel as a reset tree too.
>
> I'm not sure if this should move to the reset framework or if it would
> be an unnecessary churn. Stephen, Philipp, do you have an opinion on
> this ?
>
I'd prefer it be made into an auxiliary device and the driver put in
drivers/reset/ so we can keep reset code in the reset directory. The
auxiliary device creation function can also be in the drivers/reset/
directory so that the clk driver calls some function to create and
register the device.
^ permalink raw reply
* [PATCH 4/4] arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs
From: Dmitry Baryshkov @ 2024-04-08 2:34 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240408-hdk-orientation-gpios-v1-0-8064ba43e52a@linaro.org>
Define the USB-C orientation GPIOs so that the USB-C ports orientation
is known without having to resort to the altmode notifications.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
index 6f2e1c732ed3..6af99116c715 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
@@ -51,6 +51,8 @@ pmic-glink {
#address-cells = <1>;
#size-cells = <0>;
+ orientation-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>,
+ <&tlmm 58 GPIO_ACTIVE_HIGH>;
connector@0 {
compatible = "usb-c-connector";
--
2.39.2
^ permalink raw reply related
* [PATCH 3/4] arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs
From: Dmitry Baryshkov @ 2024-04-08 2:34 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240408-hdk-orientation-gpios-v1-0-8064ba43e52a@linaro.org>
Define the USB-C orientation GPIOs so that the USB-C ports orientation
is known without having to resort to the altmode notifications.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 15ae94c1602d..2806aa8ec497 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -100,6 +100,8 @@ pmic-glink {
#address-cells = <1>;
#size-cells = <0>;
+ orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>,
+ <&tlmm 49 GPIO_ACTIVE_HIGH>;
connector@0 {
compatible = "usb-c-connector";
--
2.39.2
^ permalink raw reply related
* [PATCH 2/4] arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO
From: Dmitry Baryshkov @ 2024-04-08 2:34 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240408-hdk-orientation-gpios-v1-0-8064ba43e52a@linaro.org>
Define the USB-C orientation GPIO so that the USB-C port orientation is
known without having to resort to the altmode notifications.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index 0786cff07b89..3be46b56c723 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -95,6 +95,7 @@ pmic-glink {
compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
+ orientation-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>;
connector@0 {
compatible = "usb-c-connector";
--
2.39.2
^ permalink raw reply related
* [PATCH 1/4] arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO
From: Dmitry Baryshkov @ 2024-04-08 2:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240408-hdk-orientation-gpios-v1-0-8064ba43e52a@linaro.org>
Define the USB-C orientation GPIO so that the USB-C port orientation is
known without having to resort to the altmode notifications.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index b43d264ed42b..4c25ab2f5670 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -42,6 +42,7 @@ pmic-glink {
compatible = "qcom,sm8350-pmic-glink", "qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
+ orientation-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
connector@0 {
compatible = "usb-c-connector";
--
2.39.2
^ permalink raw reply related
* [PATCH 0/4] arm64: dts: qcom: add USB-C orientation GPIOs
From: Dmitry Baryshkov @ 2024-04-08 2:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
Populate orientation GPIOs for some of the PMIC-GLINK-based devices.
This leaves only FairPhone5, RB3Gen2, SC8180X Primus and SC8280XP CRD
without the orientation GPIOs declared.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Dmitry Baryshkov (4):
arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs
arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 ++
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 ++
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 +
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 +
4 files changed, 6 insertions(+)
---
base-commit: 8568bb2ccc278f344e6ac44af6ed010a90aa88dc
change-id: 20240408-hdk-orientation-gpios-141bc7fd247d
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
^ permalink raw reply
* Re: [PATCH 0/3] arm64: dts: qcom: Fix the msi-map entries
From: Bjorn Andersson @ 2024-04-08 2:17 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Manivannan Sadhasivam
Cc: linux-arm-msm, devicetree, linux-kernel, stable
In-Reply-To: <20240318-pci-bdf-sid-fix-v1-0-acca6c5d9cf1@linaro.org>
On Mon, 18 Mar 2024 12:49:02 +0530, Manivannan Sadhasivam wrote:
> While adding the GIC ITS MSI support, it was found that the msi-map entries
> needed to be swapped to receive MSIs from the endpoint.
>
> But later it was identified that the swapping was needed due to a bug in
> the Qualcomm PCIe controller driver. And since the bug is now fixed with
> commit bf79e33cdd89 ("PCI: qcom: Enable BDF to SID translation properly"),
> let's fix the msi-map entries also to reflect the actual mapping in the
> hardware.
>
> [...]
Applied, thanks!
[1/3] arm64: dts: qcom: sm8450: Fix the msi-map entries
commit: d6c0602429490ff90d3f79a431aec1be779650b7
[2/3] arm64: dts: qcom: sm8550: Fix the msi-map entries
commit: 398b7c7dda6792c2646a2208a6cbab02da97d6e5
[3/3] arm64: dts: qcom: sm8650: Fix the msi-map entries
commit: 3ac680a514b6e63428481b1e6fb069383e5b7add
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply
* Re: (subset) [PATCH 0/2] phy: qcom-qmp-ufs: Fix PHY QMP clocks for SC7180
From: Bjorn Andersson @ 2024-04-08 2:17 UTC (permalink / raw)
To: konrad.dybcio, vkoul, kishon, robh, krzysztof.kozlowski+dt,
conor+dt, cros-qcom-dts-watchers, manivannan.sadhasivam,
davidwronek, Danila Tikhonov
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <20240401182240.55282-1-danila@jiaxyga.com>
On Mon, 01 Apr 2024 21:22:38 +0300, Danila Tikhonov wrote:
> This series of patches is based on the series from Manivannan:
> https://lore.kernel.org/all/20240131-ufs-phy-clock-v3-0-58a49d2f4605@linaro.org/
>
> Patch from David adding a UFS nodes for SC7180(SM7125):
> https://lore.kernel.org/all/20240121-sm7125-upstream-v4-6-f7d1212c8ebb@gmail.com/
>
> The patch submitted by David and a series of patches submitted by Manivannan
> were both applied at approximately the same time. As a result, David's patch
> did not include this change.
>
> [...]
Applied, thanks!
[2/2] arm64: dts: qcom: sc7180: Fix UFS PHY clocks
commit: 32198408f825a8ca3da4784d4c280847075990e9
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply
* Re: [PATCH AUTOSEL 6.1 04/52] arm64: dts: qcom: sdm630: add USB QMP PHY support
From: Sasha Levin @ 2024-04-08 2:07 UTC (permalink / raw)
To: Konrad Dybcio
Cc: linux-kernel, stable, Dmitry Baryshkov, Bjorn Andersson, robh,
krzysztof.kozlowski+dt, conor+dt, linux-arm-msm, devicetree
In-Reply-To: <42ef5a02-a50e-4a4a-9d07-2f5848857560@linaro.org>
On Fri, Mar 29, 2024 at 02:16:00PM +0100, Konrad Dybcio wrote:
>On 29.03.2024 1:44 PM, Sasha Levin wrote:
>> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>
>> [ Upstream commit bb5009a24ec3f2f2ec1e2ed7b8a5dcde9a9e28d9 ]
>>
>> Define USB3 QMP PHY presend on the SDM630 / SDM660 platforms. Enable it by
>> default in the USB3 host, but (for compatibility), force USB 2.0 mode
>> for all defined boards. The boards should opt-in to enable USB 3.0
>> support.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> Link: https://lore.kernel.org/r/20240116-sdm660-usb3-support-v1-3-2fbd683aea77@linaro.org
>> Signed-off-by: Bjorn Andersson <andersson@kernel.org>
>> Signed-off-by: Sasha Levin <sashal@kernel.org>
>> ---
>
>Hi, this depends on other kernel changes and can possibly regress something
>if EPROBE_DEFER isn't handled correctly (because it will never probe)
>
>Please drop it from all queues
Dropped, thanks!
--
Thanks,
Sasha
^ permalink raw reply
* Re: [RFC][PATCH 0/2] Amlogic T7 (A113D2) Clock Driver
From: Xianwei Zhao @ 2024-04-08 1:39 UTC (permalink / raw)
To: tanure
Cc: Yu Tu, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Michael Turquette, linux-arm-kernel,
linux-amlogic, devicetree, linux-kernel, linux-clk
In-Reply-To: <CAJX_Q+2wA+hNDhYtOsMi-DyuvH0KfkVgbsVFBFDj=Ph4fOEJaw@mail.gmail.com>
Hi Lucas,
Thanks for your reply.
On 2024/4/3 16:12, Lucas Tanure wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed, Apr 3, 2024 at 7:44 AM Xianwei Zhao <xianwei.zhao@amlogic.com> wrote:
>>
>> Hi Lucas,
>> As we are preparing the T7 clock patchset, we would like to your
>> purpose and plan of this RFC patches. Are you going to submit these
>> patches at last?
>
> Hi Xianwei,
>
> I made some progress, and now the SD card controller probes but fails
> to read blocks from the SD card. I do think my port of the clock
> driver is okay, but I will not send my clock driver until the SD card
> fully works, so I am sure the clocking driver is tested.
> But if you have something already done, please send it, and I will
> test and review it from my side.
>
> Any help with the sdcard controller is also much appreciated.
>
The SDCard part works well on our clock patchset. Then we will send the
formal clock submission later. What do you think?
> Thanks
> Lucas
>
>> On 2024/3/18 19:43, Lucas Tanure wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> I am trying to port the T7 clock driver from Khadas 5.4 kernel for Vim4
>>> to mainline, but I am encountering some issues in the path.
>>>
>>> The kernel panics at clk_mux_val_to_index, but I believe that all the
>>> needed clocks are registered.
>>>
>>> If anyone from Amlogic or the community could help me understand what
>>> my driver is missing, that would be great.
>>> I will continue to try to figure out, but it has been some weeks
>>> without progress =/.
>>>
>>> Lucas Tanure (2):
>>> clk: meson: T7: add support for Amlogic T7 SoC PLL clock driver
>>> arm64: dts: amlogic: t7: SDCard, Ethernet and Clocking
>>>
>>> .../amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 66 +
>>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 189 +
>>> drivers/clk/meson/Kconfig | 25 +
>>> drivers/clk/meson/Makefile | 2 +
>>> drivers/clk/meson/t7-peripherals.c | 6368 +++++++++++++++++
>>> drivers/clk/meson/t7-peripherals.h | 131 +
>>> drivers/clk/meson/t7-pll.c | 1543 ++++
>>> drivers/clk/meson/t7-pll.h | 83 +
>>> .../clock/amlogic,t7-peripherals-clkc.h | 410 ++
>>> .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 69 +
>>> 10 files changed, 8886 insertions(+)
>>> create mode 100644 drivers/clk/meson/t7-peripherals.c
>>> create mode 100644 drivers/clk/meson/t7-peripherals.h
>>> create mode 100644 drivers/clk/meson/t7-pll.c
>>> create mode 100644 drivers/clk/meson/t7-pll.h
>>> create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
>>> create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
>>>
>>> Starting kernel ...
>>>
>>> uboot time: 14277917 us
>>> boot 64bit kernel
>>> [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd092]
>>> [ 0.000000] Linux version 6.8.0-09793-gda876e5b54b3-dirty (tanureal@ryzen) (aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621, GNU ld (GNU Toolchain for the A-pr4
>>> [ 0.000000] KASLR disabled due to lack of seed
>>> [ 0.000000] Machine model: Khadas vim4
>>> [ 0.000000] efi: UEFI not found.
>>> [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
>>> [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
>>> [ 0.000000] NUMA: No NUMA configuration found
>>> [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000df7fffff]
>>> [ 0.000000] NUMA: NODE_DATA [mem 0xdf10c9c0-0xdf10efff]
>>> [ 0.000000] Zone ranges:
>>> [ 0.000000] DMA [mem 0x0000000000000000-0x00000000df7fffff]
>>> [ 0.000000] DMA32 empty
>>> [ 0.000000] Normal empty
>>> [ 0.000000] Movable zone start for each node
>>> [ 0.000000] Early memory node ranges
>>> [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
>>> [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
>>> [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000df7fffff]
>>> [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000df7fffff]
>>> [ 0.000000] On node 0, zone DMA: 2048 pages in unavailable ranges
>>> [ 0.000000] cma: Reserved 32 MiB at 0x00000000d9800000 on node -1
>>> [ 0.000000] psci: probing for conduit method from DT.
>>> [ 0.000000] psci: PSCIv1.0 detected in firmware.
>>> [ 0.000000] psci: Using standard PSCI v0.2 function IDs
>>> [ 0.000000] psci: Trusted OS migration not required
>>> [ 0.000000] psci: SMC Calling Convention v1.1
>>> [ 0.000000] percpu: Embedded 24 pages/cpu s58152 r8192 d31960 u98304
>>> [ 0.000000] Detected VIPT I-cache on CPU0
>>> [ 0.000000] CPU features: detected: Spectre-v2
>>> [ 0.000000] CPU features: detected: Spectre-v4
>>> [ 0.000000] CPU features: detected: Spectre-BHB
>>> [ 0.000000] CPU features: detected: ARM erratum 858921
>>> [ 0.000000] alternatives: applying boot alternatives
>>> [ 0.000000] Kernel command line: root=UUID=a91e7bfe-4263-4e53-867d-7824e7c6a992 rw rootfstype=ext4 console=ttyS0,921600 no_console_suspend earlycon=ttyS0,0xfe078000 khadas_board=VIM4 androidboot.selinux=permissive androidboot.0
>>> [ 0.000000] Unknown kernel command line parameters "khadas_board=VIM4", will be passed to user space.
>>> [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
>>> [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
>>> [ 0.000000] Fallback order for Node 0: 0
>>> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 901152
>>> [ 0.000000] Policy zone: DMA
>>> [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
>>> [ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
>>> [ 0.000000] software IO TLB: area num 8.
>>> [ 0.000000] software IO TLB: SWIOTLB bounce buffer size roundup to 4MB
>>> [ 0.000000] software IO TLB: mapped [mem 0x00000000d8e00000-0x00000000d9200000] (4MB)
>>> [ 0.000000] Memory: 3445944K/3661824K available (16896K kernel code, 4426K rwdata, 9184K rodata, 9728K init, 611K bss, 183112K reserved, 32768K cma-reserved)
>>> [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
>>> [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
>>> [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
>>> [ 0.000000] Trampoline variant of Tasks RCU enabled.
>>> [ 0.000000] Tracing variant of Tasks RCU enabled.
>>> [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
>>> [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
>>> [ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
>>> [ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
>>> [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
>>> [ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
>>> [ 0.000000] Root IRQ handler: gic_handle_irq
>>> [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
>>> [ 0.000000] arch_timer: Enabling local workaround for ARM erratum 858921
>>> [ 0.000000] arch_timer: CPU0: Trapping CNTVCT access
>>> [ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
>>> [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
>>> [ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
>>> [ 0.000210] Console: colour dummy device 80x25
>>> [ 0.000253] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
>>> [ 0.000261] pid_max: default: 32768 minimum: 301
>>> [ 0.000300] LSM: initializing lsm=capability
>>> [ 0.000358] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
>>> [ 0.000371] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
>>> [ 0.000920] cacheinfo: Unable to detect cache hierarchy for CPU 0
>>> [ 0.001389] rcu: Hierarchical SRCU implementation.
>>> [ 0.001391] rcu: Max phase no-delay instances is 1000.
>>> [ 0.001834] EFI services will not be available.
>>> [ 0.001999] smp: Bringing up secondary CPUs ...
>>> [ 0.002408] CPU features: detected: ARM erratum 845719
>>> [ 0.002426] Detected VIPT I-cache on CPU1
>>> [ 0.002516] CPU1: Booted secondary processor 0x0000000100 [0x410fd034]
>>> [ 0.003007] Detected VIPT I-cache on CPU2
>>> [ 0.003054] CPU2: Booted secondary processor 0x0000000101 [0x410fd034]
>>> [ 0.003497] Detected VIPT I-cache on CPU3
>>> [ 0.003546] CPU3: Booted secondary processor 0x0000000102 [0x410fd034]
>>> [ 0.003988] Detected VIPT I-cache on CPU4
>>> [ 0.004038] CPU4: Booted secondary processor 0x0000000103 [0x410fd034]
>>> [ 0.004472] Detected VIPT I-cache on CPU5
>>> [ 0.004509] arch_timer: Enabling local workaround for ARM erratum 858921
>>> [ 0.004519] arch_timer: CPU5: Trapping CNTVCT access
>>> [ 0.004527] CPU5: Booted secondary processor 0x0000000001 [0x410fd092]
>>> [ 0.004915] Detected VIPT I-cache on CPU6
>>> [ 0.004940] arch_timer: Enabling local workaround for ARM erratum 858921
>>> [ 0.004946] arch_timer: CPU6: Trapping CNTVCT access
>>> [ 0.004951] CPU6: Booted secondary processor 0x0000000002 [0x410fd092]
>>> [ 0.005333] Detected VIPT I-cache on CPU7
>>> [ 0.005358] arch_timer: Enabling local workaround for ARM erratum 858921
>>> [ 0.005364] arch_timer: CPU7: Trapping CNTVCT access
>>> [ 0.005369] CPU7: Booted secondary processor 0x0000000003 [0x410fd092]
>>> [ 0.005414] smp: Brought up 1 node, 8 CPUs
>>> [ 0.005419] SMP: Total of 8 processors activated.
>>> [ 0.005421] CPU: All CPU(s) started at EL2
>>> [ 0.005434] CPU features: detected: 32-bit EL0 Support
>>> [ 0.005437] CPU features: detected: 32-bit EL1 Support
>>> [ 0.005440] CPU features: detected: CRC32 instructions
>>> [ 0.005485] alternatives: applying system-wide alternatives
>>> [ 0.006730] devtmpfs: initialized
>>> [ 0.008534] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
>>> [ 0.008545] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
>>> [ 0.008989] pinctrl core: initialized pinctrl subsystem
>>> [ 0.009581] DMI not present or invalid.
>>> [ 0.011290] NET: Registered PF_NETLINK/PF_ROUTE protocol family
>>> [ 0.011944] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
>>> [ 0.012293] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
>>> [ 0.012711] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
>>> [ 0.012832] audit: initializing netlink subsys (disabled)
>>> [ 0.013075] audit: type=2000 audit(0.012:1): state=initialized audit_enabled=0 res=1
>>> [ 0.013508] thermal_sys: Registered thermal governor 'step_wise'
>>> [ 0.013512] thermal_sys: Registered thermal governor 'power_allocator'
>>> [ 0.013557] cpuidle: using governor menu
>>> [ 0.013675] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
>>> [ 0.013784] ASID allocator initialised with 65536 entries
>>> [ 0.014630] Serial: AMBA PL011 UART driver
>>> [ 0.017553] Modules: 22496 pages in range for non-PLT usage
>>> [ 0.017556] Modules: 514016 pages in range for PLT usage
>>> [ 0.017980] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
>>> [ 0.017984] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
>>> [ 0.017988] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
>>> [ 0.017990] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
>>> [ 0.017993] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
>>> [ 0.017995] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
>>> [ 0.017997] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
>>> [ 0.018000] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
>>> [ 0.018247] Demotion targets for Node 0: null
>>> [ 0.018884] ACPI: Interpreter disabled.
>>> [ 0.019584] iommu: Default domain type: Translated
>>> [ 0.019587] iommu: DMA domain TLB invalidation policy: strict mode
>>> [ 0.019979] SCSI subsystem initialized
>>> [ 0.020174] usbcore: registered new interface driver usbfs
>>> [ 0.020187] usbcore: registered new interface driver hub
>>> [ 0.020200] usbcore: registered new device driver usb
>>> [ 0.020434] pps_core: LinuxPPS API ver. 1 registered
>>> [ 0.020437] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
>>> [ 0.020443] PTP clock support registered
>>> [ 0.020487] EDAC MC: Ver: 3.0.0
>>> [ 0.020717] scmi_core: SCMI protocol bus registered
>>> [ 0.021039] FPGA manager framework
>>> [ 0.021076] Advanced Linux Sound Architecture Driver Initialized.
>>> [ 0.021612] vgaarb: loaded
>>> [ 0.021857] clocksource: Switched to clocksource arch_sys_counter
>>> [ 0.021967] VFS: Disk quotas dquot_6.6.0
>>> [ 0.021984] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
>>> [ 0.022062] pnp: PnP ACPI: disabled
>>> [ 0.026651] NET: Registered PF_INET protocol family
>>> [ 0.026781] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
>>> [ 0.028598] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
>>> [ 0.028615] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
>>> [ 0.028622] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
>>> [ 0.028750] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
>>> [ 0.029019] TCP: Hash tables configured (established 32768 bind 32768)
>>> [ 0.029096] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
>>> [ 0.029124] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
>>> [ 0.029225] NET: Registered PF_UNIX/PF_LOCAL protocol family
>>> [ 0.029506] RPC: Registered named UNIX socket transport module.
>>> [ 0.029510] RPC: Registered udp transport module.
>>> [ 0.029512] RPC: Registered tcp transport module.
>>> [ 0.029513] RPC: Registered tcp-with-tls transport module.
>>> [ 0.029515] RPC: Registered tcp NFSv4.1 backchannel transport module.
>>> [ 0.029524] PCI: CLS 0 bytes, default 64
>>> [ 0.029649] Unpacking initramfs...
>>> [ 0.033933] kvm [1]: IPA Size Limit: 40 bits
>>> [ 0.034713] kvm [1]: Hyp mode initialized successfully
>>> [ 0.035476] Initialise system trusted keyrings
>>> [ 0.035582] workingset: timestamp_bits=42 max_order=20 bucket_order=0
>>> [ 0.035747] squashfs: version 4.0 (2009/01/31) Phillip Lougher
>>> [ 0.035906] NFS: Registering the id_resolver key type
>>> [ 0.035919] Key type id_resolver registered
>>> [ 0.035922] Key type id_legacy registered
>>> [ 0.035933] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
>>> [ 0.035935] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
>>> [ 0.036031] 9p: Installing v9fs 9p2000 file system support
>>> [ 0.062587] Key type asymmetric registered
>>> [ 0.062596] Asymmetric key parser 'x509' registered
>>> [ 0.062657] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
>>> [ 0.062661] io scheduler mq-deadline registered
>>> [ 0.062664] io scheduler kyber registered
>>> [ 0.062688] io scheduler bfq registered
>>> [ 0.063318] irq_meson_gpio: 157 to 12 gpio interrupt mux initialized
>>> [ 0.068061] EINJ: ACPI disabled.
>>> [ 0.072570] amlogic_t7_pll_probe
>>> [ 0.072855] amlogic_t7_pll_probe ret 0
>>> [ 0.072943] amlogic_a1_periphs_probe
>>> [ 0.078155] amlogic_a1_periphs_probe ret 0
>>> [ 0.084876] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
>>> [ 0.086691] fe078000.serial: ttyS0 at MMIO 0xfe078000 (irq = 14, base_baud = 1500000) is a meson_uart
>>> [ 0.086710] printk: legacy console [ttyS0] enabled
>>> [ 0.229167] sysfs: cannot create duplicate filename '/class/tty/ttyS0'
>>> [ 0.229669] CPU: 3 PID: 1 Comm: swapper/0 Not tainted 6.8.0-09793-gda876e5b54b3-dirty #15
>>> [ 0.230684] Hardware name: Khadas vim4 (DT)
>>> [ 0.231205] Call trace:
>>> [ 0.231509] dump_backtrace+0x94/0xec
>>> [ 0.231963] show_stack+0x18/0x24
>>> [ 0.232374] dump_stack_lvl+0x78/0x90
>>> [ 0.232829] dump_stack+0x18/0x24
>>> [ 0.233241] sysfs_warn_dup+0x64/0x80
>>> [ 0.233696] sysfs_do_create_link_sd+0xf0/0xf8
>>> [ 0.234248] sysfs_create_link+0x20/0x40
>>> [ 0.234736] device_add+0x27c/0x77c
>>> [ 0.235169] device_register+0x20/0x30
>>> [ 0.235635] tty_register_device_attr+0xfc/0x240
>>> [ 0.236209] tty_port_register_device_attr_serdev+0x8c/0xac
>>> [ 0.236902] serial_core_register_port+0x318/0x658
>>> [ 0.237498] serial_ctrl_register_port+0x10/0x1c
>>> [ 0.238072] uart_add_one_port+0x10/0x1c
>>> [ 0.238560] meson_uart_probe+0x2c0/0x3b4
>>> [ 0.239058] platform_probe+0x68/0xd8
>>> [ 0.239513] really_probe+0x148/0x2b4
>>> [ 0.239968] __driver_probe_device+0x78/0x12c
>>> [ 0.240510] driver_probe_device+0xdc/0x160
>>> [ 0.241030] __driver_attach+0x94/0x19c
>>> [ 0.241507] bus_for_each_dev+0x74/0xd4
>>> [ 0.241983] driver_attach+0x24/0x30
>>> [ 0.242428] bus_add_driver+0xe4/0x1e8
>>> [ 0.242893] driver_register+0x60/0x128
>>> [ 0.243370] __platform_driver_register+0x28/0x34
>>> [ 0.243955] meson_uart_platform_driver_init+0x1c/0x28
>>> [ 0.244594] do_one_initcall+0x6c/0x1b0
>>> [ 0.245071] kernel_init_freeable+0x1cc/0x294
>>> [ 0.245613] kernel_init+0x20/0x1dc
>>> [ 0.246046] ret_from_fork+0x10/0x20
>>> [ 0.246555] meson_uart fe078000.serial: Cannot register tty device on line 0
>>> [ 0.247729] msm_serial: driver initialized
>>> [ 0.248150] SuperH (H)SCI(F) driver initialized
>>> [ 0.248544] STM32 USART driver initialized
>>> [ 0.263927] loop: module loaded
>>> [ 0.264952] megasas: 07.727.03.00-rc1
>>> [ 0.271065] tun: Universal TUN/TAP device driver, 1.6
>>> [ 0.271824] thunder_xcv, ver 1.0
>>> [ 0.271878] thunder_bgx, ver 1.0
>>> [ 0.271956] nicpf, ver 1.0
>>> [ 0.273230] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
>>> [ 0.273437] hns3: Copyright (c) 2017 Huawei Corporation.
>>> [ 0.274148] hclge is initializing
>>> [ 0.274541] e1000: Intel(R) PRO/1000 Network Driver
>>> [ 0.275116] e1000: Copyright (c) 1999-2006 Intel Corporation.
>>> [ 0.275860] e1000e: Intel(R) PRO/1000 Network Driver
>>> [ 0.276449] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
>>> [ 0.277209] igb: Intel(R) Gigabit Ethernet Network Driver
>>> [ 0.277867] igb: Copyright (c) 2007-2014 Intel Corporation.
>>> [ 0.278576] igbvf: Intel(R) Gigabit Virtual Function Network Driver
>>> [ 0.279330] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
>>> [ 0.280319] sky2: driver version 1.30
>>> [ 0.281597] VFIO - User Level meta-driver version: 0.3
>>> [ 0.283859] usbcore: registered new interface driver usb-storage
>>> [ 0.286328] i2c_dev: i2c /dev entries driver
>>> [ 0.292404] sdhci: Secure Digital Host Controller Interface driver
>>> [ 0.292481] sdhci: Copyright(c) Pierre Ossman
>>> [ 0.293577] Synopsys Designware Multimedia Card Interface Driver
>>> [ 0.294572] sdhci-pltfm: SDHCI platform and OF driver helper
>>> [ 0.296259] ledtrig-cpu: registered to indicate activity on CPUs
>>> [ 0.298966] meson-sm: secure-monitor enabled
>>> [ 0.299963] usbcore: registered new interface driver usbhid
>>> [ 0.299997] usbhid: USB HID core driver
>>> [ 0.306803] NET: Registered PF_PACKET protocol family
>>> [ 0.306919] 9pnet: Installing 9P2000 support
>>> [ 0.307331] Key type dns_resolver registered
>>> [ 0.318926] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
>>> [ 0.319462] registered taskstats version 1
>>> [ 0.319968] Loading compiled-in X.509 certificates
>>> [ 0.362771] clk: Disabling unused clocks
>>> [ 0.363100] PM: genpd: Disabling unused power domains
>>> [ 0.363383] ALSA device list:
>>> [ 0.363580] No soundcards found.
>>> [ 0.368194] meson-gx-mmc fe08a000.sd: Got CD GPIO
>>> [ 0.368524] SError Interrupt on CPU6, code 0x00000000bf000002 -- SError
>>> [ 0.368531] CPU: 6 PID: 87 Comm: kworker/u32:3 Not tainted 6.8.0-09793-gda876e5b54b3-dirty #15
>>> [ 0.368537] Hardware name: Khadas vim4 (DT)
>>> [ 0.368540] Workqueue: async async_run_entry_fn
>>> [ 0.368552] pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
>>> [ 0.368556] pc : clk_mux_val_to_index+0x0/0xc0
>>> [ 0.368565] lr : clk_mux_get_parent+0x4c/0x84
>>> [ 0.368571] sp : ffff800082efba10
>>> [ 0.368572] x29: ffff800082efba10 x28: ffff8000823279c0 x27: ffff800082327000
>>> [ 0.368578] x26: ffff000004c361c0 x25: 0000000000000000 x24: 0000000000000002
>>> [ 0.368584] x23: ffff000003f1d300 x22: ffff000003f1d2a0 x21: ffff000004c37280
>>> [ 0.368589] x20: ffff000004c36ec0 x19: ffff000004bba800 x18: 0000000000000020
>>> [ 0.368594] x17: ffff000000022000 x16: 0000000000000003 x15: ffffffffffffffff
>>> [ 0.368599] x14: ffffffffffffffff x13: 0078756d2364732e x12: 3030306138306566
>>> [ 0.368604] x11: 7f7f7f7f7f7f7f7f x10: ffff7fff83438910 x9 : 0000000000000005
>>> [ 0.368609] x8 : 0101010101010101 x7 : 0000000000000000 x6 : 05114367045e5359
>>> [ 0.368613] x5 : 0000000000000006 x4 : 0000000000000000 x3 : 0000000000000000
>>> [ 0.368618] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000004c36ec0
>>> [ 0.368624] Kernel panic - not syncing: Asynchronous SError Interrupt
>>> [ 0.368626] CPU: 6 PID: 87 Comm: kworker/u32:3 Not tainted 6.8.0-09793-gda876e5b54b3-dirty #15
>>> [ 0.368630] Hardware name: Khadas vim4 (DT)
>>> [ 0.368631] Workqueue: async async_run_entry_fn
>>> [ 0.368635] Call trace:
>>> [ 0.368637] dump_backtrace+0x94/0xec
>>> [ 0.368644] show_stack+0x18/0x24
>>> [ 0.368649] dump_stack_lvl+0x38/0x90
>>> [ 0.368656] dump_stack+0x18/0x24
>>> [ 0.368661] panic+0x388/0x3c8
>>> [ 0.368666] nmi_panic+0x48/0x94
>>> [ 0.368670] arm64_serror_panic+0x6c/0x78
>>> [ 0.368674] do_serror+0x3c/0x78
>>> [ 0.368677] el1h_64_error_handler+0x30/0x48
>>> [ 0.368681] el1h_64_error+0x64/0x68
>>> [ 0.368684] clk_mux_val_to_index+0x0/0xc0
>>> [ 0.368689] __clk_register+0x440/0x82c
>>> [ 0.368693] devm_clk_register+0x5c/0xbc
>>> [ 0.368697] meson_mmc_clk_init+0x11c/0x2a8
>>> [ 0.368702] meson_mmc_probe+0x18c/0x3c0
>>> [ 0.368705] platform_probe+0x68/0xd8
>>> [ 0.368711] really_probe+0x148/0x2b4
>>> [ 0.368714] __driver_probe_device+0x78/0x12c
>>> [ 0.368718] driver_probe_device+0xdc/0x160
>>> [ 0.368721] __device_attach_driver+0xb8/0x134
>>> [ 0.368724] bus_for_each_drv+0x84/0xe0
>>> [ 0.368727] __device_attach_async_helper+0xac/0xd0
>>> [ 0.368730] async_run_entry_fn+0x34/0xe0
>>> [ 0.368734] process_one_work+0x150/0x294
>>> [ 0.368740] worker_thread+0x304/0x408
>>> [ 0.368744] kthread+0x118/0x11c
>>> [ 0.368748] ret_from_fork+0x10/0x20
>>> [ 0.368753] SMP: stopping secondary CPUs
>>> [ 0.368760] Kernel Offset: disabled
>>> [ 0.368761] CPU features: 0x0,00000060,d0080000,0200421b
>>> [ 0.368765] Memory Limit: none
>>> [ 0.400328] ---[ end Kernel panic - not syncing: Asynchronous SError Interrupt ]---
>>>
>>>
>>> --
>>> 2.44.0
>>>
^ permalink raw reply
* Re: (subset) [PATCH v3 1/2] dt-bindings: arm: qcom: Add Motorola Moto G (2013)
From: Bjorn Andersson @ 2024-04-08 1:37 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stanislav Jakubek
Cc: linux-arm-msm, devicetree, linux-arm-kernel, phone-devel,
linux-kernel
In-Reply-To: <32c507337ab80c550fb1df08f7014d1e31eb4c32.1712480582.git.stano.jakubek@gmail.com>
On Sun, 07 Apr 2024 11:05:10 +0200, Stanislav Jakubek wrote:
> Document the Motorola Moto G (2013), which is a smartphone based
> on the Qualcomm MSM8226 SoC.
>
>
Applied, thanks!
[1/2] dt-bindings: arm: qcom: Add Motorola Moto G (2013)
commit: 4785ec47ec890fe66f31ee886a767dbdf2ea6bae
[2/2] ARM: dts: qcom: Add support for Motorola Moto G (2013)
commit: 49481b6a8f35017af23e9fdfb644095f50a474e3
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply
* Re: [PATCH 0/2] Small fixes for MSM8974 SoC dtsi
From: Bjorn Andersson @ 2024-04-08 1:37 UTC (permalink / raw)
To: ~postmarketos/upstreaming, phone-devel, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Luca Weiss
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240318-msm8974-misc2-v1-0-f71668a2b8cd@z3ntu.xyz>
On Mon, 18 Mar 2024 10:24:40 +0100, Luca Weiss wrote:
> One fix for dt schema validation, one for the /chosen node.
>
>
Applied, thanks!
[1/2] ARM: dts: qcom: msm8974: Add @0 to memory node name
commit: cad23ffd46e2205582f5a9e9014b3d78ec0256db
[2/2] ARM: dts: qcom: msm8974: Add empty chosen node
commit: 7018981366d496db4b7d5f6a5c2673683d2b1639
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply
* [PATCH v5 6/7] PCI: dwc: rcar-gen4: Add support for r8a779g0
From: Yoshihiro Shimoda @ 2024-04-08 1:24 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
In-Reply-To: <20240408012458.3717977-1-yoshihiro.shimoda.uh@renesas.com>
This driver previously supported r8a779f0 (R-Car S4-8). Add support
for r8a779g0 (R-Car V4H).
To support r8a779g0, it requires specific firmware.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 201 +++++++++++++++++++-
1 file changed, 200 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index 47ec394885f5..a62804674f4e 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -5,8 +5,10 @@
*/
#include <linux/delay.h>
+#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pci.h>
@@ -20,9 +22,10 @@
/* Renesas-specific */
/* PCIe Mode Setting Register 0 */
#define PCIEMSR0 0x0000
-#define BIFUR_MOD_SET_ON BIT(0)
+#define APP_SRIS_MODE BIT(6)
#define DEVICE_TYPE_EP 0
#define DEVICE_TYPE_RC BIT(4)
+#define BIFUR_MOD_SET_ON BIT(0)
/* PCIe Interrupt Status 0 */
#define PCIEINTSTS0 0x0084
@@ -37,19 +40,47 @@
#define PCIEDMAINTSTSEN 0x0314
#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
+/* Port Logic Registers 89 */
+#define PRTLGC89 0x0b70
+
+/* Port Logic Registers 90 */
+#define PRTLGC90 0x0b74
+
/* PCIe Reset Control Register 1 */
#define PCIERSTCTRL1 0x0014
#define APP_HOLD_PHY_RST BIT(16)
#define APP_LTSSM_ENABLE BIT(0)
+/* PCIe Power Management Control */
+#define PCIEPWRMNGCTRL 0x0070
+#define APP_CLK_REQ_N BIT(11)
+#define APP_CLK_PM_EN BIT(10)
+
+/*
+ * The R-Car Gen4 documents don't describe the PHY registers' name.
+ * But, the initialization procedure describes these offsets. So,
+ * this driver makes up own #defines for the offsets.
+ */
+#define RCAR_GEN4_PCIE_PHY_0f8 0x0f8
+#define RCAR_GEN4_PCIE_PHY_148 0x148
+#define RCAR_GEN4_PCIE_PHY_1d4 0x1d4
+#define RCAR_GEN4_PCIE_PHY_514 0x514
+#define RCAR_GEN4_PCIE_PHY_700 0x700
+
#define RCAR_NUM_SPEED_CHANGE_RETRIES 10
#define RCAR_MAX_LINK_SPEED 4
#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
+#define RCAR_GEN4_PCIE_FIRMWARE_NAME "rcar_gen4_pcie.bin"
+#define RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR 0xc000
+
+MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME);
+
struct rcar_gen4_pcie;
struct rcar_gen4_pcie_platdata {
+ void (*additional_common_init)(struct rcar_gen4_pcie *rcar);
int (*ltssm_enable)(struct rcar_gen4_pcie *rcar);
enum dw_pcie_device_mode mode;
};
@@ -57,12 +88,144 @@ struct rcar_gen4_pcie_platdata {
struct rcar_gen4_pcie {
struct dw_pcie dw;
void __iomem *base;
+ void __iomem *phy_base;
struct platform_device *pdev;
const struct rcar_gen4_pcie_platdata *platdata;
};
#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
/* Common */
+static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar,
+ u32 offset, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ tmp = readl(rcar->phy_base + offset);
+ tmp &= ~mask;
+ tmp |= val;
+ writel(tmp, rcar->phy_base + offset);
+}
+
+static int rcar_gen4_pcie_reg_check_bit(struct rcar_gen4_pcie *rcar,
+ u32 offset, u32 mask)
+{
+ struct dw_pcie *dw = &rcar->dw;
+
+ if (dw_pcie_readl_dbi(dw, offset) & mask)
+ return -EAGAIN;
+
+ return 0;
+}
+
+static int rcar_gen4_pcie_update_phy_firmware(struct rcar_gen4_pcie *rcar)
+{
+ const u32 check_addr[] = { 0x00101018, 0x00101118, 0x00101021, 0x00101121};
+ struct dw_pcie *dw = &rcar->dw;
+ const struct firmware *fw;
+ unsigned int i, timeout;
+ u32 data;
+ int ret;
+
+ ret = request_firmware(&fw, RCAR_GEN4_PCIE_FIRMWARE_NAME, dw->dev);
+ if (ret) {
+ dev_err(dw->dev, "%s: Requesting firmware failed\n", __func__);
+ return ret;
+ }
+
+ for (i = 0; i < (fw->size / 2); i++) {
+ data = fw->data[i * 2] | fw->data[(i * 2) + 1] << 8;
+ timeout = 100;
+ do {
+ dw_pcie_writel_dbi(dw, PRTLGC89, RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR + i);
+ dw_pcie_writel_dbi(dw, PRTLGC90, data);
+ if (rcar_gen4_pcie_reg_check_bit(rcar, PRTLGC89, BIT(30)) >= 0)
+ break;
+ if (!(--timeout)) {
+ ret = -ETIMEDOUT;
+ goto exit;
+ }
+ usleep_range(100, 200);
+ } while (1);
+ }
+
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_0f8, BIT(17), BIT(17));
+
+ for (i = 0; i < ARRAY_SIZE(check_addr); i++) {
+ timeout = 100;
+ do {
+ dw_pcie_writel_dbi(dw, PRTLGC89, check_addr[i]);
+ ret = rcar_gen4_pcie_reg_check_bit(rcar, PRTLGC89, BIT(30));
+ ret |= rcar_gen4_pcie_reg_check_bit(rcar, PRTLGC90, BIT(0));
+ if (ret >= 0)
+ break;
+ if (!(--timeout)) {
+ ret = -ETIMEDOUT;
+ goto exit;
+ }
+ usleep_range(100, 200);
+ } while (1);
+ }
+
+ ret = 0;
+exit:
+ release_firmware(fw);
+
+ return ret;
+}
+
+static int rcar_gen4_pcie_enable_phy(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie *dw = &rcar->dw;
+ u32 val;
+ int ret;
+
+ val = dw_pcie_readl_dbi(dw, PCIE_PORT_FORCE);
+ val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;
+ dw_pcie_writel_dbi(dw, PCIE_PORT_FORCE, val);
+
+ val = readl(rcar->base + PCIEMSR0);
+ val |= APP_SRIS_MODE;
+ writel(val, rcar->base + PCIEMSR0);
+
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_700, BIT(28), 0);
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_700, BIT(20), 0);
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_700, BIT(12), 0);
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_700, BIT(4), 0);
+
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_148,
+ GENMASK(23, 22), BIT(22));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_148,
+ GENMASK(18, 16), GENMASK(17, 16));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_148,
+ GENMASK(7, 6), BIT(6));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_148,
+ GENMASK(2, 0), GENMASK(11, 0));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_1d4,
+ GENMASK(16, 15), GENMASK(16, 15));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_514, BIT(26), BIT(26));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_0f8, BIT(16), 0);
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_0f8, BIT(19), BIT(19));
+
+ val = readl(rcar->base + PCIERSTCTRL1);
+ val &= ~APP_HOLD_PHY_RST;
+ writel(val, rcar->base + PCIERSTCTRL1);
+
+ ret = readl_poll_timeout(rcar->phy_base + RCAR_GEN4_PCIE_PHY_0f8, val,
+ !(val & BIT(18)), 100, 10000);
+ if (ret < 0)
+ return ret;
+
+ ret = rcar_gen4_pcie_update_phy_firmware(rcar);
+ if (ret)
+ return ret;
+
+ val = readl(rcar->base + PCIERSTCTRL1);
+ val |= APP_LTSSM_ENABLE;
+ writel(val, rcar->base + PCIERSTCTRL1);
+
+ return 0;
+}
+
static void rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar,
bool enable)
{
@@ -200,6 +363,9 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
if (ret)
goto err_unprepare;
+ if (rcar->platdata->additional_common_init)
+ rcar->platdata->additional_common_init(rcar);
+
return 0;
err_unprepare:
@@ -241,6 +407,10 @@ static void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
{
+ rcar->phy_base = devm_platform_ioremap_resource_byname(rcar->pdev, "phy");
+ if (IS_ERR(rcar->phy_base))
+ return PTR_ERR(rcar->base);
+
/* Renesas-specific registers */
rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
@@ -517,6 +687,31 @@ static int r8a779f0_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar)
return 0;
}
+static void rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie *dw = &rcar->dw;
+ u32 val;
+
+ /*
+ * The SoC manual said the register setting is required. Otherwise,
+ * linkup failed.
+ */
+ val = dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW);
+ val &= ~PORT_LANE_SKEW_INSERT_MASK;
+ if (dw->num_lanes < 4)
+ val |= BIT(6);
+ dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val);
+
+ val = readl(rcar->base + PCIEPWRMNGCTRL);
+ val |= APP_CLK_REQ_N | APP_CLK_PM_EN;
+ writel(val, rcar->base + PCIEPWRMNGCTRL);
+}
+
+static int rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar)
+{
+ return rcar_gen4_pcie_enable_phy(rcar);
+}
+
static struct rcar_gen4_pcie_platdata platdata_r8a779f0_pcie = {
.ltssm_enable = r8a779f0_pcie_ltssm_enable,
.mode = DW_PCIE_RC_TYPE,
@@ -528,10 +723,14 @@ static struct rcar_gen4_pcie_platdata platdata_r8a779f0_pcie_ep = {
};
static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie = {
+ .additional_common_init = rcar_gen4_pcie_additional_common_init,
+ .ltssm_enable = rcar_gen4_pcie_ltssm_enable,
.mode = DW_PCIE_RC_TYPE,
};
static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie_ep = {
+ .additional_common_init = rcar_gen4_pcie_additional_common_init,
+ .ltssm_enable = rcar_gen4_pcie_ltssm_enable,
.mode = DW_PCIE_EP_TYPE,
};
--
2.25.1
^ permalink raw reply related
* [PATCH v5 4/7] PCI: dwc: rcar-gen4: Add rcar_gen4_pcie_platdata
From: Yoshihiro Shimoda @ 2024-04-08 1:24 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
In-Reply-To: <20240408012458.3717977-1-yoshihiro.shimoda.uh@renesas.com>
This driver supports r8a779f0 now. In the future, add support for
r8a779g0 and r8a779h0. To support these new SoCs, need other
initializing settings. So, at first, add rcar_gen4_pcie_platdata
and have a member with mode. No behavior changes.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 30 ++++++++++++++-------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index 0be760ed420b..da2821d6efce 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -48,11 +48,15 @@
#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
+struct rcar_gen4_pcie_platdata {
+ enum dw_pcie_device_mode mode;
+};
+
struct rcar_gen4_pcie {
struct dw_pcie dw;
void __iomem *base;
struct platform_device *pdev;
- enum dw_pcie_device_mode mode;
+ const struct rcar_gen4_pcie_platdata *platdata;
};
#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
@@ -137,7 +141,7 @@ static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
* Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
* So, this needs remaining times for up to PCIe Gen4 if RC mode.
*/
- if (changes && rcar->mode == DW_PCIE_RC_TYPE)
+ if (changes && rcar->platdata->mode == DW_PCIE_RC_TYPE)
changes--;
for (i = 0; i < changes; i++) {
@@ -172,9 +176,9 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
val = readl(rcar->base + PCIEMSR0);
- if (rcar->mode == DW_PCIE_RC_TYPE) {
+ if (rcar->platdata->mode == DW_PCIE_RC_TYPE) {
val |= DEVICE_TYPE_RC;
- } else if (rcar->mode == DW_PCIE_EP_TYPE) {
+ } else if (rcar->platdata->mode == DW_PCIE_EP_TYPE) {
val |= DEVICE_TYPE_EP;
} else {
ret = -EINVAL;
@@ -437,9 +441,9 @@ static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
/* Common */
static int rcar_gen4_add_dw_pcie(struct rcar_gen4_pcie *rcar)
{
- rcar->mode = (uintptr_t)of_device_get_match_data(&rcar->pdev->dev);
+ rcar->platdata = of_device_get_match_data(&rcar->pdev->dev);
- switch (rcar->mode) {
+ switch (rcar->platdata->mode) {
case DW_PCIE_RC_TYPE:
return rcar_gen4_add_dw_pcie_rp(rcar);
case DW_PCIE_EP_TYPE:
@@ -480,7 +484,7 @@ static int rcar_gen4_pcie_probe(struct platform_device *pdev)
static void rcar_gen4_remove_dw_pcie(struct rcar_gen4_pcie *rcar)
{
- switch (rcar->mode) {
+ switch (rcar->platdata->mode) {
case DW_PCIE_RC_TYPE:
rcar_gen4_remove_dw_pcie_rp(rcar);
break;
@@ -500,14 +504,22 @@ static void rcar_gen4_pcie_remove(struct platform_device *pdev)
rcar_gen4_pcie_unprepare(rcar);
}
+static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie = {
+ .mode = DW_PCIE_RC_TYPE,
+};
+
+static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie_ep = {
+ .mode = DW_PCIE_EP_TYPE,
+};
+
static const struct of_device_id rcar_gen4_pcie_of_match[] = {
{
.compatible = "renesas,rcar-gen4-pcie",
- .data = (void *)DW_PCIE_RC_TYPE,
+ .data = &platdata_rcar_gen4_pcie,
},
{
.compatible = "renesas,rcar-gen4-pcie-ep",
- .data = (void *)DW_PCIE_EP_TYPE,
+ .data = &platdata_rcar_gen4_pcie_ep,
},
{},
};
--
2.25.1
^ permalink raw reply related
* [PATCH v5 7/7] misc: pci_endpoint_test: Document a policy about adding pci_device_id
From: Yoshihiro Shimoda @ 2024-04-08 1:24 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Frank Li
In-Reply-To: <20240408012458.3717977-1-yoshihiro.shimoda.uh@renesas.com>
To avoid becoming struct pci_device_id pci_endpoint_test_tbl longer
and longer, document a policy. For example, if PCIe endpoint controller
can configure vendor id and/or product id, you can reuse one of
existing entries to test.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
Cc: Frank Li <Frank.li@nxp.com>
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index c38a6083f0a7..3c8a0afad91d 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -980,6 +980,7 @@ static const struct pci_endpoint_test_data j721e_data = {
.irq_type = IRQ_TYPE_MSI,
};
+/* Don't need to add a new entry if you can use existing entry to test */
static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
.driver_data = (kernel_ulong_t)&default_data,
--
2.25.1
^ permalink raw reply related
* [PATCH v5 2/7] dt-bindings: PCI: rcar-gen4-pci-ep: Add R-Car V4H compatible
From: Yoshihiro Shimoda @ 2024-04-08 1:24 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Conor Dooley, Geert Uytterhoeven
In-Reply-To: <20240408012458.3717977-1-yoshihiro.shimoda.uh@renesas.com>
Document bindings for R-Car V4H (R8A779G0) PCIe endpoint module.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
index fe38f62da066..91b81ac75592 100644
--- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
@@ -16,7 +16,9 @@ allOf:
properties:
compatible:
items:
- - const: renesas,r8a779f0-pcie-ep # R-Car S4-8
+ - enum:
+ - renesas,r8a779f0-pcie-ep # R-Car S4-8
+ - renesas,r8a779g0-pcie-ep # R-Car V4H
- const: renesas,rcar-gen4-pcie-ep # R-Car Gen4
reg:
--
2.25.1
^ permalink raw reply related
* [PATCH v5 5/7] PCI: dwc: rcar-gen4: Add .ltssm_enable() for other SoC support
From: Yoshihiro Shimoda @ 2024-04-08 1:24 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
In-Reply-To: <20240408012458.3717977-1-yoshihiro.shimoda.uh@renesas.com>
This driver can reuse other R-Car Gen4 SoCs support like r8a779g0 and
r8a779h0. However, r8a779g0 and r8a779h0 require other initializing
settings that differ than r8a779f0. So, add a new function pointer
.ltssm_enable() for it. No behavior changes.
After applied this patch, probing SoCs by rcar_gen4_pcie_of_match[]
will be changed like below:
- r8a779f0 as "renesas,r8a779f0-pcie" and "renesas,r8a779f0-pcie-ep"
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 41 ++++++++++++++++++---
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index da2821d6efce..47ec394885f5 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -48,7 +48,9 @@
#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
+struct rcar_gen4_pcie;
struct rcar_gen4_pcie_platdata {
+ int (*ltssm_enable)(struct rcar_gen4_pcie *rcar);
enum dw_pcie_device_mode mode;
};
@@ -61,8 +63,8 @@ struct rcar_gen4_pcie {
#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
/* Common */
-static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
- bool enable)
+static void rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar,
+ bool enable)
{
u32 val;
@@ -127,9 +129,13 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
{
struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
- int i, changes;
+ int i, changes, ret;
- rcar_gen4_pcie_ltssm_enable(rcar, true);
+ if (rcar->platdata->ltssm_enable) {
+ ret = rcar->platdata->ltssm_enable(rcar);
+ if (ret)
+ return ret;
+ }
/*
* Require direct speed change with retrying here if the link_gen is
@@ -157,7 +163,7 @@ static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
{
struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
- rcar_gen4_pcie_ltssm_enable(rcar, false);
+ rcar_gen4_pcie_ltssm_control(rcar, false);
}
static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
@@ -504,6 +510,23 @@ static void rcar_gen4_pcie_remove(struct platform_device *pdev)
rcar_gen4_pcie_unprepare(rcar);
}
+static int r8a779f0_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar)
+{
+ rcar_gen4_pcie_ltssm_control(rcar, true);
+
+ return 0;
+}
+
+static struct rcar_gen4_pcie_platdata platdata_r8a779f0_pcie = {
+ .ltssm_enable = r8a779f0_pcie_ltssm_enable,
+ .mode = DW_PCIE_RC_TYPE,
+};
+
+static struct rcar_gen4_pcie_platdata platdata_r8a779f0_pcie_ep = {
+ .ltssm_enable = r8a779f0_pcie_ltssm_enable,
+ .mode = DW_PCIE_EP_TYPE,
+};
+
static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie = {
.mode = DW_PCIE_RC_TYPE,
};
@@ -513,6 +536,14 @@ static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie_ep = {
};
static const struct of_device_id rcar_gen4_pcie_of_match[] = {
+ {
+ .compatible = "renesas,r8a779f0-pcie",
+ .data = &platdata_r8a779f0_pcie,
+ },
+ {
+ .compatible = "renesas,r8a779f0-pcie-ep",
+ .data = &platdata_r8a779f0_pcie_ep,
+ },
{
.compatible = "renesas,rcar-gen4-pcie",
.data = &platdata_rcar_gen4_pcie,
--
2.25.1
^ permalink raw reply related
* [PATCH v5 1/7] dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car V4H compatible
From: Yoshihiro Shimoda @ 2024-04-08 1:24 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Conor Dooley, Geert Uytterhoeven
In-Reply-To: <20240408012458.3717977-1-yoshihiro.shimoda.uh@renesas.com>
Document bindings for R-Car V4H (R8A779G0) PCIe host module.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
index ffb34339b637..955c664f1fbb 100644
--- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
@@ -16,7 +16,9 @@ allOf:
properties:
compatible:
items:
- - const: renesas,r8a779f0-pcie # R-Car S4-8
+ - enum:
+ - renesas,r8a779f0-pcie # R-Car S4-8
+ - renesas,r8a779g0-pcie # R-Car V4H
- const: renesas,rcar-gen4-pcie # R-Car Gen4
reg:
--
2.25.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox