* Re: [PATCH v2] arm64: dts: broadcom: bcm2712: Add V3D device node
From: Peter Robinson @ 2026-01-16 3:53 UTC (permalink / raw)
To: Maíra Canal, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Florian Fainelli, Stefan Wahren,
Broadcom internal kernel review list
Cc: dri-devel, devicetree, linux-rpi-kernel, linux-arm-kernel,
kernel-dev
In-Reply-To: <20260114120610.82531-1-mcanal@igalia.com>
Hi Maira,
On 14/01/2026 12:04, Maíra Canal wrote:
> Commits 0ad5bc1ce463 ("drm/v3d: fix up register addresses for V3D 7.x")
> and 6fd9487147c4 ("drm/v3d: add brcm,2712-v3d as a compatible V3D device")
> added driver support for V3D on BCM2712, but the corresponding device
> tree node is still missing.
>
> Add the V3D device tree node to the BCM2712 DTS.
>
> Signed-off-by: Maíra Canal <mcanal@igalia.com>
>
> ---
> v1 -> v2:
>
> - Rebased on top of linux-next (Stefan Wahren)
> - Fixed node's address (2000000 -> 1002000000) (Stefan Wahren)
> - Link to v1: https://lore.kernel.org/linux-devicetree/20260113192902.48046-2-mcanal@igalia.com/
> ---
> .../boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi | 4 ++++
> arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 14 ++++++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
> index 7d4742ebe247..97522c6803c5 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
> @@ -247,3 +247,7 @@ &pcie1 {
> &pcie2 {
> status = "okay";
> };
> +
> +&v3d {
> + clocks = <&firmware_clocks 5>;
Looking at the upstream DT [1] I think this also needs a clock-names entry.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi#n233
> +};
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> index 330a121ebfcb..661668ef7419 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
> @@ -1,5 +1,6 @@
> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/bcm2835-pm.h>
>
> / {
> compatible = "brcm,bcm2712";
> @@ -642,6 +643,19 @@ mip1: msi-controller@1000131000 {
> msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>;
> brcm,msi-offset = <8>;
> };
> +
> + v3d: gpu@1002000000 {
> + compatible = "brcm,2712-v3d";
> + reg = <0x10 0x02000000 0x00 0x4000>,
> + <0x10 0x02008000 0x00 0x6000>,
> + <0x10 0x02030800 0x00 0x0700>;
> + reg-names = "hub", "core0", "sms";
> +
> + power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
> + resets = <&pm BCM2835_RESET_V3D>;
> + interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
> + };
> };
>
> vc4: gpu {
^ permalink raw reply
* [PATCH v3 2/2] arm64: dts: freescale: add NXP FRDM-IMX91S board support
From: Yanan Yang @ 2026-01-16 3:45 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, yanan.yang,
qijian.guo, justin.jiang, Lei Xu, Xiaofeng Wei
In-Reply-To: <20260116-imx91s-frdm-v3-0-98671de64925@nxp.com>
Add DeviceTree support for the NXP FRDM-IMX91S development board based
on the i.MX91 SoC. FRDM-IMX91S is a cost-optimized variant of FRDM-IMX91
and differs in memory, storage, Ethernet, and PMIC configuration:
- 512MB LPDDR4 (FRDM-IMX91 uses 1GB)
- 256MB FlexSPI-NAND (FRDM-IMX91 uses 8GB eMMC)
- Single GbE port (FRDM-IMX91 has dual GbE)
- PMIC PF9453 (FRDM-IMX91 uses PCA9451A)
This DT enables:
- ADC1
- UART1 and UART5
- I2C bus and children nodes
- USB and related nodes
- uSDHC1 and uSDHC2
- FlexSPI NAND flash
- Watchdog3
- Ethernet (eqos)
- FlexCAN
- MQS
Link: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX91S
(FRDM-IMX91S board page)
Link: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX91
(FRDM-IMX91 board page)
Co-developed-by: Lei Xu <lei.xu@nxp.com>
Signed-off-by: Lei Xu <lei.xu@nxp.com>
Co-developed-by: Xiaofeng Wei <xiaofeng.wei@nxp.com>
Signed-off-by: Xiaofeng Wei <xiaofeng.wei@nxp.com>
Signed-off-by: Yanan Yang <yanan.yang@nxp.com>
---
Changes in v3:
- add bootph- property for nodes should be kept in bootloader phase
Changes in v2:
- Correct author name: removed extra period in "Yanan.Yang"
- Removed aliases pointing to disabled nodes from DTS
- Add "rtc0 = &pcf2131;" in aliases to make external RTC the primary device
- Fix DT node name: change
"usdhc1_pwrseq: usdhc1_pwrseq" to "usdhc1_pwrseq: usdhc1-pwrseq"
- Renamed LED node from 'status' to 'led-0' to comply with gpio-leds binding
- Replace regulator-based transceiver (reg_can_stby) with CAN PHY (nxp,tja1051)
- Replaced 'xceiver-supply' property with 'phys' in flexcan1 node
- Adjusted alignment in fsl,pins property: used spaces between pin names and values for proper DTS style.
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/imx91-11x11-frdm-s.dts | 771 +++++++++++++++++++++
2 files changed, 772 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index f30d3fd724d0..927bf76a05f3 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -368,6 +368,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-frdm-s.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm-s.dts
new file mode 100644
index 000000000000..d8a455265296
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm-s.dts
@@ -0,0 +1,771 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx91.dtsi"
+
+/ {
+ compatible = "fsl,imx91-11x11-frdm-s", "fsl,imx91";
+ model = "NXP FRDM-IMX91S board";
+
+ aliases {
+ ethernet0 = &eqos;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ rtc0 = &pcf2131;
+ rtc1 = &bbnsm_rtc;
+ serial0 = &lpuart1;
+ serial4 = &lpuart5;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ flexcan1_phy: can-phy {
+ compatible = "nxp,tja1051";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ silent-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&pinctrl_gpio_key>;
+ pinctrl-names = "default";
+
+ button {
+ interrupt-parent = <&gpio3>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+ gpios = <&gpio3 26 GPIO_PULL_UP>;
+ label = "User Button";
+ linux,code = <BTN_1>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ default-state = "on";
+ gpios = <&pcal6524 7 GPIO_ACTIVE_LOW>;
+ label = "green:status";
+ };
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vref_1v8";
+ };
+
+ reg_usdhc1_vmmc: regulator-usdhc1 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "WLAN_EN";
+ startup-delay-us = <20000>;
+ gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ off-on-delay-us = <12000>;
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VSD_3V3";
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ reg_usb_vbus: regulator-vbus {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "USB_VBUS";
+ gpio = <&pcal6524 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x20000000>;
+ reusable;
+ size = <0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+
+ soc@0 {
+ bootph-all;
+ bootph-pre-ram;
+ };
+
+ sound-mqs {
+ compatible = "fsl,imx6sx-sdb-mqs", "fsl,imx-audio-mqs";
+ audio-codec = <&mqs1>;
+ audio-cpu = <&sai1>;
+ model = "mqs-audio";
+ };
+
+ usdhc1_pwrseq: usdhc1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pcal6524 18 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&adc1 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
+&aips1 {
+ bootph-pre-ram;
+ bootph-all;
+};
+
+&aips2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&aips3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&clk {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&clk_ext1 {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&eqos {
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_eqos>;
+ pinctrl-1 = <&pinctrl_eqos_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy1: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ };
+ };
+};
+
+&flexcan1 {
+ phys = <&flexcan1_phy>;
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ pinctrl-1 = <&pinctrl_flexcan1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+};
+
+&flexspi1 {
+ pinctrl-0 = <&pinctrl_flexspi1>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <104000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x000000 0x800000>;
+ label = "bootloader";
+ };
+
+ partition@1 {
+ reg = <0x800000 0x800000>;
+ label = "env";
+ };
+
+ partition@2 {
+ reg = <0x1000000 0x2800000>;
+ label = "kernel";
+ };
+
+ partition@3 {
+ reg = <0x3800000 0x20000>;
+ label = "dtb";
+ };
+
+ partition@4 {
+ reg = <0x3820000 0xc7e0000>;
+ label = "rootfs";
+ linux,rootfs;
+ };
+ };
+ };
+};
+
+&gpio1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&iomuxc {
+ bootph-pre-ram;
+ bootph-some-ram;
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
+ MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
+ MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
+ MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
+ MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_eqos_sleep: eqossleepgrp {
+ fsl,pins = <
+ MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
+ MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
+ MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
+ MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
+ MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
+ MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
+ MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
+ MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
+ MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
+ MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
+ MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
+ MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e
+ MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
+ MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO28__CAN1_TX 0x139e
+ MX91_PAD_GPIO_IO29__CAN1_RX 0x139e
+ MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
+ >;
+ };
+
+ pinctrl_flexcan1_sleep: flexcan1sleepgrp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO28__GPIO2_IO28 0x31e
+ MX91_PAD_GPIO_IO29__GPIO2_IO29 0x31e
+ MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
+ >;
+ };
+
+ pinctrl_flexspi1: flexspi1grp {
+ fsl,pins = <
+ MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe
+ MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe
+ MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x3fe
+ MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x3fe
+ MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x3fe
+ MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x3fe
+ >;
+ };
+
+ pinctrl_gpio_key: gpiokeysgrp {
+ fsl,pins = <
+ MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_mqs1: mqs1grp {
+ fsl,pins = <
+ MX91_PAD_PDM_CLK__MQS1_LEFT 0x31e
+ MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
+ MX91_PAD_SD1_DATA5__GPIO3_IO15 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
+ >;
+ bootph-pre-ram;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
+ MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
+ MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
+ MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
+ MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e
+ MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e
+ MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e
+ MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2sleepgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
+ MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
+ MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
+ MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
+ MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
+ MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
+ MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
+ >;
+ };
+};
+
+&lpi2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-names = "default";
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+
+ pcf2131: rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&lpi2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-names = "default";
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ };
+
+ pmic@32 {
+ compatible = "nxp,pf9453";
+ reg = <0x32>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ bootph-pre-ram;
+ bootph-some-ram;
+
+ regulators {
+ bootph-pre-ram;
+ bootph-some-ram;
+
+ buck1: BUCK1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3775000>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK1";
+ };
+
+ buck2: BUCK2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2187500>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK2";
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck3: BUCK3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3775000>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK3";
+ };
+
+ buck4: BUCK4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3775000>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK4";
+ };
+
+ ldo1: LDO1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <800000>;
+ regulator-name = "LDO1";
+ };
+
+ ldo2: LDO2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1950000>;
+ regulator-min-microvolt = <500000>;
+ regulator-name = "LDO2";
+ };
+
+ ldo_snvs: LDO-SNVS {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-name = "LDO-SNVS";
+ };
+ };
+ };
+
+ ptn5110: tcpc@52 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x52>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ op-sink-microwatt = <15000000>;
+ power-role = "dual";
+ self-powered;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&lpuart1 {
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+};
+
+&lpuart5 {
+ pinctrl-0 = <&pinctrl_uart5>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+&media_blk_ctrl {
+ status = "okay";
+};
+
+&mqs1 {
+ clocks = <&clk IMX93_CLK_MQS1_GATE>;
+ clock-names = "mclk";
+ pinctrl-0 = <&pinctrl_mqs1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&osc_32k {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&osc_24m {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&sai1 {
+ clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k";
+ assigned-clocks = <&clk IMX93_CLK_SAI1>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <24576000>;
+ #sound-dai-cells = <0>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&usbotg1 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ usb-role-switch;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ disable-over-current;
+ dr_mode = "host";
+ vbus-supply = <®_usb_vbus>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&usdhc1_pwrseq>;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ vmmc-supply = <®_usdhc1_vmmc>;
+ wakeup-source;
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+};
+
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ no-mmc;
+ no-sdio;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+};
+
+&wdog3 {
+ pinctrl-0 = <&pinctrl_wdog>;
+ pinctrl-names = "default";
+ fsl,ext-reset-output;
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v3 1/2] dt-bindings: arm: fsl: Add FRDM-IMX91S board
From: Yanan Yang @ 2026-01-16 3:45 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, yanan.yang,
qijian.guo, justin.jiang, Krzysztof Kozlowski
In-Reply-To: <20260116-imx91s-frdm-v3-0-98671de64925@nxp.com>
Add DT compatible string for NXP FRDM-IMX91S board
The FRDM-IMX91S is a low-cost, compact development board based on the
i.MX91 applications processor. It is a cost-optimized variant of the
FRDM-IMX91 board, with notable hardware differences requiring a separate
DTS:
- 512MB LPDDR4 (FRDM-IMX91 uses 1GB)
- 256MB FlexSPI-NAND (FRDM-IMX91 uses 8GB eMMC)
- Single GbE port (FRDM-IMX91 has dual GbE)
- PMIC PF9453 (FRDM-IMX91 uses PCA9451A)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yanan Yang <yanan.yang@nxp.com>
---
Changes in v3:
- add code-review trailers
Changes in v2:
- Correct author name: removed extra period in "Yanan.Yang"
- Refined commit message to clarify board differences
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 68a2d5fecc43..82f28be401b8 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1412,6 +1412,7 @@ properties:
items:
- enum:
- fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board
+ - fsl,imx91-11x11-frdm-s # FRDM-IMX91S Board
- const: fsl,imx91
- description: i.MX93 based Boards
--
2.43.0
^ permalink raw reply related
* [PATCH v3 0/2] Add NXP FRDM-IMX91S board support
From: Yanan Yang @ 2026-01-16 3:45 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, yanan.yang,
qijian.guo, justin.jiang, Krzysztof Kozlowski, Lei Xu,
Xiaofeng Wei
This patch set introduces DeviceTree support for the NXP FRDM-IMX91S
development board based on the i.MX91 SoC. FRDM-IMX91S is a cost-optimized
variant of FRDM-IMX91 and differs in several hardware aspects:
- 512MB LPDDR4 (FRDM-IMX91 uses 1GB)
- 256MB FlexSPI-NAND (FRDM-IMX91 uses 8GB eMMC)
- Single GbE port (FRDM-IMX91 has dual GbE)
- PMIC PF9453 (FRDM-IMX91 uses PCA9451A)
This patch has been tested on FRDM-IMX91S board and verified for basic
functionality.
For more details about the FRDM-IMX91S board, see:
https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX91S
Signed-off-by: Yanan Yang <yanan.yang@nxp.com>
---
Changes in v3:
- add bootph- property for nodes should be kept in bootloader phase
- add code-review trailers
- Link to v2: https://lore.kernel.org/r/20251215-imx91s-frdm-v2-0-87996bdaa59c@nxp.com
Changes in v2:
- Correct author name: removed extra period in "Yanan.Yang"
- Removed aliases pointing to disabled nodes from DTS
- Add "rtc0 = &pcf2131;" in aliases to make external RTC the primary device
- Fix DT node name: change
"usdhc1_pwrseq: usdhc1_pwrseq" to "usdhc1_pwrseq: usdhc1-pwrseq"
- Renamed LED node from 'status' to 'led-0' to comply with gpio-leds binding
- Replace regulator-based transceiver (reg_can_stby) with CAN PHY (nxp,tja1051)
- Replaced 'xceiver-supply' property with 'phys' in flexcan1 node
- Adjusted alignment in fsl,pins property: used spaces between pin names and values for proper DTS style.
- Refined commit message in dt binding patch to clarify board differences
- Link to v1: https://lore.kernel.org/r/20251205-imx91s-frdm-v1-0-afd6cd01c299@nxp.com
---
Yanan Yang (2):
dt-bindings: arm: fsl: Add FRDM-IMX91S board
arm64: dts: freescale: add NXP FRDM-IMX91S board support
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/imx91-11x11-frdm-s.dts | 771 +++++++++++++++++++++
3 files changed, 773 insertions(+)
---
base-commit: bc04acf4aeca588496124a6cf54bfce3db327039
change-id: 20251205-imx91s-frdm-2c339bcc2f6f
Best regards,
--
Yanan Yang <yanan.yang@nxp.com>
^ permalink raw reply
* Re: [PATCH net-next v3 0/2] net: airoha: Init Block Ack memory region for MT7996 NPU offloading
From: patchwork-bot+netdevbpf @ 2026-01-16 3:40 UTC (permalink / raw)
To: Lorenzo Bianconi
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, robh, krzk+dt,
conor+dt, netdev, devicetree, linux-arm-kernel, linux-mediatek
In-Reply-To: <20260108-airoha-ba-memory-region-v3-0-bf1814e5dcc4@kernel.org>
Hello:
This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Thu, 08 Jan 2026 16:05:06 +0100 you wrote:
> This is a preliminary series in order to enable NPU offloading for
> MT7996 (Eagle) chipset.
>
> ---
> Changes in v3:
> - Add missing minItems for memory-region-names in airoha,en7581-npu.yaml
> - Link to v2: https://lore.kernel.org/r/20260107-airoha-ba-memory-region-v2-0-d8195fc66731@kernel.org
>
> [...]
Here is the summary with links:
- [net-next,v3,1/2] dt-bindings: net: airoha: npu: Add BA memory region
https://git.kernel.org/netdev/net-next/c/40f9e446033e
- [net-next,v3,2/2] net: airoha: npu: Init BA memory region if provided via DTS
https://git.kernel.org/netdev/net-next/c/875a59c9a9e5
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH v3 0/2] net: phy: adin: enable configuration of the LP Termination Register
From: patchwork-bot+netdevbpf @ 2026-01-16 3:40 UTC (permalink / raw)
To: Osose Itua
Cc: netdev, devicetree, linux-kernel, michael.hennerich,
jerome.oufella
In-Reply-To: <20260107221913.1334157-1-osose.itua@savoirfairelinux.com>
Hello:
This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Wed, 7 Jan 2026 17:16:51 -0500 you wrote:
> Changes in v3:
> - put bindings patch first in the patchset
> - update commit message of the bindings patch and improve the bindings
> description to better explain why the added property is needed (as
> suggested by Nuno Sá and Andrew Lunn)
> - rework bit clearing to use phy_clear_bits_mmd() instead of
> phy_write_mmd() since only a single bit needs to be cleared (as noted
> by Subbaraya Sundeep)
> - remove redundant phy_read_mmd() and error checking (as suggested by
> Nuno Sá)
> - remove unnecessary C++ <cerrno> include that was causing build issues
>
> [...]
Here is the summary with links:
- [v3,1/2] dt-bindings: net: adi,adin: document LP Termination property
https://git.kernel.org/netdev/net-next/c/7376ba2db168
- [v3,2/2] net: phy: adin: enable configuration of the LP Termination Register
https://git.kernel.org/netdev/net-next/c/a6733836527d
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: (subset) [PATCH v10 00/14] Peripheral Image Loader support for Qualcomm SoCs running Linux host at EL2
From: Bjorn Andersson @ 2026-01-16 3:29 UTC (permalink / raw)
To: Mathieu Poirier, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Konrad Dybcio, Mukesh Ojha
Cc: linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Bryan O'Donoghue, Konrad Dybcio
In-Reply-To: <20260105-kvmrprocv10-v10-0-022e96815380@oss.qualcomm.com>
On Mon, 05 Jan 2026 18:52:48 +0530, Mukesh Ojha wrote:
> In May 2025, we discussed the challenges at Linaro Connect 2025 [1]
> related to Secure PAS remoteproc enablement when Linux is running at EL2
> for Qualcomm SoCs.
>
> [1] https://resources.linaro.org/en/resource/sF8jXifdb9V1mUefdbfafa
>
> Below, is the summary of the discussion.
>
> [...]
Applied, thanks!
Not sure why b4 doesn't notice that I picked up the other 13 patches as well.
[14/14] arm64: dts: qcom: Add EL2 overlay for Lemans
commit: d27267558fd25acb07d7ff28a7ff44eacf799eaf
That said, overall, this adds another 10 DTB validation warnings, because the
PMU and Bluetooth nodes are lacking supplies. I applied this, as it's
"unrelated", but please have the team prioritize fixing this!
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: display: panel: Fork Waveshare panels into separate document
From: Rob Herring @ 2026-01-16 3:26 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Conor Dooley, David Airlie, Geert Uytterhoeven,
Jessica Zhang, Krzysztof Kozlowski, Maarten Lankhorst,
Magnus Damm, Maxime Ripard, Neil Armstrong, Sam Ravnborg,
Simona Vetter, Thierry Reding, Thomas Zimmermann, devicetree,
dri-devel, linux-kernel, linux-renesas-soc
In-Reply-To: <85ff0eb2-d942-4f85-8f1d-c5982bd31bec@mailbox.org>
On Thu, Jan 15, 2026 at 1:20 PM Marek Vasut <marek.vasut@mailbox.org> wrote:
>
> On 1/15/26 6:40 PM, Rob Herring wrote:
> > On Tue, Jan 13, 2026 at 01:05:30AM +0100, Marek Vasut wrote:
> >> Move the Waveshare panels description into separate document, so they
> >> can be properly described with compatible = "waveshare,...", "panel-dpi"
> >> and attached to "waveshare,dsi2dpi" bridge.
> >
> > But why do we need "panel-dpi"? Adding that requires changing a DT.
> > Can't you make the kernel handle these compatible strings as a
> > "panel-dpi" without the compatible?
> I can, but wouldn't we then miss the more specific compatible strings in
> the DT ?
>
> compatible = "waveshare,13.3inch-panel", "panel-dpi";
> ^^^^^^^^^^^^^^^^^^^^^^^^^^
> this ... would be removed. Do we want that ?
No, drop "panel-dpi". Or really, don't add it.
>
> The other option would be to add the timings into panel-simple driver,
> then we wouldn't have to change the bindings at all. Maybe that would be
> preferable ?
Why can't the "panel-dpi" driver match to"waveshare,13.3inch-panel"?
Rob
^ permalink raw reply
* Re: [PATCH] of: guard pointers to key OF nodes with an #ifdef
From: Rob Herring @ 2026-01-16 3:21 UTC (permalink / raw)
To: Bartosz Golaszewski; +Cc: devicetree, linux-kernel, Saravana Kannan
In-Reply-To: <176850847300.1117426.16555405652845405929.robh@kernel.org>
On Thu, Jan 15, 2026 at 2:21 PM Rob Herring (Arm) <robh@kernel.org> wrote:
>
>
> On Thu, 15 Jan 2026 10:18:39 +0100, Bartosz Golaszewski wrote:
> > We declare the pointers to some key OF-nodes unconditionally in
> > linux/of.h but only export them with CONFIG_OF=y. If anyone uses them in
> > code built without devicetree support enabled, the problem will only come
> > to light at link-time. Add an #ifdef guard to catch it at compile-time.
> >
> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> > ---
> > include/linux/of.h | 2 ++
> > 1 file changed, 2 insertions(+)
> >
>
> Applied, thanks!
Err, and dropped.
BTW, my ideal fix for this is to eliminate any users of these variables.
Rob
^ permalink raw reply
* Re: [PATCH v3 net-next 05/10] phy: add phy_get_rx_polarity() and phy_get_tx_polarity()
From: Jakub Kicinski @ 2026-01-16 3:19 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Paolo Abeni, Bjørn Mork, netdev, devicetree, linux-phy,
linux-kernel, linux-arm-kernel, linux-mediatek, Daniel Golle,
Horatiu Vultur, Andrew Lunn, Heiner Kallweit, Russell King,
David S. Miller, Eric Dumazet, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Matthias Brugger,
AngeloGioacchino Del Regno, Eric Woudstra, Marek Behún,
Lee Jones, Patrice Chotard, Vinod Koul
In-Reply-To: <20260115093928.hdqlxkt6bd5w4xud@skbuf>
On Thu, 15 Jan 2026 11:39:28 +0200 Vladimir Oltean wrote:
> > > Could you please share a stable branch/tag, so that we can pull patches
> > > 1-5 into the net-next tree from there?
> >
> > Vladimir, could you please re-post patches 1-5 after that Vinod shares
> > the above? So that we don't keep in PW the dangling (current) series.
> >
> Vinod did share the PR:
> https://lore.kernel.org/netdev/aWeXvFcGNK5T6As9@vaman/
IIUC Paolo did not pull Vinod's PR, so pulled now, you can repost.
^ permalink raw reply
* Re: [PATCH 1/8] dt-bindings: soc: tenstorrent: Add tenstorrent,atlantis-syscon
From: Rob Herring (Arm) @ 2026-01-16 3:18 UTC (permalink / raw)
To: Anirudh Srinivasan
Cc: Michael Turquette, mpe, linux-clk, Philipp Zabel, mpe,
linux-riscv, devicetree, Krzysztof Kozlowski, Stephen Boyd,
Drew Fustini, linux-kernel, agross, npiggin, agross, joel,
fustini, Conor Dooley, Joel Stanley
In-Reply-To: <20260115-atlantis-clocks-v1-1-7356e671f28b@oss.tenstorrent.com>
On Thu, 15 Jan 2026 17:42:00 -0600, Anirudh Srinivasan wrote:
> Document bindings for Tenstorrent Atlantis syscon that manages clocks
> and resets. This syscon block is instantiated 4 times in the SoC.
> This commit documents the clocks from the RCPU syscon block.
>
> Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
> ---
> .../tenstorrent/tenstorrent,atlantis-syscon.yaml | 58 +++++++++++++++++++
> MAINTAINERS | 2 +
> .../clock/tenstorrent,atlantis-syscon.h | 67 ++++++++++++++++++++++
> 3 files changed, 127 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.example.dtb: /example-0/system-controller@a8000000: failed to match any schema with compatible: ['tenstorrent,atlantis-sycon-rcpu']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260115-atlantis-clocks-v1-1-7356e671f28b@oss.tenstorrent.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH v3 net-next 00/10] PHY polarity inversion via generic device tree properties
From: Jakub Kicinski @ 2026-01-16 3:16 UTC (permalink / raw)
To: Vinod Koul
Cc: Vladimir Oltean, netdev, devicetree, linux-phy, linux-kernel,
linux-arm-kernel, linux-mediatek, Daniel Golle, Horatiu Vultur,
Bjørn Mork, Andrew Lunn, Heiner Kallweit, Russell King,
David S. Miller, Eric Dumazet, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Matthias Brugger, AngeloGioacchino Del Regno, Eric Woudstra,
Marek Behún, Lee Jones, Patrice Chotard
In-Reply-To: <aWeXvFcGNK5T6As9@vaman>
On Wed, 14 Jan 2026 18:48:52 +0530 Vinod Koul wrote:
> Subject: Re: [PATCH v3 net-next 00/10] PHY polarity inversion via generic device tree properties
You can submit the PR in reply to the series, but please rewrite the
subject to a typical PR format. Patchwork does not register this reply
as a submission.
^ permalink raw reply
* Re: [PATCH net-next v3 3/6] net: dsa: lantiq: allow arbitrary MII registers
From: Jakub Kicinski @ 2026-01-16 3:11 UTC (permalink / raw)
To: Daniel Golle
Cc: Hauke Mehrtens, Andrew Lunn, Vladimir Oltean, David S. Miller,
Eric Dumazet, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, netdev, devicetree, linux-kernel,
Chen Minqiang, Xinfa Deng
In-Reply-To: <c1b9bc590aa097c98816a3fda6931db9b3d080af.1768519376.git.daniel@makrotopia.org>
On Fri, 16 Jan 2026 00:07:37 +0000 Daniel Golle wrote:
> +__diag_push();
> +__diag_ignore_all("-Woverride-init",
> + "logic to initialize all and then override some is OK");
This seems quite unjustified to save at a glance 4 lines of code.
--
pw-bot: cr
^ permalink raw reply
* Re: [PATCH v3 0/2] Initial support for 100ask CanMV-K230 DshanPi
From: Jiayu Du @ 2026-01-16 3:09 UTC (permalink / raw)
To: Conor Dooley
Cc: robh, krzk+dt, pjw, palmer, aou, alex, cyy, dlemoal, devicetree,
linux-riscv, linux-kernel, gaohan
In-Reply-To: <20260115-proud-radish-c835a76d0446@spud>
On Thu, Jan 15, 2026 at 07:23:17PM +0000, Conor Dooley wrote:
> On Thu, Jan 15, 2026 at 02:07:59PM +0800, Jiayu Du wrote:
> > This series adds initial support for the 100ask CanMV-K230 DshanPi
> > board based on Canaan K230 RISC-V SoC. There is a module on this
> > development board.
> >
> > The board and module are documented, the basic board/module devicetrees
> > are added.
> >
> > This series is based on the K230 clock series[1] and the patch 3 of the
> > k230 pinctrl series[2].
> >
> > Link: https://lore.kernel.org/all/20251127-b4-k230-clk-v9-0-3aa09e17faf5@zohomail.com/ [1]
> > Link: https://lore.kernel.org/all/20240926-k230-pinctrl-v2-3-a9a36fba4b34@163.com/ [2]
>
> Right, I've grabbed patch 3 from [2] and put it on my k230-basic branch.
> Do you intend sending a new clock driver series soon? Last time I looked
> (about a month ago) you had some changes proposed about critical clocks.
> I'd like to try get this stuff merged but obviously it depends on that
> clock set. I'll happy send Stephen a PR to smooth things along if the
> drivers are ready, but it looks like you need to send another version?
>
> Cheers,
> Conor.
I'm not working with Xukai Wang, the developer of the clock series.
I merely discovered the critical clocks during the test and raised
this issue. Regarding the new version of the clock series, you need
to contact Xukai Wang.
I am currently only working on the USB and sd/mmc series of k230.
Best Regards,
Jiayu Du.
> >
> > Changes in v3:
> > - Delet the model and compatible of the root node in the dtsi file.
> > - Use clock-50000000 as the node name.
> > - Link to v2: https://lore.kernel.org/all/20260104070911.219588-1-jiayu.riscv@isrc.iscas.ac.cn/
> >
> > Changes in v2:
> > - Add a minus sign before items.
> > - Link to v1: https://lore.kernel.org/all/20251229061318.16756-1-jiayu.riscv@isrc.iscas.ac.cn/
> >
> > Jiayu Du (2):
> > dt-bindings: riscv: canaan: add 100ask K230 boards compatible strings
> > riscv: dts: canaan: Add initial dshanpi board DT files
> >
> > .../devicetree/bindings/riscv/canaan.yaml | 5 ++
> > arch/riscv/boot/dts/canaan/Makefile | 1 +
> > .../boot/dts/canaan/k230-canmv-dshanpi.dts | 82 +++++++++++++++++++
> > .../dts/canaan/k230-canmv-module-dshanpi.dtsi | 26 ++++++
> > 4 files changed, 114 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv-dshanpi.dts
> > create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv-module-dshanpi.dtsi
> >
> > --
> > 2.52.0
> >
^ permalink raw reply
* Re: [PATCH v3 08/10] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
From: Jingyi Wang @ 2026-01-16 3:05 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
linux-arm-msm, devicetree, linux-kernel, Prasad Kumpatla
In-Reply-To: <v5rprswnwedm2y7rjr3y2zfvhdh5qztvm4nnaeti2n6yqyj5yh@7wbyro7orb3q>
On 1/15/2026 3:15 PM, Dmitry Baryshkov wrote:
> On Wed, Jan 14, 2026 at 10:49:10PM -0800, Jingyi Wang wrote:
>> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>
>> Add support for audio on the Kaanapali MTP platform by introducing device
>> tree nodes for WSA8845 smart speaker amplifier for playback, DMIC
>> microphone for capture, and sound card routing. The WCD9395 codec is add
>> to supply MIC-BIAS, for enabling onboard microphone capture.
>>
>> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++++++
>> 1 file changed, 226 insertions(+)
>> @@ -684,6 +793,14 @@ &pcie_port0 {
>> reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
>> };
>>
>> +&lpass_vamacro {
>
> It is a strange alphabet, where 'p' comes before 'l'.
>
will fix
Thanks,
Jingyi
>> + pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
>> + pinctrl-names = "default";
>> +
>> + vdd-micb-supply = <&vreg_l10b_1p8>;
>> + qcom,dmic-sample-rate = <4800000>;
>> +};
>> +
>> &remoteproc_adsp {
>> firmware-name = "qcom/kaanapali/adsp.mbn",
>> "qcom/kaanapali/adsp_dtb.mbn";
>
^ permalink raw reply
* Re: [PATCH v3 05/10] arm64: dts: qcom: kaanapali: Add support for audio
From: Jingyi Wang @ 2026-01-16 3:05 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
linux-arm-msm, devicetree, linux-kernel, Prasad Kumpatla,
Konrad Dybcio
In-Reply-To: <vyvijzse5wb4bhepmo63gfljfhya3oqi52ndl3l47hgtdmch3k@yj3aj6ayrp5g>
On 1/15/2026 3:12 PM, Dmitry Baryshkov wrote:
> On Wed, Jan 14, 2026 at 10:49:07PM -0800, Jingyi Wang wrote:
>> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>
>> Introduce audio support for Kaanapali SoC by adding LPASS macro codecs,
>> TLMM pin controller and SoundWire controller with similar hardware
>> implementation to SM8750 platform. Also add GPR (Generic Pack Router) node
>> along with support for APM (Audio Process Manager) and PRM
>> (Proxy Resource Manager) audio services.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 396 ++++++++++++++++++++++++++++++++
>> 1 file changed, 396 insertions(+)
>>
>> +
>> + swr3: soundwire@6ab0000 {
>> + compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0";
>> + reg = <0 0x06ab0000 0 0x10000>;
>> + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&lpass_wsa2macro>;
>> + clock-names = "iface";
>> + label = "WSA2";
>> +
>> + pinctrl-0 = <&wsa2_swr_active>;
>> + pinctrl-names = "default";
>> +
>> + qcom,din-ports = <4>;
>> + qcom,dout-ports = <9>;
>> +
>> + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f
>> + 0x18f 0xff 0xff 0x0f 0x0f 0xff
>
> Use a single long line, please.
>
Well noted.
Thanks,
Jingyi
>> + 0x31f>;
>> + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00
>
^ permalink raw reply
* Re: [PATCH v3 04/10] arm64: dts: qcom: kaanapali: Add ADSP and CDSP for Kaanapali SoC
From: Jingyi Wang @ 2026-01-16 3:04 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
linux-arm-msm, devicetree, linux-kernel, Kumari Pallavi
In-Reply-To: <jad4p5l6beny3uojc7lyjtku2c2i2ykple4lgikb7s5kfyfg5h@o6a3uqqkduww>
On 1/15/2026 3:10 PM, Dmitry Baryshkov wrote:
> On Wed, Jan 14, 2026 at 10:49:06PM -0800, Jingyi Wang wrote:
>> Add remoteproc PAS loader for ADSP and CDSP with its SMP2P and fastrpc
>> nodes.
>>
>> Co-developed-by: Kumari Pallavi <kumari.pallavi@oss.qualcomm.com>
>> Signed-off-by: Kumari Pallavi <kumari.pallavi@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 351 ++++++++++++++++++++++++++++++++
>> 1 file changed, 351 insertions(+)
>>
>> + smp2p-modem {
>> + compatible = "qcom,smp2p";
>
> Nit: and where is the modem?
>
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>
>
>
>
modem is not enabled in this series, I will drop the smp2p-modem in next
version and send it with modem patch
Thanks,
Jingyi
^ permalink raw reply
* Re: [PATCH v2 04/14] wifi: ath10k: snoc: support powering on the device via pwrseq
From: Dmitry Baryshkov @ 2026-01-16 2:57 UTC (permalink / raw)
To: Jeff Johnson
Cc: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bartosz Golaszewski, Marcel Holtmann,
Luiz Augusto von Dentz, Jeff Johnson, Bjorn Andersson,
Konrad Dybcio, Manivannan Sadhasivam, Vinod Koul,
Balakrishna Godavarthi, Matthias Kaehlcke, linux-arm-msm,
linux-kernel, devicetree, linux-bluetooth, linux-wireless, ath10k,
linux-pm, Krzysztof Kozlowski, Bartosz Golaszewski
In-Reply-To: <6db7a42e-7f12-499b-b36e-687ec93b2e62@oss.qualcomm.com>
On Thu, Jan 15, 2026 at 03:12:19PM -0800, Jeff Johnson wrote:
> On 1/5/2026 5:01 PM, Dmitry Baryshkov wrote:
> > @@ -1023,9 +1024,15 @@ static int ath10k_hw_power_on(struct ath10k *ar)
> >
> > ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power on\n");
> >
> > + if (ar_snoc->pwrseq) {
> > + ret = pwrseq_power_on(ar_snoc->pwrseq);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > ret = regulator_bulk_enable(ar_snoc->num_vregs, ar_snoc->vregs);
> > if (ret)
> > - return ret;
> > + goto pwrseq_off;
> >
> > ret = clk_bulk_prepare_enable(ar_snoc->num_clks, ar_snoc->clks);
> > if (ret)
> > @@ -1035,18 +1042,28 @@ static int ath10k_hw_power_on(struct ath10k *ar)
> >
> > vreg_off:
> > regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
> > +pwrseq_off:
> > + pwrseq_power_off(ar_snoc->pwrseq);
>
> in this function you conditionally call pwrseq_power_on()
> but on error you unconditionally call pwrseq_power_off()
>
> in the below function you conditionally call pwrseq_power_off()
>
> so there is inconsistency.
>
> note that both pwrseq_power_on() and pwrseq_power_off() handle a NULL
> pwrseq_desc so is there any reason to not just call both both functions
> unconditionally everywhere?
Indeed, it should not be necessary. I'll send a new iteration (and also
update the copyright).
>
> > +
> > return ret;
> > }
> >
> > static int ath10k_hw_power_off(struct ath10k *ar)
> > {
> > struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
> > + int ret_seq = 0;
> > + int ret_vreg;
> >
> > ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power off\n");
> >
> > clk_bulk_disable_unprepare(ar_snoc->num_clks, ar_snoc->clks);
> >
> > - return regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
> > + ret_vreg = regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
> > +
> > + if (ar_snoc->pwrseq)
> > + ret_seq = pwrseq_power_off(ar_snoc->pwrseq);
> > +
> > + return ret_vreg ? : ret_seq;
> > }
> >
> > static void ath10k_snoc_wlan_disable(struct ath10k *ar)
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH v2 3/3] MAINTAINERS: Add ASPEED USB3 PHY driver
From: Ryan Chen @ 2026-01-16 2:53 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery, Philipp Zabel
Cc: linux-phy, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, Ryan Chen
In-Reply-To: <20260116-upstream_usb3phy-v2-0-0b0c9f3eb6f4@aspeedtech.com>
Add maintainer entry for ASPEED USB3 PHY driver.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b11839cba9d..ad1d12f346f2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3894,6 +3894,14 @@ S: Maintained
F: Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml
F: drivers/usb/gadget/udc/aspeed_udc.c
+ASPEED USB3 PHY DRIVER
+M: Ryan Chen <ryan_chen@aspeedtech.com>
+L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
+L: linux-phy@lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/phy/aspeed,ast2700-usb3-phy.yaml
+F: drivers/phy/aspeed/phy-aspeed-usb3.c
+
ASPEED VIDEO ENGINE DRIVER
M: Eddie James <eajames@linux.ibm.com>
L: linux-media@vger.kernel.org
--
2.34.1
^ permalink raw reply related
* [PATCH v2 2/3] phy: add AST2700 usb3.2 phy driver
From: Ryan Chen @ 2026-01-16 2:53 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery, Philipp Zabel
Cc: linux-phy, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, Ryan Chen
In-Reply-To: <20260116-upstream_usb3phy-v2-0-0b0c9f3eb6f4@aspeedtech.com>
Add AST2700 USB3.2 PHY driver support.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
drivers/phy/aspeed/Kconfig | 12 ++
drivers/phy/aspeed/Makefile | 2 +
drivers/phy/aspeed/phy-aspeed-usb3.c | 236 +++++++++++++++++++++++++++++++++++
3 files changed, 250 insertions(+)
diff --git a/drivers/phy/aspeed/Kconfig b/drivers/phy/aspeed/Kconfig
new file mode 100644
index 000000000000..72b4fc17a85e
--- /dev/null
+++ b/drivers/phy/aspeed/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+#
+# PHY drivers for ASPEED
+#
+
+config PHY_ASPEED_USB3
+ tristate "ASPEED USB3 PHY driver"
+ select GENERIC_PHY
+ depends on (ARCH_ASPEED || COMPILE_TEST)
+ help
+ Enable driver support for Aspeed AST2700 USB3 PHY.
diff --git a/drivers/phy/aspeed/Makefile b/drivers/phy/aspeed/Makefile
new file mode 100644
index 000000000000..20b5ac7b7e64
--- /dev/null
+++ b/drivers/phy/aspeed/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_ASPEED_USB3_PHY) += phy-aspeed-usb3.o
diff --git a/drivers/phy/aspeed/phy-aspeed-usb3.c b/drivers/phy/aspeed/phy-aspeed-usb3.c
new file mode 100644
index 000000000000..872d2163fcf5
--- /dev/null
+++ b/drivers/phy/aspeed/phy-aspeed-usb3.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 Aspeed Technology Inc.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#define PHY3S00 0x00
+#define PHY3S00_INIT_DONE BIT(15)
+#define PHY3S00_SRAM_BYPASS BIT(7)
+#define PHY3S00_SRAM_EXT_LOAD BIT(6)
+#define PHY3S04 0x04
+#define PHY3C00 0x08
+#define PHY3C04 0x0C
+#define PHY3P00 0x10
+#define PHY3P00_RX_ADAPT_AFE_EN_G1 BIT(0)
+#define PHY3P00_RX_ADAPT_AFE_EN_G2 BIT(1)
+#define PHY3P00_RX_ADAPT_DFE_EN_G1 BIT(2)
+#define PHY3P00_RX_ADAPT_DFE_EN_G2 BIT(3)
+#define PHY3P00_RX_CDR_VCO_LOWFREQ_G1 BIT(4)
+#define PHY3P00_RX_CDR_VCO_LOWFREQ_G2 BIT(5)
+#define PHY3P00_RX_EQ_AFE_GAIN_G1 GENMASK(9, 6)
+#define PHY3P00_RX_EQ_AFE_GAIN_G2 GENMASK(13, 10)
+#define PHY3P00_RX_EQ_ATT_LVL_G1 GENMASK(16, 14)
+#define PHY3P00_RX_EQ_ATT_LVL_G2 GENMASK(19, 17)
+#define PHY3P00_RX_EQ_CTLE_BOOST_G1 GENMASK(24, 20)
+#define PHY3P00_RX_EQ_CTLE_BOOST_G2 GENMASK(29, 25)
+#define PHY3P00_RX_EQ_DELTA_IQ_G1_LO GENMASK(31, 30)
+
+#define PHY3P04 0x14
+#define PHY3P04_RX_EQ_DELTA_IQ_G1_HI GENMASK(1, 0)
+#define PHY3P04_RX_EQ_DELTA_IQ_G2 GENMASK(5, 2)
+#define PHY3P04_RX_EQ_DFE_TAP1_G1 GENMASK(13, 6)
+#define PHY3P04_RX_EQ_DFE_TAP1_G2 GENMASK(21, 14)
+#define PHY3P04_RX_LOS_LFPS_EN BIT(22)
+#define PHY3P04_RX_LOS_THRESHOLD GENMASK(25, 23)
+#define PHY3P04_RX_TERM_CTRL GENMASK(28, 26)
+#define PHY3P04_TX_EQ_MAIN_G1_LO GENMASK(31, 29)
+
+#define PHY3P08 0x18
+#define PHY3P08_TX_EQ_MAIN_G1_HI GENMASK(1, 0)
+#define PHY3P08_TX_EQ_MAIN_G2 GENMASK(6, 2)
+#define PHY3P08_TX_EQ_OVRD BIT(7)
+#define PHY3P08_TX_EQ_POST_G1 GENMASK(12, 9)
+#define PHY3P08_TX_EQ_POST_G2 GENMASK(16, 13)
+#define PHY3P08_TX_EQ_PRE_G1 GENMASK(20, 17)
+#define PHY3P08_TX_EQ_PRE_G2 GENMASK(24, 21)
+#define PHY3P08_TX_IBOOST_LVL GENMASK(28, 25)
+#define PHY3P08_TX_TERM_CTRL GENMASK(31, 29)
+
+#define PHY3P0C 0x1C
+#define PHY3P0C_TX_VBOOST_EN BIT(0)
+
+#define PHY3CMD 0x40
+
+#define PHY3P_RX_EQ_CTLE_BOOST_G1_DEFAULT 0x7
+#define PHY3P_RX_EQ_CTLE_BOOST_G2_DEFAULT 0x7
+#define PHY3P_RX_EQ_DELTA_IQ_G1_DEFAULT 0x3
+#define PHY3P_RX_EQ_DELTA_IQ_G2_DEFAULT 0x5
+#define PHY3P_RX_LOS_THRESHOLD_DEFAULT 0x3
+#define PHY3P_RX_TERM_CTRL_DEFAULT 0x2
+#define PHY3P_TX_EQ_MAIN_G1_DEFAULT 0xa
+#define PHY3P_TX_EQ_MAIN_G2_DEFAULT 0x9
+#define PHY3P_TX_EQ_POST_G1_DEFAULT 0x4
+#define PHY3P_TX_EQ_POST_G2_DEFAULT 0x3
+#define PHY3P_TX_EQ_PRE_G2_DEFAULT 0x2
+#define PHY3P_TX_IBOOST_LVL_DEFAULT 0xf
+#define PHY3P_TX_TERM_CTRL_DEFAULT 0x2
+
+#define PHY3P00_DEFAULT ( \
+ PHY3P00_RX_ADAPT_AFE_EN_G1 | \
+ PHY3P00_RX_ADAPT_AFE_EN_G2 | \
+ PHY3P00_RX_ADAPT_DFE_EN_G1 | \
+ PHY3P00_RX_ADAPT_DFE_EN_G2 | \
+ FIELD_PREP(PHY3P00_RX_EQ_CTLE_BOOST_G1, PHY3P_RX_EQ_CTLE_BOOST_G1_DEFAULT) | \
+ FIELD_PREP(PHY3P00_RX_EQ_CTLE_BOOST_G2, PHY3P_RX_EQ_CTLE_BOOST_G2_DEFAULT) | \
+ FIELD_PREP(PHY3P00_RX_EQ_DELTA_IQ_G1_LO, \
+ PHY3P_RX_EQ_DELTA_IQ_G1_DEFAULT & 0x3) \
+)
+
+#define PHY3P04_DEFAULT ( \
+ FIELD_PREP(PHY3P04_RX_EQ_DELTA_IQ_G1_HI, \
+ PHY3P_RX_EQ_DELTA_IQ_G1_DEFAULT >> 2) | \
+ FIELD_PREP(PHY3P04_RX_EQ_DELTA_IQ_G2, PHY3P_RX_EQ_DELTA_IQ_G2_DEFAULT) | \
+ PHY3P04_RX_LOS_LFPS_EN | \
+ FIELD_PREP(PHY3P04_RX_LOS_THRESHOLD, PHY3P_RX_LOS_THRESHOLD_DEFAULT) | \
+ FIELD_PREP(PHY3P04_RX_TERM_CTRL, PHY3P_RX_TERM_CTRL_DEFAULT) | \
+ FIELD_PREP(PHY3P04_TX_EQ_MAIN_G1_LO, \
+ PHY3P_TX_EQ_MAIN_G1_DEFAULT & 0x7) \
+)
+
+#define PHY3P08_DEFAULT ( \
+ FIELD_PREP(PHY3P08_TX_EQ_MAIN_G1_HI, PHY3P_TX_EQ_MAIN_G1_DEFAULT >> 3) | \
+ FIELD_PREP(PHY3P08_TX_EQ_MAIN_G2, PHY3P_TX_EQ_MAIN_G2_DEFAULT) | \
+ FIELD_PREP(PHY3P08_TX_EQ_POST_G1, PHY3P_TX_EQ_POST_G1_DEFAULT) | \
+ FIELD_PREP(PHY3P08_TX_EQ_POST_G2, PHY3P_TX_EQ_POST_G2_DEFAULT) | \
+ FIELD_PREP(PHY3P08_TX_EQ_PRE_G2, PHY3P_TX_EQ_PRE_G2_DEFAULT) | \
+ FIELD_PREP(PHY3P08_TX_IBOOST_LVL, PHY3P_TX_IBOOST_LVL_DEFAULT) | \
+ FIELD_PREP(PHY3P08_TX_TERM_CTRL, PHY3P_TX_TERM_CTRL_DEFAULT) \
+)
+
+#define PHY3P0C_DEFAULT \
+ PHY3P0C_TX_VBOOST_EN
+
+struct aspeed_usb3_phy {
+ void __iomem *regs;
+ struct reset_control *rst;
+ struct device *dev;
+ struct clk *clk;
+};
+
+static int aspeed_usb3_phy_init(struct phy *phy)
+{
+ struct aspeed_usb3_phy *aspeed_phy = phy_get_drvdata(phy);
+ u32 val;
+ int ret;
+
+ ret = clk_prepare_enable(aspeed_phy->clk);
+ if (ret) {
+ dev_err(aspeed_phy->dev, "Failed to enable clock %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_control_deassert(aspeed_phy->rst);
+ if (ret) {
+ clk_disable_unprepare(aspeed_phy->clk);
+ return ret;
+ }
+
+ /* Wait for USB3 PHY internal SRAM initialization done */
+ ret = readl_poll_timeout(aspeed_phy->regs + PHY3S00, val,
+ val & PHY3S00_INIT_DONE,
+ USEC_PER_MSEC, 10 * USEC_PER_MSEC);
+ if (ret) {
+ dev_err(aspeed_phy->dev, "SRAM init timeout\n");
+ goto err_assert_reset;
+ }
+
+ val = readl(aspeed_phy->regs + PHY3S00);
+ val |= PHY3S00_SRAM_BYPASS;
+ writel(val, aspeed_phy->regs + PHY3S00);
+
+ /* Set protocol1_ext signals as default PHY3 settings based on SNPS documents.
+ * Including PCFGI[54]: protocol1_ext_rx_los_lfps_en for better compatibility
+ */
+ writel(PHY3P00_DEFAULT, aspeed_phy->regs + PHY3P00);
+ writel(PHY3P04_DEFAULT, aspeed_phy->regs + PHY3P04);
+ writel(PHY3P08_DEFAULT, aspeed_phy->regs + PHY3P08);
+ writel(PHY3P0C_DEFAULT, aspeed_phy->regs + PHY3P0C);
+
+ return 0;
+
+err_assert_reset:
+ reset_control_assert(aspeed_phy->rst);
+ clk_disable_unprepare(aspeed_phy->clk);
+ return ret;
+}
+
+static int aspeed_usb3_phy_exit(struct phy *phy)
+{
+ struct aspeed_usb3_phy *aspeed_phy = phy_get_drvdata(phy);
+
+ reset_control_assert(aspeed_phy->rst);
+ clk_disable_unprepare(aspeed_phy->clk);
+
+ return 0;
+}
+
+static const struct phy_ops aspeed_usb3_phy_ops = {
+ .init = aspeed_usb3_phy_init,
+ .exit = aspeed_usb3_phy_exit,
+ .owner = THIS_MODULE,
+};
+
+static int aspeed_usb3_phy_probe(struct platform_device *pdev)
+{
+ struct aspeed_usb3_phy *aspeed_phy;
+ struct phy_provider *phy_provider;
+ struct device *dev = &pdev->dev;
+ struct phy *phy;
+
+ aspeed_phy = devm_kzalloc(dev, sizeof(*aspeed_phy), GFP_KERNEL);
+ if (!aspeed_phy)
+ return -ENOMEM;
+
+ aspeed_phy->dev = dev;
+
+ aspeed_phy->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(aspeed_phy->clk))
+ return PTR_ERR(aspeed_phy->clk);
+
+ aspeed_phy->rst = devm_reset_control_get_exclusive(dev, NULL);
+ if (IS_ERR(aspeed_phy->rst))
+ return PTR_ERR(aspeed_phy->rst);
+
+ aspeed_phy->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(aspeed_phy->regs))
+ return PTR_ERR(aspeed_phy->regs);
+
+ phy = devm_phy_create(dev, NULL, &aspeed_usb3_phy_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ phy_set_drvdata(phy, aspeed_phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id aspeed_usb3_phy_match_table[] = {
+ {
+ .compatible = "aspeed,ast2700-usb3-phy",
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, aspeed_usb3_phy_match_table);
+
+static struct platform_driver aspeed_usb3_phy_driver = {
+ .probe = aspeed_usb3_phy_probe,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = aspeed_usb3_phy_match_table,
+ },
+};
+module_platform_driver(aspeed_usb3_phy_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ASPEED USB3.0 PHY Driver");
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/3] dt-bindings: phy: aspeed: Document AST2700 USB3.0 PHY
From: Ryan Chen @ 2026-01-16 2:53 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery, Philipp Zabel
Cc: linux-phy, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, Ryan Chen, Krzysztof Kozlowski
In-Reply-To: <20260116-upstream_usb3phy-v2-0-0b0c9f3eb6f4@aspeedtech.com>
Document AST2700 USB3.2 PHY. This IP is connected between
USB3 controller and PHY module.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
.../bindings/phy/aspeed,ast2700-usb3-phy.yaml | 48 ++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/aspeed,ast2700-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/aspeed,ast2700-usb3-phy.yaml
new file mode 100644
index 000000000000..b83037aa0438
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/aspeed,ast2700-usb3-phy.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/aspeed,ast2700-usb3-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2700 USB 3.2 PHY
+
+maintainers:
+ - Ryan Chen <ryan_chen@aspeedtech.com>
+
+properties:
+ compatible:
+ const: aspeed,ast2700-usb3-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#phy-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/aspeed,ast2700-scu.h>
+ #include <dt-bindings/reset/aspeed,ast2700-scu.h>
+
+ usb-phy@12010000 {
+ compatible = "aspeed,ast2700-usb3-phy";
+ reg = <0x12010000 0xc0>;
+ clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>;
+ resets = <&syscon0 SCU0_RESET_PORTA_PHY3>;
+ #phy-cells = <0>;
+ };
--
2.34.1
^ permalink raw reply related
* [PATCH v2 0/3] Add AST2700 USB3.2 PHY driver
From: Ryan Chen @ 2026-01-16 2:53 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery, Philipp Zabel
Cc: linux-phy, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, Ryan Chen, Krzysztof Kozlowski
Add AST2700 USB3.2 PHY support.
- Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
Changes in v2:
- aspeed,ast2700-usb3-phy.yaml
- Drop clocks, resets descripton.
- Kconfig
- add COMPILE_TEST, remove default n
- Link to v1: https://lore.kernel.org/r/20260114-upstream_usb3phy-v1-0-2e59590be2d7@aspeedtech.com
---
Ryan Chen (3):
dt-bindings: phy: aspeed: Document AST2700 USB3.0 PHY
phy: add AST2700 usb3.2 phy driver
MAINTAINERS: Add ASPEED USB3 PHY driver
.../bindings/phy/aspeed,ast2700-usb3-phy.yaml | 48 +++++
MAINTAINERS | 8 +
drivers/phy/aspeed/Kconfig | 12 ++
drivers/phy/aspeed/Makefile | 2 +
drivers/phy/aspeed/phy-aspeed-usb3.c | 236 +++++++++++++++++++++
5 files changed, 306 insertions(+)
---
base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
change-id: 20260112-upstream_usb3phy-7116f8dfe779
Best regards,
--
Ryan Chen <ryan_chen@aspeedtech.com>
^ permalink raw reply
* [PATCH v1] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable SDIO interface
From: Nick Xie @ 2026-01-16 2:39 UTC (permalink / raw)
To: neil.armstrong, khilman, jbrunet, martin.blumenstingl, devicetree,
linux-kernel, linux-arm-kernel, linux-amlogic
Cc: krzk+dt, robh, conor+dt, xieqinick, Nick Xie
Enable the SDIO controller interface connected to the on-board
AP6256 WiFi/BT module.
Signed-off-by: Nick Xie <nick@khadas.com>
---
.../amlogic/meson-s4-s905y4-khadas-vim1s.dts | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
index 4a66c1bec965e..74ef02c713207 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
@@ -220,6 +220,35 @@ &sd {
vqmmc-supply = <&vddio_sd>;
};
+&sdio {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ max-frequency = <50000000>;
+ non-removable;
+ disable-wp;
+
+ amlogic,dram-access-quirk;
+
+ no-sd;
+ no-mmc;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_ao1v8>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
&spicc0 {
status = "okay";
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply related
* [PATCH v1] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable eMMC storage
From: Nick Xie @ 2026-01-16 2:36 UTC (permalink / raw)
To: neil.armstrong, khilman, jbrunet, martin.blumenstingl, devicetree,
linux-kernel, linux-arm-kernel, linux-amlogic
Cc: krzk+dt, robh, conor+dt, xieqinick, Nick Xie
Enable the on-board eMMC storage for Khadas VIM1S.
The VIM1S features a 16GB eMMC 5.1 module. This patch adds the
necessary regulators and the eMMC controller node.
Signed-off-by: Nick Xie <nick@khadas.com>
---
.../amlogic/meson-s4-s905y4-khadas-vim1s.dts | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
index 79ffc703a2e99..4a66c1bec965e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
@@ -38,6 +38,11 @@ secmon_reserved: secmon@5000000 {
};
};
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio GPIOB_9 GPIO_ACTIVE_LOW>;
+ };
+
sdio_32k: sdio-32k {
compatible = "pwm-clock";
#clock-cells = <0>;
@@ -80,6 +85,24 @@ vddio_sd: regulator-vddio-sd {
3300000 0>;
};
+ vddao_3v3: regulator-vddao-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&main_5v>;
+ regulator-always-on;
+ };
+
+ vddio_ao1v8: regulator-vddio-ao1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
/* SY8120B1ABC DC/DC Regulator. */
vddcpu: regulator-vddcpu {
compatible = "pwm-regulator";
@@ -136,6 +159,25 @@ vddcpu: regulator-vddcpu {
};
};
+&emmc {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_ao1v8>;
+};
+
ðmac {
status = "okay";
phy-handle = <&internal_ephy>;
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v5 0/3] spmi-pmic-arb: Add support for PMIC arbiter v8 for Glymur and Kaanapali
From: Stephen Boyd @ 2026-01-16 2:20 UTC (permalink / raw)
To: Conor Dooley, David Collins, Jishnu Prakash, Krzysztof Kozlowski,
Rob Herring, konrad.dybcio
Cc: linux-arm-msm, linux-kernel, devicetree, Jishnu Prakash, aiqun.yu,
kamal.wadhwa, Pankaj Patil, Jingyi Wang
In-Reply-To: <20251126-pmic_arb_v8-v5-0-4dd8dc5dc5a1@oss.qualcomm.com>
Quoting Jishnu Prakash (2025-11-25 23:12:52)
> This patch series updates the SPMI dt-bindings and driver to add
> support for PMIC arbiter v8, targeting Qualcomm SoCs Glymur and
> Kaanapali.
>
> SPMI PMIC Arbiter version 8 builds upon version 7 with support for
> up to four SPMI buses. To achieve this, the register map was
> slightly rearranged.
>
> Device tree changes are not included in this series and will be
> posted separately.
>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
> ---
Applied to spmi-next
^ permalink raw reply
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