* Re: [PATCH v9 2/9] lib: vsprintf: export simple_strntoull() in a safe prototype
From: Andy Shevchenko @ 2026-03-27 9:17 UTC (permalink / raw)
To: Petr Mladek
Cc: rodrigo.alencar, linux-kernel, linux-iio, devicetree, linux-doc,
Jonathan Cameron, David Lechner, Andy Shevchenko,
Lars-Peter Clausen, Michael Hennerich, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jonathan Corbet, Andrew Morton,
Steven Rostedt, Rasmus Villemoes, Sergey Senozhatsky, Shuah Khan
In-Reply-To: <acZDneLrIPOmU5ci@pathway.suse.cz>
On Fri, Mar 27, 2026 at 09:45:17AM +0100, Petr Mladek wrote:
> On Fri 2026-03-20 16:27:27, Rodrigo Alencar via B4 Relay wrote:
...
> > +extern ssize_t __must_check simple_strntoull(const char *startp, const char **endp,
> > + unsigned int base, size_t max_chars,
> > + unsigned long long *res);
>
> Sigh, naming is hard. I personally find it a bit confusing that the
> name is too similar to the unsafe API.
>
> IMHO, the semantic of the new API is closer to kstrtoull().
> It just limits the size, so I would call it kstrntoull().
It's not. kstrto*() quite strict about the input, this one is actually relaxed
variant, so I wouldn't mix these two groups.
> Also I would use int as the return parameter, see below.
...
TBH, I am skeptical about this approach. My main objection is max_chars
parameter. If we want to limit the input strictly to the given number of
characters, we have to copy the string and then just use kstrto*() in a normal
way. The whole idea of that parameter is to be able to parse the fractional
part of the float number as 'iiiii.fffff', where 'i' is for integer part, and
'f' for the fractional. Since we have *endp, we may simply check that.
In case if we want to parse only, say, 6 digits and input is longer there are
a few options (in my personal preferences, the first is the better):
- consider the input invalid
- parse it as is up to the maximum and then do ceil() or floor() on top of that
- copy only necessary amount of the (sub)string and parse that.
The problem with precision is that we need to also consider floor() or ceil()
and I don't think this should be burden of the library as it's individual
preference of each of the callers (users). At least for the starter, we will
see if it's only one approach is used, we may incorporate it into the library
code.
The easiest way out is to just consider the input invalid if it overflows the
given type (s32 or s64).
But we need to have an agreement what will be the representation of the
fixed-width float numbers in the kernel? Currently IIO uses
struct float // name is crafted for simplicity
{
int integer;
int fraction;
}
This parser wants AFAIU to have at the end of the day something like
struct float
{
s64 integer;
s64 fraction;
}
but also wants to have the fraction part be limited in some cases to s32
or so:
struct float
{
s64 integer;
s32 fraction; // precision may be lost if input is longer
}
Maybe we want to have kstrtof32() and kstrtof64() for these two cases?
With that we will always consider the fraction part as 32- or 64-bit,
imply floor() on the fraction for the sake of simplicity and require
it to be NUL-terminated with possible trailing '\n'.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH 5/7] arm64: dts: qcom: sm6125-xiaomi-ginkgo: Add IR transmitter
From: Konrad Dybcio @ 2026-03-27 9:19 UTC (permalink / raw)
To: Biswapriyo Nath
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Pavel Machek, Sean Young,
Michael Turquette, Stephen Boyd, Martin Botka, linux-arm-msm,
devicetree, linux-kernel, linux-leds, linux-clk,
~postmarketos/upstreaming, phone-devel
In-Reply-To: <20260326184126.9280-1-nathbappai@gmail.com>
On 3/26/26 7:41 PM, Biswapriyo Nath wrote:
> On Thu, 26 Mar 2026 10:29:49 +0100 Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
>
>> On 3/25/26 7:07 PM, Biswapriyo Nath wrote:
>>> The IR transmitting LED is connected to SPI8 controller.
>>>
>>> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
>>> ---
>>
>> [...]
>>
>>> +&spi8 {
>>> + status = "okay";
>>> +
>>> + irled@1 {
>>> + compatible = "ir-spi-led";
>>> + reg = <1>;
>>> +
>>> + duty-cycle = /bits/ 8 <30>;
>>> + spi-max-frequency = <1000000>;
>>
>> I see the binding allows a power-supply handle - do you need one?
>>
>> Konrad
>>
>
> I have tested the IR transmitter with my TV and set-top box both.
> power-supply is not required and not mentioned in Android devicetree.
Thanks
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v11 2/4] crypto: spacc - Add SPAcc ahash support
From: Herbert Xu @ 2026-03-27 9:20 UTC (permalink / raw)
To: Pavitrakumar Managutte
Cc: linux-crypto, linux-kernel, devicetree, robh, conor+dt,
Ruud.Derwig, manjunath.hadli, adityak, navami.telsang, bhoomikak
In-Reply-To: <20260318071808.817074-3-pavitrakumarm@vayavyalabs.com>
On Wed, Mar 18, 2026 at 12:48:06PM +0530, Pavitrakumar Managutte wrote:
>
> + switch (salg->mode->id) {
> + case CRYPTO_MODE_HMAC_SHA224:
> + rc = do_shash(salg->dev, "sha224", tctx->ipad, key,
> + keylen);
> + break;
Since you're doing a giant switch statement anyway, please convert
this to use lib/crypto instead of shash.
Thanks,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* [PATCH v3] ASoC: dt-bindings: hisilicon: Convert hi6210 I2S to dt-schema
From: Chaitanya Sabnis @ 2026-03-27 9:21 UTC (permalink / raw)
To: lgirdwood, broonie, robh, krzk+dt, conor+dt
Cc: john.stultz, linux-sound, devicetree, linux-kernel,
Chaitanya Sabnis
Convert the Hisilicon hi6210 I2S controller hardware binding from
legacy plain text to modern YAML dt-schema format.
During the conversion, the order of the dma-names properties in the
example was corrected to "tx", "rx" to match the official property
description, resolving a contradiction in the original text binding.
Signed-off-by: Chaitanya Sabnis <chaitanya.msabnis@gmail.com>
---
.../bindings/sound/hisilicon,hi6210-i2s.txt | 42 ----------
.../bindings/sound/hisilicon,hi6210-i2s.yaml | 80 +++++++++++++++++++
2 files changed, 80 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.txt
create mode 100644 Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.yaml
diff --git a/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.txt b/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.txt
deleted file mode 100644
index 7a296784eb37..000000000000
--- a/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-* Hisilicon 6210 i2s controller
-
-Required properties:
-
-- compatible: should be one of the following:
- - "hisilicon,hi6210-i2s"
-- reg: physical base address of the i2s controller unit and length of
- memory mapped region.
-- interrupts: should contain the i2s interrupt.
-- clocks: a list of phandle + clock-specifier pairs, one for each entry
- in clock-names.
-- clock-names: should contain following:
- - "dacodec"
- - "i2s-base"
-- dmas: DMA specifiers for tx dma. See the DMA client binding,
- Documentation/devicetree/bindings/dma/dma.txt
-- dma-names: should be "tx" and "rx"
-- hisilicon,sysctrl-syscon: phandle to sysctrl syscon
-- #sound-dai-cells: Should be set to 1 (for multi-dai)
- - The dai cell indexes reference the following interfaces:
- 0: S2 interface
- (Currently that is the only one available, but more may be
- supported in the future)
-
-Example for the hi6210 i2s controller:
-
-i2s0: i2s@f7118000{
- compatible = "hisilicon,hi6210-i2s";
- reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
- clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
- <&sys_ctrl HI6220_BBPPLL0_DIV>;
- clock-names = "dacodec", "i2s-base";
- dmas = <&dma0 15 &dma0 14>;
- dma-names = "rx", "tx";
- hisilicon,sysctrl-syscon = <&sys_ctrl>;
- #sound-dai-cells = <1>;
-};
-
-Then when referencing the i2s controller:
- sound-dai = <&i2s0 0>; /* index 0 => S2 interface */
-
diff --git a/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.yaml b/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.yaml
new file mode 100644
index 000000000000..5171f984630b
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/hisilicon,hi6210-i2s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon hi6210 I2S controller
+
+maintainers:
+ - John Stultz <john.stultz@linaro.org>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: hisilicon,hi6210-i2s
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: dacodec
+ - const: i2s-base
+
+ dmas:
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+ hisilicon,sysctrl-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to sysctrl syscon
+
+ "#sound-dai-cells":
+ const: 1
+ description: |
+ The dai cell indexes reference the following interfaces:
+ 0: S2 interface
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+ - hisilicon,sysctrl-syscon
+ - "#sound-dai-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/hi6220-clock.h>
+
+ i2s@f7118000 {
+ compatible = "hisilicon,hi6210-i2s";
+ reg = <0xf7118000 0x8000>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
+ <&sys_ctrl HI6220_BBPPLL0_DIV>;
+ clock-names = "dacodec", "i2s-base";
+ dmas = <&dma0 14>, <&dma0 15>;
+ dma-names = "tx", "rx";
+ hisilicon,sysctrl-syscon = <&sys_ctrl>;
+ #sound-dai-cells = <1>;
+ };
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v9 2/9] lib: vsprintf: export simple_strntoull() in a safe prototype
From: Rodrigo Alencar @ 2026-03-27 9:24 UTC (permalink / raw)
To: Petr Mladek, rodrigo.alencar
Cc: linux-kernel, linux-iio, devicetree, linux-doc, Jonathan Cameron,
David Lechner, Andy Shevchenko, Lars-Peter Clausen,
Michael Hennerich, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Corbet, Andrew Morton, Steven Rostedt, Andy Shevchenko,
Rasmus Villemoes, Sergey Senozhatsky, Shuah Khan
In-Reply-To: <acZDneLrIPOmU5ci@pathway.suse.cz>
On 26/03/27 09:45AM, Petr Mladek wrote:
> On Fri 2026-03-20 16:27:27, Rodrigo Alencar via B4 Relay wrote:
> > From: Rodrigo Alencar <rodrigo.alencar@analog.com>
> >
> > Expose simple_strntoull(), by addressing its FIXME, i.e. its prototype is
> > slightly changed so that -ERANGE or -EINVAL can be evaluated by the user.
> > Flow of the function is not changed and error value is returned in the
> > end. Unsafe internal wrapper is created to reduce amount of changes.
> >
> > --- a/include/linux/kstrtox.h
> > +++ b/include/linux/kstrtox.h
> > @@ -148,4 +148,8 @@ extern long simple_strtol(const char *,char **,unsigned int);
> > extern unsigned long long simple_strtoull(const char *,char **,unsigned int);
> > extern long long simple_strtoll(const char *,char **,unsigned int);
> >
> > +extern ssize_t __must_check simple_strntoull(const char *startp, const char **endp,
> > + unsigned int base, size_t max_chars,
> > + unsigned long long *res);
>
> Sigh, naming is hard. I personally find it a bit confusing that the
> name is too similar to the unsafe API.
>
> IMHO, the semantic of the new API is closer to kstrtoull().
> It just limits the size, so I would call it kstrntoull().
>
> Also I would use int as the return parameter, see below.
Thanks for look into this one.
kstrntoull() was what I used in v8:
https://lore.kernel.org/r/20260303-adf41513-iio-driver-v8-0-8dd2417cc465@analog.com
There was a discussion around the naming:
https://lore.kernel.org/all/4mtdzxfj656sjr66npabfvrr7yd7q26l2unhsihjtniz4ossfj@g3qnzonoary6/
please suggest how the function prototype should look like.
...
> > +/* unsafe_strntoull ignores simple_strntoull() return value and endp const qualifier */
> > +inline
> > +static unsigned long long unsafe_strntoull(const char *startp, char **endp,
> > + unsigned int base, size_t max_chars)
> > +{
> > + unsigned long long result;
> > + const char *cp;
> > +
> > +#pragma GCC diagnostic push
> > +#pragma GCC diagnostic ignored "-Wunused-result"
> > + simple_strntoull(startp, &cp, base, max_chars, &result);
> > +#pragma GCC diagnostic pop
> > +
> > if (endp)
> > *endp = (char *)cp;
>
> IMHO, we do not need local "cp". We could simply pass the endp
> to the new simple_strntoull. Or do I miss anything?
Basically the unsafe version drops the const qualifier and compiler
complains that pointer types do not match. Maybe an extra warning can
be suppressed there.
--
Kind regards,
Rodrigo Alencar
^ permalink raw reply
* [PATCH v1 0/3] arm64: dts: amlogic: meson-s4: enable RTC and IR for Khadas VIM1S
From: Nick Xie @ 2026-03-27 9:30 UTC (permalink / raw)
To: neil.armstrong, khilman, martin.blumenstingl, jbrunet
Cc: krzk+dt, robh, conor+dt, linux-amlogic, linux-arm-kernel,
devicetree, linux-kernel, Nick Xie
This series adds support for the Real Time Clock (RTC) on the Amlogic
Meson S4 (S905Y4) SoC and enables the hardware RTC and IR receiver on
the Khadas VIM1S board.
- Patch 1 adds the internal Virtual RTC (VRTC) controller node to the
Meson S4 SoC dtsi.
- Patch 2 enables the I2C-attached Haoyu Micro HYM8563 RTC on the
Khadas VIM1S board. It also sets up aliases to ensure the hardware
RTC is prioritized as rtc0 over the VRTC.
- Patch 3 configures the default keymap to "rc-khadas" to support the
official Khadas IR remote control.
Nick Xie (3):
arm64: dts: amlogic: meson-s4: add VRTC node
arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable HYM8563 RTC
arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: use rc-khadas
keymap
.../dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts | 16 ++++++++++++++++
arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 5 +++++
2 files changed, 21 insertions(+)
--
2.34.1
^ permalink raw reply
* [PATCH v1 1/3] arm64: dts: amlogic: meson-s4: add VRTC node
From: Nick Xie @ 2026-03-27 9:30 UTC (permalink / raw)
To: neil.armstrong, khilman, martin.blumenstingl, jbrunet
Cc: krzk+dt, robh, conor+dt, linux-amlogic, linux-arm-kernel,
devicetree, linux-kernel, Nick Xie
In-Reply-To: <20260327093016.722095-1-nick@khadas.com>
Add the Virtual RTC (VRTC) controller node to the Meson S4 SoC dtsi.
Signed-off-by: Nick Xie <nick@khadas.com>
---
arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index 936a5c1353d15..2a6fbd5308362 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -59,6 +59,11 @@ psci {
method = "smc";
};
+ vrtc: rtc@fe010288 {
+ compatible = "amlogic,meson-vrtc";
+ reg = <0x0 0xfe010288 0x0 0x4>;
+ };
+
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v1 2/3] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable HYM8563 RTC
From: Nick Xie @ 2026-03-27 9:30 UTC (permalink / raw)
To: neil.armstrong, khilman, martin.blumenstingl, jbrunet
Cc: krzk+dt, robh, conor+dt, linux-amlogic, linux-arm-kernel,
devicetree, linux-kernel, Nick Xie
In-Reply-To: <20260327093016.722095-1-nick@khadas.com>
The Khadas VIM1S board has an on-board Haoyu Micro HYM8563 Real Time
Clock (RTC) connected to the I2C1 bus.
Enable the I2C1 controller and add the RTC child node to support
hardware clock persistence.
Signed-off-by: Nick Xie <nick@khadas.com>
---
.../dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
index 792ab45c4c944..7314e0ab81da3 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
@@ -20,6 +20,8 @@ aliases {
mmc0 = &emmc; /* eMMC */
mmc1 = &sd; /* SD card */
mmc2 = &sdio; /* SDIO */
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
serial0 = &uart_b;
};
@@ -223,6 +225,19 @@ ðmac {
phy-mode = "rmii";
};
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins2>;
+ clock-frequency = <100000>;
+
+ rtc: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+};
+
&ir {
status = "okay";
pinctrl-0 = <&remote_pins>;
--
2.34.1
^ permalink raw reply related
* [PATCH v1 3/3] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: use rc-khadas keymap
From: Nick Xie @ 2026-03-27 9:30 UTC (permalink / raw)
To: neil.armstrong, khilman, martin.blumenstingl, jbrunet
Cc: krzk+dt, robh, conor+dt, linux-amlogic, linux-arm-kernel,
devicetree, linux-kernel, Nick Xie
In-Reply-To: <20260327093016.722095-1-nick@khadas.com>
The Khadas VIM1S board has an onboard IR receiver.
Configure the default keymap to "rc-khadas" to support the official
Khadas IR remote control.
Signed-off-by: Nick Xie <nick@khadas.com>
---
arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
index 7314e0ab81da3..99d5df71b9cd4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
@@ -242,6 +242,7 @@ &ir {
status = "okay";
pinctrl-0 = <&remote_pins>;
pinctrl-names = "default";
+ linux,rc-map-name = "rc-khadas";
};
&pwm_ef {
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v11 2/3] of: Factor arguments passed to of_map_id() into a struct
From: Vijayanand Jitta @ 2026-03-27 9:35 UTC (permalink / raw)
To: Bjorn Helgaas, Richard Zhu, Lucas Stach
Cc: Nipun Gupta, Nikhil Agarwal, Joerg Roedel, Will Deacon,
Robin Murphy, Marc Zyngier, Lorenzo Pieralisi, Thomas Gleixner,
Saravana Kannan, Krzysztof Wilczyński, Manivannan Sadhasivam,
Bjorn Helgaas, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Juergen Gross, Stefano Stabellini,
Oleksandr Tyshchenko, Dmitry Baryshkov, Konrad Dybcio,
Bjorn Andersson, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
Prakash Gupta, Vikash Garodia, linux-kernel, iommu,
linux-arm-kernel, devicetree, linux-pci, imx, xen-devel,
linux-arm-msm, Charan Teja Kalla
In-Reply-To: <20260326161957.GA1324845@bhelgaas>
On 3/26/2026 9:49 PM, Bjorn Helgaas wrote:
> [cc->to: Richard, Lucas for pci-imx6.c question]
>
> On Wed, Mar 25, 2026 at 04:38:23PM +0530, Vijayanand Jitta wrote:
>> From: Charan Teja Kalla <charan.kalla@oss.qualcomm.com>
>>
>> Change of_map_id() to take a pointer to struct of_phandle_args
>> instead of passing target device node and translated IDs separately.
>> Update all callers accordingly.
>>
>> Add an explicit filter_np parameter to of_map_id() and of_map_msi_id()
>> to separate the filter input from the output. Previously, the target
>> parameter served dual purpose: as an input filter (if non-NULL, only
>> match entries targeting that node) and as an output (receiving the
>> matched node with a reference held). Now filter_np is the explicit
>> input filter and arg->np is the pure output.
>>
>> Previously, of_map_id() would call of_node_put() on the matched node
>> when a filter was provided, making reference ownership inconsistent.
>> Remove this internal of_node_put() call so that of_map_id() now always
>> transfers ownership of the matched node reference to the caller via
>> arg->np. Callers are now consistently responsible for releasing this
>> reference with of_node_put(arg->np) when done.
>> ...
>
> Not actually part of *this* patch, and AFAICS this patch is correct
> as-is, but is it necessary to have different logic around
> of_node_put() for imx_pcie_add_lut_by_rid() and
> apple_pcie_enable_device()?
>
Thanks for the review comments. Right, there is no need to have different
logic, I will update imx_pcie_add_lut_by_rid() in v12 so that of_node_put()
would be called unconditionally.
>> +++ b/drivers/pci/controller/dwc/pci-imx6.c
>> @@ -1137,6 +1137,8 @@ static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 rid)
>>
>> static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid)
>> {
>> + struct of_phandle_args iommu_spec = {};
>> + struct of_phandle_args msi_spec = {};
>> struct device *dev = imx_pcie->pci->dev;
>> struct device_node *target;
>> u32 sid_i, sid_m;
>> @@ -1144,7 +1146,12 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid)
>> u32 sid = 0;
>>
>> target = NULL;
>> - err_i = of_map_iommu_id(dev->of_node, rid, &target, &sid_i);
>> + err_i = of_map_iommu_id(dev->of_node, rid, &iommu_spec);
>> + if (!err_i) {
>> + target = iommu_spec.np;
>> + sid_i = iommu_spec.args[0];
>> + }
>> +
>> if (target) {
>> of_node_put(target);
>
> Here it's conditional on "target" even though of_node_put() checks
> internally for non-NULL, so it would be safe without the conditional
> here.
>
Agreed, here of_node_put can be called unconditionally , will fix it in v12.
>> } else {
>> @@ -1156,8 +1163,11 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid)
>> err_i = -EINVAL;
>> }
>>
>> - target = NULL;
>> - err_m = of_map_msi_id(dev->of_node, rid, &target, &sid_m);
>> + err_m = of_map_msi_id(dev->of_node, rid, NULL, &msi_spec);
>> + if (!err_m) {
>> + target = msi_spec.np;
>> + sid_m = msi_spec.args[0];
>> + }
>>
>> /*
>> * err_m target
>
> And here (outside the diff context) we also call of_node_put()
> conditionally:
>
> ...
> else if (target)
> of_node_put(target);
>
Agreed, same as above.
>> diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c
>> index a0937b7b3c4d..c2cffc0659f4 100644
>> --- a/drivers/pci/controller/pcie-apple.c
>> +++ b/drivers/pci/controller/pcie-apple.c
>> @@ -755,6 +755,7 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d
>> {
>> u32 sid, rid = pci_dev_id(pdev);
>> struct apple_pcie_port *port;
>> + struct of_phandle_args iommu_spec = {};
>> int idx, err;
>>
>> port = apple_pcie_get_port(pdev);
>> @@ -764,10 +765,12 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d
>> dev_dbg(&pdev->dev, "added to bus %s, index %d\n",
>> pci_name(pdev->bus->self), port->idx);
>>
>> - err = of_map_iommu_id(port->pcie->dev->of_node, rid, NULL, &sid);
>> + err = of_map_iommu_id(port->pcie->dev->of_node, rid, &iommu_spec);
>> if (err)
>> return err;
>>
>> + of_node_put(iommu_spec.np);
>
> Here we call of_node_put() unconditionally.
>
> I think it would be much nicer if imx_pcie_add_lut_by_rid() used the
> same style as apple_pcie_enable_device() and did the of_node_put()
> unconditionally. That would untangle the function a bit and make it
> easier to analyze.
>
Sure, as mentioned above will align imx_pcie_add_lut_by_rid() and
apple_pcie_enable_device().
Thanks,
Vijay
>> + sid = iommu_spec.args[0];
>> mutex_lock(&port->pcie->lock);
>>
>> idx = bitmap_find_free_region(port->sid_map, port->sid_map_sz, 0);
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: qcom: lemans-evk: enable UART0 for robot expansion board
From: Konrad Dybcio @ 2026-03-27 9:37 UTC (permalink / raw)
To: Canfeng Zhuang, konradybcio, andersson
Cc: robh, krzk+dt, conor+dt, linux-arm-msm, devicetree,
linux-arm-kernel
In-Reply-To: <20260327083101.1343613-2-canfeng.zhuang@oss.qualcomm.com>
On 3/27/26 9:31 AM, Canfeng Zhuang wrote:
> The lemans-evk mezzanine connector supports a robot expansion board that
> requires UART0, which is currently disabled. This prevents the expansion
> board from exchanging data and control commands.
>
> Enable UART0 and assign the serial2 alias to provide stable device
> enumeration for the expansion board.
>
> Signed-off-by: Canfeng Zhuang <canfeng.zhuang@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: qcom: monaco-evk: enable UART6 for robot expansion board
From: Konrad Dybcio @ 2026-03-27 9:37 UTC (permalink / raw)
To: Canfeng Zhuang, konradybcio, andersson
Cc: robh, krzk+dt, conor+dt, linux-arm-msm, devicetree,
linux-arm-kernel
In-Reply-To: <20260327083101.1343613-3-canfeng.zhuang@oss.qualcomm.com>
On 3/27/26 9:31 AM, Canfeng Zhuang wrote:
> The monaco-evk mezzanine connector supports a robot expansion board that
> requires UART6, which is currently disabled. This prevents the expansion
> board from exchanging data and control commands.
>
> Enable UART6 and assign the serial2 alias to provide stable device
> enumeration for the expansion board.
>
> Signed-off-by: Canfeng Zhuang <canfeng.zhuang@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* [PATCH net-next v2] dt-bindings: net: wireless: brcm: Add compatible for bcm43752
From: Ronald Claveau @ 2026-03-27 9:36 UTC (permalink / raw)
To: Johannes Berg, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
van Spriel
Cc: linux-wireless, devicetree, linux-kernel, netdev, Conor Dooley,
Ronald Claveau
Add bcm43752 compatible with its bcm4329 compatible fallback.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
---
The Khadas VIM4 board based on Amlogic A311D2 aka T7 features an AP6275s Wi-Fi/Bluetooth module with a BCM43752 chipset.
This patch aims to add this chipset with its fallback to bcm4329 compatible.
The original patch series is here:
https://lore.kernel.org/r/20260326-add-emmc-t7-vim4-v5-0-d3f182b48e9d@aliel.fr
---
Changes in v2:
- Add netdev in CC.
- Link to v1: https://lore.kernel.org/r/20260326-add-bcm43752-compatible-v1-1-b3b9a58ab38b@aliel.fr
---
Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml
index 3be7576787644..81fd3e37452a6 100644
--- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml
+++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml
@@ -42,6 +42,7 @@ properties:
- brcm,bcm4356-fmac
- brcm,bcm4359-fmac
- brcm,bcm4366-fmac
+ - brcm,bcm43752-fmac
- cypress,cyw4373-fmac
- cypress,cyw43012-fmac
- infineon,cyw43439-fmac
---
base-commit: 45b2b84ac6fde39c427018d6cdf7d44258938faa
change-id: 20260326-add-bcm43752-compatible-e264a4f7973a
Best regards,
--
Ronald Claveau <linux-kernel-dev@aliel.fr>
^ permalink raw reply related
* Re: [PATCH 4/7] dt-bindings: leds: irled: ir-spi-led: Add new duty-cycle value
From: Krzysztof Kozlowski @ 2026-03-27 9:38 UTC (permalink / raw)
To: Sean Young
Cc: Biswapriyo Nath, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Lee Jones, Pavel Machek,
Michael Turquette, Stephen Boyd, Martin Botka, linux-arm-msm,
devicetree, linux-kernel, linux-leds, linux-clk,
~postmarketos/upstreaming, phone-devel
In-Reply-To: <acZCrqffLvUpM7AW@gofer.mess.org>
On 27/03/2026 09:41, Sean Young wrote:
> On Fri, Mar 27, 2026 at 08:51:18AM +0100, Krzysztof Kozlowski wrote:
>> On Wed, Mar 25, 2026 at 06:07:27PM +0000, Biswapriyo Nath wrote:
>>> 30 duty cycle for IR transmitter is used in Xiaomi Redmi Note 8 (ginkgo).
>>>
>>> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
>>> ---
>>> Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml b/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml
>>> index 72cadebf6e3..0297bfbb275 100644
>>> --- a/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml
>>> +++ b/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml
>>> @@ -25,7 +25,7 @@ properties:
>>>
>>> duty-cycle:
>>> $ref: /schemas/types.yaml#/definitions/uint8
>>> - enum: [50, 60, 70, 75, 80, 90]
>>> + enum: [30, 50, 60, 70, 75, 80, 90]
>>
>> Hm, why is this enum, instead of 1-99, in the first place?
>
> Well in reality only a few different duty cycles are used by IR protocols.
> 30% is quite common so that should part of the list.
>
> Having said that a range of 1-99 would be nicer. Do we set this like so:
>
> - minimum: 1
> - maximum: 99
I asked, because I don't know what hardware is really there. This should
match reality, so if you say continuous range is never used, it does not
have the be changed to 1-99.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 2/3] remoteproc: imx_rproc: Pass bootaddr to SM CPU/LMM reset vector
From: Daniel Baluta @ 2026-03-27 9:45 UTC (permalink / raw)
To: Peng Fan (OSS), Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Daniel Baluta
Cc: linux-remoteproc, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
In-Reply-To: <20260327-imx943-rproc-v2-2-a547a3588730@nxp.com>
On 3/27/26 04:42, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Cortex-M[7,33] processors use a fixed reset vector table format:
>
> 0x00 Initial SP value
> 0x04 Reset vector
> 0x08 NMI
> 0x0C ...
> ...
> IRQ[n]
>
> In ELF images, the corresponding layout is:
>
> reset_vectors: --> hardware reset address
> .word __stack_end__
> .word Reset_Handler
> .word NMI_Handler
> .word HardFault_Handler
> ...
> .word UART_IRQHandler
> .word SPI_IRQHandler
> ...
>
> Reset_Handler: --> ELF entry point address
> ...
>
> The hardware fetches the first two words from reset_vectors and populates
> SP with __stack_end__ and PC with Reset_Handler. Execution proceeds from
> Reset_Handler.
>
> However, the ELF entry point does not always match the hardware reset
> address. For example, on i.MX94 CM33S:
>
> ELF entry point: 0x0ffc211d
> hardware reset base: 0x0ffc0000 (default reset value, sw programmable)
>
> To derive the correct hardware reset address, the unused lower bits must
> be masked off. The boot code should apply a SoC-specific mask before
> programming the reset address registers, e.g.:
>
> reset_address = entry & reset_vector_mask
>
> Current driver always programs the reset vector as 0. But i.MX94 CM33S's
> default reset base is 0x0ffc0000, so the correct reset vector must be
> passed to the SM API; otherwise the M33 Sync core cannot boot successfully.
>
> rproc_elf_get_boot_addr() returns the ELF entry point, which is not the
> hardware reset vector address. To derive the proper reset vector, this
> patch introduces imx_rproc_get_boot_addr(), which masks the ELF entry
> point using the SoC‑specific 'reset_vector_mask'. The resulting reset
> vector address is then passed to the SM CPU/LMM reset vector API calls.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
^ permalink raw reply
* Re: [PATCH v2 3/3] remoteproc: imx_rproc: Add support for i.MX94
From: Daniel Baluta @ 2026-03-27 9:46 UTC (permalink / raw)
To: Peng Fan (OSS), Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Daniel Baluta
Cc: linux-remoteproc, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
In-Reply-To: <20260327-imx943-rproc-v2-3-a547a3588730@nxp.com>
On 3/27/26 04:42, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add basic remoteproc support for the i.MX94 M-core processors, including
> address translation tables(dev addr is from view of remote processor,
> sys addr is from view of main processor) and device configuration data for
> the CM70, CM71, and CM33S cores.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
^ permalink raw reply
* Re: [PATCH 1/3] arm64: dts: qcom: kaanapali: Add SoCCP for Kaanapali SoC
From: Konrad Dybcio @ 2026-03-27 9:52 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang, linux-arm-msm,
devicetree, linux-kernel, 20260310-knp-soccp-v4-0-0a91575e0e7e
In-Reply-To: <20260326-knp-soccp-dt-v1-1-a60c2ae36e9b@oss.qualcomm.com>
On 3/27/26 4:20 AM, Jingyi Wang wrote:
> Add remoteproc PAS loader for SoCCP with its SMP2P. On Kaanapali, it
> is brought up by bootloader, so set the status "okay".
Simply remove it, "okay" is the default if the property is absent
[...]
> + remoteproc_soccp: remoteproc-soccp@d00000 {
-> remoteproc@
Konrad
^ permalink raw reply
* Re: [PATCH 2/3] arm64: dts: qcom: kaanapali-qrd: Add SoCCP node
From: Konrad Dybcio @ 2026-03-27 9:53 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang, linux-arm-msm,
devicetree, linux-kernel, 20260310-knp-soccp-v4-0-0a91575e0e7e
In-Reply-To: <20260326-knp-soccp-dt-v1-2-a60c2ae36e9b@oss.qualcomm.com>
On 3/27/26 4:20 AM, Jingyi Wang wrote:
> Add SoCCP node on Kaanapali QRD board.
This is really more of an "add firmware path"
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
> index da0e8f9091c3..6a7eb7f4050a 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
> @@ -781,6 +781,11 @@ &remoteproc_cdsp {
> status = "okay";
> };
>
> +&remoteproc_soccp {
> + firmware-name = "qcom/kaanapali/soccp.mbn",
> + "qcom/kaanapali/soccp_dtb.mbn";
Given that this contains battmgr now, can MTP and QRD use the same
firmware?
Konrad
^ permalink raw reply
* Re: [PATCH v4 1/2] dt-bindings: power: reset: qcom-pon: Add new compatible PMM8654AU
From: Rakesh Kota @ 2026-03-27 9:53 UTC (permalink / raw)
To: Rob Herring
Cc: Sebastian Reichel, Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Bjorn Andersson, Konrad Dybcio, linux-pm, devicetree,
linux-kernel, linux-arm-msm, Dmitry Baryshkov, Rakesh Kota
In-Reply-To: <20260323181820.GA888901-robh@kernel.org>
On Mon, Mar 23, 2026 at 01:18:20PM -0500, Rob Herring wrote:
> On Mon, Mar 23, 2026 at 04:15:15PM +0530, Rakesh Kota wrote:
> > PMM8654AU is a different PMIC from PMM8650AU, even though both share
> > the same PMIC subtype. Add PON compatible string for PMM8654AU PMIC
> > variant.
> >
> > The PMM8654AU PON block is compatible with the PMK8350 PON
> > implementation, but PMM8654AU also implements additional PON registers
> > beyond the baseline. Use the PMM8654AU naming to match the compatible
> > string already present in the upstream pinctrl-spmi-gpio driver, keeping
> > device tree and kernel driver naming consistent.
> >
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
> > ---
> > Changes in v4:
> > - Remove the contain for PMK8350 and new if:then for PMM8654AU as
> > suggested by Krzysztof Kozlowski
> >
> > Changes in v3:
> > - Update the commit message.
> >
> > Changes in v2:
> > - Introduces PMM8654AU compatible strings as suggested by Konrad Dybcio.
> > ---
> > .../devicetree/bindings/power/reset/qcom,pon.yaml | 32 +++++++++++++++++-----
> > 1 file changed, 25 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml
> > index 979a377cb4ffd577bfa51b9a3cd089acc202de0c..2a5d9182b8d5c1a286716ab175c7bb5e39b334e0 100644
> > --- a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml
> > +++ b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml
> > @@ -17,12 +17,16 @@ description: |
> >
> > properties:
> > compatible:
> > - enum:
> > - - qcom,pm8916-pon
> > - - qcom,pm8941-pon
> > - - qcom,pms405-pon
> > - - qcom,pm8998-pon
> > - - qcom,pmk8350-pon
> > + oneOf:
> > + - enum:
> > + - qcom,pm8916-pon
> > + - qcom,pm8941-pon
> > + - qcom,pms405-pon
> > + - qcom,pm8998-pon
> > + - qcom,pmk8350-pon
> > + - items:
> > + - const: qcom,pmm8654au-pon
> > + - const: qcom,pmk8350-pon
> >
> > reg:
> > description: |
> > @@ -100,7 +104,6 @@ allOf:
> > - if:
> > properties:
> > compatible:
> > - contains:
> > const: qcom,pmk8350-pon
> > then:
> > properties:
> > @@ -113,6 +116,21 @@ allOf:
> > - const: hlos
> > - const: pbs
> >
> > + - if:
> > + properties:
> > + compatible:
> > + const: qcom,pmm8654au-pon
> > + then:
> > + properties:
> > + reg:
> > + minItems: 1
> > + maxItems: 2
> > + reg-names:
> > + minItems: 1
> > + items:
> > + - const: hlos
> > + - const: pbs
>
> I don't understand this. The existing if/then schema did the exact same
> thing until you removed 'contains'. Now we just have the same schema
> duplicated.
>
> What does need changing now that I've looked at it is dropping 'reg'
> in this schema as it just repeats what the top-level schema has.
>
we have got suggestion to add a new if:then block for the new compatible from Krzysztof Kozlowski.
Best regards,
Rakesh kota
> Rob
^ permalink raw reply
* Re: [PATCH 2/7] arm64: dts: qcom: sm6125: Enable USB-C port handling
From: Konrad Dybcio @ 2026-03-27 9:55 UTC (permalink / raw)
To: Biswapriyo Nath
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Pavel Machek, Sean Young,
Michael Turquette, Stephen Boyd, Martin Botka, linux-arm-msm,
devicetree, linux-kernel, linux-leds, linux-clk,
~postmarketos/upstreaming, phone-devel
In-Reply-To: <20260326182821.8332-1-nathbappai@gmail.com>
On 3/26/26 7:28 PM, Biswapriyo Nath wrote:
> On Thu, 26 Mar 2026 10:41:03 +0100 Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
>
>> On 3/25/26 7:07 PM, Biswapriyo Nath wrote:
>>> Plug in USB-C related bits and pieces to enable USB role switching.
>>> Also, remove dr_mode to enable OTG capability.
>>>
>>> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
>>> ---
>>
>> I'm not sure what this is going to do for other 6125 devices
>> that don't have the Type-C infra wired up.. Does just applying
>> this commit alone keep peripheral mode working on your phone?
>>
>> Konrad
>>
>
> Yes, I have verified that USB peripheral mode is working with this
> patch only by using USB network[1].
Thanks
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH net-next 1/5] dpll: zl3073x: clean up esync get/set and use zl3073x_out_is_ndiv()
From: Petr Oros @ 2026-03-27 10:03 UTC (permalink / raw)
To: Ivan Vecera, netdev
Cc: Arkadiusz Kubalewski, Jiri Pirko, Michal Schmidt, Prathosh Satish,
Simon Horman, Vadim Fedorenko, linux-kernel, Conor Dooley,
Krzysztof Kozlowski, Rob Herring, devicetree, Pasi Vaananen
In-Reply-To: <20260319174826.7623-2-ivecera@redhat.com>
> Return -EOPNOTSUPP early in esync_get callbacks when esync is not
> supported instead of conditionally populating the range at the end.
> This simplifies the control flow by removing the finish label/goto
> in the output variant and the conditional range assignment in both
> input and output variants.
>
> Replace open-coded N-div signal format switch statements with
> zl3073x_out_is_ndiv() helper in esync_get, esync_set and
> frequency_set callbacks.
>
> Signed-off-by: Ivan Vecera <ivecera@redhat.com>
> ---
> drivers/dpll/zl3073x/dpll.c | 64 ++++++++++++-------------------------
> 1 file changed, 20 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c
> index a29f606318f6d..79ef62d69a32d 100644
> --- a/drivers/dpll/zl3073x/dpll.c
> +++ b/drivers/dpll/zl3073x/dpll.c
> @@ -131,6 +131,12 @@ zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin,
> ref_id = zl3073x_input_pin_ref_get(pin->id);
> ref = zl3073x_ref_state_get(zldev, ref_id);
>
> + if (!pin->esync_control || zl3073x_ref_freq_get(ref) == 1)
> + return -EOPNOTSUPP;
> +
> + esync->range = esync_freq_ranges;
> + esync->range_num = ARRAY_SIZE(esync_freq_ranges);
> +
> switch (FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl)) {
> case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75:
> esync->freq = ref->esync_n_div == ZL_REF_ESYNC_DIV_1HZ ? 1 : 0;
> @@ -142,17 +148,6 @@ zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin,
> break;
> }
>
> - /* If the pin supports esync control expose its range but only
> - * if the current reference frequency is > 1 Hz.
> - */
> - if (pin->esync_control && zl3073x_ref_freq_get(ref) > 1) {
> - esync->range = esync_freq_ranges;
> - esync->range_num = ARRAY_SIZE(esync_freq_ranges);
> - } else {
> - esync->range = NULL;
> - esync->range_num = 0;
> - }
> -
> return 0;
> }
>
> @@ -582,8 +577,8 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin,
> struct zl3073x_dpll_pin *pin = pin_priv;
> const struct zl3073x_synth *synth;
> const struct zl3073x_out *out;
> + u32 synth_freq, out_freq;
> u8 clock_type, out_id;
> - u32 synth_freq;
>
> out_id = zl3073x_output_pin_out_get(pin->id);
> out = zl3073x_out_state_get(zldev, out_id);
> @@ -592,17 +587,19 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin,
> * for N-division is also used for the esync divider so both cannot
> * be used.
> */
> - switch (zl3073x_out_signal_format_get(out)) {
> - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV:
> - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV:
> + if (zl3073x_out_is_ndiv(out))
> return -EOPNOTSUPP;
> - default:
> - break;
> - }
>
> /* Get attached synth frequency */
> synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(out));
> synth_freq = zl3073x_synth_freq_get(synth);
> + out_freq = synth_freq / out->div;
> +
> + if (!pin->esync_control || out_freq == 1)
> + return -EOPNOTSUPP;
> +
> + esync->range = esync_freq_ranges;
> + esync->range_num = ARRAY_SIZE(esync_freq_ranges);
>
> clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode);
> if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) {
> @@ -610,11 +607,11 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin,
> esync->freq = 0;
> esync->pulse = 0;
>
> - goto finish;
> + return 0;
> }
>
> /* Compute esync frequency */
> - esync->freq = synth_freq / out->div / out->esync_n_period;
> + esync->freq = out_freq / out->esync_n_period;
>
> /* By comparing the esync_pulse_width to the half of the pulse width
> * the esync pulse percentage can be determined.
> @@ -623,18 +620,6 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin,
> */
> esync->pulse = (50 * out->esync_n_width) / out->div;
>
> -finish:
> - /* Set supported esync ranges if the pin supports esync control and
> - * if the output frequency is > 1 Hz.
> - */
> - if (pin->esync_control && (synth_freq / out->div) > 1) {
> - esync->range = esync_freq_ranges;
> - esync->range_num = ARRAY_SIZE(esync_freq_ranges);
> - } else {
> - esync->range = NULL;
> - esync->range_num = 0;
> - }
> -
> return 0;
> }
>
> @@ -660,13 +645,8 @@ zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin,
> * for N-division is also used for the esync divider so both cannot
> * be used.
> */
> - switch (zl3073x_out_signal_format_get(&out)) {
> - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV:
> - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV:
> + if (zl3073x_out_is_ndiv(&out))
> return -EOPNOTSUPP;
> - default:
> - break;
> - }
>
> /* Select clock type */
> if (freq)
> @@ -728,9 +708,9 @@ zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin,
> struct zl3073x_dev *zldev = zldpll->dev;
> struct zl3073x_dpll_pin *pin = pin_priv;
> const struct zl3073x_synth *synth;
> - u8 out_id, signal_format;
> u32 new_div, synth_freq;
> struct zl3073x_out out;
> + u8 out_id;
>
> out_id = zl3073x_output_pin_out_get(pin->id);
> out = *zl3073x_out_state_get(zldev, out_id);
> @@ -740,12 +720,8 @@ zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin,
> synth_freq = zl3073x_synth_freq_get(synth);
> new_div = synth_freq / (u32)frequency;
>
> - /* Get used signal format for the given output */
> - signal_format = zl3073x_out_signal_format_get(&out);
> -
> /* Check signal format */
> - if (signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV &&
> - signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV) {
> + if (!zl3073x_out_is_ndiv(&out)) {
> /* For non N-divided signal formats the frequency is computed
> * as division of synth frequency and output divisor.
> */
LGTM,
Reviewed-by: Petr Oros <poros@redhat.com>
^ permalink raw reply
* Re: [PATCH v5 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema
From: Konrad Dybcio @ 2026-03-27 10:07 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Kishon Vijay Abraham I,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong
Cc: Bryan O'Donoghue, Vladimir Zapolskiy, linux-arm-msm,
linux-phy, linux-media, devicetree, linux-kernel
In-Reply-To: <20260326-x1e-csi2-phy-v5-1-0c0fc7f5c01b@linaro.org>
On 3/26/26 2:04 AM, Bryan O'Donoghue wrote:
> Add a base schema initially compatible with x1e80100 to describe MIPI CSI2
> PHY devices.
>
> The hardware can support both CPHY, DPHY and a special split-mode DPHY. We
> capture those modes as:
>
> - PHY_QCOM_CSI2_MODE_DPHY
> - PHY_QCOM_CSI2_MODE_CPHY
> - PHY_QCOM_CSI2_MODE_SPLIT_DPHY
Does the _PHY_ DT node need to be aware about this upfront?
If we have some sideband signal (e.g. the sensor driver specifically
requesting C-PHY mode), we can simply throw all this complexity into
phy_mode + phy_configure_opts, all at runtime
Further, the combo/split mode may possibly be selected through
aggregation of requests.
The question remains whether the sensor should have a direct connection to
the PHY itself (i.e. phys = <&csiphyN> or of_graph straight into the PHY)
or whether it's going to be translated by the camss node (which would be
the one holding a PHY reference) - there's probably surface for adding such
negotiation logic in both places
Note this is a question and I'm not aware of all the possible combinations
Konrad
^ permalink raw reply
* [PATCH RESEND] dt-bindings: thermal: qcom-tsens: Add Eliza SoC TSENS
From: Krzysztof Kozlowski @ 2026-03-27 10:07 UTC (permalink / raw)
To: Amit Kucheria, Thara Gopinath, Rafael J. Wysocki, Daniel Lezcano,
Zhang Rui, Lukasz Luba, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, linux-pm, devicetree, linux-kernel
Cc: Krzysztof Kozlowski, Konrad Dybcio
Document the compatible for Qualcomm Eliza SoC TSENS module, fully
compatible with TSENS v2 generation (e.g. SM8650).
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index 928243cd2883..7d34ba00e684 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -54,6 +54,7 @@ properties:
- description: v2 of TSENS
items:
- enum:
+ - qcom,eliza-tsens
- qcom,glymur-tsens
- qcom,kaanapali-tsens
- qcom,milos-tsens
--
2.51.0
^ permalink raw reply related
* Re: [PATCH v5 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver
From: Konrad Dybcio @ 2026-03-27 10:07 UTC (permalink / raw)
To: Hangxiang Ma, Bryan O'Donoghue, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong
Cc: Bryan O'Donoghue, Vladimir Zapolskiy, linux-arm-msm,
linux-phy, linux-media, devicetree, linux-kernel
In-Reply-To: <bc6abd24-d56a-4fc0-89e9-8986e8d8b3b7@oss.qualcomm.com>
On 3/27/26 3:23 AM, Hangxiang Ma wrote:
> On 3/26/2026 9:04 AM, Bryan O'Donoghue wrote:
>> +#include <linux/delay.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/time64.h>
>> +
>> +#include "phy-qcom-mipi-csi2.h"
>> +
>> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(offset, n) ((offset) + 0x4 * (n))
>> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL0_PHY_SW_RESET BIT(0)
>> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7)
>> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0)
>> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1)
>> +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL10_IRQ_CLEAR_CMD BIT(0)
>> +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x4 * (n))
>>
> Hi Bryan, one minor observation on the following macro:
>
> CSIPHY_3PH_CMN_CSI_COMMON_STATUSn
>
> The 0xb0 offset implicitly assumes a fixed distance between the
> common_ctrl and common_status register blocks. This holds for the PHYs
> covered by this series, but on some other platforms (e.g. Kaanapali,
> Pakala) the offset differs.
>
> That said, I think keeping this fixed value is reasonable for the scope
> of the current PHY series, and it does help keep the macro set simple.
> It might just be worth documenting this assumption (e.g. via a comment
> or in the commit message).
>
> Alternatively, if future PHY variants need to support different layouts,
> this could be made more extensible by moving the status base offset into
> the per-PHY data (similar to other register layout parameters). But I
> don’t think that needs to block the current series.
If the register contents are generally similar but the bit positions
and/or reg offsets differ, regmap_fields may be useful
Konrad
^ permalink raw reply
* [PATCH v7 0/5] Add driver for EC found on Qualcomm reference devices
From: Anvesh Jain P @ 2026-03-27 10:08 UTC (permalink / raw)
To: Sibi Sankar, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans de Goede, Ilpo Järvinen, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Randy Dunlap
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
Anvesh Jain P, Maya Matuszczyk, Krzysztof Kozlowski,
Dmitry Baryshkov, Konrad Dybcio, Abel Vesa, Gaurav Kohli
From: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Add Embedded controller driver support for Hamoa/Purwa/Glymur Qualcomm
reference boards. It handles fan control, temperature sensors, access
to EC state changes and supports reporting suspend entry/exit to the EC.
---
Changes in v7:
- Fixed alphabetical ordering of MAINTAINERS entry.
- Link to v6: https://lore.kernel.org/r/20260325-add-driver-for-ec-v6-0-a8e888d09f0f@oss.qualcomm.com
Changes in v6:
- Add missing includes: <linux/bits.h>, <linux/device.h>
and <linux/err.h>.
- Change the thermistor_mask format specifier from %d to %x.
- Change loop counter to unsigned int.
- Replace snprintf() with scnprintf() for safer string handling.
- Use sizeof(name) instead of the EC_FAN_NAME_SIZE macro directly.
- Add missing braces.
- Link to v5: https://lore.kernel.org/r/20260317-add-driver-for-ec-v5-0-38d11f524856@oss.qualcomm.com
Changes in v5:
- Fix subject line and commit description, drop redundant
"bindings for".
- Rename binding file: qcom,hamoa-ec.yaml → qcom,hamoa-crd-ec.yaml
to match the compatible string.
- Update $id URI to match the new filename.
- Add <linux/interrupt.h> and <linux/slab.h> includes.
- Switch to devm_thermal_of_cooling_device_register, remove manual
unroll loop.
- Ratelimit all IRQ handler log messages.
- Promote unknown EC event log from dev_dbg to dev_notice.
- Remove redundant error message after devm_request_threaded_irq.
- Simplify qcom_ec_sci_evt_control, resume, and suspend using direct
returns.
- Add dev_warn + early return for zero fan count; driver stays loaded
for PM notifications.
- Fix thermistor presence bitmask documentation: 1 = present, 0 = absent.
- Fix snprintf format specifier to %u to suppress -Wformat-truncation.
- Remove unused cdev variable from qcom_ec_probe.
- Fix typo: "exluding" → "excluding" in register map comments.
- Fix capitalization: "ec" → "EC" in error messages.
- Link to v4: https://lore.kernel.org/r/20260313-v04-add-driver-for-ec-v4-0-ca9d0efd62aa@oss.qualcomm.com
Changes in v4:
- Fix fan count calculation to use min() instead of max() to correctly
cap fan_cnt at EC_MAX_FAN_CNT.
- Remove unnecessary mutex lock/unlock.
- Disable fan debug mode on ec module removal.
- Fix issue reported by kernel test robot.
- Consolidate hamoa-iot-evk specific changes into hamoa-iot-evk.dts.
- Add board-specific compatible strings as per review comments.
- Link to v3: https://lore.kernel.org/all/20260308233646.2318676-1-sibi.sankar@oss.qualcomm.com/
Changes in v3:
- Revamp the bindings and driver to support generic ec specification
that works across Qualcomm Hamoa/Purwa and Glymur reference devices.
- Add ec nodes to Hamoa/Purwa CRDs and IOT-EVKs.
- Add ec node to Glymur CRDs.
- Link to v2: https://lore.kernel.org/lkml/20241219200821.8328-1-maccraft123mc@gmail.com/
- Link to v1: https://lore.kernel.org/lkml/20240927185345.3680-1-maccraft123mc@gmail.com/
---
Maya Matuszczyk (1):
dt-bindings: embedded-controller: Add Qualcomm reference device EC description
Sibi Sankar (4):
platform: arm64: Add driver for EC found on Qualcomm reference devices
arm64: dts: qcom: glymur-crd: Add Embedded controller node
arm64: dts: qcom: x1-crd: Add Embedded controller node
arm64: dts: qcom: hamoa-iot-evk: Add Embedded controller node
.../embedded-controller/qcom,hamoa-crd-ec.yaml | 56 +++
MAINTAINERS | 8 +
arch/arm64/boot/dts/qcom/glymur-crd.dts | 22 +
arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 16 +
arch/arm64/boot/dts/qcom/x1-crd.dtsi | 16 +
drivers/platform/arm64/Kconfig | 12 +
drivers/platform/arm64/Makefile | 1 +
drivers/platform/arm64/qcom-hamoa-ec.c | 451 +++++++++++++++++++++
8 files changed, 582 insertions(+)
---
base-commit: 85964cdcad0fac9a0eb7b87a0f9d88cc074b854c
change-id: 20260309-add-driver-for-ec-3fa478f264d9
Best regards,
--
Anvesh Jain P <anvesh.p@oss.qualcomm.com>
^ permalink raw reply
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