* [PATCH v3] dt-bindings: sound: Convert pcm3060 to DT Schema
From: Padmashree S S @ 2026-03-27 12:19 UTC (permalink / raw)
To: k.marinushkin, lgirdwood
Cc: broonie, robh, krzk+dt, conor+dt, linux-sound, devicetree,
linux-kernel, Padmashree S S
Convert pcm3060 to DT Schema
Signed-off-by: Padmashree S S <padmashreess2006@gmail.com>
---
.../devicetree/bindings/sound/pcm3060.txt | 23 ----------
.../devicetree/bindings/sound/pcm3060.yaml | 42 +++++++++++++++++++
2 files changed, 42 insertions(+), 23 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/pcm3060.txt
create mode 100644 Documentation/devicetree/bindings/sound/pcm3060.yaml
diff --git a/Documentation/devicetree/bindings/sound/pcm3060.txt b/Documentation/devicetree/bindings/sound/pcm3060.txt
deleted file mode 100644
index 97de66932d44..000000000000
--- a/Documentation/devicetree/bindings/sound/pcm3060.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-PCM3060 audio CODEC
-
-This driver supports both I2C and SPI.
-
-Required properties:
-
-- compatible: "ti,pcm3060"
-
-- reg : the I2C address of the device for I2C, the chip select
- number for SPI.
-
-Optional properties:
-
-- ti,out-single-ended: "true" if output is single-ended;
- "false" or not specified if output is differential.
-
-Examples:
-
- pcm3060: pcm3060@46 {
- compatible = "ti,pcm3060";
- reg = <0x46>;
- ti,out-single-ended = "true";
- };
diff --git a/Documentation/devicetree/bindings/sound/pcm3060.yaml b/Documentation/devicetree/bindings/sound/pcm3060.yaml
new file mode 100644
index 000000000000..2d920a70bced
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/pcm3060.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/pcm3060.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PCM3060 audio CODEC
+
+maintainers:
+ - Kirill Marinushkin <k.marinushkin@gmail.com>
+
+properties:
+ compatible:
+ const: ti,pcm3060
+
+ reg:
+ maxItems: 1
+
+ ti,out-single-ended:
+ type: boolean
+ description: |
+ If present, the output is single-ended.
+ If absent, the output is differential.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcm3060: audio-codec@46 {
+ compatible = "ti,pcm3060";
+ reg = <0x46>;
+ ti,out-single-ended;
+ };
+ };
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v2 03/15] firmware: qcom_scm: Migrate to generic PAS service
From: Sumit Garg @ 2026-03-27 12:18 UTC (permalink / raw)
To: Harshal Dev
Cc: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc, andersson,
konradybcio, robh, krzk+dt, conor+dt, robin.clark, sean, akhilpo,
lumag, abhinav.kumar, jesszhan0024, marijn.suijten, airlied,
simona, vikash.garodia, dikshita.agarwal, bod, mchehab, elder,
andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
linux-kernel, Sumit Garg
In-Reply-To: <bc7b116d-de41-4b9a-9c84-1010e226bac8@oss.qualcomm.com>
On Fri, Mar 27, 2026 at 05:40:16PM +0530, Harshal Dev wrote:
>
>
> On 3/12/2026 11:57 AM, Sumit Garg wrote:
> > From: Sumit Garg <sumit.garg@oss.qualcomm.com>
> >
> > With the availability of generic PAS service, let's add SCM calls as
> > a backend to keep supporting legacy QTEE interfaces. The exported
> > qcom_scm* wrappers will get dropped once all the client drivers get
> > migrated as part of future patches.
> >
> > Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
> > ---
> > drivers/firmware/qcom/Kconfig | 1 +
> > drivers/firmware/qcom/qcom_scm.c | 336 ++++++++++++++-----------------
> > 2 files changed, 156 insertions(+), 181 deletions(-)
> >
>
> [..]
>
> > diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
> > index 8fbc96693a55..2d7937ae7c8f 100644
> > --- a/drivers/firmware/qcom/qcom_scm.c
> > +++ b/drivers/firmware/qcom/qcom_scm.c
> > @@ -13,6 +13,7 @@
> > #include <linux/dma-mapping.h>
>
> [..]
>
> >
> > -/**
> > - * devm_qcom_scm_pas_context_alloc() - Allocate peripheral authentication service
> > - * context for a given peripheral
> > - *
> > - * PAS context is device-resource managed, so the caller does not need
> > - * to worry about freeing the context memory.
> > - *
> > - * @dev: PAS firmware device
> > - * @pas_id: peripheral authentication service id
> > - * @mem_phys: Subsystem reserve memory start address
> > - * @mem_size: Subsystem reserve memory size
> > - *
> > - * Returns: The new PAS context, or ERR_PTR() on failure.
> > - */
>
> Shouldn't we drop the documentation for the exported functions in this file as part of
> patch 14/15? After this patch is applied, the devm_qcom_scm_pas_context_alloc() function
> still remains exported and available.
I don't see value in maintaining redundant documentation during the
course of the patch-set. The wrappers are only maintained to keep the
individual commits compilable such that we don't break kernel git
bisection scripts.
-Sumit
^ permalink raw reply
* [PATCH 2/2] arm64: dts: qcom: milos: Add missing CX power domain to GCC
From: Abel Vesa @ 2026-03-27 12:13 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Luca Weiss, Taniya Das,
Konrad Dybcio, Dmitry Baryshkov
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Konrad Dybcio, Abel Vesa
In-Reply-To: <20260327-dt-fix-milos-eliza-gcc-power-domains-v1-0-f14a22c73fe9@oss.qualcomm.com>
Unless CX is declared as the power-domain of GCC, votes (power and
performance) on the GDSCs it provides will not propagate to the CX,
which might result in under-voltage conditions.
Add the missing power-domains property to associate GCC with RPMHPD_CX.
Fixes: d9d59d105f98 ("arm64: dts: qcom: Add initial Milos dtsi")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/milos.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 67f8ef4d524a..eec82a69ddc2 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -804,6 +804,8 @@ gcc: clock-controller@100000 {
<&ufs_mem_phy 2>,
<0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
--
2.48.1
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: clock: qcom: Add missing power-domains property
From: Abel Vesa @ 2026-03-27 12:13 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Luca Weiss, Taniya Das,
Konrad Dybcio, Dmitry Baryshkov
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Konrad Dybcio, Abel Vesa
In-Reply-To: <20260327-dt-fix-milos-eliza-gcc-power-domains-v1-0-f14a22c73fe9@oss.qualcomm.com>
In order for the GCC votes on the GDSCs it provides to be propagated
to CX, CX needs to be declared as power domain of the GCC.
Document the missing power-domains property to that purpose.
Fixes: 95ba6820a665 ("dt-bindings: clock: qcom: document the Milos Global Clock Controller")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml
index 60f1c8ca2c13..c65a6ad893d2 100644
--- a/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml
@@ -35,9 +35,14 @@ properties:
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
+ power-domains:
+ items:
+ - description: CX domain
+
required:
- compatible
- clocks
+ - power-domains
- '#power-domain-cells'
allOf:
@@ -48,6 +53,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,milos-gcc";
reg = <0x00100000 0x1f4200>;
@@ -59,6 +65,7 @@ examples:
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
--
2.48.1
^ permalink raw reply related
* [PATCH 0/2] arm64: dts: qcom: milos: Add missing CX power domain to GCC
From: Abel Vesa @ 2026-03-27 12:13 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Luca Weiss, Taniya Das,
Konrad Dybcio, Dmitry Baryshkov
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Konrad Dybcio, Abel Vesa
Recently, on Eliza, the CX has been tied up to the GCC.
This leads to dt-bindings check failing.
So the schema needs to be fixed. But the schema is same
for Milos. So instead of adding an if-clause for Eliza only,
tie the CX power domain to the GCC on Milos as well, for the
same exact reasons as on Eliza.
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Abel Vesa (2):
dt-bindings: clock: qcom: Add missing power-domains property
arm64: dts: qcom: milos: Add missing CX power domain to GCC
Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml | 7 +++++++
arch/arm64/boot/dts/qcom/milos.dtsi | 2 ++
2 files changed, 9 insertions(+)
---
base-commit: e77a5a5cfe43b4c25bd44a3818e487033287517f
change-id: 20260327-dt-fix-milos-eliza-gcc-power-domains-bdc66ad5d982
Best regards,
--
Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v2 03/15] firmware: qcom_scm: Migrate to generic PAS service
From: Harshal Dev @ 2026-03-27 12:10 UTC (permalink / raw)
To: Sumit Garg, linux-arm-msm, devicetree, dri-devel, freedreno,
linux-media, netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
linux-kernel, Sumit Garg
In-Reply-To: <20260312062756.694390-4-sumit.garg@kernel.org>
On 3/12/2026 11:57 AM, Sumit Garg wrote:
> From: Sumit Garg <sumit.garg@oss.qualcomm.com>
>
> With the availability of generic PAS service, let's add SCM calls as
> a backend to keep supporting legacy QTEE interfaces. The exported
> qcom_scm* wrappers will get dropped once all the client drivers get
> migrated as part of future patches.
>
> Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
> ---
> drivers/firmware/qcom/Kconfig | 1 +
> drivers/firmware/qcom/qcom_scm.c | 336 ++++++++++++++-----------------
> 2 files changed, 156 insertions(+), 181 deletions(-)
>
[..]
> diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
> index 8fbc96693a55..2d7937ae7c8f 100644
> --- a/drivers/firmware/qcom/qcom_scm.c
> +++ b/drivers/firmware/qcom/qcom_scm.c
> @@ -13,6 +13,7 @@
> #include <linux/dma-mapping.h>
[..]
>
> -/**
> - * devm_qcom_scm_pas_context_alloc() - Allocate peripheral authentication service
> - * context for a given peripheral
> - *
> - * PAS context is device-resource managed, so the caller does not need
> - * to worry about freeing the context memory.
> - *
> - * @dev: PAS firmware device
> - * @pas_id: peripheral authentication service id
> - * @mem_phys: Subsystem reserve memory start address
> - * @mem_size: Subsystem reserve memory size
> - *
> - * Returns: The new PAS context, or ERR_PTR() on failure.
> - */
Shouldn't we drop the documentation for the exported functions in this file as part of
patch 14/15? After this patch is applied, the devm_qcom_scm_pas_context_alloc() function
still remains exported and available.
Regards,
Harshal
^ permalink raw reply
* Re: [PATCH net-next 4/4] net: dsa: initial support for MT7628 embedded switch
From: Andrew Lunn @ 2026-03-27 12:07 UTC (permalink / raw)
To: Joris Vaisvila
Cc: netdev, horms, pabeni, kuba, edumazet, davem, olteanv, devicetree,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <20260326204413.3317584-5-joey@tinyisr.com>
> diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
> index 39fb8ead16b5..d07fc8dfe228 100644
> --- a/drivers/net/dsa/Kconfig
> +++ b/drivers/net/dsa/Kconfig
> @@ -70,6 +70,13 @@ config NET_DSA_MV88E6060
> This enables support for the Marvell 88E6060 ethernet switch
> chip.
>
> +config NET_DSA_MT7628
> + tristate "MT7628 Embedded ethernet switch support"
Please could you make this fit the pattern other devices have.
MediaTek MT7628 Embedded ethernet switch support
would be better. And please put it before MT7530. The sorting in
drivers/net/dsa/Kconfig is not great, but we should not make it worse.
> diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
> index f5a463b87ec2..22da6b680f29 100644
> --- a/drivers/net/dsa/Makefile
> +++ b/drivers/net/dsa/Makefile
> @@ -15,6 +15,7 @@ obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX) += vitesse-vsc73xx-core.o
> obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM) += vitesse-vsc73xx-platform.o
> obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_SPI) += vitesse-vsc73xx-spi.o
> obj-$(CONFIG_NET_DSA_YT921X) += yt921x.o
> +obj-$(CONFIG_NET_DSA_MT7628) += mt7628.o
This is also sorted, so should be inserted earlier.
> +static int mt7628_mii_read(struct mii_bus *bus, int port, int regnum)
> +{
> + struct mt7628_esw *esw = bus->priv;
> + int ret;
> + u32 val;
> +
> + ret = regmap_read_poll_timeout(esw->regmap, MT7628_ESW_REG_PCR1, val,
> + !(val & MT7628_ESW_PCR1_RD_DONE), 10,
> + 5000);
> + if (ret)
> + goto out;
> +
> + ret = regmap_write(esw->regmap, MT7628_ESW_REG_PCR0,
> + FIELD_PREP(MT7628_ESW_PCR0_CPU_PHY_REG,
> + regnum) |
> + FIELD_PREP(MT7628_ESW_PCR0_CPU_PHY_ADDR,
> + port) | MT7628_ESW_PCR0_RD_PHY_CMD);
> + if (ret)
> + goto out;
> +
> + ret = regmap_read_poll_timeout(esw->regmap, MT7628_ESW_REG_PCR1, val,
> + (val & MT7628_ESW_PCR1_RD_DONE), 10,
> + 5000);
> +out:
> + if (ret) {
> + dev_err(&bus->dev, "read failed. MDIO timeout?\n");
> + return -ETIMEDOUT;
Return the error code regmap_read_poll_timeout() or regmap_write()
returned.
> +static int mt7628_mii_write(struct mii_bus *bus, int port, int regnum, u16 dat)
> +{
> + struct mt7628_esw *esw = bus->priv;
> + u32 val;
> + int ret;
> +
> + ret = regmap_read_poll_timeout(esw->regmap, MT7628_ESW_REG_PCR1, val,
> + !(val & MT7628_ESW_PCR1_WT_DONE), 10,
> + 5000);
> + if (ret)
> + goto out;
> +
> + ret = regmap_write(esw->regmap, MT7628_ESW_REG_PCR0,
> + FIELD_PREP(MT7628_ESW_PCR0_WT_NWAY_DATA, dat) |
> + FIELD_PREP(MT7628_ESW_PCR0_CPU_PHY_REG,
> + regnum) |
> + FIELD_PREP(MT7628_ESW_PCR0_CPU_PHY_ADDR,
> + port) | MT7628_ESW_PCR0_WT_PHY_CMD);
> + if (ret)
> + goto out;
> +
> + ret = regmap_read_poll_timeout(esw->regmap, MT7628_ESW_REG_PCR1, val,
> + (val & MT7628_ESW_PCR1_WT_DONE), 10,
> + 5000);
> +out:
> + if (ret) {
> + dev_err(&bus->dev, "write failed. MDIO timeout?\n");
> + return -ETIMEDOUT;
Same here. And in general, always return the error code, if there is
one, don't make one up.
> +static int mt7628_setup_internal_mdio(struct dsa_switch *ds)
> +{
> + struct mt7628_esw *esw = ds->priv;
> + struct device_node *mdio;
> + struct mii_bus *bus;
> + int ret = 0;
> +
> + mdio = of_get_child_by_name(ds->dev->of_node, "mdio");
> + if (mdio && !of_device_is_available(mdio))
> + goto out_put_node;
of_get_available_child_by_name() ?
Andrew
^ permalink raw reply
* [PATCH v2] dts: riscv: spacemit: k3: add P1 PMIC regulator tree
From: Yixun Lan @ 2026-03-27 11:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Yixun Lan
Add the P1 PMIC's regulator topology tree for pico-itx board.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
This series try to add a regulator power tree from P1 PMIC,
the PMIC is controlled via an I2C interface.
To test this patch, it will need the I2C patch series [1]
Link: https://lore.kernel.org/all/20260325-02-k3-i2c-v1-0-78f29c83d9ac@kernel.org [1]
---
Changes in v2:
- drop regulator (dc 12v) which serves no devices
- drop regulators which current has no users
- Link to v1: https://lore.kernel.org/r/20260325-02-k3-i2c-v1-1-a793776b88bc@kernel.org
---
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 147 +++++++++++++++++++++++++++
arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 11 ++
2 files changed, 158 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
index 504fe6bd46b2..4486dc1fe114 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -25,6 +25,153 @@ memory@100000000 {
device_type = "memory";
reg = <0x1 0x00000000 0x4 0x00000000>;
};
+
+ reg_aux_vcc5v: regulator-aux-vcc5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AUX_VCC5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&i2c8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8_cfg>;
+ status = "okay";
+
+ p1@41 {
+ compatible = "spacemit,p1";
+ reg = <0x41>;
+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
+ vin1-supply = <®_aux_vcc5v>;
+ vin2-supply = <®_aux_vcc5v>;
+ vin3-supply = <®_aux_vcc5v>;
+ vin4-supply = <®_aux_vcc5v>;
+ vin5-supply = <®_aux_vcc5v>;
+ vin6-supply = <®_aux_vcc5v>;
+ aldoin-supply = <®_aux_vcc5v>;
+ dldoin1-supply = <&buck4>;
+ dldoin2-supply = <&buck4>;
+
+ regulators {
+ buck1: buck1 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck2: buck2 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck3: buck3 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck4: buck4 {
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2100000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck5: buck5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck6: buck6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <500000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ aldo1: aldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ aldo2: aldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ aldo3: aldo3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ aldo4: aldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ dldo1: dldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ dldo2: dldo2 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ dldo3: dldo3 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ dldo4: dldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ dldo5: dldo5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ dldo6: dldo6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ dldo7: dldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
};
ð0 {
diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
index a7b5d10c332e..23899d3f308a 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
@@ -45,6 +45,17 @@ gmac0-phy-0-pins {
};
};
+ /omit-if-no-ref/
+ i2c8_cfg: i2c8-cfg {
+ i2c8-pins {
+ pinmux = <K3_PADCONF(128, 0)>, /* i2c8 scl */
+ <K3_PADCONF(129, 0)>; /* i2c8 sda */
+
+ bias-pull-up = <0>;
+ drive-strength = <25>;
+ };
+ };
+
/omit-if-no-ref/
uart0_0_cfg: uart0-0-cfg {
uart0-0-pins {
---
base-commit: c9bc6f02e3252c20dd967811de7bf7739812259f
change-id: 20260311-02-k3-i2c-6ad52566a9a3
prerequisite-change-id: 20260311-02-k3-i2c-6ad52566a9a3:v1
prerequisite-patch-id: 9a6b8f6968935c8ed5c9acd8ecb778be2d1a3faa
prerequisite-patch-id: d43e077460cb3ea4e391fb7c528b6ffa80f35574
Best regards,
--
Yixun Lan <dlan@kernel.org>
^ permalink raw reply related
* Re: [PATCH v7 2/5] platform: arm64: Add driver for EC found on Qualcomm reference devices
From: Ilpo Järvinen @ 2026-03-27 11:50 UTC (permalink / raw)
To: Anvesh Jain P
Cc: Sibi Sankar, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans de Goede, Ilpo Järvinen, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Randy Dunlap, linux-arm-msm,
devicetree, linux-kernel, platform-driver-x86, Maya Matuszczyk,
Dmitry Baryshkov, Konrad Dybcio
In-Reply-To: <20260327-add-driver-for-ec-v7-2-7684c915e42c@oss.qualcomm.com>
On Fri, 27 Mar 2026, Anvesh Jain P wrote:
> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>
> Add Embedded controller driver support for Hamoa/Purwa/Glymur qualcomm
> reference boards. It handles fan control, temperature sensors, access
> to EC state changes and supports reporting suspend entry/exit to the
> EC.
>
> Co-developed-by: Maya Matuszczyk <maccraft123mc@gmail.com>
> Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Co-developed-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
> ---
> MAINTAINERS | 8 +
> drivers/platform/arm64/Kconfig | 12 +
> drivers/platform/arm64/Makefile | 1 +
> drivers/platform/arm64/qcom-hamoa-ec.c | 451 +++++++++++++++++++++++++++++++++
> 4 files changed, 472 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 30ca84404976..536dfd9adff4 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21804,6 +21804,14 @@ F: Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml
> F: drivers/misc/fastrpc.c
> F: include/uapi/misc/fastrpc.h
>
> +QUALCOMM HAMOA EMBEDDED CONTROLLER DRIVER
> +M: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
> +M: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> +L: linux-arm-msm@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-ec.yaml
> +F: drivers/platform/arm64/qcom-hamoa-ec.c
> +
> QUALCOMM HEXAGON ARCHITECTURE
> M: Brian Cain <brian.cain@oss.qualcomm.com>
> L: linux-hexagon@vger.kernel.org
> diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig
> index 10f905d7d6bf..025cdf091f9e 100644
> --- a/drivers/platform/arm64/Kconfig
> +++ b/drivers/platform/arm64/Kconfig
> @@ -90,4 +90,16 @@ config EC_LENOVO_THINKPAD_T14S
>
> Say M or Y here to include this support.
>
> +config EC_QCOM_HAMOA
> + tristate "Embedded Controller driver for Qualcomm Hamoa/Glymur reference devices"
> + depends on ARCH_QCOM || COMPILE_TEST
> + depends on I2C
> + help
> + Say M or Y here to enable the Embedded Controller driver for Qualcomm
> + Snapdragon-based Hamoa/Glymur reference devices. The driver handles fan
> + control, temperature sensors, access to EC state changes and supports
> + reporting suspend entry/exit to the EC.
> +
> + This driver currently supports Hamoa/Purwa/Glymur reference devices.
> +
> endif # ARM64_PLATFORM_DEVICES
> diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makefile
> index 60c131cff6a1..7681be4a46e9 100644
> --- a/drivers/platform/arm64/Makefile
> +++ b/drivers/platform/arm64/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_EC_ACER_ASPIRE1) += acer-aspire1-ec.o
> obj-$(CONFIG_EC_HUAWEI_GAOKUN) += huawei-gaokun-ec.o
> obj-$(CONFIG_EC_LENOVO_YOGA_C630) += lenovo-yoga-c630.o
> obj-$(CONFIG_EC_LENOVO_THINKPAD_T14S) += lenovo-thinkpad-t14s.o
> +obj-$(CONFIG_EC_QCOM_HAMOA) += qcom-hamoa-ec.o
> diff --git a/drivers/platform/arm64/qcom-hamoa-ec.c b/drivers/platform/arm64/qcom-hamoa-ec.c
> new file mode 100644
> index 000000000000..0f883130ac9a
> --- /dev/null
> +++ b/drivers/platform/arm64/qcom-hamoa-ec.c
> @@ -0,0 +1,451 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024 Maya Matuszczyk <maccraft123mc@gmail.com>
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/i2c.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/pm.h>
> +#include <linux/slab.h>
> +#include <linux/thermal.h>
> +
> +#define EC_SCI_EVT_READ_CMD 0x05
> +#define EC_FW_VERSION_CMD 0x0e
> +#define EC_MODERN_STANDBY_CMD 0x23
> +#define EC_FAN_DBG_CONTROL_CMD 0x30
> +#define EC_SCI_EVT_CONTROL_CMD 0x35
> +#define EC_THERMAL_CAP_CMD 0x42
> +
> +#define EC_FW_VERSION_RESP_LEN 4
> +#define EC_THERMAL_CAP_RESP_LEN 3
> +#define EC_FAN_DEBUG_CMD_LEN 6
> +#define EC_FAN_SPEED_DATA_SIZE 4
> +
> +#define EC_MODERN_STANDBY_ENTER 0x01
> +#define EC_MODERN_STANDBY_EXIT 0x00
> +
> +#define EC_FAN_DEBUG_MODE_OFF 0
> +#define EC_FAN_DEBUG_MODE_ON BIT(0)
Add include for BIT().
> +#define EC_FAN_ON BIT(1)
> +#define EC_FAN_DEBUG_TYPE_PWM BIT(2)
> +#define EC_MAX_FAN_CNT 2
> +#define EC_FAN_NAME_SIZE 20
> +#define EC_FAN_MAX_PWM 255
> +
> +enum qcom_ec_sci_events {
> + EC_FAN1_STATUS_CHANGE_EVT = 0x30,
> + EC_FAN2_STATUS_CHANGE_EVT,
> + EC_FAN1_SPEED_CHANGE_EVT,
> + EC_FAN2_SPEED_CHANGE_EVT,
> + EC_NEW_LUT_SET_EVT,
> + EC_FAN_PROFILE_SWITCH_EVT,
> + EC_THERMISTOR_1_THRESHOLD_CROSS_EVT,
> + EC_THERMISTOR_2_THRESHOLD_CROSS_EVT,
> + EC_THERMISTOR_3_THRESHOLD_CROSS_EVT,
> + /* Reserved: 0x39 - 0x3c/0x3f */
> + EC_RECOVERED_FROM_RESET_EVT = 0x3d,
> +};
> +
> +struct qcom_ec_version {
> + u8 main_version;
> + u8 sub_version;
> + u8 test_version;
> +};
> +
> +struct qcom_ec_thermal_cap {
> +#define EC_THERMAL_FAN_CNT(x) (FIELD_GET(GENMASK(1, 0), (x)))
> +#define EC_THERMAL_FAN_TYPE(x) (FIELD_GET(GENMASK(4, 2), (x)))
> +#define EC_THERMAL_THERMISTOR_MASK(x) (FIELD_GET(GENMASK(7, 0), (x)))
> + u8 fan_cnt;
> + u8 fan_type;
> + u8 thermistor_mask;
> +};
> +
> +struct qcom_ec_cooling_dev {
> + struct thermal_cooling_device *cdev;
> + struct device *parent_dev;
> + u8 fan_id;
> + u8 state;
> +};
> +
> +struct qcom_ec {
> + struct qcom_ec_cooling_dev *ec_cdev;
> + struct qcom_ec_thermal_cap thermal_cap;
> + struct qcom_ec_version version;
> + struct i2c_client *client;
> +};
> +
> +static int qcom_ec_read(struct qcom_ec *ec, u8 cmd, u8 resp_len, u8 *resp)
> +{
> + int ret;
> +
> + ret = i2c_smbus_read_i2c_block_data(ec->client, cmd, resp_len, resp);
> +
> + if (ret < 0)
> + return ret;
> + else if (ret == 0 || ret == 0xff)
> + return -EOPNOTSUPP;
> +
> + if (resp[0] >= resp_len)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +/*
> + * EC Device Firmware Version:
> + *
> + * Read Response:
> + * ----------------------------------------------------------------------
> + * | Offset | Name | Description |
> + * ----------------------------------------------------------------------
> + * | 0x00 | Byte count | Number of bytes in response |
> + * | | | (excluding byte count) |
> + * ----------------------------------------------------------------------
> + * | 0x01 | Test-version | Test-version of EC firmware |
> + * ----------------------------------------------------------------------
> + * | 0x02 | Sub-version | Sub-version of EC firmware |
> + * ----------------------------------------------------------------------
> + * | 0x03 | Main-version | Main-version of EC firmware |
> + * ----------------------------------------------------------------------
> + *
> + */
> +static int qcom_ec_read_fw_version(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + struct qcom_ec *ec = i2c_get_clientdata(client);
> + struct qcom_ec_version *version = &ec->version;
> + u8 resp[EC_FW_VERSION_RESP_LEN];
> + int ret;
> +
> + ret = qcom_ec_read(ec, EC_FW_VERSION_CMD, EC_FW_VERSION_RESP_LEN, resp);
> + if (ret < 0)
> + return ret;
> +
> + version->main_version = resp[3];
> + version->sub_version = resp[2];
> + version->test_version = resp[1];
> +
> + dev_dbg(dev, "EC Version %d.%d.%d\n",
> + version->main_version, version->sub_version, version->test_version);
> +
> + return 0;
> +}
> +
> +/*
> + * EC Device Thermal Capabilities:
> + *
> + * Read Response:
> + * ------------------------------------------------------------------------------
> + * | Offset | Name | Description |
> + * ------------------------------------------------------------------------------
> + * | 0x00 | Byte count | Number of bytes in response |
> + * | | | (excluding byte count) |
> + * ------------------------------------------------------------------------------
> + * | 0x02 (LSB) | EC Thermal | Bit 0-1: Number of fans |
> + * | 0x3 | Capabilities | Bit 2-4: Type of fan |
0x03 ?
> + * | | | Bit 5-6: Reserved |
> + * | | | Bit 7: Data Valid/Invalid |
> + * | | | (Valid - 1, Invalid - 0) |
> + * | | | Bit 8-15: Thermistor 0 - 7 presence |
> + * | | | (1 present, 0 absent) |
> + * ------------------------------------------------------------------------------
> + *
> + */
> +static int qcom_ec_thermal_capabilities(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + struct qcom_ec *ec = i2c_get_clientdata(client);
> + struct qcom_ec_thermal_cap *cap = &ec->thermal_cap;
> + u8 resp[EC_THERMAL_CAP_RESP_LEN];
> + int ret;
> +
> + ret = qcom_ec_read(ec, EC_THERMAL_CAP_CMD, EC_THERMAL_CAP_RESP_LEN, resp);
> + if (ret < 0)
> + return ret;
> +
> + cap->fan_cnt = min(EC_MAX_FAN_CNT, EC_THERMAL_FAN_CNT(resp[1]));
> + cap->fan_type = EC_THERMAL_FAN_TYPE(resp[1]);
> + cap->thermistor_mask = EC_THERMAL_THERMISTOR_MASK(resp[2]);
> +
> + dev_dbg(dev, "Fan count: %d Fan Type: %d Thermistor Mask: %x\n",
Please add include for dev_dbg().
It seems you've missed at least some of my comments to v5, please recheck
those comments. I won't look further for now.
--
i.
> + cap->fan_cnt, cap->fan_type, cap->thermistor_mask);
> +
> + return 0;
> +}
> +
> +static irqreturn_t qcom_ec_irq(int irq, void *data)
> +{
> + struct qcom_ec *ec = data;
> + struct device *dev = &ec->client->dev;
> + int val;
> +
> + val = i2c_smbus_read_byte_data(ec->client, EC_SCI_EVT_READ_CMD);
> + if (val < 0) {
> + dev_err_ratelimited(dev, "Failed to read EC SCI Event: %d\n", val);
> + return IRQ_HANDLED;
> + }
> +
> + switch (val) {
> + case EC_FAN1_STATUS_CHANGE_EVT:
> + dev_dbg_ratelimited(dev, "Fan1 status changed\n");
> + break;
> + case EC_FAN2_STATUS_CHANGE_EVT:
> + dev_dbg_ratelimited(dev, "Fan2 status changed\n");
> + break;
> + case EC_FAN1_SPEED_CHANGE_EVT:
> + dev_dbg_ratelimited(dev, "Fan1 speed crossed low/high trip point\n");
> + break;
> + case EC_FAN2_SPEED_CHANGE_EVT:
> + dev_dbg_ratelimited(dev, "Fan2 speed crossed low/high trip point\n");
> + break;
> + case EC_NEW_LUT_SET_EVT:
> + dev_dbg_ratelimited(dev, "New LUT set\n");
> + break;
> + case EC_FAN_PROFILE_SWITCH_EVT:
> + dev_dbg_ratelimited(dev, "FAN Profile switched\n");
> + break;
> + case EC_THERMISTOR_1_THRESHOLD_CROSS_EVT:
> + dev_dbg_ratelimited(dev, "Thermistor 1 threshold crossed\n");
> + break;
> + case EC_THERMISTOR_2_THRESHOLD_CROSS_EVT:
> + dev_dbg_ratelimited(dev, "Thermistor 2 threshold crossed\n");
> + break;
> + case EC_THERMISTOR_3_THRESHOLD_CROSS_EVT:
> + dev_dbg_ratelimited(dev, "Thermistor 3 threshold crossed\n");
> + break;
> + case EC_RECOVERED_FROM_RESET_EVT:
> + dev_dbg_ratelimited(dev, "EC recovered from reset\n");
> + break;
> + default:
> + dev_notice_ratelimited(dev, "Unknown EC event: %d\n", val);
> + break;
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int qcom_ec_sci_evt_control(struct device *dev, bool enable)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> +
> + return i2c_smbus_write_byte_data(client, EC_SCI_EVT_CONTROL_CMD, !!enable);
> +}
> +
> +static int qcom_ec_fan_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state)
> +{
> + *state = EC_FAN_MAX_PWM;
> +
> + return 0;
> +}
> +
> +static int qcom_ec_fan_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state)
> +{
> + struct qcom_ec_cooling_dev *ec_cdev = cdev->devdata;
> +
> + *state = ec_cdev->state;
> +
> + return 0;
> +}
> +
> +/*
> + * Fan Debug control command:
> + *
> + * Command Payload:
> + * --------------------------------------------------------------------------------------
> + * | Offset | Name | Description |
> + * --------------------------------------------------------------------------------------
> + * | 0x00 | Command | Fan control command |
> + * --------------------------------------------------------------------------------------
> + * | 0x01 | Fan ID | 0x1 : Fan 1 |
> + * | | | 0x2 : Fan 2 |
> + * --------------------------------------------------------------------------------------
> + * | 0x02 | Byte count = 4| Size of data to set fan speed |
> + * --------------------------------------------------------------------------------------
> + * | 0x03 | Mode | Bit 0: Debug Mode On/Off (0 - OFF, 1 - ON ) |
> + * | | | Bit 1: Fan On/Off (0 - Off, 1 - ON) |
> + * | | | Bit 2: Debug Type (0 - RPM, 1 - PWM) |
> + * --------------------------------------------------------------------------------------
> + * | 0x04 (LSB) | Speed in RPM | RPM value, if mode selected is RPM |
> + * | 0x05 | | |
> + * --------------------------------------------------------------------------------------
> + * | 0x06 | Speed in PWM | PWM value, if mode selected is PWM (0 - 255) |
> + * ______________________________________________________________________________________
> + *
> + */
> +static int qcom_ec_fan_debug_mode_off(struct qcom_ec_cooling_dev *ec_cdev)
> +{
> + struct device *dev = ec_cdev->parent_dev;
> + struct i2c_client *client = to_i2c_client(dev);
> + u8 request[6] = { ec_cdev->fan_id, EC_FAN_SPEED_DATA_SIZE,
> + EC_FAN_DEBUG_MODE_OFF, 0, 0, 0 };
> + int ret;
> +
> + ret = i2c_smbus_write_i2c_block_data(client, EC_FAN_DBG_CONTROL_CMD,
> + sizeof(request), request);
> + if (ret) {
> + dev_err(dev, "Failed to turn off fan%d debug mode: %d\n",
> + ec_cdev->fan_id, ret);
> + }
> +
> + return ret;
> +}
> +
> +static int qcom_ec_fan_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)
> +{
> + struct qcom_ec_cooling_dev *ec_cdev = cdev->devdata;
> + struct device *dev = ec_cdev->parent_dev;
> + struct i2c_client *client = to_i2c_client(dev);
> + u8 request[6] = { ec_cdev->fan_id, EC_FAN_SPEED_DATA_SIZE,
> + EC_FAN_DEBUG_MODE_ON | EC_FAN_ON | EC_FAN_DEBUG_TYPE_PWM,
> + 0, 0, state };
> + int ret;
> +
> + ret = i2c_smbus_write_i2c_block_data(client, EC_FAN_DBG_CONTROL_CMD,
> + sizeof(request), request);
> + if (ret) {
> + dev_err(dev, "Failed to set fan pwm: %d\n", ret);
> + return ret;
> + }
> +
> + ec_cdev->state = state;
> +
> + return 0;
> +}
> +
> +static const struct thermal_cooling_device_ops qcom_ec_thermal_ops = {
> + .get_max_state = qcom_ec_fan_get_max_state,
> + .get_cur_state = qcom_ec_fan_get_cur_state,
> + .set_cur_state = qcom_ec_fan_set_cur_state,
> +};
> +
> +static int qcom_ec_resume(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> +
> + return i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD,
> + EC_MODERN_STANDBY_ENTER);
> +}
> +
> +static int qcom_ec_suspend(struct device *dev)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> +
> + return i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD,
> + EC_MODERN_STANDBY_EXIT);
> +}
> +
> +static int qcom_ec_probe(struct i2c_client *client)
> +{
> + struct device *dev = &client->dev;
> + struct qcom_ec *ec;
> + unsigned int i;
> + int ret;
> +
> + ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL);
> + if (!ec)
> + return -ENOMEM;
> +
> + ec->client = client;
> +
> + ret = devm_request_threaded_irq(dev, client->irq, NULL, qcom_ec_irq,
> + IRQF_ONESHOT, "qcom_ec", ec);
> + if (ret < 0)
> + return ret;
> +
> + i2c_set_clientdata(client, ec);
> +
> + ret = qcom_ec_read_fw_version(dev);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to read EC firmware version\n");
> +
> + ret = qcom_ec_sci_evt_control(dev, true);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to enable SCI events\n");
> +
> + ret = qcom_ec_thermal_capabilities(dev);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to read thermal capabilities\n");
> +
> + if (ec->thermal_cap.fan_cnt == 0) {
> + dev_warn(dev, FW_BUG "Failed to get fan count, firmware update required\n");
> + return 0;
> + }
> +
> + ec->ec_cdev = devm_kcalloc(dev, ec->thermal_cap.fan_cnt, sizeof(*ec->ec_cdev), GFP_KERNEL);
> + if (!ec->ec_cdev)
> + return -ENOMEM;
> +
> + for (i = 0; i < ec->thermal_cap.fan_cnt; i++) {
> + struct qcom_ec_cooling_dev *ec_cdev = &ec->ec_cdev[i];
> + char name[EC_FAN_NAME_SIZE];
> +
> + scnprintf(name, sizeof(name), "qcom_ec_fan_%u", i);
> + ec_cdev->fan_id = i + 1;
> + ec_cdev->parent_dev = dev;
> +
> + ec_cdev->cdev = devm_thermal_of_cooling_device_register(dev, NULL, name, ec_cdev,
> + &qcom_ec_thermal_ops);
> + if (IS_ERR(ec_cdev->cdev)) {
> + return dev_err_probe(dev, PTR_ERR(ec_cdev->cdev),
> + "Failed to register fan%d cooling device\n", i);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_ec_remove(struct i2c_client *client)
> +{
> + struct qcom_ec *ec = i2c_get_clientdata(client);
> + struct device *dev = &client->dev;
> + int ret;
> +
> + ret = qcom_ec_sci_evt_control(dev, false);
> + if (ret < 0)
> + dev_err(dev, "Failed to disable SCI events: %d\n", ret);
> +
> + for (int i = 0; i < ec->thermal_cap.fan_cnt; i++) {
> + struct qcom_ec_cooling_dev *ec_cdev = &ec->ec_cdev[i];
> +
> + qcom_ec_fan_debug_mode_off(ec_cdev);
> + }
> +}
> +
> +static const struct of_device_id qcom_ec_of_match[] = {
> + { .compatible = "qcom,hamoa-crd-ec" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, qcom_ec_of_match);
> +
> +static const struct i2c_device_id qcom_ec_i2c_id_table[] = {
> + { "qcom-hamoa-ec", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(i2c, qcom_ec_i2c_id_table);
> +
> +static DEFINE_SIMPLE_DEV_PM_OPS(qcom_ec_pm_ops,
> + qcom_ec_suspend,
> + qcom_ec_resume);
> +
> +static struct i2c_driver qcom_ec_i2c_driver = {
> + .driver = {
> + .name = "qcom-hamoa-ec",
> + .of_match_table = qcom_ec_of_match,
> + .pm = &qcom_ec_pm_ops
> + },
> + .probe = qcom_ec_probe,
> + .remove = qcom_ec_remove,
> + .id_table = qcom_ec_i2c_id_table,
> +};
> +module_i2c_driver(qcom_ec_i2c_driver);
> +
> +MODULE_DESCRIPTION("QCOM Hamoa Embedded Controller");
> +MODULE_LICENSE("GPL");
>
>
^ permalink raw reply
* [PATCH v6 3/3] fpga-mgr: Add Efinix SPI programming driver
From: iansdannapel @ 2026-03-27 11:48 UTC (permalink / raw)
To: linux-fpga, devicetree, linux-kernel
Cc: mdf, yilun.xu, trix, robh, krzk+dt, conor+dt, neil.armstrong,
heiko, marex, prabhakar.mahadev-lad.rj, dev, Ian Dannapel
In-Reply-To: <20260327114842.1300284-1-iansdannapel@gmail.com>
From: Ian Dannapel <iansdannapel@gmail.com>
Add a new driver for loading binary firmware to configuration
RAM using "SPI passive mode" on Efinix FPGAs.
Efinix passive SPI configuration requires chip select to remain asserted
from reset until the complete bitstream and trailing idle clocks have
been transferred, so the driver keeps CS active with cs_change and locks
the SPI bus for the duration of configuration.
Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
---
drivers/fpga/Kconfig | 7 +
drivers/fpga/Makefile | 1 +
drivers/fpga/efinix-spi.c | 263 ++++++++++++++++++++++++++++++++++++++
3 files changed, 271 insertions(+)
create mode 100644 drivers/fpga/efinix-spi.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 37b35f58f0df..748fc210c135 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -288,6 +288,13 @@ config FPGA_MGR_LATTICE_SYSCONFIG_SPI
FPGA manager driver support for Lattice FPGAs programming over slave
SPI sysCONFIG interface.
+config FPGA_MGR_EFINIX_SPI
+ tristate "Efinix FPGA configuration over SPI"
+ depends on SPI
+ help
+ FPGA manager driver support for Efinix FPGAs configuration over SPI
+ (passive mode only).
+
source "drivers/fpga/tests/Kconfig"
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index aeb89bb13517..21eb0ef1fc2e 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
obj-$(CONFIG_FPGA_MGR_MICROCHIP_SPI) += microchip-spi.o
obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG) += lattice-sysconfig.o
obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI) += lattice-sysconfig-spi.o
+obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-spi.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
diff --git a/drivers/fpga/efinix-spi.c b/drivers/fpga/efinix-spi.c
new file mode 100644
index 000000000000..5cd6de0c5411
--- /dev/null
+++ b/drivers/fpga/efinix-spi.c
@@ -0,0 +1,263 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * FPGA Manager Driver for Efinix
+ *
+ * Copyright (C) 2025 iris-GmbH infrared & intelligent sensors
+ *
+ * Ian Dannapel <iansdannapel@gmail.com>
+ *
+ * Load Efinix FPGA firmware over SPI using the serial configuration interface.
+ *
+ * Note: Only passive mode (host initiates transfer) is currently supported.
+ */
+
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/spi/spi.h>
+
+/*
+ * 13 dummy bytes generate 104 SPI clock cycles (8 bits each).
+ * Used to meet the requirement for >100 clock cycles idle sequence.
+ */
+#define EFINIX_SPI_IDLE_CYCLES_BYTES 13
+
+/*
+ * tDMIN: Minimum time between deassertion of CRESET_N to first
+ * valid configuration data. (32 µs)
+ */
+#define EFINIX_TDMIN_US_MIN 35
+#define EFINIX_TDMIN_US_MAX 40
+
+/*
+ * tCRESET_N: Minimum CRESET_N low pulse width required to
+ * trigger re-configuration. (320 ns)
+ */
+#define EFINIX_TCRESETN_DELAY_MIN_US 1
+#define EFINIX_TCRESETN_DELAY_MAX_US 2
+
+/*
+ * tUSER: Minimum configuration duration after CDONE goes high
+ * before entering user mode. (25 µs)
+ */
+#define EFINIX_TUSER_US_MIN 30
+#define EFINIX_TUSER_US_MAX 35
+
+struct efinix_spi_conf {
+ struct spi_device *spi;
+ struct gpio_desc *cdone;
+ struct gpio_desc *reset;
+};
+
+static void efinix_spi_reset(struct efinix_spi_conf *conf)
+{
+ gpiod_set_value(conf->reset, 1);
+ usleep_range(EFINIX_TCRESETN_DELAY_MIN_US, EFINIX_TCRESETN_DELAY_MAX_US);
+ gpiod_set_value(conf->reset, 0);
+ usleep_range(EFINIX_TDMIN_US_MIN, EFINIX_TDMIN_US_MAX);
+}
+
+static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr)
+{
+ struct efinix_spi_conf *conf = mgr->priv;
+
+ if (conf->cdone && gpiod_get_value(conf->cdone) == 1)
+ return FPGA_MGR_STATE_OPERATING;
+
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int efinix_spi_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t count)
+{
+ struct device *dev = &mgr->dev;
+ struct efinix_spi_conf *conf = mgr->priv;
+ struct spi_transfer assert_cs = {
+ .cs_change = 1,
+ };
+ struct spi_message message;
+ int ret;
+
+ if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
+ dev_err(dev, "Partial reconfiguration not supported\n");
+ return -EOPNOTSUPP;
+ }
+
+ /*
+ * Efinix passive SPI configuration requires chip select to stay
+ * asserted from reset until the bitstream is fully clocked in.
+ * Lock the SPI bus so no other device can toggle CS between the
+ * reset pulse and the write/complete transfers.
+ */
+ spi_bus_lock(conf->spi->controller);
+ spi_message_init_with_transfers(&message, &assert_cs, 1);
+ ret = spi_sync_locked(conf->spi, &message);
+ if (ret) {
+ spi_bus_unlock(conf->spi->controller);
+ return ret;
+ }
+
+ /* Reset with CS asserted */
+ efinix_spi_reset(conf);
+
+ return 0;
+}
+
+static int efinix_spi_write(struct fpga_manager *mgr, const char *buf,
+ size_t count)
+{
+ struct device *dev = &mgr->dev;
+ struct spi_transfer write_xfer = {
+ .tx_buf = buf,
+ .len = count,
+ .cs_change = 1, /* Keep CS asserted */
+ };
+ struct efinix_spi_conf *conf = mgr->priv;
+ struct spi_message message;
+ int ret;
+
+ spi_message_init_with_transfers(&message, &write_xfer, 1);
+ ret = spi_sync_locked(conf->spi, &message);
+ if (ret) {
+ dev_err(dev, "SPI error in firmware write: %d\n", ret);
+ spi_bus_unlock(conf->spi->controller);
+ }
+
+ return ret;
+}
+
+static int efinix_spi_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ unsigned long timeout =
+ jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
+ struct spi_transfer clk_cycles = {
+ .len = EFINIX_SPI_IDLE_CYCLES_BYTES,
+ /* Release CS after the trailing idle clocks are sent. */
+ .cs_change = 0,
+ };
+ struct efinix_spi_conf *conf = mgr->priv;
+ struct spi_message message;
+ int done, ret;
+ bool expired = false;
+ u8 *dummy_buf;
+
+ dummy_buf = kzalloc(EFINIX_SPI_IDLE_CYCLES_BYTES, GFP_KERNEL);
+ if (!dummy_buf) {
+ ret = -ENOMEM;
+ goto unlock_spi;
+ }
+
+ /*
+ * Keep the bus locked while sending the trailing idle clocks, then
+ * let this final transfer deassert CS to terminate configuration.
+ */
+ clk_cycles.tx_buf = dummy_buf;
+ spi_message_init_with_transfers(&message, &clk_cycles, 1);
+ ret = spi_sync_locked(conf->spi, &message);
+ if (ret) {
+ dev_err(&mgr->dev, "SPI error in write complete: %d\n", ret);
+ goto free_buf;
+ }
+
+ if (conf->cdone) {
+ while (!expired) {
+ done = gpiod_get_value(conf->cdone);
+ if (done < 0) {
+ ret = done;
+ goto free_buf;
+ }
+ if (done)
+ break;
+
+ usleep_range(10, 20);
+ expired = time_after(jiffies, timeout);
+ }
+
+ if (expired) {
+ dev_err(&mgr->dev, "Timeout waiting for CDONE\n");
+ ret = -ETIMEDOUT;
+ goto free_buf;
+ }
+ }
+
+ usleep_range(EFINIX_TUSER_US_MIN, EFINIX_TUSER_US_MAX);
+
+free_buf:
+ kfree(dummy_buf);
+unlock_spi:
+ spi_bus_unlock(conf->spi->controller);
+
+ return ret;
+}
+
+static const struct fpga_manager_ops efinix_spi_ops = {
+ .state = efinix_spi_state,
+ .write_init = efinix_spi_write_init,
+ .write = efinix_spi_write,
+ .write_complete = efinix_spi_write_complete,
+};
+
+static int efinix_spi_probe(struct spi_device *spi)
+{
+ struct efinix_spi_conf *conf;
+ struct fpga_manager *mgr;
+
+ if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL))
+ return dev_err_probe(&spi->dev, -EINVAL,
+ "Unsupported SPI mode, set CPHA and CPOL\n");
+
+ conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
+ if (!conf)
+ return -ENOMEM;
+
+ conf->reset = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(conf->reset))
+ return dev_err_probe(&spi->dev, PTR_ERR(conf->reset),
+ "Failed to get RESET gpio\n");
+
+ conf->cdone = devm_gpiod_get_optional(&spi->dev, "cdone", GPIOD_IN);
+ if (IS_ERR(conf->cdone))
+ return dev_err_probe(&spi->dev, PTR_ERR(conf->cdone),
+ "Failed to get CDONE gpio\n");
+
+ conf->spi = spi;
+
+ mgr = devm_fpga_mgr_register(&spi->dev,
+ "Efinix FPGA Manager",
+ &efinix_spi_ops, conf);
+
+ return PTR_ERR_OR_ZERO(mgr);
+}
+
+static const struct of_device_id efinix_spi_of_match[] = {
+ { .compatible = "efinix,trion-config", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, efinix_spi_of_match);
+
+static const struct spi_device_id efinix_ids[] = {
+ { "trion-config", 0 },
+ { "titanium-config", 0 },
+ { "topaz-config", 0 },
+ {},
+};
+MODULE_DEVICE_TABLE(spi, efinix_ids);
+
+static struct spi_driver efinix_spi_driver = {
+ .driver = {
+ .name = "efinix-spi",
+ .of_match_table = efinix_spi_of_match,
+ },
+ .probe = efinix_spi_probe,
+ .id_table = efinix_ids,
+};
+
+module_spi_driver(efinix_spi_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Ian Dannapel <iansdannapel@gmail.com>");
+MODULE_DESCRIPTION("Efinix FPGA SPI Programming Driver");
--
2.43.0
^ permalink raw reply related
* [PATCH v6 2/3] dt-bindings: fpga: Add Efinix SPI programming bindings
From: iansdannapel @ 2026-03-27 11:48 UTC (permalink / raw)
To: linux-fpga, devicetree, linux-kernel
Cc: mdf, yilun.xu, trix, robh, krzk+dt, conor+dt, neil.armstrong,
heiko, marex, prabhakar.mahadev-lad.rj, dev, Ian Dannapel
In-Reply-To: <20260327114842.1300284-1-iansdannapel@gmail.com>
From: Ian Dannapel <iansdannapel@gmail.com>
Add device tree bindings documentation for configuring Efinix FPGA
using serial SPI passive programming mode.
Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
---
.../bindings/fpga/efinix,trion-config.yaml | 96 +++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml
diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml
new file mode 100644
index 000000000000..7e84397e242c
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/efinix,trion-config.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Efinix SPI FPGA Manager
+
+maintainers:
+ - Ian Dannapel <iansdannapel@gmail.com>
+
+description: |
+ Efinix FPGAs (Trion, Topaz, and Titanium families) support loading bitstreams
+ through "SPI Passive Mode".
+ Additional pin hogs for bus width configuration should be set
+ elsewhere, if necessary.
+
+ References:
+ - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.3.pdf
+ - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.8.pdf
+ - https://www.efinixinc.com/docs/an061-configuring-topaz-fpgas-v1.1.pdf
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - efinix,titanium-config
+ - efinix,topaz-config
+ - const: efinix,trion-config
+ - const: efinix,trion-config
+
+ spi-cpha: true
+
+ spi-cpol: true
+
+ spi-max-frequency:
+ maximum: 25000000
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ description:
+ reset and re-configuration trigger pin (low active)
+ maxItems: 1
+
+ cdone-gpios:
+ description:
+ optional configuration done status pin (high active)
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ fpga-mgr@0 {
+ compatible = "efinix,trion-config";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ spi-cpha;
+ spi-cpol;
+ reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+ cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ fpga-mgr@0 {
+ compatible = "efinix,titanium-config", "efinix,trion-config";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ spi-cpha;
+ spi-cpol;
+ reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+ cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+ };
+...
--
2.43.0
^ permalink raw reply related
* [PATCH v6 1/3] dt-bindings: vendor-prefix: Add prefix for Efinix, Inc.
From: iansdannapel @ 2026-03-27 11:48 UTC (permalink / raw)
To: linux-fpga, devicetree, linux-kernel
Cc: mdf, yilun.xu, trix, robh, krzk+dt, conor+dt, neil.armstrong,
heiko, marex, prabhakar.mahadev-lad.rj, dev, Ian Dannapel,
Conor Dooley, Alexander Dahl
In-Reply-To: <20260327114842.1300284-1-iansdannapel@gmail.com>
From: Ian Dannapel <iansdannapel@gmail.com>
Add entry for Efinix, Inc. (https://www.efinixinc.com/)
Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Alexander Dahl <ada@thorsis.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ee7fd3cfe203..dd3837500915 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -481,6 +481,8 @@ patternProperties:
description: Emtop Embedded Solutions
"^eeti,.*":
description: eGalax_eMPIA Technology Inc
+ "^efinix,.*":
+ description: Efinix, Inc.
"^egnite,.*":
description: egnite GmbH
"^einfochips,.*":
--
2.43.0
^ permalink raw reply related
* [PATCH v6 0/3] Add Efinix FPGA configuration support
From: iansdannapel @ 2026-03-27 11:48 UTC (permalink / raw)
To: linux-fpga, devicetree, linux-kernel
Cc: mdf, yilun.xu, trix, robh, krzk+dt, conor+dt, neil.armstrong,
heiko, marex, prabhakar.mahadev-lad.rj, dev, Ian Dannapel
From: Ian Dannapel <iansdannapel@gmail.com>
Hi all,
This is v6 of the series adding support for programming Efinix FPGAs
over SPI using the fpga-mgr subsystem.
The series adds DT bindings for the Efinix SPI configuration interface
and a new FPGA manager driver implementing passive SPI configuration.
Testing:
- Verified on a custom board with an Efinix Trion T13 FPGA
- Tested full bitstream configuration over SPI at 25 MHz
Changes since v5:
dt-bindings: vendor-prefix: Add prefix for Efinix, Inc.
- fixed trailer formatting
dt-bindings: fpga: Add Efinix SPI programming bindings
- renamed the binding from efinix,trion-spi.yaml to
efinix,trion-config.yaml
- replaced the generic fallback approach with a family fallback scheme
- made efinix,trion-config the required fallback for Titanium and Topaz
- updated the example to use the new compatible naming
- added an example showing the fallback-compatible form
- removed driver-limitation wording from the binding description
fpga-mgr: Add Efinix SPI programming driver
- renamed compatibles from *-spi to *-config
- aligned the driver with the fallback-compatible scheme
- removed direct OF matching for Titanium and Topaz so binding happens
via the Trion fallback compatible
- moved Kconfig and Makefile entries to the end of the FPGA manager
sections
- fixed kernel-doc style multi-line comments
- documented why chip select must stay asserted across reset and
bitstream transfer
- removed the redundant bus_locked state
- reordered probe initialization
Ian Dannapel (3):
dt-bindings: vendor-prefix: Add prefix for Efinix, Inc.
dt-bindings: fpga: Add Efinix SPI programming bindings
fpga-mgr: Add Efinix SPI programming driver
.../bindings/fpga/efinix,trion-config.yaml | 96 +++++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
drivers/fpga/Kconfig | 7 +
drivers/fpga/Makefile | 1 +
drivers/fpga/efinix-spi.c | 263 ++++++++++++++++++
5 files changed, 369 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml
create mode 100644 drivers/fpga/efinix-spi.c
--
2.43.0
^ permalink raw reply
* Re: [PATCH net-next 2/4] net: phy: mediatek: add phy driver for MT7628 built-in Fast Ethernet PHYs
From: Andrew Lunn @ 2026-03-27 11:48 UTC (permalink / raw)
To: Joris Vaisvila
Cc: netdev, horms, pabeni, kuba, edumazet, davem, olteanv, devicetree,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <20260326204413.3317584-3-joey@tinyisr.com>
On Thu, Mar 26, 2026 at 10:44:11PM +0200, Joris Vaisvila wrote:
> The Fast Ethernet PHYs present in the MT7628 SoCs require an
> undocumented bit to be set before they can establish 100mbps links.
>
> This commit adds the Kconfig option MEDIATEK_FE_SOC_PHY and the
> corresponding driver mtk-fe-soc.c.
>
> Signed-off-by: Joris Vaisvila <joey@tinyisr.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [PATCH v2] dt-bindings: arm: marvell: Convert armada-380-mpcore-soc-ctrl to DT Schema
From: Padmashree S S @ 2026-03-27 11:46 UTC (permalink / raw)
To: andrew, gregory.clement, sebastian.hesselbarth
Cc: robh, krzk+dt, conor+dt, linux-arm-kernel, devicetree,
linux-kernel, Padmashree S S
Convert armada-380-mpcore-soc-ctrl to DT schema
Signed-off-by: Padmashree S S <padmashreess2006@gmail.com>
---
.../marvell/armada-380-mpcore-soc-ctrl.txt | 14 --------
.../marvell/armada-380-mpcore-soc-ctrl.yaml | 32 +++++++++++++++++++
2 files changed, 32 insertions(+), 14 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.yaml
diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
deleted file mode 100644
index 8781073029e9..000000000000
--- a/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Marvell Armada 38x CA9 MPcore SoC Controller
-============================================
-
-Required properties:
-
-- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
-
-- reg: should be the register base and length as documented in the
- datasheet for the CA9 MPcore SoC Control registers
-
-mpcore-soc-ctrl@20d20 {
- compatible = "marvell,armada-380-mpcore-soc-ctrl";
- reg = <0x20d20 0x6c>;
-};
diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.yaml
new file mode 100644
index 000000000000..a897d4ba4e32
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.yaml
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/marvell/armada-380-mpcore-soc-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Armada 38x CA9 MPcore SoC Controller
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+ - Gregory Clement <gregory.clement@bootlin.com>
+ - Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+
+properties:
+ compatible:
+ const: marvell,armada-380-mpcore-soc-ctrl
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ mpcore-soc-ctrl@20d20 {
+ compatible = "marvell,armada-380-mpcore-soc-ctrl";
+ reg = <0x20d20 0x6c>;
+ };
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v2 1/3] pinctrl: sunxi: a523: Remove unneeded IRQ remuxing flag
From: Jernej Škrabec @ 2026-03-27 11:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Samuel Holland, Andre Przywara
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
In-Reply-To: <20260327113006.3135663-2-andre.przywara@arm.com>
Dne petek, 27. marec 2026 ob 12:30:04 Srednjeevropski standardni čas je Andre Przywara napisal(a):
> The Allwinner A10 and H3 SoCs cannot read the state of a GPIO line when
> that line is muxed for IRQ triggering (muxval 6), but only if it's
> explicitly muxed for GPIO input (muxval 0). Other SoCs do not show this
> behaviour, so we added a optional workaround, triggered by a quirk bit,
> which triggers remuxing the pin when it's configured for IRQ, while we
> need to read its value.
>
> For some reasons this quirk flag was copied over to newer SoCs, even
> though they don't show this behaviour, and the GPIO data register
> reflects the true GPIO state even with a pin muxed to IRQ trigger.
>
> Remove the unneeded quirk from the A523 family, where it's definitely
> not needed (confirmed by experiments), and where it actually breaks,
> because the workaround is not compatible with the newer generation
> pinctrl IP used in that chip.
>
> Together with a DT change this fixes GPIO IRQ operation on the A523
> family of SoCs, as for instance used for the SD card detection.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Fixes: b8a51e95b376 ("pinctrl: sunxi: Add support for the secondary A523 GPIO ports")
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
^ permalink raw reply
* Re: [PATCH v2 2/3] dt-bindings: pinctrl: sun55i-a523: increase IRQ banks number
From: Jernej Škrabec @ 2026-03-27 11:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Samuel Holland, Andre Przywara
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
In-Reply-To: <20260327113006.3135663-3-andre.przywara@arm.com>
Dne petek, 27. marec 2026 ob 12:30:05 Srednjeevropski standardni čas je Andre Przywara napisal(a):
> The Allwinner A523 SoC implements 10 GPIO banks in the first pinctrl
> instance, but it skips the first bank (PortA), so their index goes from
> 1 to 10. The same is actually true for the IRQ banks: there are registers
> for 11 banks, though the first bank is not implemented (RAZ/WI).
> In contrast to previous SoCs, the count of the IRQ banks starts with this
> first unimplemented bank, so we need to provide an interrupt for it.
> And indeed the A523 user manual lists an interrupt number for PortA, so we
> need to increase the maximum number of interrupts per pin controller to 11,
> to be able to assign the correct interrupt number for each bank.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: allwinner: a523: Add missing GPIO interrupt
From: Jernej Škrabec @ 2026-03-27 11:42 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Samuel Holland, Andre Przywara
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
In-Reply-To: <20260327113006.3135663-4-andre.przywara@arm.com>
Dne petek, 27. marec 2026 ob 12:30:06 Srednjeevropski standardni čas je Andre Przywara napisal(a):
> Even though the Allwinner A523 SoC implements 10 GPIO banks, it has
> actually registers for 11 IRQ banks, and even an interrupt assigned to
> the first, non-implemented IRQ bank.
> Add that first interrupt to the list of GPIO interrupts, to correct the
> association between IRQs and GPIO banks.
>
> This fixes GPIO IRQ operation on boards with A523 SoCs, as seen by
> broken SD card detect functionality, for instance.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Fixes: 35ac96f79664 ("arm64: dts: allwinner: Add Allwinner A523 .dtsi file")
> Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
^ permalink raw reply
* Re: [PATCH 01/12] dt-bindings: i3c: Add mipi-i3c-static-method to support SETAASA
From: Akhil R @ 2026-03-27 11:42 UTC (permalink / raw)
To: alexandre.belloni
Cc: Frank.Li, acpica-devel, akhilrajeev, conor+dt, conor, devicetree,
ebiggers, fredrik.markstrom, jonathanh, krzk+dt, lenb, linux-acpi,
linux-hwmon, linux-i3c, linux-kernel, linux-tegra, linux,
miquel.raynal, p.zabel, rafael, robert.moore, robh, smangipudi,
thierry.reding
In-Reply-To: <20260327082721f7e69e6a@mail.local>
On Fri, 27 Mar 2026 09:27:21 +0100, Alexandre Belloni wrote:
> On 27/03/2026 13:48:58+0530, Akhil R wrote:
>> On Thu, 26 Mar 2026 16:44:31 +0100, Alexandre Belloni wrote:
>> > On 26/03/2026 10:05:03-0500, Rob Herring wrote:
>> >> On Wed, Mar 18, 2026 at 05:31:50PM +0000, Conor Dooley wrote:
>> >> > On Wed, Mar 18, 2026 at 10:57:14PM +0530, Akhil R wrote:
>> >> > > Add the 'mipi-i3c-static-method' property mentioned in the MIPI I3C
>> >> > > Discovery and Configuration Specification [1] to specify which discovery
>> >> > > method an I3C device supports during bus initialization. The property is
>> >> > > a bitmap, where a bit value of 1 indicates support for that method, and 0
>> >> > > indicates lack of support.
>> >> > > Bit 0: SETDASA CCC (Direct)
>> >> > > Bit 1: SETAASA CCC (Broadcast)
>> >> > > Bit 2: Other CCC (vendor / standards extension)
>> >> > > All other bits are reserved.
>> >> > >
>> >> > > It is specifically needed when an I3C device requires SETAASA for the
>> >> > > address assignment. SETDASA will be supported by default if this property
>> >> > > is absent - which means for now the property just serves as a flag to
>> >> > > enable SETAASA, but keep the property as a bitmap to align with the
>> >> > > specifications.
>> >> > >
>> >> > > [1] https://www.mipi.org/specifications/disco
>> >> > >
>> >> > > Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
>> >> > > ---
>> >> > > .../devicetree/bindings/i3c/i3c.yaml | 30 ++++++++++++++++---
>> >> > > 1 file changed, 26 insertions(+), 4 deletions(-)
>> >> > >
>> >> > > diff --git a/Documentation/devicetree/bindings/i3c/i3c.yaml b/Documentation/devicetree/bindings/i3c/i3c.yaml
>> >> > > index e25fa72fd785..1705d90d4d79 100644
>> >> > > --- a/Documentation/devicetree/bindings/i3c/i3c.yaml
>> >> > > +++ b/Documentation/devicetree/bindings/i3c/i3c.yaml
>> >> > > @@ -31,10 +31,12 @@ properties:
>> >> > > described in the device tree, which in turn means we have to describe
>> >> > > I3C devices.
>> >> > >
>> >> > > - Another use case for describing an I3C device in the device tree is when
>> >> > > - this I3C device has a static I2C address and we want to assign it a
>> >> > > - specific I3C dynamic address before the DAA takes place (so that other
>> >> > > - devices on the bus can't take this dynamic address).
>> >> > > + Other use-cases for describing an I3C device in the device tree are:
>> >> > > + - When the I3C device has a static I2C address and we want to assign
>> >> > > + it a specific I3C dynamic address before the DAA takes place (so
>> >> > > + that other devices on the bus can't take this dynamic address).
>> >> > > + - When the I3C device requires SETAASA for its discovery and uses a
>> >> > > + pre-defined static address.
>> >> > >
>> >> > > "#size-cells":
>> >> > > const: 0
>> >> > > @@ -147,6 +149,26 @@ patternProperties:
>> >> > > through SETDASA. If static address is not present, this address is assigned
>> >> > > through SETNEWDA after assigning a temporary address via ENTDAA.
>> >> > >
>> >> > > + mipi-i3c-static-method:
>> >> > > + $ref: /schemas/types.yaml#/definitions/uint32
>> >> > > + minimum: 0x1
>> >> > > + maximum: 0xff
>> >> > > + default: 1
>> >> > > + description: |
>> >> > > + Bitmap describing which methods of Dynamic Address Assignment from a
>> >> > > + static address are supported by this I3C Target. A bit value of 1
>> >> > > + indicates support for that method, and 0 indicates lack of support.
>> >> >
>> >> > I really am not keen on properties that are bitmaps, why can't we just
>> >> > use the strings "setdasa", "setaasa" etc?
>> >>
>> >> If this comes from a specification, then I'd tend to just copy it rather
>> >> than invent our own thing. Obviously if is something structured
>> >> fundamentally different from how DT is designed, then we wouldn't. But
>> >> this is just a simple property.
>> >>
>> >
>> > The issue being that the specification is not public so it is difficult
>> > to take any decision.
>>
>> There is a public version available in the same link, but you would still
>> have to provide them a name and an email ID. The document will be sent to
>> the mail ID.
>>
>
> The public version only contains one property:
> mipi-disco-interface-revision
Could you check once if the below link works?
https://www.mipi.org/mipi-disco-for-i3c-download
Best Regards,
Akhil
^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: soc: renesas: Document MFIS IP core
From: Wolfram Sang @ 2026-03-27 11:42 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-renesas-soc, Marek Vasut, devicetree, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <20260326-magnetic-cautious-earthworm-aee7ec@quoll>
[-- Attachment #1: Type: text/plain, Size: 889 bytes --]
Hi Krzysztof,
> > + interrupts:
>
> Missing constraints.
Will add.
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + system-controller@189e0000 {
> > + compatible = "renesas,r8a78000-mfis";
>
> Since I expect next version, one more detail I forgot to ask last time:
>
> Use 4 spaces for example indentation.
Will do.
> > +#define MFIS_CHANNEL_TX (0 << 0)
> > +#define MFIS_CHANNEL_RX (1 << 0)
>
> No improvements and no answers to comments. Same review, drop, not a
> binding. If disagree, respond to v1 comments.
I think I did. I explained above in "changes since v1" that I decided to
keep it because of the existing users in upstream that Geert mentioned.
Also, you have been added to CC to get the driver this time because you
were missing that in v1. So, what exactly is missing?
Happy hacking,
Wolfram
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [GIT PULL] RISC-V T-HEAD Devicetrees for v7.1
From: Krzysztof Kozlowski @ 2026-03-27 11:42 UTC (permalink / raw)
To: Drew Fustini
Cc: soc, Arnd Bergmann, Alexandre Belloni, Linus Walleij,
Icenowy Zheng, Icenowy Zheng, Luca Ceresoli, Jisheng Zhang,
Guo Ren, Fu Wei, Conor Dooley, Michal Wilczynski, Yao Zi, Han Gao,
linux-riscv, devicetree, linux-kernel
In-Reply-To: <abcEKCNIA9wDgIcE@x1>
On Sun, Mar 15, 2026 at 12:10:32PM -0700, Drew Fustini wrote:
> The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
>
> Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git tags/thead-dt-for-v7.1
>
> for you to fetch changes up to 9c99a784d9117a192ebf779d4f72ebec435ada97:
>
> riscv: dts: thead: lichee-pi-4a: enable HDMI (2026-03-14 09:19:26 -0700)
Thanks, applied (dropping the SoB from tag - no code is in the tag).
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v2] dts: riscv: spacemit: k3: Add i2c nodes
From: Yixun Lan @ 2026-03-27 11:40 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: spacemit, devicetree, linux-riscv, linux-kernel, Yixun Lan
Populate all I2C devicetree nodes for SpacemiT K3 SoC. The controller of
i2c3 is reserved for secure domain, and not available from Linux. The
controller of i2c7 simply doesn't exist from hardware perspective, as
vendor directly name the i2c controller used for PMIC as i2c8.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
This series try to introduce a compatible string for the I2C
controller found in K3 SoC, and add all devicetree nodes .
---
Changes in v2:
- drop compatible binding patch which merged into i2c subsystem
- add comments about why no i2c3 and i2c7
- Link to v1: https://lore.kernel.org/r/20260325-02-k3-i2c-v1-0-78f29c83d9ac@kernel.org
---
arch/riscv/boot/dts/spacemit/k3.dtsi | 100 +++++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index a3a8ceddabec..38e6e212fbf2 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -438,6 +438,76 @@ soc: soc {
dma-noncoherent;
ranges;
+ i2c0: i2c@d4010800 {
+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
+ reg = <0x0 0xd4010800 0x0 0x38>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon_apbc CLK_APBC_TWSI0>,
+ <&syscon_apbc CLK_APBC_TWSI0_BUS>;
+ clock-names = "func", "bus";
+ clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_APBC_TWSI0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@d4011000 {
+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
+ reg = <0x0 0xd4011000 0x0 0x38>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon_apbc CLK_APBC_TWSI1>,
+ <&syscon_apbc CLK_APBC_TWSI1_BUS>;
+ clock-names = "func", "bus";
+ clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_APBC_TWSI1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@d4012000 {
+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
+ reg = <0x0 0xd4012000 0x0 0x38>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon_apbc CLK_APBC_TWSI2>,
+ <&syscon_apbc CLK_APBC_TWSI2_BUS>;
+ clock-names = "func", "bus";
+ clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_APBC_TWSI2>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@d4012800 {
+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
+ reg = <0x0 0xd4012800 0x0 0x38>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon_apbc CLK_APBC_TWSI4>,
+ <&syscon_apbc CLK_APBC_TWSI4_BUS>;
+ clock-names = "func", "bus";
+ clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_APBC_TWSI4>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@d4013800 {
+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
+ reg = <0x0 0xd4013800 0x0 0x38>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon_apbc CLK_APBC_TWSI5>,
+ <&syscon_apbc CLK_APBC_TWSI5_BUS>;
+ clock-names = "func", "bus";
+ clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_APBC_TWSI5>;
+ status = "disabled";
+ };
+
syscon_apbc: system-controller@d4015000 {
compatible = "spacemit,k3-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
@@ -564,6 +634,20 @@ uart9: serial@d4017800 {
status = "disabled";
};
+ i2c6: i2c@d4018800 {
+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
+ reg = <0x0 0xd4018800 0x0 0x38>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon_apbc CLK_APBC_TWSI6>,
+ <&syscon_apbc CLK_APBC_TWSI6_BUS>;
+ clock-names = "func", "bus";
+ clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_APBC_TWSI6>;
+ status = "disabled";
+ };
+
gpio: gpio@d4019000 {
compatible = "spacemit,k3-gpio";
reg = <0x0 0xd4019000 0x0 0x100>;
@@ -582,6 +666,20 @@ gpio: gpio@d4019000 {
<&pinctrl 3 0 96 32>;
};
+ i2c8: i2c@d401d800 {
+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
+ reg = <0x0 0xd401d800 0x0 0x38>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon_apbc CLK_APBC_TWSI8>,
+ <&syscon_apbc CLK_APBC_TWSI8_BUS>;
+ clock-names = "func", "bus";
+ clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_APBC_TWSI8>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl@d401e000 {
compatible = "spacemit,k3-pinctrl";
reg = <0x0 0xd401e000 0x0 0x1000>;
@@ -677,6 +775,8 @@ clint: timer@e081c000 {
<&cpu7_intc 3>, <&cpu7_intc 7>;
};
+ /* sec_i2c3: 0xf0614000, not available from Linux */
+
mimsic: interrupt-controller@f1000000 {
compatible = "spacemit,k3-imsics", "riscv,imsics";
reg = <0x0 0xf1000000 0x0 0x10000>;
---
base-commit: d72db7cc40947f208e77fbc6049f2da6ea6822f4
change-id: 20260311-02-k3-i2c-6ad52566a9a3
Best regards,
--
Yixun Lan <dlan@kernel.org>
^ permalink raw reply related
* Re: [PATCH v2 1/3] pinctrl: sunxi: a523: Remove unneeded IRQ remuxing flag
From: Chen-Yu Tsai @ 2026-03-27 11:38 UTC (permalink / raw)
To: Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec,
Samuel Holland, linux-gpio, devicetree, linux-arm-kernel,
linux-sunxi, linux-kernel
In-Reply-To: <20260327113006.3135663-2-andre.przywara@arm.com>
On Fri, Mar 27, 2026 at 7:30 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> The Allwinner A10 and H3 SoCs cannot read the state of a GPIO line when
> that line is muxed for IRQ triggering (muxval 6), but only if it's
> explicitly muxed for GPIO input (muxval 0). Other SoCs do not show this
> behaviour, so we added a optional workaround, triggered by a quirk bit,
> which triggers remuxing the pin when it's configured for IRQ, while we
> need to read its value.
>
> For some reasons this quirk flag was copied over to newer SoCs, even
> though they don't show this behaviour, and the GPIO data register
> reflects the true GPIO state even with a pin muxed to IRQ trigger.
>
> Remove the unneeded quirk from the A523 family, where it's definitely
> not needed (confirmed by experiments), and where it actually breaks,
> because the workaround is not compatible with the newer generation
> pinctrl IP used in that chip.
>
> Together with a DT change this fixes GPIO IRQ operation on the A523
> family of SoCs, as for instance used for the SD card detection.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Fixes: b8a51e95b376 ("pinctrl: sunxi: Add support for the secondary A523 GPIO ports")
Acked-by: Chen-Yu Tsai <wens@kernel.org>
> ---
> drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 1 -
> drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c | 1 -
> 2 files changed, 2 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c
> index 69cd2b4ebd7d..462aa1c4a5fa 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c
> @@ -26,7 +26,6 @@ static const u8 a523_r_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
> static struct sunxi_pinctrl_desc a523_r_pinctrl_data = {
> .irq_banks = ARRAY_SIZE(a523_r_irq_bank_map),
> .irq_bank_map = a523_r_irq_bank_map,
> - .irq_read_needs_mux = true,
> .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
> .pin_base = PL_BASE,
> };
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
> index 7d2308c37d29..b6f78f1f30ac 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
> @@ -26,7 +26,6 @@ static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
> static struct sunxi_pinctrl_desc a523_pinctrl_data = {
> .irq_banks = ARRAY_SIZE(a523_irq_bank_map),
> .irq_bank_map = a523_irq_bank_map,
> - .irq_read_needs_mux = true,
> .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
> };
>
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH v6] riscv: dts: spacemit: Add ethernet device for K3
From: Yixun Lan @ 2026-03-27 11:38 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Richard Cochran,
Inochi Amaoto
Cc: Yixun Lan, devicetree, linux-riscv, spacemit, linux-kernel,
netdev, Longbin Li
In-Reply-To: <20260326014617.1011732-1-inochiama@gmail.com>
On Thu, 26 Mar 2026 09:46:17 +0800, Inochi Amaoto wrote:
> Add all ethernet device nodes for K3 SoC.
>
>
Applied, thanks!
[1/1] riscv: dts: spacemit: Add ethernet device for K3
https://github.com/spacemit-com/linux/commit/74657a376960252e248089e518cfaaf813906989
Best regards,
--
Yixun Lan <dlan@kernel.org>
^ permalink raw reply
* Re: [PATCH v5 2/4] iio: adc: ad4691: add initial driver for AD4691 family
From: Andy Shevchenko @ 2026-03-27 11:36 UTC (permalink / raw)
To: radu.sabau
Cc: Lars-Peter Clausen, Michael Hennerich, Jonathan Cameron,
David Lechner, Nuno Sá, Andy Shevchenko, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Uwe Kleine-König,
Liam Girdwood, Mark Brown, Linus Walleij, Bartosz Golaszewski,
Philipp Zabel, Jonathan Corbet, Shuah Khan, linux-iio, devicetree,
linux-kernel, linux-pwm, linux-gpio, linux-doc
In-Reply-To: <20260327-ad4692-multichannel-sar-adc-driver-v5-2-11f789de47b8@analog.com>
On Fri, Mar 27, 2026 at 01:07:58PM +0200, Radu Sabau via B4 Relay wrote:
> Add support for the Analog Devices AD4691 family of high-speed,
> low-power multichannel SAR ADCs: AD4691 (16-ch, 500 kSPS),
> AD4692 (16-ch, 1 MSPS), AD4693 (8-ch, 500 kSPS) and
> AD4694 (8-ch, 1 MSPS).
>
> The driver implements a custom regmap layer over raw SPI to handle the
> device's mixed 1/2/3/4-byte register widths and uses the standard IIO
> read_raw/write_raw interface for single-channel reads.
>
> The chip idles in Autonomous Mode so that single-shot read_raw can use
> the internal oscillator without disturbing the hardware configuration.
>
> Three voltage supply domains are managed: avdd (required), vio, and a
> reference supply on either the REF pin (ref-supply, external buffer)
> or the REFIN pin (refin-supply, uses the on-chip reference buffer;
> REFBUF_EN is set accordingly). Hardware reset is performed via
> the reset controller framework; a software reset through SPI_CONFIG_A
> is used as fallback when no hardware reset is available.
>
> Accumulator channel masking for single-shot reads uses ACC_MASK_REG via
> an ADDR_DESCENDING SPI write, which covers both mask bytes in a single
> 16-bit transfer.
...
+ array_size.h
> +#include <linux/bitfield.h>
> +#include <linux/bitops.h>
> +#include <linux/cleanup.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
Hmm... Is it used? Or perhaps you need only
dev_printk.h
device/devres.h
?
> +#include <linux/err.h>
> +#include <linux/math.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> +#include <linux/spi/spi.h>
> +#include <linux/units.h>
> +#include <linux/unaligned.h>
...
> +/*
> + * Internal oscillator frequency table. Index is the OSC_FREQ_REG[3:0] value.
> + * Index 0 (1 MHz) is only valid for AD4692/AD4694; AD4691/AD4693 support
> + * up to 500 kHz and use index 1 as their highest valid rate.
> + */
> +static const int ad4691_osc_freqs[] = {
> + 1000000, /* 0x0: 1 MHz */
> + 500000, /* 0x1: 500 kHz */
> + 400000, /* 0x2: 400 kHz */
> + 250000, /* 0x3: 250 kHz */
> + 200000, /* 0x4: 200 kHz */
> + 167000, /* 0x5: 167 kHz */
> + 133000, /* 0x6: 133 kHz */
> + 125000, /* 0x7: 125 kHz */
> + 100000, /* 0x8: 100 kHz */
> + 50000, /* 0x9: 50 kHz */
> + 25000, /* 0xA: 25 kHz */
> + 12500, /* 0xB: 12.5 kHz */
> + 10000, /* 0xC: 10 kHz */
> + 5000, /* 0xD: 5 kHz */
> + 2500, /* 0xE: 2.5 kHz */
> + 1250, /* 0xF: 1.25 kHz */
Instead of comments, make the code self-commented and robust:
/* ...the top comment... */
static const int ad4691_osc_freqs_Hz[] = {
...
[0xD] = 5000,
[0xE] = 2500,
[0xF] = 1250,
};
I would even use unit multipliers in some cases, but it might make the whole
table inconsistent, dunno.
> +};
From this it will be visible that the table is in Hz and each value is properly
indexed, even shuffling won't break the code.
...
> +static int ad4691_set_sampling_freq(struct iio_dev *indio_dev, int freq)
> +{
> + struct ad4691_state *st = iio_priv(indio_dev);
> + unsigned int start = (st->info->max_rate == 1 * HZ_PER_MHZ) ? 0 : 1;
> + unsigned int i;
> +
> + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
> + if (IIO_DEV_ACQUIRE_FAILED(claim))
> + return -EBUSY;
> + for (i = start; i < ARRAY_SIZE(ad4691_osc_freqs); i++) {
for (unsigned int i = start; i < ARRAY_SIZE(ad4691_osc_freqs); i++) {
> + if (ad4691_osc_freqs[i] != freq)
> + continue;
> + return regmap_update_bits(st->regmap, AD4691_OSC_FREQ_REG,
> + AD4691_OSC_FREQ_MASK, i);
> + }
> +
> + return -EINVAL;
> +}
...
> +static int ad4691_read_avail(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + const int **vals, int *type,
> + int *length, long mask)
> +{
> + struct ad4691_state *st = iio_priv(indio_dev);
> + unsigned int start = (st->info->max_rate == 1 * HZ_PER_MHZ) ? 0 : 1;
Yeah, in the table it's written as 1000000... But as I mentioned above, using
unit multipliers _there_ maybe not a good idea.
> + switch (mask) {
> + case IIO_CHAN_INFO_SAMP_FREQ:
> + *vals = &ad4691_osc_freqs[start];
> + *type = IIO_VAL_INT;
> + *length = ARRAY_SIZE(ad4691_osc_freqs) - start;
> + return IIO_AVAIL_LIST;
> + default:
> + return -EINVAL;
> + }
> +}
...
> +static int ad4691_single_shot_read(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan, int *val)
> +{
> + struct ad4691_state *st = iio_priv(indio_dev);
> + unsigned int reg_val;
> + int ret;
> +
> + guard(mutex)(&st->lock);
> + /*
> + * Use AUTONOMOUS mode for single-shot reads.
> + */
One line?
> + ret = regmap_write(st->regmap, AD4691_STATE_RESET_REG,
> + AD4691_STATE_RESET_ALL);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG,
> + BIT(chan->channel));
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(st->regmap, AD4691_ACC_MASK_REG,
> + (u16)~BIT(chan->channel));
Why do you need casting?
> + if (ret)
> + return ret;
> + ret = regmap_read(st->regmap, AD4691_OSC_FREQ_REG, ®_val);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(st->regmap, AD4691_OSC_EN_REG, 1);
> + if (ret)
> + return ret;
> +
> + /*
> + * Wait for at least 2 internal oscillator periods for the
> + * conversion to complete.
> + */
> + fsleep(DIV_ROUND_UP(2 * USEC_PER_SEC, ad4691_osc_freqs[FIELD_GET(AD4691_OSC_FREQ_MASK, reg_val)]));
Way too long line. Use temporary variables for that to make it easier to parse.
Also add a (short) comment on how the OSC periods are being calculated.
> + ret = regmap_write(st->regmap, AD4691_OSC_EN_REG, 0);
> + if (ret)
> + return ret;
> +
> + ret = regmap_read(st->regmap, AD4691_AVG_IN(chan->channel), ®_val);
> + if (ret)
> + return ret;
> +
> + *val = reg_val;
> +
> + ret = regmap_write(st->regmap, AD4691_STATE_RESET_REG, AD4691_STATE_RESET_ALL);
> + if (ret)
> + return ret;
> +
> + return IIO_VAL_INT;
> +}
...
> + ret = devm_regulator_get_enable(dev, "avdd");
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to get and enable AVDD\n");
> +
> + ret = devm_regulator_get_enable(dev, "vio");
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to get and enable VIO\n");
Can they be united to a bulk?
...
> +static int ad4691_reset(struct ad4691_state *st)
> +{
> + struct device *dev = regmap_get_device(st->regmap);
> + struct reset_control *rst;
> +
> + rst = devm_reset_control_get_optional_exclusive(dev, NULL);
> + if (IS_ERR(rst))
> + return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset\n");
> +
> + if (rst) {
> + /*
> + * The GPIO is already asserted by reset_gpio_probe (GPIOD_OUT_HIGH).
> + * Wait for the reset pulse width required by the chip. See datasheet Table 5.
Too long, try to wrap around 80, and drop unneeded (confusing?) details.
> + */
/*
* The GPIO is already asserted by reset_gpio_probe().
* Wait for the reset pulse width required by the chip.
* See datasheet Table 5.
*/
> + fsleep(300);
> + return reset_control_deassert(rst);
> + }
> +
> + /* No hardware reset available, fall back to software reset. */
> + return regmap_write(st->regmap, AD4691_SPI_CONFIG_A_REG,
> + AD4691_SW_RESET);
> +}
...
> + ret = regmap_update_bits(st->regmap, AD4691_REF_CTRL,
> + AD4691_REF_CTRL_MASK | AD4691_REFBUF_EN,
> + FIELD_PREP(AD4691_REF_CTRL_MASK, ref_val) |
> + (st->refbuf_en ? AD4691_REFBUF_EN : 0));
With temporary variable it will become something like
/* ...Comment on what is this... */
val = FIELD_PREP(...);
FIELD_MODIFY(...);
ret = regmap_update_bits(st->regmap, AD4691_REF_CTRL,
AD4691_REF_CTRL_MASK | AD4691_REFBUF_EN, val);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to write REF_CTRL\n");
...
> + /*
> + * Set the internal oscillator to the highest rate this chip supports.
> + * Index 0 (1 MHz) exceeds the 500 kHz max of AD4691/AD4693, so those
> + * chips start at index 1 (500 kHz).
> + */
> + ret = regmap_update_bits(st->regmap, AD4691_OSC_FREQ_REG,
> + AD4691_OSC_FREQ_MASK,
> + (st->info->max_rate == 1 * HZ_PER_MHZ) ? 0 : 1);
_assign_bits?
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to write OSC_FREQ\n");
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
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