* [PATCH 03/16] dt-bindings: rng: Rename the title of the EIP-76 file
From: Miquel Raynal (Schneider Electric) @ 2026-03-27 20:09 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Gleixner, Olivia Mackall, Herbert Xu,
Jayesh Choudhary, David S. Miller, Christian Marangi,
Antoine Tenart, Geert Uytterhoeven, Magnus Damm
Cc: Thomas Petazzoni, Pascal EBERHARD, Wolfram Sang, linux-clk,
devicetree, linux-kernel, linux-crypto, linux-renesas-soc,
Miquel Raynal (Schneider Electric)
In-Reply-To: <20260327-schneider-v7-0-rc1-crypto-v1-0-5e6ff7853994@bootlin.com>
Be a little more precise in the title by giving the family name and the
own name of the hardware block. Despite the original compatibles, this
file describes a SafeXcel EIP-76 hardware random number generator.
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
---
Documentation/devicetree/bindings/rng/inside-secure,safexcel-eip76.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/rng/inside-secure,safexcel-eip76.yaml b/Documentation/devicetree/bindings/rng/inside-secure,safexcel-eip76.yaml
index f501fc7691c6..92d906998211 100644
--- a/Documentation/devicetree/bindings/rng/inside-secure,safexcel-eip76.yaml
+++ b/Documentation/devicetree/bindings/rng/inside-secure,safexcel-eip76.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/rng/inside-secure,safexcel-eip76.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Inside-Secure HWRNG Module
+title: Inside-Secure SafeXcel EIP-76 HWRNG Module
maintainers:
- Jayesh Choudhary <j-choudhary@ti.com>
--
2.51.1
^ permalink raw reply related
* [PATCH 02/16] dt-bindings: interrupt-controller: Describe EIP-201 AIC
From: Miquel Raynal (Schneider Electric) @ 2026-03-27 20:09 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Gleixner, Olivia Mackall, Herbert Xu,
Jayesh Choudhary, David S. Miller, Christian Marangi,
Antoine Tenart, Geert Uytterhoeven, Magnus Damm
Cc: Thomas Petazzoni, Pascal EBERHARD, Wolfram Sang, linux-clk,
devicetree, linux-kernel, linux-crypto, linux-renesas-soc,
Miquel Raynal (Schneider Electric)
In-Reply-To: <20260327-schneider-v7-0-rc1-crypto-v1-0-5e6ff7853994@bootlin.com>
The EIP-201 Advanced Interrupt Controller is part of a bigger container
block from Inside Secure nicely named EIP-150. It typically takes one
clock from the EIP-150 and offers basic controls through a few simple
registers.
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
---
.../inside-secure,safexcel-eip201.yaml | 41 ++++++++++++++++++++++
.../inside-secure,safexcel-eip201.h | 14 ++++++++
2 files changed, 55 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/inside-secure,safexcel-eip201.yaml b/Documentation/devicetree/bindings/interrupt-controller/inside-secure,safexcel-eip201.yaml
new file mode 100644
index 000000000000..ddad8e5eab96
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/inside-secure,safexcel-eip201.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/inside-secure,safexcel-eip201.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Inside-Secure SafeXcel EIP-201 Advanced Interrupt Controller
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ const: inside-secure,safexcel-eip201
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - interrupt-controller
+ - "#interrupt-cells"
+
+unevaluatedProperties: false
diff --git a/include/dt-bindings/interrupt-controller/inside-secure,safexcel-eip201.h b/include/dt-bindings/interrupt-controller/inside-secure,safexcel-eip201.h
new file mode 100644
index 000000000000..ead73bd96296
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/inside-secure,safexcel-eip201.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+
+#ifndef _DT_BINDINGS_IRQ_SAFEXCEL_EIP201_AIC_H
+#define _DT_BINDINGS_IRQ_SAFEXCEL_EIP201_AIC_H
+
+#define AIC_PKA_INT0 0
+#define AIC_PKA_INT1 1
+#define AIC_PKA_INT2 2
+#define AIC_TRNG_INT 3
+#define AIC_RESERVED 4
+#define AIC_SL_ERR_INT 5
+#define AIC_PROTECTION_INT 6
+
+#endif
--
2.51.1
^ permalink raw reply related
* [PATCH 01/16] dt-bindings: clock: Introduce nexus nodes
From: Miquel Raynal (Schneider Electric) @ 2026-03-27 20:09 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Gleixner, Olivia Mackall, Herbert Xu,
Jayesh Choudhary, David S. Miller, Christian Marangi,
Antoine Tenart, Geert Uytterhoeven, Magnus Damm
Cc: Thomas Petazzoni, Pascal EBERHARD, Wolfram Sang, linux-clk,
devicetree, linux-kernel, linux-crypto, linux-renesas-soc,
Miquel Raynal (Schneider Electric)
In-Reply-To: <20260327-schneider-v7-0-rc1-crypto-v1-0-5e6ff7853994@bootlin.com>
Hardware containers can just decouple external resources like clock
without any more control. Nexus nodes already exist for PWM and GPIOs,
add a binding to allow them for clocks as well.
No examples are given, the file is litteraly a copy-paste from Hervé
Codina's work on PWM Nexus nodes, hence we just point to the examples
there which already illustrate very clearly the concept of the various
properties.
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
---
.../bindings/clock/clock-nexus-node.yaml | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/clock-nexus-node.yaml b/Documentation/devicetree/bindings/clock/clock-nexus-node.yaml
new file mode 100644
index 000000000000..f07e2972e8aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clock-nexus-node.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/clock-nexus-node.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock Nexus
+
+description: >
+ A nexus node allows to remap a phandle list in a consumer node through a
+ container or a connector node in a generic way. With this remapping,
+ the consumer node needs to know only about the nexus node. Resources
+ behind the nexus node are decoupled by the nexus node itself.
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+
+select: true
+
+properties:
+ '#clock-cells': true
+
+ clock-map:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+
+ clock-map-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ clock-map-pass-thru:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+dependentRequired:
+ clock-map: ['#clock-cells']
+ clock-map-mask: [ clock-map ]
+ clock-map-pass-thru: [ clock-map ]
+
+additionalProperties: true
+
+# See the original pwm-nexus-node.yaml description for examples
--
2.51.1
^ permalink raw reply related
* [PATCH 00/16] Add support for Inside-Secure EIP-150 crypto block
From: Miquel Raynal (Schneider Electric) @ 2026-03-27 20:09 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Gleixner, Olivia Mackall, Herbert Xu,
Jayesh Choudhary, David S. Miller, Christian Marangi,
Antoine Tenart, Geert Uytterhoeven, Magnus Damm
Cc: Thomas Petazzoni, Pascal EBERHARD, Wolfram Sang, linux-clk,
devicetree, linux-kernel, linux-crypto, linux-renesas-soc,
Miquel Raynal (Schneider Electric), Herve Codina
Hello,
This is a series adding support for the EIP-150, which is a crypto block
containing:
- a public key accelerator
- a random number generator
- an interrupt controller
The series is a bit long but every subsystem may take its own share
independently. I might want to split it into several chunks in the
future if it expands but at as for now, here is the full picture.
For instance, the clock part has grown due to the inputs From Stephan
Boyd (addition of Kunit tests + a couple of misc preliminary changes).
Link: https://lore.kernel.org/linux-clk/20260129201003.288605-1-miquel.raynal@bootlin.com/
Regarding the big engine, the EIP-28 Public Key Accelerator, it
currently only supports RSA, but more algorithms might be added
later. The hardware supports (EC)DSA and (EC)DH. It also requires a
firmware.
The very last patch adds the block in the Renesas RZ/N1D DTSI, as this
is the platform I am using this hardware one.
Thanks,
Miquèl
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
---
Miquel Raynal (Schneider Electric) (16):
dt-bindings: clock: Introduce nexus nodes
dt-bindings: interrupt-controller: Describe EIP-201 AIC
dt-bindings: rng: Rename the title of the EIP-76 file
dt-bindings: crypto: eip28: Describe EIP-28 PKA
dt-bindings: bus: eip150: Describe the EIP-150 container node
clk: tests: Add clk_parse_clkspec() Kunit testing
clk: tests: Add Kunit testing for of_clk_get_parent_name()
clk: Improve a couple of comments
clk: Use the generic OF phandle parsing in only one place
clk: Add support for clock nexus dt bindings
clk: tests: Add Kunit testing for nexus nodes
irqchip/eip201-aic: Add support for Safexcel EIP-201 AIC
hwrng: omap: Enable on Renesas RZ/N1D
crypto: Group Inside-Secure IPs together and align the titles
crypto: eip28: Add support for SafeXcel EIP-28 Public Key Accelerator
ARM: dts: renesas: r9a06g032: Describe the EIP-150 block
.../bus/inside-secure,safexcel-eip150.yaml | 58 ++
.../bindings/clock/clock-nexus-node.yaml | 39 ++
.../crypto/inside-secure,safexcel-eip28.yaml | 31 +
.../inside-secure,safexcel-eip201.yaml | 41 ++
.../bindings/rng/inside-secure,safexcel-eip76.yaml | 2 +-
arch/arm/boot/dts/renesas/r9a06g032.dtsi | 42 ++
drivers/char/hw_random/Kconfig | 2 +-
drivers/clk/Makefile | 1 +
drivers/clk/clk.c | 12 +-
drivers/clk/clk_test.c | 154 +++++
drivers/clk/kunit_clk_parse_clkspec.dtso | 31 +
drivers/crypto/Kconfig | 55 +-
drivers/crypto/inside-secure/Makefile | 1 +
drivers/crypto/inside-secure/eip28.c | 760 +++++++++++++++++++++
drivers/crypto/inside-secure/eip93/Kconfig | 2 +-
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-eip201-aic.c | 221 ++++++
.../inside-secure,safexcel-eip201.h | 14 +
19 files changed, 1444 insertions(+), 31 deletions(-)
---
base-commit: f6ad621bcf627fe4719cbf97c1d3c9366cc49eff
change-id: 20260327-schneider-v7-0-rc1-crypto-58cd846ddb81
Best regards,
--
Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
^ permalink raw reply
* Re: Warning from free_reserved_area() in next-20260325+
From: Bert Karwatzki @ 2026-03-27 19:54 UTC (permalink / raw)
To: Mike Rapoport
Cc: linux-kernel, spasswolf, Liam.Howlett, akpm, andreas, ardb, bp,
brauner, catalin.marinas, chleroy, dave.hansen, davem, david,
devicetree, dvyukov, elver, glider, hannes, hpa, ilias.apalodimas,
iommu, jack, jackmanb, kasan-dev, linux-arm-kernel, linux-efi,
linux-fsdevel, linux-mm, linux-trace-kernel, linuxppc-dev,
lorenzo.stoakes, m.szyprowski, maddy, mhiramat, mhocko, mingo,
mpe, npiggin, robh, robin.murphy, saravanak, sparclinux, surenb,
tglx, vbabka, viro, will, x86, ziy
In-Reply-To: <aca6blFFWskxAcAr@kernel.org>
Am Freitag, dem 27.03.2026 um 20:12 +0300 schrieb Mike Rapoport:
> Hi Bert,
>
> On Fri, Mar 27, 2026 at 03:01:08PM +0100, Bert Karwatzki wrote:
> > Starting with linux next-20260325 I see the following warning early in the
> > boot process of a machine running debian stable (trixie) (except for the kernel):
>
> Thanks for the report!
>
> > [ 0.027118] [ T0] ------------[ cut here ]------------
> > [ 0.027118] [ T0] Cannot free reserved memory because of deferred initialization of the memory map
> > [ 0.027119] [ T0] WARNING: mm/memblock.c:904 at __free_reserved_area+0xa9/0xc0, CPU#0: swapper/0/0
> > [ 0.027122] [ T0] Modules linked in:
> > [ 0.027123] [ T0] CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 7.0.0-rc5-next-20260326-master #385 PREEMPT_RT
> > [ 0.027125] [ T0] Hardware name: ASUS System Product Name/ROG STRIX B850-F GAMING WIFI, BIOS 1627 02/05/2026
> > [ 0.027125] [ T0] RIP: 0010:__free_reserved_area+0xa9/0xc0
> > [ 0.027126] [ T0] Code: 48 89 df 48 89 ee e8 06 fe ff ff 48 89 c3 48 39 e8 72 a0 5b 4c 89 e8 5d 41 5c 41 5d 41 5e c3 cc cc cc cc 48 8d 3d 97 c2 c6 00 <67> 48 0f b9 3a 45 31 ed eb df 66 66 2e 0f 1f 84 00 00 00 00 00 66
> > [ 0.027127] [ T0] RSP: 0000:ffffffff9b203e98 EFLAGS: 00010202
> > [ 0.027128] [ T0] RAX: 0000000e91c00001 RBX: ffffffff9b100c0f RCX: 0000000080000001
> > [ 0.027128] [ T0] RDX: 00000000000000cc RSI: 0000000e2d42d000 RDI: ffffffff9b32ef60
> > [ 0.027128] [ T0] RBP: ffff9eeafdd6fbc0 R08: 0000000000000000 R09: 0000000000000001
> > [ 0.027129] [ T0] R10: 0000000000001000 R11: 8000000000000163 R12: 000000000000006f
> > [ 0.027129] [ T0] R13: 0000000000000000 R14: 0000000000000045 R15: 000000005c8a1000
> > [ 0.027129] [ T0] FS: 0000000000000000(0000) GS:ffff9eeb21c05000(0000) knlGS:0000000000000000
> > [ 0.027130] [ T0] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> > [ 0.027130] [ T0] CR2: ffff9ee8ad801000 CR3: 0000000e2ce1e000 CR4: 0000000000f50ef0
> > [ 0.027131] [ T0] PKRU: 55555554
> > [ 0.027131] [ T0] Call Trace:
> > [ 0.027132] [ T0] <TASK>
> > [ 0.027132] [ T0] free_reserved_area+0x89/0xd0
> > [ 0.027133] [ T0] alternative_instructions+0xee/0x110
> > [ 0.027136] [ T0] arch_cpu_finalize_init+0x10f/0x160
> > [ 0.027138] [ T0] start_kernel+0x686/0x710
> > [ 0.027140] [ T0] x86_64_start_reservations+0x24/0x30
> > [ 0.027141] [ T0] x86_64_start_kernel+0xd4/0xe0
> > [ 0.027142] [ T0] common_startup_64+0x13e/0x141
> > [ 0.027143] [ T0] </TASK>
> > [ 0.027144] [ T0] ---[ end trace 0000000000000000 ]---
>
> Does this patch fix it for you?
>
> diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
> index e87da25d1236..62936a3bde19 100644
> --- a/arch/x86/kernel/alternative.c
> +++ b/arch/x86/kernel/alternative.c
> @@ -2448,19 +2448,31 @@ void __init alternative_instructions(void)
> __smp_locks, __smp_locks_end,
> _text, _etext);
> }
> +#endif
>
> + restart_nmi();
> + alternatives_patched = 1;
> +
> + alt_reloc_selftest();
> +}
> +
> +#ifdef CONFIG_SMP
> +/*
> + * With CONFIG_DEFERRED_STRUCT_PAGE_INIT enabled we can free_init_pages() only
> + * after the deferred initialization of the memory map is complete.
> + */
> +static int __init free_smp_locks(void)
> +{
> if (!uniproc_patched || num_possible_cpus() == 1) {
> free_init_pages("SMP alternatives",
> (unsigned long)__smp_locks,
> (unsigned long)__smp_locks_end);
> }
> -#endif
>
> - restart_nmi();
> - alternatives_patched = 1;
> -
> - alt_reloc_selftest();
> + return 0;
> }
> +arch_initcall(free_smp_locks);
> +#endif
>
> /**
> * text_poke_early - Update instructions on a live kernel at boot time
>
> > Bert Karwatzki
Yes, your patch fixes the issue in next-20260326.
Tested-By: Bert Karwatzki <spasswolf@web.de>
Bert Karwatzki
^ permalink raw reply
* Re: [PATCH v4 0/4] Add DSI display support for SC8280XP
From: Dmitry Baryshkov @ 2026-03-27 19:47 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Krishna Manikandan, Jonathan Marek, Pengyu Luo
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Tianyu Gao, White Lewis
In-Reply-To: <20260308064835.479356-1-mitltlatltl@gmail.com>
On Sun, 08 Mar 2026 14:48:31 +0800, Pengyu Luo wrote:
> Add DSI display support for SC8280XP.
Applied to msm-next, thanks!
[1/4] dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP
https://gitlab.freedesktop.org/lumag/msm/-/commit/59f6bdf913dd
[2/4] dt-bindings: display/msm: dsi-controller-main: Add SC8280XP
https://gitlab.freedesktop.org/lumag/msm/-/commit/1607c084b18f
[3/4] dt-bindings: display: msm: Document DSI controller and DSI PHY on SC8280XP
https://gitlab.freedesktop.org/lumag/msm/-/commit/6113aaf7a5ce
Best regards,
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 0/8] drm/msm: Add Qualcomm Eliza SoC support
From: Dmitry Baryshkov @ 2026-03-27 19:47 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Jonathan Marek,
Krishna Manikandan, Neil Armstrong, Bjorn Andersson,
Konrad Dybcio, Krzysztof Kozlowski
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Krzysztof Kozlowski
In-Reply-To: <20260304-drm-display-eliza-v2-0-ea0579f62358@oss.qualcomm.com>
On Wed, 04 Mar 2026 13:58:42 +0100, Krzysztof Kozlowski wrote:
> Changes in v2:
> - Add Rb tags.
> - Changes after review - changelog per individual patches
> - Link to v1: https://patch.msgid.link/20260303-drm-display-eliza-v1-0-814121dbb2bf@oss.qualcomm.com
>
> The MDSS on Eliza SoC is evolution of one in SM8750, with several blocks
> removed and added HDMI.
>
> [...]
Applied to msm-next, thanks!
[1/8] dt-bindings: display/msm: dp-controller: Add Eliza SoC
https://gitlab.freedesktop.org/lumag/msm/-/commit/069a1db1904f
[2/8] dt-bindings: display/msm: dsi-phy-7nm: Add Eliza SoC
https://gitlab.freedesktop.org/lumag/msm/-/commit/4a0172e8a4d9
[3/8] dt-bindings: display/msm: dsi-controller-main: Add Eliza SoC
https://gitlab.freedesktop.org/lumag/msm/-/commit/c01cca40073e
[4/8] dt-bindings: display/msm: qcom,sm8650-dpu: Add Eliza SoC
https://gitlab.freedesktop.org/lumag/msm/-/commit/df761873418a
[5/8] dt-bindings: display/msm: qcom,eliza-mdss: Add Eliza SoC
https://gitlab.freedesktop.org/lumag/msm/-/commit/0a40e2e91b21
[7/8] drm/msm/dpu: Add support for Eliza SoC
https://gitlab.freedesktop.org/lumag/msm/-/commit/0eb707bbc7fc
[8/8] drm/msm/mdss: Add support for Eliza SoC
https://gitlab.freedesktop.org/lumag/msm/-/commit/3e64e6959d8b
Best regards,
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH 11/11] arm64: dts: renesas: r9a09g087: add MTU3 support
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com>
The Renesas RZ/N2H (R9A09G087) SoC has an MTU3 block.
Add support for it.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 68 ++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index f697e9698ed3..c64b532f3d23 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -1119,6 +1119,74 @@ gic: interrupt-controller@83000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+ mtu3: timer@90001200 {
+ compatible = "renesas,r9a09g087-mtu3",
+ "renesas,rz-mtu3";
+ reg = <0 0x90001200 0 0xb00>;
+ interrupts = <GIC_SPI 420 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 421 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 422 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 423 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 424 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 425 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 429 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 430 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 441 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 444 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 445 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 446 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 447 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 450 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 453 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 454 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 455 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 458 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
+ "tciv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tciv1", "tciu1",
+ "tgia2", "tgib2", "tciv2", "tciu2",
+ "tgia3", "tgib3", "tgic3", "tgid3",
+ "tciv3",
+ "tgia4", "tgib4", "tgic4", "tgid4",
+ "tciv4",
+ "tgiu5", "tgiv5", "tgiw5",
+ "tgia6", "tgib6", "tgic6", "tgid6",
+ "tciv6",
+ "tgia7", "tgib7", "tgic7", "tgid7",
+ "tciv7",
+ "tgia8", "tgib8", "tgic8", "tgid8",
+ "tciv8";
+ clocks = <&cpg CPG_MOD 200>;
+ power-domains = <&cpg>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
adc0: adc@90014000 {
compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc";
reg = <0 0x90014000 0 0x400>;
--
2.53.0
^ permalink raw reply related
* [PATCH 10/11] arm64: dts: renesas: r9a09g077: add MTU3 support
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com>
The Renesas RZ/T2H (R9A09G077) SoC has an MTU3 block.
Add support for it.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 68 ++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 3761551c9647..fe5d206d4def 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -1116,6 +1116,74 @@ gic: interrupt-controller@83000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+ mtu3: timer@90001200 {
+ compatible = "renesas,r9a09g077-mtu3",
+ "renesas,rz-mtu3";
+ reg = <0 0x90001200 0 0xb00>;
+ interrupts = <GIC_SPI 420 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 421 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 422 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 423 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 424 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 425 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 429 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 430 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 441 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 444 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 445 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 446 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 447 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 450 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 453 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 454 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 455 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 458 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
+ "tciv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tciv1", "tciu1",
+ "tgia2", "tgib2", "tciv2", "tciu2",
+ "tgia3", "tgib3", "tgic3", "tgid3",
+ "tciv3",
+ "tgia4", "tgib4", "tgic4", "tgid4",
+ "tciv4",
+ "tgiu5", "tgiv5", "tgiw5",
+ "tgia6", "tgib6", "tgic6", "tgid6",
+ "tciv6",
+ "tgia7", "tgib7", "tgic7", "tgid7",
+ "tciv7",
+ "tgia8", "tgib8", "tgic8", "tgid8",
+ "tciv8";
+ clocks = <&cpg CPG_MOD 200>;
+ power-domains = <&cpg>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
adc0: adc@90014000 {
compatible = "renesas,r9a09g077-adc";
reg = <0 0x90014000 0 0x400>;
--
2.53.0
^ permalink raw reply related
* [PATCH 09/11] arm64: dts: renesas: r9a07g0{43,44,54}: remove TCIU8 interrupt from MTU3
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com>
Based on the following pages in the User Manuals, the MTU3 block does
not have a TCIU8 interrupt, only a TCIV8 interrupt, as the row where
TCIU8 should have been is marked as reserved, and the GIC SPI numbers
stop at 212.
* Page 486, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2UL
Rev.1.40 User Manual
* Page 363, Table 8.2 Interrupt Mapping (6/13) in the Renesas RZ/Five
Rev.1.30 User Manual
* Page 528, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2L
and RZ/G2LC Rev.1.50 User Manual
* Page 540, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/V2L
Rev.1.50 User Manual
Remove the TCIU8 interrupt. This does not cause any breakage as the
driver does not make use of the interrupts.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 5 ++---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 ++---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 5 ++---
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 593c66b27ad1..7bc37e1015a4 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -120,8 +120,7 @@ mtu3: timer@10001200 {
<SOC_PERIPHERAL_IRQ(209) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(210) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(211) IRQ_TYPE_EDGE_RISING>,
- <SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>,
- <SOC_PERIPHERAL_IRQ(213) IRQ_TYPE_EDGE_RISING>;
+ <SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
@@ -136,7 +135,7 @@ mtu3: timer@10001200 {
"tgia7", "tgib7", "tgic7", "tgid7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
- "tciv8", "tciu8";
+ "tciv8";
clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 29273da81995..799a974c4dba 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -220,8 +220,7 @@ mtu3: timer@10001200 {
<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
@@ -236,7 +235,7 @@ mtu3: timer@10001200 {
"tgia7", "tgib7", "tgic7", "tgid7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
- "tciv8", "tciu8";
+ "tciv8";
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 0dee48c4f1e4..0dc4c3c8c06b 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -220,8 +220,7 @@ mtu3: timer@10001200 {
<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
@@ -236,7 +235,7 @@ mtu3: timer@10001200 {
"tgia7", "tgib7", "tgic7", "tgid7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
- "tciv8", "tciu8";
+ "tciv8";
clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
--
2.53.0
^ permalink raw reply related
* [PATCH 08/11] dt-bindings: timer: renesas,rz-mtu3: document RZ/{T2H,N2H}
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com>
Compared to the previously supported SoCs, the Renesas RZ/T2H and RZ/N2H
SoCs do not have a reset line.
Add a new conditional only matching RZ/T2H and RZ/N2H which disables the
resets property.
Document RZ/T2H and RZ/N2H, and use the generic compatible as a
fallback, as functionality is the same.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../devicetree/bindings/timer/renesas,rz-mtu3.yaml | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
index 4623f6cddaf0..410951ca53f8 100644
--- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
+++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
@@ -112,6 +112,8 @@ properties:
- renesas,r9a07g043-mtu3 # RZ/{G2UL,Five}
- renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
- renesas,r9a07g054-mtu3 # RZ/V2L
+ - renesas,r9a09g077-mtu3 # RZ/T2H
+ - renesas,r9a09g087-mtu3 # RZ/N2H
- const: renesas,rz-mtu3
reg:
@@ -245,6 +247,17 @@ allOf:
required:
- resets
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a09g077-mtu3
+ - renesas,r9a09g087-mtu3
+ then:
+ properties:
+ resets: false
+
additionalProperties: false
examples:
--
2.53.0
^ permalink raw reply related
* [PATCH 07/11] dt-bindings: timer: renesas,rz-mtu3: move required resets to conditional
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com>
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs do not have a
reset line for the MTU3 block.
Prepare for adding support for them by moving the required reset into a
conditional matching all compatibles except the fallback one.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../devicetree/bindings/timer/renesas,rz-mtu3.yaml | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
index 00cd5cbcf6e9..4623f6cddaf0 100644
--- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
+++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
@@ -231,7 +231,19 @@ required:
- interrupt-names
- clocks
- power-domains
- - resets
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a07g043-mtu3
+ - renesas,r9a07g044-mtu3
+ - renesas,r9a07g054-mtu3
+ then:
+ required:
+ - resets
additionalProperties: false
--
2.53.0
^ permalink raw reply related
* [PATCH 06/11] dt-bindings: timer: renesas,rz-mtu3: remove TCIU8 interrupt
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com>
Based on the following pages in the User Manuals, the MTU3 block does
not have a TCIU8 interrupt, only a TCIV8 interrupt, as the row where
TCIU8 should have been is marked as reserved, and the GIC SPI numbers
stop at 212.
* Page 486, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2UL
Rev.1.40 User Manual
* Page 363, Table 8.2 Interrupt Mapping (6/13) in the Renesas RZ/Five
Rev.1.30 User Manual
* Page 528, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2L
and RZ/G2LC Rev.1.50 User Manual
* Page 540, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/V2L
Rev.1.50 User Manual
Remove the TCIU8 interrupt.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../devicetree/bindings/timer/renesas,rz-mtu3.yaml | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
index 3ad10c5b66ba..00cd5cbcf6e9 100644
--- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
+++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
@@ -162,7 +162,6 @@ properties:
- description: MTU8.TGRC input capture/compare match
- description: MTU8.TGRD input capture/compare match
- description: MTU8.TCNT overflow
- - description: MTU8.TCNT underflow
interrupt-names:
items:
@@ -209,7 +208,6 @@ properties:
- const: tgic8
- const: tgid8
- const: tciv8
- - const: tciu8
clocks:
maxItems: 1
@@ -287,8 +285,7 @@ examples:
<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0",
"tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
@@ -298,7 +295,7 @@ examples:
"tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6", "tciv6",
"tgia7", "tgib7", "tgic7", "tgid7", "tciv7",
- "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8";
+ "tgia8", "tgib8", "tgic8", "tgid8", "tciv8";
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
--
2.53.0
^ permalink raw reply related
* [PATCH 05/11] mfd: rz-mtu3: make reset optional
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com>
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs do not have a
reset line for the MTU3 block.
Prepare for them by making it optional.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/mfd/rz-mtu3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mfd/rz-mtu3.c b/drivers/mfd/rz-mtu3.c
index 37d12030e069..689dbb181d30 100644
--- a/drivers/mfd/rz-mtu3.c
+++ b/drivers/mfd/rz-mtu3.c
@@ -331,7 +331,7 @@ static int rz_mtu3_probe(struct platform_device *pdev)
if (IS_ERR(priv->mmio))
return PTR_ERR(priv->mmio);
- rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);
+ rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
if (IS_ERR(rstc))
return PTR_ERR(rstc);
--
2.53.0
^ permalink raw reply related
* [PATCH 04/11] mfd: rz-mtu3: store &pdev->dev in local variable
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com>
&pdev->dev is accessed multiple times during probe. Store it in a local
variable and use that to simplify the code.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/mfd/rz-mtu3.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/mfd/rz-mtu3.c b/drivers/mfd/rz-mtu3.c
index 3be6f6c900b8..37d12030e069 100644
--- a/drivers/mfd/rz-mtu3.c
+++ b/drivers/mfd/rz-mtu3.c
@@ -311,16 +311,17 @@ static const struct mfd_cell rz_mtu3_devs[] = {
static int rz_mtu3_probe(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
struct reset_control *rstc;
struct rz_mtu3_priv *priv;
struct rz_mtu3 *ddata;
unsigned int i;
- ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
+ ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
- ddata->priv_data = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ ddata->priv_data = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!ddata->priv_data)
return -ENOMEM;
@@ -330,11 +331,11 @@ static int rz_mtu3_probe(struct platform_device *pdev)
if (IS_ERR(priv->mmio))
return PTR_ERR(priv->mmio);
- rstc = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL);
+ rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);
if (IS_ERR(rstc))
return PTR_ERR(rstc);
- ddata->clk = devm_clk_get(&pdev->dev, NULL);
+ ddata->clk = devm_clk_get(dev, NULL);
if (IS_ERR(ddata->clk))
return PTR_ERR(ddata->clk);
@@ -347,7 +348,7 @@ static int rz_mtu3_probe(struct platform_device *pdev)
mutex_init(&ddata->channels[i].lock);
}
- return devm_mfd_add_devices(&pdev->dev, 0, rz_mtu3_devs,
+ return devm_mfd_add_devices(dev, 0, rz_mtu3_devs,
ARRAY_SIZE(rz_mtu3_devs), NULL, 0, NULL);
}
--
2.53.0
^ permalink raw reply related
* [PATCH 03/11] mfd: rz-mtu3: use device-managed mfd_add_devices()
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com>
Replace mfd_add_devices() and the custom cleanup action with
devm_mfd_add_devices().
Remove the ret variable as it is now unused.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/mfd/rz-mtu3.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/drivers/mfd/rz-mtu3.c b/drivers/mfd/rz-mtu3.c
index 6b9c6831dffa..3be6f6c900b8 100644
--- a/drivers/mfd/rz-mtu3.c
+++ b/drivers/mfd/rz-mtu3.c
@@ -300,11 +300,6 @@ void rz_mtu3_disable(struct rz_mtu3_channel *ch)
}
EXPORT_SYMBOL_GPL(rz_mtu3_disable);
-static void rz_mtu3_mfd_remove(void *data)
-{
- mfd_remove_devices(data);
-}
-
static const struct mfd_cell rz_mtu3_devs[] = {
{
.name = "rz-mtu3-counter",
@@ -320,7 +315,6 @@ static int rz_mtu3_probe(struct platform_device *pdev)
struct rz_mtu3_priv *priv;
struct rz_mtu3 *ddata;
unsigned int i;
- int ret;
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
@@ -353,13 +347,8 @@ static int rz_mtu3_probe(struct platform_device *pdev)
mutex_init(&ddata->channels[i].lock);
}
- ret = mfd_add_devices(&pdev->dev, 0, rz_mtu3_devs,
- ARRAY_SIZE(rz_mtu3_devs), NULL, 0, NULL);
- if (ret < 0)
- return ret;
-
- return devm_add_action_or_reset(&pdev->dev, rz_mtu3_mfd_remove,
- &pdev->dev);
+ return devm_mfd_add_devices(&pdev->dev, 0, rz_mtu3_devs,
+ ARRAY_SIZE(rz_mtu3_devs), NULL, 0, NULL);
}
static const struct of_device_id rz_mtu3_of_match[] = {
--
2.53.0
^ permalink raw reply related
* [PATCH 02/11] mfd: rz-mtu3: use device-managed reset deassert
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com>
Replace devm_reset_control_get_exclusive() and the manual
reset_control_deassert()/reset_control_assert() with handling by
devm_reset_control_get_exclusive_deasserted().
While at it, remove struct rz_mtu3_priv::rstc and use a local variable
for it as it is not needed inside rz_mtu3_reset_assert().
Rename rz_mtu3_reset_assert() to rz_mtu3_mfd_remove() to accurately
describe its usage since it no longer calls reset_control_assert().
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/mfd/rz-mtu3.c | 23 +++++++----------------
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/drivers/mfd/rz-mtu3.c b/drivers/mfd/rz-mtu3.c
index 9cdfef610398..6b9c6831dffa 100644
--- a/drivers/mfd/rz-mtu3.c
+++ b/drivers/mfd/rz-mtu3.c
@@ -21,7 +21,6 @@
struct rz_mtu3_priv {
void __iomem *mmio;
- struct reset_control *rstc;
spinlock_t lock;
};
@@ -301,13 +300,9 @@ void rz_mtu3_disable(struct rz_mtu3_channel *ch)
}
EXPORT_SYMBOL_GPL(rz_mtu3_disable);
-static void rz_mtu3_reset_assert(void *data)
+static void rz_mtu3_mfd_remove(void *data)
{
- struct rz_mtu3 *mtu = dev_get_drvdata(data);
- struct rz_mtu3_priv *priv = mtu->priv_data;
-
mfd_remove_devices(data);
- reset_control_assert(priv->rstc);
}
static const struct mfd_cell rz_mtu3_devs[] = {
@@ -321,6 +316,7 @@ static const struct mfd_cell rz_mtu3_devs[] = {
static int rz_mtu3_probe(struct platform_device *pdev)
{
+ struct reset_control *rstc;
struct rz_mtu3_priv *priv;
struct rz_mtu3 *ddata;
unsigned int i;
@@ -340,15 +336,14 @@ static int rz_mtu3_probe(struct platform_device *pdev)
if (IS_ERR(priv->mmio))
return PTR_ERR(priv->mmio);
- priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
- if (IS_ERR(priv->rstc))
- return PTR_ERR(priv->rstc);
+ rstc = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL);
+ if (IS_ERR(rstc))
+ return PTR_ERR(rstc);
ddata->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(ddata->clk))
return PTR_ERR(ddata->clk);
- reset_control_deassert(priv->rstc);
spin_lock_init(&priv->lock);
platform_set_drvdata(pdev, ddata);
@@ -361,14 +356,10 @@ static int rz_mtu3_probe(struct platform_device *pdev)
ret = mfd_add_devices(&pdev->dev, 0, rz_mtu3_devs,
ARRAY_SIZE(rz_mtu3_devs), NULL, 0, NULL);
if (ret < 0)
- goto err_assert;
+ return ret;
- return devm_add_action_or_reset(&pdev->dev, rz_mtu3_reset_assert,
+ return devm_add_action_or_reset(&pdev->dev, rz_mtu3_mfd_remove,
&pdev->dev);
-
-err_assert:
- reset_control_assert(priv->rstc);
- return ret;
}
static const struct of_device_id rz_mtu3_of_match[] = {
--
2.53.0
^ permalink raw reply related
* [PATCH 01/11] clk: renesas: r9a09g077: add MTU3 module clock
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com>
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a MTU3
block connected to the PCLKH and with a module clock controlled by
register 0x308, bit 0.
Add support for the module clock.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/clk/renesas/r9a09g077-cpg.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index 93b15e06a19b..f777601a23b9 100644
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -257,6 +257,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
DEF_MOD("spi0", 104, CLK_SPI0ASYNC),
DEF_MOD("spi1", 105, CLK_SPI1ASYNC),
DEF_MOD("spi2", 106, CLK_SPI2ASYNC),
+ DEF_MOD("mtu3", 200, R9A09G077_CLK_PCLKH),
DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),
DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),
DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),
--
2.53.0
^ permalink raw reply related
* [PATCH 00/11] Add MTU3 for RZ/T2H and RZ/N2H
From: Cosmin Tanislav @ 2026-03-27 19:24 UTC (permalink / raw)
To: Biju Das, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Michael Turquette, Stephen Boyd, Lee Jones,
Philipp Zabel
Cc: linux-iio, linux-renesas-soc, linux-kernel, devicetree, linux-clk,
Cosmin Tanislav
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have an MTU3
block. Add support for them and fix the non-existing TCIU8 interrupt.
Cosmin Tanislav (11):
clk: renesas: r9a09g077: add MTU3 module clock
mfd: rz-mtu3: use device-managed reset deassert
mfd: rz-mtu3: use device-managed mfd_add_devices()
mfd: rz-mtu3: store &pdev->dev in local variable
mfd: rz-mtu3: make reset optional
dt-bindings: timer: renesas,rz-mtu3: remove TCIU8 interrupt
dt-bindings: timer: renesas,rz-mtu3: move required resets to
conditional
dt-bindings: timer: renesas,rz-mtu3: document RZ/{T2H,N2H}
arm64: dts: renesas: r9a07g0{43,44,54}: remove TCIU8 interrupt from
MTU3
arm64: dts: renesas: r9a09g077: add MTU3 support
arm64: dts: renesas: r9a09g087: add MTU3 support
.../bindings/timer/renesas,rz-mtu3.yaml | 34 ++++++++--
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 5 +-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +-
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 5 +-
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 68 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 68 +++++++++++++++++++
drivers/clk/renesas/r9a09g077-cpg.c | 1 +
drivers/mfd/rz-mtu3.c | 39 +++--------
8 files changed, 181 insertions(+), 44 deletions(-)
--
2.53.0
^ permalink raw reply
* Re: [PATCH 2/2] iio: adc: qcom-pm8xxx-xoadc: add support for reading channel labels
From: Antony Kurniawan Soemardi @ 2026-03-27 19:05 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, linux-arm-msm, devicetree, linux-kernel,
linux-iio, phone-devel
In-Reply-To: <acWDMg58qxyeM5Eq@ashevche-desk.local>
On 3/27/2026 2:04 AM, Andy Shevchenko wrote:
> On Thu, Mar 26, 2026 at 12:00:52PM +0000, Antony Kurniawan Soemardi wrote:
>> On 3/26/2026 5:18 PM, Andy Shevchenko wrote:
> ...
>>>> + if (!ch) {
>>>> + dev_err(adc->dev, "no such channel %lu\n", chan->address);
>>>> + return -EINVAL;
>>>> + }
>>>
>>> Isn't it a dead code? Also poisoning dmesg with this recurrent message is
>>> not good idea to begin with (the user space will have a door to flood it,
>>> which might be considered as an assistance to hackers to clear immediate
>>> logs after a successful attack).
>>
>> Good point about the successful attack hint! I was copying the existing
>> code from pm8xxx_read_raw. Do you think those checks are unnecessary for
>> pm8xxx_read_raw as well?
>
> Yes, I think they are not as the returned code should be enough to identify
> the problem. (For no such channel I would rather see -ENOENT, but we can't
> simply replace that in the existing code as it's part of ABI.)
Just to re-clarify, do you mean for both pm8xxx_read_label &
pm8xxx_read_raw:
1. if the check fails, it should only return -EINVAL without any
logging; or
2. remove the checks because there's no way it's not found?
--
Thanks,
Antony K. S.
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: qcom: qcs6490-rb3gen2: Enable uPD720201 and GL3590
From: Dmitry Baryshkov @ 2026-03-27 19:00 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <acSZ8AqKC3hdaz2A@baldur>
On Wed, Mar 25, 2026 at 09:40:58PM -0500, Bjorn Andersson wrote:
> On Wed, Mar 25, 2026 at 01:35:46AM +0200, Dmitry Baryshkov wrote:
> > On Mon, Mar 23, 2026 at 09:32:39PM -0500, Bjorn Andersson wrote:
> > > The QCS6490 Rb3Gen2 has a Renesas μPD720201 XHCI controller hanging off
> > > the TC9563 PCIe switch, on this a Genesys Logic GL3590 USB hub provides
> > > two USB Type-A ports and an ASIX AX88179 USB 3.0 Gigabit Ethernet
> > > interface.
> > >
> > > The Renesas chip is powered by two regulators controlled through PM7250B
> > > GPIOs 1 and 4, and the power/reset pin is pulled down by PM8350C GPIO 4.
> > > The Genesys chip power is always-on, but the reset pin is controlled
> > > through TLMM GPIO 162.
> > >
> > > Describe the Renesas chip on the PCIe bus, with supplies and reset, to
> > > allow it to be brought out of reset and discovered. Then describe the
> > > two peers of the USB hub, with its reset GPIO, to allow this to be
> > > brought out of reset.
> > >
> > > The USB Type-A connectors are not described, as they are in no regard
> > > controlled by the operating system.
> > >
> > > Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> > > ---
> > > Dependencies has now landed, so this provides USB Type-A and Ethernet
> > > support (when renesas_usb_fw.mem) is present.
> >
> > Note, I initially applied the patch to the bit old -next (20260317) and
> > I ended up with no PCIe host at all (bare -next would still show the
> > PCIe host and the TC9563 bridge).
> >
>
> Applied the patch to next-20260323 and tested again.
>
> >
> > ANyway, does this actually work for you?
>
> Yes, I booted with pcie_aspm=off I have functional ethernet and I can
> plug/unplug a USB storage device and access the content on this.
>
> > The hub is detected, but the USB bus is empty.
>
> I've disconnected the USB stick again, so here's the output when only
> ethernet is present.
>
> /: Bus 001.Port 001: Dev 001, Class=root_hub, Driver=xhci-pci-renesas/4p, 480M
> |__ Port 001: Dev 002, If 0, Class=Hub, Driver=hub/4p, 480M
> /: Bus 002.Port 001: Dev 001, Class=root_hub, Driver=xhci-pci-renesas/4p, 5000M
> |__ Port 001: Dev 002, If 0, Class=Hub, Driver=hub/4p, 5000M
> |__ Port 001: Dev 003, If 0, Class=Vendor Specific Class, Driver=ax88179_178a, 5000M
>
> > I tried plugging in several devices (includin the
> > powered USB hub) and they were completely ignored by the hub.
> >
>
> The USB stick above was powered by the device, so that part is tested as
> well. (And schematics shows VBUS is always present on the Type-A ports).
>
This makes me wander, what is wrong with the device of mine. I will run
more checks later. Let's not stall the patch though. In the end, I also
can see the hub registered and working with the driver.
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 1/4] iio: adc: xilinx-xadc: Split driver into core and platform files
From: kernel test robot @ 2026-03-27 18:58 UTC (permalink / raw)
To: Sai Krishna Potthuri, Jonathan Cameron, David Lechner, Nuno Sa,
Andy Shevchenko, Michal Simek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: oe-kbuild-all, linux-iio, devicetree, linux-arm-kernel,
linux-kernel, saikrishna12468, git, Sai Krishna Potthuri
In-Reply-To: <20260323074505.3853353-2-sai.krishna.potthuri@amd.com>
Hi Sai,
kernel test robot noticed the following build warnings:
[auto build test WARNING on jic23-iio/togreg]
[also build test WARNING on robh/for-next linus/master v7.0-rc5 next-20260326]
[cannot apply to xilinx-xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Sai-Krishna-Potthuri/iio-adc-xilinx-xadc-Split-driver-into-core-and-platform-files/20260326-024045
base: https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git togreg
patch link: https://lore.kernel.org/r/20260323074505.3853353-2-sai.krishna.potthuri%40amd.com
patch subject: [PATCH v2 1/4] iio: adc: xilinx-xadc: Split driver into core and platform files
config: hexagon-randconfig-r133-20260326 (https://download.01.org/0day-ci/archive/20260328/202603280238.N4wp7jaC-lkp@intel.com/config)
compiler: clang version 23.0.0git (https://github.com/llvm/llvm-project 054e11d1a17e5ba88bb1a8ef32fad3346e80b186)
sparse: v0.6.5-rc1
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260328/202603280238.N4wp7jaC-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603280238.N4wp7jaC-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/iio/adc/xilinx-xadc-core.c:764:12: sparse: sparse: symbol 'xadc_type_names' was not declared. Should it be static?
vim +/xadc_type_names +764 drivers/iio/adc/xilinx-xadc-core.c
763
> 764 const char * const xadc_type_names[] = {
765 [XADC_TYPE_S7] = "xadc",
766 [XADC_TYPE_US] = "xilinx-system-monitor",
767 };
768
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v1 1/1] arm64: dts: imx91-var-dart-sonata: add RGB select supply for PCA6408
From: Frank Li @ 2026-03-27 18:41 UTC (permalink / raw)
To: Stefano Radaelli
Cc: linux-kernel, devicetree, imx, linux-arm-kernel, pierluigi.p,
Stefano Radaelli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
In-Reply-To: <aca7ckVY9ure8Cwe@Lord-Beerus.station>
On Fri, Mar 27, 2026 at 06:16:34PM +0100, Stefano Radaelli wrote:
> Hi Frank,
>
> On Fri, Mar 27, 2026 at 12:51:25PM -0400, Frank Li wrote:
> > On Fri, Mar 27, 2026 at 05:32:43PM +0100, Stefano Radaelli wrote:
> > > From: Stefano Radaelli <stefano.r@variscite.com>
> > >
> > > RGB_SEL controls the routing of some carrier board lines on the Sonata
> > > board. The two PCA6408 GPIO expanders depend on that path being enabled,
> > > so describe the selector as a fixed regulator and use it as their
> > > vcc-supply.
> >
> > Does below resolve your problem?
> > https://lore.kernel.org/imx/20260325-pinctrl-mux-v4-0-043c2c82e623@nxp.com/
> >
> > So needn't hack select as regualtor
> >
>
> Thanks for pointing me your patch, interesting improvement!
>
> Actually, in this case RGB_SEL is not meant to model a selectable mux
> on the Sonata carrier.
> On this board it must stay asserted permanently, otherwise the
> downstream path to the two PCA6408 expanders is not accessible.
Accroding to signal name, it is MUX chip select signal. Of couse it may
connect to a buffer's EN pin. I have not checked your schematic.
If it connect to MUX chip or some select signal, it should use above method,
even though it is permanently asserted when access PCA6408.
If it connect to EN pin of buffer, regualtor should be good.
Frank
>
> Modeling it as a mux might be confusing for users of the DART-MX91, as
> as it would suggest that the routing is configurable, while on this
> board it is actually fixed.
>
> Best Regards,
> Stefano
^ permalink raw reply
* [PATCH v3 2/3] arm64: Kconfig: Add ARCH_HPE platform
From: nick.hawkins @ 2026-03-27 17:44 UTC (permalink / raw)
To: catalin.marinas, will, robh, krzk+dt, conor+dt
Cc: nick.hawkins, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260327174445.3275835-1-nick.hawkins@hpe.com>
From: Nick Hawkins <nick.hawkins@hpe.com>
Add the ARCH_HPE config for HPE ARM64 BMC SoCs to Kconfig.platforms.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
arch/arm64/Kconfig.platforms | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 54eb1d7fd419..b4217809c774 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -168,6 +168,17 @@ config ARCH_HISI
help
This enables support for Hisilicon ARMv8 SoC family
+config ARCH_HPE
+ bool "HPE SoC Support"
+ select PINCTRL
+ select GENERIC_IRQ_CHIP
+ select CLKSRC_MMIO
+ help
+ This enables support for HPE ARM-based SoC chips used
+ on HPE servers. HPE SoCs serve as the Baseboard
+ Management Controller (BMC) providing out-of-band server
+ management.
+
config ARCH_KEEMBAY
bool "Keem Bay SoC"
help
--
2.34.1
^ permalink raw reply related
* [PATCH v9 6/6] reset: rzv2h-usb2phy: Add support for VBUS mux controller registration
From: Tommaso Merciai @ 2026-03-27 18:08 UTC (permalink / raw)
To: tomm.merciai, peda, p.zabel
Cc: linux-renesas-soc, biju.das.jz, Tommaso Merciai, Fabrizio Castro,
Lad Prabhakar, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Josua Mayer,
Ulf Hansson, devicetree, linux-kernel
In-Reply-To: <cover.1774601289.git.tommaso.merciai.xr@bp.renesas.com>
The RZ/V2H USB2 PHY requires control of the VBUS selection line
(VBENCTL) through a mux controller described in the device tree as
"mux-controller". This change adds support for registering the
rzv2h-usb-vbenctl auxiliary driver during probe.
This enables proper management of USB2.0 VBUS source selection on
platforms using the RZ/V2H SoC.
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v8->v9:
- Drop linux/reset/reset_rzv2h_usb2phy.h dependecy as the driver
is now based on regmap and does not need the reset driver's
private header, update driver accordingly.
- Collected PZabel tag.
v7->v8:
- No changes
v6->v7:
- No changes
v5->v6:
- No changes
v4->v5:
- Update mux_name to "vbenctl" to match the driver name.
- Updated commit message.
v3->v4:
- No changes.
v2->v3:
- Use __devm_auxiliary_device_create() to create the auxiliary device.
v1->v2:
- New patch
drivers/reset/Kconfig | 1 +
drivers/reset/reset-rzv2h-usb2phy.c | 35 +++++++++++++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c539ca88518f..62b2c3919613 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -257,6 +257,7 @@ config RESET_RZG2L_USBPHY_CTRL
config RESET_RZV2H_USB2PHY
tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver"
depends on ARCH_RENESAS || COMPILE_TEST
+ select AUXILIARY_BUS
select REGMAP_MMIO
help
Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC
diff --git a/drivers/reset/reset-rzv2h-usb2phy.c b/drivers/reset/reset-rzv2h-usb2phy.c
index 4014eff0f017..b1b8fa8377dd 100644
--- a/drivers/reset/reset-rzv2h-usb2phy.c
+++ b/drivers/reset/reset-rzv2h-usb2phy.c
@@ -5,7 +5,9 @@
* Copyright (C) 2025 Renesas Electronics Corporation
*/
+#include <linux/auxiliary_bus.h>
#include <linux/delay.h>
+#include <linux/idr.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -15,6 +17,8 @@
#include <linux/reset.h>
#include <linux/reset-controller.h>
+static DEFINE_IDA(auxiliary_ids);
+
struct rzv2h_usb2phy_regval {
u16 reg;
u16 val;
@@ -99,6 +103,33 @@ static int rzv2h_usb2phy_reset_of_xlate(struct reset_controller_dev *rcdev,
return 0;
}
+static void rzv2h_usb2phy_reset_ida_free(void *data)
+{
+ struct auxiliary_device *adev = data;
+
+ ida_free(&auxiliary_ids, adev->id);
+}
+
+static int rzv2h_usb2phy_reset_mux_register(struct device *dev,
+ const char *mux_name)
+{
+ struct auxiliary_device *adev;
+ int id;
+
+ id = ida_alloc(&auxiliary_ids, GFP_KERNEL);
+ if (id < 0)
+ return id;
+
+ adev = __devm_auxiliary_device_create(dev, dev->driver->name,
+ mux_name, NULL, id);
+ if (!adev) {
+ ida_free(&auxiliary_ids, id);
+ return -ENOMEM;
+ }
+
+ return devm_add_action_or_reset(dev, rzv2h_usb2phy_reset_ida_free, adev);
+}
+
static const struct regmap_config rzv2h_usb2phy_reset_regconf = {
.reg_bits = 32,
.val_bits = 32,
@@ -166,6 +197,10 @@ static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev)
if (error)
return dev_err_probe(dev, error, "could not register reset controller\n");
+ error = rzv2h_usb2phy_reset_mux_register(dev, "vbenctl");
+ if (error)
+ return dev_err_probe(dev, error, "could not register aux mux\n");
+
return 0;
}
--
2.43.0
^ permalink raw reply related
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