* Re: [PATCH 2/5] dt-bindings: clock: qcom,milos-camcc: Document interconnect path
From: Luca Weiss @ 2026-03-30 14:55 UTC (permalink / raw)
To: Mike Tipton, Konrad Dybcio
Cc: Krzysztof Kozlowski, Luca Weiss, Taniya Das, Georgi Djakov,
Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, ~postmarketos/upstreaming,
phone-devel, linux-pm, linux-kernel, linux-arm-msm, linux-clk,
devicetree
In-Reply-To: <acH7aEBvSbiNwhBz@hu-mdtipton-lv.qualcomm.com>
Hi Mike,
On Tue Mar 24, 2026 at 3:48 AM CET, Mike Tipton wrote:
> On Mon, Jan 19, 2026 at 11:28:07AM +0100, Konrad Dybcio wrote:
>>
>>
>> On 1/19/26 11:20 AM, Konrad Dybcio wrote:
>> > On 1/17/26 12:46 PM, Krzysztof Kozlowski wrote:
>> >> On Fri, Jan 16, 2026 at 02:17:21PM +0100, Luca Weiss wrote:
>> >>> Document an interconnect path for camcc that's required to enable
>> >>> the CAMSS_TOP_GDSC power domain.
>> >>
>> >> I find it confusing. Enabling GDSC power domains is done via power
>> >> domains, not via interconnects. Do not represent power domains as
>> >> interconnects, it's something completely different.
>> >
>> > The name of the power domains is CAMSS_TOP_GDSC (seems you misread)
>> >
>> > For the power domain to successfully turn on, the MNoC needs to be
>> > turned on (empirical evidence). The way to do it is to request a
>> > nonzero vote on this interconnect path
>> >
>> > (presumably because the GDSC or its invisible providers require
>> > something connected over that bus to carry out their enable sequences).
>
> The GDSC itself shouldn't depend on MMNOC in order to turn on properly.
> It should turn on just fine without it. There *is* a dependency between
> CAM_TOP_GDSC and MMNOC, but it's in the opposite direction.
I can personally just write from practical experience, as Qualcomm
doesn't share any relevant documentation with OEMs.
Without this patch the GDSC refuses to turn on.
[ 291.055839] ------------[ cut here ]------------
[ 291.055860] cam_cc_camss_top_gdsc status stuck at 'off'
[ 291.055878] WARNING: drivers/clk/qcom/gdsc.c:178 at gdsc_toggle_logic+0x138/0x144, CPU#4: hexdump/1995
With the patch it turns on just fine, no issues seen.
As Konrad has written, originally I didn't see any issue because that
interconnect was being kept alive by simple-framebuffer where I've added
'interconnects' to keep the framebuffer alive. However when testing
without this, the GDSC would refuse to turn on, which led me to this
patch series.
Additionally you can see in downstream devicetree you can also see an
interconnect defined for the "cam_cc_camss_top_gdsc" node:
https://gerrit-public.fairphone.software/plugins/gitiles/platform/vendor/qcom/proprietary/devicetree/+/refs/heads/odm/rc/target/15/fp6/fps_overlay/volcano.dtsi#2943
Regards
Luca
^ permalink raw reply
* RE: [PATCH v3 1/3] dt-bindings: arm: hpe,gxp: Add HPE GSC platform compatible
From: Hawkins, Nick @ 2026-03-30 14:53 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: catalin.marinas@arm.com, will@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20260328-chirpy-sturdy-emu-9eb0cb@quoll>
Hi Krzysztof Kozlowski,
> > maintainers:
> > - Nick Hawkins <nick.hawkins@hpe.com>
> > @@ -18,6 +18,11 @@ properties:
> > - enum:
> > - hpe,gxp-dl360gen10
> > - const: hpe,gxp
> > + - description: GSC Based Boards
> > + items:
> > + - enum:
> > + - hpe,gsc-dl340gen12
> > + - const: hpe,gsc
> What sort of ordering are you going to use in this file? Usual choice is
> the fallback compatible, but I see you have chosen something else. That
> is fine, just keep that else sorting in the future instead of adding to
> the end.
Thank you for the feedback, just to confirm are you looking for me
to do something like this?:
- description: GSC Based Boards
items:
- enum:
- hpe,gsc-dl340gen12
- const: hpe,gsc
- description: GXP Based Boards
items:
- enum:
- hpe,gxp-dl360gen10
- const: hpe,gxp
That way we have the newest first and going forward if there is
something newer we add it to the top of the list rather than
the bottom?
Thanks,
-Nick Hawkins
^ permalink raw reply
* [PATCH] arm64: dts: meson-gxl-p230: fix ethernet PHY interrupt number
From: Jun Yan @ 2026-03-30 14:51 UTC (permalink / raw)
To: linux-kernel, linux-amlogic, linux-arm-kernel, devicetree
Cc: robh, krzk+dt, conor+dt, neil.armstrong, khilman, jbrunet,
martin.blumenstingl, Jun Yan
Correct the interrupt number assigned to the Realtek PHY in the p230
following the same logic as commit 3106507e1004 ("ARM64: dts: meson-gxm:
fix q200 interrupt number"),as reported in [PATCH 0/2] Ethernet PHY
interrupt improvements [1].
[1] https://lore.kernel.org/all/20171202214037.17017-1-martin.blumenstingl@googlemail.com/
Fixes: b94d22d94ad2 ("ARM64: dts: meson-gx: add external PHY interrupt on some platforms")
Signed-off-by: Jun Yan <jerrysteve1101@gmail.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
index 7dffeb5931c9..701de57ff0f3 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -84,7 +84,8 @@ external_phy: ethernet-phy@0 {
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
- interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ /* MAC_INTR on GPIOZ_15 */
+ interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
eee-broken-1000t;
};
};
--
2.53.0
^ permalink raw reply related
* Re: [PATCH 08/16] clk: Improve a couple of comments
From: Brian Masney @ 2026-03-30 14:50 UTC (permalink / raw)
To: Miquel Raynal (Schneider Electric)
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Gleixner, Olivia Mackall, Herbert Xu,
Jayesh Choudhary, David S. Miller, Christian Marangi,
Antoine Tenart, Geert Uytterhoeven, Magnus Damm, Thomas Petazzoni,
Pascal EBERHARD, Wolfram Sang, linux-clk, devicetree,
linux-kernel, linux-crypto, linux-renesas-soc
In-Reply-To: <20260327-schneider-v7-0-rc1-crypto-v1-8-5e6ff7853994@bootlin.com>
On Fri, Mar 27, 2026 at 09:09:30PM +0100, Miquel Raynal (Schneider Electric) wrote:
> Avoid mentioning the function names directly in the comments, it makes
> them easily out of sync with the rest of the code. Use a more generic
> wording.
>
> Suggested-by: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
^ permalink raw reply
* Re: [PATCH 06/16] clk: tests: Add clk_parse_clkspec() Kunit testing
From: Brian Masney @ 2026-03-30 14:48 UTC (permalink / raw)
To: Miquel Raynal (Schneider Electric)
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Gleixner, Olivia Mackall, Herbert Xu,
Jayesh Choudhary, David S. Miller, Christian Marangi,
Antoine Tenart, Geert Uytterhoeven, Magnus Damm, Thomas Petazzoni,
Pascal EBERHARD, Wolfram Sang, linux-clk, devicetree,
linux-kernel, linux-crypto, linux-renesas-soc, Chen-Yu Tsai
In-Reply-To: <20260327-schneider-v7-0-rc1-crypto-v1-6-5e6ff7853994@bootlin.com>
Hi Miquel,
On Fri, Mar 27, 2026 at 09:09:28PM +0100, Miquel Raynal (Schneider Electric) wrote:
> Create a new set of kunit tests to make sure clk_parse_clkspec() is
> working as expected. We currently verify if we get a proper device when
> using indexes and names. If we make an out of bounds request we expect
> an error.
>
> For testing purposes, we must ensure of_clk_get_hw()'s symbol is
> exported.
>
> Suggested-by: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
> ---
> drivers/clk/Makefile | 1 +
> drivers/clk/clk.c | 1 +
> drivers/clk/clk_test.c | 124 +++++++++++++++++++++++++++++++
> drivers/clk/kunit_clk_parse_clkspec.dtso | 21 ++++++
> 4 files changed, 147 insertions(+)
>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index f7bce3951a30..97b621456bf5 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -19,6 +19,7 @@ clk-test-y := clk_test.o \
> kunit_clk_assigned_rates_zero.dtbo.o \
> kunit_clk_assigned_rates_zero_consumer.dtbo.o \
> kunit_clk_hw_get_dev_of_node.dtbo.o \
> + kunit_clk_parse_clkspec.dtbo.o \
> kunit_clk_parent_data_test.dtbo.o
> obj-$(CONFIG_COMMON_CLK) += clk-divider.o
> obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 47093cda9df3..1795246b10a0 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -5312,6 +5312,7 @@ struct clk_hw *of_clk_get_hw(struct device_node *np, int index,
>
> return hw;
> }
> +EXPORT_SYMBOL_GPL(of_clk_get_hw);
So that we don't unnecessarily broaden the API that's available to the
clk providers, you can use EXPORT_SYMBOL_IF_KUNIT so that this is only
available to the kunit tests.
Note that Chen-Yu posted a separate patch to add the includes for a
separate test. The two patches will conflict since Stephen hasn't picked
this up yet.
https://lore.kernel.org/linux-clk/20260225083413.3384950-1-wenst@chromium.org/
>
> static struct clk *__of_clk_get(struct device_node *np,
> int index, const char *dev_id,
> diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c
> index a268d7b5d4cb..b814b45f1f7e 100644
> --- a/drivers/clk/clk_test.c
> +++ b/drivers/clk/clk_test.c
> @@ -3541,10 +3541,134 @@ static struct kunit_suite clk_hw_get_dev_of_node_test_suite = {
> .test_cases = clk_hw_get_dev_of_node_test_cases,
> };
>
> +static const struct clk_init_data clk_parse_clkspec_1_init_data = {
> + .name = "clk_parse_clkspec_1",
> + .ops = &empty_clk_ops,
> +};
> +
> +static const struct clk_init_data clk_parse_clkspec_2_init_data = {
> + .name = "clk_parse_clkspec_2",
> + .ops = &empty_clk_ops,
> +};
> +
> +static struct clk_hw *kunit_clk_get(struct of_phandle_args *clkspec, void *data)
> +{
> + return (struct clk_hw *)data;
> +}
> +
> +struct clk_parse_clkspec_ctx {
> + struct device_node *prov1_np;
> + struct device_node *prov2_np;
> + struct device_node *cons_np;
> +};
> +
> +static int clk_parse_clkspec_init(struct kunit *test)
> +{
> + struct clk_parse_clkspec_ctx *ctx;
> + struct clk_hw *hw1, *hw2;
> +
> + ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
> + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx);
> + test->priv = ctx;
> +
> + KUNIT_ASSERT_EQ(test, 0, of_overlay_apply_kunit(test, kunit_clk_parse_clkspec));
> +
> + /* Register provider 1 */
> + hw1 = kunit_kzalloc(test, sizeof(*hw1), GFP_KERNEL);
> + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw1);
> + hw1->init = &clk_parse_clkspec_1_init_data;
> +
> + ctx->prov1_np = of_find_compatible_node(NULL, NULL, "test,clock-provider1");
> + KUNIT_ASSERT_NOT_NULL(test, ctx->prov1_np);
> +
> + KUNIT_ASSERT_EQ(test, 0, of_clk_hw_register_kunit(test, ctx->prov1_np, hw1));
> + of_clk_add_hw_provider(ctx->prov1_np, kunit_clk_get, hw1);
Can you just use of_clk_hw_simple_get() and drop kunit_clk_get() above?
> + of_node_put(ctx->prov1_np);
> +
> + /* Register provider 2 */
> + hw2 = kunit_kzalloc(test, sizeof(*hw2), GFP_KERNEL);
> + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw2);
> + hw2->init = &clk_parse_clkspec_2_init_data;
> +
> + ctx->prov2_np = of_find_compatible_node(NULL, NULL, "test,clock-provider2");
> + KUNIT_ASSERT_NOT_NULL(test, ctx->prov2_np);
> +
> + KUNIT_ASSERT_EQ(test, 0, of_clk_hw_register_kunit(test, ctx->prov2_np, hw2));
> + of_clk_add_hw_provider(ctx->prov2_np, kunit_clk_get, hw2);
> + of_node_put(ctx->prov2_np);
> +
> + ctx->cons_np = of_find_compatible_node(NULL, NULL, "test,clock-consumer");
> + KUNIT_ASSERT_NOT_NULL(test, ctx->cons_np);
> +
> + return 0;
> +}
> +
> +static void clk_parse_clkspec_exit(struct kunit *test)
> +{
> + struct clk_parse_clkspec_ctx *ctx = test->priv;
> +
> + of_node_put(ctx->prov1_np);
> + of_node_put(ctx->prov2_np);
Is there a double free of prov1_np and prov2_np? If this is dropped from
the test exit, then they should't need to be in the ctx struct.
Brian
^ permalink raw reply
* Re: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency
From: kernel test robot @ 2026-03-30 14:47 UTC (permalink / raw)
To: Mikko Perttunen, Thierry Reding, Uwe Kleine-König,
Jonathan Hunter, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: oe-kbuild-all, linux-pwm, linux-tegra, linux-kernel, devicetree,
Yi-Wei Wang, Mikko Perttunen
In-Reply-To: <20260325-t264-pwm-v2-2-998d885984b3@nvidia.com>
Hi Mikko,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 11439c4635edd669ae435eec308f4ab8a0804808]
url: https://github.com/intel-lab-lkp/linux/commits/Mikko-Perttunen/dt-bindings-pwm-Document-Tegra194-and-Tegra264-controllers/20260329-233356
base: 11439c4635edd669ae435eec308f4ab8a0804808
patch link: https://lore.kernel.org/r/20260325-t264-pwm-v2-2-998d885984b3%40nvidia.com
patch subject: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency
config: hexagon-randconfig-r113-20260330 (https://download.01.org/0day-ci/archive/20260330/202603302251.AFXspVqF-lkp@intel.com/config)
compiler: clang version 23.0.0git (https://github.com/llvm/llvm-project 2cd67b8b69f78e3f95918204320c3075a74ba16c)
sparse: v0.6.5-rc1
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260330/202603302251.AFXspVqF-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603302251.AFXspVqF-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/pwm/pwm-tegra.c:303:47: sparse: sparse: cast truncates bits from constant value (7fffffffffffffff becomes ffffffff)
vim +303 drivers/pwm/pwm-tegra.c
266
267 static int tegra_pwm_probe(struct platform_device *pdev)
268 {
269 struct pwm_chip *chip;
270 struct tegra_pwm_chip *pc;
271 const struct tegra_pwm_soc *soc;
272 int ret;
273
274 soc = of_device_get_match_data(&pdev->dev);
275
276 chip = devm_pwmchip_alloc(&pdev->dev, soc->num_channels, sizeof(*pc));
277 if (IS_ERR(chip))
278 return PTR_ERR(chip);
279 pc = to_tegra_pwm_chip(chip);
280
281 pc->soc = soc;
282
283 pc->regs = devm_platform_ioremap_resource(pdev, 0);
284 if (IS_ERR(pc->regs))
285 return PTR_ERR(pc->regs);
286
287 platform_set_drvdata(pdev, chip);
288
289 pc->clk = devm_clk_get(&pdev->dev, NULL);
290 if (IS_ERR(pc->clk))
291 return PTR_ERR(pc->clk);
292
293 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
294 if (ret)
295 return ret;
296
297 pm_runtime_enable(&pdev->dev);
298 ret = pm_runtime_resume_and_get(&pdev->dev);
299 if (ret)
300 return ret;
301
302 /* Set maximum frequency of the IP */
> 303 ret = dev_pm_opp_set_rate(&pdev->dev, S64_MAX);
304 if (ret < 0) {
305 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
306 goto put_pm;
307 }
308
309 /*
310 * The requested and configured frequency may differ due to
311 * clock register resolutions. Get the configured frequency
312 * so that PWM period can be calculated more accurately.
313 */
314 pc->clk_rate = clk_get_rate(pc->clk);
315
316 /* Set minimum limit of PWM period for the IP */
317 pc->min_period_ns =
318 (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1;
319
320 pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
321 if (IS_ERR(pc->rst)) {
322 ret = PTR_ERR(pc->rst);
323 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
324 goto put_pm;
325 }
326
327 reset_control_deassert(pc->rst);
328
329 chip->ops = &tegra_pwm_ops;
330
331 ret = pwmchip_add(chip);
332 if (ret < 0) {
333 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
334 reset_control_assert(pc->rst);
335 goto put_pm;
336 }
337
338 pm_runtime_put(&pdev->dev);
339
340 return 0;
341 put_pm:
342 pm_runtime_put_sync_suspend(&pdev->dev);
343 pm_runtime_force_suspend(&pdev->dev);
344 return ret;
345 }
346
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* [PATCH v5 10/10] arm64: tegra: Enable GPCDMA in Tegra264 and add iommu-map
From: Akhil R @ 2026-03-30 14:44 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Philipp Zabel, dmaengine, devicetree, linux-tegra, linux-kernel
Cc: Akhil R
In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com>
Enable GPCDMA in Tegra264 and add the iommu-map property so that each
channel uses a separate stream ID and gets its own IOMMU domain for
memory.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 4 ++++
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
index 7e2c3e66c2ab..58cd81bc33d7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
@@ -9,6 +9,10 @@ aliases {
};
bus@0 {
+ dma-controller@8400000 {
+ status = "okay";
+ };
+
serial@c4e0000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index af077420d7d9..b2f20d4b567a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3244,6 +3244,7 @@ gpcdma: dma-controller@8400000 {
<GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
iommus = <&smmu1 0x00000800>;
+ iommu-map = <1 &smmu1 0x801 31>;
dma-coherent;
dma-channel-mask = <0xfffffffe>;
status = "disabled";
--
2.50.1
^ permalink raw reply related
* [PATCH v5 09/10] dmaengine: tegra: Add Tegra264 support
From: Akhil R @ 2026-03-30 14:44 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Philipp Zabel, dmaengine, devicetree, linux-tegra, linux-kernel
Cc: Akhil R, Frank Li
In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com>
Add compatible and chip data to support GPCDMA in Tegra264, which has
differences in register layout and address bits compared to previous
versions.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/tegra186-gpc-dma.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
index 64743d852dda..0b7faf8bb80b 100644
--- a/drivers/dma/tegra186-gpc-dma.c
+++ b/drivers/dma/tegra186-gpc-dma.c
@@ -1319,6 +1319,23 @@ static const struct tegra_dma_channel_regs tegra186_reg_offsets = {
.fixed_pattern = 0x34,
};
+static const struct tegra_dma_channel_regs tegra264_reg_offsets = {
+ .csr = 0x0,
+ .status = 0x4,
+ .csre = 0x8,
+ .src = 0xc,
+ .dst = 0x10,
+ .src_high = 0x14,
+ .dst_high = 0x18,
+ .mc_seq = 0x1c,
+ .mmio_seq = 0x20,
+ .wcount = 0x24,
+ .wxfer = 0x28,
+ .wstatus = 0x2c,
+ .err_status = 0x34,
+ .fixed_pattern = 0x38,
+};
+
static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
.nr_channels = 32,
.addr_bits = 39,
@@ -1349,6 +1366,16 @@ static const struct tegra_dma_chip_data tegra234_dma_chip_data = {
.terminate = tegra_dma_pause_noerr,
};
+static const struct tegra_dma_chip_data tegra264_dma_chip_data = {
+ .nr_channels = 32,
+ .addr_bits = 41,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = true,
+ .channel_regs = &tegra264_reg_offsets,
+ .terminate = tegra_dma_pause_noerr,
+};
+
static const struct of_device_id tegra_dma_of_match[] = {
{
.compatible = "nvidia,tegra186-gpcdma",
@@ -1359,6 +1386,9 @@ static const struct of_device_id tegra_dma_of_match[] = {
}, {
.compatible = "nvidia,tegra234-gpcdma",
.data = &tegra234_dma_chip_data,
+ }, {
+ .compatible = "nvidia,tegra264-gpcdma",
+ .data = &tegra264_dma_chip_data,
}, {
},
};
--
2.50.1
^ permalink raw reply related
* [PATCH v5 08/10] dmaengine: tegra: Use iommu-map for stream ID
From: Akhil R @ 2026-03-30 14:44 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Philipp Zabel, dmaengine, devicetree, linux-tegra, linux-kernel
Cc: Akhil R
In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com>
Use 'iommu-map', when provided, to get the stream ID to be programmed
for each channel. Iterate over the channels registered and configure
each channel device separately using of_dma_configure_id() to allow
it to use a separate IOMMU domain for the transfer. However, do this
in a second loop since the first loop populates the DMA device channels
list and async_device_register() registers the channels. Both are
prerequisites for using the channel device in the next loop.
Channels will continue to use the same global stream ID if the
'iommu-map' property is not present in the device tree.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
drivers/dma/tegra186-gpc-dma.c | 57 ++++++++++++++++++++++++++++------
1 file changed, 48 insertions(+), 9 deletions(-)
diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
index 9bea2ffb3b9e..64743d852dda 100644
--- a/drivers/dma/tegra186-gpc-dma.c
+++ b/drivers/dma/tegra186-gpc-dma.c
@@ -15,6 +15,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_dma.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/slab.h>
@@ -1380,9 +1381,13 @@ static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id)
static int tegra_dma_probe(struct platform_device *pdev)
{
const struct tegra_dma_chip_data *cdata = NULL;
+ struct tegra_dma_channel *tdc;
+ struct tegra_dma *tdma;
+ struct dma_chan *chan;
+ struct device *chdev;
+ bool use_iommu_map = false;
unsigned int i;
u32 stream_id;
- struct tegra_dma *tdma;
int ret;
cdata = of_device_get_match_data(&pdev->dev);
@@ -1410,9 +1415,12 @@ static int tegra_dma_probe(struct platform_device *pdev)
tdma->dma_dev.dev = &pdev->dev;
- if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) {
- dev_err(&pdev->dev, "Missing iommu stream-id\n");
- return -EINVAL;
+ use_iommu_map = of_property_present(pdev->dev.of_node, "iommu-map");
+ if (!use_iommu_map) {
+ if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) {
+ dev_err(&pdev->dev, "Missing iommu stream-id\n");
+ return -EINVAL;
+ }
}
ret = device_property_read_u32(&pdev->dev, "dma-channel-mask",
@@ -1424,9 +1432,10 @@ static int tegra_dma_probe(struct platform_device *pdev)
tdma->chan_mask = TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK;
}
+ /* Initialize vchan for each channel and populate the channels list */
INIT_LIST_HEAD(&tdma->dma_dev.channels);
for (i = 0; i < cdata->nr_channels; i++) {
- struct tegra_dma_channel *tdc = &tdma->channels[i];
+ tdc = &tdma->channels[i];
/* Check for channel mask */
if (!(tdma->chan_mask & BIT(i)))
@@ -1446,10 +1455,6 @@ static int tegra_dma_probe(struct platform_device *pdev)
vchan_init(&tdc->vc, &tdma->dma_dev);
tdc->vc.desc_free = tegra_dma_desc_free;
-
- /* program stream-id for this channel */
- tegra_dma_program_sid(tdc, stream_id);
- tdc->stream_id = stream_id;
}
dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(cdata->addr_bits));
@@ -1483,6 +1488,7 @@ static int tegra_dma_probe(struct platform_device *pdev)
tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;
tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+ /* Register the DMA device and the channels */
ret = dmaenginem_async_device_register(&tdma->dma_dev);
if (ret < 0) {
dev_err_probe(&pdev->dev, ret,
@@ -1490,6 +1496,39 @@ static int tegra_dma_probe(struct platform_device *pdev)
return ret;
}
+ /*
+ * Configure stream ID for each channel from the channels registered
+ * above. This is done in a separate iteration to ensure that only
+ * the channels available and registered for the DMA device are used.
+ */
+ list_for_each_entry(chan, &tdma->dma_dev.channels, device_node) {
+ chdev = &chan->dev->device;
+ tdc = to_tegra_dma_chan(chan);
+
+ if (use_iommu_map) {
+ chdev->bus = pdev->dev.bus;
+ dma_coerce_mask_and_coherent(chdev, DMA_BIT_MASK(cdata->addr_bits));
+
+ ret = of_dma_configure_id(chdev, pdev->dev.of_node,
+ true, &tdc->id);
+ if (ret)
+ return dev_err_probe(chdev, ret,
+ "Failed to configure IOMMU for channel %d", tdc->id);
+
+ if (!tegra_dev_iommu_get_stream_id(chdev, &stream_id)) {
+ dev_err(chdev, "Failed to get stream ID for channel %d\n",
+ tdc->id);
+ return -EINVAL;
+ }
+
+ chan->dev->chan_dma_dev = true;
+ }
+
+ /* program stream-id for this channel */
+ tegra_dma_program_sid(tdc, stream_id);
+ tdc->stream_id = stream_id;
+ }
+
ret = devm_of_dma_controller_register(&pdev->dev, pdev->dev.of_node,
tegra_dma_of_xlate, tdma);
if (ret < 0) {
--
2.50.1
^ permalink raw reply related
* [PATCH v5 07/10] dmaengine: tegra: Use managed DMA controller registration
From: Akhil R @ 2026-03-30 14:44 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Philipp Zabel, dmaengine, devicetree, linux-tegra, linux-kernel
Cc: Akhil R, Frank Li
In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com>
Switch to managed registration in probe. This simplifies the error
paths in the probe and also removes the requirement of the driver
remove function.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Suggested-by: Frank Li <frank.li@nxp.com>
---
drivers/dma/tegra186-gpc-dma.c | 19 ++++---------------
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
index 3ac43ad19ed6..9bea2ffb3b9e 100644
--- a/drivers/dma/tegra186-gpc-dma.c
+++ b/drivers/dma/tegra186-gpc-dma.c
@@ -1483,37 +1483,27 @@ static int tegra_dma_probe(struct platform_device *pdev)
tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;
tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
- ret = dma_async_device_register(&tdma->dma_dev);
+ ret = dmaenginem_async_device_register(&tdma->dma_dev);
if (ret < 0) {
dev_err_probe(&pdev->dev, ret,
"GPC DMA driver registration failed\n");
return ret;
}
- ret = of_dma_controller_register(pdev->dev.of_node,
- tegra_dma_of_xlate, tdma);
+ ret = devm_of_dma_controller_register(&pdev->dev, pdev->dev.of_node,
+ tegra_dma_of_xlate, tdma);
if (ret < 0) {
dev_err_probe(&pdev->dev, ret,
"GPC DMA OF registration failed\n");
-
- dma_async_device_unregister(&tdma->dma_dev);
return ret;
}
- dev_info(&pdev->dev, "GPC DMA driver register %lu channels\n",
+ dev_info(&pdev->dev, "GPC DMA driver registered %lu channels\n",
hweight_long(tdma->chan_mask));
return 0;
}
-static void tegra_dma_remove(struct platform_device *pdev)
-{
- struct tegra_dma *tdma = platform_get_drvdata(pdev);
-
- of_dma_controller_free(pdev->dev.of_node);
- dma_async_device_unregister(&tdma->dma_dev);
-}
-
static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
{
struct tegra_dma *tdma = dev_get_drvdata(dev);
@@ -1564,7 +1554,6 @@ static struct platform_driver tegra_dma_driver = {
.of_match_table = tegra_dma_of_match,
},
.probe = tegra_dma_probe,
- .remove = tegra_dma_remove,
};
module_platform_driver(tegra_dma_driver);
--
2.50.1
^ permalink raw reply related
* [PATCH v5 06/10] dmaengine: tegra: Support address width > 39 bits
From: Akhil R @ 2026-03-30 14:44 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Philipp Zabel, dmaengine, devicetree, linux-tegra, linux-kernel
Cc: Akhil R, Frank Li
In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com>
Tegra264 supports address width of 41 bits. Unlike older SoCs which use
a common high_addr register for upper address bits, Tegra264 has separate
src_high and dst_high registers to accommodate this wider address space.
Add an addr_bits property to the device data structure to specify the
number of address bits supported on each device and use that to program
the appropriate registers.
Update the sg_req struct to remove the high_addr field and use
dma_addr_t for src and dst to store the complete addresses. Extract
the high address bits only when programming the registers.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/tegra186-gpc-dma.c | 83 +++++++++++++++++++++-------------
1 file changed, 52 insertions(+), 31 deletions(-)
diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
index b213c4ae07d2..3ac43ad19ed6 100644
--- a/drivers/dma/tegra186-gpc-dma.c
+++ b/drivers/dma/tegra186-gpc-dma.c
@@ -146,6 +146,7 @@ struct tegra_dma_channel;
*/
struct tegra_dma_chip_data {
bool hw_support_pause;
+ unsigned int addr_bits;
unsigned int nr_channels;
unsigned int channel_reg_size;
unsigned int max_dma_count;
@@ -161,6 +162,8 @@ struct tegra_dma_channel_regs {
u32 src;
u32 dst;
u32 high_addr;
+ u32 src_high;
+ u32 dst_high;
u32 mc_seq;
u32 mmio_seq;
u32 wcount;
@@ -179,10 +182,9 @@ struct tegra_dma_channel_regs {
*/
struct tegra_dma_sg_req {
unsigned int len;
+ dma_addr_t src;
+ dma_addr_t dst;
u32 csr;
- u32 src;
- u32 dst;
- u32 high_addr;
u32 mc_seq;
u32 mmio_seq;
u32 wcount;
@@ -266,6 +268,25 @@ static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
return tdc->vc.chan.device->dev;
}
+static void tegra_dma_program_addr(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req)
+{
+ tdc_write(tdc, tdc->regs->src, lower_32_bits(sg_req->src));
+ tdc_write(tdc, tdc->regs->dst, lower_32_bits(sg_req->dst));
+
+ if (tdc->tdma->chip_data->addr_bits > 39) {
+ tdc_write(tdc, tdc->regs->src_high, upper_32_bits(sg_req->src));
+ tdc_write(tdc, tdc->regs->dst_high, upper_32_bits(sg_req->dst));
+ } else {
+ u32 src_high = FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR,
+ upper_32_bits(sg_req->src));
+ u32 dst_high = FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR,
+ upper_32_bits(sg_req->dst));
+
+ tdc_write(tdc, tdc->regs->high_addr, src_high | dst_high);
+ }
+}
+
static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
{
dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n",
@@ -274,10 +295,20 @@ static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
tdc_read(tdc, tdc->regs->csr),
tdc_read(tdc, tdc->regs->status),
tdc_read(tdc, tdc->regs->csre));
- dev_dbg(tdc2dev(tdc), "SRC %x DST %x HI ADDR %x\n",
- tdc_read(tdc, tdc->regs->src),
- tdc_read(tdc, tdc->regs->dst),
- tdc_read(tdc, tdc->regs->high_addr));
+
+ if (tdc->tdma->chip_data->addr_bits > 39) {
+ dev_dbg(tdc2dev(tdc), "SRC %x SRC HI %x DST %x DST HI %x\n",
+ tdc_read(tdc, tdc->regs->src),
+ tdc_read(tdc, tdc->regs->src_high),
+ tdc_read(tdc, tdc->regs->dst),
+ tdc_read(tdc, tdc->regs->dst_high));
+ } else {
+ dev_dbg(tdc2dev(tdc), "SRC %x DST %x HI ADDR %x\n",
+ tdc_read(tdc, tdc->regs->src),
+ tdc_read(tdc, tdc->regs->dst),
+ tdc_read(tdc, tdc->regs->high_addr));
+ }
+
dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x WSTA %x\n",
tdc_read(tdc, tdc->regs->mc_seq),
tdc_read(tdc, tdc->regs->mmio_seq),
@@ -480,9 +511,7 @@ static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc)
sg_req = &dma_desc->sg_req[dma_desc->sg_idx];
tdc_write(tdc, tdc->regs->wcount, sg_req->wcount);
- tdc_write(tdc, tdc->regs->src, sg_req->src);
- tdc_write(tdc, tdc->regs->dst, sg_req->dst);
- tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr);
+ tegra_dma_program_addr(tdc, sg_req);
/* Start DMA */
tdc_write(tdc, tdc->regs->csr,
@@ -510,11 +539,9 @@ static void tegra_dma_start(struct tegra_dma_channel *tdc)
sg_req = &dma_desc->sg_req[dma_desc->sg_idx];
+ tegra_dma_program_addr(tdc, sg_req);
tdc_write(tdc, tdc->regs->wcount, sg_req->wcount);
tdc_write(tdc, tdc->regs->csr, 0);
- tdc_write(tdc, tdc->regs->src, sg_req->src);
- tdc_write(tdc, tdc->regs->dst, sg_req->dst);
- tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr);
tdc_write(tdc, tdc->regs->fixed_pattern, sg_req->fixed_pattern);
tdc_write(tdc, tdc->regs->mmio_seq, sg_req->mmio_seq);
tdc_write(tdc, tdc->regs->mc_seq, sg_req->mc_seq);
@@ -819,7 +846,7 @@ static unsigned int get_burst_size(struct tegra_dma_channel *tdc,
static int get_transfer_param(struct tegra_dma_channel *tdc,
enum dma_transfer_direction direction,
- u32 *apb_addr,
+ dma_addr_t *apb_addr,
u32 *mmio_seq,
u32 *csr,
unsigned int *burst_size,
@@ -897,11 +924,9 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
dma_desc->bytes_req = len;
dma_desc->sg_count = 1;
sg_req = dma_desc->sg_req;
-
sg_req[0].src = 0;
sg_req[0].dst = dest;
- sg_req[0].high_addr =
- FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+
sg_req[0].fixed_pattern = value;
/* Word count reg takes value as (N +1) words */
sg_req[0].wcount = ((len - 4) >> 2);
@@ -969,10 +994,7 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,
sg_req[0].src = src;
sg_req[0].dst = dest;
- sg_req[0].high_addr =
- FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
- sg_req[0].high_addr |=
- FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+
/* Word count reg takes value as (N +1) words */
sg_req[0].wcount = ((len - 4) >> 2);
sg_req[0].csr = csr;
@@ -992,7 +1014,8 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
enum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED;
- u32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0;
+ u32 csr, mc_seq, mmio_seq = 0;
+ dma_addr_t apb_ptr = 0;
struct tegra_dma_sg_req *sg_req;
struct tegra_dma_desc *dma_desc;
struct scatterlist *sg;
@@ -1080,13 +1103,9 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
if (direction == DMA_MEM_TO_DEV) {
sg_req[i].src = mem;
sg_req[i].dst = apb_ptr;
- sg_req[i].high_addr =
- FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
} else if (direction == DMA_DEV_TO_MEM) {
sg_req[i].src = apb_ptr;
sg_req[i].dst = mem;
- sg_req[i].high_addr =
- FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
}
/*
@@ -1110,7 +1129,8 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_l
unsigned long flags)
{
enum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED;
- u32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0, burst_size;
+ u32 csr, mc_seq, mmio_seq = 0, burst_size;
+ dma_addr_t apb_ptr = 0;
unsigned int max_dma_count, len, period_count, i;
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
struct tegra_dma_desc *dma_desc;
@@ -1201,13 +1221,9 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_l
if (direction == DMA_MEM_TO_DEV) {
sg_req[i].src = mem;
sg_req[i].dst = apb_ptr;
- sg_req[i].high_addr =
- FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
} else if (direction == DMA_DEV_TO_MEM) {
sg_req[i].src = apb_ptr;
sg_req[i].dst = mem;
- sg_req[i].high_addr =
- FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
}
/*
* Word count register takes input in words. Writing a value
@@ -1304,6 +1320,7 @@ static const struct tegra_dma_channel_regs tegra186_reg_offsets = {
static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
.nr_channels = 32,
+ .addr_bits = 39,
.channel_reg_size = SZ_64K,
.max_dma_count = SZ_1G,
.hw_support_pause = false,
@@ -1313,6 +1330,7 @@ static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
.nr_channels = 32,
+ .addr_bits = 39,
.channel_reg_size = SZ_64K,
.max_dma_count = SZ_1G,
.hw_support_pause = true,
@@ -1322,6 +1340,7 @@ static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
static const struct tegra_dma_chip_data tegra234_dma_chip_data = {
.nr_channels = 32,
+ .addr_bits = 39,
.channel_reg_size = SZ_64K,
.max_dma_count = SZ_1G,
.hw_support_pause = true,
@@ -1433,6 +1452,8 @@ static int tegra_dma_probe(struct platform_device *pdev)
tdc->stream_id = stream_id;
}
+ dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(cdata->addr_bits));
+
dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);
--
2.50.1
^ permalink raw reply related
* [PATCH v5 05/10] dmaengine: tegra: Use struct for register offsets
From: Akhil R @ 2026-03-30 14:44 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Philipp Zabel, dmaengine, devicetree, linux-tegra, linux-kernel
Cc: Akhil R, Frank Li
In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com>
Repurpose the struct tegra_dma_channel_regs to define offsets for all the
channel registers. Previously, the struct only held the register values
for each transfer and was wrapped within tegra_dma_sg_req. Move the
values directly into tegra_dma_sg_req and use channel_regs for
storing the register offsets. Update all register reads/writes to use
the struct channel_regs. This prepares for the register offset change
in Tegra264.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/tegra186-gpc-dma.c | 282 +++++++++++++++++----------------
1 file changed, 142 insertions(+), 140 deletions(-)
diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
index a0522a992ebc..b213c4ae07d2 100644
--- a/drivers/dma/tegra186-gpc-dma.c
+++ b/drivers/dma/tegra186-gpc-dma.c
@@ -22,7 +22,6 @@
#include "virt-dma.h"
/* CSR register */
-#define TEGRA_GPCDMA_CHAN_CSR 0x00
#define TEGRA_GPCDMA_CSR_ENB BIT(31)
#define TEGRA_GPCDMA_CSR_IE_EOC BIT(30)
#define TEGRA_GPCDMA_CSR_ONCE BIT(27)
@@ -58,7 +57,6 @@
#define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10)
/* STATUS register */
-#define TEGRA_GPCDMA_CHAN_STATUS 0x004
#define TEGRA_GPCDMA_STATUS_BUSY BIT(31)
#define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30)
#define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28)
@@ -70,22 +68,13 @@
#define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21)
#define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20)
-#define TEGRA_GPCDMA_CHAN_CSRE 0x008
#define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31)
-/* Source address */
-#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C
-
-/* Destination address */
-#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010
-
/* High address pointer */
-#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014
#define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0)
#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16)
/* MC sequence register */
-#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18
#define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31)
#define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25)
#define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23)
@@ -101,7 +90,6 @@
#define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0)
/* MMIO sequence register */
-#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c
#define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31)
#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28)
#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \
@@ -120,17 +108,7 @@
#define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16)
#define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7)
-/* Channel WCOUNT */
-#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20
-
-/* Transfer count */
-#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24
-
-/* DMA byte count status */
-#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28
-
/* Error Status Register */
-#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30
#define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT 8
#define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK 0xF
#define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \
@@ -143,16 +121,6 @@
#define TEGRA_DMA_MC_SLAVE_ERR 0xB
#define TEGRA_DMA_MMIO_SLAVE_ERR 0xA
-/* Fixed Pattern */
-#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34
-
-#define TEGRA_GPCDMA_CHAN_TZ 0x38
-#define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0)
-#define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1)
-
-#define TEGRA_GPCDMA_CHAN_SPARE 0x3c
-#define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16)
-
/*
* If any burst is in flight and DMA paused then this is the time to complete
* on-flight burst and update DMA status register.
@@ -181,18 +149,24 @@ struct tegra_dma_chip_data {
unsigned int nr_channels;
unsigned int channel_reg_size;
unsigned int max_dma_count;
+ const struct tegra_dma_channel_regs *channel_regs;
int (*terminate)(struct tegra_dma_channel *tdc);
};
/* DMA channel registers */
struct tegra_dma_channel_regs {
u32 csr;
- u32 src_ptr;
- u32 dst_ptr;
- u32 high_addr_ptr;
+ u32 status;
+ u32 csre;
+ u32 src;
+ u32 dst;
+ u32 high_addr;
u32 mc_seq;
u32 mmio_seq;
u32 wcount;
+ u32 wxfer;
+ u32 wstatus;
+ u32 err_status;
u32 fixed_pattern;
};
@@ -205,7 +179,14 @@ struct tegra_dma_channel_regs {
*/
struct tegra_dma_sg_req {
unsigned int len;
- struct tegra_dma_channel_regs ch_regs;
+ u32 csr;
+ u32 src;
+ u32 dst;
+ u32 high_addr;
+ u32 mc_seq;
+ u32 mmio_seq;
+ u32 wcount;
+ u32 fixed_pattern;
};
/*
@@ -228,19 +209,20 @@ struct tegra_dma_desc {
* tegra_dma_channel: Channel specific information
*/
struct tegra_dma_channel {
- bool config_init;
- char name[30];
- enum dma_transfer_direction sid_dir;
- enum dma_status status;
- int id;
- int irq;
- int slave_id;
+ const struct tegra_dma_channel_regs *regs;
struct tegra_dma *tdma;
struct virt_dma_chan vc;
struct tegra_dma_desc *dma_desc;
struct dma_slave_config dma_sconfig;
+ enum dma_transfer_direction sid_dir;
+ enum dma_status status;
unsigned int stream_id;
unsigned long chan_base_offset;
+ bool config_init;
+ char name[30];
+ int id;
+ int irq;
+ int slave_id;
};
/*
@@ -288,22 +270,22 @@ static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
{
dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n",
tdc->id, tdc->name);
- dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n",
- tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),
- tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),
- tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),
- tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),
- tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)
- );
- dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n",
- tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),
- tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),
- tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),
- tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),
- tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)
- );
+ dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x\n",
+ tdc_read(tdc, tdc->regs->csr),
+ tdc_read(tdc, tdc->regs->status),
+ tdc_read(tdc, tdc->regs->csre));
+ dev_dbg(tdc2dev(tdc), "SRC %x DST %x HI ADDR %x\n",
+ tdc_read(tdc, tdc->regs->src),
+ tdc_read(tdc, tdc->regs->dst),
+ tdc_read(tdc, tdc->regs->high_addr));
+ dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x WSTA %x\n",
+ tdc_read(tdc, tdc->regs->mc_seq),
+ tdc_read(tdc, tdc->regs->mmio_seq),
+ tdc_read(tdc, tdc->regs->wcount),
+ tdc_read(tdc, tdc->regs->wxfer),
+ tdc_read(tdc, tdc->regs->wstatus));
dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n",
- tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));
+ tdc_read(tdc, tdc->regs->err_status));
}
static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc,
@@ -377,13 +359,13 @@ static int tegra_dma_pause(struct tegra_dma_channel *tdc)
int ret;
u32 val;
- val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);
+ val = tdc_read(tdc, tdc->regs->csre);
val |= TEGRA_GPCDMA_CHAN_CSRE_PAUSE;
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);
+ tdc_write(tdc, tdc->regs->csre, val);
/* Wait until busy bit is de-asserted */
ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
- tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
+ tdc->chan_base_offset + tdc->regs->status,
val,
!(val & TEGRA_GPCDMA_STATUS_BUSY),
TEGRA_GPCDMA_BURST_COMPLETE_TIME,
@@ -419,9 +401,9 @@ static void tegra_dma_resume(struct tegra_dma_channel *tdc)
{
u32 val;
- val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);
+ val = tdc_read(tdc, tdc->regs->csre);
val &= ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE;
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);
+ tdc_write(tdc, tdc->regs->csre, val);
tdc->status = DMA_IN_PROGRESS;
}
@@ -456,27 +438,27 @@ static void tegra_dma_disable(struct tegra_dma_channel *tdc)
{
u32 csr, status;
- csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+ csr = tdc_read(tdc, tdc->regs->csr);
/* Disable interrupts */
csr &= ~TEGRA_GPCDMA_CSR_IE_EOC;
/* Disable DMA */
csr &= ~TEGRA_GPCDMA_CSR_ENB;
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+ tdc_write(tdc, tdc->regs->csr, csr);
/* Clear interrupt status if it is there */
- status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ status = tdc_read(tdc, tdc->regs->status);
if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);
+ tdc_write(tdc, tdc->regs->status, status);
}
}
static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc)
{
struct tegra_dma_desc *dma_desc = tdc->dma_desc;
- struct tegra_dma_channel_regs *ch_regs;
+ struct tegra_dma_sg_req *sg_req;
int ret;
u32 val;
@@ -488,29 +470,29 @@ static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc)
/* Configure next transfer immediately after DMA is busy */
ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
- tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
+ tdc->chan_base_offset + tdc->regs->status,
val,
(val & TEGRA_GPCDMA_STATUS_BUSY), 0,
TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
if (ret)
return;
- ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs;
+ sg_req = &dma_desc->sg_req[dma_desc->sg_idx];
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
+ tdc_write(tdc, tdc->regs->wcount, sg_req->wcount);
+ tdc_write(tdc, tdc->regs->src, sg_req->src);
+ tdc_write(tdc, tdc->regs->dst, sg_req->dst);
+ tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr);
/* Start DMA */
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
- ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);
+ tdc_write(tdc, tdc->regs->csr,
+ sg_req->csr | TEGRA_GPCDMA_CSR_ENB);
}
static void tegra_dma_start(struct tegra_dma_channel *tdc)
{
struct tegra_dma_desc *dma_desc = tdc->dma_desc;
- struct tegra_dma_channel_regs *ch_regs;
+ struct tegra_dma_sg_req *sg_req;
struct virt_dma_desc *vdesc;
if (!dma_desc) {
@@ -526,21 +508,21 @@ static void tegra_dma_start(struct tegra_dma_channel *tdc)
tegra_dma_resume(tdc);
}
- ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs;
+ sg_req = &dma_desc->sg_req[dma_desc->sg_idx];
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);
+ tdc_write(tdc, tdc->regs->wcount, sg_req->wcount);
+ tdc_write(tdc, tdc->regs->csr, 0);
+ tdc_write(tdc, tdc->regs->src, sg_req->src);
+ tdc_write(tdc, tdc->regs->dst, sg_req->dst);
+ tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr);
+ tdc_write(tdc, tdc->regs->fixed_pattern, sg_req->fixed_pattern);
+ tdc_write(tdc, tdc->regs->mmio_seq, sg_req->mmio_seq);
+ tdc_write(tdc, tdc->regs->mc_seq, sg_req->mc_seq);
+ tdc_write(tdc, tdc->regs->csr, sg_req->csr);
/* Start DMA */
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
- ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);
+ tdc_write(tdc, tdc->regs->csr,
+ sg_req->csr | TEGRA_GPCDMA_CSR_ENB);
}
static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc)
@@ -601,19 +583,19 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
u32 status;
/* Check channel error status register */
- status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
+ status = tdc_read(tdc, tdc->regs->err_status);
if (status) {
tegra_dma_chan_decode_error(tdc, status);
tegra_dma_dump_chan_regs(tdc);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
+ tdc_write(tdc, tdc->regs->err_status, 0xFFFFFFFF);
}
spin_lock(&tdc->vc.lock);
- status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ status = tdc_read(tdc, tdc->regs->status);
if (!(status & TEGRA_GPCDMA_STATUS_ISE_EOC))
goto irq_done;
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
+ tdc_write(tdc, tdc->regs->status,
TEGRA_GPCDMA_STATUS_ISE_EOC);
if (!dma_desc)
@@ -673,10 +655,10 @@ static int tegra_dma_stop_client(struct tegra_dma_channel *tdc)
* to stop DMA engine from starting any more bursts for
* the given client and wait for in flight bursts to complete
*/
- csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+ csr = tdc_read(tdc, tdc->regs->csr);
csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);
csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+ tdc_write(tdc, tdc->regs->csr, csr);
/* Wait for in flight data transfer to finish */
udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME);
@@ -687,7 +669,7 @@ static int tegra_dma_stop_client(struct tegra_dma_channel *tdc)
ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
tdc->chan_base_offset +
- TEGRA_GPCDMA_CHAN_STATUS,
+ tdc->regs->status,
status,
!(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX |
TEGRA_GPCDMA_STATUS_CHANNEL_RX)),
@@ -739,14 +721,14 @@ static int tegra_dma_get_residual(struct tegra_dma_channel *tdc)
unsigned int bytes_xfer, residual;
u32 wcount = 0, status;
- wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
+ wcount = tdc_read(tdc, tdc->regs->wxfer);
/*
* Set wcount = 0 if EOC bit is set. The transfer would have
* already completed and the CHAN_XFER_COUNT could have updated
* for the next transfer, specifically in case of cyclic transfers.
*/
- status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ status = tdc_read(tdc, tdc->regs->status);
if (status & TEGRA_GPCDMA_STATUS_ISE_EOC)
wcount = 0;
@@ -893,7 +875,7 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
/* Configure default priority weight for the channel */
csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
- mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ mc_seq = tdc_read(tdc, tdc->regs->mc_seq);
/* retain stream-id and clean rest */
mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
@@ -916,16 +898,16 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
dma_desc->sg_count = 1;
sg_req = dma_desc->sg_req;
- sg_req[0].ch_regs.src_ptr = 0;
- sg_req[0].ch_regs.dst_ptr = dest;
- sg_req[0].ch_regs.high_addr_ptr =
+ sg_req[0].src = 0;
+ sg_req[0].dst = dest;
+ sg_req[0].high_addr =
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
- sg_req[0].ch_regs.fixed_pattern = value;
+ sg_req[0].fixed_pattern = value;
/* Word count reg takes value as (N +1) words */
- sg_req[0].ch_regs.wcount = ((len - 4) >> 2);
- sg_req[0].ch_regs.csr = csr;
- sg_req[0].ch_regs.mmio_seq = 0;
- sg_req[0].ch_regs.mc_seq = mc_seq;
+ sg_req[0].wcount = ((len - 4) >> 2);
+ sg_req[0].csr = csr;
+ sg_req[0].mmio_seq = 0;
+ sg_req[0].mc_seq = mc_seq;
sg_req[0].len = len;
dma_desc->cyclic = false;
@@ -961,7 +943,7 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,
/* Configure default priority weight for the channel */
csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
- mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ mc_seq = tdc_read(tdc, tdc->regs->mc_seq);
/* retain stream-id and clean rest */
mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) |
(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
@@ -985,17 +967,17 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,
dma_desc->sg_count = 1;
sg_req = dma_desc->sg_req;
- sg_req[0].ch_regs.src_ptr = src;
- sg_req[0].ch_regs.dst_ptr = dest;
- sg_req[0].ch_regs.high_addr_ptr =
+ sg_req[0].src = src;
+ sg_req[0].dst = dest;
+ sg_req[0].high_addr =
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
- sg_req[0].ch_regs.high_addr_ptr |=
+ sg_req[0].high_addr |=
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
/* Word count reg takes value as (N +1) words */
- sg_req[0].ch_regs.wcount = ((len - 4) >> 2);
- sg_req[0].ch_regs.csr = csr;
- sg_req[0].ch_regs.mmio_seq = 0;
- sg_req[0].ch_regs.mc_seq = mc_seq;
+ sg_req[0].wcount = ((len - 4) >> 2);
+ sg_req[0].csr = csr;
+ sg_req[0].mmio_seq = 0;
+ sg_req[0].mc_seq = mc_seq;
sg_req[0].len = len;
dma_desc->cyclic = false;
@@ -1049,7 +1031,7 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
if (flags & DMA_PREP_INTERRUPT)
csr |= TEGRA_GPCDMA_CSR_IE_EOC;
- mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ mc_seq = tdc_read(tdc, tdc->regs->mc_seq);
/* retain stream-id and clean rest */
mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
@@ -1096,14 +1078,14 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
dma_desc->bytes_req += len;
if (direction == DMA_MEM_TO_DEV) {
- sg_req[i].ch_regs.src_ptr = mem;
- sg_req[i].ch_regs.dst_ptr = apb_ptr;
- sg_req[i].ch_regs.high_addr_ptr =
+ sg_req[i].src = mem;
+ sg_req[i].dst = apb_ptr;
+ sg_req[i].high_addr =
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
} else if (direction == DMA_DEV_TO_MEM) {
- sg_req[i].ch_regs.src_ptr = apb_ptr;
- sg_req[i].ch_regs.dst_ptr = mem;
- sg_req[i].ch_regs.high_addr_ptr =
+ sg_req[i].src = apb_ptr;
+ sg_req[i].dst = mem;
+ sg_req[i].high_addr =
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
}
@@ -1111,10 +1093,10 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
* Word count register takes input in words. Writing a value
* of N into word count register means a req of (N+1) words.
*/
- sg_req[i].ch_regs.wcount = ((len - 4) >> 2);
- sg_req[i].ch_regs.csr = csr;
- sg_req[i].ch_regs.mmio_seq = mmio_seq;
- sg_req[i].ch_regs.mc_seq = mc_seq;
+ sg_req[i].wcount = ((len - 4) >> 2);
+ sg_req[i].csr = csr;
+ sg_req[i].mmio_seq = mmio_seq;
+ sg_req[i].mc_seq = mc_seq;
sg_req[i].len = len;
}
@@ -1186,7 +1168,7 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_l
mmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1);
- mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ mc_seq = tdc_read(tdc, tdc->regs->mc_seq);
/* retain stream-id and clean rest */
mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
@@ -1217,24 +1199,24 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_l
for (i = 0; i < period_count; i++) {
mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
if (direction == DMA_MEM_TO_DEV) {
- sg_req[i].ch_regs.src_ptr = mem;
- sg_req[i].ch_regs.dst_ptr = apb_ptr;
- sg_req[i].ch_regs.high_addr_ptr =
+ sg_req[i].src = mem;
+ sg_req[i].dst = apb_ptr;
+ sg_req[i].high_addr =
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
} else if (direction == DMA_DEV_TO_MEM) {
- sg_req[i].ch_regs.src_ptr = apb_ptr;
- sg_req[i].ch_regs.dst_ptr = mem;
- sg_req[i].ch_regs.high_addr_ptr =
+ sg_req[i].src = apb_ptr;
+ sg_req[i].dst = mem;
+ sg_req[i].high_addr =
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
}
/*
* Word count register takes input in words. Writing a value
* of N into word count register means a req of (N+1) words.
*/
- sg_req[i].ch_regs.wcount = ((len - 4) >> 2);
- sg_req[i].ch_regs.csr = csr;
- sg_req[i].ch_regs.mmio_seq = mmio_seq;
- sg_req[i].ch_regs.mc_seq = mc_seq;
+ sg_req[i].wcount = ((len - 4) >> 2);
+ sg_req[i].csr = csr;
+ sg_req[i].mmio_seq = mmio_seq;
+ sg_req[i].mc_seq = mc_seq;
sg_req[i].len = len;
mem += len;
@@ -1304,11 +1286,28 @@ static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
return chan;
}
+static const struct tegra_dma_channel_regs tegra186_reg_offsets = {
+ .csr = 0x0,
+ .status = 0x4,
+ .csre = 0x8,
+ .src = 0xc,
+ .dst = 0x10,
+ .high_addr = 0x14,
+ .mc_seq = 0x18,
+ .mmio_seq = 0x1c,
+ .wcount = 0x20,
+ .wxfer = 0x24,
+ .wstatus = 0x28,
+ .err_status = 0x30,
+ .fixed_pattern = 0x34,
+};
+
static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
.nr_channels = 32,
.channel_reg_size = SZ_64K,
.max_dma_count = SZ_1G,
.hw_support_pause = false,
+ .channel_regs = &tegra186_reg_offsets,
.terminate = tegra_dma_stop_client,
};
@@ -1317,6 +1316,7 @@ static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
.channel_reg_size = SZ_64K,
.max_dma_count = SZ_1G,
.hw_support_pause = true,
+ .channel_regs = &tegra186_reg_offsets,
.terminate = tegra_dma_pause,
};
@@ -1325,6 +1325,7 @@ static const struct tegra_dma_chip_data tegra234_dma_chip_data = {
.channel_reg_size = SZ_64K,
.max_dma_count = SZ_1G,
.hw_support_pause = true,
+ .channel_regs = &tegra186_reg_offsets,
.terminate = tegra_dma_pause_noerr,
};
@@ -1345,7 +1346,7 @@ MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id)
{
- unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ unsigned int reg_val = tdc_read(tdc, tdc->regs->mc_seq);
reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK);
reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
@@ -1353,7 +1354,7 @@ static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id)
reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id);
reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id);
- tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);
+ tdc_write(tdc, tdc->regs->mc_seq, reg_val);
return 0;
}
@@ -1419,6 +1420,7 @@ static int tegra_dma_probe(struct platform_device *pdev)
tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET +
i * cdata->channel_reg_size;
snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);
+ tdc->regs = cdata->channel_regs;
tdc->tdma = tdma;
tdc->id = i;
tdc->slave_id = -1;
--
2.50.1
^ permalink raw reply related
* [PATCH v5 04/10] dmaengine: tegra: Make reset control optional
From: Akhil R @ 2026-03-30 14:44 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Philipp Zabel, dmaengine, devicetree, linux-tegra, linux-kernel
Cc: Akhil R, Frank Li
In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com>
On Tegra264, reset is not available for the driver to control as
this is handled by the boot firmware. Hence make the reset control
optional and update the error message to reflect the correct error.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/tegra186-gpc-dma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
index 5948fbf32c21..a0522a992ebc 100644
--- a/drivers/dma/tegra186-gpc-dma.c
+++ b/drivers/dma/tegra186-gpc-dma.c
@@ -1381,10 +1381,10 @@ static int tegra_dma_probe(struct platform_device *pdev)
if (IS_ERR(tdma->base_addr))
return PTR_ERR(tdma->base_addr);
- tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
+ tdma->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, "gpcdma");
if (IS_ERR(tdma->rst)) {
return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst),
- "Missing controller reset\n");
+ "Failed to get controller reset\n");
}
reset_control_reset(tdma->rst);
--
2.50.1
^ permalink raw reply related
* [PATCH v5 03/10] dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property
From: Akhil R @ 2026-03-30 14:44 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Philipp Zabel, dmaengine, devicetree, linux-tegra, linux-kernel
Cc: Akhil R
In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com>
Add iommu-map property to specify separate stream IDs for each DMA
channel. This enables each channel to be in its own IOMMU domain,
keeping memory isolated from other devices sharing the same DMA
controller.
Define the constraints such that if the channel and stream IDs are
contiguous, a single entry can map all the channels, but if the
channels or stream IDs are non-contiguous support multiple entries.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
.../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
index 64f1e9d9896d..bc093c783d98 100644
--- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
@@ -14,6 +14,7 @@ description: |
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Rajesh Gumasta <rgumasta@nvidia.com>
+ - Akhil R <akhilrajeev@nvidia.com>
properties:
compatible:
@@ -49,6 +50,14 @@ properties:
iommus:
maxItems: 1
+ iommu-map:
+ description:
+ Maps DMA channel numbers to IOMMU stream IDs. A single entry can map all
+ channels when stream IDs are contiguous. In systems where the channels or
+ stream IDs are not contiguous, multiple entries may be needed.
+ minItems: 1
+ maxItems: 32
+
dma-coherent: true
dma-channel-mask:
--
2.50.1
^ permalink raw reply related
* [PATCH v5 02/10] arm64: tegra: Remove fallback compatible for GPCDMA
From: Akhil R @ 2026-03-30 14:44 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Philipp Zabel, dmaengine, devicetree, linux-tegra, linux-kernel
Cc: Akhil R
In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com>
Remove the fallback compatible string "nvidia,tegra186-gpcdma" for GPCDMA
in Tegra264. Tegra186 compatible cannot work on Tegra264 because of the
register offset changes and absence of the reset property.
Fixes: 65ef237e4810 ("arm64: tegra: Add Tegra264 support")
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 24cc2c51a272..af077420d7d9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3208,7 +3208,7 @@ agic_page5: interrupt-controller@99b0000 {
};
gpcdma: dma-controller@8400000 {
- compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma";
+ compatible = "nvidia,tegra264-gpcdma";
reg = <0x0 0x08400000 0x0 0x210000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
--
2.50.1
^ permalink raw reply related
* [PATCH v5 01/10] dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional
From: Akhil R @ 2026-03-30 14:44 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Philipp Zabel, dmaengine, devicetree, linux-tegra, linux-kernel
Cc: Akhil R
In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com>
On Tegra264, GPCDMA reset control is not exposed to Linux and is handled
by the boot firmware.
Although reset was not exposed in Tegra234 as well, the firmware supported
a dummy reset which just returns success on reset without doing an actual
reset. This is also not supported in Tegra264 BPMP. Therefore mark 'reset'
and 'reset-names' properties as required only for devices prior to
Tegra264.
This also necessitates that the Tegra264 compatible be standalone and
cannot have the fallback compatible of Tegra186. Since there is no
functional impact, we keep reset as required for Tegra234 to avoid
breaking the ABI.
Fixes: bb8c97571db5 ("dt-bindings: dma: Add Tegra264 compatible string")
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 23 +++++++++++++------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
index 0dabe9bbb219..64f1e9d9896d 100644
--- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
@@ -15,16 +15,14 @@ maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Rajesh Gumasta <rgumasta@nvidia.com>
-allOf:
- - $ref: dma-controller.yaml#
-
properties:
compatible:
oneOf:
- - const: nvidia,tegra186-gpcdma
+ - enum:
+ - nvidia,tegra264-gpcdma
+ - nvidia,tegra186-gpcdma
- items:
- enum:
- - nvidia,tegra264-gpcdma
- nvidia,tegra234-gpcdma
- nvidia,tegra194-gpcdma
- const: nvidia,tegra186-gpcdma
@@ -60,12 +58,23 @@ required:
- compatible
- reg
- interrupts
- - resets
- - reset-names
- "#dma-cells"
- iommus
- dma-channel-mask
+allOf:
+ - $ref: dma-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra186-gpcdma
+ then:
+ required:
+ - resets
+ - reset-names
+
additionalProperties: false
examples:
--
2.50.1
^ permalink raw reply related
* [PATCH v5 00/10] Add GPCDMA support in Tegra264
From: Akhil R @ 2026-03-30 14:44 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Philipp Zabel, dmaengine, devicetree, linux-tegra, linux-kernel
Cc: Akhil R
This series adds support for GPCDMA in Tegra264 with additional
support for separate stream ID for each channel. Tegra264 GPCDMA
controller has changes in the register offsets and uses 41-bit
addressing for memory. Add changes in the tegra186-gpc-dma driver
to support these.
v4->v5:
- Use dev_err_probe() when returning error from the probe function.
- Remove tegra194 and tegra234 compatible from the reset 'if' condition
in the bindings as suggested in v2 (which I missed).
v3->v4:
- Split device tree changes to two patches.
- Reordered patches to have fixes first.
- Added fixes tag to dt-bindings and device tree changes.
v2->v3:
- Add description for iommu-map property and update commit descriptions.
- Use enum for compatible string instead of const.
- Remove unused registers from struct tegra_dma_channel_regs.
- Use devm_of_dma_controller_register() to register the DMA controller.
- Remove return value check for mask setting in the driver as the bitmask
value is always greater than 32.
v1->v2:
- Fix dt_bindings_check warnings
- Drop fallback compatible "nvidia,tegra186-gpcdma" from Tegra264 DT
- Use dma_addr_t for sg_req src/dst fields and drop separate high_add
variable and check for the addr_bits only when programming the
registers.
- Update address width to 39 bits for Tegra234 and before since the SMMU
supports only up to 39 bits till Tegra234.
- Add a patch to do managed DMA controller registration.
- Describe the second iteration in the probe.
- Update commit descriptions.
Akhil R (10):
dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional
arm64: tegra: Remove fallback compatible for GPCDMA
dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property
dmaengine: tegra: Make reset control optional
dmaengine: tegra: Use struct for register offsets
dmaengine: tegra: Support address width > 39 bits
dmaengine: tegra: Use managed DMA controller registration
dmaengine: tegra: Use iommu-map for stream ID
dmaengine: tegra: Add Tegra264 support
arm64: tegra: Enable GPCDMA in Tegra264 and add iommu-map
.../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 32 +-
.../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 4 +
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 3 +-
drivers/dma/tegra186-gpc-dma.c | 433 +++++++++++-------
4 files changed, 288 insertions(+), 184 deletions(-)
--
2.50.1
^ permalink raw reply
* Re: [PATCH v7 3/3] soc: qcom: ice: Set ICE clk to TURBO on probe
From: Harshal Dev @ 2026-03-30 14:44 UTC (permalink / raw)
To: Abhinaba Rakshit, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Manivannan Sadhasivam, James E.J. Bottomley, Martin K. Petersen,
Neeraj Soni
Cc: linux-arm-msm, linux-crypto, devicetree, linux-kernel, linux-scsi,
Konrad Dybcio
In-Reply-To: <acF0ggIIJFb7mUUR@hu-arakshit-hyd.qualcomm.com>
On 3/23/2026 10:42 PM, Abhinaba Rakshit wrote:
> On Mon, Mar 02, 2026 at 04:19:15PM +0530, Abhinaba Rakshit wrote:
>> MMC controller lacks a clock scaling mechanism, unlike the UFS
>> controller. By default, the MMC controller is set to TURBO mode
>> during probe, but the ICE clock remains at XO frequency,
>> leading to read/write performance degradation on eMMC.
>>
>> To address this, set the ICE clock to TURBO during probe to
>> align it with the controller clock. This ensures consistent
>> performance and avoids mismatches between the controller
>> and ICE clock frequencies.
>>
>> For platforms where ICE is represented as a separate device,
>> use the OPP framework to vote for TURBO mode, maintaining
>> proper voltage and power domain constraints.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
>> ---
>> drivers/soc/qcom/ice.c | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
>> index 7976a18d9a4cda1ad6b62b66ce011e244d0f6856..e8ee02a709574afa4ebb8e4395a8d899bf1d4976 100644
>> --- a/drivers/soc/qcom/ice.c
>> +++ b/drivers/soc/qcom/ice.c
>> @@ -659,6 +659,13 @@ static struct qcom_ice *qcom_ice_create(struct device *dev,
>> dev_info(dev, "ICE OPP table is not registered, please update your DT\n");
>> }
>>
>> + if (engine->has_opp) {
>> + /* Vote for maximum clock rate for maximum performance */
>> + err = dev_pm_opp_set_rate(dev, INT_MAX);
>> + if (err)
>> + dev_warn(dev, "Failed boosting the ICE clk to TURBO\n");
>> + }
>> +
>> engine->core_clk_freq = clk_get_rate(engine->core_clk);
>> if (!qcom_ice_check_supported(engine))
>> return ERR_PTR(-EOPNOTSUPP);
>
> Hi Konrad
>
> Since you previously reviewed this change, I wanted to share an improved approach
> that I recently realized for handling ICE clock scaling in the MMC use‑case.
>
> So far, we have been voting for the maximum frequency during the ICE device probe
> to align with MMC requirements.
> But because the ICE probe is common across different storage clients, applying
> the MAX vote at probe time may unintentionally impact other storage paths.
>
> Now that we have a generic scaling API exposed, we can make this logic
> MMC‑specific instead. In particular, within sdhci_msm_ice_init().
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/mmc/host/sdhci-msm.c#n1966,
> we can invoke: qcom_ice_scale_clk(ice, INT_MAX, false);
>
I agree, this is better instead of blindly turning the clk freq to maximum.
I was about to ask you to move this to qcom_ice_probe() as per comments in previous
commit. However, since you have mentioned this now, I suggest adding a call in
sdhci_msm_ice_init() to qcom_ice_clk_scale() immediately after it calls qcom_ice_create().
Regards,
Harshal
> This ensures the MAX clock vote is applied only in the MMC context,
> without altering behavior for other storage clients relying on the ICE driver.
>
> I believe this results in a cleaner and correctly scoped design.
> Let me know your thoughts.
>
> Abhinaba Rakshit
>
^ permalink raw reply
* Re: [PATCH 2/2 v2] devicetree: spi: add spi-mosi-idle-low property support
From: Mark Brown @ 2026-03-30 14:41 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: charles-antoine.couret, robh, krzk+dt, conor+dt, linux-spi,
devicetree, linux-kernel
In-Reply-To: <20260330-invisible-rich-ant-e7fdab@quoll>
[-- Attachment #1: Type: text/plain, Size: 429 bytes --]
On Mon, Mar 30, 2026 at 09:16:56AM +0200, Krzysztof Kozlowski wrote:
> On Sun, Mar 29, 2026 at 02:58:32PM +0200, charles-antoine.couret@mind.be wrote:
> > This flag means that device requires the MOSI line to be low
> > when it's in idle state.
> There is no patch 1/2 here, even on mailing lists, so probably this has
> messed threading.
Yes: https://lore.kernel.org/r/20260329125725.2984756-1-charles-antoine.couret@mind.be
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH v1 1/1] arm64: dts: imx91-var-dart-sonata: add RGB select supply for PCA6408
From: Frank Li @ 2026-03-30 14:40 UTC (permalink / raw)
To: Stefano Radaelli
Cc: linux-kernel, devicetree, imx, linux-arm-kernel, pierluigi.p,
Stefano Radaelli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
In-Reply-To: <acoxJ3KUVHqIR1yQ@Lord-Beerus.station>
On Mon, Mar 30, 2026 at 10:15:35AM +0200, Stefano Radaelli wrote:
> Hi Frank,
>
> On Fri, Mar 27, 2026 at 02:41:21PM -0400, Frank Li wrote:
> >
> > Accroding to signal name, it is MUX chip select signal. Of couse it may
> > connect to a buffer's EN pin. I have not checked your schematic.
> >
> > If it connect to MUX chip or some select signal, it should use above method,
> > even though it is permanently asserted when access PCA6408.
> >
> > If it connect to EN pin of buffer, regualtor should be good.
> >
>
> Yes, it is exactly the second case!
> It's just an EN pin, that enables a buffer to route RGB signals used on
> the DART-MX91 som only.
> That's why I think regulator is the right way for this case.
Okay, it'd better to emphrase it in commit message because _SEL is miss
leasing.
Frank
>
> Best Regards,
> Stefano
^ permalink raw reply
* Re: [PATCH v7 2/3] ufs: host: Add ICE clock scaling during UFS clock changes
From: Harshal Dev @ 2026-03-30 14:39 UTC (permalink / raw)
To: Abhinaba Rakshit, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Manivannan Sadhasivam, James E.J. Bottomley, Martin K. Petersen,
Neeraj Soni
Cc: linux-arm-msm, linux-crypto, devicetree, linux-kernel, linux-scsi
In-Reply-To: <20260302-enable-ufs-ice-clock-scaling-v7-2-669b96ecadd8@oss.qualcomm.com>
Hi Abhinaba,
On 3/2/2026 4:19 PM, Abhinaba Rakshit wrote:
> Implement ICE (Inline Crypto Engine) clock scaling in sync with
> UFS controller clock scaling. This ensures that the ICE operates at
> an appropriate frequency when the UFS clocks are scaled up or down,
> improving performance and maintaining stability for crypto operations.
>
> For scale_up operation ensure to pass ~round_ceil (round_floor)
> and vice-versa for scale_down operations.
>
> Incase of OPP scaling is not supported by ICE, ensure to not prevent
> devfreq for UFS, as ICE OPP-table is optional.
>
> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> ---
> drivers/ufs/host/ufs-qcom.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 8d119b3223cbdaa3297d2beabced0962a1a847d5..776444f46fe5f00f947e4b0b4dfe6d64e2ad2150 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -305,6 +305,15 @@ static int ufs_qcom_ice_prepare_key(struct blk_crypto_profile *profile,
> return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key);
> }
>
> +static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned long target_freq,
> + bool round_ceil)
> +{
> + if (host->hba->caps & UFSHCD_CAP_CRYPTO)
> + return qcom_ice_scale_clk(host->ice, target_freq, round_ceil);
> +
> + return 0;
> +}
> +
> static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = {
> .keyslot_program = ufs_qcom_ice_keyslot_program,
> .keyslot_evict = ufs_qcom_ice_keyslot_evict,
> @@ -339,6 +348,12 @@ static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host)
> {
> }
>
> +static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned long target_freq,
> + bool round_ceil)
> +{
> + return 0;
> +}
> +
> #endif
>
> static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
> @@ -1646,8 +1661,10 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
> else
> err = ufs_qcom_clk_scale_down_post_change(hba, target_freq);
>
> + if (!err)
> + err = ufs_qcom_ice_scale_clk(host, target_freq, !scale_up);
>
> - if (err) {
> + if (err && err != -EOPNOTSUPP) {
Using -EOPNOTSUPP here works fine for now. But anyone touching any of the lower APIs called by
ufs_qcom_clk_scale_up/down_post_change() needs to ensure they don't return -EOPNOTSUPP, otherwise
hibernate exit will be skipped. So this carries a minor risk of breaking.
Since regardless of whether ufs_qcom_clk_scale_up/down_post_change() fails or ufs_qcom_ice_scale_clk()
fails, we exit from hibernate and return from this function, I suggest you handle the error for ice_scale
separately.
> ufshcd_uic_hibern8_exit(hba);
> return err;
> }
>
Add the call to ufs_qcom_ice_scale_clk() along with error handle here, and let the above error handle
remain untouched.
err = ufs_qcom_ice_scale_clk(host, target_freq, !scale_up);
if (err && err != -EOPNOTSUPP) {
ufshcd_uic_hibern8_exit(hba);
return err;
}
Regards,
Harshal
^ permalink raw reply
* Re: [PATCH v7 1/3] soc: qcom: ice: Add OPP-based clock scaling support for ICE
From: Harshal Dev @ 2026-03-30 14:39 UTC (permalink / raw)
To: Abhinaba Rakshit, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Manivannan Sadhasivam, James E.J. Bottomley, Martin K. Petersen,
Neeraj Soni
Cc: linux-arm-msm, linux-crypto, devicetree, linux-kernel, linux-scsi
In-Reply-To: <20260302-enable-ufs-ice-clock-scaling-v7-1-669b96ecadd8@oss.qualcomm.com>
Hi Abhinaba,
On 3/2/2026 4:19 PM, Abhinaba Rakshit wrote:
> Register optional operation-points-v2 table for ICE device
> during device probe.
>
> Introduce clock scaling API qcom_ice_scale_clk which scale ICE
> core clock based on the target frequency provided and if a valid
> OPP-table is registered. Use round_ceil passed to decide on the
> rounding of the clock freq against OPP-table. Disable clock scaling
> if OPP-table is not registered.
>
> When an ICE-device specific OPP table is available, use the PM OPP
> framework to manage frequency scaling and maintain proper power-domain
> constraints.
>
> Also, ensure to drop the votes in suspend to prevent power/thermal
> retention. Subsequently restore the frequency in resume from
> core_clk_freq which stores the last ICE core clock operating frequency.
>
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> ---
> drivers/soc/qcom/ice.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++++--
> include/soc/qcom/ice.h | 2 ++
> 2 files changed, 81 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
> index b203bc685cadd21d6f96eb1799963a13db4b2b72..7976a18d9a4cda1ad6b62b66ce011e244d0f6856 100644
> --- a/drivers/soc/qcom/ice.c
> +++ b/drivers/soc/qcom/ice.c
> @@ -16,6 +16,7 @@
> #include <linux/of.h>
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
>
> #include <linux/firmware/qcom/qcom_scm.h>
>
> @@ -111,6 +112,8 @@ struct qcom_ice {
> bool use_hwkm;
> bool hwkm_init_complete;
> u8 hwkm_version;
> + unsigned long core_clk_freq;
> + bool has_opp;
> };
>
> static bool qcom_ice_check_supported(struct qcom_ice *ice)
> @@ -310,6 +313,10 @@ int qcom_ice_resume(struct qcom_ice *ice)
> struct device *dev = ice->dev;
> int err;
>
> + /* Restore the ICE core clk freq */
> + if (ice->has_opp && ice->core_clk_freq)
> + dev_pm_opp_set_rate(ice->dev, ice->core_clk_freq);
> +
> err = clk_prepare_enable(ice->core_clk);
> if (err) {
> dev_err(dev, "failed to enable core clock (%d)\n",
> @@ -324,6 +331,11 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume);
> int qcom_ice_suspend(struct qcom_ice *ice)
> {
> clk_disable_unprepare(ice->core_clk);
> +
> + /* Drop the clock votes while suspend */
> + if (ice->has_opp)
> + dev_pm_opp_set_rate(ice->dev, 0);
> +
> ice->hwkm_init_complete = false;
>
> return 0;
> @@ -549,10 +561,54 @@ int qcom_ice_import_key(struct qcom_ice *ice,
> }
> EXPORT_SYMBOL_GPL(qcom_ice_import_key);
>
> +/**
> + * qcom_ice_scale_clk() - Scale ICE clock for DVFS-aware operations
> + * @ice: ICE driver data
> + * @target_freq: requested frequency in Hz
> + * @round_ceil: when true, selects nearest freq >= @target_freq;
> + * otherwise, selects nearest freq <= @target_freq
> + *
> + * Selects an OPP frequency based on @target_freq and the rounding direction
> + * specified by @round_ceil, then programs it using dev_pm_opp_set_rate(),
> + * including any voltage or power-domain transitions handled by the OPP
> + * framework. Updates ice->core_clk_freq on success.
> + *
> + * Return: 0 on success; -EOPNOTSUPP if no OPP table; -EINVAL in-case of
> + * incorrect flags; or error from dev_pm_opp_set_rate()/OPP lookup.
> + */
> +int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq,
> + bool round_ceil)
Any particular reason for choosing round_ceil? Using round_floor would have
saved the need for caller to pass negation of scale_up.
> +{
> + unsigned long ice_freq = target_freq;
> + struct dev_pm_opp *opp;
> + int ret;
> +
> + if (!ice->has_opp)
> + return -EOPNOTSUPP;
> +
> + if (round_ceil)
> + opp = dev_pm_opp_find_freq_ceil(ice->dev, &ice_freq);
> + else
> + opp = dev_pm_opp_find_freq_floor(ice->dev, &ice_freq);
> +
> + if (IS_ERR(opp))
> + return PTR_ERR(opp);
> + dev_pm_opp_put(opp);
> +
> + ret = dev_pm_opp_set_rate(ice->dev, ice_freq);
> + if (!ret)
> + ice->core_clk_freq = ice_freq;
Nit: Follow same error handling pattern everywhere in the driver.
if (ret) {
dev_err(dev, "error");
return ret;
}
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(qcom_ice_scale_clk);
> +
> static struct qcom_ice *qcom_ice_create(struct device *dev,
> - void __iomem *base)
> + void __iomem *base,
> + bool is_legacy_binding)
You don't need to introduce is_legacy_binding.
Since you only need to add the OPP table when this function gets called from ICE probe,
you should not touch this function. Instead, you should call devm_pm_opp_of_add_table()
in ICE probe before calling qcom_ice_create() then once qcom_ice_create() is success, you
can store the clk rate in the returned qcom_ice *engine ptr by calling clk_get_rate().
> {
> struct qcom_ice *engine;
> + int err;
>
> if (!qcom_scm_is_available())
> return ERR_PTR(-EPROBE_DEFER);
> @@ -584,6 +640,26 @@ static struct qcom_ice *qcom_ice_create(struct device *dev,
> if (IS_ERR(engine->core_clk))
> return ERR_CAST(engine->core_clk);
>
> + /*
> + * Register the OPP table only when ICE is described as a standalone
> + * device node. Older platforms place ICE inside the storage controller
> + * node, so they don't need an OPP table here, as they are handled in
> + * storage controller.
> + */
> + if (!is_legacy_binding) {
> + /* OPP table is optional */
> + err = devm_pm_opp_of_add_table(dev);
> + if (err && err != -ENODEV) {
> + dev_err(dev, "Invalid OPP table in Device tree\n");
> + return ERR_PTR(err);
> + }
> + engine->has_opp = (err == 0);
Let's keep it readable and simple. engine->has_opps = true; here and false in error handle above.
> +
> + if (!engine->has_opp)
> + dev_info(dev, "ICE OPP table is not registered, please update your DT\n");
Since OPP table is optional, I don't understand the reason for requesting the user to add one.
> + }
> +
> + engine->core_clk_freq = clk_get_rate(engine->core_clk);
> if (!qcom_ice_check_supported(engine))
> return ERR_PTR(-EOPNOTSUPP);
>
> @@ -628,7 +704,7 @@ static struct qcom_ice *of_qcom_ice_get(struct device *dev)
> return ERR_CAST(base);
>
> /* create ICE instance using consumer dev */
> - return qcom_ice_create(&pdev->dev, base);
> + return qcom_ice_create(&pdev->dev, base, true);
> }
>
> /*
> @@ -725,7 +801,7 @@ static int qcom_ice_probe(struct platform_device *pdev)
> return PTR_ERR(base);
> }
>
> - engine = qcom_ice_create(&pdev->dev, base);
> + engine = qcom_ice_create(&pdev->dev, base, false);
Change not needed as per above comment.
Regards,
Harshal
> if (IS_ERR(engine))
> return PTR_ERR(engine);
>
> diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h
> index 4bee553f0a59d86ec6ce20f7c7b4bce28a706415..4eb58a264d416e71228ed4b13e7f53c549261fdc 100644
> --- a/include/soc/qcom/ice.h
> +++ b/include/soc/qcom/ice.h
> @@ -30,5 +30,7 @@ int qcom_ice_import_key(struct qcom_ice *ice,
> const u8 *raw_key, size_t raw_key_size,
> u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]);
> struct qcom_ice *devm_of_qcom_ice_get(struct device *dev);
> +int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq,
> + bool round_ceil);
>
> #endif /* __QCOM_ICE_H__ */
>
^ permalink raw reply
* Re: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency
From: kernel test robot @ 2026-03-30 14:36 UTC (permalink / raw)
To: Mikko Perttunen, Thierry Reding, Uwe Kleine-König,
Jonathan Hunter, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: oe-kbuild-all, linux-pwm, linux-tegra, linux-kernel, devicetree,
Yi-Wei Wang, Mikko Perttunen
In-Reply-To: <20260325-t264-pwm-v2-2-998d885984b3@nvidia.com>
Hi Mikko,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 11439c4635edd669ae435eec308f4ab8a0804808]
url: https://github.com/intel-lab-lkp/linux/commits/Mikko-Perttunen/dt-bindings-pwm-Document-Tegra194-and-Tegra264-controllers/20260329-233356
base: 11439c4635edd669ae435eec308f4ab8a0804808
patch link: https://lore.kernel.org/r/20260325-t264-pwm-v2-2-998d885984b3%40nvidia.com
patch subject: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency
config: nios2-allmodconfig (https://download.01.org/0day-ci/archive/20260330/202603302259.NdAkuCVx-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 11.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260330/202603302259.NdAkuCVx-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603302259.NdAkuCVx-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from include/linux/kernel.h:17,
from include/linux/clk.h:13,
from drivers/pwm/pwm-tegra.c:39:
drivers/pwm/pwm-tegra.c: In function 'tegra_pwm_probe':
>> include/linux/limits.h:26:25: warning: unsigned conversion from 'long long int' to 'long unsigned int' changes value from '9223372036854775807' to '4294967295' [-Woverflow]
26 | #define S64_MAX ((s64)(U64_MAX >> 1))
| ^~~~~~~~~~~~~~~~~~~~~
drivers/pwm/pwm-tegra.c:303:47: note: in expansion of macro 'S64_MAX'
303 | ret = dev_pm_opp_set_rate(&pdev->dev, S64_MAX);
| ^~~~~~~
vim +26 include/linux/limits.h
3c9d017cc283df Andy Shevchenko 2023-08-04 14
54d50897d544c8 Masahiro Yamada 2019-03-07 15 #define U8_MAX ((u8)~0U)
54d50897d544c8 Masahiro Yamada 2019-03-07 16 #define S8_MAX ((s8)(U8_MAX >> 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 17 #define S8_MIN ((s8)(-S8_MAX - 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 18 #define U16_MAX ((u16)~0U)
54d50897d544c8 Masahiro Yamada 2019-03-07 19 #define S16_MAX ((s16)(U16_MAX >> 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 20 #define S16_MIN ((s16)(-S16_MAX - 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 21 #define U32_MAX ((u32)~0U)
3f50f132d8400e John Fastabend 2020-03-30 22 #define U32_MIN ((u32)0)
54d50897d544c8 Masahiro Yamada 2019-03-07 23 #define S32_MAX ((s32)(U32_MAX >> 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 24 #define S32_MIN ((s32)(-S32_MAX - 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 25 #define U64_MAX ((u64)~0ULL)
54d50897d544c8 Masahiro Yamada 2019-03-07 @26 #define S64_MAX ((s64)(U64_MAX >> 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 27 #define S64_MIN ((s64)(-S64_MAX - 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 28
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
From: Bjorn Andersson @ 2026-03-30 14:33 UTC (permalink / raw)
To: webgeek1234
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Georgi Djakov, Sibi Sankar, linux-arm-msm, devicetree,
linux-kernel, linux-pm, Neil Armstrong, Konrad Dybcio
In-Reply-To: <20260219-sm8550-ddr-bw-scaling-v3-2-75c19152e921@gmail.com>
On Thu, Feb 19, 2026 at 10:07:40PM -0600, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
>
> Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
> to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
> frequency by aggregating bandwidth requests of all CPU core with referenc
> to the current OPP they are configured in by the LMH/EPSS hardware.
>
> The effect is a proper caches & DDR frequency scaling when CPU cores
> changes frequency.
>
> The OPP tables were built using the downstream memlat ddr, llcc & l3
> tables for each cluster types with the actual EPSS cpufreq LUT tables
> from running a QCS8550 device.
>
> Also add the OSC L3 Cache controller node.
>
> Also add the interconnect entry for each cpu, with 3 different paths:
> - CPU to Last Level Cache Controller (LLCC)
> - Last Level Cache Controller (LLCC) to DDR
> - L3 Cache from CPU to DDR interface
>
"8 out of 11 hunks FAILED", it seems things moved since you wrote this.
Can you please help me by rebasing this onto linux-next and resubmitting
it?
Regards,
Bjorn
> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++++++
> 1 file changed, 367 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..de4d43f7b8d2416997db70c98b0fc36d25f3c2a6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -17,6 +17,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interconnect/qcom,icc.h>
> #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
> +#include <dt-bindings/interconnect/qcom,osm-l3.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/power/qcom,rpmhpd.h>
> @@ -78,6 +79,13 @@ cpu0: cpu@0 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <100>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_0: l2-cache {
> compatible = "cache";
> @@ -104,6 +112,13 @@ cpu1: cpu@100 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <100>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_100: l2-cache {
> compatible = "cache";
> @@ -125,6 +140,13 @@ cpu2: cpu@200 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <100>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_200: l2-cache {
> compatible = "cache";
> @@ -146,6 +168,13 @@ cpu3: cpu@300 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_300: l2-cache {
> compatible = "cache";
> @@ -167,6 +196,13 @@ cpu4: cpu@400 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_400: l2-cache {
> compatible = "cache";
> @@ -188,6 +224,13 @@ cpu5: cpu@500 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_500: l2-cache {
> compatible = "cache";
> @@ -209,6 +252,13 @@ cpu6: cpu@600 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_600: l2-cache {
> compatible = "cache";
> @@ -230,6 +280,13 @@ cpu7: cpu@700 {
> qcom,freq-domain = <&cpufreq_hw 2>;
> capacity-dmips-mhz = <1894>;
> dynamic-power-coefficient = <588>;
> + operating-points-v2 = <&cpu7_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_700: l2-cache {
> compatible = "cache";
> @@ -397,6 +454,306 @@ memory@a0000000 {
> reg = <0 0xa0000000 0 0>;
> };
>
> + cpu0_opp_table: opp-table-cpu0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-307200000 {
> + opp-hz = /bits/ 64 <307200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> + };
> +
> + opp-441600000 {
> + opp-hz = /bits/ 64 <441600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
> + };
> +
> + opp-556800000 {
> + opp-hz = /bits/ 64 <556800000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-672000000 {
> + opp-hz = /bits/ 64 <672000000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-787200000 {
> + opp-hz = /bits/ 64 <787200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
> + };
> +
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
> + };
> +
> + opp-1017600000 {
> + opp-hz = /bits/ 64 <1017600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1113600000 {
> + opp-hz = /bits/ 64 <1113600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1228800000 {
> + opp-hz = /bits/ 64 <1228800000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1152000 * 32)>;
> + };
> +
> + opp-1344000000 {
> + opp-hz = /bits/ 64 <1344000000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1459200000 {
> + opp-hz = /bits/ 64 <1459200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1555200000 {
> + opp-hz = /bits/ 64 <1555200000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-1670400000 {
> + opp-hz = /bits/ 64 <1670400000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-1785600000 {
> + opp-hz = /bits/ 64 <1785600000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-1900800000 {
> + opp-hz = /bits/ 64 <1900800000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1689600 * 32)>;
> + };
> +
> + opp-2016000000 {
> + opp-hz = /bits/ 64 <2016000000>;
> + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1804800 * 32)>;
> + };
> + };
> +
> + cpu3_opp_table: opp-table-cpu3 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-499200000 {
> + opp-hz = /bits/ 64 <499200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> + };
> +
> + opp-614400000 {
> + opp-hz = /bits/ 64 <614400000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-729600000 {
> + opp-hz = /bits/ 64 <729600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-844800000 {
> + opp-hz = /bits/ 64 <844800000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-940800000 {
> + opp-hz = /bits/ 64 <940800000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1171200000 {
> + opp-hz = /bits/ 64 <1171200000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1401600000 {
> + opp-hz = /bits/ 64 <1401600000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1536000000 {
> + opp-hz = /bits/ 64 <1536000000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1651200000 {
> + opp-hz = /bits/ 64 <1651200000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1785600000 {
> + opp-hz = /bits/ 64 <1785600000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1920000000 {
> + opp-hz = /bits/ 64 <1920000000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-2054400000 {
> + opp-hz = /bits/ 64 <2054400000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2188800000 {
> + opp-hz = /bits/ 64 <2188800000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2323200000 {
> + opp-hz = /bits/ 64 <2323200000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2457600000 {
> + opp-hz = /bits/ 64 <2457600000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2592000000 {
> + opp-hz = /bits/ 64 <2592000000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2707200000 {
> + opp-hz = /bits/ 64 <2707200000>;
> + opp-peak-kBps = <(933000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2803200000 {
> + opp-hz = /bits/ 64 <2803200000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> + };
> +
> + cpu7_opp_table: opp-table-cpu7 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-595200000 {
> + opp-hz = /bits/ 64 <595200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> + };
> +
> + opp-729600000 {
> + opp-hz = /bits/ 64 <729600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-864000000 {
> + opp-hz = /bits/ 64 <864000000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-998400000 {
> + opp-hz = /bits/ 64 <998400000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1478400000 {
> + opp-hz = /bits/ 64 <1478400000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1593600000 {
> + opp-hz = /bits/ 64 <1593600000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1708800000 {
> + opp-hz = /bits/ 64 <1708800000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1843200000 {
> + opp-hz = /bits/ 64 <1843200000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1977600000 {
> + opp-hz = /bits/ 64 <1977600000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-2092800000 {
> + opp-hz = /bits/ 64 <2092800000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2227200000 {
> + opp-hz = /bits/ 64 <2227200000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2342400000 {
> + opp-hz = /bits/ 64 <2342400000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2476800000 {
> + opp-hz = /bits/ 64 <2476800000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2592000000 {
> + opp-hz = /bits/ 64 <2592000000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2726400000 {
> + opp-hz = /bits/ 64 <2726400000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2841600000 {
> + opp-hz = /bits/ 64 <2841600000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> +
> + opp-2956800000 {
> + opp-hz = /bits/ 64 <2956800000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> +
> + opp-3187200000 {
> + opp-hz = /bits/ 64 <3187200000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> + };
> +
> pmu-a510 {
> compatible = "arm,cortex-a510-pmu";
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
> @@ -5437,6 +5794,16 @@ rpmhpd_opp_turbo_l1: opp-416 {
> };
> };
>
> + epss_l3: interconnect@17d90000 {
> + compatible = "qcom,sm8550-epss-l3", "qcom,epss-l3";
> + reg = <0 0x17d90000 0 0x1000>;
> +
> + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
> + clock-names = "xo", "alternate";
> +
> + #interconnect-cells = <1>;
> + };
> +
> cpufreq_hw: cpufreq@17d91000 {
> compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
> reg = <0 0x17d91000 0 0x1000>,
>
> --
> 2.52.0
>
>
^ permalink raw reply
* Re: [RFC PATCH 2/3] media: qcom: camss: Add CAMSS Offline Processing Engine driver
From: Bryan O'Donoghue @ 2026-03-30 14:32 UTC (permalink / raw)
To: johannes.goede, Dmitry Baryshkov
Cc: Loic Poulain, vladimir.zapolskiy, laurent.pinchart,
kieran.bingham, robh, krzk+dt, andersson, konradybcio,
linux-media, linux-arm-msm, devicetree, linux-kernel, mchehab
In-Reply-To: <2e4c4641-f631-48fa-b5dd-6efd70110dd6@oss.qualcomm.com>
On 30/03/2026 15:27, johannes.goede@oss.qualcomm.com wrote:
>> That's another reason I bring up CDM again and again. We probably don't want to fix to the wrong format for OPE, introduce the CDM and then find we have to map from one format to another for large and complex data over and over again for each frame or every N frames.
> CDM is a much lower-level API then what is expected from
> a media-controller centric V4L2 driver. Basically the OPE
> driver will export:
My concern is about wrappering one thing inside of another thing and
then stuffing it again back into CDM and doing the same on the way out.
There are already 50 MMIO writes in the OPE ISR, I don't believe it is
sustainable to keep adding MMIO into that.
I'm aware of a project in qcom that did something with making the CDM
format in libcamera and handed that off to kernel, recommend looking
into that.
---
bod
^ permalink raw reply
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