* Re: [PATCH v2 0/2] regulator: mt6315: add regulator supplies
From: Mark Brown @ 2026-03-30 14:45 UTC (permalink / raw)
To: Liam Girdwood, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno, Chen-Yu Tsai
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree
In-Reply-To: <20260326081050.1115201-1-wenst@chromium.org>
On Thu, 26 Mar 2026 16:10:47 +0800, Chen-Yu Tsai wrote:
> regulator: mt6315: add regulator supplies
>
> Hi,
>
> This is v2 of the "Add MT6315 regulator supplies" series.
>
> Changes since v1:
> - Link to v1: https://lore.kernel.org/all/20260324053030.4077453-1-wenst@chromium.org/
> - Move supplies to top level node, at the same level as the compatible
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git for-7.1
Thanks!
[1/2] regulator: dt-bindings: mt6315: Add regulator supplies
https://git.kernel.org/broonie/regulator/c/d15d0f1a27b2
[2/2] regulator: mt6315: Add regulator supplies
https://git.kernel.org/broonie/regulator/c/292d64fb98a2
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* Re: [PATCH v2 5/7] phy: ti: gmii-sel: add support for J722S SoC family
From: Vladimir Oltean @ 2026-03-30 22:37 UTC (permalink / raw)
To: Nora Schiffer
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Siddharth Vadapalli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, netdev, devicetree,
linux-kernel, linux-phy, linux-arm-kernel, linux
In-Reply-To: <5d00697f133cd33a1df62ac7ebf73e507e49ed2f.1774354734.git.nora.schiffer@ew.tq-group.com>
Hi Nora,
On Tue, Mar 24, 2026 at 01:29:41PM +0100, Nora Schiffer wrote:
> The J722S gmii-sel is mostly identical to the AM64's, but additionally
> supports SGMII.
>
> Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
> ---
> drivers/phy/ti/phy-gmii-sel.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
> index 6213c2b6005a5..4e242b1892334 100644
> --- a/drivers/phy/ti/phy-gmii-sel.c
> +++ b/drivers/phy/ti/phy-gmii-sel.c
> @@ -251,6 +251,13 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
> .regfields = phy_gmii_sel_fields_am654,
> };
>
> +static const
> +struct phy_gmii_sel_soc_data phy_gmii_sel_soc_j722s = {
> + .use_of_data = true,
> + .regfields = phy_gmii_sel_fields_am654,
> + .extra_modes = BIT(PHY_INTERFACE_MODE_SGMII),
I'm not familiar with the hardware, but "mostly identical to AM64, but
additionally supports SGMII" does not explain why j722s does not inherit
the features that am654 has (PHY_GMII_SEL_RGMII_ID_MODE and
BIT(PHY_GMII_SEL_FIXED_TX_DELAY).
The phy-gmii-sel from j722s does support RGMII, right? Because in lack
of the PHY_GMII_SEL_RGMII_ID_MODE feature, phy_gmii_sel_mode() will just
silently skip the regmap_field_write(regfield, rgmii_id) call, and
return successfully despite an incomplete configuration.
We have the phy_validate() call and phy_ops::validate() through which
the PHY can report to the Ethernet controller which phy_interface_t it
supports and which it doesn't. If the j722s doesn't support RGMII, maybe
it should implement this method.
> +};
> +
^ permalink raw reply
* [PATCH] arm64: dts: imx8mp-phyboard-pollux: Add HDMI support
From: Paul Kocialkowski @ 2026-03-30 22:37 UTC (permalink / raw)
To: devicetree, imx, linux-arm-kernel, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Paul Kocialkowski
The PHYTEC phyBOARD Pollux comes with a HDMI port on the base board.
Add the required device-tree nodes to enable support for it.
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
.../freescale/imx8mp-phyboard-pollux-rdk.dts | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 0fe52c73fc8f..0d52f29813f1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -38,6 +38,18 @@ fan0: fan {
#cooling-cells = <2>;
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
panel_lvds1: panel-lvds1 {
/* compatible panel in overlay */
backlight = <&backlight_lvds1>;
@@ -201,6 +213,28 @@ &flexcan2 {
status = "okay";
};
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
@@ -244,6 +278,10 @@ &i2c3 {
scl-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
+&lcdif3 {
+ status = "okay";
+};
+
&ldb_lvds_ch1 {
remote-endpoint = <&panel1_in>;
};
@@ -444,6 +482,15 @@ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
>;
};
+ pinctrl_hdmi: hdmigrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3
+ MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3
+ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19
+ MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
--
2.53.0
^ permalink raw reply related
* [PATCH v2] riscv: dts: spacemit: k3: Add USB2.0 support
From: Yixun Lan @ 2026-03-30 22:15 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Yixun Lan
There is one USB2.0 host in K3 SoC which use DWC3 IP but only provide
USB2.0 functionality, and with only one USB2 PHY connected.
The USB2.0 controller on Pico-ITX board connects to a Terminus FE1.1 Hub
which fully USB2.0 protocol compliant and provides 4 ports.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
This series adds devicetree support to enable USB2.0 in Pico-ITX board,
There is a run-time dependency on USB phy[1], Hub[2] and reset[3] patches,
but each series should be quite independent.
For people who interested, I've collected all patches and put a complete
branch here[4].
Currently, the USB phy[1] patch is still waiting for maintainer to
merge.
Link: https://lore.kernel.org/r/20260305-11-k3-usb2-phy-v4-0-15554fb933bc@kernel.org [1]
Link: https://lore.kernel.org/r/20260317-03-usb-hub-fe1-v1-0-71ec3989f5be@kernel.org [2]
Link: https://lore.kernel.org/r/20260314-01-k3-reset-usb-pci-v2-1-9dc0976d524e@kernel.org [3]
Link: https://github.com/spacemit-com/linux/tree/WIP/k3/usb2 [4]
---
Changes in v2:
- separate DT patch out, no code changes
- Link to v1: https://lore.kernel.org/r/20260317-02-k3-usb20-support-v1-0-d89f59062ad4@kernel.org
---
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 24 +++++++++++++++++++++
arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++++++++++
2 files changed, 55 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
index 4486dc1fe114..b89c1521e664 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -26,6 +26,14 @@ memory@100000000 {
reg = <0x1 0x00000000 0x4 0x00000000>;
};
+ reg_aux_vcc3v3: regulator-aux-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "AUX_VCC3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
reg_aux_vcc5v: regulator-aux-vcc5v {
compatible = "regulator-fixed";
regulator-name = "AUX_VCC5V";
@@ -197,3 +205,19 @@ &uart0 {
pinctrl-0 = <&uart0_0_cfg>;
status = "okay";
};
+
+&usb2_host {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub@1 {
+ compatible = "usb1a40,0101";
+ reg = <1>;
+ vdd-supply = <®_aux_vcc3v3>;
+ };
+};
+
+&usb2_phy {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 815debd16409..9eb2ff07218a 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -438,6 +438,37 @@ soc: soc {
dma-noncoherent;
ranges;
+ usb2_host: usb@c0a00000 {
+ compatible = "spacemit,k3-dwc3";
+ reg = <0x0 0xc0a00000 0x0 0x10000>;
+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>;
+ clock-names = "usbdrd30";
+ resets = <&syscon_apmu RESET_APMU_USB2_AHB>,
+ <&syscon_apmu RESET_APMU_USB2_VCC>,
+ <&syscon_apmu RESET_APMU_USB2_PHY>;
+ reset-names = "ahb", "vcc", "phy";
+ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&saplic>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
+ phy_type = "utmi";
+ snps,dis_enblslpm_quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ status = "disabled";
+ };
+
+ usb2_phy: phy@c0a20000 {
+ compatible = "spacemit,k3-usb2-phy";
+ reg = <0x0 0xc0a20000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
eth0: ethernet@cac80000 {
compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a";
reg = <0x0 0xcac80000 0x0 0x2000>;
---
base-commit: af62a095eb0c3359d477b55ef72d2afd94c83c8f
change-id: 20260330-02-k3-usb20-dts-670aeb20e2d3
Best regards,
--
Yixun Lan <dlan@kernel.org>
^ permalink raw reply related
* Re: [PATCH 1/2] dt-bindings: pwm: amlogic: Add new bindings for S6 S7 S7D
From: Martin Blumenstingl @ 2026-03-30 21:58 UTC (permalink / raw)
To: xianwei.zhao
Cc: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, linux-pwm, devicetree, linux-kernel,
linux-arm-kernel, linux-amlogic, Junyi Zhao
In-Reply-To: <20260326-s6-s7-pwm-v1-1-67e2f72b98bc@amlogic.com>
On Thu, Mar 26, 2026 at 7:35 AM Xianwei Zhao via B4 Relay
<devnull+xianwei.zhao.amlogic.com@kernel.org> wrote:
>
> From: Junyi Zhao <junyi.zhao@amlogic.com>
>
> Amlogic S7/S7D/S6 different from the previous SoCs, a controller
> includes one pwm, at the same time, the controller has only one
> input clock source.
>
> Signed-off-by: Junyi Zhao <junyi.zhao@amlogic.com>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
With the two suggestions from Krzysztof added:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^ permalink raw reply
* Re: [PATCH 0/2] Add PWM support Amlogic S7 S7D S6
From: Martin Blumenstingl @ 2026-03-30 21:54 UTC (permalink / raw)
To: xianwei.zhao
Cc: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, linux-pwm, devicetree, linux-kernel,
linux-arm-kernel, linux-amlogic, Junyi Zhao
In-Reply-To: <20260326-s6-s7-pwm-v1-0-67e2f72b98bc@amlogic.com>
Hi Xianwei Zhao,
thanks for your contribution!
On Thu, Mar 26, 2026 at 7:35 AM Xianwei Zhao via B4 Relay
<devnull+xianwei.zhao.amlogic.com@kernel.org> wrote:
>
> Add bindings and driver support Amlogic S7/S7D/S6 SoCs.
There is an old report that got lost, stating that the current
pwm-meson driver has an off-by-one error with the hi and lo fields:
[0]
Since you are working on bringing up a new platform: is this something
you can verify in your lab?
To be clear: I'm not expecting you to work on this ad-hoc or bring a
patch into this series. However, it would be great if you could verify
if the findings from [0] are correct and send an updated patch in
future.
Thank you and best regards
Martin
[0] https://lore.kernel.org/all/20241225105639.1787237-3-gnstark@salutedevices.com/
^ permalink raw reply
* Re: [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
From: Aaron Kling @ 2026-03-30 21:52 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Georgi Djakov, Sibi Sankar, linux-arm-msm, devicetree,
linux-kernel, linux-pm, Neil Armstrong, Konrad Dybcio
In-Reply-To: <acqJWzQHi7ajuzml@baldur>
On Mon, Mar 30, 2026 at 9:33 AM Bjorn Andersson <andersson@kernel.org> wrote:
>
> On Thu, Feb 19, 2026 at 10:07:40PM -0600, Aaron Kling via B4 Relay wrote:
> > From: Aaron Kling <webgeek1234@gmail.com>
> >
> > Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
> > to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
> > frequency by aggregating bandwidth requests of all CPU core with referenc
> > to the current OPP they are configured in by the LMH/EPSS hardware.
> >
> > The effect is a proper caches & DDR frequency scaling when CPU cores
> > changes frequency.
> >
> > The OPP tables were built using the downstream memlat ddr, llcc & l3
> > tables for each cluster types with the actual EPSS cpufreq LUT tables
> > from running a QCS8550 device.
> >
> > Also add the OSC L3 Cache controller node.
> >
> > Also add the interconnect entry for each cpu, with 3 different paths:
> > - CPU to Last Level Cache Controller (LLCC)
> > - Last Level Cache Controller (LLCC) to DDR
> > - L3 Cache from CPU to DDR interface
> >
>
> "8 out of 11 hunks FAILED", it seems things moved since you wrote this.
> Can you please help me by rebasing this onto linux-next and resubmitting
> it?
This was a conflict from the EAS patch. I have sent a new revision
rebased on today's -next.
Aaron
> Regards,
> Bjorn
>
> > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> > ---
> > arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 367 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..de4d43f7b8d2416997db70c98b0fc36d25f3c2a6 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > @@ -17,6 +17,7 @@
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/interconnect/qcom,icc.h>
> > #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
> > +#include <dt-bindings/interconnect/qcom,osm-l3.h>
> > #include <dt-bindings/mailbox/qcom-ipcc.h>
> > #include <dt-bindings/power/qcom-rpmpd.h>
> > #include <dt-bindings/power/qcom,rpmhpd.h>
> > @@ -78,6 +79,13 @@ cpu0: cpu@0 {
> > qcom,freq-domain = <&cpufreq_hw 0>;
> > capacity-dmips-mhz = <1024>;
> > dynamic-power-coefficient = <100>;
> > + operating-points-v2 = <&cpu0_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_0: l2-cache {
> > compatible = "cache";
> > @@ -104,6 +112,13 @@ cpu1: cpu@100 {
> > qcom,freq-domain = <&cpufreq_hw 0>;
> > capacity-dmips-mhz = <1024>;
> > dynamic-power-coefficient = <100>;
> > + operating-points-v2 = <&cpu0_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_100: l2-cache {
> > compatible = "cache";
> > @@ -125,6 +140,13 @@ cpu2: cpu@200 {
> > qcom,freq-domain = <&cpufreq_hw 0>;
> > capacity-dmips-mhz = <1024>;
> > dynamic-power-coefficient = <100>;
> > + operating-points-v2 = <&cpu0_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_200: l2-cache {
> > compatible = "cache";
> > @@ -146,6 +168,13 @@ cpu3: cpu@300 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_300: l2-cache {
> > compatible = "cache";
> > @@ -167,6 +196,13 @@ cpu4: cpu@400 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_400: l2-cache {
> > compatible = "cache";
> > @@ -188,6 +224,13 @@ cpu5: cpu@500 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_500: l2-cache {
> > compatible = "cache";
> > @@ -209,6 +252,13 @@ cpu6: cpu@600 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_600: l2-cache {
> > compatible = "cache";
> > @@ -230,6 +280,13 @@ cpu7: cpu@700 {
> > qcom,freq-domain = <&cpufreq_hw 2>;
> > capacity-dmips-mhz = <1894>;
> > dynamic-power-coefficient = <588>;
> > + operating-points-v2 = <&cpu7_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_700: l2-cache {
> > compatible = "cache";
> > @@ -397,6 +454,306 @@ memory@a0000000 {
> > reg = <0 0xa0000000 0 0>;
> > };
> >
> > + cpu0_opp_table: opp-table-cpu0 {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-307200000 {
> > + opp-hz = /bits/ 64 <307200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> > + };
> > +
> > + opp-441600000 {
> > + opp-hz = /bits/ 64 <441600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
> > + };
> > +
> > + opp-556800000 {
> > + opp-hz = /bits/ 64 <556800000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-672000000 {
> > + opp-hz = /bits/ 64 <672000000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-787200000 {
> > + opp-hz = /bits/ 64 <787200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-902400000 {
> > + opp-hz = /bits/ 64 <902400000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
> > + };
> > +
> > + opp-1017600000 {
> > + opp-hz = /bits/ 64 <1017600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1113600000 {
> > + opp-hz = /bits/ 64 <1113600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1228800000 {
> > + opp-hz = /bits/ 64 <1228800000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1152000 * 32)>;
> > + };
> > +
> > + opp-1344000000 {
> > + opp-hz = /bits/ 64 <1344000000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1459200000 {
> > + opp-hz = /bits/ 64 <1459200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1555200000 {
> > + opp-hz = /bits/ 64 <1555200000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-1670400000 {
> > + opp-hz = /bits/ 64 <1670400000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-1785600000 {
> > + opp-hz = /bits/ 64 <1785600000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-1900800000 {
> > + opp-hz = /bits/ 64 <1900800000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1689600 * 32)>;
> > + };
> > +
> > + opp-2016000000 {
> > + opp-hz = /bits/ 64 <2016000000>;
> > + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1804800 * 32)>;
> > + };
> > + };
> > +
> > + cpu3_opp_table: opp-table-cpu3 {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-499200000 {
> > + opp-hz = /bits/ 64 <499200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> > + };
> > +
> > + opp-614400000 {
> > + opp-hz = /bits/ 64 <614400000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-729600000 {
> > + opp-hz = /bits/ 64 <729600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-844800000 {
> > + opp-hz = /bits/ 64 <844800000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-940800000 {
> > + opp-hz = /bits/ 64 <940800000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1056000000 {
> > + opp-hz = /bits/ 64 <1056000000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1171200000 {
> > + opp-hz = /bits/ 64 <1171200000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1286400000 {
> > + opp-hz = /bits/ 64 <1286400000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1401600000 {
> > + opp-hz = /bits/ 64 <1401600000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1536000000 {
> > + opp-hz = /bits/ 64 <1536000000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1651200000 {
> > + opp-hz = /bits/ 64 <1651200000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1785600000 {
> > + opp-hz = /bits/ 64 <1785600000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1920000000 {
> > + opp-hz = /bits/ 64 <1920000000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-2054400000 {
> > + opp-hz = /bits/ 64 <2054400000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2188800000 {
> > + opp-hz = /bits/ 64 <2188800000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2323200000 {
> > + opp-hz = /bits/ 64 <2323200000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2457600000 {
> > + opp-hz = /bits/ 64 <2457600000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2592000000 {
> > + opp-hz = /bits/ 64 <2592000000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2707200000 {
> > + opp-hz = /bits/ 64 <2707200000>;
> > + opp-peak-kBps = <(933000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2803200000 {
> > + opp-hz = /bits/ 64 <2803200000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > + };
> > +
> > + cpu7_opp_table: opp-table-cpu7 {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-595200000 {
> > + opp-hz = /bits/ 64 <595200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> > + };
> > +
> > + opp-729600000 {
> > + opp-hz = /bits/ 64 <729600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-864000000 {
> > + opp-hz = /bits/ 64 <864000000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-998400000 {
> > + opp-hz = /bits/ 64 <998400000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1132800000 {
> > + opp-hz = /bits/ 64 <1132800000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1248000000 {
> > + opp-hz = /bits/ 64 <1248000000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1363200000 {
> > + opp-hz = /bits/ 64 <1363200000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1478400000 {
> > + opp-hz = /bits/ 64 <1478400000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1593600000 {
> > + opp-hz = /bits/ 64 <1593600000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1708800000 {
> > + opp-hz = /bits/ 64 <1708800000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1843200000 {
> > + opp-hz = /bits/ 64 <1843200000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1977600000 {
> > + opp-hz = /bits/ 64 <1977600000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-2092800000 {
> > + opp-hz = /bits/ 64 <2092800000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2227200000 {
> > + opp-hz = /bits/ 64 <2227200000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2342400000 {
> > + opp-hz = /bits/ 64 <2342400000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2476800000 {
> > + opp-hz = /bits/ 64 <2476800000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2592000000 {
> > + opp-hz = /bits/ 64 <2592000000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2726400000 {
> > + opp-hz = /bits/ 64 <2726400000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2841600000 {
> > + opp-hz = /bits/ 64 <2841600000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > +
> > + opp-2956800000 {
> > + opp-hz = /bits/ 64 <2956800000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > +
> > + opp-3187200000 {
> > + opp-hz = /bits/ 64 <3187200000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > + };
> > +
> > pmu-a510 {
> > compatible = "arm,cortex-a510-pmu";
> > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
> > @@ -5437,6 +5794,16 @@ rpmhpd_opp_turbo_l1: opp-416 {
> > };
> > };
> >
> > + epss_l3: interconnect@17d90000 {
> > + compatible = "qcom,sm8550-epss-l3", "qcom,epss-l3";
> > + reg = <0 0x17d90000 0 0x1000>;
> > +
> > + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
> > + clock-names = "xo", "alternate";
> > +
> > + #interconnect-cells = <1>;
> > + };
> > +
> > cpufreq_hw: cpufreq@17d91000 {
> > compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
> > reg = <0 0x17d91000 0 0x1000>,
> >
> > --
> > 2.52.0
> >
> >
^ permalink raw reply
* Re: [PATCH v2 6/6] phy: realtek: usb2: Make configs available for MACH_REALTEK_RTL
From: Vladimir Oltean @ 2026-03-30 21:52 UTC (permalink / raw)
To: Rustam Adilov
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260327160638.15134-7-adilov@disroot.org>
On Fri, Mar 27, 2026 at 09:06:38PM +0500, Rustam Adilov wrote:
> Add the MACH_REALTEK_RTL to the if statement to make the config
> options available for Realtek RTL SoCs as well.
>
> Signed-off-by: Rustam Adilov <adilov@disroot.org>
> ---
> drivers/phy/realtek/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/phy/realtek/Kconfig b/drivers/phy/realtek/Kconfig
> index 75ac7e7c31ae..f9eadffacd18 100644
> --- a/drivers/phy/realtek/Kconfig
> +++ b/drivers/phy/realtek/Kconfig
> @@ -3,7 +3,7 @@
> # Phy drivers for Realtek platforms
> #
>
> -if ARCH_REALTEK || COMPILE_TEST
> +if ARCH_REALTEK || MACH_REALTEK_RTL || COMPILE_TEST
>
> config PHY_RTK_RTD_USB2PHY
> tristate "Realtek RTD USB2 PHY Transceiver Driver"
> --
> 2.53.0
>
>
The file now reads:
if ARCH_REALTEK || MACH_REALTEK_RTL || COMPILE_TEST
...
endif # ARCH_REALTEK || COMPILE_TEST
Please update the end comment as well.
^ permalink raw reply
* Re: [PATCH v2 5/6] phy: realtek: usb2: add support for RTL9607C USB2 PHY
From: Vladimir Oltean @ 2026-03-30 21:50 UTC (permalink / raw)
To: Rustam Adilov
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel,
Michael Zavertkin
In-Reply-To: <20260327160638.15134-6-adilov@disroot.org>
On Fri, Mar 27, 2026 at 09:06:37PM +0500, Rustam Adilov wrote:
> Add support for the usb2 phy of RTL9607C series based SoCs.
> Add the macros and phy config struct for rtl9607.
>
> RTL9607C requires to clear a "force host disconnect" bit in the
> specific register (which is at an offset from reg_wrap_vstatus)
> before proceeding with phy parameter writes.
>
> Add the bool variable to the driver data struct and hide this whole
> procedure under the if statement that checks this new variable.
>
> Co-developed-by: Michael Zavertkin <misha.zavertkin@mail.ru>
> Signed-off-by: Michael Zavertkin <misha.zavertkin@mail.ru>
> Signed-off-by: Rustam Adilov <adilov@disroot.org>
> ---
> drivers/phy/realtek/phy-rtk-usb2.c | 57 ++++++++++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-rtk-usb2.c
> index 070cba1e0e0a..bf22d12681dc 100644
> --- a/drivers/phy/realtek/phy-rtk-usb2.c
> +++ b/drivers/phy/realtek/phy-rtk-usb2.c
> @@ -26,6 +26,12 @@
> #define PHY_VCTRL_SHIFT 8
> #define PHY_REG_DATA_MASK 0xff
>
> +#define PHY_9607_VSTS_BUSY BIT(17)
> +#define PHY_9607_NEW_REG_REQ BIT(13)
> +
> +#define PHY_9607_FORCE_DISCONNECT_REG 0x10
> +#define PHY_9607_FORCE_DISCONNECT_BIT BIT(5)
> +
> #define GET_LOW_NIBBLE(addr) ((addr) & 0x0f)
> #define GET_HIGH_NIBBLE(addr) (((addr) & 0xf0) >> 4)
>
> @@ -109,6 +115,7 @@ struct phy_cfg {
>
> u32 (*read)(void __iomem *reg);
> void (*write)(u32 val, void __iomem *reg);
> + bool force_host_disconnect;
> };
>
> struct phy_parameter {
> @@ -614,6 +621,16 @@ static int do_rtk_phy_init(struct rtk_phy *rtk_phy, int index)
> goto do_toggle;
> }
>
> + if (phy_cfg->force_host_disconnect) {
> + /* disable force-host-disconnect */
> + u32 temp = readl(phy_reg->reg_wrap_vstatus + PHY_9607_FORCE_DISCONNECT_REG);
> +
> + temp &= ~PHY_9607_FORCE_DISCONNECT_BIT;
> + writel(temp, phy_reg->reg_wrap_vstatus + PHY_9607_FORCE_DISCONNECT_REG);
> +
> + mdelay(10);
LLM review:
Could we use msleep(10) or usleep_range(10000, 11000) here instead of
mdelay(10)?
Since do_rtk_phy_init() executes as part of the phy_ops->init callback
with a mutex held from a sleepable process context, spinning the CPU for
10ms wastes CPU resources and increases scheduling latency.
> + }
> +
> /* Set page 0 */
> phy_data_page = phy_cfg->page0;
> rtk_phy_set_page(phy_reg, 0);
> @@ -1141,6 +1158,7 @@ static const struct phy_cfg rtd1295_phy_cfg = {
> .new_reg_req = PHY_NEW_REG_REQ,
> .read = phy_read,
> .write = phy_write,
> + .force_host_disconnect = false,
You don't need to initialize rodata struct fields with false/0/NULL.
> };
>
> static const struct phy_cfg rtd1395_phy_cfg = {
> @@ -1170,6 +1188,7 @@ static const struct phy_cfg rtd1395_phy_cfg = {
> .new_reg_req = PHY_NEW_REG_REQ,
> .read = phy_read,
> .write = phy_write,
> + .force_host_disconnect = false,
> };
>
> static const struct phy_cfg rtd1395_phy_cfg_2port = {
> @@ -1199,6 +1218,7 @@ static const struct phy_cfg rtd1395_phy_cfg_2port = {
> .new_reg_req = PHY_NEW_REG_REQ,
> .read = phy_read,
> .write = phy_write,
> + .force_host_disconnect = false,
> };
>
> static const struct phy_cfg rtd1619_phy_cfg = {
> @@ -1226,6 +1246,7 @@ static const struct phy_cfg rtd1619_phy_cfg = {
> .new_reg_req = PHY_NEW_REG_REQ,
> .read = phy_read,
> .write = phy_write,
> + .force_host_disconnect = false,
> };
>
> static const struct phy_cfg rtd1319_phy_cfg = {
> @@ -1257,6 +1278,7 @@ static const struct phy_cfg rtd1319_phy_cfg = {
> .new_reg_req = PHY_NEW_REG_REQ,
> .read = phy_read,
> .write = phy_write,
> + .force_host_disconnect = false,
> };
>
> static const struct phy_cfg rtd1312c_phy_cfg = {
> @@ -1287,6 +1309,7 @@ static const struct phy_cfg rtd1312c_phy_cfg = {
> .new_reg_req = PHY_NEW_REG_REQ,
> .read = phy_read,
> .write = phy_write,
> + .force_host_disconnect = false,
> };
>
> static const struct phy_cfg rtd1619b_phy_cfg = {
> @@ -1317,6 +1340,7 @@ static const struct phy_cfg rtd1619b_phy_cfg = {
> .new_reg_req = PHY_NEW_REG_REQ,
> .read = phy_read,
> .write = phy_write,
> + .force_host_disconnect = false,
> };
>
> static const struct phy_cfg rtd1319d_phy_cfg = {
> @@ -1347,6 +1371,7 @@ static const struct phy_cfg rtd1319d_phy_cfg = {
> .new_reg_req = PHY_NEW_REG_REQ,
> .read = phy_read,
> .write = phy_write,
> + .force_host_disconnect = false,
> };
>
> static const struct phy_cfg rtd1315e_phy_cfg = {
> @@ -1378,6 +1403,37 @@ static const struct phy_cfg rtd1315e_phy_cfg = {
> .new_reg_req = PHY_NEW_REG_REQ,
> .read = phy_read,
> .write = phy_write,
> + .force_host_disconnect = false,
> +};
> +
> +static const struct phy_cfg rtl9607_phy_cfg = {
> + .page0_size = MAX_USB_PHY_PAGE0_DATA_SIZE,
> + .page0 = { [0] = {0xe0, 0x95},
> + [4] = {0xe4, 0x6a},
> + [12] = {0xf3, 0x31}, },
> + .page1_size = MAX_USB_PHY_PAGE1_DATA_SIZE,
> + .page1 = { [0] = {0xe0, 0x26}, },
> + .page2_size = MAX_USB_PHY_PAGE2_DATA_SIZE,
> + .page2 = { [7] = {0xe7, 0x33}, },
> + .num_phy = 1,
> + .check_efuse = false,
Similar for these (+do_toggle_driving, use_default_parameter).
> + .check_efuse_version = CHECK_EFUSE_V2,
> + .efuse_dc_driving_rate = EFUS_USB_DC_CAL_RATE,
> + .dc_driving_mask = 0x1f,
> + .efuse_dc_disconnect_rate = EFUS_USB_DC_DIS_RATE,
> + .dc_disconnect_mask = 0xf,
> + .usb_dc_disconnect_at_page0 = true,
> + .do_toggle = true,
> + .do_toggle_driving = false,
> + .driving_updated_for_dev_dis = 0x8,
> + .use_default_parameter = false,
> + .is_double_sensitivity_mode = true,
> + .vstatus_offset = 0xc,
> + .vstatus_busy = PHY_9607_VSTS_BUSY,
> + .new_reg_req = PHY_9607_NEW_REG_REQ,
> + .read = phy_read_le,
> + .write = phy_write_le,
> + .force_host_disconnect = true,
> };
>
> static const struct of_device_id usbphy_rtk_dt_match[] = {
> @@ -1390,6 +1446,7 @@ static const struct of_device_id usbphy_rtk_dt_match[] = {
> { .compatible = "realtek,rtd1395-usb2phy-2port", .data = &rtd1395_phy_cfg_2port },
> { .compatible = "realtek,rtd1619-usb2phy", .data = &rtd1619_phy_cfg },
> { .compatible = "realtek,rtd1619b-usb2phy", .data = &rtd1619b_phy_cfg },
> + { .compatible = "realtek,rtl9607-usb2phy", .data = &rtl9607_phy_cfg },
> {},
> };
> MODULE_DEVICE_TABLE(of, usbphy_rtk_dt_match);
> --
> 2.53.0
>
>
^ permalink raw reply
* [PATCH v4] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
From: Aaron Kling via B4 Relay @ 2026-03-30 21:50 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Sibi Sankar
Cc: linux-arm-msm, devicetree, linux-kernel, linux-pm, Neil Armstrong,
Konrad Dybcio, Dmitry Baryshkov, Aaron Kling
From: Aaron Kling <webgeek1234@gmail.com>
Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
frequency by aggregating bandwidth requests of all CPU core with referenc
to the current OPP they are configured in by the LMH/EPSS hardware.
The effect is a proper caches & DDR frequency scaling when CPU cores
changes frequency.
The OPP tables were built using the downstream memlat ddr, llcc & l3
tables for each cluster types with the actual EPSS cpufreq LUT tables
from running a QCS8550 device.
Also add the OSC L3 Cache controller node.
Also add the interconnect entry for each cpu, with 3 different paths:
- CPU to Last Level Cache Controller (LLCC)
- Last Level Cache Controller (LLCC) to DDR
- L3 Cache from CPU to DDR interface
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
Add the OSM L3 controller node then add the necessary interconnect
properties with the appropriate OPP table for each CPU cluster to
allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU
cluster operating point.
---
Changes in v4:
- Rebase on -next and resolve merge conflicts
- Drop patch 1 as it was already picked up
- Link to v3: https://lore.kernel.org/r/20260219-sm8550-ddr-bw-scaling-v3-0-75c19152e921@gmail.com
Changes in v3:
- Squash the last two patches
- Link to v2: https://lore.kernel.org/r/20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com
Changes in v2:
- Squash first two patches
- Update opp tables in last patch to match how the downstream driver
parses those tables
- Link to v1: https://lore.kernel.org/r/20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++++++
1 file changed, 367 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..b7a7c49db077bd36f5705efeae427287eb23ffe4 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -17,6 +17,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
@@ -78,6 +79,13 @@ cpu0: cpu@0 {
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <326>;
dynamic-power-coefficient = <251>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
@@ -104,6 +112,13 @@ cpu1: cpu@100 {
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <326>;
dynamic-power-coefficient = <251>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_100: l2-cache {
compatible = "cache";
@@ -125,6 +140,13 @@ cpu2: cpu@200 {
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <326>;
dynamic-power-coefficient = <251>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_200: l2-cache {
compatible = "cache";
@@ -146,6 +168,13 @@ cpu3: cpu@300 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <693>;
dynamic-power-coefficient = <447>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_300: l2-cache {
compatible = "cache";
@@ -167,6 +196,13 @@ cpu4: cpu@400 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <693>;
dynamic-power-coefficient = <447>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_400: l2-cache {
compatible = "cache";
@@ -188,6 +224,13 @@ cpu5: cpu@500 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <693>;
dynamic-power-coefficient = <447>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_500: l2-cache {
compatible = "cache";
@@ -209,6 +252,13 @@ cpu6: cpu@600 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <693>;
dynamic-power-coefficient = <447>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_600: l2-cache {
compatible = "cache";
@@ -230,6 +280,13 @@ cpu7: cpu@700 {
qcom,freq-domain = <&cpufreq_hw 2>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <1057>;
+ operating-points-v2 = <&cpu7_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_700: l2-cache {
compatible = "cache";
@@ -397,6 +454,306 @@ memory@a0000000 {
reg = <0 0xa0000000 0 0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
+ };
+
+ opp-441600000 {
+ opp-hz = /bits/ 64 <441600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
+ };
+
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-672000000 {
+ opp-hz = /bits/ 64 <672000000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-787200000 {
+ opp-hz = /bits/ 64 <787200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
+ };
+
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (940800 * 32)>;
+ };
+
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1152000 * 32)>;
+ };
+
+ opp-1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
+ };
+
+ opp-1670400000 {
+ opp-hz = /bits/ 64 <1670400000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
+ };
+
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1689600 * 32)>;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1804800 * 32)>;
+ };
+ };
+
+ cpu3_opp_table: opp-table-cpu3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-499200000 {
+ opp-hz = /bits/ 64 <499200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
+ };
+
+ opp-614400000 {
+ opp-hz = /bits/ 64 <614400000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1171200000 {
+ opp-hz = /bits/ 64 <1171200000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
+ };
+
+ opp-2054400000 {
+ opp-hz = /bits/ 64 <2054400000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2323200000 {
+ opp-hz = /bits/ 64 <2323200000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2457600000 {
+ opp-hz = /bits/ 64 <2457600000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2592000000 {
+ opp-hz = /bits/ 64 <2592000000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2707200000 {
+ opp-hz = /bits/ 64 <2707200000>;
+ opp-peak-kBps = <(933000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2803200000 {
+ opp-hz = /bits/ 64 <2803200000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+ };
+
+ cpu7_opp_table: opp-table-cpu7 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-595200000 {
+ opp-hz = /bits/ 64 <595200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
+ };
+
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-998400000 {
+ opp-hz = /bits/ 64 <998400000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1977600000 {
+ opp-hz = /bits/ 64 <1977600000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
+ };
+
+ opp-2092800000 {
+ opp-hz = /bits/ 64 <2092800000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2227200000 {
+ opp-hz = /bits/ 64 <2227200000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2342400000 {
+ opp-hz = /bits/ 64 <2342400000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2476800000 {
+ opp-hz = /bits/ 64 <2476800000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2592000000 {
+ opp-hz = /bits/ 64 <2592000000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2726400000 {
+ opp-hz = /bits/ 64 <2726400000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2841600000 {
+ opp-hz = /bits/ 64 <2841600000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+
+ opp-2956800000 {
+ opp-hz = /bits/ 64 <2956800000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+
+ opp-3187200000 {
+ opp-hz = /bits/ 64 <3187200000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+ };
+
pmu-a510 {
compatible = "arm,cortex-a510-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
@@ -5482,6 +5839,16 @@ rpmhpd_opp_turbo_l1: opp-416 {
};
};
+ epss_l3: interconnect@17d90000 {
+ compatible = "qcom,sm8550-epss-l3", "qcom,epss-l3";
+ reg = <0 0x17d90000 0 0x1000>;
+
+ clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@17d91000 {
compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x17d91000 0 0x1000>,
---
base-commit: cf7c3c02fdd0dfccf4d6611714273dcb538af2cb
change-id: 20260207-sm8550-ddr-bw-scaling-b1524827f207
Best regards,
--
Aaron Kling <webgeek1234@gmail.com>
^ permalink raw reply related
* Re: [PATCH v2] arm64: dts: amlogic: t7: khadas-vim4: Remove invalid property
From: Martin Blumenstingl @ 2026-03-30 21:47 UTC (permalink / raw)
To: Ronald Claveau
Cc: Neil Armstrong, Kevin Hilman, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel,
linux-amlogic, devicetree, linux-kernel, kernel test robot,
Krzysztof Kozlowski
In-Reply-To: <20260330-fix-invalid-property-v2-1-228c51c8de93@aliel.fr>
On Mon, Mar 30, 2026 at 2:15 PM Ronald Claveau
<linux-kernel-dev@aliel.fr> wrote:
>
> Fix introduced invalid property for Khadas VIM4 sdcard regulator.
>
> arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dtb: regulator-sdcard-3v3 (regulator-fixed): Unevaluated properties are not allowed ('enable-active-low' was unexpected)
>
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202603290828.5gt393t6-lkp@intel.com/
> Fixes: 60eff75ac67b ("arm64: dts: amlogic: t7: khadas-vim4: Add power regulators")
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^ permalink raw reply
* Re: [PATCH 2/2] pwm: meson: Add support for Amlogic S7
From: Martin Blumenstingl @ 2026-03-30 21:44 UTC (permalink / raw)
To: xianwei.zhao
Cc: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, linux-pwm, devicetree, linux-kernel,
linux-arm-kernel, linux-amlogic
In-Reply-To: <20260326-s6-s7-pwm-v1-2-67e2f72b98bc@amlogic.com>
Hi Xianwei Zhao,
On Thu, Mar 26, 2026 at 7:35 AM Xianwei Zhao via B4 Relay
<devnull+xianwei.zhao.amlogic.com@kernel.org> wrote:
>
> From: Xianwei Zhao <xianwei.zhao@amlogic.com>
>
> Add support for Amlogic S7 PWM. Amlogic S7 different from the
> previous SoCs, a controller includes one pwm, at the same time,
> the controller has only one input clock source.
>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> ---
> drivers/pwm/pwm-meson.c | 32 ++++++++++++++++++++++++++++++--
> 1 file changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
> index 8c6bf3d49753..3d16694e254e 100644
> --- a/drivers/pwm/pwm-meson.c
> +++ b/drivers/pwm/pwm-meson.c
> @@ -113,6 +113,7 @@ struct meson_pwm_data {
> int (*channels_init)(struct pwm_chip *chip);
> bool has_constant;
> bool has_polarity;
> + bool single_pwm;
At first I wasn't sure about this and thought we should replace it
with a num_pwms (or similar) variable.
However, I think it will be hard to add a third (or even more)
channels to the PWM controller (not just from driver perspective but
also from hardware perspective). So I think this is good enough as the
choice will only be 1 or 2.
[...]
> +static const struct meson_pwm_data pwm_s7_data = {
> + .channels_init = meson_pwm_init_channels_s7,
I think you can use .channels_init = meson_pwm_init_channels_s4, if
you change the code inside that function from:
for (i = 0; i < MESON_NUM_PWMS; i++) {
to:
for (i = 0; i < chip->npwm; i++) {
[...]
> @@ -650,9 +674,13 @@ static int meson_pwm_probe(struct platform_device *pdev)
> {
> struct pwm_chip *chip;
> struct meson_pwm *meson;
> + const struct meson_pwm_data *pdata = of_device_get_match_data(&pdev->dev);
> int err;
>
> - chip = devm_pwmchip_alloc(&pdev->dev, MESON_NUM_PWMS, sizeof(*meson));
> + if (pdata->single_pwm)
> + chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*meson));
> + else
> + chip = devm_pwmchip_alloc(&pdev->dev, MESON_NUM_PWMS, sizeof(*meson));
I don't think this code is too bad for now.
However, I'm wondering if you want to make "channels" from struct
meson_pwm a flexible array member in a future patch. In that case it
will be helpful to have an "unsigned int npwm = pdata->single_pwm ? 1
: MESON_NUM_PWMS;" (or similar) variable to future-proof your code.
What do you think?
Best regards,
Martin
^ permalink raw reply
* Re: [PATCH v2 4/6] phy: realtek: usb2: introduce reset controller struct
From: Vladimir Oltean @ 2026-03-30 21:39 UTC (permalink / raw)
To: Rustam Adilov
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel,
Michael Zavertkin
In-Reply-To: <20260327160638.15134-5-adilov@disroot.org>
On Fri, Mar 27, 2026 at 09:06:36PM +0500, Rustam Adilov wrote:
> In RTL9607C, there is so called "IP Enable Controller" which resemble
> reset controller with reset lines and is used for various things like
> USB, PCIE, GMAC and such.
>
> Introduce the reset_control struct to this driver to handle deasserting
> usb2 phy reset line.
>
> Make use of the function devm_reset_control_array_get_optional_exclusive()
> function to get the reset controller and since existing RTD SoCs don't
> specify the resets we can have a cleaner code.
>
> Co-developed-by: Michael Zavertkin <misha.zavertkin@mail.ru>
> Signed-off-by: Michael Zavertkin <misha.zavertkin@mail.ru>
> Signed-off-by: Rustam Adilov <adilov@disroot.org>
> ---
> drivers/phy/realtek/phy-rtk-usb2.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-rtk-usb2.c
> index e65b8525b88b..070cba1e0e0a 100644
> --- a/drivers/phy/realtek/phy-rtk-usb2.c
> +++ b/drivers/phy/realtek/phy-rtk-usb2.c
> @@ -17,6 +17,7 @@
> #include <linux/sys_soc.h>
> #include <linux/mfd/syscon.h>
> #include <linux/phy/phy.h>
> +#include <linux/reset.h>
> #include <linux/usb.h>
>
> /* GUSB2PHYACCn register */
> @@ -130,6 +131,7 @@ struct rtk_phy {
> struct phy_cfg *phy_cfg;
> int num_phy;
> struct phy_parameter *phy_parameter;
> + struct reset_control *phy_rst;
>
> struct dentry *debug_dir;
> };
> @@ -602,6 +604,10 @@ static int do_rtk_phy_init(struct rtk_phy *rtk_phy, int index)
> phy_parameter = &((struct phy_parameter *)rtk_phy->phy_parameter)[index];
> phy_reg = &phy_parameter->phy_reg;
>
> + reset_control_deassert(rtk_phy->phy_rst);
LLM review says:
(less important)
Can reset_control_deassert() fail here? If there is a hardware communication
error with the reset controller, should this check the return value and
propagate the error up instead of proceeding to configure the PHY?
Additionally, since the exclusive reset line is deasserted here, does this
code need a corresponding reset_control_assert() in the driver's teardown
or exit path? Leaving the IP block permanently enabled after shutdown could
lead to power leaks and prevent proper hardware re-initialization.
> +
> + mdelay(5);
(more important)
This code unnecessarily penalizes existing platforms. If rtk_phy->phy_rst
is NULL (as on older platforms where the optional reset is not defined), the
delay still executes.
Also, since PHY initialization callbacks run in a sleepable context, would it
be better to use a sleep-based delay like usleep_range(5000, 6000) to yield
the CPU instead of busy-waiting with mdelay(5)?
> +
> if (phy_cfg->use_default_parameter) {
> dev_dbg(rtk_phy->dev, "%s phy#%d use default parameter\n",
> __func__, index);
> @@ -1069,6 +1075,12 @@ static int rtk_usb2phy_probe(struct platform_device *pdev)
>
> rtk_phy->num_phy = phy_cfg->num_phy;
>
> + rtk_phy->phy_rst = devm_reset_control_array_get_optional_exclusive(dev);
> + if (IS_ERR(rtk_phy->phy_rst)) {
> + dev_err(dev, "usb2 phy resets are not working\n");
> + return PTR_ERR(rtk_phy->phy_rst);
> + }
> +
(still LLM review)
If the reset controller driver is not yet ready, this will return
-EPROBE_DEFER and print an error message to the kernel log.
Should this use dev_err_probe() to silently handle probe deferral while
correctly logging actual errors?
> ret = parse_phy_data(rtk_phy);
> if (ret)
> goto err;
> --
> 2.53.0
>
>
^ permalink raw reply
* Re: [PATCH v2 2/6] phy: realtek: usb2: introduce read and write functions to driver data
From: Vladimir Oltean @ 2026-03-30 21:32 UTC (permalink / raw)
To: Rustam Adilov
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel,
Michael Zavertkin
In-Reply-To: <20260330211918.y7su36j47e3uelcv@skbuf>
On Tue, Mar 31, 2026 at 12:19:18AM +0300, Vladimir Oltean wrote:
> On Fri, Mar 27, 2026 at 09:06:34PM +0500, Rustam Adilov wrote:
> > +static inline u32 phy_read(void __iomem *reg)
> > +{
> > + return readl(reg);
> > +}
> > +
> > +static inline u32 phy_read_le(void __iomem *reg)
> > +{
> > + return le32_to_cpu(readl(reg));
> > +}
> > +
> > +static inline void phy_write(u32 val, void __iomem *reg)
> > +{
> > + writel(val, reg);
> > +}
> > +
> > +static inline void phy_write_le(u32 val, void __iomem *reg)
> > +{
> > + writel(cpu_to_le32(val), reg);
> > +}
>
> Please don't name driver-level functions phy_read() and phy_write().
> That will collide with networking API functions of the same name and
> will make grep-based code searching more difficult.
>
> Also, have you looked at regmap? It has native support for endianness;
> it supports regmap_field_read()/regmap_field_write() for abstracting
> registers which may be found at different places for different HW;
> it offers regmap_read_poll_timeout() so you don't have to pass the
> function pointer to utmi_wait_register(). It seems the result would be a
> bit more elegant.
Even if you decide not to use regmap. I thought I should let you know
that LLM review says:
Are these double byte-swaps intentional?
Since readl() and writel() inherently perform little-endian memory accesses
and handle byte-swapping on big-endian architectures automatically, won't
wrapping them in le32_to_cpu() and cpu_to_le32() apply a second, redundant
byte-swap?
On big-endian systems, wouldn't these double swaps cancel each other out
and result in a native big-endian access instead of the intended
little-endian access? If the SoC bus bridge implicitly swaps and requires
a native access, should __raw_readl() and __raw_writel() (or ioread32be /
iowrite32be) be used instead to avoid obfuscating it with double-swaps?
Also, does passing the __le32 restricted type returned by cpu_to_le32()
into writel() (which expects a native u32) trigger Sparse static analysis
warnings for an incorrect type in argument?
For reference:
https://elixir.bootlin.com/linux/v6.19.10/source/include/asm-generic/io.h#L184
/*
* {read,write}{b,w,l,q}() access little endian memory and return result in
* native endianness.
*/
and yes, your patch does trigger sparse warnings:
../drivers/phy/realtek/phy-rtk-usb2.c:153:16: warning: cast to restricted __le32
../drivers/phy/realtek/phy-rtk-usb2.c:163:16: warning: incorrect type in argument 1 (different base types)
../drivers/phy/realtek/phy-rtk-usb2.c:163:16: expected unsigned int val
../drivers/phy/realtek/phy-rtk-usb2.c:163:16: got restricted __le32 [usertype]
Furthermore, please drop the 'inline' keyword from C files and let the
compiler decide. Your use of this keyword has no value - you declare
phy_read(), phy_read_le() etc as inline but then assign function
pointers to them. How can the compiler inline the indirect calls?
^ permalink raw reply
* Re: [PATCH] arm64: dts: meson-gxl-p230: fix ethernet PHY interrupt number
From: Martin Blumenstingl @ 2026-03-30 21:25 UTC (permalink / raw)
To: Jun Yan
Cc: linux-kernel, linux-amlogic, linux-arm-kernel, devicetree, robh,
krzk+dt, conor+dt, neil.armstrong, khilman, jbrunet
In-Reply-To: <20260330145111.115318-1-jerrysteve1101@gmail.com>
On Mon, Mar 30, 2026 at 4:53 PM Jun Yan <jerrysteve1101@gmail.com> wrote:
>
> Correct the interrupt number assigned to the Realtek PHY in the p230
>
> following the same logic as commit 3106507e1004 ("ARM64: dts: meson-gxm:
> fix q200 interrupt number"),as reported in [PATCH 0/2] Ethernet PHY
> interrupt improvements [1].
>
> [1] https://lore.kernel.org/all/20171202214037.17017-1-martin.blumenstingl@googlemail.com/
>
> Fixes: b94d22d94ad2 ("ARM64: dts: meson-gx: add external PHY interrupt on some platforms")
> Signed-off-by: Jun Yan <jerrysteve1101@gmail.com>
Thank you! I don't have a matching device to verify this myself.
However, it's in line with commit 3106507e1004d ("ARM64: dts:
meson-gxm: fix q200 interrupt number") as IRQ 29 is GPIOZ_15 on GXBB
(but no longer on GXL/GXM). So this gets my:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^ permalink raw reply
* Re: [PATCH v2 2/6] phy: realtek: usb2: introduce read and write functions to driver data
From: Vladimir Oltean @ 2026-03-30 21:19 UTC (permalink / raw)
To: Rustam Adilov
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel,
Michael Zavertkin
In-Reply-To: <20260327160638.15134-3-adilov@disroot.org>
On Fri, Mar 27, 2026 at 09:06:34PM +0500, Rustam Adilov wrote:
> +static inline u32 phy_read(void __iomem *reg)
> +{
> + return readl(reg);
> +}
> +
> +static inline u32 phy_read_le(void __iomem *reg)
> +{
> + return le32_to_cpu(readl(reg));
> +}
> +
> +static inline void phy_write(u32 val, void __iomem *reg)
> +{
> + writel(val, reg);
> +}
> +
> +static inline void phy_write_le(u32 val, void __iomem *reg)
> +{
> + writel(cpu_to_le32(val), reg);
> +}
Please don't name driver-level functions phy_read() and phy_write().
That will collide with networking API functions of the same name and
will make grep-based code searching more difficult.
Also, have you looked at regmap? It has native support for endianness;
it supports regmap_field_read()/regmap_field_write() for abstracting
registers which may be found at different places for different HW;
it offers regmap_read_poll_timeout() so you don't have to pass the
function pointer to utmi_wait_register(). It seems the result would be a
bit more elegant.
^ permalink raw reply
* Re: (subset) [PATCH v9 0/8] Initial support for Samsung Galaxy Tab 2 series
From: Kevin Hilman @ 2026-03-30 21:19 UTC (permalink / raw)
To: Neil Armstrong, aaro.koskinen, airlied, andreas, conor+dt,
jernej.skrabec, jonas, krzk+dt, laurent.pinchart,
maarten.lankhorst, mripard, prabhakar.mahadev-lad.rj,
jesszhan0024, rfoss, robh, rogerq, simona, thierry.reding, tony,
tzimmermann, andrzej.hajda, Mithil Bavishi
Cc: devicetree, dri-devel, linux-kernel, linux-omap
In-Reply-To: <177451576215.103892.12129135091369769725.b4-ty@linaro.org>
Hi Neil,
Neil Armstrong <neil.armstrong@linaro.org> writes:
> Hi,
>
> On Tue, 03 Mar 2026 15:30:09 -0500, Mithil Bavishi wrote:
>> This series adds initial support for the Samsung Galaxy Tab 2
>> (samsung-espresso7/10) series of devices. It adds support for 6 variants
>> (P3100, P3110, P3113, P5100, P5110, P5113). Downstream categorised them
>> based on 3G and WiFi, but since they use different panel, touch
>> controllers, batteries, I decided to categorise them based on screen
>> size as espresso7 and espresso10.
>>
>> [...]
>
> Thanks, Applied to https://gitlab.freedesktop.org/drm/misc/kernel.git (drm-misc-next)
>
> [4/8] dt-bindings: display: panel-lvds: Add compatibles for Samsung LTN070NL01 and LTN101AL03 panels
> https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/d37690b5e02418a2365548300628ef3895a24ed2
Since the bindings patch already had acks from the DT maintainers, I
queued it along with the DT patches (via the OMAP tree.)
Do you prefer if I drop my version?
Kevin
^ permalink raw reply
* Re: [PATCH v2 1/3] ARM: dts: ti: Enable overlays for am335x BeagleBoard devicetrees
From: Kevin Hilman @ 2026-03-30 21:14 UTC (permalink / raw)
To: Kory Maincent
Cc: Aaro Koskinen, Andreas Kemnade, Roger Quadros, Tony Lindgren,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Russell King,
Thomas Petazzoni, linux-omap, devicetree, linux-kernel,
linux-arm-kernel, dri-devel, Luca Ceresoli, Bajjuri Praneeth,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Louis Chauvet
In-Reply-To: <20260324103934.7d259008@kmaincent-XPS-13-7390>
Kory Maincent <kory.maincent@bootlin.com> writes:
> Hello Kevin,
>
> On Thu, 05 Mar 2026 17:07:23 -0800
> Kevin Hilman <khilman@baylibre.com> wrote:
>
>> On Mon, 16 Feb 2026 17:55:52 +0100, Kory Maincent (TI) wrote:
>> > Allow overlays to be applied to am335x BeagleBoard boards. This adds
>> > around ~40% to the total size of the DTB files on average.
>> >
>> >
>>
>> Applied, thanks!
>>
>> [1/3] ARM: dts: ti: Enable overlays for am335x BeagleBoard devicetrees
>> commit: 18161bb01ede109fed41c66efa2624a4c27377f7
>>
>> Best regards,
>
> Thanks for merging it.
> I see that you have merged patch 1 and 2 in your for-next branch.
> Is there a reason to not merge the patch 3? Are you waiting for a dts
> maintainer ack?
>
> Maybe I can resend only the 3rd patch to ping the dts maintainers.
Not necessary. I'm not sure how/why I missed patch 3. It's now queued
in my tree.
Thanks for letting me know,
Kevin
^ permalink raw reply
* Re: [PATCH 0/4] drm/panel: simple: add Waveshare LCD panels
From: Marek Vasut @ 2026-03-30 17:21 UTC (permalink / raw)
To: Dmitry Baryshkov, Neil Armstrong, Jessica Zhang,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Thierry Reding, Sam Ravnborg, Joseph Guo, Marek Vasut,
Andrzej Hajda, Robert Foss, Laurent Pinchart, Jonas Karlman,
Jernej Skrabec
Cc: dri-devel, devicetree, linux-kernel
In-Reply-To: <20260330-ws-lcd-v1-0-309834a435c0@oss.qualcomm.com>
On 3/30/26 3:25 PM, Dmitry Baryshkov wrote:
> Waveshare have a serie of DSI panel kits with the DPI or LVDS panel
> being attached to the DSI2DPI or DSI2LVDS bridge. Commit 80b0eb11f8e0
> ("dt-bindings: display: panel: Add waveshare DPI panel support")
> described two of them in the bindings and commit 46be11b678e0
> ("drm/panel: simple: Add Waveshare 13.3" panel support") added
> definitions for one of those panels. Add support for the rest of them.
Can we by any chance use the icn6211 driver in tree for this ?
^ permalink raw reply
* [PATCH ath-next v3 6/6] wifi: ath12k: Enable IPQ5424 WiFi device support
From: Raj Kumar Bhagat @ 2026-03-30 20:39 UTC (permalink / raw)
To: Johannes Berg, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jeff Johnson
Cc: linux-wireless, devicetree, linux-kernel, ath12k,
Raj Kumar Bhagat, Sowmiya Sree Elavalagan,
Saravanakumar Duraisamy
In-Reply-To: <20260331-ath12k-ipq5424-v3-0-1455b9cae29c@oss.qualcomm.com>
From: Sowmiya Sree Elavalagan <sowmiya.elavalagan@oss.qualcomm.com>
Currently, ath12k AHB (in IPQ5332) uses SCM calls to authenticate the
firmware image to bring up userpd. From IPQ5424 onwards, Q6 firmware can
directly communicate with the Trusted Management Engine - Lite (TME-L),
eliminating the need for SCM calls for userpd bring-up.
Hence, to enable IPQ5424 device support, use qcom_mdt_load_no_init() and
skip the SCM call as Q6 will directly authenticate the userpd firmware.
Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.6-01243-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5332 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5424 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1
Signed-off-by: Sowmiya Sree Elavalagan <sowmiya.elavalagan@oss.qualcomm.com>
Co-developed-by: Saravanakumar Duraisamy <quic_saradura@quicinc.com>
Signed-off-by: Saravanakumar Duraisamy <quic_saradura@quicinc.com>
Co-developed-by: Raj Kumar Bhagat <raj.bhagat@oss.qualcomm.com>
Signed-off-by: Raj Kumar Bhagat <raj.bhagat@oss.qualcomm.com>
---
drivers/net/wireless/ath/ath12k/ahb.c | 36 ++++++++++++++++++-----------
drivers/net/wireless/ath/ath12k/ahb.h | 1 +
drivers/net/wireless/ath/ath12k/wifi7/ahb.c | 8 +++++++
3 files changed, 31 insertions(+), 14 deletions(-)
diff --git a/drivers/net/wireless/ath/ath12k/ahb.c b/drivers/net/wireless/ath/ath12k/ahb.c
index 9a4d34e49104..2dcf0a52e4c1 100644
--- a/drivers/net/wireless/ath/ath12k/ahb.c
+++ b/drivers/net/wireless/ath/ath12k/ahb.c
@@ -382,8 +382,12 @@ static int ath12k_ahb_power_up(struct ath12k_base *ab)
ATH12K_AHB_UPD_SWID;
/* Load FW image to a reserved memory location */
- ret = qcom_mdt_load(dev, fw, fw_name, pasid, mem_region, mem_phys, mem_size,
- &mem_phys);
+ if (ab_ahb->scm_auth_enabled)
+ ret = qcom_mdt_load(dev, fw, fw_name, pasid, mem_region,
+ mem_phys, mem_size, &mem_phys);
+ else
+ ret = qcom_mdt_load_no_init(dev, fw, fw_name, mem_region,
+ mem_phys, mem_size, &mem_phys);
if (ret) {
ath12k_err(ab, "Failed to load MDT segments: %d\n", ret);
goto err_fw;
@@ -414,11 +418,13 @@ static int ath12k_ahb_power_up(struct ath12k_base *ab)
goto err_fw2;
}
- /* Authenticate FW image using peripheral ID */
- ret = qcom_scm_pas_auth_and_reset(pasid);
- if (ret) {
- ath12k_err(ab, "failed to boot the remote processor %d\n", ret);
- goto err_fw2;
+ if (ab_ahb->scm_auth_enabled) {
+ /* Authenticate FW image using peripheral ID */
+ ret = qcom_scm_pas_auth_and_reset(pasid);
+ if (ret) {
+ ath12k_err(ab, "failed to boot the remote processor %d\n", ret);
+ goto err_fw2;
+ }
}
/* Instruct Q6 to spawn userPD thread */
@@ -475,13 +481,15 @@ static void ath12k_ahb_power_down(struct ath12k_base *ab, bool is_suspend)
qcom_smem_state_update_bits(ab_ahb->stop_state, BIT(ab_ahb->stop_bit), 0);
- pasid = (u32_encode_bits(ab_ahb->userpd_id, ATH12K_USERPD_ID_MASK)) |
- ATH12K_AHB_UPD_SWID;
- /* Release the firmware */
- ret = qcom_scm_pas_shutdown(pasid);
- if (ret)
- ath12k_err(ab, "scm pas shutdown failed for userPD%d: %d\n",
- ab_ahb->userpd_id, ret);
+ if (ab_ahb->scm_auth_enabled) {
+ pasid = (u32_encode_bits(ab_ahb->userpd_id, ATH12K_USERPD_ID_MASK)) |
+ ATH12K_AHB_UPD_SWID;
+ /* Release the firmware */
+ ret = qcom_scm_pas_shutdown(pasid);
+ if (ret)
+ ath12k_err(ab, "scm pas shutdown failed for userPD%d\n",
+ ab_ahb->userpd_id);
+ }
}
static void ath12k_ahb_init_qmi_ce_config(struct ath12k_base *ab)
diff --git a/drivers/net/wireless/ath/ath12k/ahb.h b/drivers/net/wireless/ath/ath12k/ahb.h
index be9e31b3682d..0fa15daaa3e6 100644
--- a/drivers/net/wireless/ath/ath12k/ahb.h
+++ b/drivers/net/wireless/ath/ath12k/ahb.h
@@ -68,6 +68,7 @@ struct ath12k_ahb {
int userpd_irq_num[ATH12K_USERPD_MAX_IRQ];
const struct ath12k_ahb_ops *ahb_ops;
const struct ath12k_ahb_device_family_ops *device_family_ops;
+ bool scm_auth_enabled;
};
struct ath12k_ahb_driver {
diff --git a/drivers/net/wireless/ath/ath12k/wifi7/ahb.c b/drivers/net/wireless/ath/ath12k/wifi7/ahb.c
index a6c5f7689edd..6a8b8b2a56f9 100644
--- a/drivers/net/wireless/ath/ath12k/wifi7/ahb.c
+++ b/drivers/net/wireless/ath/ath12k/wifi7/ahb.c
@@ -19,6 +19,9 @@ static const struct of_device_id ath12k_wifi7_ahb_of_match[] = {
{ .compatible = "qcom,ipq5332-wifi",
.data = (void *)ATH12K_HW_IPQ5332_HW10,
},
+ { .compatible = "qcom,ipq5424-wifi",
+ .data = (void *)ATH12K_HW_IPQ5424_HW10,
+ },
{ }
};
@@ -38,6 +41,11 @@ static int ath12k_wifi7_ahb_probe(struct platform_device *pdev)
switch (hw_rev) {
case ATH12K_HW_IPQ5332_HW10:
ab_ahb->userpd_id = ATH12K_IPQ5332_USERPD_ID;
+ ab_ahb->scm_auth_enabled = true;
+ break;
+ case ATH12K_HW_IPQ5424_HW10:
+ ab_ahb->userpd_id = ATH12K_IPQ5332_USERPD_ID;
+ ab_ahb->scm_auth_enabled = false;
break;
default:
return -EOPNOTSUPP;
--
2.34.1
^ permalink raw reply related
* [PATCH ath-next v3 5/6] wifi: ath12k: Add CE remap hardware parameters for IPQ5424
From: Raj Kumar Bhagat @ 2026-03-30 20:39 UTC (permalink / raw)
To: Johannes Berg, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jeff Johnson
Cc: linux-wireless, devicetree, linux-kernel, ath12k,
Raj Kumar Bhagat, Saravanakumar Duraisamy
In-Reply-To: <20260331-ath12k-ipq5424-v3-0-1455b9cae29c@oss.qualcomm.com>
From: Saravanakumar Duraisamy <quic_saradura@quicinc.com>
Add CE remap hardware parameters for Ath12k AHB device IPQ5424.
Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.6-01243-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5332 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5424 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1
Signed-off-by: Saravanakumar Duraisamy <quic_saradura@quicinc.com>
Signed-off-by: Raj Kumar Bhagat <raj.bhagat@oss.qualcomm.com>
---
drivers/net/wireless/ath/ath12k/ce.h | 13 +++++++++----
drivers/net/wireless/ath/ath12k/wifi7/hw.c | 22 +++++++++++++++++-----
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/net/wireless/ath/ath12k/ce.h b/drivers/net/wireless/ath/ath12k/ce.h
index df4f2a4f8480..009cddf2d68d 100644
--- a/drivers/net/wireless/ath/ath12k/ce.h
+++ b/drivers/net/wireless/ath/ath12k/ce.h
@@ -38,10 +38,15 @@
#define PIPEDIR_INOUT 3 /* bidirectional */
#define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */
-/* CE address/mask */
-#define CE_HOST_IE_ADDRESS 0x75804C
-#define CE_HOST_IE_2_ADDRESS 0x758050
-#define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS
+/* IPQ5332 CE address/mask */
+#define CE_HOST_IPQ5332_IE_ADDRESS 0x75804C
+#define CE_HOST_IPQ5332_IE_2_ADDRESS 0x758050
+#define CE_HOST_IPQ5332_IE_3_ADDRESS CE_HOST_IPQ5332_IE_ADDRESS
+
+/* IPQ5424 CE address/mask */
+#define CE_HOST_IPQ5424_IE_ADDRESS 0x21804C
+#define CE_HOST_IPQ5424_IE_2_ADDRESS 0x218050
+#define CE_HOST_IPQ5424_IE_3_ADDRESS CE_HOST_IPQ5424_IE_ADDRESS
#define CE_HOST_IE_3_SHIFT 0xC
diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hw.c b/drivers/net/wireless/ath/ath12k/wifi7/hw.c
index 9b9ca06a9f45..a2c98cc1e348 100644
--- a/drivers/net/wireless/ath/ath12k/wifi7/hw.c
+++ b/drivers/net/wireless/ath/ath12k/wifi7/hw.c
@@ -329,9 +329,15 @@ static const struct ath12k_hw_ring_mask ath12k_wifi7_hw_ring_mask_wcn7850 = {
};
static const struct ce_ie_addr ath12k_wifi7_ce_ie_addr_ipq5332 = {
- .ie1_reg_addr = CE_HOST_IE_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
- .ie2_reg_addr = CE_HOST_IE_2_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
- .ie3_reg_addr = CE_HOST_IE_3_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
+ .ie1_reg_addr = CE_HOST_IPQ5332_IE_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
+ .ie2_reg_addr = CE_HOST_IPQ5332_IE_2_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
+ .ie3_reg_addr = CE_HOST_IPQ5332_IE_3_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
+};
+
+static const struct ce_ie_addr ath12k_wifi7_ce_ie_addr_ipq5424 = {
+ .ie1_reg_addr = CE_HOST_IPQ5424_IE_ADDRESS - HAL_IPQ5424_CE_WFSS_REG_BASE,
+ .ie2_reg_addr = CE_HOST_IPQ5424_IE_2_ADDRESS - HAL_IPQ5424_CE_WFSS_REG_BASE,
+ .ie3_reg_addr = CE_HOST_IPQ5424_IE_3_ADDRESS - HAL_IPQ5424_CE_WFSS_REG_BASE,
};
static const struct ce_remap ath12k_wifi7_ce_remap_ipq5332 = {
@@ -340,6 +346,12 @@ static const struct ce_remap ath12k_wifi7_ce_remap_ipq5332 = {
.cmem_offset = HAL_SEQ_WCSS_CMEM_OFFSET,
};
+static const struct ce_remap ath12k_wifi7_ce_remap_ipq5424 = {
+ .base = HAL_IPQ5424_CE_WFSS_REG_BASE,
+ .size = HAL_IPQ5424_CE_SIZE,
+ .cmem_offset = HAL_SEQ_WCSS_CMEM_OFFSET,
+};
+
static const struct ath12k_hw_params ath12k_wifi7_hw_params[] = {
{
.name = "qcn9274 hw1.0",
@@ -822,8 +834,8 @@ static const struct ath12k_hw_params ath12k_wifi7_hw_params[] = {
.iova_mask = 0,
.supports_aspm = false,
- .ce_ie_addr = NULL,
- .ce_remap = NULL,
+ .ce_ie_addr = &ath12k_wifi7_ce_ie_addr_ipq5424,
+ .ce_remap = &ath12k_wifi7_ce_remap_ipq5424,
.bdf_addr_offset = 0x940000,
.dp_primary_link_only = true,
--
2.34.1
^ permalink raw reply related
* [PATCH ath-next v3 4/6] wifi: ath12k: add ath12k_hw_regs for IPQ5424
From: Raj Kumar Bhagat @ 2026-03-30 20:39 UTC (permalink / raw)
To: Johannes Berg, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jeff Johnson
Cc: linux-wireless, devicetree, linux-kernel, ath12k,
Raj Kumar Bhagat, Saravanakumar Duraisamy
In-Reply-To: <20260331-ath12k-ipq5424-v3-0-1455b9cae29c@oss.qualcomm.com>
From: Saravanakumar Duraisamy <quic_saradura@quicinc.com>
Add register addresses (ath12k_hw_regs) for ath12k AHB based
WiFi 7 device IPQ5424.
Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.6-01243-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5332 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5424 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1
Signed-off-by: Saravanakumar Duraisamy <quic_saradura@quicinc.com>
Signed-off-by: Raj Kumar Bhagat <raj.bhagat@oss.qualcomm.com>
---
drivers/net/wireless/ath/ath12k/wifi7/hal.c | 2 +-
drivers/net/wireless/ath/ath12k/wifi7/hal.h | 3 +
.../net/wireless/ath/ath12k/wifi7/hal_qcn9274.c | 88 ++++++++++++++++++++++
.../net/wireless/ath/ath12k/wifi7/hal_qcn9274.h | 1 +
4 files changed, 93 insertions(+), 1 deletion(-)
diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal.c b/drivers/net/wireless/ath/ath12k/wifi7/hal.c
index c2cc99a83f09..a0a1902fb491 100644
--- a/drivers/net/wireless/ath/ath12k/wifi7/hal.c
+++ b/drivers/net/wireless/ath/ath12k/wifi7/hal.c
@@ -55,7 +55,7 @@ static const struct ath12k_hw_version_map ath12k_wifi7_hw_ver_map[] = {
.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274_compact),
.tcl_to_wbm_rbm_map = ath12k_hal_tcl_to_wbm_rbm_map_qcn9274,
.hal_params = &ath12k_hw_hal_params_ipq5332,
- .hw_regs = NULL,
+ .hw_regs = &ipq5424_regs,
},
};
diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal.h b/drivers/net/wireless/ath/ath12k/wifi7/hal.h
index 9337225a5253..3d9386198893 100644
--- a/drivers/net/wireless/ath/ath12k/wifi7/hal.h
+++ b/drivers/net/wireless/ath/ath12k/wifi7/hal.h
@@ -364,6 +364,9 @@
#define HAL_IPQ5332_CE_WFSS_REG_BASE 0x740000
#define HAL_IPQ5332_CE_SIZE 0x100000
+#define HAL_IPQ5424_CE_WFSS_REG_BASE 0x200000
+#define HAL_IPQ5424_CE_SIZE 0x100000
+
#define HAL_RX_MAX_BA_WINDOW 256
#define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC (100 * 1000)
diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c
index 41c918eb1767..ba9ce1e718e8 100644
--- a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c
+++ b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c
@@ -484,6 +484,94 @@ const struct ath12k_hw_regs ipq5332_regs = {
HAL_IPQ5332_CE_WFSS_REG_BASE,
};
+const struct ath12k_hw_regs ipq5424_regs = {
+ /* SW2TCL(x) R0 ring configuration address */
+ .tcl1_ring_id = 0x00000918,
+ .tcl1_ring_misc = 0x00000920,
+ .tcl1_ring_tp_addr_lsb = 0x0000092c,
+ .tcl1_ring_tp_addr_msb = 0x00000930,
+ .tcl1_ring_consumer_int_setup_ix0 = 0x00000940,
+ .tcl1_ring_consumer_int_setup_ix1 = 0x00000944,
+ .tcl1_ring_msi1_base_lsb = 0x00000958,
+ .tcl1_ring_msi1_base_msb = 0x0000095c,
+ .tcl1_ring_base_lsb = 0x00000910,
+ .tcl1_ring_base_msb = 0x00000914,
+ .tcl1_ring_msi1_data = 0x00000960,
+ .tcl2_ring_base_lsb = 0x00000988,
+ .tcl_ring_base_lsb = 0x00000b68,
+
+ /* TCL STATUS ring address */
+ .tcl_status_ring_base_lsb = 0x00000d48,
+
+ /* REO DEST ring address */
+ .reo2_ring_base = 0x00000578,
+ .reo1_misc_ctrl_addr = 0x00000b9c,
+ .reo1_sw_cookie_cfg0 = 0x0000006c,
+ .reo1_sw_cookie_cfg1 = 0x00000070,
+ .reo1_qdesc_lut_base0 = 0x00000074,
+ .reo1_qdesc_lut_base1 = 0x00000078,
+ .reo1_ring_base_lsb = 0x00000500,
+ .reo1_ring_base_msb = 0x00000504,
+ .reo1_ring_id = 0x00000508,
+ .reo1_ring_misc = 0x00000510,
+ .reo1_ring_hp_addr_lsb = 0x00000514,
+ .reo1_ring_hp_addr_msb = 0x00000518,
+ .reo1_ring_producer_int_setup = 0x00000524,
+ .reo1_ring_msi1_base_lsb = 0x00000548,
+ .reo1_ring_msi1_base_msb = 0x0000054C,
+ .reo1_ring_msi1_data = 0x00000550,
+ .reo1_aging_thres_ix0 = 0x00000B28,
+ .reo1_aging_thres_ix1 = 0x00000B2C,
+ .reo1_aging_thres_ix2 = 0x00000B30,
+ .reo1_aging_thres_ix3 = 0x00000B34,
+
+ /* REO Exception ring address */
+ .reo2_sw0_ring_base = 0x000008c0,
+
+ /* REO Reinject ring address */
+ .sw2reo_ring_base = 0x00000320,
+ .sw2reo1_ring_base = 0x00000398,
+
+ /* REO cmd ring address */
+ .reo_cmd_ring_base = 0x000002A8,
+
+ /* REO status ring address */
+ .reo_status_ring_base = 0x00000aa0,
+
+ /* WBM idle link ring address */
+ .wbm_idle_ring_base_lsb = 0x00000d3c,
+ .wbm_idle_ring_misc_addr = 0x00000d4c,
+ .wbm_r0_idle_list_cntl_addr = 0x00000240,
+ .wbm_r0_idle_list_size_addr = 0x00000244,
+ .wbm_scattered_ring_base_lsb = 0x00000250,
+ .wbm_scattered_ring_base_msb = 0x00000254,
+ .wbm_scattered_desc_head_info_ix0 = 0x00000260,
+ .wbm_scattered_desc_head_info_ix1 = 0x00000264,
+ .wbm_scattered_desc_tail_info_ix0 = 0x00000270,
+ .wbm_scattered_desc_tail_info_ix1 = 0x00000274,
+ .wbm_scattered_desc_ptr_hp_addr = 0x0000027c,
+
+ /* SW2WBM release ring address */
+ .wbm_sw_release_ring_base_lsb = 0x0000037c,
+
+ /* WBM2SW release ring address */
+ .wbm0_release_ring_base_lsb = 0x00000e08,
+ .wbm1_release_ring_base_lsb = 0x00000e80,
+
+ /* PPE release ring address */
+ .ppe_rel_ring_base = 0x0000046c,
+
+ /* CE address */
+ .umac_ce0_src_reg_base = 0x00200000 -
+ HAL_IPQ5424_CE_WFSS_REG_BASE,
+ .umac_ce0_dest_reg_base = 0x00201000 -
+ HAL_IPQ5424_CE_WFSS_REG_BASE,
+ .umac_ce1_src_reg_base = 0x00202000 -
+ HAL_IPQ5424_CE_WFSS_REG_BASE,
+ .umac_ce1_dest_reg_base = 0x00203000 -
+ HAL_IPQ5424_CE_WFSS_REG_BASE,
+};
+
static inline
bool ath12k_hal_rx_desc_get_first_msdu_qcn9274(struct hal_rx_desc *desc)
{
diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.h b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.h
index 08c0a0469474..03cf3792d523 100644
--- a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.h
+++ b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.h
@@ -17,6 +17,7 @@ extern const struct hal_ops hal_qcn9274_ops;
extern const struct ath12k_hw_regs qcn9274_v1_regs;
extern const struct ath12k_hw_regs qcn9274_v2_regs;
extern const struct ath12k_hw_regs ipq5332_regs;
+extern const struct ath12k_hw_regs ipq5424_regs;
extern const struct ath12k_hal_tcl_to_wbm_rbm_map
ath12k_hal_tcl_to_wbm_rbm_map_qcn9274[DP_TCL_NUM_RING_MAX];
extern const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274;
--
2.34.1
^ permalink raw reply related
* [PATCH ath-next v3 3/6] wifi: ath12k: add ath12k_hw_version_map entry for IPQ5424
From: Raj Kumar Bhagat @ 2026-03-30 20:39 UTC (permalink / raw)
To: Johannes Berg, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jeff Johnson
Cc: linux-wireless, devicetree, linux-kernel, ath12k,
Raj Kumar Bhagat
In-Reply-To: <20260331-ath12k-ipq5424-v3-0-1455b9cae29c@oss.qualcomm.com>
Add a new ath12k_hw_version_map entry for the AHB based WiFi 7 device
IPQ5424.
Reuse most of the ath12k_hw_version_map fields such as hal_ops,
hal_desc_sz, tcl_to_wbm_rbm_map, and hal_params from IPQ5332. The
register addresses differ on IPQ5424, hence set hw_regs temporarily
to NULL and populated it in a subsequent patch.
Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.6-01243-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5332 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5424 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1
Signed-off-by: Raj Kumar Bhagat <raj.bhagat@oss.qualcomm.com>
---
drivers/net/wireless/ath/ath12k/wifi7/hal.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal.c b/drivers/net/wireless/ath/ath12k/wifi7/hal.c
index bd1753ca0db6..c2cc99a83f09 100644
--- a/drivers/net/wireless/ath/ath12k/wifi7/hal.c
+++ b/drivers/net/wireless/ath/ath12k/wifi7/hal.c
@@ -50,6 +50,13 @@ static const struct ath12k_hw_version_map ath12k_wifi7_hw_ver_map[] = {
.hal_params = &ath12k_hw_hal_params_wcn7850,
.hw_regs = &qcc2072_regs,
},
+ [ATH12K_HW_IPQ5424_HW10] = {
+ .hal_ops = &hal_qcn9274_ops,
+ .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274_compact),
+ .tcl_to_wbm_rbm_map = ath12k_hal_tcl_to_wbm_rbm_map_qcn9274,
+ .hal_params = &ath12k_hw_hal_params_ipq5332,
+ .hw_regs = NULL,
+ },
};
int ath12k_wifi7_hal_init(struct ath12k_base *ab)
--
2.34.1
^ permalink raw reply related
* [PATCH ath-next v3 2/6] wifi: ath12k: Add ath12k_hw_params for IPQ5424
From: Raj Kumar Bhagat @ 2026-03-30 20:39 UTC (permalink / raw)
To: Johannes Berg, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jeff Johnson
Cc: linux-wireless, devicetree, linux-kernel, ath12k,
Raj Kumar Bhagat, Saravanakumar Duraisamy
In-Reply-To: <20260331-ath12k-ipq5424-v3-0-1455b9cae29c@oss.qualcomm.com>
From: Saravanakumar Duraisamy <quic_saradura@quicinc.com>
Add ath12k_hw_params for the ath12k AHB-based WiFi 7 device IPQ5424.
The WiFi device IPQ5424 is similar to IPQ5332. Most of the hardware
parameters like hw_ops, wmi_init, ring_mask, etc., are the same between
IPQ5424 and IPQ5332, hence use these same parameters for IPQ5424.
Some parameters are specific to IPQ5424; initially set these to
0 or NULL, and populate them in subsequent patches.
Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.6-01243-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5332 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5424 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1
Signed-off-by: Saravanakumar Duraisamy <quic_saradura@quicinc.com>
Signed-off-by: Raj Kumar Bhagat <raj.bhagat@oss.qualcomm.com>
---
drivers/net/wireless/ath/ath12k/core.h | 1 +
drivers/net/wireless/ath/ath12k/wifi7/hw.c | 75 ++++++++++++++++++++++++++++++
2 files changed, 76 insertions(+)
diff --git a/drivers/net/wireless/ath/ath12k/core.h b/drivers/net/wireless/ath/ath12k/core.h
index 59c193b24764..68453594eba8 100644
--- a/drivers/net/wireless/ath/ath12k/core.h
+++ b/drivers/net/wireless/ath/ath12k/core.h
@@ -157,6 +157,7 @@ enum ath12k_hw_rev {
ATH12K_HW_WCN7850_HW20,
ATH12K_HW_IPQ5332_HW10,
ATH12K_HW_QCC2072_HW10,
+ ATH12K_HW_IPQ5424_HW10,
};
enum ath12k_firmware_mode {
diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hw.c b/drivers/net/wireless/ath/ath12k/wifi7/hw.c
index ec6dba96640b..9b9ca06a9f45 100644
--- a/drivers/net/wireless/ath/ath12k/wifi7/hw.c
+++ b/drivers/net/wireless/ath/ath12k/wifi7/hw.c
@@ -753,6 +753,81 @@ static const struct ath12k_hw_params ath12k_wifi7_hw_params[] = {
.dp_primary_link_only = false,
},
+ {
+ .name = "ipq5424 hw1.0",
+ .hw_rev = ATH12K_HW_IPQ5424_HW10,
+ .fw = {
+ .dir = "IPQ5424/hw1.0",
+ .board_size = 256 * 1024,
+ .cal_offset = 128 * 1024,
+ .m3_loader = ath12k_m3_fw_loader_remoteproc,
+ .download_aux_ucode = false,
+ },
+ .max_radios = 1,
+ .single_pdev_only = false,
+ .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332,
+ .internal_sleep_clock = false,
+
+ .hw_ops = &qcn9274_ops,
+ .ring_mask = &ath12k_wifi7_hw_ring_mask_ipq5332,
+
+ .host_ce_config = ath12k_wifi7_host_ce_config_ipq5332,
+ .ce_count = 12,
+ .target_ce_config = ath12k_wifi7_target_ce_config_wlan_ipq5332,
+ .target_ce_count = 12,
+ .svc_to_ce_map =
+ ath12k_wifi7_target_service_to_ce_map_wlan_ipq5332,
+ .svc_to_ce_map_len = 18,
+
+ .rxdma1_enable = true,
+ .num_rxdma_per_pdev = 1,
+ .num_rxdma_dst_ring = 0,
+ .rx_mac_buf_ring = false,
+ .vdev_start_delay = false,
+
+ .interface_modes = BIT(NL80211_IFTYPE_STATION) |
+ BIT(NL80211_IFTYPE_AP) |
+ BIT(NL80211_IFTYPE_MESH_POINT),
+ .supports_monitor = true,
+
+ .idle_ps = false,
+ .download_calib = true,
+ .supports_suspend = false,
+ .tcl_ring_retry = true,
+ .reoq_lut_support = false,
+ .supports_shadow_regs = false,
+
+ .num_tcl_banks = 48,
+ .max_tx_ring = 4,
+
+ .wmi_init = &ath12k_wifi7_wmi_init_qcn9274,
+
+ .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01),
+
+ .rfkill_pin = 0,
+ .rfkill_cfg = 0,
+ .rfkill_on_level = 0,
+
+ .rddm_size = 0,
+
+ .def_num_link = 0,
+ .max_mlo_peer = 256,
+
+ .otp_board_id_register = 0,
+
+ .supports_sta_ps = false,
+
+ .acpi_guid = NULL,
+ .supports_dynamic_smps_6ghz = false,
+ .iova_mask = 0,
+ .supports_aspm = false,
+
+ .ce_ie_addr = NULL,
+ .ce_remap = NULL,
+ .bdf_addr_offset = 0x940000,
+
+ .dp_primary_link_only = true,
+ },
};
/* Note: called under rcu_read_lock() */
--
2.34.1
^ permalink raw reply related
* [PATCH ath-next v3 1/6] dt-bindings: net: wireless: add ath12k wifi device IPQ5424
From: Raj Kumar Bhagat @ 2026-03-30 20:39 UTC (permalink / raw)
To: Johannes Berg, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jeff Johnson
Cc: linux-wireless, devicetree, linux-kernel, ath12k,
Raj Kumar Bhagat
In-Reply-To: <20260331-ath12k-ipq5424-v3-0-1455b9cae29c@oss.qualcomm.com>
Add the device-tree bindings for the ATH12K AHB wifi device IPQ5424.
Signed-off-by: Raj Kumar Bhagat <raj.bhagat@oss.qualcomm.com>
---
Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml
index 363a0ecb6ad9..b30f639b4c91 100644
--- a/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml
+++ b/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/wireless/qcom,ipq5332-wifi.yaml#
@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- qcom,ipq5332-wifi
+ - qcom,ipq5424-wifi
reg:
maxItems: 1
--
2.34.1
^ permalink raw reply related
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