* [PATCH v4 1/3] riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2
From: Han Gao @ 2026-03-31 16:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao
In-Reply-To: <cover.1774974017.git.gaohan@iscas.ac.cn>
The adapter is used to access the SpacemiT P1 PMIC present in this board.
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index 7b7331cb3c72..93880ba7bdfe 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -87,6 +87,12 @@ &pdma {
status = "okay";
};
+&i2c8 {
+ pinctrl-0 = <&i2c8_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
--
2.47.3
^ permalink raw reply related
* [PATCH v4 2/3] riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2
From: Han Gao @ 2026-03-31 16:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao
In-Reply-To: <cover.1774974017.git.gaohan@iscas.ac.cn>
Define the DC power input and the 4v power as fixed regulator supplies.
Define the SpacemiT P1 PMIC voltage regulators and their constraints.
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 97 +++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index 93880ba7bdfe..e5e358d49c09 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -23,6 +23,15 @@ chosen {
stdout-path = "serial0";
};
+ reg_vcc_4v: regulator-vcc-4v {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc4v0";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
leds {
compatible = "gpio-leds";
@@ -91,6 +100,94 @@ &i2c8 {
pinctrl-0 = <&i2c8_cfg>;
pinctrl-names = "default";
status = "okay";
+
+ pmic@41 {
+ compatible = "spacemit,p1";
+ reg = <0x41>;
+ interrupts = <64>;
+ vin1-supply = <®_vcc_4v>;
+ vin2-supply = <®_vcc_4v>;
+ vin3-supply = <®_vcc_4v>;
+ vin4-supply = <®_vcc_4v>;
+ vin5-supply = <®_vcc_4v>;
+ vin6-supply = <®_vcc_4v>;
+ aldoin-supply = <®_vcc_4v>;
+ dldoin1-supply = <&buck5>;
+ dldoin2-supply = <&buck5>;
+
+ regulators {
+ buck1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck3_1v8: buck3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck5: buck5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ aldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ dldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ dldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+ };
+ };
};
&uart0 {
--
2.47.3
^ permalink raw reply related
* [PATCH v4 0/3] riscv: dts: spacemit: Add PMIC regulators usb pcie
From: Han Gao @ 2026-03-31 16:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao
Changes in v4:
- Drop reg_dc_in
- Drop vin-supply from reg_vcc_4v
- Rename regulator-name to match schematic net names: vcc4v0, pcie_vcc3v3
- Remove aldo2, aldo3, aldo4, dldo2, dldo3, dldo7 nodes
- Drop usb3_hub_5v, no device consumer
- Drop vdd-supply from USB hub nodes, hub is powered by always-on VCC_5V0
- Drop "identical to BPI-F3" claim from commit message
- Link to v3: https://lore.kernel.org/all/cover.1774803532.git.gaohan@iscas.ac.cn/
Han Gao (3):
riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2
riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2
riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 171 ++++++++++++++++++
1 file changed, 171 insertions(+)
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
prerequisite-patch-id: ef6e9c7b5854d0c08066b72f9a7868db8c2140eb
prerequisite-patch-id: cfe3800f8c791ec4c63e070af9628e88e0fc31b9
prerequisite-patch-id: b76493e625ae257c8adcd67874178458420e4d47
prerequisite-patch-id: 88e01dc92c83bd88ddeb78891d3088209fed8d6b
prerequisite-patch-id: 60336d10ab8322c70596d0f046b6b5c54bb24b54
prerequisite-patch-id: 68c4d869548687dc115dd91e2ffb8f4c11482d86
prerequisite-patch-id: fdadcf964c2cb3406160edb579d99a8d5695f8e6
prerequisite-patch-id: 73b9e745338b0499b849fa4f7f9508987ab39a59
prerequisite-patch-id: cd26770c2160c3c31a406bd8a6b01ab666180ae0
prerequisite-patch-id: e5dfddc32cefae195692da8b80e19adf086e4ad7
prerequisite-patch-id: 7fd53cbe4977598f26148a4bb1cf692bbdb79a09
prerequisite-patch-id: 96ebac57bb29619b97fe95422206a685825618e9
prerequisite-patch-id: 00fac16b52f60383db3140e2885f3f7f8d14dd1a
prerequisite-patch-id: 3b7a60047b922c48e93599f621cb738856f42354
prerequisite-patch-id: 275c030b963be05dd1041451f539a130ce614277
prerequisite-patch-id: 93963424b0871e64276af0e0b2199b52e29b4603
prerequisite-patch-id: 8383188b1c01ed6280629faaa29c37d699ade241
prerequisite-patch-id: 5f8126b912b924d63d4a1e0c5eb42d212eb0d369
prerequisite-patch-id: e80af628a2e0b5f2eeb3cb1b5e7133d08bdd2c4e
prerequisite-patch-id: 0234a6dca15eb91f98a45a46604ce5b4935048a5
--
2.47.3
^ permalink raw reply
* [PATCH v4 3/3] riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
From: Han Gao @ 2026-03-31 16:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao
In-Reply-To: <cover.1774974017.git.gaohan@iscas.ac.cn>
Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the
OrangePi RV2 board.
The board utilizes a Genesys Logic GL3523 USB3.0 hub.
Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and
PHY-related Device Tree nodes for the OrangePi RV2.
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index e5e358d49c09..e93e7f660820 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -23,6 +23,15 @@ chosen {
stdout-path = "serial0";
};
+ pcie_vcc_3v3: regulator-pcie-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie_vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_vcc_4v: regulator-vcc-4v {
compatible = "regulator-fixed";
regulator-name = "vcc4v0";
@@ -44,6 +53,10 @@ led1 {
};
};
+&combo_phy {
+ status = "okay";
+};
+
ð0 {
phy-handle = <&rgmii0>;
phy-mode = "rgmii-id";
@@ -190,8 +203,63 @@ dldo6 {
};
};
+&pcie1_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_3_cfg>;
+ status = "okay";
+};
+
+&pcie1_port {
+ phys = <&pcie1_phy>;
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+};
+
+&pcie1 {
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+ status = "okay";
+};
+
+&pcie2_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_4_cfg>;
+ status = "okay";
+};
+
+&pcie2_port {
+ phys = <&pcie2_phy>;
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+};
+
+&pcie2 {
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb5e3,610";
+ reg = <0x1>;
+ peer-hub = <&hub_3_0>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb5e3,620";
+ reg = <0x2>;
+ peer-hub = <&hub_2_0>;
+ };
+};
--
2.47.3
^ permalink raw reply related
* Re: [PATCH v2 2/6] phy: realtek: usb2: introduce read and write functions to driver data
From: Rustam Adilov @ 2026-03-31 16:26 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel,
Michael Zavertkin
In-Reply-To: <20260330213227.zujvcvsxdfknzltz@skbuf>
On 2026-03-30 21:32, Vladimir Oltean wrote:
> On Tue, Mar 31, 2026 at 12:19:18AM +0300, Vladimir Oltean wrote:
>> On Fri, Mar 27, 2026 at 09:06:34PM +0500, Rustam Adilov wrote:
>> > +static inline u32 phy_read(void __iomem *reg)
>> > +{
>> > + return readl(reg);
>> > +}
>> > +
>> > +static inline u32 phy_read_le(void __iomem *reg)
>> > +{
>> > + return le32_to_cpu(readl(reg));
>> > +}
>> > +
>> > +static inline void phy_write(u32 val, void __iomem *reg)
>> > +{
>> > + writel(val, reg);
>> > +}
>> > +
>> > +static inline void phy_write_le(u32 val, void __iomem *reg)
>> > +{
>> > + writel(cpu_to_le32(val), reg);
>> > +}
>>
>> Please don't name driver-level functions phy_read() and phy_write().
>> That will collide with networking API functions of the same name and
>> will make grep-based code searching more difficult.
>>
>> Also, have you looked at regmap? It has native support for endianness;
>> it supports regmap_field_read()/regmap_field_write() for abstracting
>> registers which may be found at different places for different HW;
>> it offers regmap_read_poll_timeout() so you don't have to pass the
>> function pointer to utmi_wait_register(). It seems the result would be a
>> bit more elegant.
>
> Even if you decide not to use regmap. I thought I should let you know
> that LLM review says:
>
> Are these double byte-swaps intentional?
>
> Since readl() and writel() inherently perform little-endian memory accesses
> and handle byte-swapping on big-endian architectures automatically, won't
> wrapping them in le32_to_cpu() and cpu_to_le32() apply a second, redundant
> byte-swap?
From my experience (and also understanding), readl returns value in native endian
and doesn't do byte swapping. The same goes writel.
Thus wrapping le32_to_cpu() and cpu_to_le32() around them correctly swaps the
bytes from big endian to little endian, without the double byte-swaps.
The comment even mentions it "{read,write}{b,w,l,q}() access little endian memory
and return result in native endianness." which was provided for reference later on.
> On big-endian systems, wouldn't these double swaps cancel each other out
> and result in a native big-endian access instead of the intended
> little-endian access? If the SoC bus bridge implicitly swaps and requires
> a native access, should __raw_readl() and __raw_writel() (or ioread32be /
> iowrite32be) be used instead to avoid obfuscating it with double-swaps?
The __raw_readl() and __raw_writel() are indeed in native endian, and for
RTL9607C SoC it is in big endian.
The way Realtek did it is by using the volatile and wrapping them around
le32_to_cpu() and cpu_to_le32() respectively, which is certainly hacky.
static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
__u32 __iomem *regs)
{
+#if defined(CONFIG_RTK_MIPS_SOC)
+ return (le32_to_cpu((*(volatile unsigned long *)(regs))));
+#else
[...]
static inline void ehci_writel(const struct ehci_hcd *ehci,
const unsigned int val, __u32 __iomem *regs)
{
+#if defined(CONFIG_RTK_MIPS_SOC)
+ ((*(volatile unsigned long *)(regs))=cpu_to_le32(val));
+#else
We did a bit of debugging with usb some time ago and and printed the value
of the readl result from the base usb address and got this
[ 1.327473] ehci_setup:694 ehci caps: 0xb8021000, value: 0x10000001
[ 1.334478] ehci_setup:695 ehci regs: 0xb8021001
[ 1.339706] ehci_halt:187 ehci regs: 0xb8021001
"0x10000001" is supposed to be "0x01000010". Otherwise, it would take 0x01
for the cap length and result in immediate halt from timeout.
Even though it is for linux-usb and not the phy subsystem, it was worth
mentioning as it is very much related to this issue.
What is surprising, the ioread32be and iowrite32be functions actually do
swap bytes, thus resulting in little endian (ironic). But using it here
would be just incorrect as it is intended for accessing big endian mmio,
not for big endian CPU and its little endian USB phy/host.
So, that is a conundrum we have here. Let me know if what you think of it
and maybe even how to better solve it.
Will hold on posting v3 until this hopefully is more or less solved..
> Also, does passing the __le32 restricted type returned by cpu_to_le32()
> into writel() (which expects a native u32) trigger Sparse static analysis
> warnings for an incorrect type in argument?
>
> For reference:
> https://elixir.bootlin.com/linux/v6.19.10/source/include/asm-generic/io.h#L184
> /*
> * {read,write}{b,w,l,q}() access little endian memory and return result in
> * native endianness.
> */
>
> and yes, your patch does trigger sparse warnings:
> ../drivers/phy/realtek/phy-rtk-usb2.c:153:16: warning: cast to restricted __le32
> ../drivers/phy/realtek/phy-rtk-usb2.c:163:16: warning: incorrect type in argument 1 (different base types)
> ../drivers/phy/realtek/phy-rtk-usb2.c:163:16: expected unsigned int val
> ../drivers/phy/realtek/phy-rtk-usb2.c:163:16: got restricted __le32 [usertype]
I can alleviate it by creating a temp u32 variable to hold the cpu_to_le32() and then
using that temp variable for writel.
> Furthermore, please drop the 'inline' keyword from C files and let the
> compiler decide. Your use of this keyword has no value - you declare
> phy_read(), phy_read_le() etc as inline but then assign function
> pointers to them. How can the compiler inline the indirect calls?
Will drop these.
^ permalink raw reply
* Re: [PATCH v9 0/6] Add USB2.0 VBUS mux driver and extend rzv2h-usb2phy reset for RZ/G3E support
From: Ulf Hansson @ 2026-03-31 16:16 UTC (permalink / raw)
To: Tommaso Merciai
Cc: tomm.merciai, peda, p.zabel, linux-renesas-soc, biju.das.jz,
Fabrizio Castro, Lad Prabhakar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman,
Josua Mayer, devicetree, linux-kernel
In-Reply-To: <cover.1774601289.git.tommaso.merciai.xr@bp.renesas.com>
On Fri, 27 Mar 2026 at 19:09, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
>
> Dear All,
>
> The series adds:
> - A new mux driver for RZ/V2H USB VBENCTL VBUS_SEL
> - Updates to the rzv2h-usb2phy reset driver/bindings to support RZ/G3E.
>
> Merge strategy, if any:
>
> - patches 1/6 can go through the MUX tree
I have quite some MUX changes queued via my mmc tree for v7.1-rc1.
I can pick patch1/6 as well, if this makes sense for everybody. Peter?
> - patches 2-6/6 can go through the Reset tree
>
> Thanks & Regards,
> Tommaso
>
[...]
Kind regards
Uffe
^ permalink raw reply
* Re: [PATCH v5 0/2] Add support for Texas Instruments INA4230 power monitor
From: Guenter Roeck @ 2026-03-31 16:10 UTC (permalink / raw)
To: Rob Herring, Alexey Charkov
Cc: Krzysztof Kozlowski, Conor Dooley, linux-hwmon, devicetree,
linux-kernel, Krzysztof Kozlowski
In-Reply-To: <20260331155246.GA1299761-robh@kernel.org>
On 3/31/26 08:52, Rob Herring wrote:
> On Mon, Mar 30, 2026 at 09:07:32AM -0700, Guenter Roeck wrote:
>> On 3/30/26 08:14, Alexey Charkov wrote:
>>> TI INA4230 is a 4-channel power monitor with I2C interface, similar in
>>> operation to INA3221 (3-channel) and INA219 (single-channel) but with
>>> a different register layout, different alerting mechanism and slightly
>>> different support for directly reading calculated current/power/energy
>>> values (pre-multiplied by the device itself and needing only to be scaled
>>> by the driver depending on its selected LSB unit values).
>>>
>>> In this initial implementation, the driver supports reading voltage,
>>> current, power and energy values, but does not yet support alerts, which
>>> can be added separately if needed. Also the overflows during hardware
>>> calculations are not yet handled, nor is the support for the device's
>>> internal 32-bit energy counter reset.
>>>
>>> An example device tree using this binding and driver is available at [1]
>>> (not currently upstreamed, as the device in question is in engineering
>>> phase and not yet publicly available)
>>>
>>> [1] https://github.com/flipperdevices/flipper-linux-kernel/blob/flipper-devel/arch/arm64/boot/dts/rockchip/rk3576-flipper-one-rev-f0b0c1.dts
>>>
>>> Signed-off-by: Alexey Charkov <alchark@flipper.net>
>>> ---
>>> Changes in v5:
>>> - Reworded per-channel subnodes description in the binding for clarity (Sashiko)
>>> - NB: Sashiko's suggestion to allow interrupts in the binding sounds premature,
>>> as the alerts mechanism is not implemented yet and there are no known users
>>> to test it. If anyone has hardware with the alert pins wired to an interrupt
>>> line - please shout and we can test/extend it together
>>
>> The bindings are supposed to be complete, even if not implemented, so I am not sure
>> if the DT maintainers will agree here. We'll see.
>
> Given ti,alert-polarity-active-high is added seems like the interrupt
> should be too. And the interrupt can specify the polarity, so is that
> property really needed? There's alway the possibility that you have some
> inverter on the board too and the interrupt polarity is not enough, but
> solve that problem when it actually exists.
>
The alert pin can be attached to a board interrupt, or (more likely) it can
be attached to the I2C controller's alert pin. In the latter case there is
no interrupt property.
Guenter
^ permalink raw reply
* Re: [PATCH v4 2/4] irqchip/ast2700-intc: Add AST2700-A2 support
From: Thomas Gleixner @ 2026-03-31 16:10 UTC (permalink / raw)
To: Ryan Chen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-aspeed,
linux-riscv, Ryan Chen
In-Reply-To: <20260330-irqchip-v4-2-3c0f1620cc06@aspeedtech.com>
On Mon, Mar 30 2026 at 14:32, Ryan Chen wrote:
> +static int resolve_parent_range_for_output(const struct aspeed_intc0 *intc0,
> + const struct fwnode_handle *parent,
> + u32 output,
> + struct aspeed_intc_interrupt_range *resolved)
Please reduce the number of line breaks. You still have 100 characters.
> +{
> + for (size_t i = 0; i < intc0->ranges.nranges; i++) {
> + struct aspeed_intc_interrupt_range range =
> + intc0->ranges.ranges[i];
No line break required.
> +static int aspeed_intc1_irq_domain_activate(struct irq_domain *domain,
> + struct irq_data *data, bool reserve)
> +{
> + struct aspeed_intc1 *intc1 = irq_data_get_irq_chip_data(data);
> + struct aspeed_intc_interrupt_range resolved;
> + int rc, bank, bit;
> + u32 mask;
> +
> + if (WARN_ON_ONCE((data->hwirq >> INTC1_ROUTE_SHIFT) >= ARRAY_SIZE(aspeed_intc1_routes)))
> + return -EINVAL;
> +
> + /*
> + * outpin may be an error if the upstream is the BootMCU APLIC node, or
> + * anything except a valid intc0 driver instance
> + */
> + rc = aspeed_intc0_resolve_route(intc1->upstream, INTC1_ROUTE_NUM,
> + aspeed_intc1_routes[data->hwirq >> INTC1_ROUTE_SHIFT],
> + intc1->ranges.nranges,
> + intc1->ranges.ranges, &resolved);
Please test your code with CONFIG_PROVE_LOCKING=y, which is mandatory
for submission according to documentation.
This is invoked with the interrupt descriptor lock held and interrupts
disabled.
aspeed_intc0_resolve_route()
....
irq_find_matching_fwspec()
mutex_lock(&irq_domain_mutex); <---- FAIL
Thanks,
tglx
^ permalink raw reply
* Re: [PATCH v4 2/3] ath10k: Add device-tree quirk to skip host cap QMI requests
From: Vasanthakumar Thiagarajan @ 2026-03-31 16:06 UTC (permalink / raw)
To: david, Johannes Berg, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jeff Johnson, Bjorn Andersson, Konrad Dybcio,
Paul Sajna
Cc: Amit Pundir, linux-wireless, devicetree, ath10k, linux-kernel,
linux-arm-msm, phone-devel
In-Reply-To: <20260325-skip-host-cam-qmi-req-v4-2-bc08538487aa@ixit.cz>
On 3/25/2026 11:27 PM, David Heidelberg via B4 Relay wrote:
> From: Amit Pundir <amit.pundir@linaro.org>
>
> Some firmware versions do not support the host capability QMI request.
> Since this request occurs before firmware-N.bin and board-M.bin are
> loaded, the quirk cannot be expressed in the firmware itself.
>
> The root cause is unclear, but there appears to be a generation of
> firmware that lacks host capability support.
>
> Without this quirk, ath10k_qmi_host_cap_send_sync() returns
> QMI_ERR_MALFORMED_MSG_V01 before loading the firmware. This error is not
> fatal - Wi-Fi services still come up successfully if the request is simply
> skipped.
>
> Add a device-tree quirk to skip the host capability QMI request on devices
> whose firmware does not support it.
>
> For example, firmware build
> "QC_IMAGE_VERSION_STRING=WLAN.HL.2.0.c3-00257-QCAHLSWMTPLZ-1"
> on Xiaomi Poco F1 phone requires this quirk.
>
> Suggested-by: Bjorn Andersson <andersson@kernel.org>
> Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
> Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v4 5/9] mfd: mt6397: Add support for MT6392 PMIC
From: kernel test robot @ 2026-03-31 16:01 UTC (permalink / raw)
To: Luca Leonardo Scorcia, linux-mediatek
Cc: llvm, oe-kbuild-all, Fabien Parent, Val Packett,
Luca Leonardo Scorcia, AngeloGioacchino Del Regno,
Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Sen Chu, Sean Wang, Macpaul Lin, Lee Jones, Matthias Brugger,
Linus Walleij, Liam Girdwood, Mark Brown, Gary Bisson,
Julien Massot, Louis-Alexis Eyraud, Chen Zhong, linux-input,
devicetree, linux-kernel, linux-pm, linux-arm-kernel, linux-gpio
In-Reply-To: <20260330083429.359819-6-l.scorcia@gmail.com>
Hi Luca,
kernel test robot noticed the following build warnings:
[auto build test WARNING on lee-mfd/for-mfd-next]
[also build test WARNING on broonie-regulator/for-next linusw-pinctrl/devel linusw-pinctrl/for-next lee-mfd/for-mfd-fixes linus/master v7.0-rc6 next-20260330]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Luca-Leonardo-Scorcia/dt-bindings-mfd-mt6397-Add-MT6392-PMIC/20260331-081127
base: https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git for-mfd-next
patch link: https://lore.kernel.org/r/20260330083429.359819-6-l.scorcia%40gmail.com
patch subject: [PATCH v4 5/9] mfd: mt6397: Add support for MT6392 PMIC
config: s390-randconfig-002-20260331 (https://download.01.org/0day-ci/archive/20260331/202603312339.CMJpqhEq-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260331/202603312339.CMJpqhEq-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603312339.CMJpqhEq-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/mfd/mt6397-core.c:421:16: warning: cast to smaller integer type 'enum mfd_match_data' from 'const void *' [-Wvoid-pointer-to-enum-cast]
421 | device_data = (enum mfd_match_data)of_device_get_match_data(&pdev->dev);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +421 drivers/mfd/mt6397-core.c
398
399 static int mt6397_probe(struct platform_device *pdev)
400 {
401 int ret;
402 unsigned int id = 0;
403 struct mt6397_chip *pmic;
404 const struct chip_data *pmic_core;
405 enum mfd_match_data device_data;
406
407 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
408 if (!pmic)
409 return -ENOMEM;
410
411 pmic->dev = &pdev->dev;
412
413 /*
414 * mt6397 MFD is child device of soc pmic wrapper.
415 * Regmap is set from its parent.
416 */
417 pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
418 if (!pmic->regmap)
419 return -ENODEV;
420
> 421 device_data = (enum mfd_match_data)of_device_get_match_data(&pdev->dev);
422 switch (device_data) {
423 case MATCH_DATA_MT6323:
424 pmic_core = &mt6323_core;
425 break;
426 case MATCH_DATA_MT6328:
427 pmic_core = &mt6328_core;
428 break;
429 case MATCH_DATA_MT6331:
430 pmic_core = &mt6331_mt6332_core;
431 break;
432 case MATCH_DATA_MT6357:
433 pmic_core = &mt6357_core;
434 break;
435 case MATCH_DATA_MT6358:
436 pmic_core = &mt6358_core;
437 break;
438 case MATCH_DATA_MT6359:
439 pmic_core = &mt6359_core;
440 break;
441 case MATCH_DATA_MT6392:
442 pmic_core = &mt6392_core;
443 break;
444 case MATCH_DATA_MT6397:
445 pmic_core = &mt6397_core;
446 break;
447 default:
448 dev_err(&pdev->dev, "Unknown device match data %u\n", device_data);
449 return -ENODEV;
450 }
451
452 ret = regmap_read(pmic->regmap, pmic_core->cid_addr, &id);
453 if (ret) {
454 dev_err(&pdev->dev, "Failed to read chip id: %d\n", ret);
455 return ret;
456 }
457
458 pmic->chip_id = (id >> pmic_core->cid_shift) & 0xff;
459
460 platform_set_drvdata(pdev, pmic);
461
462 pmic->irq = platform_get_irq(pdev, 0);
463 if (pmic->irq <= 0)
464 return pmic->irq;
465
466 ret = pmic_core->irq_init(pmic);
467 if (ret)
468 return ret;
469
470 ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
471 pmic_core->cells, pmic_core->cell_size,
472 NULL, 0, pmic->irq_domain);
473 if (ret) {
474 irq_domain_remove(pmic->irq_domain);
475 dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
476 }
477
478 return ret;
479 }
480
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v5 0/2] Add support for Texas Instruments INA4230 power monitor
From: Rob Herring @ 2026-03-31 15:52 UTC (permalink / raw)
To: Guenter Roeck, Alexey Charkov
Cc: Krzysztof Kozlowski, Conor Dooley, linux-hwmon, devicetree,
linux-kernel, Krzysztof Kozlowski
In-Reply-To: <67a5d1c1-a9c5-47fb-a0ec-5b69a991b01e@roeck-us.net>
On Mon, Mar 30, 2026 at 09:07:32AM -0700, Guenter Roeck wrote:
> On 3/30/26 08:14, Alexey Charkov wrote:
> > TI INA4230 is a 4-channel power monitor with I2C interface, similar in
> > operation to INA3221 (3-channel) and INA219 (single-channel) but with
> > a different register layout, different alerting mechanism and slightly
> > different support for directly reading calculated current/power/energy
> > values (pre-multiplied by the device itself and needing only to be scaled
> > by the driver depending on its selected LSB unit values).
> >
> > In this initial implementation, the driver supports reading voltage,
> > current, power and energy values, but does not yet support alerts, which
> > can be added separately if needed. Also the overflows during hardware
> > calculations are not yet handled, nor is the support for the device's
> > internal 32-bit energy counter reset.
> >
> > An example device tree using this binding and driver is available at [1]
> > (not currently upstreamed, as the device in question is in engineering
> > phase and not yet publicly available)
> >
> > [1] https://github.com/flipperdevices/flipper-linux-kernel/blob/flipper-devel/arch/arm64/boot/dts/rockchip/rk3576-flipper-one-rev-f0b0c1.dts
> >
> > Signed-off-by: Alexey Charkov <alchark@flipper.net>
> > ---
> > Changes in v5:
> > - Reworded per-channel subnodes description in the binding for clarity (Sashiko)
> > - NB: Sashiko's suggestion to allow interrupts in the binding sounds premature,
> > as the alerts mechanism is not implemented yet and there are no known users
> > to test it. If anyone has hardware with the alert pins wired to an interrupt
> > line - please shout and we can test/extend it together
>
> The bindings are supposed to be complete, even if not implemented, so I am not sure
> if the DT maintainers will agree here. We'll see.
Given ti,alert-polarity-active-high is added seems like the interrupt
should be too. And the interrupt can specify the polarity, so is that
property really needed? There's alway the possibility that you have some
inverter on the board too and the interrupt polarity is not enough, but
solve that problem when it actually exists.
Rob
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: connector: add pd-disable dependency
From: Rob Herring (Arm) @ 2026-03-31 15:46 UTC (permalink / raw)
To: Xu Yang
Cc: amitsd, kyletso, krzk+dt, badhri, conor+dt, imx, linux-usb,
linux-kernel, devicetree, gregkh
In-Reply-To: <20260330063518.719345-1-xu.yang_2@nxp.com>
On Mon, 30 Mar 2026 14:35:18 +0800, Xu Yang wrote:
> When Power Delivery is not supported, the source is unable to obtain the
> current capability from the Source PDO. As a result, typec-power-opmode
> needs to be added to advertise such capability.
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Fixes: 7a4440bc0d86 ("dt-bindings: connector: Add pd-disable property")
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
>
> ---
> Changes in v2:
> - add acked by tag
> - DTS patch has been picked by Frank
> ---
> Documentation/devicetree/bindings/connector/usb-connector.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH v2 2/6] phy: realtek: usb2: introduce read and write functions to driver data
From: Rustam Adilov @ 2026-03-31 15:45 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel,
Michael Zavertkin
In-Reply-To: <20260330211918.y7su36j47e3uelcv@skbuf>
Hello,
On 2026-03-30 21:19, Vladimir Oltean wrote:
> On Fri, Mar 27, 2026 at 09:06:34PM +0500, Rustam Adilov wrote:
>> +static inline u32 phy_read(void __iomem *reg)
>> +{
>> + return readl(reg);
>> +}
>> +
>> +static inline u32 phy_read_le(void __iomem *reg)
>> +{
>> + return le32_to_cpu(readl(reg));
>> +}
>> +
>> +static inline void phy_write(u32 val, void __iomem *reg)
>> +{
>> + writel(val, reg);
>> +}
>> +
>> +static inline void phy_write_le(u32 val, void __iomem *reg)
>> +{
>> + writel(cpu_to_le32(val), reg);
>> +}
>
> Please don't name driver-level functions phy_read() and phy_write().
> That will collide with networking API functions of the same name and
> will make grep-based code searching more difficult.
I can change it to something like "rtk_phy_read" or "usb2phy_read" then.
> Also, have you looked at regmap? It has native support for endianness;
> it supports regmap_field_read()/regmap_field_write() for abstracting
> registers which may be found at different places for different HW;
> it offers regmap_read_poll_timeout() so you don't have to pass the
> function pointer to utmi_wait_register(). It seems the result would be a
> bit more elegant.
In fact, I did not because it would involve in way more refactoring for patch
series that is supposed to simply add RTL9607C support. And unfortunately,
the regmap is not going to the solve the issue, which i will explain in the
later email to your LLM review on readl/writel.
^ permalink raw reply
* Re: [PATCH 3/8] mfd: omap-usb-host: Cleanup header includes
From: Lee Jones @ 2026-03-31 15:45 UTC (permalink / raw)
To: Thomas Richard
Cc: Aaro Koskinen, Andreas Kemnade, Kevin Hilman, Roger Quadros,
Tony Lindgren, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thomas Petazzoni, linux-omap,
linux-kernel, devicetree
In-Reply-To: <20260323-omap4-fix-usb-support-v1-3-b668132124ac@bootlin.com>
On Mon, 23 Mar 2026, Thomas Richard wrote:
> Remove unused includes (linux/kernel.h, linux/types.h and linux/delay.h).
> Sort the remaining ones alphabetically.
What about 'linux/slab.h'?
> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
> ---
> drivers/mfd/omap-usb-host.c | 10 +++-------
> 1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
> index 4d29a6e2ed87abf2a0f6d5a704525baaa6f0cbcb..4e066a17cef0400edbfcb3012a16ceee06e52140 100644
> --- a/drivers/mfd/omap-usb-host.c
> +++ b/drivers/mfd/omap-usb-host.c
> @@ -6,19 +6,15 @@
> * Author: Keshava Munegowda <keshava_mgowda@ti.com>
> * Author: Roger Quadros <rogerq@ti.com>
> */
> -#include <linux/kernel.h>
> -#include <linux/module.h>
> -#include <linux/types.h>
> -#include <linux/slab.h>
> -#include <linux/delay.h>
> #include <linux/clk.h>
> #include <linux/dma-mapping.h>
> -#include <linux/platform_device.h>
> +#include <linux/err.h>
> +#include <linux/module.h>
> #include <linux/platform_data/usb-omap.h>
> +#include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/of.h>
> #include <linux/of_platform.h>
This is still not alphabetical.
--
Lee Jones [李琼斯]
^ permalink raw reply
* Re: [PATCH v8 2/3] dt-bindings: iio: adc: ad4080: add AD4880 support
From: Rob Herring @ 2026-03-31 15:44 UTC (permalink / raw)
To: Antoniu Miclaus
Cc: Lars-Peter Clausen, Michael Hennerich, Jonathan Cameron,
David Lechner, Nuno Sá, Krzysztof Kozlowski, Conor Dooley,
Olivier Moysan, linux-iio, devicetree, linux-kernel
In-Reply-To: <20260328114050.46848-3-antoniu.miclaus@analog.com>
On Sat, Mar 28, 2026 at 01:40:49PM +0200, Antoniu Miclaus wrote:
> Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC
> with integrated fully differential amplifiers (FDA).
>
> The AD4880 has two independent ADC channels, each with its own SPI
> configuration interface. This requires:
> - Two entries in reg property for primary and secondary channel
> chip selects
> - Two io-backends entries for the two data channels
>
> Reviewed-by: David Lechner <dlechner@baylibre.com>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
> Changes in v8:
> - No changes
Missing Conor's ack.
^ permalink raw reply
* Re: [PATCH ath-next v3 1/6] dt-bindings: net: wireless: add ath12k wifi device IPQ5424
From: Jeff Johnson @ 2026-03-31 15:44 UTC (permalink / raw)
To: Krzysztof Kozlowski, Raj Kumar Bhagat
Cc: Johannes Berg, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jeff Johnson, linux-wireless, devicetree, linux-kernel, ath12k
In-Reply-To: <0de0574a-04ce-45d0-946d-5fdc1a7b8181@kernel.org>
On 3/31/2026 7:42 AM, Krzysztof Kozlowski wrote:
> On 31/03/2026 16:23, Jeff Johnson wrote:
>> On 3/31/2026 12:24 AM, Krzysztof Kozlowski wrote:
>>> On Tue, Mar 31, 2026 at 02:09:06AM +0530, Raj Kumar Bhagat wrote:
>>>> $id: http://devicetree.org/schemas/net/wireless/qcom,ipq5332-wifi.yaml#
>>>> @@ -17,6 +17,7 @@ properties:
>>>> compatible:
>>>> enum:
>>>> - qcom,ipq5332-wifi
>>>> + - qcom,ipq5424-wifi
>>>
>>> No, use previous patch.
>>>
>>> I am annoyed that you keep making changes even for such trivialities and
>>> require re-review from the community. Previous patch was correct. This
>>> one doing whatever you want to do in copyrights is too much. You don't
>>> change copyrights just because you wrote one device model.
>>
>> Krzysztof,
>>
>> FYI here is the guidance I received from Qualcomm legal (links to internal
>> documentation, removed -- I've forwarded the entire e-mail to your Qualcomm
>> mailbox):
>
> As I explained already more than once, legal can engage in open source
> discussions directly. I am not going to discuss with them via proxies.
>
>>
>> ... Repos under copyleft license [...] QTI copyright must be added when we
>> make significant changes.
>>
>> ... Repos under friendly license (BSD, Apache, MIT, ...) [...] QTI copyright
>> must be added for any changes, not just significant ones.
>>
>> ... under the regular QUIC to QTI open-source copyright transitioning [...]
>> all QUIC Copyright instances should be replaced with year-less QTI OSS Copyright.
>>
>> I'll follow up with them on this case where there is a dual-license file.
>
> You nicely removed the quote where they ask to follow what the upstream
> maintainer asks for. So as one of the maintainers I ask not to change
> it, because it is churn and pointless waste of my time.
Although I feel the latest patch correctly represents Qualcomm legal guidance,
I'm not going to insist upon the copyright change.
/jeff
^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: display: waveshare,dsp2dpi: describe DSI2LVDS setup
From: Dmitry Baryshkov @ 2026-03-31 15:44 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Neil Armstrong, Jessica Zhang, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thierry Reding, Sam Ravnborg,
Joseph Guo, Marek Vasut, Andrzej Hajda, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, dri-devel,
devicetree, linux-kernel
In-Reply-To: <20260331-roaring-carrot-stork-edaef8@quoll>
On Tue, Mar 31, 2026 at 10:40:12AM +0200, Krzysztof Kozlowski wrote:
> On Mon, Mar 30, 2026 at 04:25:50PM +0300, Dmitry Baryshkov wrote:
> > Several the Waveshare DSI LCD panel kits use DSI2LVDS ICN6202 bridge
>
> If you know the hardware bridge used, should not it be the front
> compatible (with waveshare,dsi2lvds fallback)? Or even alone? Can the
> waveshare kits come with different bridges? I guess yes, they could.
After additional thought (and an email to Marek): the actual ICN bridge
chip is an integrated entity. It is not (and it should not) be
programmed by the host. The kit handles it internally. As such, I don't
think we should be a part of the DT.
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH v2 4/4] drm/panel: simple: add Waveshare LCD panels
From: Dmitry Baryshkov @ 2026-03-31 15:44 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thierry Reding, Sam Ravnborg,
Joseph Guo, Marek Vasut, Andrzej Hajda, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec
Cc: dri-devel, devicetree, linux-kernel
In-Reply-To: <20260331-ws-lcd-v2-0-a1add63b6eb6@oss.qualcomm.com>
Waveshare have a serie of DSI panel kits with the DPI or LVDS panel
being attached to the DSI2DPI or DSI2LVDS bridge. The commit
46be11b678e0 ("drm/panel: simple: Add Waveshare 13.3" panel support")
added definitions for one of those panels, describe the rest of them.
Note, since the panels are hidden behind the bridges which are not being
programmed by the kernel, I could not confirm the pixel format for the
panels.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-simple.c | 381 +++++++++++++++++++++++++++++++++++
1 file changed, 381 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 236bd56208cc..b2708a1fe464 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -5061,6 +5061,342 @@ static const struct panel_desc vl050_8048nt_c01 = {
.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
};
+static const struct drm_display_mode waveshare_28_lcd_mode = {
+ .clock = 50000,
+ .hdisplay = 480,
+ .hsync_start = 480 + 150,
+ .hsync_end = 480 + 150 + 50,
+ .htotal = 480 + 150 + 50 + 150,
+ .vdisplay = 640,
+ .vsync_start = 640 + 150,
+ .vsync_end = 640 + 150 + 50,
+ .vtotal = 640 + 150 + 50 + 150,
+ .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
+};
+
+static const struct panel_desc waveshare_28_lcd_panel = {
+ .modes = &waveshare_28_lcd_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 44,
+ .height = 58,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+ .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
+ DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE,
+};
+
+static const struct drm_display_mode waveshare_34_lcd_c_mode = {
+ .clock = 50000,
+ .hdisplay = 800,
+ .hsync_start = 800 + 32,
+ .hsync_end = 800 + 32 + 6,
+ .htotal = 800 + 32 + 6 + 120,
+ .vdisplay = 800,
+ .vsync_start = 800 + 8,
+ .vsync_end = 800 + 8 + 4,
+ .vtotal = 800 + 8 + 4 + 16,
+};
+
+static const struct panel_desc waveshare_34_lcd_c_panel = {
+ .modes = &waveshare_34_lcd_c_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 88,
+ .height = 88,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
+static const struct drm_display_mode waveshare_40_lcd_mode = {
+ .clock = 50000,
+ .hdisplay = 480,
+ .hsync_start = 480 + 150,
+ .hsync_end = 480 + 150 + 100,
+ .htotal = 480 + 150 + 100 + 150,
+ .vdisplay = 800,
+ .vsync_start = 800 + 20,
+ .vsync_end = 800 + 20 + 100,
+ .vtotal = 800 + 20 + 100 + 20,
+ .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
+};
+
+static const struct panel_desc waveshare_40_lcd_panel = {
+ .modes = &waveshare_40_lcd_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 52,
+ .height = 87,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+ .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
+ DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE,
+};
+
+static const struct drm_display_mode waveshare_40_lcd_c_mode = {
+ .clock = 50000,
+ .hdisplay = 720,
+ .hsync_start = 720 + 32,
+ .hsync_end = 720 + 32 + 200,
+ .htotal = 720 + 32 + 200 + 120,
+ .vdisplay = 720,
+ .vsync_start = 720 + 8,
+ .vsync_end = 720 + 8 + 4,
+ .vtotal = 720 + 8 + 4 + 16,
+};
+
+static const struct panel_desc waveshare_40_lcd_c_panel = {
+ .modes = &waveshare_40_lcd_c_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 102,
+ .height = 102,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
+static const struct drm_display_mode waveshare_50_lcd_c_mode = {
+ .clock = 50000,
+ .hdisplay = 1024,
+ .hsync_start = 1024 + 100,
+ .hsync_end = 1024 + 100 + 100,
+ .htotal = 1024 + 100 + 100 + 100,
+ .vdisplay = 600,
+ .vsync_start = 600 + 10,
+ .vsync_end = 600 + 10 + 10,
+ .vtotal = 600 + 10 + 10 + 10,
+ .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
+};
+
+static const struct panel_desc waveshare_50_lcd_c_panel = {
+ .modes = &waveshare_50_lcd_c_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 109,
+ .height = 66,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+ .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
+ DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE,
+};
+
+static const struct drm_display_mode waveshare_50_lcd_d_mode = {
+ .clock = 83333,
+ .hdisplay = 720,
+ .hsync_start = 720 + 100,
+ .hsync_end = 720 + 100 + 80,
+ .htotal = 720 + 100 + 80 + 100,
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 20,
+ .vsync_end = 1280 + 20 + 20,
+ .vtotal = 1280 + 20 + 20 + 20,
+};
+
+static const struct panel_desc waveshare_50_lcd_d_panel = {
+ .modes = &waveshare_50_lcd_d_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 62,
+ .height = 110,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
+static const struct drm_display_mode waveshare_625_lcd_mode = {
+ .clock = 83333,
+ .hdisplay = 720,
+ .hsync_start = 720 + 50,
+ .hsync_end = 720 + 50 + 50,
+ .htotal = 720 + 50 + 50 + 50,
+ .vdisplay = 1560,
+ .vsync_start = 1560 + 20,
+ .vsync_end = 1560 + 20 + 20,
+ .vtotal = 1560 + 20 + 20 + 20,
+};
+
+static const struct panel_desc waveshare_625_lcd_panel = {
+ .modes = &waveshare_625_lcd_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 66,
+ .height = 144,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
+static const struct panel_desc waveshare_70_lcd_c_panel = {
+ .modes = &waveshare_50_lcd_c_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 155,
+ .height = 87,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+ .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
+ DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE,
+};
+
+static const struct drm_display_mode waveshare_80_lcd_c_mode;
+static const struct panel_desc waveshare_70_lcd_e_panel = {
+ .modes = &waveshare_80_lcd_c_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 152,
+ .height = 95,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
+static const struct drm_display_mode waveshare_70_lcd_h_mode = {
+ .clock = 83333,
+ .hdisplay = 1280,
+ .hsync_start = 1280 + 64,
+ .hsync_end = 1280 + 64 + 64,
+ .htotal = 1280 + 64 + 64 + 64,
+ .vdisplay = 720,
+ .vsync_start = 720 + 64,
+ .vsync_end = 720 + 64 + 64,
+ .vtotal = 720 + 64 + 64 + 64,
+};
+
+static const struct panel_desc waveshare_70_lcd_h_panel = {
+ .modes = &waveshare_70_lcd_h_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 155,
+ .height = 88,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
+static const struct drm_display_mode waveshare_79_lcd_mode = {
+ .clock = 50000,
+ .hdisplay = 400,
+ .hsync_start = 400 + 40,
+ .hsync_end = 400 + 40 + 30,
+ .htotal = 400 + 40 + 30 + 40,
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 20,
+ .vsync_end = 1280 + 20 + 10,
+ .vtotal = 1280 + 20 + 10 + 20,
+};
+
+static const struct panel_desc waveshare_79_lcd_panel = {
+ .modes = &waveshare_79_lcd_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 60,
+ .height = 191,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
+static const struct drm_display_mode waveshare_80_lcd_c_mode = {
+ .clock = 83333,
+ .hdisplay = 1280,
+ .hsync_start = 1280 + 156,
+ .hsync_end = 1280 + 156 + 20,
+ .htotal = 1280 + 156 + 20 + 40,
+ .vdisplay = 800,
+ .vsync_start = 800 + 40,
+ .vsync_end = 800 + 40 + 48,
+ .vtotal = 800 + 40 + 48 + 40,
+};
+
+static const struct panel_desc waveshare_80_lcd_c_panel = {
+ .modes = &waveshare_80_lcd_c_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 173,
+ .height = 108,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
+static const struct drm_display_mode waveshare_88_lcd_mode = {
+ .clock = 83333,
+ .hdisplay = 480,
+ .hsync_start = 480 + 50,
+ .hsync_end = 480 + 50 + 50,
+ .htotal = 480 + 50 + 50 + 50,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 20,
+ .vsync_end = 1920 + 20 + 20,
+ .vtotal = 1920 + 20 + 20 + 20,
+};
+
+static const struct panel_desc waveshare_88_lcd_panel = {
+ .modes = &waveshare_88_lcd_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 56,
+ .height = 220,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
+static const struct panel_desc waveshare_101_lcd_c_panel = {
+ .modes = &waveshare_80_lcd_c_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 217,
+ .height = 136,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
+static const struct drm_display_mode waveshare_119_lcd_mode = {
+ .clock = 50000,
+ .hdisplay = 320,
+ .hsync_start = 320 + 60,
+ .hsync_end = 320 + 60 + 60,
+ .htotal = 320 + 60 + 60 + 60,
+ .vdisplay = 1480,
+ .vsync_start = 1480 + 60,
+ .vsync_end = 1480 + 60 + 60,
+ .vtotal = 1480 + 60 + 60 + 60,
+};
+
+static const struct panel_desc waveshare_119_lcd_panel = {
+ .modes = &waveshare_119_lcd_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 58,
+ .height = 268,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
static const struct drm_display_mode waveshare_133inch_mode = {
.clock = 148500,
.hdisplay = 1920,
@@ -5697,6 +6033,51 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "vxt,vl050-8048nt-c01",
.data = &vl050_8048nt_c01,
+ }, {
+ .compatible = "waveshare,2.8inch-panel",
+ .data = &waveshare_28_lcd_panel
+ }, {
+ .compatible = "waveshare,3.4inch-c-panel",
+ .data = &waveshare_34_lcd_c_panel
+ }, {
+ .compatible = "waveshare,4.0inch-panel",
+ .data = &waveshare_40_lcd_panel
+ }, {
+ .compatible = "waveshare,4.0inch-c-panel",
+ .data = &waveshare_40_lcd_c_panel
+ }, {
+ .compatible = "waveshare,5.0inch-c-panel",
+ .data = &waveshare_50_lcd_c_panel
+ }, {
+ .compatible = "waveshare,5.0inch-d-panel",
+ .data = &waveshare_50_lcd_d_panel
+ }, {
+ .compatible = "waveshare,6.25inch-panel",
+ .data = &waveshare_625_lcd_panel
+ }, {
+ .compatible = "waveshare,7.0inch-c-panel",
+ .data = &waveshare_70_lcd_c_panel
+ }, {
+ .compatible = "waveshare,7.0inch-e-panel",
+ .data = &waveshare_70_lcd_e_panel
+ }, {
+ .compatible = "waveshare,7.0inch-h-panel",
+ .data = &waveshare_70_lcd_h_panel
+ }, {
+ .compatible = "waveshare,7.9inch-panel",
+ .data = &waveshare_79_lcd_panel
+ }, {
+ .compatible = "waveshare,8.0inch-c-panel",
+ .data = &waveshare_80_lcd_c_panel
+ }, {
+ .compatible = "waveshare,8.8inch-panel",
+ .data = &waveshare_88_lcd_panel
+ }, {
+ .compatible = "waveshare,10.1inch-c-panel",
+ .data = &waveshare_101_lcd_c_panel
+ }, {
+ .compatible = "waveshare,11.9inch-panel",
+ .data = &waveshare_119_lcd_panel
}, {
.compatible = "waveshare,13.3inch-panel",
.data = &waveshare_133inch,
--
2.47.3
^ permalink raw reply related
* [PATCH v2 3/4] dt-bindings: display: panel: add Waveshare LCD panels
From: Dmitry Baryshkov @ 2026-03-31 15:44 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thierry Reding, Sam Ravnborg,
Joseph Guo, Marek Vasut, Andrzej Hajda, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec
Cc: dri-devel, devicetree, linux-kernel, Krzysztof Kozlowski
In-Reply-To: <20260331-ws-lcd-v2-0-a1add63b6eb6@oss.qualcomm.com>
Waveshare has a family of LVDS / DPI panels bundled with the DSI2DPI or
DSI2LVDS bridge. The bridge and the rest of the logic are covered by the
waveshare,dsi2dpi compatible. The bindings already include several
entries for the panels from this series (waveshare,13.3inch-panel,
waveshare,7.0inch-c-panel). Define compatible strings for the rest of
the panels from that series.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../bindings/display/panel/panel-simple.yaml | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
index 9b8fa03f7cbc..c9ac59e04118 100644
--- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
+++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
@@ -343,10 +343,38 @@ properties:
- vivax,tpc9150-panel
# VXT 800x480 color TFT LCD panel
- vxt,vl050-8048nt-c01
+ # Waveshare 10.1" WXGA (1280x800) LCD panel
+ - waveshare,10.1inch-c-panel
+ # Waveshare 11.9" (320x1480) LCD panel
+ - waveshare,11.9inch-panel
# Waveshare 13.3" FHD (1920x1080) LCD panel
- waveshare,13.3inch-panel
+ # Waveshare 2.8" VGA (480x640) LCD panel
+ - waveshare,2.8inch-panel
+ # Waveshare 3.4" (800x800) LCD panel
+ - waveshare,3.4inch-c-panel
+ # Waveshare 4.0" WVGA (480x800) LCD panel
+ - waveshare,4.0inch-panel
+ # Waveshare 4.0" (720x720) LCD panel
+ - waveshare,4.0inch-c-panel
+ # Waveshare 5.0" WSVGA (1024x600) LCD panel
+ - waveshare,5.0inch-c-panel
+ # Waveshare 5.0" HD 720p (720x1280) LCD panel
+ - waveshare,5.0inch-d-panel
+ # Waveshare 6.25" (720x1560) LCD panel
+ - waveshare,6.25inch-panel
# Waveshare 7.0" WSVGA (1024x600) LCD panel
- waveshare,7.0inch-c-panel
+ # Waveshare 7.0" WXGA (1280x800) LCD panel
+ - waveshare,7.0inch-e-panel
+ # Waveshare 7.0" HD 720p (720x1280) LCD panel
+ - waveshare,7.0inch-h-panel
+ # Waveshare 7.9" (400x1280) LCD panel
+ - waveshare,7.9inch-panel
+ # Waveshare 8.0" WXGA (1280x800) LCD panel
+ - waveshare,8.0inch-c-panel
+ # Waveshare 8.8" (480x1920) LCD panel
+ - waveshare,8.8inch-panel
# Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel
- winstar,wf35ltiacd
# Yes Optoelectronics YTC700TLAG-05-201C 7" TFT LCD panel
--
2.47.3
^ permalink raw reply related
* [PATCH v6 11/11] power: supply: bq257xx: Add support for BQ25792
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
Add support for TI BQ25792 integrated battery charger and buck-boost
converter.
It shares high-level logic of operation with the already supported
BQ25703A, but has a different register map, bit definitions and some of
the lower-level hardware states.
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
drivers/power/supply/bq257xx_charger.c | 482 ++++++++++++++++++++++++++++++++-
1 file changed, 481 insertions(+), 1 deletion(-)
diff --git a/drivers/power/supply/bq257xx_charger.c b/drivers/power/supply/bq257xx_charger.c
index 9c082865e745..b9a41fe6f00e 100644
--- a/drivers/power/supply/bq257xx_charger.c
+++ b/drivers/power/supply/bq257xx_charger.c
@@ -5,6 +5,7 @@
*/
#include <linux/bitfield.h>
+#include <linux/byteorder/generic.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mfd/bq257xx.h>
@@ -88,6 +89,53 @@ struct bq257xx_chg {
u32 vsys_min;
};
+/**
+ * bq25792_read16() - Read a 16-bit value from device register
+ * @pdata: driver platform data
+ * @reg: register address to read from
+ * @val: pointer to store the register value
+ *
+ * Read a 16-bit big-endian value from the BQ25792 device via regmap
+ * and convert to CPU byte order.
+ *
+ * Return: Returns 0 on success or error on failure to read.
+ */
+static int bq25792_read16(struct bq257xx_chg *pdata, unsigned int reg, u16 *val)
+{
+ __be16 regval;
+ int ret;
+
+ ret = regmap_raw_read(pdata->bq->regmap, reg, ®val, sizeof(regval));
+ if (ret)
+ return ret;
+
+ *val = be16_to_cpu(regval);
+ return 0;
+}
+
+/**
+ * bq25792_write16() - Write a 16-bit value to device register
+ * @pdata: driver platform data
+ * @reg: register address to write to
+ * @val: 16-bit value to write in CPU byte order
+ *
+ * Convert the value to big-endian and write a 16-bit value to the
+ * BQ25792 device via regmap.
+ *
+ * Return: Returns 0 on success or error on failure to write.
+ */
+static int bq25792_write16(struct bq257xx_chg *pdata, unsigned int reg, u16 val)
+{
+ __be16 regval = cpu_to_be16(val);
+ int ret;
+
+ ret = regmap_raw_write(pdata->bq->regmap, reg, ®val, sizeof(regval));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
/**
* bq25703_get_state() - Get the current state of the device
* @pdata: driver platform data
@@ -119,6 +167,43 @@ static int bq25703_get_state(struct bq257xx_chg *pdata)
return 0;
}
+/**
+ * bq25792_get_state() - Get the current state of the device
+ * @pdata: driver platform data
+ *
+ * Get the current state of the BQ25792 charger by reading status
+ * registers. Updates the online, charging, overvoltage, and fault
+ * status fields in the driver data structure.
+ *
+ * Return: Returns 0 on success or error on failure to read device.
+ */
+static int bq25792_get_state(struct bq257xx_chg *pdata)
+{
+ unsigned int reg;
+ int ret;
+
+ ret = regmap_read(pdata->bq->regmap, BQ25792_REG1B_CHARGER_STATUS_0, ®);
+ if (ret)
+ return ret;
+
+ pdata->online = reg & BQ25792_REG1B_PG_STAT;
+
+ ret = regmap_read(pdata->bq->regmap, BQ25792_REG1C_CHARGER_STATUS_1, ®);
+ if (ret)
+ return ret;
+
+ pdata->charging = reg & BQ25792_REG1C_CHG_STAT_MASK;
+
+ ret = regmap_read(pdata->bq->regmap, BQ25792_REG20_FAULT_STATUS_0, ®);
+ if (ret)
+ return ret;
+
+ pdata->overvoltage = reg & BQ25792_REG20_OVERVOLTAGE_MASK;
+ pdata->oc_fault = reg & BQ25792_REG20_OVERCURRENT_MASK;
+
+ return 0;
+}
+
/**
* bq25703_get_min_vsys() - Get the minimum system voltage
* @pdata: driver platform data
@@ -142,6 +227,31 @@ static int bq25703_get_min_vsys(struct bq257xx_chg *pdata, int *intval)
return ret;
}
+/**
+ * bq25792_get_min_vsys() - Get the minimum system voltage
+ * @pdata: driver platform data
+ * @intval: pointer to store the minimum voltage value
+ *
+ * Read the current minimum system voltage setting from the device
+ * and return it in microvolts.
+ *
+ * Return: Returns 0 on success or error on failure to read.
+ */
+static int bq25792_get_min_vsys(struct bq257xx_chg *pdata, int *intval)
+{
+ unsigned int reg;
+ int ret;
+
+ ret = regmap_read(pdata->bq->regmap, BQ25792_REG00_MIN_SYS_VOLTAGE, ®);
+ if (ret)
+ return ret;
+
+ reg = FIELD_GET(BQ25792_REG00_VSYSMIN_MASK, reg);
+ *intval = (reg * BQ25792_MINVSYS_STEP_UV) + BQ25792_MINVSYS_MIN_UV;
+
+ return ret;
+}
+
/**
* bq25703_set_min_vsys() - Set the minimum system voltage
* @pdata: driver platform data
@@ -166,6 +276,29 @@ static int bq25703_set_min_vsys(struct bq257xx_chg *pdata, int vsys)
reg);
}
+/**
+ * bq25792_set_min_vsys() - Set the minimum system voltage
+ * @pdata: driver platform data
+ * @vsys: voltage value to set in uV
+ *
+ * Set the minimum system voltage by clamping the requested value
+ * between device limits and writing to the appropriate register.
+ *
+ * Return: Returns 0 on success or error on failure to write.
+ */
+static int bq25792_set_min_vsys(struct bq257xx_chg *pdata, int vsys)
+{
+ unsigned int reg;
+ int vsys_min = pdata->vsys_min;
+
+ vsys = clamp(vsys, vsys_min, BQ25792_MINVSYS_MAX_UV);
+ reg = ((vsys - BQ25792_MINVSYS_MIN_UV) / BQ25792_MINVSYS_STEP_UV);
+ reg = FIELD_PREP(BQ25792_REG00_VSYSMIN_MASK, reg);
+
+ return regmap_write(pdata->bq->regmap,
+ BQ25792_REG00_MIN_SYS_VOLTAGE, reg);
+}
+
/**
* bq25703_get_cur() - Get the reported current from the battery
* @pdata: driver platform data
@@ -195,6 +328,30 @@ static int bq25703_get_cur(struct bq257xx_chg *pdata, int *intval)
return ret;
}
+/**
+ * bq25792_get_cur() - Get the reported current from the battery
+ * @pdata: driver platform data
+ * @intval: pointer to store the battery current value
+ *
+ * Read the current ADC value from the device representing the battery
+ * charge or discharge current and return it in microamps.
+ *
+ * Return: Returns 0 on success or error on failure to read.
+ */
+static int bq25792_get_cur(struct bq257xx_chg *pdata, int *intval)
+{
+ u16 reg;
+ int ret;
+
+ ret = bq25792_read16(pdata, BQ25792_REG33_IBAT_ADC, ®);
+ if (ret < 0)
+ return ret;
+
+ *intval = (s16)reg * BQ25792_ADCIBAT_STEP_UA;
+
+ return ret;
+}
+
/**
* bq25703_get_ichg_cur() - Get the maximum reported charge current
* @pdata: driver platform data
@@ -218,6 +375,30 @@ static int bq25703_get_ichg_cur(struct bq257xx_chg *pdata, int *intval)
return ret;
}
+/**
+ * bq25792_get_ichg_cur() - Get the maximum reported charge current
+ * @pdata: driver platform data
+ * @intval: pointer to store the maximum charge current value
+ *
+ * Read the programmed maximum charge current limit from the device.
+ *
+ * Return: Returns 0 on success or error on failure to read value.
+ */
+static int bq25792_get_ichg_cur(struct bq257xx_chg *pdata, int *intval)
+{
+ u16 reg;
+ int ret;
+
+ ret = bq25792_read16(pdata, BQ25792_REG03_CHARGE_CURRENT_LIMIT, ®);
+ if (ret)
+ return ret;
+
+ *intval = FIELD_GET(BQ25792_REG03_ICHG_MASK, reg) *
+ BQ25792_ICHG_STEP_UA;
+
+ return ret;
+}
+
/**
* bq25703_set_ichg_cur() - Set the maximum charge current
* @pdata: driver platform data
@@ -242,6 +423,28 @@ static int bq25703_set_ichg_cur(struct bq257xx_chg *pdata, int ichg)
reg);
}
+/**
+ * bq25792_set_ichg_cur() - Set the maximum charge current
+ * @pdata: driver platform data
+ * @ichg: current value to set in uA
+ *
+ * Set the maximum charge current by clamping the requested value
+ * between device limits and writing to the appropriate register.
+ *
+ * Return: Returns 0 on success or error on failure to write.
+ */
+static int bq25792_set_ichg_cur(struct bq257xx_chg *pdata, int ichg)
+{
+ int ichg_max = pdata->ichg_max;
+ u16 reg;
+
+ ichg = clamp(ichg, BQ25792_ICHG_MIN_UA, ichg_max);
+ reg = FIELD_PREP(BQ25792_REG03_ICHG_MASK,
+ (ichg / BQ25792_ICHG_STEP_UA));
+
+ return bq25792_write16(pdata, BQ25792_REG03_CHARGE_CURRENT_LIMIT, reg);
+}
+
/**
* bq25703_get_chrg_volt() - Get the maximum set charge voltage
* @pdata: driver platform data
@@ -265,6 +468,30 @@ static int bq25703_get_chrg_volt(struct bq257xx_chg *pdata, int *intval)
return ret;
}
+/**
+ * bq25792_get_chrg_volt() - Get the maximum set charge voltage
+ * @pdata: driver platform data
+ * @intval: pointer to store the maximum charge voltage value
+ *
+ * Read the current charge voltage limit from the device.
+ *
+ * Return: Returns 0 on success or error on failure to read value.
+ */
+static int bq25792_get_chrg_volt(struct bq257xx_chg *pdata, int *intval)
+{
+ u16 reg;
+ int ret;
+
+ ret = bq25792_read16(pdata, BQ25792_REG01_CHARGE_VOLTAGE_LIMIT, ®);
+ if (ret)
+ return ret;
+
+ *intval = FIELD_GET(BQ25792_REG01_VREG_MASK, reg) *
+ BQ25792_VBATREG_STEP_UV;
+
+ return ret;
+}
+
/**
* bq25703_set_chrg_volt() - Set the maximum charge voltage
* @pdata: driver platform data
@@ -291,6 +518,29 @@ static int bq25703_set_chrg_volt(struct bq257xx_chg *pdata, int vbat)
reg);
}
+/**
+ * bq25792_set_chrg_volt() - Set the maximum charge voltage
+ * @pdata: driver platform data
+ * @vbat: voltage value to set in uV
+ *
+ * Set the maximum charge voltage by clamping the requested value
+ * between device limits and writing to the appropriate register.
+ *
+ * Return: Returns 0 on success or error on failure to write.
+ */
+static int bq25792_set_chrg_volt(struct bq257xx_chg *pdata, int vbat)
+{
+ int vbat_max = pdata->vbat_max;
+ u16 reg;
+
+ vbat = clamp(vbat, BQ25792_VBATREG_MIN_UV, vbat_max);
+
+ reg = FIELD_PREP(BQ25792_REG01_VREG_MASK,
+ (vbat / BQ25792_VBATREG_STEP_UV));
+
+ return bq25792_write16(pdata, BQ25792_REG01_CHARGE_VOLTAGE_LIMIT, reg);
+}
+
/**
* bq25703_get_iindpm() - Get the maximum set input current
* @pdata: driver platform data
@@ -319,6 +569,30 @@ static int bq25703_get_iindpm(struct bq257xx_chg *pdata, int *intval)
return ret;
}
+/**
+ * bq25792_get_iindpm() - Get the maximum set input current
+ * @pdata: driver platform data
+ * @intval: pointer to store the maximum input current value
+ *
+ * Read the current input current limit from the device.
+ *
+ * Return: Returns 0 on success or error on failure to read value.
+ */
+static int bq25792_get_iindpm(struct bq257xx_chg *pdata, int *intval)
+{
+ u16 reg;
+ int ret;
+
+ ret = bq25792_read16(pdata, BQ25792_REG06_INPUT_CURRENT_LIMIT, ®);
+ if (ret)
+ return ret;
+
+ reg = FIELD_GET(BQ25792_REG06_IINDPM_MASK, reg);
+ *intval = reg * BQ25792_IINDPM_STEP_UA;
+
+ return ret;
+}
+
/**
* bq25703_set_iindpm() - Set the maximum input current
* @pdata: driver platform data
@@ -344,6 +618,29 @@ static int bq25703_set_iindpm(struct bq257xx_chg *pdata, int iindpm)
FIELD_PREP(BQ25703_IINDPM_MASK, reg));
}
+/**
+ * bq25792_set_iindpm() - Set the maximum input current
+ * @pdata: driver platform data
+ * @iindpm: current value in uA
+ *
+ * Set the maximum input current by clamping the requested value
+ * between device limits and writing to the appropriate register.
+ *
+ * Return: Returns 0 on success or error on failure to write.
+ */
+static int bq25792_set_iindpm(struct bq257xx_chg *pdata, int iindpm)
+{
+ u16 reg;
+ int iindpm_max = pdata->iindpm_max;
+
+ iindpm = clamp(iindpm, BQ25792_IINDPM_MIN_UA, iindpm_max);
+
+ reg = iindpm / BQ25792_IINDPM_STEP_UA;
+
+ return bq25792_write16(pdata, BQ25792_REG06_INPUT_CURRENT_LIMIT,
+ FIELD_PREP(BQ25792_REG06_IINDPM_MASK, reg));
+}
+
/**
* bq25703_get_vbat() - Get the reported voltage from the battery
* @pdata: driver platform data
@@ -368,6 +665,30 @@ static int bq25703_get_vbat(struct bq257xx_chg *pdata, int *intval)
return ret;
}
+/**
+ * bq25792_get_vbat() - Get the reported voltage from the battery
+ * @pdata: driver platform data
+ * @intval: pointer to store the battery voltage value
+ *
+ * Read the current ADC value representing the battery voltage
+ * and return it in microvolts.
+ *
+ * Return: Returns 0 on success or error on failure to read value.
+ */
+static int bq25792_get_vbat(struct bq257xx_chg *pdata, int *intval)
+{
+ u16 reg;
+ int ret;
+
+ ret = bq25792_read16(pdata, BQ25792_REG3B_VBAT_ADC, ®);
+ if (ret)
+ return ret;
+
+ *intval = reg * BQ25792_ADCVSYSVBAT_STEP_UV;
+
+ return ret;
+}
+
/**
* bq25703_hw_init() - Set all the required registers to init the charger
* @pdata: driver platform data
@@ -434,6 +755,62 @@ static int bq25703_hw_init(struct bq257xx_chg *pdata)
return ret;
}
+/**
+ * bq25792_hw_init() - Initialize BQ25792 hardware
+ * @pdata: driver platform data
+ *
+ * Initialize the BQ25792 by disabling the watchdog, enabling discharge
+ * current sensing with 5A limit, and configuring input current regulation.
+ * Set the charge current, charge voltage, minimum system voltage, and
+ * input current limit from platform data. Enable and configure the ADC
+ * to measure all available channels.
+ *
+ * Return: Returns 0 on success or error code on error.
+ */
+static int bq25792_hw_init(struct bq257xx_chg *pdata)
+{
+ struct regmap *regmap = pdata->bq->regmap;
+ int ret = 0;
+
+ /* Disable watchdog (TODO: make it work instead) */
+ regmap_write(regmap, BQ25792_REG10_CHARGER_CONTROL_1, 0);
+
+ /*
+ * Enable battery discharge current sensing, 5A discharge current
+ * limit, input current regulation and ship FET functions
+ */
+ regmap_write(regmap, BQ25792_REG14_CHARGER_CONTROL_5,
+ BQ25792_REG14_SFET_PRESENT |
+ BQ25792_REG14_EN_IBAT |
+ BQ25792_IBAT_5A |
+ BQ25792_REG14_EN_IINDPM);
+
+ ret = pdata->chip->bq257xx_set_ichg(pdata, pdata->ichg_max);
+ if (ret)
+ return ret;
+
+ ret = pdata->chip->bq257xx_set_vbatreg(pdata, pdata->vbat_max);
+ if (ret)
+ return ret;
+
+ ret = bq25792_set_min_vsys(pdata, pdata->vsys_min);
+ if (ret)
+ return ret;
+
+ ret = pdata->chip->bq257xx_set_iindpm(pdata, pdata->iindpm_max);
+ if (ret)
+ return ret;
+
+ /* Enable the ADC. */
+ regmap_write(regmap, BQ25792_REG2E_ADC_CONTROL, BQ25792_REG2E_ADC_EN);
+
+ /* Clear per-channel ADC disable bits - enable all channels */
+ regmap_write(regmap, BQ25792_REG2F_ADC_FUNCTION_DISABLE_0, 0);
+ regmap_write(regmap, BQ25792_REG30_ADC_FUNCTION_DISABLE_1, 0);
+
+ return ret;
+}
+
/**
* bq25703_hw_shutdown() - Set registers for shutdown
* @pdata: driver platform data
@@ -446,6 +823,30 @@ static void bq25703_hw_shutdown(struct bq257xx_chg *pdata)
BQ25703_EN_LWPWR, BQ25703_EN_LWPWR);
}
+/**
+ * bq25792_hw_shutdown() - Shutdown BQ25792 hardware
+ * @pdata: driver platform data
+ *
+ * Perform hardware shutdown for the BQ25792. Currently a no-op
+ * as the device does not require special shutdown configuration.
+ */
+static void bq25792_hw_shutdown(struct bq257xx_chg *pdata)
+{
+ /* Nothing to do here */
+}
+
+/**
+ * bq257xx_set_charger_property() - Set a power supply property
+ * @psy: power supply device
+ * @prop: power supply property to set
+ * @val: value to set for the property
+ *
+ * Handle requests to set power supply properties such as input current
+ * limit, constant charge voltage, and constant charge current. Routes
+ * the request to the chip-specific implementation.
+ *
+ * Return: Returns 0 on success or -EINVAL if property is not supported.
+ */
static int bq257xx_set_charger_property(struct power_supply *psy,
enum power_supply_property prop,
const union power_supply_propval *val)
@@ -469,6 +870,19 @@ static int bq257xx_set_charger_property(struct power_supply *psy,
return -EINVAL;
}
+/**
+ * bq257xx_get_charger_property() - Get a power supply property
+ * @psy: power supply device
+ * @psp: power supply property to get
+ * @val: pointer to store the property value
+ *
+ * Handle requests to get power supply properties, including status,
+ * health, manufacturer, online state, and various voltage/current
+ * measurements. Reads current device state and routes chip-specific
+ * property requests to appropriate handlers.
+ *
+ * Return: Returns 0 on success or -EINVAL if property is not supported.
+ */
static int bq257xx_get_charger_property(struct power_supply *psy,
enum power_supply_property psp,
union power_supply_propval *val)
@@ -550,6 +964,17 @@ static enum power_supply_property bq257xx_power_supply_props[] = {
POWER_SUPPLY_PROP_USB_TYPE,
};
+/**
+ * bq257xx_property_is_writeable() - Check if a property is writeable
+ * @psy: power supply device
+ * @prop: power supply property to check
+ *
+ * Determines which power supply properties can be written to. Only
+ * charge current limit, charge voltage limit, and input current
+ * limit are writeable.
+ *
+ * Return: Returns 1 if property is writeable, 0 otherwise.
+ */
static int bq257xx_property_is_writeable(struct power_supply *psy,
enum power_supply_property prop)
{
@@ -622,6 +1047,17 @@ static void bq257xx_external_power_changed(struct power_supply *psy)
power_supply_changed(psy);
}
+/**
+ * bq257xx_irq_handler_thread() - Handle charger interrupt
+ * @irq: interrupt number
+ * @private: pointer to driver private data
+ *
+ * Thread handler for charger interrupts. Triggers re-evaluation of
+ * external power status and updates power supply state in response
+ * to charger events.
+ *
+ * Return: Returns IRQ_HANDLED if interrupt was processed.
+ */
static irqreturn_t bq257xx_irq_handler_thread(int irq, void *private)
{
struct bq257xx_chg *pdata = private;
@@ -662,6 +1098,22 @@ static const struct bq257xx_chip_info bq25703_chip_info = {
.bq257xx_get_min_vsys = &bq25703_get_min_vsys,
};
+static const struct bq257xx_chip_info bq25792_chip_info = {
+ .default_iindpm_uA = BQ25792_IINDPM_DEFAULT_UA,
+ .bq257xx_hw_init = &bq25792_hw_init,
+ .bq257xx_hw_shutdown = &bq25792_hw_shutdown,
+ .bq257xx_get_state = &bq25792_get_state,
+ .bq257xx_get_ichg = &bq25792_get_ichg_cur,
+ .bq257xx_set_ichg = &bq25792_set_ichg_cur,
+ .bq257xx_get_vbatreg = &bq25792_get_chrg_volt,
+ .bq257xx_set_vbatreg = &bq25792_set_chrg_volt,
+ .bq257xx_get_iindpm = &bq25792_get_iindpm,
+ .bq257xx_set_iindpm = &bq25792_set_iindpm,
+ .bq257xx_get_cur = &bq25792_get_cur,
+ .bq257xx_get_vbat = &bq25792_get_vbat,
+ .bq257xx_get_min_vsys = &bq25792_get_min_vsys,
+};
+
/**
* bq257xx_parse_dt() - Parse the device tree for required properties
* @pdata: driver platform data
@@ -707,6 +1159,17 @@ static int bq257xx_parse_dt(struct bq257xx_chg *pdata,
return 0;
}
+/**
+ * bq257xx_charger_probe() - Probe routine for charger platform device
+ * @pdev: platform device
+ *
+ * Probe the charger device, allocate driver data structure, select the
+ * appropriate chip-specific function pointers, register the power supply,
+ * parse device tree properties for battery limits, initialize hardware,
+ * and set up the interrupt handler if available.
+ *
+ * Return: Returns 0 on success or error code on failure.
+ */
static int bq257xx_charger_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -722,7 +1185,17 @@ static int bq257xx_charger_probe(struct platform_device *pdev)
return -ENOMEM;
pdata->bq = bq;
- pdata->chip = &bq25703_chip_info;
+
+ switch (bq->type) {
+ case BQ25703A:
+ pdata->chip = &bq25703_chip_info;
+ break;
+ case BQ25792:
+ pdata->chip = &bq25792_chip_info;
+ break;
+ default:
+ return dev_err_probe(dev, -EINVAL, "Unknown chip type\n");
+ }
platform_set_drvdata(pdev, pdata);
@@ -760,6 +1233,13 @@ static int bq257xx_charger_probe(struct platform_device *pdev)
return ret;
}
+/**
+ * bq257xx_charger_shutdown() - Shutdown routine for charger platform device
+ * @pdev: platform device
+ *
+ * Called during system shutdown to perform charger cleanup, including
+ * disabling watchdog timers or other chip-specific shutdown procedures.
+ */
static void bq257xx_charger_shutdown(struct platform_device *pdev)
{
struct bq257xx_chg *pdata = platform_get_drvdata(pdev);
--
2.52.0
^ permalink raw reply related
* [PATCH v2 2/4] drm/bridge: waveshare-dsi: support DSI LCD kits with LVDS panels
From: Dmitry Baryshkov @ 2026-03-31 15:44 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thierry Reding, Sam Ravnborg,
Joseph Guo, Marek Vasut, Andrzej Hajda, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec
Cc: dri-devel, devicetree, linux-kernel
In-Reply-To: <20260331-ws-lcd-v2-0-a1add63b6eb6@oss.qualcomm.com>
Several Waveshare DSI LCD kits use LVDS panels and the ICN6202 DSI2LVDS
bridge. Support that setup by handling waveshare,dsi2lvds compatible.
The only difference with the existing waveshare,dsi2dpi is the bridge's
output type (LVDS vs DPI).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/bridge/waveshare-dsi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/waveshare-dsi.c b/drivers/gpu/drm/bridge/waveshare-dsi.c
index 32d40414adb9..ded57f298d64 100644
--- a/drivers/gpu/drm/bridge/waveshare-dsi.c
+++ b/drivers/gpu/drm/bridge/waveshare-dsi.c
@@ -177,7 +177,7 @@ static int ws_bridge_probe(struct i2c_client *i2c)
regmap_write(ws->reg_map, 0xc2, 0x01);
regmap_write(ws->reg_map, 0xac, 0x01);
- ws->bridge.type = DRM_MODE_CONNECTOR_DPI;
+ ws->bridge.type = (uintptr_t)i2c_get_match_data(i2c);
ws->bridge.of_node = dev->of_node;
devm_drm_bridge_add(dev, &ws->bridge);
@@ -185,7 +185,8 @@ static int ws_bridge_probe(struct i2c_client *i2c)
}
static const struct of_device_id ws_bridge_of_ids[] = {
- {.compatible = "waveshare,dsi2dpi",},
+ {.compatible = "waveshare,dsi2dpi", .data = (void *)DRM_MODE_CONNECTOR_DPI, },
+ {.compatible = "waveshare,dsi2lvds", .data = (void *)DRM_MODE_CONNECTOR_LVDS, },
{ }
};
--
2.47.3
^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: display: waveshare,dsp2dpi: describe DSI2LVDS setup
From: Dmitry Baryshkov @ 2026-03-31 15:44 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thierry Reding, Sam Ravnborg,
Joseph Guo, Marek Vasut, Andrzej Hajda, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec
Cc: dri-devel, devicetree, linux-kernel
In-Reply-To: <20260331-ws-lcd-v2-0-a1add63b6eb6@oss.qualcomm.com>
Several the Waveshare DSI LCD panel kits use DSI2LVDS ICN6202 bridge
together with the LVDS panels. Define new compatible for the on-kit
bridge setup (it is not itmized and it uses Waveshare prefix since the
rest of the integration details are not known).
Note: the ICN6202 / ICN6211 bridges are completely handled by the board
itself, they should not be programmed by the host (which otherwise might
override correct params), etc. As such, it doesn't make sense to use
those in the compat strings. I consider those to be an internal detail
of the setup.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml
index 3820dd7e11af..4d34a92192bf 100644
--- a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml
@@ -10,11 +10,14 @@ maintainers:
- Joseph Guo <qijian.guo@nxp.com>
description:
- Waveshare bridge board is part of Waveshare panel which converts DSI to DPI.
+ Waveshare bridge board is part of Waveshare panel which converts DSI to DPI
+ or LVDS.
properties:
compatible:
- const: waveshare,dsi2dpi
+ enum:
+ - waveshare,dsi2dpi
+ - waveshare,dsi2lvds
reg:
maxItems: 1
@@ -53,7 +56,7 @@ properties:
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
- Video port for MIPI DPI output panel.
+ Video port for MIPI DPI or LVDS output to the panel.
required:
- port@0
--
2.47.3
^ permalink raw reply related
* [PATCH v2 0/4] drm/panel: simple: add Waveshare LCD panels
From: Dmitry Baryshkov @ 2026-03-31 15:44 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thierry Reding, Sam Ravnborg,
Joseph Guo, Marek Vasut, Andrzej Hajda, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec
Cc: dri-devel, devicetree, linux-kernel, Krzysztof Kozlowski
Waveshare have a serie of DSI panel kits with the DPI or LVDS panel
being attached to the DSI2DPI or DSI2LVDS bridge. Commit 80b0eb11f8e0
("dt-bindings: display: panel: Add waveshare DPI panel support")
described two of them in the bindings and commit 46be11b678e0
("drm/panel: simple: Add Waveshare 13.3" panel support") added
definitions for one of those panels. Add support for the rest of them.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Changes in v2:
- Updated waveshare,dsi2dpi schema to implicitly mention LVDS
(Krzysztof)
- Updated commit message to explain why the ICN6202 / ICN6211 bridges
are not a part of the DT bindings.
- Link to v1: https://patch.msgid.link/20260330-ws-lcd-v1-0-309834a435c0@oss.qualcomm.com
---
Dmitry Baryshkov (4):
dt-bindings: display: waveshare,dsp2dpi: describe DSI2LVDS setup
drm/bridge: waveshare-dsi: support DSI LCD kits with LVDS panels
dt-bindings: display: panel: add Waveshare LCD panels
drm/panel: simple: add Waveshare LCD panels
.../bindings/display/bridge/waveshare,dsi2dpi.yaml | 9 +-
.../bindings/display/panel/panel-simple.yaml | 28 ++
drivers/gpu/drm/bridge/waveshare-dsi.c | 5 +-
drivers/gpu/drm/panel/panel-simple.c | 381 +++++++++++++++++++++
4 files changed, 418 insertions(+), 5 deletions(-)
---
base-commit: 3b058d1aeeeff27a7289529c4944291613b364e9
change-id: 20260330-ws-lcd-b65c03c5ac17
Best regards,
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH v6 10/11] regulator: bq257xx: Add support for BQ25792
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
Add support for TI BQ25792, an integrated battery charger and buck/boost
regulator. This enables VBUS output from the charger's boost converter
for use in USB OTG applications, supporting 2.8-22V output at up to 3.32A
with 10mV and 40mA resolution.
Acked-by: Mark Brown <broonie@kernel.org>
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
drivers/regulator/bq257xx-regulator.c | 98 ++++++++++++++++++++++++++++++++++-
1 file changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/regulator/bq257xx-regulator.c b/drivers/regulator/bq257xx-regulator.c
index 0bb58ab4b8d4..f197162382cc 100644
--- a/drivers/regulator/bq257xx-regulator.c
+++ b/drivers/regulator/bq257xx-regulator.c
@@ -31,6 +31,32 @@ static int bq25703_vbus_get_cur_limit(struct regulator_dev *rdev)
return FIELD_GET(BQ25703_OTG_CUR_MASK, reg) * BQ25703_OTG_CUR_STEP_UA;
}
+static int bq25792_vbus_get_cur_limit(struct regulator_dev *rdev)
+{
+ struct regmap *regmap = rdev_get_regmap(rdev);
+ int ret;
+ unsigned int reg;
+
+ ret = regmap_read(regmap, BQ25792_REG0D_IOTG_REGULATION, ®);
+ if (ret)
+ return ret;
+ return FIELD_GET(BQ25792_REG0D_IOTG_MASK, reg) * BQ25792_OTG_CUR_STEP_UA;
+}
+
+static int bq25792_vbus_get_voltage_sel(struct regulator_dev *rdev)
+{
+ struct regmap *regmap = rdev_get_regmap(rdev);
+ __be16 reg;
+ int ret;
+
+ ret = regmap_raw_read(regmap, BQ25792_REG0B_VOTG_REGULATION,
+ ®, sizeof(reg));
+ if (ret)
+ return ret;
+
+ return FIELD_GET(BQ25792_REG0B_VOTG_MASK, be16_to_cpu(reg));
+}
+
/*
* Check if the minimum current and maximum current requested are
* sane values, then set the register accordingly.
@@ -54,6 +80,37 @@ static int bq25703_vbus_set_cur_limit(struct regulator_dev *rdev,
FIELD_PREP(BQ25703_OTG_CUR_MASK, reg));
}
+static int bq25792_vbus_set_cur_limit(struct regulator_dev *rdev,
+ int min_uA, int max_uA)
+{
+ struct regmap *regmap = rdev_get_regmap(rdev);
+ unsigned int reg;
+
+ if ((min_uA > BQ25792_OTG_CUR_MAX_UA) ||
+ (max_uA < BQ25792_OTG_CUR_MIN_UA))
+ return -EINVAL;
+
+ reg = (max_uA / BQ25792_OTG_CUR_STEP_UA);
+
+ /* Catch rounding errors since our step is 40000uA. */
+ if ((reg * BQ25792_OTG_CUR_STEP_UA) < min_uA)
+ return -EINVAL;
+
+ return regmap_write(regmap, BQ25792_REG0D_IOTG_REGULATION,
+ FIELD_PREP(BQ25792_REG0D_IOTG_MASK, reg));
+}
+
+static int bq25792_vbus_set_voltage_sel(struct regulator_dev *rdev,
+ unsigned int sel)
+{
+ struct regmap *regmap = rdev_get_regmap(rdev);
+ __be16 reg;
+
+ reg = cpu_to_be16(FIELD_PREP(BQ25792_REG0B_VOTG_MASK, sel));
+ return regmap_raw_write(regmap, BQ25792_REG0B_VOTG_REGULATION,
+ ®, sizeof(reg));
+}
+
static int bq25703_vbus_enable(struct regulator_dev *rdev)
{
struct bq257xx_reg_data *pdata = rdev_get_drvdata(rdev);
@@ -101,6 +158,34 @@ static const struct regulator_desc bq25703_vbus_desc = {
.vsel_mask = BQ25703_OTG_VOLT_MASK,
};
+static const struct regulator_ops bq25792_vbus_ops = {
+ /* No GPIO for enabling the OTG regulator */
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .list_voltage = regulator_list_voltage_linear,
+ .get_voltage_sel = bq25792_vbus_get_voltage_sel,
+ .set_voltage_sel = bq25792_vbus_set_voltage_sel,
+ .get_current_limit = bq25792_vbus_get_cur_limit,
+ .set_current_limit = bq25792_vbus_set_cur_limit,
+};
+
+static const struct regulator_desc bq25792_vbus_desc = {
+ .name = "vbus",
+ .of_match = of_match_ptr("vbus"),
+ .regulators_node = of_match_ptr("regulators"),
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ .ops = &bq25792_vbus_ops,
+ .min_uV = BQ25792_OTG_VOLT_MIN_UV,
+ .uV_step = BQ25792_OTG_VOLT_STEP_UV,
+ .n_voltages = BQ25792_OTG_VOLT_NUM_VOLT,
+ .enable_mask = BQ25792_REG12_EN_OTG,
+ .enable_reg = BQ25792_REG12_CHARGER_CONTROL_3,
+ .enable_val = BQ25792_REG12_EN_OTG,
+ .disable_val = 0,
+};
+
/* Get optional GPIO for OTG regulator enable. */
static void bq257xx_reg_dt_parse_gpio(struct platform_device *pdev)
{
@@ -141,6 +226,7 @@ static void bq257xx_reg_dt_parse_gpio(struct platform_device *pdev)
static int bq257xx_regulator_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ struct bq257xx_device *bq = dev_get_drvdata(pdev->dev.parent);
struct bq257xx_reg_data *pdata;
struct device_node *np = dev->of_node;
struct regulator_config cfg = {};
@@ -153,7 +239,17 @@ static int bq257xx_regulator_probe(struct platform_device *pdev)
if (!pdata)
return -ENOMEM;
- pdata->desc = bq25703_vbus_desc;
+ switch (bq->type) {
+ case BQ25703A:
+ pdata->desc = bq25703_vbus_desc;
+ break;
+ case BQ25792:
+ pdata->desc = bq25792_vbus_desc;
+ break;
+ default:
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "Unsupported device type\n");
+ }
platform_set_drvdata(pdev, pdata);
bq257xx_reg_dt_parse_gpio(pdev);
--
2.52.0
^ permalink raw reply related
* [PATCH v6 09/11] mfd: bq257xx: Add BQ25792 support
From: Alexey Charkov @ 2026-03-31 15:43 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chris Morgan, Liam Girdwood, Mark Brown, Sebastian Reichel
Cc: devicetree, linux-kernel, Sebastian Reichel, linux-pm,
Alexey Charkov
In-Reply-To: <20260331-bq25792-v6-0-0278fba33eb9@flipper.net>
Add register definitions and a new 'type' enum to be passed via MFD
private data to support the BQ25792, which is a newer variant of the
BQ257xx family.
BQ25792 shares similar logic of operation with the already supported
BQ25703A but has a completely different register map and different
electrical constraints.
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
---
drivers/mfd/bq257xx.c | 54 +++++-
include/linux/mfd/bq257xx.h | 412 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 463 insertions(+), 3 deletions(-)
diff --git a/drivers/mfd/bq257xx.c b/drivers/mfd/bq257xx.c
index e9d49dac0a16..054342c60b73 100644
--- a/drivers/mfd/bq257xx.c
+++ b/drivers/mfd/bq257xx.c
@@ -39,6 +39,39 @@ static const struct regmap_config bq25703_regmap_config = {
.val_format_endian = REGMAP_ENDIAN_LITTLE,
};
+static const struct regmap_range bq25792_writeable_reg_ranges[] = {
+ regmap_reg_range(BQ25792_REG00_MIN_SYS_VOLTAGE,
+ BQ25792_REG18_NTC_CONTROL_1),
+ regmap_reg_range(BQ25792_REG28_CHARGER_MASK_0,
+ BQ25792_REG30_ADC_FUNCTION_DISABLE_1),
+};
+
+static const struct regmap_access_table bq25792_writeable_regs = {
+ .yes_ranges = bq25792_writeable_reg_ranges,
+ .n_yes_ranges = ARRAY_SIZE(bq25792_writeable_reg_ranges),
+};
+
+static const struct regmap_range bq25792_volatile_reg_ranges[] = {
+ regmap_reg_range(BQ25792_REG19_ICO_CURRENT_LIMIT,
+ BQ25792_REG27_FAULT_FLAG_1),
+ regmap_reg_range(BQ25792_REG31_IBUS_ADC,
+ BQ25792_REG47_DPDM_DRIVER),
+};
+
+static const struct regmap_access_table bq25792_volatile_regs = {
+ .yes_ranges = bq25792_volatile_reg_ranges,
+ .n_yes_ranges = ARRAY_SIZE(bq25792_volatile_reg_ranges),
+};
+
+static const struct regmap_config bq25792_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = BQ25792_REG48_PART_INFORMATION,
+ .cache_type = REGCACHE_MAPLE,
+ .wr_table = &bq25792_writeable_regs,
+ .volatile_table = &bq25792_volatile_regs,
+};
+
static const struct mfd_cell cells[] = {
MFD_CELL_NAME("bq257xx-regulator"),
MFD_CELL_NAME("bq257xx-charger"),
@@ -46,6 +79,7 @@ static const struct mfd_cell cells[] = {
static int bq257xx_probe(struct i2c_client *client)
{
+ const struct regmap_config *rcfg;
struct bq257xx_device *ddata;
int ret;
@@ -53,9 +87,21 @@ static int bq257xx_probe(struct i2c_client *client)
if (!ddata)
return -ENOMEM;
+ ddata->type = (uintptr_t)i2c_get_match_data(client);
ddata->client = client;
- ddata->regmap = devm_regmap_init_i2c(client, &bq25703_regmap_config);
+ switch (ddata->type) {
+ case BQ25703A:
+ rcfg = &bq25703_regmap_config;
+ break;
+ case BQ25792:
+ rcfg = &bq25792_regmap_config;
+ break;
+ default:
+ return dev_err_probe(&client->dev, -ENODEV, "Unsupported device type\n");
+ }
+
+ ddata->regmap = devm_regmap_init_i2c(client, rcfg);
if (IS_ERR(ddata->regmap)) {
return dev_err_probe(&client->dev, PTR_ERR(ddata->regmap),
"Failed to allocate register map\n");
@@ -73,13 +119,15 @@ static int bq257xx_probe(struct i2c_client *client)
}
static const struct i2c_device_id bq257xx_i2c_ids[] = {
- { "bq25703a" },
+ { "bq25703a", BQ25703A },
+ { "bq25792", BQ25792 },
{}
};
MODULE_DEVICE_TABLE(i2c, bq257xx_i2c_ids);
static const struct of_device_id bq257xx_of_match[] = {
- { .compatible = "ti,bq25703a" },
+ { .compatible = "ti,bq25703a", .data = (void *)BQ25703A },
+ { .compatible = "ti,bq25792", .data = (void *)BQ25792 },
{}
};
MODULE_DEVICE_TABLE(of, bq257xx_of_match);
diff --git a/include/linux/mfd/bq257xx.h b/include/linux/mfd/bq257xx.h
index 1d6ddc7fb09f..4ec72eb920f2 100644
--- a/include/linux/mfd/bq257xx.h
+++ b/include/linux/mfd/bq257xx.h
@@ -98,7 +98,419 @@
#define BQ25703_EN_OTG_MASK BIT(12)
+#define BQ25792_REG00_MIN_SYS_VOLTAGE 0x00
+#define BQ25792_REG01_CHARGE_VOLTAGE_LIMIT 0x01
+#define BQ25792_REG03_CHARGE_CURRENT_LIMIT 0x03
+#define BQ25792_REG05_INPUT_VOLTAGE_LIMIT 0x05
+#define BQ25792_REG06_INPUT_CURRENT_LIMIT 0x06
+#define BQ25792_REG08_PRECHARGE_CONTROL 0x08
+#define BQ25792_REG09_TERMINATION_CONTROL 0x09
+#define BQ25792_REG0A_RECHARGE_CONTROL 0x0a
+#define BQ25792_REG0B_VOTG_REGULATION 0x0b
+#define BQ25792_REG0D_IOTG_REGULATION 0x0d
+#define BQ25792_REG0E_TIMER_CONTROL 0x0e
+#define BQ25792_REG0F_CHARGER_CONTROL_0 0x0f
+#define BQ25792_REG10_CHARGER_CONTROL_1 0x10
+#define BQ25792_REG11_CHARGER_CONTROL_2 0x11
+#define BQ25792_REG12_CHARGER_CONTROL_3 0x12
+#define BQ25792_REG13_CHARGER_CONTROL_4 0x13
+#define BQ25792_REG14_CHARGER_CONTROL_5 0x14
+/* REG15 reserved */
+#define BQ25792_REG16_TEMPERATURE_CONTROL 0x16
+#define BQ25792_REG17_NTC_CONTROL_0 0x17
+#define BQ25792_REG18_NTC_CONTROL_1 0x18
+#define BQ25792_REG19_ICO_CURRENT_LIMIT 0x19
+#define BQ25792_REG1B_CHARGER_STATUS_0 0x1b
+#define BQ25792_REG1C_CHARGER_STATUS_1 0x1c
+#define BQ25792_REG1D_CHARGER_STATUS_2 0x1d
+#define BQ25792_REG1E_CHARGER_STATUS_3 0x1e
+#define BQ25792_REG1F_CHARGER_STATUS_4 0x1f
+#define BQ25792_REG20_FAULT_STATUS_0 0x20
+#define BQ25792_REG21_FAULT_STATUS_1 0x21
+#define BQ25792_REG22_CHARGER_FLAG_0 0x22
+#define BQ25792_REG23_CHARGER_FLAG_1 0x23
+#define BQ25792_REG24_CHARGER_FLAG_2 0x24
+#define BQ25792_REG25_CHARGER_FLAG_3 0x25
+#define BQ25792_REG26_FAULT_FLAG_0 0x26
+#define BQ25792_REG27_FAULT_FLAG_1 0x27
+#define BQ25792_REG28_CHARGER_MASK_0 0x28
+#define BQ25792_REG29_CHARGER_MASK_1 0x29
+#define BQ25792_REG2A_CHARGER_MASK_2 0x2a
+#define BQ25792_REG2B_CHARGER_MASK_3 0x2b
+#define BQ25792_REG2C_FAULT_MASK_0 0x2c
+#define BQ25792_REG2D_FAULT_MASK_1 0x2d
+#define BQ25792_REG2E_ADC_CONTROL 0x2e
+#define BQ25792_REG2F_ADC_FUNCTION_DISABLE_0 0x2f
+#define BQ25792_REG30_ADC_FUNCTION_DISABLE_1 0x30
+#define BQ25792_REG31_IBUS_ADC 0x31
+#define BQ25792_REG33_IBAT_ADC 0x33
+#define BQ25792_REG35_VBUS_ADC 0x35
+#define BQ25792_REG37_VAC1_ADC 0x37
+#define BQ25792_REG39_VAC2_ADC 0x39
+#define BQ25792_REG3B_VBAT_ADC 0x3b
+#define BQ25792_REG3D_VSYS_ADC 0x3d
+#define BQ25792_REG3F_TS_ADC 0x3f
+#define BQ25792_REG41_TDIE_ADC 0x41
+#define BQ25792_REG43_DP_ADC 0x43
+#define BQ25792_REG45_DM_ADC 0x45
+#define BQ25792_REG47_DPDM_DRIVER 0x47
+#define BQ25792_REG48_PART_INFORMATION 0x48
+
+/* Minimal System Voltage */
+#define BQ25792_REG00_VSYSMIN_MASK GENMASK(5, 0)
+
+#define BQ25792_MINVSYS_MIN_UV 2500000
+#define BQ25792_MINVSYS_STEP_UV 250000
+#define BQ25792_MINVSYS_MAX_UV 16000000
+
+/* Charge Voltage Limit */
+#define BQ25792_REG01_VREG_MASK GENMASK(10, 0)
+
+#define BQ25792_VBATREG_MIN_UV 3000000
+#define BQ25792_VBATREG_STEP_UV 10000
+#define BQ25792_VBATREG_MAX_UV 18800000
+
+/* Charge Current Limit */
+#define BQ25792_REG03_ICHG_MASK GENMASK(8, 0)
+
+#define BQ25792_ICHG_MIN_UA 50000
+#define BQ25792_ICHG_STEP_UA 10000
+#define BQ25792_ICHG_MAX_UA 5000000
+
+/* Input Voltage Limit */
+#define BQ25792_REG05_VINDPM_MASK GENMASK(7, 0)
+
+/* Input Current Limit */
+#define BQ25792_REG06_IINDPM_MASK GENMASK(8, 0)
+#define BQ25792_IINDPM_DEFAULT_UA 3000000
+#define BQ25792_IINDPM_STEP_UA 10000
+#define BQ25792_IINDPM_MIN_UA 100000
+#define BQ25792_IINDPM_MAX_UA 3300000
+
+/* Precharge Control */
+#define BQ25792_REG08_VBAT_LOWV_MASK GENMASK(7, 6)
+#define BQ25792_REG08_IPRECHG_MASK GENMASK(5, 0)
+
+/* Termination Control */
+#define BQ25792_REG09_REG_RST BIT(6)
+#define BQ25792_REG09_ITERM_MASK GENMASK(4, 0)
+
+/* Re-charge Control */
+#define BQ25792_REG0A_CELL_MASK GENMASK(7, 6)
+#define BQ25792_REG0A_TRECHG_MASK GENMASK(5, 4)
+#define BQ25792_REG0A_VRECHG_MASK GENMASK(3, 0)
+
+/* VOTG regulation */
+#define BQ25792_REG0B_VOTG_MASK GENMASK(10, 0)
+
+#define BQ25792_OTG_VOLT_MIN_UV 2800000
+#define BQ25792_OTG_VOLT_STEP_UV 10000
+#define BQ25792_OTG_VOLT_MAX_UV 22000000
+#define BQ25792_OTG_VOLT_NUM_VOLT ((BQ25792_OTG_VOLT_MAX_UV \
+ - BQ25792_OTG_VOLT_MIN_UV) \
+ / BQ25792_OTG_VOLT_STEP_UV + 1)
+
+/* IOTG regulation */
+#define BQ25792_REG0D_PRECHG_TMR BIT(7)
+#define BQ25792_REG0D_IOTG_MASK GENMASK(6, 0)
+
+#define BQ25792_OTG_CUR_MIN_UA 120000
+#define BQ25792_OTG_CUR_STEP_UA 40000
+#define BQ25792_OTG_CUR_MAX_UA 3320000
+
+/* Timer Control */
+#define BQ25792_REG0E_TOPOFF_TMR_MASK GENMASK(7, 6)
+#define BQ25792_REG0E_EN_TRICHG_TMR BIT(5)
+#define BQ25792_REG0E_EN_PRECHG_TMR BIT(4)
+#define BQ25792_REG0E_EN_CHG_TMR BIT(3)
+#define BQ25792_REG0E_CHG_TMR_MASK GENMASK(2, 1)
+#define BQ25792_REG0E_TMR2X_EN BIT(0)
+
+/* Charger Control 0 */
+#define BQ25792_REG0F_EN_AUTO_IBATDIS BIT(7)
+#define BQ25792_REG0F_FORCE_IBATDIS BIT(6)
+#define BQ25792_REG0F_EN_CHG BIT(5)
+#define BQ25792_REG0F_EN_ICO BIT(4)
+#define BQ25792_REG0F_FORCE_ICO BIT(3)
+#define BQ25792_REG0F_EN_HIZ BIT(2)
+#define BQ25792_REG0F_EN_TERM BIT(1)
+/* bit0 reserved */
+
+/* Charger Control 1 */
+#define BQ25792_REG10_VAC_OVP_MASK GENMASK(5, 4)
+#define BQ25792_REG10_WD_RST BIT(3)
+#define BQ25792_REG10_WATCHDOG_MASK GENMASK(2, 0)
+
+/* Charger Control 2 */
+#define BQ25792_REG11_FORCE_INDET BIT(7)
+#define BQ25792_REG11_AUTO_INDET_EN BIT(6)
+#define BQ25792_REG11_EN_12V BIT(5)
+#define BQ25792_REG11_EN_9V BIT(4)
+#define BQ25792_REG11_HVDCP_EN BIT(3)
+#define BQ25792_REG11_SDRV_CTRL_MASK GENMASK(2, 1)
+#define BQ25792_REG11_SDRV_DLY BIT(0)
+
+/* Charger Control 3 */
+#define BQ25792_REG12_DIS_ACDRV BIT(7)
+#define BQ25792_REG12_EN_OTG BIT(6)
+#define BQ25792_REG12_PFM_OTG_DIS BIT(5)
+#define BQ25792_REG12_PFM_FWD_DIS BIT(4)
+#define BQ25792_REG12_WKUP_DLY BIT(3)
+#define BQ25792_REG12_DIS_LDO BIT(2)
+#define BQ25792_REG12_DIS_OTG_OOA BIT(1)
+#define BQ25792_REG12_DIS_FWD_OOA BIT(0)
+
+/* Charger Control 4 */
+#define BQ25792_REG13_EN_ACDRV2 BIT(7)
+#define BQ25792_REG13_EN_ACDRV1 BIT(6)
+#define BQ25792_REG13_PWM_FREQ BIT(5)
+#define BQ25792_REG13_DIS_STAT BIT(4)
+#define BQ25792_REG13_DIS_VSYS_SHORT BIT(3)
+#define BQ25792_REG13_DIS_VOTG_UVP BIT(2)
+#define BQ25792_REG13_FORCE_VINDPM_DET BIT(1)
+#define BQ25792_REG13_EN_IBUS_OCP BIT(0)
+
+/* Charger Control 5 */
+#define BQ25792_REG14_SFET_PRESENT BIT(7)
+/* bit6 reserved */
+#define BQ25792_REG14_EN_IBAT BIT(5)
+#define BQ25792_REG14_IBAT_REG_MASK GENMASK(4, 3)
+#define BQ25792_REG14_EN_IINDPM BIT(2)
+#define BQ25792_REG14_EN_EXTILIM BIT(1)
+#define BQ25792_REG14_EN_BATOC BIT(0)
+
+#define BQ25792_IBAT_3A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 0)
+#define BQ25792_IBAT_4A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 1)
+#define BQ25792_IBAT_5A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 2)
+#define BQ25792_IBAT_UNLIM FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 3)
+
+/* Temperature Control */
+#define BQ25792_REG16_TREG_MASK GENMASK(7, 6)
+#define BQ25792_REG16_TSHUT_MASK GENMASK(5, 4)
+#define BQ25792_REG16_VBUS_PD_EN BIT(3)
+#define BQ25792_REG16_VAC1_PD_EN BIT(2)
+#define BQ25792_REG16_VAC2_PD_EN BIT(1)
+
+/* NTC Control 0 */
+#define BQ25792_REG17_JEITA_VSET_MASK GENMASK(7, 5)
+#define BQ25792_REG17_JEITA_ISETH_MASK GENMASK(4, 3)
+#define BQ25792_REG17_JEITA_ISETC_MASK GENMASK(2, 1)
+
+/* NTC Control 1 */
+#define BQ25792_REG18_TS_COOL_MASK GENMASK(7, 6)
+#define BQ25792_REG18_TS_WARM_MASK GENMASK(5, 4)
+#define BQ25792_REG18_BHOT_MASK GENMASK(3, 2)
+#define BQ25792_REG18_BCOLD BIT(1)
+#define BQ25792_REG18_TS_IGNORE BIT(0)
+
+/* ICO Current Limit */
+#define BQ25792_REG19_ICO_ILIM_MASK GENMASK(8, 0)
+
+/* Charger Status 0 */
+#define BQ25792_REG1B_IINDPM_STAT BIT(7)
+#define BQ25792_REG1B_VINDPM_STAT BIT(6)
+#define BQ25792_REG1B_WD_STAT BIT(5)
+#define BQ25792_REG1B_POORSRC_STAT BIT(4)
+#define BQ25792_REG1B_PG_STAT BIT(3)
+#define BQ25792_REG1B_AC2_PRESENT_STAT BIT(2)
+#define BQ25792_REG1B_AC1_PRESENT_STAT BIT(1)
+#define BQ25792_REG1B_VBUS_PRESENT_STAT BIT(0)
+
+/* Charger Status 1 */
+#define BQ25792_REG1C_CHG_STAT_MASK GENMASK(7, 5)
+#define BQ25792_REG1C_VBUS_STAT_MASK GENMASK(4, 1)
+#define BQ25792_REG1C_BC12_DONE_STAT BIT(0)
+
+/* Charger Status 2 */
+#define BQ25792_REG1D_ICO_STAT_MASK GENMASK(7, 6)
+#define BQ25792_REG1D_TREG_STAT BIT(2)
+#define BQ25792_REG1D_DPDM_STAT BIT(1)
+#define BQ25792_REG1D_VBAT_PRESENT_STAT BIT(0)
+
+/* Charger Status 3 */
+#define BQ25792_REG1E_ACRB2_STAT BIT(7)
+#define BQ25792_REG1E_ACRB1_STAT BIT(6)
+#define BQ25792_REG1E_ADC_DONE_STAT BIT(5)
+#define BQ25792_REG1E_VSYS_STAT BIT(4)
+#define BQ25792_REG1E_CHG_TMR_STAT BIT(3)
+#define BQ25792_REG1E_TRICHG_TMR_STAT BIT(2)
+#define BQ25792_REG1E_PRECHG_TMR_STAT BIT(1)
+
+/* Charger Status 4 */
+#define BQ25792_REG1F_VBATOTG_LOW_STAT BIT(4)
+#define BQ25792_REG1F_TS_COLD_STAT BIT(3)
+#define BQ25792_REG1F_TS_COOL_STAT BIT(2)
+#define BQ25792_REG1F_TS_WARM_STAT BIT(1)
+#define BQ25792_REG1F_TS_HOT_STAT BIT(0)
+
+/* FAULT Status 0 */
+#define BQ25792_REG20_IBAT_REG_STAT BIT(7)
+#define BQ25792_REG20_VBUS_OVP_STAT BIT(6)
+#define BQ25792_REG20_VBAT_OVP_STAT BIT(5)
+#define BQ25792_REG20_IBUS_OCP_STAT BIT(4)
+#define BQ25792_REG20_IBAT_OCP_STAT BIT(3)
+#define BQ25792_REG20_CONV_OCP_STAT BIT(2)
+#define BQ25792_REG20_VAC2_OVP_STAT BIT(1)
+#define BQ25792_REG20_VAC1_OVP_STAT BIT(0)
+
+#define BQ25792_REG20_OVERVOLTAGE_MASK (BQ25792_REG20_VBAT_OVP_STAT | \
+ BQ25792_REG20_VAC2_OVP_STAT | \
+ BQ25792_REG20_VAC1_OVP_STAT)
+#define BQ25792_REG20_OVERCURRENT_MASK (BQ25792_REG20_IBAT_OCP_STAT | \
+ BQ25792_REG20_CONV_OCP_STAT)
+
+/* FAULT Status 1 */
+#define BQ25792_REG21_VSYS_SHORT_STAT BIT(7)
+#define BQ25792_REG21_VSYS_OVP_STAT BIT(6)
+#define BQ25792_REG21_OTG_OVP_STAT BIT(5)
+#define BQ25792_REG21_OTG_UVP_STAT BIT(4)
+#define BQ25792_REG21_TSHUT_STAT BIT(2)
+
+
+/* Charger Flag 0 */
+#define BQ25792_REG22_IINDPM_FLAG BIT(7)
+#define BQ25792_REG22_VINDPM_FLAG BIT(6)
+#define BQ25792_REG22_WD_FLAG BIT(5)
+#define BQ25792_REG22_POORSRC_FLAG BIT(4)
+#define BQ25792_REG22_PG_FLAG BIT(3)
+#define BQ25792_REG22_AC2_PRESENT_FLAG BIT(2)
+#define BQ25792_REG22_AC1_PRESENT_FLAG BIT(1)
+#define BQ25792_REG22_VBUS_PRESENT_FLAG BIT(0)
+
+/* Charger Flag 1 */
+#define BQ25792_REG23_CHG_FLAG BIT(7)
+#define BQ25792_REG23_ICO_FLAG BIT(6)
+#define BQ25792_REG23_VBUS_FLAG BIT(4)
+#define BQ25792_REG23_TREG_FLAG BIT(2)
+#define BQ25792_REG23_VBAT_PRESENT_FLAG BIT(1)
+#define BQ25792_REG23_BC12_DONE_FLAG BIT(0)
+
+/* Charger Flag 2 */
+#define BQ25792_REG24_DPDM_DONE_FLAG BIT(6)
+#define BQ25792_REG24_ADC_DONE_FLAG BIT(5)
+#define BQ25792_REG24_VSYS_FLAG BIT(4)
+#define BQ25792_REG24_CHG_TMR_FLAG BIT(3)
+#define BQ25792_REG24_TRICHG_TMR_FLAG BIT(2)
+#define BQ25792_REG24_PRECHG_TMR_FLAG BIT(1)
+#define BQ25792_REG24_TOPOFF_TMR_FLAG BIT(0)
+
+/* Charger Flag 3 */
+#define BQ25792_REG25_VBATOTG_LOW_FLAG BIT(4)
+#define BQ25792_REG25_TS_COLD_FLAG BIT(3)
+#define BQ25792_REG25_TS_COOL_FLAG BIT(2)
+#define BQ25792_REG25_TS_WARM_FLAG BIT(1)
+#define BQ25792_REG25_TS_HOT_FLAG BIT(0)
+
+/* FAULT Flag 0 */
+#define BQ25792_REG26_IBAT_REG_FLAG BIT(7)
+#define BQ25792_REG26_VBUS_OVP_FLAG BIT(6)
+#define BQ25792_REG26_VBAT_OVP_FLAG BIT(5)
+#define BQ25792_REG26_IBUS_OCP_FLAG BIT(4)
+#define BQ25792_REG26_IBAT_OCP_FLAG BIT(3)
+#define BQ25792_REG26_CONV_OCP_FLAG BIT(2)
+#define BQ25792_REG26_VAC2_OVP_FLAG BIT(1)
+#define BQ25792_REG26_VAC1_OVP_FLAG BIT(0)
+
+/* FAULT Flag 1 */
+#define BQ25792_REG27_VSYS_SHORT_FLAG BIT(7)
+#define BQ25792_REG27_VSYS_OVP_FLAG BIT(6)
+#define BQ25792_REG27_OTG_OVP_FLAG BIT(5)
+#define BQ25792_REG27_OTG_UVP_FLAG BIT(4)
+#define BQ25792_REG27_TSHUT_FLAG BIT(2)
+
+/* Charger Mask 0 */
+#define BQ25792_REG28_IINDPM_MASK BIT(7)
+#define BQ25792_REG28_VINDPM_MASK BIT(6)
+#define BQ25792_REG28_WD_MASK BIT(5)
+#define BQ25792_REG28_POORSRC_MASK BIT(4)
+#define BQ25792_REG28_PG_MASK BIT(3)
+#define BQ25792_REG28_AC2_PRESENT_MASK BIT(2)
+#define BQ25792_REG28_AC1_PRESENT_MASK BIT(1)
+#define BQ25792_REG28_VBUS_PRESENT_MASK BIT(0)
+
+/* Charger Mask 1 */
+#define BQ25792_REG29_CHG_MASK BIT(7)
+#define BQ25792_REG29_ICO_MASK BIT(6)
+#define BQ25792_REG29_VBUS_MASK BIT(4)
+#define BQ25792_REG29_TREG_MASK BIT(2)
+#define BQ25792_REG29_VBAT_PRESENT_MASK BIT(1)
+#define BQ25792_REG29_BC12_DONE_MASK BIT(0)
+
+/* Charger Mask 2 */
+#define BQ25792_REG2A_DPDM_DONE_MASK BIT(6)
+#define BQ25792_REG2A_ADC_DONE_MASK BIT(5)
+#define BQ25792_REG2A_VSYS_MASK BIT(4)
+#define BQ25792_REG2A_CHG_TMR_MASK BIT(3)
+#define BQ25792_REG2A_TRICHG_TMR_MASK BIT(2)
+#define BQ25792_REG2A_PRECHG_TMR_MASK BIT(1)
+#define BQ25792_REG2A_TOPOFF_TMR_MASK BIT(0)
+
+/* Charger Mask 3 */
+#define BQ25792_REG2B_VBATOTG_LOW_MASK BIT(4)
+#define BQ25792_REG2B_TS_COLD_MASK BIT(3)
+#define BQ25792_REG2B_TS_COOL_MASK BIT(2)
+#define BQ25792_REG2B_TS_WARM_MASK BIT(1)
+#define BQ25792_REG2B_TS_HOT_MASK BIT(0)
+
+/* FAULT Mask 0 */
+#define BQ25792_REG2C_IBAT_REG_MASK BIT(7)
+#define BQ25792_REG2C_VBUS_OVP_MASK BIT(6)
+#define BQ25792_REG2C_VBAT_OVP_MASK BIT(5)
+#define BQ25792_REG2C_IBUS_OCP_MASK BIT(4)
+#define BQ25792_REG2C_IBAT_OCP_MASK BIT(3)
+#define BQ25792_REG2C_CONV_OCP_MASK BIT(2)
+#define BQ25792_REG2C_VAC2_OVP_MASK BIT(1)
+#define BQ25792_REG2C_VAC1_OVP_MASK BIT(0)
+
+/* FAULT Mask 1 */
+#define BQ25792_REG2D_VSYS_SHORT_MASK BIT(7)
+#define BQ25792_REG2D_VSYS_OVP_MASK BIT(6)
+#define BQ25792_REG2D_OTG_OVP_MASK BIT(5)
+#define BQ25792_REG2D_OTG_UVP_MASK BIT(4)
+#define BQ25792_REG2D_TSHUT_MASK BIT(2)
+
+/* ADC Control */
+#define BQ25792_REG2E_ADC_EN BIT(7)
+#define BQ25792_REG2E_ADC_RATE BIT(6)
+#define BQ25792_REG2E_ADC_SAMPLE_MASK GENMASK(5, 4)
+#define BQ25792_REG2E_ADC_AVG BIT(3)
+#define BQ25792_REG2E_ADC_AVG_INIT BIT(2)
+
+/* ADC Function Disable 0 */
+#define BQ25792_REG2F_IBUS_ADC_DIS BIT(7)
+#define BQ25792_REG2F_IBAT_ADC_DIS BIT(6)
+#define BQ25792_REG2F_VBUS_ADC_DIS BIT(5)
+#define BQ25792_REG2F_VBAT_ADC_DIS BIT(4)
+#define BQ25792_REG2F_VSYS_ADC_DIS BIT(3)
+#define BQ25792_REG2F_TS_ADC_DIS BIT(2)
+#define BQ25792_REG2F_TDIE_ADC_DIS BIT(1)
+
+/* ADC Function Disable 1 */
+#define BQ25792_REG30_DP_ADC_DIS BIT(7)
+#define BQ25792_REG30_DM_ADC_DIS BIT(6)
+#define BQ25792_REG30_VAC2_ADC_DIS BIT(5)
+#define BQ25792_REG30_VAC1_ADC_DIS BIT(4)
+
+/* 0x31-0x45: ADC result registers (16-bit, RO): single full-width field */
+
+#define BQ25792_ADCVSYSVBAT_STEP_UV 1000
+#define BQ25792_ADCIBAT_STEP_UA 1000
+
+/* DPDM Driver */
+#define BQ25792_REG47_DPLUS_DAC_MASK GENMASK(7, 5)
+#define BQ25792_REG47_DMINUS_DAC_MASK GENMASK(4, 2)
+
+/* Part Information */
+#define BQ25792_REG48_PN_MASK GENMASK(5, 3)
+#define BQ25792_REG48_DEV_REV_MASK GENMASK(2, 0)
+
+enum bq257xx_type {
+ BQ25703A = 1,
+ BQ25792,
+};
+
struct bq257xx_device {
struct i2c_client *client;
struct regmap *regmap;
+ enum bq257xx_type type;
};
--
2.52.0
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