* Re: [PATCH v3 1/3] dt-bindings: soc: renesas: Document MFIS IP core
From: Krzysztof Kozlowski @ 2026-04-01 6:43 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-renesas-soc, Krzysztof Kozlowski, Marek Vasut,
Geert Uytterhoeven, Magnus Damm, Rob Herring, Conor Dooley,
devicetree
In-Reply-To: <20260331104527.29170-2-wsa+renesas@sang-engineering.com>
On Tue, Mar 31, 2026 at 12:45:23PM +0200, Wolfram Sang wrote:
> Document the Renesas Multifunctional Interface (MFIS) as found on the
> Renesas R-Car X5H (r8a78000) SoC. MFIS includes features like Mailbox/HW
> Spinlock/Product Register/Error Injection/Error Detection and the likes.
> Family-compatible values are not introduced here because MFIS is usually
> very different per SoC.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
> Changes since v2:
> * added interrupt constraints
> * fixed whitespaces in example (Thanks, Krzysztof, for both!)
>
> .../soc/renesas/renesas,r8a78000-mfis.yaml | 191 ++++++++++++++++++
> .../dt-bindings/soc/renesas,r8a78000-mfis.h | 28 +++
> 2 files changed, 219 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml
> create mode 100644 include/dt-bindings/soc/renesas,r8a78000-mfis.h
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree
From: Troy Mitchell @ 2026-04-01 6:42 UTC (permalink / raw)
To: 曹珊珊, Yixun Lan
Cc: Conor Dooley, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Heinrich Schuchardt, Troy Mitchell, Michael Opdenacker,
Guodong Xu, Hendrik Hamerlinck, Yangyu Chen, spacemit,
linux-riscv, devicetree, linux-kernel
In-Reply-To: <407ce3d77416bb2522b7906b0df3d5adf02c27ee.4c756029.b64e.488e.905e.99baaf78d6a1@feishu.cn>
On Wed Apr 1, 2026 at 2:10 PM CST, 曹珊珊 wrote:
> Hi Lan,
>
>> From: "Yixun Lan"<dlan@kernel.org>
>> Hi Sandie,
>>
>> On 11:46 Tue 31 Mar , Sandie Cao wrote:
>> > From: sandiecao <sandie.cao@deepcomputing.io>
>> >
>> > The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
>> > SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
>> > which has (Framework) SKU FRANHQ0001.
>> >
>> > The FML13V05 board features:
>> > - SpacemiT K3 RISC-V SoC
>> > - LPDDR5 16GB or 32GB
>> > - eMMC 32GB ~128GB (Optional)
>> > - UFS 3.1 256G (Optional)
>> > - QSPI Flash
>> > - MicroSD Slot
>> > - PCIe-based Wi-Fi
>> > - 4 USB-C Ports
>> > - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
>> > - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
>> > - Port 3 & 4: USB 3.2 Gen 1
>> >
>> > This minimal device tree enables booting into a serial console with UART
>> > output.
>> >
>> > Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
>> > Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
>> > +&uart0 {
>> Can you also add pinctrl data explicitly?
>
> To avoid conflict, the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit.
> Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch.
> Sandie
I think you don't understand what Yixun said.
You should add pinctrl properties here like:
pinctrl-0 = xxx;
pinctrl-names = "default";
While the bootloader is expected to initialize the UART pins, explicitly adding the pinctrl properties
ensures hardware state consistency.
- Troy
^ permalink raw reply
* Re: [PATCH v3 1/5] dt-bindings: dmaengine: Add SpacemiT K3 DMA compatible string
From: Krzysztof Kozlowski @ 2026-04-01 6:42 UTC (permalink / raw)
To: Troy Mitchell
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Guodong Xu, Michael Turquette,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, dmaengine, devicetree, linux-riscv, spacemit,
linux-kernel, linux-clk
In-Reply-To: <20260331-k3-pdma-v3-1-a4e60dd8b4b3@linux.spacemit.com>
On Tue, Mar 31, 2026 at 04:27:04PM +0800, Troy Mitchell wrote:
> From: Guodong Xu <guodong@riscstar.com>
>
> Add the "spacemit,k3-pdma" compatible string for the SpacemiT K3 SoC.
>
> While the K3 PDMA IP reuses most of the design found on the earlier K1 SoC,
> a new compatible string is required due to the following hardware differences:
Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597
>
> - Variable extended DRCMR base: The DRCMR (DMA Request/Command Register) base
> address for extended DMA request numbers (>= 64) differs from the K1
> implementation, requiring different driver ops.
Please do not mention drivers.
> - Memory addressing capabilities: Unlike the K1 SoC, which had memory addressing
> limitations (e.g., restricted to the 0-4GB space) and required a dedicated
> dma-bus with dma-ranges to restrict memory allocations, the K3 DMA masters
> possess full memory addressing capabilities.
Programming interface is still compatible, regardless of memory
addressing limitations, so that is rather incorrect reason.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 1/7] dt-bindings: clock: qcom: Add X1P42100 video clock controller
From: Krzysztof Kozlowski @ 2026-04-01 6:40 UTC (permalink / raw)
To: Jagadeesh Kona
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jagadeesh Kona,
Bryan O'Donoghue, Konrad Dybcio, Ajit Pandey, Imran Shaik,
Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
In-Reply-To: <20260331-purwa-videocc-camcc-v3-1-6daca180a4b1@oss.qualcomm.com>
On Tue, Mar 31, 2026 at 10:54:10AM +0530, Jagadeesh Kona wrote:
> Add device tree bindings for the video clock controller on Qualcomm
> X1P42100 (Purwa) SoC.
>
> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
> ---
> .../bindings/clock/qcom,sm8450-videocc.yaml | 3 ++
> include/dt-bindings/clock/qcom,x1p42100-videocc.h | 48 ++++++++++++++++++++++
> 2 files changed, 51 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH] arm64: dts: imx8x-colibri: Correct SODIMM PAD settings
From: Peng Fan (OSS) @ 2026-04-01 6:40 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Philippe Schenker, Ernest Van Hoecke
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
SION is BIT(30), not BIT(26). Correct it.
Fixes: 7ece3cbc8b1ef ("arm64: dts: colibri-imx8x: Add atmel pinctrl groups")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 47895ff8cb244e9bbebe228eb554c2b3f0dded1d..2415487d3a5dea92f9084cd1b312a07f6a09f3cf 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -631,12 +631,12 @@ pinctrl_adc0: adc0grp {
*/
pinctrl_atmel_adap: atmeladaptergrp {
fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x21>, /* SODIMM 30 */
- <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x4000021>; /* SODIMM 28 */
+ <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x40000021>; /* SODIMM 28 */
};
/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
pinctrl_atmel_conn: atmelconnectorgrp {
- fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x4000021>, /* SODIMM 107 */
+ fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x40000021>, /* SODIMM 107 */
<IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21>; /* SODIMM 106 */
};
---
base-commit: 36ece9697e89016181e5ae87510e40fb31d86f2b
change-id: 20260401-imx8-fix-10369e895b8a
Best regards,
--
Peng Fan <peng.fan@nxp.com>
^ permalink raw reply related
* Re: [PATCH v5 2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0
From: Krzysztof Kozlowski @ 2026-04-01 6:36 UTC (permalink / raw)
To: Billy Tsai
Cc: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery, Linus Walleij, Bartosz Golaszewski,
Ryan Chen, Andrew Jeffery, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc, linux-gpio, linux-clk
In-Reply-To: <20260331-upstream_pinctrl-v5-2-8994f59ff367@aspeedtech.com>
On Tue, Mar 31, 2026 at 03:31:17PM +0800, Billy Tsai wrote:
> AST2700 consists of two interconnected SoC instances, each with its own
> System Control Unit (SCU). The SCU0 provides pin control, interrupt
> controllers, clocks, resets, and address-space mappings for the
> Secondary and Tertiary Service Processors (SSP and TSP).
>
> Describe the SSP/TSP address mappings using the standard
> memory-region and memory-region-names properties.
>
> Disallow legacy child nodes that are not present on AST2700, including
> p2a-control and smp-memram. The latter is unnecessary as software can
> access the scratch registers via the SCU syscon.
>
> Also allow the AST2700 SoC0 pin controller to be described as a child
> node of the SCU0, and add an example illustrating the SCU0 layout,
> including reserved-memory, interrupt controllers, and pinctrl.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
> .../bindings/mfd/aspeed,ast2x00-scu.yaml | 117 +++++++++++++++++++++
> 1 file changed, 117 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> index a87f31fce019..86d51389689c 100644
> --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> @@ -46,6 +46,9 @@ properties:
> '#reset-cells':
> const: 1
>
> + memory-region: true
> + memory-region-names: true
Missing constraints. From where did you take such syntax (so I can fix
it)?
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH RFC 4/4] arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR
From: Qiang Yu @ 2026-04-01 6:35 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Konrad Dybcio,
johan
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, Qiang Yu
In-Reply-To: <20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com>
The TCSR clkref clocks gate the QREF block which provides reference
clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF
and refgen blocks on the CRD board:
- vdda-refgen_0p9/1p2: LDOs for the refgen block that generates the
reference voltage for QREF
- vdda-qrefrx/tx/rpt: LDOs for the QREF receiver, transmitter
and repeater circuits
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index 51ea23a49b9e66f14d08dcff777789d16647fd17..3ca181d082ebbbc4d4778abc853c39deaa2a76e6 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -342,6 +342,25 @@ &usb_1 {
status = "okay";
};
+&tcsr {
+ vdda-refgen-0p9-supply = <&vreg_l1f_e1_0p82>;
+ vdda-refgen-1p2-supply = <&vreg_l4f_e1_1p08>;
+
+ vdda-qrefrx5-0p9-supply = <&vreg_l3f_e0_0p72>;
+ vdda-qreftx0-0p9-supply = <&vreg_l3f_e0_0p72>;
+ vdda-qreftx0-1p2-supply = <&vreg_l4h_e0_1p2>;
+ vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrpt3-0p9-supply = <&vreg_l2h_e0_0p72>;
+ vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0_0p72>;
+ vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrx4-0p9-supply = <&vreg_l2h_e0_0p72>;
+ vdda-qreftx1-0p9-supply = <&vreg_l1f_e1_0p82>;
+};
+
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in1>;
};
--
2.34.1
^ permalink raw reply related
* [PATCH RFC 3/4] clk: qcom: tcsrcc-glymur: Migrate tcsr_pcie_N_clkref_en to clk_ref common helper
From: Qiang Yu @ 2026-04-01 6:35 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Konrad Dybcio,
johan
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, Qiang Yu
In-Reply-To: <20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com>
Replace local clk_branch-based clkref definitions with descriptor-based
registration via qcom_clk_ref_probe().
This keeps the glymur driver focused on clock metadata and reuses common
runtime logic for regulator handling, enable/disable sequencing, and OF
provider wiring.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
---
drivers/clk/qcom/tcsrcc-glymur.c | 340 +++++++++++----------------------------
1 file changed, 93 insertions(+), 247 deletions(-)
diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c
index 9c0edebcdbb12816d1be5249e4f04bcaf02048aa..585f87b23af2d92daef1787b2f38911681c0d8ee 100644
--- a/drivers/clk/qcom/tcsrcc-glymur.c
+++ b/drivers/clk/qcom/tcsrcc-glymur.c
@@ -4,265 +4,115 @@
*/
#include <linux/clk-provider.h>
+#include <linux/clk/qcom.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,glymur-tcsr.h>
-#include "clk-alpha-pll.h"
-#include "clk-branch.h"
-#include "clk-pll.h"
-#include "clk-rcg.h"
-#include "clk-regmap.h"
-#include "clk-regmap-divider.h"
-#include "clk-regmap-mux.h"
-#include "common.h"
-#include "gdsc.h"
-#include "reset.h"
-
-enum {
- DT_BI_TCXO_PAD,
-};
-
-static struct clk_branch tcsr_edp_clkref_en = {
- .halt_reg = 0x60,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x60,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_edp_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+static const char * const tcsr_pcie_1_regulators[] = {
+ "vdda-refgen-0p9",
+ "vdda-refgen-1p2",
+ "vdda-qrefrx5-0p9",
+ "vdda-qreftx0-0p9",
+ "vdda-qreftx0-1p2",
+};
+
+static const char * const tcsr_pcie_2_regulators[] = {
+ "vdda-refgen-0p9",
+ "vdda-refgen-1p2",
+ "vdda-qreftx1-0p9",
+ "vdda-qrefrpt0-0p9",
+ "vdda-qrefrpt1-0p9",
+ "vdda-qrefrpt2-0p9",
+ "vdda-qrefrx2-0p9",
+};
+
+static const char * const tcsr_pcie_3_regulators[] = {
+ "vdda-refgen-0p9",
+ "vdda-refgen-1p2",
+ "vdda-qreftx1-0p9",
+ "vdda-qrefrpt0-0p9",
+ "vdda-qrefrpt1-0p9",
+ "vdda-qrefrx1-0p9",
+};
+
+static const char * const tcsr_pcie_4_regulators[] = {
+ "vdda-refgen-0p9",
+ "vdda-refgen-1p2",
+ "vdda-qreftx1-0p9",
+ "vdda-qrefrpt0-0p9",
+ "vdda-qrefrpt1-0p9",
+ "vdda-qrefrpt2-0p9",
+ "vdda-qrefrx2-0p9",
+};
+
+static const struct qcom_clk_ref_desc tcsr_cc_glymur_clk_descs[] = {
+ [TCSR_EDP_CLKREF_EN] = {
+ .name = "tcsr_edp_clkref_en",
+ .offset = 0x60,
},
-};
-
-static struct clk_branch tcsr_pcie_1_clkref_en = {
- .halt_reg = 0x48,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x48,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_pcie_1_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_PCIE_1_CLKREF_EN] = {
+ .name = "tcsr_pcie_1_clkref_en",
+ .offset = 0x48,
+ .regulator_names = tcsr_pcie_1_regulators,
+ .num_regulators = ARRAY_SIZE(tcsr_pcie_1_regulators),
},
-};
-
-static struct clk_branch tcsr_pcie_2_clkref_en = {
- .halt_reg = 0x4c,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x4c,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_pcie_2_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_PCIE_2_CLKREF_EN] = {
+ .name = "tcsr_pcie_2_clkref_en",
+ .offset = 0x4c,
+ .regulator_names = tcsr_pcie_2_regulators,
+ .num_regulators = ARRAY_SIZE(tcsr_pcie_2_regulators),
},
-};
-
-static struct clk_branch tcsr_pcie_3_clkref_en = {
- .halt_reg = 0x54,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x54,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_pcie_3_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_PCIE_3_CLKREF_EN] = {
+ .name = "tcsr_pcie_3_clkref_en",
+ .offset = 0x54,
+ .regulator_names = tcsr_pcie_3_regulators,
+ .num_regulators = ARRAY_SIZE(tcsr_pcie_3_regulators),
},
-};
-
-static struct clk_branch tcsr_pcie_4_clkref_en = {
- .halt_reg = 0x58,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x58,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_pcie_4_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_PCIE_4_CLKREF_EN] = {
+ .name = "tcsr_pcie_4_clkref_en",
+ .offset = 0x58,
+ .regulator_names = tcsr_pcie_4_regulators,
+ .num_regulators = ARRAY_SIZE(tcsr_pcie_4_regulators),
},
-};
-
-static struct clk_branch tcsr_usb2_1_clkref_en = {
- .halt_reg = 0x6c,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x6c,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_usb2_1_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_USB2_1_CLKREF_EN] = {
+ .name = "tcsr_usb2_1_clkref_en",
+ .offset = 0x6c,
},
-};
-
-static struct clk_branch tcsr_usb2_2_clkref_en = {
- .halt_reg = 0x70,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x70,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_usb2_2_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_USB2_2_CLKREF_EN] = {
+ .name = "tcsr_usb2_2_clkref_en",
+ .offset = 0x70,
},
-};
-
-static struct clk_branch tcsr_usb2_3_clkref_en = {
- .halt_reg = 0x74,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x74,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_usb2_3_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_USB2_3_CLKREF_EN] = {
+ .name = "tcsr_usb2_3_clkref_en",
+ .offset = 0x74,
},
-};
-
-static struct clk_branch tcsr_usb2_4_clkref_en = {
- .halt_reg = 0x88,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x88,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_usb2_4_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_USB2_4_CLKREF_EN] = {
+ .name = "tcsr_usb2_4_clkref_en",
+ .offset = 0x88,
},
-};
-
-static struct clk_branch tcsr_usb3_0_clkref_en = {
- .halt_reg = 0x64,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x64,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_usb3_0_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_USB3_0_CLKREF_EN] = {
+ .name = "tcsr_usb3_0_clkref_en",
+ .offset = 0x64,
},
-};
-
-static struct clk_branch tcsr_usb3_1_clkref_en = {
- .halt_reg = 0x68,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x68,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_usb3_1_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_USB3_1_CLKREF_EN] = {
+ .name = "tcsr_usb3_1_clkref_en",
+ .offset = 0x68,
},
-};
-
-static struct clk_branch tcsr_usb4_1_clkref_en = {
- .halt_reg = 0x44,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x44,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_usb4_1_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_USB4_1_CLKREF_EN] = {
+ .name = "tcsr_usb4_1_clkref_en",
+ .offset = 0x44,
},
-};
-
-static struct clk_branch tcsr_usb4_2_clkref_en = {
- .halt_reg = 0x5c,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x5c,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "tcsr_usb4_2_clkref_en",
- .parent_data = &(const struct clk_parent_data){
- .index = DT_BI_TCXO_PAD,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
+ [TCSR_USB4_2_CLKREF_EN] = {
+ .name = "tcsr_usb4_2_clkref_en",
+ .offset = 0x5c,
},
};
-static struct clk_regmap *tcsr_cc_glymur_clocks[] = {
- [TCSR_EDP_CLKREF_EN] = &tcsr_edp_clkref_en.clkr,
- [TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr,
- [TCSR_PCIE_2_CLKREF_EN] = &tcsr_pcie_2_clkref_en.clkr,
- [TCSR_PCIE_3_CLKREF_EN] = &tcsr_pcie_3_clkref_en.clkr,
- [TCSR_PCIE_4_CLKREF_EN] = &tcsr_pcie_4_clkref_en.clkr,
- [TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr,
- [TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr,
- [TCSR_USB2_3_CLKREF_EN] = &tcsr_usb2_3_clkref_en.clkr,
- [TCSR_USB2_4_CLKREF_EN] = &tcsr_usb2_4_clkref_en.clkr,
- [TCSR_USB3_0_CLKREF_EN] = &tcsr_usb3_0_clkref_en.clkr,
- [TCSR_USB3_1_CLKREF_EN] = &tcsr_usb3_1_clkref_en.clkr,
- [TCSR_USB4_1_CLKREF_EN] = &tcsr_usb4_1_clkref_en.clkr,
- [TCSR_USB4_2_CLKREF_EN] = &tcsr_usb4_2_clkref_en.clkr,
-};
-
static const struct regmap_config tcsr_cc_glymur_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -271,11 +121,12 @@ static const struct regmap_config tcsr_cc_glymur_regmap_config = {
.fast_io = true,
};
-static const struct qcom_cc_desc tcsr_cc_glymur_desc = {
- .config = &tcsr_cc_glymur_regmap_config,
- .clks = tcsr_cc_glymur_clocks,
- .num_clks = ARRAY_SIZE(tcsr_cc_glymur_clocks),
-};
+static int tcsr_cc_glymur_probe(struct platform_device *pdev)
+{
+ return qcom_clk_ref_probe(pdev, &tcsr_cc_glymur_regmap_config,
+ tcsr_cc_glymur_clk_descs,
+ ARRAY_SIZE(tcsr_cc_glymur_clk_descs));
+}
static const struct of_device_id tcsr_cc_glymur_match_table[] = {
{ .compatible = "qcom,glymur-tcsr" },
@@ -283,11 +134,6 @@ static const struct of_device_id tcsr_cc_glymur_match_table[] = {
};
MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table);
-static int tcsr_cc_glymur_probe(struct platform_device *pdev)
-{
- return qcom_cc_probe(pdev, &tcsr_cc_glymur_desc);
-}
-
static struct platform_driver tcsr_cc_glymur_driver = {
.probe = tcsr_cc_glymur_probe,
.driver = {
--
2.34.1
^ permalink raw reply related
* [PATCH RFC 2/4] clk: qcom: Add generic clkref_en support
From: Qiang Yu @ 2026-04-01 6:35 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Konrad Dybcio,
johan
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, Qiang Yu
In-Reply-To: <20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com>
Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through
a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en
register controls whether refclk is gated through to the PHY side.
These clkref controls are different from typical GCC branch clocks:
- only a single enable bit is present, without branch-style config bits
- regulators must be voted before enable and unvoted after disable
Model this as a dedicated clk_ref clock type with custom clk_ops instead
of reusing struct clk_branch semantics.
Also provide a common registration/probe API so the same clkref model
can be reused regardless of where clkref_en registers are placed, e.g.
TCSR on glymur and TLMM on SM8750.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
---
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-ref.c | 202 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/qcom.h | 69 ++++++++++++++++
3 files changed, 272 insertions(+)
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index b818fd5af8bfb85a51ee90fdc3baa93af30dc39a..c5effc18efd80dd6c25a5398d723cec0f66fe0e6 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -8,6 +8,7 @@ clk-qcom-y += clk-pll.o
clk-qcom-y += clk-rcg.o
clk-qcom-y += clk-rcg2.o
clk-qcom-y += clk-branch.o
+clk-qcom-y += clk-ref.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
clk-qcom-y += clk-regmap-mux-div.o
diff --git a/drivers/clk/qcom/clk-ref.c b/drivers/clk/qcom/clk-ref.c
new file mode 100644
index 0000000000000000000000000000000000000000..ea2ed03460f28c6dae089e19cc07a5697b9f3d35
--- /dev/null
+++ b/drivers/clk/qcom/clk-ref.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk/qcom.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+
+#define QCOM_CLK_REF_EN_MASK BIT(0)
+
+struct qcom_clk_ref_provider {
+ struct qcom_clk_ref *refs;
+ size_t num_refs;
+};
+
+static inline struct qcom_clk_ref *to_qcom_clk_ref(struct clk_hw *hw)
+{
+ return container_of(hw, struct qcom_clk_ref, hw);
+}
+
+static const struct clk_parent_data qcom_clk_ref_parent_data = {
+ .index = 0,
+};
+
+static int qcom_clk_ref_prepare(struct clk_hw *hw)
+{
+ struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
+ int ret;
+
+ if (!rclk->desc.num_regulators)
+ return 0;
+
+ ret = regulator_bulk_enable(rclk->desc.num_regulators, rclk->regulators);
+ if (ret)
+ pr_err("Failed to enable regulators for %s: %d\n",
+ clk_hw_get_name(hw), ret);
+
+ return ret;
+}
+
+static void qcom_clk_ref_unprepare(struct clk_hw *hw)
+{
+ struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
+
+ if (rclk->desc.num_regulators)
+ regulator_bulk_disable(rclk->desc.num_regulators, rclk->regulators);
+}
+
+static int qcom_clk_ref_enable(struct clk_hw *hw)
+{
+ struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
+ int ret;
+
+ ret = regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK,
+ QCOM_CLK_REF_EN_MASK);
+ if (ret)
+ return ret;
+
+ udelay(10);
+
+ return 0;
+}
+
+static void qcom_clk_ref_disable(struct clk_hw *hw)
+{
+ struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
+
+ regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK, 0);
+ udelay(10);
+}
+
+static int qcom_clk_ref_is_enabled(struct clk_hw *hw)
+{
+ struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
+ u32 val;
+ int ret;
+
+ ret = regmap_read(rclk->regmap, rclk->desc.offset, &val);
+ if (ret)
+ return ret;
+
+ return !!(val & QCOM_CLK_REF_EN_MASK);
+}
+
+static const struct clk_ops qcom_clk_ref_ops = {
+ .prepare = qcom_clk_ref_prepare,
+ .unprepare = qcom_clk_ref_unprepare,
+ .enable = qcom_clk_ref_enable,
+ .disable = qcom_clk_ref_disable,
+ .is_enabled = qcom_clk_ref_is_enabled,
+};
+
+static int qcom_clk_ref_register(struct device *dev, struct regmap *regmap,
+ struct qcom_clk_ref *clk_refs,
+ const struct qcom_clk_ref_desc *descs,
+ size_t num_clk_refs)
+{
+ const struct qcom_clk_ref_desc *desc;
+ struct qcom_clk_ref *clk_ref;
+ size_t clk_idx;
+ unsigned int i;
+ int ret;
+
+ for (clk_idx = 0; clk_idx < num_clk_refs; clk_idx++) {
+ clk_ref = &clk_refs[clk_idx];
+ desc = &descs[clk_idx];
+
+ if (!desc->name)
+ return -EINVAL;
+
+ clk_ref->regmap = regmap;
+ clk_ref->desc = *desc;
+
+ if (clk_ref->desc.num_regulators) {
+ clk_ref->regulators = devm_kcalloc(dev, clk_ref->desc.num_regulators,
+ sizeof(*clk_ref->regulators),
+ GFP_KERNEL);
+ if (!clk_ref->regulators)
+ return -ENOMEM;
+
+ for (i = 0; i < clk_ref->desc.num_regulators; i++)
+ clk_ref->regulators[i].supply =
+ clk_ref->desc.regulator_names[i];
+
+ ret = devm_regulator_bulk_get(dev, clk_ref->desc.num_regulators,
+ clk_ref->regulators);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to get regulators for %s\n",
+ clk_ref->desc.name);
+ }
+
+ clk_ref->init_data.name = clk_ref->desc.name;
+ clk_ref->init_data.parent_data = &qcom_clk_ref_parent_data;
+ clk_ref->init_data.num_parents = 1;
+ clk_ref->init_data.ops = &qcom_clk_ref_ops;
+ clk_ref->hw.init = &clk_ref->init_data;
+
+ ret = devm_clk_hw_register(dev, &clk_ref->hw);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct clk_hw *qcom_clk_ref_provider_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct qcom_clk_ref_provider *provider = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= provider->num_refs)
+ return ERR_PTR(-EINVAL);
+
+ return &provider->refs[idx].hw;
+}
+
+int qcom_clk_ref_probe(struct platform_device *pdev,
+ const struct regmap_config *config,
+ const struct qcom_clk_ref_desc *descs,
+ size_t num_clk_refs)
+{
+ struct qcom_clk_ref_provider *provider;
+ struct device *dev = &pdev->dev;
+ struct regmap *regmap;
+ void __iomem *base;
+ int ret;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(dev, base, config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
+ if (!provider)
+ return -ENOMEM;
+
+ provider->refs = devm_kcalloc(dev, num_clk_refs, sizeof(*provider->refs),
+ GFP_KERNEL);
+ if (!provider->refs)
+ return -ENOMEM;
+
+ provider->num_refs = num_clk_refs;
+
+ ret = qcom_clk_ref_register(dev, regmap, provider->refs, descs,
+ provider->num_refs);
+ if (ret)
+ return ret;
+
+ return devm_of_clk_add_hw_provider(dev, qcom_clk_ref_provider_get, provider);
+}
+EXPORT_SYMBOL_GPL(qcom_clk_ref_probe);
diff --git a/include/linux/clk/qcom.h b/include/linux/clk/qcom.h
new file mode 100644
index 0000000000000000000000000000000000000000..1066ef46ac21e9db1f3440faf81ba52afdf1faf2
--- /dev/null
+++ b/include/linux/clk/qcom.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __LINUX_CLK_QCOM_H
+#define __LINUX_CLK_QCOM_H
+
+#include <linux/clk-provider.h>
+#include <linux/errno.h>
+#include <linux/kconfig.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+struct device;
+struct platform_device;
+struct regulator_bulk_data;
+
+/**
+ * struct qcom_clk_ref_desc - description of a simple XO reference gate
+ * @name: clock name
+ * @offset: register offset
+ * @regulator_names: optional per-clock regulator names
+ * @num_regulators: number of entries in @regulator_names
+ */
+struct qcom_clk_ref_desc {
+ const char *name;
+ u32 offset;
+ const char * const *regulator_names;
+ unsigned int num_regulators;
+};
+
+/**
+ * struct qcom_clk_ref - runtime state for a qcom reference gate
+ * @hw: clock hardware handle
+ * @init_data: clock init data
+ * @regmap: register map backing the gate register
+ * @desc: clock descriptor copied at registration
+ * @regulators: optional regulator handles
+ */
+struct qcom_clk_ref {
+ struct clk_hw hw;
+ struct clk_init_data init_data;
+ struct regmap *regmap;
+ struct qcom_clk_ref_desc desc;
+ struct regulator_bulk_data *regulators;
+};
+
+#if IS_ENABLED(CONFIG_COMMON_CLK_QCOM)
+
+int qcom_clk_ref_probe(struct platform_device *pdev,
+ const struct regmap_config *config,
+ const struct qcom_clk_ref_desc *descs,
+ size_t num_clk_refs);
+
+#else
+
+static inline int
+qcom_clk_ref_probe(struct platform_device *pdev,
+ const struct regmap_config *config,
+ const struct qcom_clk_ref_desc *descs,
+ size_t num_clk_refs)
+{
+ return -EOPNOTSUPP;
+}
+
+#endif
+
+#endif
--
2.34.1
^ permalink raw reply related
* [PATCH RFC 0/4] clk: qcom: Add common clkref support and migrate Glymur
From: Qiang Yu @ 2026-04-01 6:35 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Konrad Dybcio,
johan
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, Qiang Yu
This series adds a common clkref_en implementation and converts glymur to
use it, along with the related binding and DTS updates.
The PCIe clkref clocks on Glymur gate the QREF block which provides
reference clocks to the PCIe PHYs. QREF requires LDO supplies and a
reference voltage from the refgen block to operate. The refgen block
itself requires vdda-refgen_0p9 and vdda-refgen_1p2 LDOs to function.
Previously, these QREF votes were done in PHY drivers. In earlier
discussion [1], the feedback was that this is the wrong ownership point:
those supplies are for the QREF controlled by clkref registers, not for
PHY directly. Based on that feedback, this series keeps the regulator
handling with the clkref control path.
Another reason for this series is reuse. clkref_en registers may live in
different blocks across platforms (for example TCSR on Glymur, TLMM on
SM8750 [2]), while the behavior is the same. The common helper lets each
driver provide simple descriptors (name, offset, optional supplies) and
reuse shared registration and runtime logic.
[1] https://lore.kernel.org/lkml/aEBfV2M-ZqDF7aRz@hovoldconsulting.com/
[2] https://lore.kernel.org/linux-arm-msm/20260202-topic-8750_tcsr-v1-0-cd7e6648c64f@oss.qualcomm.com/
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
---
Qiang Yu (4):
dt-bindings: clock: qcom,sm8550-tcsr: Add QREF regulator supplies for glymur
clk: qcom: Add generic clkref_en support
clk: qcom: tcsrcc-glymur: Migrate tcsr_pcie_N_clkref_en to clk_ref common helper
arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR
.../bindings/clock/qcom,sm8550-tcsr.yaml | 26 +-
arch/arm64/boot/dts/qcom/glymur-crd.dts | 19 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-ref.c | 202 ++++++++++++
drivers/clk/qcom/tcsrcc-glymur.c | 340 ++++++---------------
include/linux/clk/qcom.h | 69 +++++
6 files changed, 409 insertions(+), 248 deletions(-)
---
base-commit: 36ece9697e89016181e5ae87510e40fb31d86f2b
change-id: 20260331-qref_vote-3f38b46d5847
Best regards,
--
Qiang Yu <qiang.yu@oss.qualcomm.com>
^ permalink raw reply
* [PATCH RFC 1/4] dt-bindings: clock: qcom,sm8550-tcsr: Add QREF regulator supplies for glymur
From: Qiang Yu @ 2026-04-01 6:35 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Konrad Dybcio,
johan
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, Qiang Yu
In-Reply-To: <20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com>
The glymur TCSR PCIe clkref clocks require regulator supplies for the
QREF block and its refgen reference voltage generator. Add the optional
supply properties restricted to qcom,glymur-tcsr via an allOf/if/then
conditional schema.
Switch from additionalProperties to unevaluatedProperties so that
properties defined inside the if/then block are correctly recognised as
evaluated and not rejected by the schema validator.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
---
.../bindings/clock/qcom,sm8550-tcsr.yaml | 26 +++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
index ae9aef0e54e8b8b85bc70e6096d524447091f39e..88db650e69ef2388a5bfb6783a57c1d48c0e780f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
@@ -49,11 +49,35 @@ properties:
'#reset-cells':
const: 1
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,glymur-tcsr
+ then:
+ properties:
+ vdda-refgen-0p9-supply: true
+ vdda-refgen-1p2-supply: true
+ vdda-qrefrx0-0p9-supply: true
+ vdda-qrefrx1-0p9-supply: true
+ vdda-qrefrx2-0p9-supply: true
+ vdda-qrefrx4-0p9-supply: true
+ vdda-qrefrx5-0p9-supply: true
+ vdda-qreftx0-0p9-supply: true
+ vdda-qreftx0-1p2-supply: true
+ vdda-qreftx1-0p9-supply: true
+ vdda-qrefrpt0-0p9-supply: true
+ vdda-qrefrpt1-0p9-supply: true
+ vdda-qrefrpt2-0p9-supply: true
+ vdda-qrefrpt3-0p9-supply: true
+ vdda-qrefrpt4-0p9-supply: true
+
required:
- compatible
- clocks
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree
From: 曹珊珊 @ 2026-04-01 6:10 UTC (permalink / raw)
To: Yixun Lan
Cc: Conor Dooley, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Heinrich Schuchardt, Troy Mitchell, Michael Opdenacker,
Guodong Xu, Hendrik Hamerlinck, Yangyu Chen, spacemit,
linux-riscv, devicetree, linux-kernel
In-Reply-To: <20260331085925-GKB976850@kernel.org>
Hi Lan,
> From: "Yixun Lan"<dlan@kernel.org>
> Hi Sandie,
>
> On 11:46 Tue 31 Mar , Sandie Cao wrote:
> > From: sandiecao <sandie.cao@deepcomputing.io>
> >
> > The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
> > SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
> > which has (Framework) SKU FRANHQ0001.
> >
> > The FML13V05 board features:
> > - SpacemiT K3 RISC-V SoC
> > - LPDDR5 16GB or 32GB
> > - eMMC 32GB ~128GB (Optional)
> > - UFS 3.1 256G (Optional)
> > - QSPI Flash
> > - MicroSD Slot
> > - PCIe-based Wi-Fi
> > - 4 USB-C Ports
> > - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
> > - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
> > - Port 3 & 4: USB 3.2 Gen 1
> >
> > This minimal device tree enables booting into a serial console with UART
> > output.
> >
> > Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
> > Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> should put your own signed-off at the end.
>
> > ---
> > arch/riscv/boot/dts/spacemit/Makefile | 1 +
> > .../spacemit/k3-deepcomputing-fml13v05.dts | 28 +++++++++++++++++++
> > 2 files changed, 29 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
> > index 7e2b87702571..acb993c452ba 100644
> > --- a/arch/riscv/boot/dts/spacemit/Makefile
> > +++ b/arch/riscv/boot/dts/spacemit/Makefile
> > @@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
> > dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
> > dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
> > dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
> > +dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb
> > dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
> > diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
> > new file mode 100644
> > index 000000000000..2343ae3acc2d
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
> > @@ -0,0 +1,28 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2024 DeepComputing (HK) Limited
> should cover current year, which is 2026 now..
>
> > + */
> > +
> > +#include "k3.dtsi"
> > +
> > +/ {
> > + model = "DeepComputing FML13V05";
> > + compatible = "deepcomputing,fml13v05", "spacemit,k3";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0";
> > + };
> > +
> > + memory@100000000 {
> > + device_type = "memory";
> > + reg = <0x1 0x00000000 0x4 0x00000000>;
> > + };
> > +};
> > +
> > +&uart0 {
> Can you also add pinctrl data explicitly?
To avoid conflict, the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit.
Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch.
Sandie
>
> > + status = "okay";
> > +};
> > --
> > 2.43.0
>
> --
> Yixun Lan (dlan)
>
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: qcom: agatti: enable FastRPC on the ADSP
From: Ekansh Gupta @ 2026-04-01 5:59 UTC (permalink / raw)
To: Konrad Dybcio, Sumit Garg, Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <3447efbf-2720-4c9f-9a74-ca9baafa96ad@oss.qualcomm.com>
On 3/30/2026 4:07 PM, Konrad Dybcio wrote:
> On 3/30/26 6:54 AM, Sumit Garg wrote:
>> On Tue, Jan 13, 2026 at 06:41:59PM +0200, Dmitry Baryshkov wrote:
>>> On Agatti platform the ADSP provides FastRPC support. Add corresponding
>>> device node, in order to be able to utilize the DSP offload from the
>>> Linux side.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>>> ---
>>> Changes in v2:
>>> - Add more FastRPC context banks (6, 7)
>>> - Link to v1: https://lore.kernel.org/r/20260113-agatti-fastrpc-v1-1-e210903ffcb1@oss.qualcomm.com
>>> ---
>>> arch/arm64/boot/dts/qcom/agatti.dtsi | 41 ++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 41 insertions(+)
>>>
>> This patch causes a critical boot regression on RB1 as per the CI test
>> report here [1]. I see this change already landed in this merge window.
>> So, either this commit has to be reverted for v7.0 release or an
>> appropriate fix is required.
>>
>> [1] https://github.com/qualcomm-linux/kernel/issues/359
> Why has that issue been opened 2 weeks ago with no action since?
>
> FWIW, copying the broader log from the LAVA job:
>
>
> [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
> Starting [0;1;39maDSP RPC daemon[0m...
> Starting [0;1;39maudiopd aDSP RPC daemon[0m...
> Starting [0;1;39mAndroid Debug Bridge[0m...
> Starting [0;1;39mAvahi mDNS/DNS-SD Stack[0m...
> Starting [0;1;39mBluetooth service[0m...
> Starting [0;1;39mD-Bus System Message Bus[0m...
> [ 17.318840] qcom,fastrpc-cb ab00000.remoteproc:glink-edge:fastrpc:compute-cb@4: mem mmap error, fd 11, vaddr ffffae380000, size 262144
> [ 17.327877] qcom_q6v5_pas ab00000.remoteproc: fatal error received: SFR Init: wdog or kernel error suspected.
> [ 17.343248] remoteproc remoteproc1: crash detected in adsp: type fatal error
> [ 17.350567] qcom_q6v5_pas ab00000.remoteproc: Handover signaled, but it already happened
> [ 17.358869] remoteproc remoteproc1: handling crash #1 in adsp
> [ 17.364730] remoteproc remoteproc1: recovering adsp
>
> Format: Log Type - Time(microsec) - Message - Optional Info
> Log Type: B - Since Boot(Power On Reset), D - Delta, S - Statistic
> <ded>
>
> It seems like this only ends up being a problem once the userland
> daemon starting poking at the channel - +Ekansh, have you seen this
> before?
Looks like daemon attaching to PD is causing some DSP privileged PD crash. Checking this crash
now, will update here if I have any findings.
>
> Konrad
>
>
^ permalink raw reply
* Re: [PATCH v9 00/21] media: i2c: add Maxim GMSL2/3 serializer and deserializer drivers
From: Ceclan Dumitru @ 2026-04-01 5:52 UTC (permalink / raw)
To: Dayananda, Vivekananda, dumitru.ceclan@analog.com, Tomi Valkeinen,
Mauro Carvalho Chehab, Sakari Ailus, Laurent Pinchart,
Julien Massot, Rob Herring, Niklas Söderlund,
Greg Kroah-Hartman, Cosmin Tanislav
Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-staging@lists.linux.dev,
linux-gpio@vger.kernel.org, Niklas Söderlund,
martin.hecht@avnet.eu, Tomi Valkeinen, Cosmin Tanislav,
Cory Keitz
In-Reply-To: <MW4PR12MB56682D24FB2D7B1EF2D53B78E853A@MW4PR12MB5668.namprd12.prod.outlook.com>
On 3/31/26 8:43 PM, Dayananda, Vivekananda wrote:
> [Public]
>
> There is one other patch that is required in addition, which enables the remote-control channel links from port 1 using REG3. Adding the patch below
> ----
> From 36936732c6ecd599f1a26744bef3031e41194229 Mon Sep 17 00:00:00 2001
> From: Vivekananda Dayananda <vivekana@amd.com>
> Date: Tue, 31 Mar 2026 08:12:20 -0700
> Subject: [PATCH] media: i2c: maxim-serdes: max96724: allow selecting CC port
>
> Add a DT property that lets platforms choose which control-channel port the MAX96724 exposes to the upstream I2C host. Document the new property for the MAX96724 compatibles and default to port 0 so existing device trees retain their behaviour.
>
> The driver caches the chosen port and reprograms register 0x03 after every reset, restoring control-channel access regardless of whether the deserializer was power-cycled. Boards that need to talk through port 1 can now opt in by setting "maxim,control-channel-port = <1>;" in the device tree.
>
> Signed-off-by: Vivekananda Dayananda <vivekana@amd.com>
> ---
[...]
Thank you, will be included in V10. I'll await first confirmation from
Sakari that the failing v4l2 compliance tests do not make sense for
serdes like I've considered.
^ permalink raw reply
* RE: [PATCH 0/5] ufs-exynos support for ExynosAutov920
From: Alim Akhtar @ 2026-04-01 5:29 UTC (permalink / raw)
To: krzk+dt, robh, krzk, conor+dt, vkoul, kishon
Cc: linux-kernel, devicetree, linux-samsung-soc, 'Sowon Na'
In-Reply-To: <20250702013316.2837427-1-sowon.na@samsung.com>
Hi All
> -----Original Message-----
> From: Sowon Na <sowon.na@samsung.com>
> Sent: Wednesday, July 2, 2025 7:03 AM
> To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> sowon.na@samsung.com
> Subject: [PATCH 0/5] ufs-exynos support for ExynosAutov920
>
> Hi,
>
> This series adds support to the ufs-exynos driver for ExynosAutov920,
> Samsung Automotive SoC series.
> ExynosAutov920 has the UFSHCI 3.1 compliant UFS controller.
>
> ExynosAutov920 has a different mask of UFS sharability from ExynosAutov9,
> so this series provide flexible parameter for the mask.
>
> With this series applied, UFS is functional. The Samsung KLUDG4UHYB is
> tested for enumeration and I/O.
>
> Sowon Na (5):
> phy: samsung-ufs: update calibration settings for EVT2
> dt-bindings: ufs: exynos: add ExynosAutov920 compatible string
> dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920
> scsi: ufs: exynos: add support for ExynosAutov920 SoC
> arm64: dts: exynosautov920: enable support for ufs device
>
Looks like Sowon will not be able to work on these patches anytime soon.
Have spoken to her offline on this and I will be posting V2 of these patches to enable
UFS on ExynosAutov920 SoC.
Patch 3/5 (dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920) was already merged.
Will keep Krzysztof's Acked-by in patch 2/5 (dt-bindings: ufs: exynos: add ExynosAutov920 compatible string)
Will fix review comments on rest of the patches in V2
^ permalink raw reply
* [PATCH v2 7/7] arm64: dts: exynos850: add PMU interrupt generation node
From: Alexey Klimov @ 2026-04-01 4:52 UTC (permalink / raw)
To: Sam Protsenko, linux-samsung-soc, Krzysztof Kozlowski,
Peter Griffin, André Draszik, Conor Dooley, Alim Akhtar
Cc: Tudor Ambarus, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
devicetree, linux-kernel, Alexey Klimov
In-Reply-To: <20260401-exynos850-cpuhotplug-v2-0-c5a760a3e259@linaro.org>
Add pmu_intr_gen node for Exynos850. This hw block is required
for different power management routines like CPU hotplug and
different sleep and idle states.
Also reference this node from main PMU node.
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
arch/arm64/boot/dts/exynos/exynos850.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index cb55015c8dce..f5cbd4d86226 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -214,6 +214,7 @@ gic: interrupt-controller@12a01000 {
pmu_system_controller: system-controller@11860000 {
compatible = "samsung,exynos850-pmu", "syscon";
reg = <0x11860000 0x10000>;
+ samsung,pmu-intr-gen-syscon = <&pmu_intr_gen>;
reboot: syscon-reboot {
compatible = "syscon-reboot";
@@ -224,6 +225,11 @@ reboot: syscon-reboot {
};
};
+ pmu_intr_gen: syscon@11870000 {
+ compatible = "samsung,exynos850-pmu-intr-gen", "syscon";
+ reg = <0x11870000 0x10000>;
+ };
+
watchdog_cl0: watchdog@10050000 {
compatible = "samsung,exynos850-wdt";
reg = <0x10050000 0x100>;
--
2.51.0
^ permalink raw reply related
* [PATCH v2 6/7] MAINTAINERS: add exynos850-pmu.c to Exynos850 entry
From: Alexey Klimov @ 2026-04-01 4:51 UTC (permalink / raw)
To: Sam Protsenko, linux-samsung-soc, Krzysztof Kozlowski,
Peter Griffin, André Draszik, Conor Dooley, Alim Akhtar
Cc: Tudor Ambarus, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
devicetree, linux-kernel, Alexey Klimov
In-Reply-To: <20260401-exynos850-cpuhotplug-v2-0-c5a760a3e259@linaro.org>
Update Exynos850 entry to include new file
drivers/soc/samsung/exynos850-pmu.c. Add myself as M
there.
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e14e6f874e05..4b28e92b4d9b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23601,6 +23601,7 @@ F: include/dt-bindings/clock/samsung,exynos2200-cmu.h
SAMSUNG EXYNOS850 SoC SUPPORT
M: Sam Protsenko <semen.protsenko@linaro.org>
+M: Alexey Klimov <alexey.klimov@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-samsung-soc@vger.kernel.org
S: Maintained
@@ -23608,6 +23609,7 @@ F: Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
F: Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-pmu-intr-gen.yaml
F: arch/arm64/boot/dts/exynos/exynos850*
F: drivers/clk/samsung/clk-exynos850.c
+F: drivers/soc/samsung/exynos850-pmu.c
F: include/dt-bindings/clock/exynos850.h
SAMSUNG EXYNOS ACPM MAILBOX PROTOCOL
--
2.51.0
^ permalink raw reply related
* [PATCH v2 5/7] soc: samsung: exynos-pmu: add Exynos850 CPU hotplug support
From: Alexey Klimov @ 2026-04-01 4:51 UTC (permalink / raw)
To: Sam Protsenko, linux-samsung-soc, Krzysztof Kozlowski,
Peter Griffin, André Draszik, Conor Dooley, Alim Akhtar
Cc: Tudor Ambarus, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
devicetree, linux-kernel, Alexey Klimov
In-Reply-To: <20260401-exynos850-cpuhotplug-v2-0-c5a760a3e259@linaro.org>
Add cpuhotplug support for Exynos850 platforms. This SoC requires
its own specific set of writes/updates to PMU and PMU interrupts
generation block in order to put a CPU or a group of CPUs into
a different sleep states or prepare these entities for a CPU_OFF
or wake-up out of idle state or after CPU online.
Without these writes/updates the CPU(s) wake-up or online fails.
While at this, also add description of Exynos850 PMU registers.
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
drivers/soc/samsung/Makefile | 2 +-
drivers/soc/samsung/exynos-pmu.c | 1 +
drivers/soc/samsung/exynos-pmu.h | 1 +
drivers/soc/samsung/exynos850-pmu.c | 78 +++++++++++++++++++++++++++++
include/linux/soc/samsung/exynos-regs-pmu.h | 5 ++
5 files changed, 86 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
index 636a762608c9..7f544e3c1fcc 100644
--- a/drivers/soc/samsung/Makefile
+++ b/drivers/soc/samsung/Makefile
@@ -7,7 +7,7 @@ exynos_chipid-y += exynos-chipid.o exynos-asv.o
obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o
obj-$(CONFIG_EXYNOS_PMU) += exynos_pmu.o
-exynos_pmu-y += exynos-pmu.o gs101-pmu.o
+exynos_pmu-y += exynos-pmu.o gs101-pmu.o exynos850-pmu.o
obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \
exynos5250-pmu.o exynos5420-pmu.o
diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
index 4e5fcc01e5e0..daa870ba88f5 100644
--- a/drivers/soc/samsung/exynos-pmu.c
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -133,6 +133,7 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = {
.compatible = "samsung,exynos7-pmu",
}, {
.compatible = "samsung,exynos850-pmu",
+ .data = &exynos850_pmu_data,
},
{ /*sentinel*/ },
};
diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h
index 186299a049a8..4202d3cd94c9 100644
--- a/drivers/soc/samsung/exynos-pmu.h
+++ b/drivers/soc/samsung/exynos-pmu.h
@@ -102,6 +102,7 @@ extern const struct exynos_pmu_data exynos5250_pmu_data;
extern const struct exynos_pmu_data exynos5420_pmu_data;
#endif
extern const struct exynos_pmu_data gs101_pmu_data;
+extern const struct exynos_pmu_data exynos850_pmu_data;
extern void pmu_raw_writel(u32 val, u32 offset);
extern u32 pmu_raw_readl(u32 offset);
diff --git a/drivers/soc/samsung/exynos850-pmu.c b/drivers/soc/samsung/exynos850-pmu.c
new file mode 100644
index 000000000000..b3841547577a
--- /dev/null
+++ b/drivers/soc/samsung/exynos850-pmu.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2026 Linaro Ltd.
+ *
+ * Exynos850 PMU support
+ */
+
+#include <linux/soc/samsung/exynos-pmu.h>
+#include <linux/soc/samsung/exynos-regs-pmu.h>
+#include <linux/regmap.h>
+
+#include "exynos-pmu.h"
+
+static int exynos850_cpu_pmu_offline(struct exynos_pmu_context *pmu_context, unsigned int cpu)
+ __must_hold(&pmu_context->cpupm_lock)
+{
+ u32 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 2);
+ u32 cluster_cpu = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
+ unsigned int cpuhint = smp_processor_id();
+ u32 reg, mask;
+
+ /* set cpu inform hint */
+ regmap_write(pmu_context->pmureg, EXYNOS850_CPU_INFORM(cpuhint),
+ CPU_INFORM_C2);
+
+ mask = BIT(cpu);
+ regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE,
+ mask, BIT(cpu));
+
+ regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®);
+ regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR,
+ reg & mask);
+
+ mask = (BIT(cpu + 8));
+ regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®);
+ regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR,
+ reg & mask);
+
+ regmap_update_bits(pmu_context->pmureg,
+ EXYNOS850_CLUSTER_CPU_INT_EN(this_cluster, cluster_cpu),
+ 1 << 3, 1 << 3);
+ return 0;
+}
+
+static int exynos850_cpu_pmu_online(struct exynos_pmu_context *pmu_context, unsigned int cpu)
+ __must_hold(&pmu_context->cpupm_lock)
+{
+ u32 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 2);
+ u32 cluster_cpu = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
+ unsigned int cpuhint = smp_processor_id();
+ u32 reg, mask;
+
+ /* clear cpu inform hint */
+ regmap_write(pmu_context->pmureg, EXYNOS850_CPU_INFORM(cpuhint),
+ CPU_INFORM_CLEAR);
+
+ mask = BIT(cpu);
+
+ regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE,
+ mask, (0 << cpu));
+
+ regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_UPEND, ®);
+
+ regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_CLEAR,
+ reg & mask);
+
+ regmap_update_bits(pmu_context->pmureg,
+ EXYNOS850_CLUSTER_CPU_INT_EN(this_cluster, cluster_cpu),
+ 1 << 3, 0 << 3);
+ return 0;
+}
+
+const struct exynos_pmu_data exynos850_pmu_data = {
+ .pmu_cpuhp = true,
+ .cpu_pmu_offline = exynos850_cpu_pmu_offline,
+ .cpu_pmu_online = exynos850_cpu_pmu_online,
+};
+
diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
index 9c4d3da41dbf..93c4d724c8ea 100644
--- a/include/linux/soc/samsung/exynos-regs-pmu.h
+++ b/include/linux/soc/samsung/exynos-regs-pmu.h
@@ -1015,6 +1015,11 @@
#define EXYNOS_GRP2_INTR_BID_UPEND (0x0208)
#define EXYNOS_GRP2_INTR_BID_CLEAR (0x020c)
+/* Exynos850 PMU Alive */
+#define EXYNOS850_CPU_INFORM(cpu) (0x0860 + ((cpu) & 7) * 4)
+#define EXYNOS850_CLUSTER_CPU_OFFSET(cl, cpu) (0x1000 + ((cl * 0x400) + ((cpu) * 0x80)))
+#define EXYNOS850_CLUSTER_CPU_INT_EN(cl, cpu) (EXYNOS850_CLUSTER_CPU_OFFSET(cl, cpu) + 0x44)
+
/* exynosautov920 */
#define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710)
#define EXYNOSAUTOV920_PHY_CTRL_USB31 (0x0714)
--
2.51.0
^ permalink raw reply related
* [PATCH v2 4/7] soc: samsung: exynos-pmu: generalise gs101-specific cpu{idle,hotplug} for Exynos SoCs
From: Alexey Klimov @ 2026-04-01 4:51 UTC (permalink / raw)
To: Sam Protsenko, linux-samsung-soc, Krzysztof Kozlowski,
Peter Griffin, André Draszik, Conor Dooley, Alim Akhtar
Cc: Tudor Ambarus, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
devicetree, linux-kernel, Alexey Klimov
In-Reply-To: <20260401-exynos850-cpuhotplug-v2-0-c5a760a3e259@linaro.org>
The cpuhotplug and cpuidle support for GS101-based SoCs which
utilizes GS101 PMU interrupts generation block can be generalised
to be (re)used for other Exynos-based SoCs. Also, the GS101 PMU
interrupts generation block is not exclusive to Google GS101 SoCs
and should be made more Exynos-generic.
Specifically, apply the following changes:
- rename gs101-specific calls, structs, names to be exynos-prefixed;
- move exynos_pmu_context and CPU_INFORM_* defines into exynos-pmu.h;
- introduce cpu_pmu_{offline,online} callbacks in driver-specific
exynos_pmu_data which can be used to hold PMU and PMU intr gen
update routines for different platforms and update cpuidle and cpuhotplug
support to use them;
- query the "samsung,pmu-intr-gen-syscon" phandle to reflect updates in
the DT bindings;
- add checks for the presense of cpu_pmu_{offline,online} callbacks;
- move and rename gs101-specific cpu{offline,online} PMU updates
routines into gs101-pmu.c file, also removing underscore prefix;
- update gs101_pmu_data to use newly introduced callbacks;
- rename PMU interrupts generation GS101_INTR_* regs to EXYNOS_INTR_*.
This allows other platforms to add cpuhotplug and cpuidle support in
a similar manner, using their own platform-specific PMU and
PMU intr gen update routines.
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
drivers/soc/samsung/exynos-pmu.c | 126 +++++++---------------------
drivers/soc/samsung/exynos-pmu.h | 31 +++++++
drivers/soc/samsung/gs101-pmu.c | 57 +++++++++++++
include/linux/soc/samsung/exynos-regs-pmu.h | 10 +--
4 files changed, 121 insertions(+), 103 deletions(-)
diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
index d58376c38179..4e5fcc01e5e0 100644
--- a/drivers/soc/samsung/exynos-pmu.c
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -24,22 +24,6 @@
#include "exynos-pmu.h"
-struct exynos_pmu_context {
- struct device *dev;
- const struct exynos_pmu_data *pmu_data;
- struct regmap *pmureg;
- struct regmap *pmuintrgen;
- /*
- * Serialization lock for CPU hot plug and cpuidle ACPM hint
- * programming. Also protects in_cpuhp, sys_insuspend & sys_inreboot
- * flags.
- */
- raw_spinlock_t cpupm_lock;
- unsigned long *in_cpuhp;
- bool sys_insuspend;
- bool sys_inreboot;
-};
-
void __iomem *pmu_base_addr;
static struct exynos_pmu_context *pmu_context;
/* forward declaration */
@@ -219,44 +203,8 @@ struct regmap *exynos_get_pmu_regmap_by_phandle(struct device_node *np,
}
EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap_by_phandle);
-/*
- * CPU_INFORM register "hint" values are required to be programmed in addition to
- * the standard PSCI calls to have functional CPU hotplug and CPU idle states.
- * This is required to workaround limitations in the el3mon/ACPM firmware.
- */
-#define CPU_INFORM_CLEAR 0
-#define CPU_INFORM_C2 1
-
-/*
- * __gs101_cpu_pmu_ prefix functions are common code shared by CPU PM notifiers
- * (CPUIdle) and CPU hotplug callbacks. Functions should be called with IRQs
- * disabled and cpupm_lock held.
- */
-static int __gs101_cpu_pmu_online(unsigned int cpu)
- __must_hold(&pmu_context->cpupm_lock)
-{
- unsigned int cpuhint = smp_processor_id();
- u32 reg, mask;
-
- /* clear cpu inform hint */
- regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint),
- CPU_INFORM_CLEAR);
-
- mask = BIT(cpu);
-
- regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE,
- mask, (0 << cpu));
-
- regmap_read(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_UPEND, ®);
-
- regmap_write(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_CLEAR,
- reg & mask);
-
- return 0;
-}
-
/* Called from CPU PM notifier (CPUIdle code path) with IRQs disabled */
-static int gs101_cpu_pmu_online(void)
+static int exynos_cpu_pmu_online(void)
{
int cpu;
@@ -268,20 +216,20 @@ static int gs101_cpu_pmu_online(void)
}
cpu = smp_processor_id();
- __gs101_cpu_pmu_online(cpu);
+ pmu_context->pmu_data->cpu_pmu_online(pmu_context, cpu);
raw_spin_unlock(&pmu_context->cpupm_lock);
return NOTIFY_OK;
}
/* Called from CPU hot plug callback with IRQs enabled */
-static int gs101_cpuhp_pmu_online(unsigned int cpu)
+static int exynos_cpuhp_pmu_online(unsigned int cpu)
{
unsigned long flags;
raw_spin_lock_irqsave(&pmu_context->cpupm_lock, flags);
- __gs101_cpu_pmu_online(cpu);
+ pmu_context->pmu_data->cpu_pmu_online(pmu_context, cpu);
/*
* Mark this CPU as having finished the hotplug.
* This means this CPU can now enter C2 idle state.
@@ -292,35 +240,8 @@ static int gs101_cpuhp_pmu_online(unsigned int cpu)
return 0;
}
-/* Common function shared by both CPU hot plug and CPUIdle */
-static int __gs101_cpu_pmu_offline(unsigned int cpu)
- __must_hold(&pmu_context->cpupm_lock)
-{
- unsigned int cpuhint = smp_processor_id();
- u32 reg, mask;
-
- /* set cpu inform hint */
- regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint),
- CPU_INFORM_C2);
-
- mask = BIT(cpu);
- regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE,
- mask, BIT(cpu));
-
- regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®);
- regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR,
- reg & mask);
-
- mask = (BIT(cpu + 8));
- regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®);
- regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR,
- reg & mask);
-
- return 0;
-}
-
/* Called from CPU PM notifier (CPUIdle code path) with IRQs disabled */
-static int gs101_cpu_pmu_offline(void)
+static int exynos_cpu_pmu_offline(void)
{
int cpu;
@@ -338,14 +259,14 @@ static int gs101_cpu_pmu_offline(void)
return NOTIFY_OK;
}
- __gs101_cpu_pmu_offline(cpu);
+ pmu_context->pmu_data->cpu_pmu_offline(pmu_context, cpu);
raw_spin_unlock(&pmu_context->cpupm_lock);
return NOTIFY_OK;
}
/* Called from CPU hot plug callback with IRQs enabled */
-static int gs101_cpuhp_pmu_offline(unsigned int cpu)
+static int exynos_cpuhp_pmu_offline(unsigned int cpu)
{
unsigned long flags;
@@ -355,29 +276,29 @@ static int gs101_cpuhp_pmu_offline(unsigned int cpu)
* ACPM the CPU entering hotplug should not enter C2 idle state.
*/
set_bit(cpu, pmu_context->in_cpuhp);
- __gs101_cpu_pmu_offline(cpu);
+ pmu_context->pmu_data->cpu_pmu_offline(pmu_context, cpu);
raw_spin_unlock_irqrestore(&pmu_context->cpupm_lock, flags);
return 0;
}
-static int gs101_cpu_pm_notify_callback(struct notifier_block *self,
+static int exynos_cpu_pm_notify_callback(struct notifier_block *self,
unsigned long action, void *v)
{
switch (action) {
case CPU_PM_ENTER:
- return gs101_cpu_pmu_offline();
+ return exynos_cpu_pmu_offline();
case CPU_PM_EXIT:
- return gs101_cpu_pmu_online();
+ return exynos_cpu_pmu_online();
}
return NOTIFY_OK;
}
-static struct notifier_block gs101_cpu_pm_notifier = {
- .notifier_call = gs101_cpu_pm_notify_callback,
+static struct notifier_block exynos_cpu_pm_notifier = {
+ .notifier_call = exynos_cpu_pm_notify_callback,
/*
* We want to be called first, as the ACPM hint and handshake is what
* puts the CPU into C2.
@@ -414,8 +335,12 @@ static int setup_cpuhp_and_cpuidle(struct device *dev)
void __iomem *virt_addr;
int ret, cpu;
- intr_gen_node = of_parse_phandle(dev->of_node,
- "google,pmu-intr-gen-syscon", 0);
+ intr_gen_node = of_parse_phandle(dev->of_node, "samsung,pmu-intr-gen-syscon", 0);
+
+ /* Fall back to the google pmu intr gen property for older DTBs */
+ if (!intr_gen_node)
+ intr_gen_node = of_parse_phandle(dev->of_node, "google,pmu-intr-gen-syscon", 0);
+
if (!intr_gen_node) {
/*
* To maintain support for older DTs that didn't specify syscon
@@ -425,6 +350,11 @@ static int setup_cpuhp_and_cpuidle(struct device *dev)
return 0;
}
+ if (!pmu_context->pmu_data->cpu_pmu_offline || !pmu_context->pmu_data->cpu_pmu_online) {
+ dev_err(dev, "PMU write/read sequence is not present for cpuhotplug and cpuidle\n");
+ return -ENODEV;
+ }
+
/*
* To avoid lockdep issues (CPU PM notifiers use raw spinlocks) create
* a mmio regmap for pmu-intr-gen that uses raw spinlocks instead of
@@ -458,17 +388,17 @@ static int setup_cpuhp_and_cpuidle(struct device *dev)
/* set PMU to power on */
for_each_online_cpu(cpu)
- gs101_cpuhp_pmu_online(cpu);
+ exynos_cpuhp_pmu_online(cpu);
/* register CPU hotplug callbacks */
cpuhp_setup_state(CPUHP_BP_PREPARE_DYN, "soc/exynos-pmu:prepare",
- gs101_cpuhp_pmu_online, NULL);
+ exynos_cpuhp_pmu_online, NULL);
cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "soc/exynos-pmu:online",
- NULL, gs101_cpuhp_pmu_offline);
+ NULL, exynos_cpuhp_pmu_offline);
/* register CPU PM notifiers for cpuidle */
- cpu_pm_register_notifier(&gs101_cpu_pm_notifier);
+ cpu_pm_register_notifier(&exynos_cpu_pm_notifier);
register_reboot_notifier(&exynos_cpupm_reboot_nb);
return 0;
}
diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h
index fbe381e2a2e1..186299a049a8 100644
--- a/drivers/soc/samsung/exynos-pmu.h
+++ b/drivers/soc/samsung/exynos-pmu.h
@@ -13,6 +13,14 @@
#define PMU_TABLE_END (-1U)
+/*
+ * CPU_INFORM register "hint" values are required to be programmed in addition to
+ * the standard PSCI calls to have functional CPU hotplug and CPU idle states.
+ * This is required to workaround limitations in the el3mon/ACPM firmware.
+ */
+#define CPU_INFORM_CLEAR 0
+#define CPU_INFORM_C2 1
+
struct regmap_access_table;
struct exynos_pmu_conf {
@@ -20,6 +28,22 @@ struct exynos_pmu_conf {
u8 val[NUM_SYS_POWERDOWN];
};
+struct exynos_pmu_context {
+ struct device *dev;
+ const struct exynos_pmu_data *pmu_data;
+ struct regmap *pmureg;
+ struct regmap *pmuintrgen;
+ /*
+ * Serialization lock for CPU hot plug and cpuidle ACPM hint
+ * programming. Also protects in_cpuhp, sys_insuspend & sys_inreboot
+ * flags.
+ */
+ raw_spinlock_t cpupm_lock;
+ unsigned long *in_cpuhp;
+ bool sys_insuspend;
+ bool sys_inreboot;
+};
+
/**
* struct exynos_pmu_data - of_device_id (match) data
*
@@ -44,6 +68,10 @@ struct exynos_pmu_conf {
* used (i.e. when @pmu_secure is @true).
* @wr_table: A table of writable register ranges in case a custom regmap is
* used (i.e. when @pmu_secure is @true).
+ * @cpu_pmu_offline: Optional callback to be called before entering CPU offline
+ * or idle state. Only valid when pmu_cpuhp set to true.
+ * @cpu_pmu_online: Optional callback to be called after CPU onlined or after
+ * exiting idle state. Only valid when pmu_cpuhp set to true.
*/
struct exynos_pmu_data {
const struct exynos_pmu_conf *pmu_config;
@@ -57,6 +85,9 @@ struct exynos_pmu_data {
const struct regmap_access_table *rd_table;
const struct regmap_access_table *wr_table;
+
+ int (*cpu_pmu_offline)(struct exynos_pmu_context *pmu_context, unsigned int cpu);
+ int (*cpu_pmu_online)(struct exynos_pmu_context *pmu_context, unsigned int cpu);
};
extern void __iomem *pmu_base_addr;
diff --git a/drivers/soc/samsung/gs101-pmu.c b/drivers/soc/samsung/gs101-pmu.c
index 17dadc1b9c6e..5f2a59924144 100644
--- a/drivers/soc/samsung/gs101-pmu.c
+++ b/drivers/soc/samsung/gs101-pmu.c
@@ -322,11 +322,68 @@ static const struct regmap_access_table gs101_pmu_wr_table = {
.n_no_ranges = ARRAY_SIZE(gs101_pmu_ro_registers),
};
+/*
+ * gs101_cpu_pmu_ prefix functions are common code shared by CPU PM notifiers
+ * (CPUIdle) and CPU hotplug callbacks. Functions should be called with IRQs
+ * disabled and cpupm_lock held.
+ */
+static int gs101_cpu_pmu_online(struct exynos_pmu_context *pmu_context, unsigned int cpu)
+ __must_hold(&pmu_context->cpupm_lock)
+{
+ unsigned int cpuhint = smp_processor_id();
+ u32 reg, mask;
+
+ /* clear cpu inform hint */
+ regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint),
+ CPU_INFORM_CLEAR);
+
+ mask = BIT(cpu);
+
+ regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE,
+ mask, (0 << cpu));
+
+ regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_UPEND, ®);
+
+ regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_CLEAR,
+ reg & mask);
+
+ return 0;
+}
+
+/* Common function shared by both CPU hot plug and CPUIdle */
+static int gs101_cpu_pmu_offline(struct exynos_pmu_context *pmu_context, unsigned int cpu)
+ __must_hold(&pmu_context->cpupm_lock)
+{
+ unsigned int cpuhint = smp_processor_id();
+ u32 reg, mask;
+
+ /* set cpu inform hint */
+ regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint),
+ CPU_INFORM_C2);
+
+ mask = BIT(cpu);
+ regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE,
+ mask, BIT(cpu));
+
+ regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®);
+ regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR,
+ reg & mask);
+
+ mask = (BIT(cpu + 8));
+ regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®);
+ regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR,
+ reg & mask);
+
+ return 0;
+}
+
const struct exynos_pmu_data gs101_pmu_data = {
.pmu_secure = true,
.pmu_cpuhp = true,
.rd_table = &gs101_pmu_rd_table,
.wr_table = &gs101_pmu_wr_table,
+ .cpu_pmu_offline = gs101_cpu_pmu_offline,
+ .cpu_pmu_online = gs101_cpu_pmu_online,
};
/*
diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
index db8a7ca81080..9c4d3da41dbf 100644
--- a/include/linux/soc/samsung/exynos-regs-pmu.h
+++ b/include/linux/soc/samsung/exynos-regs-pmu.h
@@ -1009,11 +1009,11 @@
#define GS101_PHY_CTRL_UFS 0x3ec8
/* PMU INTR GEN */
-#define GS101_GRP1_INTR_BID_UPEND (0x0108)
-#define GS101_GRP1_INTR_BID_CLEAR (0x010c)
-#define GS101_GRP2_INTR_BID_ENABLE (0x0200)
-#define GS101_GRP2_INTR_BID_UPEND (0x0208)
-#define GS101_GRP2_INTR_BID_CLEAR (0x020c)
+#define EXYNOS_GRP1_INTR_BID_UPEND (0x0108)
+#define EXYNOS_GRP1_INTR_BID_CLEAR (0x010c)
+#define EXYNOS_GRP2_INTR_BID_ENABLE (0x0200)
+#define EXYNOS_GRP2_INTR_BID_UPEND (0x0208)
+#define EXYNOS_GRP2_INTR_BID_CLEAR (0x020c)
/* exynosautov920 */
#define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710)
--
2.51.0
^ permalink raw reply related
* [PATCH v2 3/7] dt-bindings: soc: samsung: exynos-pmu: deprecate google,pmu-intr-gen-syscon
From: Alexey Klimov @ 2026-04-01 4:51 UTC (permalink / raw)
To: Sam Protsenko, linux-samsung-soc, Krzysztof Kozlowski,
Peter Griffin, André Draszik, Conor Dooley, Alim Akhtar
Cc: Tudor Ambarus, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
devicetree, linux-kernel, Alexey Klimov
In-Reply-To: <20260401-exynos850-cpuhotplug-v2-0-c5a760a3e259@linaro.org>
The generic property samsung,pmu-intr-gen-syscon should be used
by default for Samsung Exynos PMU hardware blocks. Update binding
document to add deprecated flag for google,pmu-intr-gen-syscon
property.
While at this, also add dependency to not allow usage of both
above mentioned properties in the same time.
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
index 92acdfd5d44e..1ff1a8729989 100644
--- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
@@ -119,6 +119,7 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to PMU interrupt generation interface.
+ deprecated: true
required:
- compatible
@@ -207,6 +208,11 @@ allOf:
properties:
samsung,pmu-intr-gen-syscon: false
+dependencies:
+ google,pmu-intr-gen-syscon:
+ not:
+ required: ['samsung,pmu-intr-gen-syscon']
+
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
--
2.51.0
^ permalink raw reply related
* [PATCH v2 2/7] dt-bindings: soc: samsung: exynos-pmu: add samsung,pmu-intr-gen phandle
From: Alexey Klimov @ 2026-04-01 4:51 UTC (permalink / raw)
To: Sam Protsenko, linux-samsung-soc, Krzysztof Kozlowski,
Peter Griffin, André Draszik, Conor Dooley, Alim Akhtar
Cc: Tudor Ambarus, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
devicetree, linux-kernel, Alexey Klimov
In-Reply-To: <20260401-exynos850-cpuhotplug-v2-0-c5a760a3e259@linaro.org>
Some Exynos-based SoCs, for instance Exynos850, require access
to the pmu interrupt generation register region which is exposed
as a syscon. Update the exynos-pmu bindings documentation to
reflect this.
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
.../devicetree/bindings/soc/samsung/exynos-pmu.yaml | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
index 76ce7e98c10f..92acdfd5d44e 100644
--- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
@@ -110,6 +110,11 @@ properties:
description:
Node for reboot method
+ samsung,pmu-intr-gen-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to PMU interrupt generation interface.
+
google,pmu-intr-gen-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
@@ -189,6 +194,19 @@ allOf:
properties:
google,pmu-intr-gen-syscon: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos850-pmu
+ then:
+ required:
+ - samsung,pmu-intr-gen-syscon
+ else:
+ properties:
+ samsung,pmu-intr-gen-syscon: false
+
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
--
2.51.0
^ permalink raw reply related
* [PATCH v2 1/7] dt-bindings: soc: move,rename google,gs101-pmu-intr-gen and add exynos850
From: Alexey Klimov @ 2026-04-01 4:51 UTC (permalink / raw)
To: Sam Protsenko, linux-samsung-soc, Krzysztof Kozlowski,
Peter Griffin, André Draszik, Conor Dooley, Alim Akhtar
Cc: Tudor Ambarus, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
devicetree, linux-kernel, Alexey Klimov
In-Reply-To: <20260401-exynos850-cpuhotplug-v2-0-c5a760a3e259@linaro.org>
The PMU interrupt generation block introduced for the Google GS101 is
actually a standard Samsung Exynos IP block found in older SoCs, such
as the Exynos850, and is not exclusive to Google SoCs. To accurately
reflect its origin, move the schema file to under soc/samsung/
directory and rename it.
Concurrently, add the new "samsung,exynos850-pmu-intr-gen" compatible
string to the bindings. Support for this block is required to enable
power management features like CPU hotplug and idle states on Exynos850
platforms.
Also, move this file under Exynos850 SoC in MAINTAINERS entry.
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
.../samsung,exynos850-pmu-intr-gen.yaml} | 8 +++++---
MAINTAINERS | 2 +-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-pmu-intr-gen.yaml
similarity index 70%
rename from Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml
rename to Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-pmu-intr-gen.yaml
index 2be022ca6a7d..df23467d0e0e 100644
--- a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-pmu-intr-gen.yaml
@@ -1,10 +1,10 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/soc/google/google,gs101-pmu-intr-gen.yaml#
+$id: http://devicetree.org/schemas/soc/samsung/samsung,exynos850-pmu-intr-gen.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Google Power Management Unit (PMU) Interrupt Generation
+title: Samsung Power Management Unit (PMU) Interrupt Generation
description: |
PMU interrupt generator for handshaking between PMU through interrupts.
@@ -15,7 +15,9 @@ maintainers:
properties:
compatible:
items:
- - const: google,gs101-pmu-intr-gen
+ - enum:
+ - google,gs101-pmu-intr-gen
+ - samsung,exynos850-pmu-intr-gen
- const: syscon
reg:
diff --git a/MAINTAINERS b/MAINTAINERS
index ff935e197c21..e14e6f874e05 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10947,7 +10947,6 @@ P: Documentation/process/maintainer-soc-clean-dts.rst
C: irc://irc.oftc.net/pixel6-kernel-dev
F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
F: Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml
-F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml
F: Documentation/devicetree/bindings/usb/google,lga-dwc3.yaml
F: arch/arm64/boot/dts/exynos/google/
F: drivers/clk/samsung/clk-gs101.c
@@ -23606,6 +23605,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-samsung-soc@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+F: Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-pmu-intr-gen.yaml
F: arch/arm64/boot/dts/exynos/exynos850*
F: drivers/clk/samsung/clk-exynos850.c
F: include/dt-bindings/clock/exynos850.h
--
2.51.0
^ permalink raw reply related
* [PATCH v2 0/7] Exynos-pmu: Generalise cpu{hotplug,idle},PMU intr gen and add Exynos850 CPU hotplug
From: Alexey Klimov @ 2026-04-01 4:51 UTC (permalink / raw)
To: Sam Protsenko, linux-samsung-soc, Krzysztof Kozlowski,
Peter Griffin, André Draszik, Conor Dooley, Alim Akhtar
Cc: Tudor Ambarus, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
devicetree, linux-kernel, Alexey Klimov
(b4 forces me to send this as v2, however previous version was RFC and b4
uses RFC as v1; but I don't want to break b4 tracking and b4 comparison)
Series generalises the GS101-specific cpuhotplug, cpuidle and PMU interrupt
generation block support, which is currently implemented specifically for
the google GS101 SoC, to make it reusable by other Samsung Exynos SoCs.
The PMU interrupt generation IP block introduced for google GS101 is a
standard Samsung Exynos block found in other SoCs, including Exynos850,
and it is not strictly exclusive to google Exynos-based platforms.
Access to this block is required to implement and enable cpuhotplug
on Exynos850-based boards.
As a next steps it will be possible to enable idle states on top of it.
First patches work on DT bindings to reflect that Exynos850 SoC predates
gs101 one, introduce new samsung,pmu-intr-gen-syscon phandle.
Then series generalises ("Exynosizes") cpuhotplug/cpuidle routines by
deferring platform-specific PMU and PMU-intr-gen updates to platform-
specific callbacks and then finally introduces new file exynos850-pmu.c
where such callbacks are implemented for Exynos850. Last commit adds
pmu_intr_gen DT node to exynos850.dtsi.
This series was tested on Exynos850 WinLink E850-96 board:
-- by spinning "chcpu -d 1-7; chcpu -e 1-7" in a loop for a few hours;
-- by running script [1] that randomly offlines or onlines random cpus
for a few hours.
I do not have access to a development google Pixel 6 or other gs101-based
devices to verify. I tried to implement it in way to not break anything
for gs101, but testing from others is highly appreciated.
Otherwise, if it can be tested on a "normal" pixel6 phone without breaking
userdata/android there, then please point me to instructions.
Will check sashiko after submitting this to see if anything can be improved.
Thanks,
Alexey
[1]: https://github.com/laklimov/xlam/blob/main/e850_cpuhotplug_random.sh
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
Changes in v2:
- moved gs101 cpu {offline,online} callbacks to gs101-pmu.c, updated MAINTAINERS;
- added new file exynos850-pmu.c with cpu {offline,online} callbacks and
exynos850 pmu data;
- new patch that adds exynos850-pmu.c to MAINTAINERS;
- moved pmu_intr_gen to right after pmu_system_controller@11860000;
- merged two patches that update google,gs101-pmu-intr-gen.yaml together,
now rename and adding exynos850 entry goes in a single patch;
- commits 5 and 6 from RFC series are merged together and reworked,
cpu_pmu_{offline,online} callbacks are moved into pmu_data struct, and
callbacks now need pmu_context as an argument, exynos_pmu_context and
CPU_INFORM defines are moved to exynos-pmu.h, gs101 callbacks
renamed. It is really better to check commit description.
- Link to RFC (v1 from b4 point of view):
https://lore.kernel.org/r/20260226-exynos850-cpuhotplug-v1-0-71d7c4063382@linaro.org
---
Alexey Klimov (7):
dt-bindings: soc: move,rename google,gs101-pmu-intr-gen and add exynos850
dt-bindings: soc: samsung: exynos-pmu: add samsung,pmu-intr-gen phandle
dt-bindings: soc: samsung: exynos-pmu: deprecate google,pmu-intr-gen-syscon
soc: samsung: exynos-pmu: generalise gs101-specific cpu{idle,hotplug} for Exynos SoCs
soc: samsung: exynos-pmu: add Exynos850 CPU hotplug support
MAINTAINERS: add exynos850-pmu.c to Exynos850 entry
arm64: dts: exynos850: add PMU interrupt generation node
.../bindings/soc/samsung/exynos-pmu.yaml | 24 ++++
.../samsung,exynos850-pmu-intr-gen.yaml} | 8 +-
MAINTAINERS | 4 +-
arch/arm64/boot/dts/exynos/exynos850.dtsi | 6 +
drivers/soc/samsung/Makefile | 2 +-
drivers/soc/samsung/exynos-pmu.c | 127 +++++----------------
drivers/soc/samsung/exynos-pmu.h | 32 ++++++
drivers/soc/samsung/exynos850-pmu.c | 78 +++++++++++++
drivers/soc/samsung/gs101-pmu.c | 57 +++++++++
include/linux/soc/samsung/exynos-regs-pmu.h | 15 ++-
10 files changed, 245 insertions(+), 108 deletions(-)
---
base-commit: 3b058d1aeeeff27a7289529c4944291613b364e9
change-id: 20260226-exynos850-cpuhotplug-69f1976eefa8
Best regards,
--
Alexey Klimov <alexey.klimov@linaro.org>
^ permalink raw reply
* Re: [PATCH v2 4/7] PCI: intel-gw: Add start_link callback function
From: kernel test robot @ 2026-04-01 4:10 UTC (permalink / raw)
To: Florian Eckert, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Johan Hovold,
Sajid Dalvi, Ajay Agarwal, Krzysztof Kozlowski, Conor Dooley,
Rahul Tanwar
Cc: llvm, oe-kbuild-all, linux-pci, linux-kernel, devicetree,
Florian Eckert, Eckert.Florian, ms
In-Reply-To: <20260330-pcie-intel-gw-v2-4-8bd07367a298@dev.tdt.de>
Hi Florian,
kernel test robot noticed the following build warnings:
[auto build test WARNING on f338e77383789c0cae23ca3d48adcc5e9e137e3c]
url: https://github.com/intel-lab-lkp/linux/commits/Florian-Eckert/PCI-intel-gw-Remove-unused-define/20260401-051352
base: f338e77383789c0cae23ca3d48adcc5e9e137e3c
patch link: https://lore.kernel.org/r/20260330-pcie-intel-gw-v2-4-8bd07367a298%40dev.tdt.de
patch subject: [PATCH v2 4/7] PCI: intel-gw: Add start_link callback function
config: arm64-randconfig-001-20260401 (https://download.01.org/0day-ci/archive/20260401/202604011157.4RiSNWVi-lkp@intel.com/config)
compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260401/202604011157.4RiSNWVi-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202604011157.4RiSNWVi-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/pci/controller/dwc/pcie-intel-gw.c:329:1: warning: unused label 'err' [-Wunused-label]
329 | err:
| ^~~~
1 warning generated.
vim +/err +329 drivers/pci/controller/dwc/pcie-intel-gw.c
6cbd614d1f7c81 Florian Eckert 2026-03-30 296
733770d4a2bea0 Fan Fei 2021-12-22 297 static int intel_pcie_host_setup(struct intel_pcie *pcie)
ed22aaaede44f6 Dilip Kota 2019-12-09 298 {
ed22aaaede44f6 Dilip Kota 2019-12-09 299 int ret;
733770d4a2bea0 Fan Fei 2021-12-22 300 struct dw_pcie *pci = &pcie->pci;
ed22aaaede44f6 Dilip Kota 2019-12-09 301
733770d4a2bea0 Fan Fei 2021-12-22 302 intel_pcie_core_rst_assert(pcie);
733770d4a2bea0 Fan Fei 2021-12-22 303 intel_pcie_device_rst_assert(pcie);
733770d4a2bea0 Fan Fei 2021-12-22 304 intel_pcie_core_rst_deassert(pcie);
ed22aaaede44f6 Dilip Kota 2019-12-09 305
1927e1ec66a6ee Florian Eckert 2026-03-30 306 /* Controller clock must be provided earlier than PHY */
733770d4a2bea0 Fan Fei 2021-12-22 307 ret = clk_prepare_enable(pcie->core_clk);
ed22aaaede44f6 Dilip Kota 2019-12-09 308 if (ret) {
733770d4a2bea0 Fan Fei 2021-12-22 309 dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret);
ed22aaaede44f6 Dilip Kota 2019-12-09 310 goto clk_err;
ed22aaaede44f6 Dilip Kota 2019-12-09 311 }
ed22aaaede44f6 Dilip Kota 2019-12-09 312
1cc9a559993a4a Rob Herring 2020-11-05 313 pci->atu_base = pci->dbi_base + 0xC0000;
1cc9a559993a4a Rob Herring 2020-11-05 314
1927e1ec66a6ee Florian Eckert 2026-03-30 315 ret = phy_init(pcie->phy);
1927e1ec66a6ee Florian Eckert 2026-03-30 316 if (ret)
1927e1ec66a6ee Florian Eckert 2026-03-30 317 goto phy_err;
1927e1ec66a6ee Florian Eckert 2026-03-30 318
733770d4a2bea0 Fan Fei 2021-12-22 319 intel_pcie_ltssm_disable(pcie);
733770d4a2bea0 Fan Fei 2021-12-22 320 intel_pcie_link_setup(pcie);
1cc9a559993a4a Rob Herring 2020-11-05 321 intel_pcie_init_n_fts(pci);
ce06bf570390fb Serge Semin 2022-06-24 322
1cc9a559993a4a Rob Herring 2020-11-05 323 dw_pcie_upconfig_setup(pci);
1cc9a559993a4a Rob Herring 2020-11-05 324
4db57fd92a7d2d Florian Eckert 2026-03-30 325 intel_pcie_core_irq_enable(pcie);
ed22aaaede44f6 Dilip Kota 2019-12-09 326
ed22aaaede44f6 Dilip Kota 2019-12-09 327 return 0;
ed22aaaede44f6 Dilip Kota 2019-12-09 328
1927e1ec66a6ee Florian Eckert 2026-03-30 @329 err:
1927e1ec66a6ee Florian Eckert 2026-03-30 330 phy_exit(pcie->phy);
1927e1ec66a6ee Florian Eckert 2026-03-30 331 phy_err:
733770d4a2bea0 Fan Fei 2021-12-22 332 clk_disable_unprepare(pcie->core_clk);
ed22aaaede44f6 Dilip Kota 2019-12-09 333 clk_err:
733770d4a2bea0 Fan Fei 2021-12-22 334 intel_pcie_core_rst_assert(pcie);
ed22aaaede44f6 Dilip Kota 2019-12-09 335
ed22aaaede44f6 Dilip Kota 2019-12-09 336 return ret;
ed22aaaede44f6 Dilip Kota 2019-12-09 337 }
ed22aaaede44f6 Dilip Kota 2019-12-09 338
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v2 2/2] hwmon: pmbus: Add support for Sony APS-379
From: Chris Packham @ 2026-04-01 4:05 UTC (permalink / raw)
To: Guenter Roeck, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org
Cc: devicetree@vger.kernel.org, linux-hwmon@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <451d4cca-5966-4817-92b5-b886c7f7271d@roeck-us.net>
On 01/04/2026 16:58, Guenter Roeck wrote:
> On 3/31/26 19:42, Chris Packham wrote:
>> Add pmbus support for Sony APS-379 power supplies. There are a few PMBUS
>> commands that return data that is undocumented/invalid so these need to
>> be rejected with -ENXIO. The READ_VOUT command returns data in linear11
>> format instead of linear16 so we need to workaround this.
>>
>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>> ---
>>
>
> Here is the AI feedback:
>
> https://scanmail.trustwave.com/?c=20988&d=-5fM6Qyi3kX42boReXvp_F06nhM1_AVskUmlQ71c3g&u=https%3a%2f%2fsashiko%2edev%2f%23%2fpatchset%2f20260401024214%2e804237-1-chris%2epackham%2540alliedtelesis%2eco%2enz
>
>
> All good points ...
Yep agreed. The lack of MODULE_DEVICE_TABLE() is an omission on my part.
The other two are arguably style but I find myself agreeing with both
suggestions. I'll wait to send a v3.
>
>
> Guenter
>
>> Notes:
>> Changes in v2:
>> - Simplify code per recommendations from Guenter
>> - Add driver documentation
>>
>> Documentation/hwmon/aps-379.rst | 58 +++++++++++
>> Documentation/hwmon/index.rst | 1 +
>> drivers/hwmon/pmbus/Kconfig | 6 ++
>> drivers/hwmon/pmbus/Makefile | 1 +
>> drivers/hwmon/pmbus/aps-379.c | 168 ++++++++++++++++++++++++++++++++
>> 5 files changed, 234 insertions(+)
>> create mode 100644 Documentation/hwmon/aps-379.rst
>> create mode 100644 drivers/hwmon/pmbus/aps-379.c
>>
>> diff --git a/Documentation/hwmon/aps-379.rst
>> b/Documentation/hwmon/aps-379.rst
>> new file mode 100644
>> index 000000000000..468ec5a98fd6
>> --- /dev/null
>> +++ b/Documentation/hwmon/aps-379.rst
>> @@ -0,0 +1,58 @@
>> +Kernel driver aps-379
>> +=====================
>> +
>> +Supported chips:
>> +
>> + * Sony APS-379
>> +
>> + Prefix: 'aps-379'
>> +
>> + Addresses scanned: -
>> +
>> + Authors:
>> + - Chris Packham
>> +
>> +Description
>> +-----------
>> +
>> +This driver implements support for the PMBus monitor on the Sony
>> APS-379
>> +modular power supply. The APS-379 deviates from the PMBus standard
>> for the
>> +READ_VOUT command by using the linear11 format instead of linear16.
>> +
>> +The known supported PMBus commands are:
>> +
>> +=== ============================= ========= ======= =====
>> +Cmd Function Protocol Scaling Bytes
>> +=== ============================= ========= ======= =====
>> +01 On / Off Command (OPERATION) Byte R/W -- 1
>> +10 WRITE_PROTECT Byte R/W -- 1
>> +3B FAN_COMMAND_1 Word R/W -- 2
>> +46 Current Limit (in percent) Word R/W 2^0 2
>> +47 Current Limit Fault Response Byte R/W -- 1
>> +79 Alarm Data Bits (STATUS_WORD) Word Rd -- 2
>> +8B Output Voltage (READ_VOUT) Word Rd 2^-4 2
>> +8C Output Current (READ_IOUT) Word Rd 2^-2 2
>> +8D Power Supply Ambient Temp Word Rd 2^0 2
>> +90 READ_FAN_SPEED_1 Word Rd 2^6 2
>> +91 READ_FAN_SPEED_2 Word Rd 2^6 2
>> +96 Output Wattage (READ_POUT) Word Rd 2^1 2
>> +97 Input Wattage (READ_PIN) Word Rd 2^1 2
>> +9A Unit Model Number (MFR_MODEL) Block R/W -- 10
>> +9B Unit Revision Number Block R/W -- 10
>> +9E Unit Serial Number Block R/W -- 8
>> +99 Unit Manufacturer ID (MFR_ID) Block R/W -- 8
>> +D0 Unit Run Time Information Block Rd -- 4
>> +D5 Firmware Version Rd cust -- 8
>> +B0 User Data 1 (USER_DATA_00) Block R/W -- 4
>> +B1 User Data 2 (USER_DATA_01) Block R/W -- 4
>> +B2 User Data 3 (USER_DATA_02) Block R/W -- 4
>> +B3 User Data 4 (USER_DATA_03) Block R/W -- 4
>> +B4 User Data 5 (USER_DATA_04) Block R/W -- 4
>> +B5 User Data 6 (USER_DATA_05) Block R/W -- 4
>> +B6 User Data 7 (USER_DATA_06) Block R/W -- 4
>> +B7 User Data 8 (USER_DATA_07) Block R/W -- 4
>> +F0 Calibration command Byte R/W -- 1
>> +F1 Calibration data Word Wr 2^9 2
>> +F2 Unlock Calibration Byte Wr -- 1
>> +=== ============================= ========= ======= =====
>> +
>> diff --git a/Documentation/hwmon/index.rst
>> b/Documentation/hwmon/index.rst
>> index b2ca8513cfcd..2bc8d88b5724 100644
>> --- a/Documentation/hwmon/index.rst
>> +++ b/Documentation/hwmon/index.rst
>> @@ -41,6 +41,7 @@ Hardware Monitoring Kernel Drivers
>> adt7475
>> aht10
>> amc6821
>> + aps-379
>> aquacomputer_d5next
>> asb100
>> asc7621
>> diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig
>> index fc1273abe357..29076921e330 100644
>> --- a/drivers/hwmon/pmbus/Kconfig
>> +++ b/drivers/hwmon/pmbus/Kconfig
>> @@ -77,6 +77,12 @@ config SENSORS_ADP1050_REGULATOR
>> µModule regulators that can provide microprocessor power from
>> 54V
>> power distribution architecture.
>> +config SENSORS_APS_379
>> + tristate "Sony APS-379 Power Supplies"
>> + help
>> + If you say yes here you get hardware monitoring support for Sony
>> + APS-379 Power Supplies.
>> +
>> config SENSORS_BEL_PFE
>> tristate "Bel PFE Compatible Power Supplies"
>> help
>> diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile
>> index d6c86924f887..94f36c7069ec 100644
>> --- a/drivers/hwmon/pmbus/Makefile
>> +++ b/drivers/hwmon/pmbus/Makefile
>> @@ -9,6 +9,7 @@ obj-$(CONFIG_SENSORS_ACBEL_FSG032) += acbel-fsg032.o
>> obj-$(CONFIG_SENSORS_ADM1266) += adm1266.o
>> obj-$(CONFIG_SENSORS_ADM1275) += adm1275.o
>> obj-$(CONFIG_SENSORS_ADP1050) += adp1050.o
>> +obj-$(CONFIG_SENSORS_APS_379) += aps-379.o
>> obj-$(CONFIG_SENSORS_BEL_PFE) += bel-pfe.o
>> obj-$(CONFIG_SENSORS_BPA_RS600) += bpa-rs600.o
>> obj-$(CONFIG_SENSORS_DELTA_AHE50DC_FAN) += delta-ahe50dc-fan.o
>> diff --git a/drivers/hwmon/pmbus/aps-379.c
>> b/drivers/hwmon/pmbus/aps-379.c
>> new file mode 100644
>> index 000000000000..edc489558437
>> --- /dev/null
>> +++ b/drivers/hwmon/pmbus/aps-379.c
>> @@ -0,0 +1,168 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/*
>> + * Hardware monitoring driver for Sony APS-379 Power Supplies
>> + *
>> + * Copyright 2026 Allied Telesis Labs
>> + */
>> +
>> +#include <linux/i2c.h>
>> +#include <linux/init.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/pmbus.h>
>> +#include "pmbus.h"
>> +
>> +struct aps_379_data {
>> + struct pmbus_driver_info info;
>> + u8 vout_linear_exponent;
>> +};
>> +
>> +#define to_aps_379_data(x) container_of(x, struct aps_379_data, info)
>> +
>> +static const struct i2c_device_id aps_379_id[] = {
>> + { "aps-379", 0 },
>> + {},
>> +};
>> +
>> +static int aps_379_read_byte_data(struct i2c_client *client, int
>> page, int reg)
>> +{
>> + const struct pmbus_driver_info *info =
>> pmbus_get_driver_info(client);
>> + struct aps_379_data *data = to_aps_379_data(info);
>> +
>> + switch (reg) {
>> + case PMBUS_VOUT_MODE:
>> + /*
>> + * The VOUT format used by the chip is linear11,
>> + * not linear16. Report that VOUT is in linear mode
>> + * and return exponent value extracted while probing
>> + * the chip.
>> + */
>> + return data->vout_linear_exponent;
>> + default:
>> + return -ENODATA;
>> + }
>> +}
>> +
>> +/*
>> + * The APS-379 uses linear11 format instead of linear16. We've
>> reported the exponent
>> + * via the PMBUS_VOUT_MODE so we just return the mantissa here.
>> + */
>> +static int aps_379_read_vout(struct i2c_client *client)
>> +{
>> + int ret;
>> +
>> + ret = pmbus_read_word_data(client, 0, 0xff, PMBUS_READ_VOUT);
>> + if (ret < 0)
>> + return ret;
>> +
>> + return sign_extend32(ret & 0x7ff, 11);
>> +}
>> +
>> +static int aps_379_read_word_data(struct i2c_client *client, int
>> page, int phase, int reg)
>> +{
>> + switch (reg) {
>> + case PMBUS_VOUT_UV_WARN_LIMIT:
>> + case PMBUS_VOUT_OV_WARN_LIMIT:
>> + case PMBUS_VOUT_UV_FAULT_LIMIT:
>> + case PMBUS_VOUT_OV_FAULT_LIMIT:
>> + case PMBUS_PIN_OP_WARN_LIMIT:
>> + case PMBUS_POUT_OP_WARN_LIMIT:
>> + case PMBUS_MFR_IIN_MAX:
>> + case PMBUS_MFR_PIN_MAX:
>> + case PMBUS_MFR_VOUT_MIN:
>> + case PMBUS_MFR_VOUT_MAX:
>> + case PMBUS_MFR_IOUT_MAX:
>> + case PMBUS_MFR_POUT_MAX:
>> + case PMBUS_MFR_MAX_TEMP_1:
>> + /* These commands return data but it is
>> invalid/un-documented */
>> + return -ENXIO;
>> + case PMBUS_READ_VOUT:
>> + return aps_379_read_vout(client);
>> + default:
>> + if (reg >= PMBUS_VIRT_BASE)
>> + return -ENXIO;
>> + else
>> + return -ENODATA;
>> + }
>> +}
>> +
>> +static struct pmbus_driver_info aps_379_info = {
>> + .pages = 1,
>> + .format[PSC_VOLTAGE_OUT] = linear,
>> + .format[PSC_CURRENT_OUT] = linear,
>> + .format[PSC_POWER] = linear,
>> + .format[PSC_TEMPERATURE] = linear,
>> + .format[PSC_FAN] = linear,
>> + .func[0] = PMBUS_HAVE_VOUT |
>> + PMBUS_HAVE_IOUT |
>> + PMBUS_HAVE_PIN | PMBUS_HAVE_POUT |
>> + PMBUS_HAVE_TEMP |
>> + PMBUS_HAVE_FAN12,
>> + .read_byte_data = aps_379_read_byte_data,
>> + .read_word_data = aps_379_read_word_data,
>> +};
>> +
>> +static int aps_379_probe(struct i2c_client *client)
>> +{
>> + struct device *dev = &client->dev;
>> + struct pmbus_driver_info *info;
>> + struct aps_379_data *data;
>> + u8 buf[I2C_SMBUS_BLOCK_MAX + 1];
>> + int ret;
>> +
>> + data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + memcpy(&data->info, &aps_379_info, sizeof(*info));
>> + info = &data->info;
>> +
>> + if (!i2c_check_functionality(client->adapter,
>> + I2C_FUNC_SMBUS_READ_BYTE_DATA
>> + | I2C_FUNC_SMBUS_READ_WORD_DATA
>> + | I2C_FUNC_SMBUS_READ_BLOCK_DATA))
>> + return -ENODEV;
>> +
>> + ret = i2c_smbus_read_block_data(client, PMBUS_MFR_MODEL, buf);
>> + if (ret < 0) {
>> + dev_err(dev, "Failed to read Manufacturer Model\n");
>> + return ret;
>> + }
>> +
>> + if (strncasecmp(buf,
>> http://scanmail.trustwave.com/?c=20988&d=-5fM6Qyi3kX42boReXvp_F06nhM1_AVskRzwE-YPiQ&u=http%3a%2f%2faps%5f379%5fid%5b0%5d%2ename
>> strlen(aps_379_id[0].name)) != 0) {
>> + buf[ret] = '\0';
>> + dev_err(dev, "Unsupported Manufacturer Model '%s'\n", buf);
>> + return -ENODEV;
>> + }
>> +
>> + ret = i2c_smbus_read_word_data(client, PMBUS_READ_VOUT);
>> + if (ret < 0) {
>> + dev_err(dev, "Can't get vout exponent.\n");
>> + return ret;
>> + }
>> + data->vout_linear_exponent = (u8)((ret >> 11) & 0x1f);
>> +
>> + return pmbus_do_probe(client, info);
>> +}
>> +
>> +static const struct of_device_id __maybe_unused aps_379_of_match[] = {
>> + { .compatible = "sony,aps-379" },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, aps_379_of_match);
>> +
>> +static struct i2c_driver aps_379_driver = {
>> + .driver = {
>> + .name = "aps-379",
>> + .of_match_table = of_match_ptr(aps_379_of_match),
>> + },
>> + .probe = aps_379_probe,
>> + .id_table = aps_379_id,
>> +};
>> +
>> +module_i2c_driver(aps_379_driver);
>> +
>> +MODULE_AUTHOR("Chris Packham");
>> +MODULE_DESCRIPTION("PMBus driver for Sony APS-379");
>> +MODULE_LICENSE("GPL");
>> +MODULE_IMPORT_NS("PMBUS");
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox