* Re: [PATCH v2 2/2] hwmon: (pmbus/q54sj108a2) Add support for q50sn12072 and q54sn120a1
From: Brian Chiang @ 2026-04-01 7:38 UTC (permalink / raw)
To: Guenter Roeck
Cc: Cheng.JackHY, chiang.brian, conor+dt, devicetree, krzk+dt,
linux-hwmon, linux-kernel, robh
In-Reply-To: <79e3b8f1-f8ba-41af-96d4-b9a1b84ef810@roeck-us.net>
On Thu, Mar 26, 2026 at 09:29:38AM -0700, Guenter Roeck wrote:
>On Thu, Mar 26, 2026 at 01:48:06PM +0000, Brian Chiang wrote:
>> From: Jack Cheng <cheng.jackhy@inventec.com>
>>
>> The Q50SN12072 and Q54SN120A1 are high-efficiency, high-density DC-DC power
>> module from Delta Power Modules.
>>
>> The Q50SN12072, quarter brick, single output 12V. This product provides up
>> to 1200 watts of output power at 38~60V. The Q50SN12072 offers peak
>> efficiency up to 98.3%@54Vin.
>>
>> The Q54SN120A1, quarter brick, single output 12V. This product provides up
>> to 1300 watts of output power at 40~60V. The Q54SN120A1 offers peak
>> efficiency up to 98.1%@54Vin.
>>
>> Add support for them to q54sj108a2 driver.
>>
>> Signed-off-by: Jack Cheng <cheng.jackhy@inventec.com>
>> Co-developed-by: Brian Chiang <chiang.brian@inventec.com>
>> Signed-off-by: Brian Chiang <chiang.brian@inventec.com>
>> ---
>> drivers/hwmon/pmbus/q54sj108a2.c | 97 ++++++++++++++++++++++++++++------------
>> 1 file changed, 68 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/hwmon/pmbus/q54sj108a2.c b/drivers/hwmon/pmbus/q54sj108a2.c
>> index d5d60a9af8c5..cc2b32ad935c 100644
>> --- a/drivers/hwmon/pmbus/q54sj108a2.c
>> +++ b/drivers/hwmon/pmbus/q54sj108a2.c
>> @@ -22,7 +22,9 @@
>> #define PMBUS_FLASH_KEY_WRITE 0xEC
>>
>> enum chips {
>> - q54sj108a2
>> + q50sn12072,
>> + q54sj108a2,
>> + q54sn120a1
>> };
>>
>> enum {
>> @@ -55,10 +57,24 @@ struct q54sj108a2_data {
>> #define to_psu(x, y) container_of((x), struct q54sj108a2_data, debugfs_entries[(y)])
>>
>> static struct pmbus_driver_info q54sj108a2_info[] = {
>> - [q54sj108a2] = {
>> + [q50sn12072] = {
>> .pages = 1,
>> + /* Source : Delta Q50SN12072 */
>> + .format[PSC_VOLTAGE_OUT] = linear,
>> + .format[PSC_TEMPERATURE] = linear,
>> + .format[PSC_VOLTAGE_IN] = linear,
>> + .format[PSC_CURRENT_OUT] = linear,
>>
>> + .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_IIN | PMBUS_HAVE_PIN |
>> + PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT |
>> + PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT |
>> + PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP |
>> + PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_POUT,
>> + },
>> + [q54sj108a2] = {
>> + .pages = 1,
>> /* Source : Delta Q54SJ108A2 */
>> + .format[PSC_VOLTAGE_OUT] = linear,
>> .format[PSC_TEMPERATURE] = linear,
>> .format[PSC_VOLTAGE_IN] = linear,
>> .format[PSC_CURRENT_OUT] = linear,
>> @@ -69,6 +85,20 @@ static struct pmbus_driver_info q54sj108a2_info[] = {
>> PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP |
>> PMBUS_HAVE_STATUS_INPUT,
>> },
>> + [q54sn120a1] = {
>> + .pages = 1,
>> + /* Source : Delta Q54SN120A1 */
>> + .format[PSC_VOLTAGE_OUT] = linear,
>> + .format[PSC_TEMPERATURE] = linear,
>> + .format[PSC_VOLTAGE_IN] = linear,
>> + .format[PSC_CURRENT_OUT] = linear,
>> +
>> + .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_IIN | PMBUS_HAVE_PIN |
>> + PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT |
>> + PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT |
>> + PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP |
>> + PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_POUT,
>> + },
>> };
>>
>> static ssize_t q54sj108a2_debugfs_read(struct file *file, char __user *buf,
>> @@ -270,7 +300,9 @@ static const struct file_operations q54sj108a2_fops = {
>> };
>>
>> static const struct i2c_device_id q54sj108a2_id[] = {
>> + { "q50sn12072", q50sn12072 },
>> { "q54sj108a2", q54sj108a2 },
>> + { "q54sn120a1", q54sn120a1 },
>> { },
>> };
>>
>> @@ -280,6 +312,7 @@ static int q54sj108a2_probe(struct i2c_client *client)
>> {
>> struct device *dev = &client->dev;
>> u8 buf[I2C_SMBUS_BLOCK_MAX + 1];
>> + const struct i2c_device_id *mid;
>> enum chips chip_id;
>> int ret, i;
>> struct dentry *debugfs;
>> @@ -292,14 +325,9 @@ static int q54sj108a2_probe(struct i2c_client *client)
>> I2C_FUNC_SMBUS_BLOCK_DATA))
>> return -ENODEV;
>>
>> - if (client->dev.of_node)
>> - chip_id = (enum chips)(unsigned long)of_device_get_match_data(dev);
>> - else
>> - chip_id = i2c_match_id(q54sj108a2_id, client)->driver_data;
>> -
>> ret = i2c_smbus_read_block_data(client, PMBUS_MFR_ID, buf);
>> if (ret < 0) {
>> - dev_err(&client->dev, "Failed to read Manufacturer ID\n");
>> + dev_err(dev, "Failed to read Manufacturer ID\n");
>> return ret;
>> }
>> if (ret != 6 || strncmp(buf, "DELTA", 5)) {
>> @@ -308,19 +336,25 @@ static int q54sj108a2_probe(struct i2c_client *client)
>> return -ENODEV;
>> }
>>
>> - /*
>> - * The chips support reading PMBUS_MFR_MODEL.
>> - */
>> ret = i2c_smbus_read_block_data(client, PMBUS_MFR_MODEL, buf);
>> if (ret < 0) {
>> dev_err(dev, "Failed to read Manufacturer Model\n");
>> return ret;
>> }
>> - if (ret != 14 || strncmp(buf, "Q54SJ108A2", 10)) {
>> + for (mid = q54sj108a2_id; mid->name[0]; mid++) {
>> + if (ret == strlen(mid->name) && !strncasecmp(mid->name, buf, ret))
>> + break;
>> + }
>> + if (!mid->name[0]) {
>> buf[ret] = '\0';
>> dev_err(dev, "Unsupported Manufacturer Model '%s'\n", buf);
>> return -ENODEV;
>> }
>
>>From Sashiko feedback:
>
>In the original driver, the PMBUS_MFR_MODEL response length was explicitly
>expected to be 14 bytes (if (ret != 14 || strncmp(buf, "Q54SJ108A2", 10))),
>indicating the hardware returns the 10-character name padded with 4 extra
>bytes. The patch changes the detection logic to loop through supported
>devices and strictly require the returned length to match the device name's
>length exactly (`ret == strlen(mid->name)`). Since `ret` will be 14 for the
>original hardware, and strlen("q54sj108a2") is 10, the condition 14 == 10
>evaluates to false. This causes the loop to exit without matching,
>erroneously printing 'Unsupported Manufacturer Model' and returning -ENODEV.
>This completely breaks driver probing and hardware monitoring for the
>pre-existing Q54SJ108A2 device."
Thank you for the explanation. Maybe we should simply match the manufacturer
model and remove the strict length comparison to prevent it from breaking
the driver probing. I will add this change in v3.
>
>> + chip_id = mid->driver_data;
>> +
>> + if (strcmp(client->name, mid->name) != 0)
>> + dev_notice(dev, "Device mismatch: Configured %s, detected %s\n",
>> + client->name, mid->name);
>>
>> ret = i2c_smbus_read_block_data(client, PMBUS_MFR_REVISION, buf);
>> if (ret < 0) {
>> @@ -341,6 +375,7 @@ static int q54sj108a2_probe(struct i2c_client *client)
>> if (!psu)
>> return 0;
>>
>> + psu->chip = chip_id;
>> psu->client = client;
>>
>> debugfs = pmbus_get_debugfs_dir(client);
>> @@ -359,9 +394,6 @@ static int q54sj108a2_probe(struct i2c_client *client)
>> debugfs_create_file("write_protect", 0444, q54sj108a2_dir,
>> &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_WRITEPROTECT],
>> &q54sj108a2_fops);
>> - debugfs_create_file("store_default", 0200, q54sj108a2_dir,
>> - &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_STOREDEFAULT],
>> - &q54sj108a2_fops);
>> debugfs_create_file("vo_ov_response", 0644, q54sj108a2_dir,
>> &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_VOOV_RESPONSE],
>> &q54sj108a2_fops);
>> @@ -383,27 +415,34 @@ static int q54sj108a2_probe(struct i2c_client *client)
>> debugfs_create_file("mfr_location", 0444, q54sj108a2_dir,
>> &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_MFR_LOCATION],
>> &q54sj108a2_fops);
>> - debugfs_create_file("blackbox_erase", 0200, q54sj108a2_dir,
>> - &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_BLACKBOX_ERASE],
>> - &q54sj108a2_fops);
>> debugfs_create_file("blackbox_read_offset", 0444, q54sj108a2_dir,
>> &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_BLACKBOX_READ_OFFSET],
>> &q54sj108a2_fops);
>
>What is the purpose/value of keeping this file outside the if() block ?
Thank you for catching this. It was an oversight in v2, the
`blackbox_read_offset` should have been kept inside of the block.
I'll add this change in v3.
>
>> - debugfs_create_file("blackbox_set_offset", 0200, q54sj108a2_dir,
>> - &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_BLACKBOX_SET_OFFSET],
>> - &q54sj108a2_fops);
>> - debugfs_create_file("blackbox_read", 0444, q54sj108a2_dir,
>> - &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_BLACKBOX_READ],
>> - &q54sj108a2_fops);
>> - debugfs_create_file("flash_key", 0444, q54sj108a2_dir,
>> - &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_FLASH_KEY],
>> - &q54sj108a2_fops);
>> + if (psu->chip == q54sj108a2) {
>> + debugfs_create_file("store_default", 0200, q54sj108a2_dir,
>> + &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_STOREDEFAULT],
>> + &q54sj108a2_fops);
>> + debugfs_create_file("blackbox_erase", 0200, q54sj108a2_dir,
>> + &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_BLACKBOX_ERASE],
>> + &q54sj108a2_fops);
>> + debugfs_create_file("blackbox_set_offset", 0200, q54sj108a2_dir,
>> + &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_BLACKBOX_SET_OFFSET],
>> + &q54sj108a2_fops);
>> + debugfs_create_file("blackbox_read", 0444, q54sj108a2_dir,
>> + &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_BLACKBOX_READ],
>> + &q54sj108a2_fops);
>> + debugfs_create_file("flash_key", 0444, q54sj108a2_dir,
>> + &psu->debugfs_entries[Q54SJ108A2_DEBUGFS_FLASH_KEY],
>> + &q54sj108a2_fops);
>> + }
>>
>> return 0;
>> }
>>
>> static const struct of_device_id q54sj108a2_of_match[] = {
>> - { .compatible = "delta,q54sj108a2", .data = (void *)q54sj108a2 },
>> + { .compatible = "delta,q50sn12072" },
>> + { .compatible = "delta,q54sj108a2" },
>> + { .compatible = "delta,q54sn120a1" },
>
>Why drop .data here ?
I would like to drop .data since it was previously consumed by
`of_device_get_match_data()`, which has been removed in v2 changes.
>
>Thanks,
>Guenter
>
>> { },
>> };
>>
>> @@ -421,6 +460,6 @@ static struct i2c_driver q54sj108a2_driver = {
>> module_i2c_driver(q54sj108a2_driver);
>>
>> MODULE_AUTHOR("Xiao.Ma <xiao.mx.ma@deltaww.com>");
>> -MODULE_DESCRIPTION("PMBus driver for Delta Q54SJ108A2 series modules");
>> +MODULE_DESCRIPTION("PMBus driver for Delta Q54SJ108A2 and compatibles");
>> MODULE_LICENSE("GPL");
>> MODULE_IMPORT_NS("PMBUS");
>>
>> --
>> 2.43.0
>>
^ permalink raw reply
* [PATCH 3/4] arm64: dts: qcom: hamoa-pmics: define VADC for pmk8550
From: Aleksandrs Vinarskis @ 2026-04-01 7:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans de Goede, Ilpo Järvinen,
Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett
In-Reply-To: <20260401-dell-xps-9345-ec-v1-0-afa5cacd49be@vinarskis.com>
Follow pattern of pmk8350 to add missing pmk8550 VADC to hamoa.
Register address of 0x9000 matches example schema for spmi-adc5-gen3.
Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com>
---
arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
index 6a31a0adf8be472badea502a916cdbc9477e9f2b..58c0dd3ccca70bce3424f83bfd5a52b1fef35c2e 100644
--- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
@@ -218,6 +218,17 @@ pon_resin: resin {
};
};
+ pmk8550_vadc: adc@9000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x9000>, <0x9100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
+ };
+
pmk8550_rtc: rtc@6100 {
compatible = "qcom,pmk8350-rtc";
reg = <0x6100>, <0x6200>;
--
2.53.0
^ permalink raw reply related
* [PATCH 2/4] platform: arm64: dell-xps-ec: new driver
From: Aleksandrs Vinarskis @ 2026-04-01 7:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans de Goede, Ilpo Järvinen,
Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett
In-Reply-To: <20260401-dell-xps-9345-ec-v1-0-afa5cacd49be@vinarskis.com>
Introduce EC driver for Dell XPS 13 9345 (codename 'tributo') which may
partially of fully compatible with Snapdragon-based Dell Latitude,
Inspiron ('thena'). Primary function of this driver is unblock EC's
thermal management, specifically to provide it with necessary
information to control device fans, peripherals power.
The driver was developed primarily by analyzing ACPI DSDT's _DSM and
i2c dumps of communication between SoC and EC. Changes to Windows
driver's behavior include increasing temperature feed loop from ~50ms
to 100ms here.
While Xps's EC is rather complex and controls practically all device
peripherals including touch row's brightness and special keys such as
mic mute, these do not go over this particular i2c interface.
Not yet implemented features:
- On lid-close IRQ event is registered. Windows performs what to
appears to be thermistor constants readout, though its not obvious
what it used for.
- According to ACPI's _DSM there is a method to readout fans' RPM.
- Initial thermistor constants were sniffed from Windows, these can be
likely fine tuned for better cooling performance.
- There is additional temperature reading that Windows sents to EC but
more rare than others, likely SoC T_j / TZ98 or TZ4. This is the only
thermal zone who's reading can exceed 115C without triggering thermal
shutdown.
- Given similarities between 'tributo' and 'thena' platforms, including
EC i2c address, driver can be potentially extended to support both.
Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com>
---
MAINTAINERS | 1 +
drivers/platform/arm64/Kconfig | 12 ++
drivers/platform/arm64/Makefile | 1 +
drivers/platform/arm64/dell-xps-ec.c | 269 +++++++++++++++++++++++++++++++++++
4 files changed, 283 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fe3f2fc4fbc087d8041f97708fbb93722f7d1882..f82c7f6c7377d3f2ff0ae1be263d854749541f03 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7240,6 +7240,7 @@ DELL XPS EMBEDDED CONTROLLER DRIVER
M: Aleksandrs Vinarskis <alex@vinarskis.com>
S: Maintained
F: Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml
+F: drivers/platform/arm64/dell-xps-ec.c
DELTA AHE-50DC FAN CONTROL MODULE DRIVER
M: Zev Weiss <zev@bewilderbeest.net>
diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig
index 10f905d7d6bfa5fad30a0689d3a20481268c781e..0bc8f016032bb05cb3a7cc50bdf1092da04153bc 100644
--- a/drivers/platform/arm64/Kconfig
+++ b/drivers/platform/arm64/Kconfig
@@ -33,6 +33,18 @@ config EC_ACER_ASPIRE1
laptop where this information is not properly exposed via the
standard ACPI devices.
+config EC_DELL_XPS
+ tristate "Dell XPS 9345 Embedded Controller driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on I2C
+ depends on IIO
+ help
+ Driver for the Embedded Controller in the Qualcomm Snapdragon-based
+ Dell XPS 13 9345, which handles thermal management and fan speed
+ control.
+
+ Say M or Y here to include this support.
+
config EC_HUAWEI_GAOKUN
tristate "Huawei Matebook E Go Embedded Controller driver"
depends on ARCH_QCOM || COMPILE_TEST
diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makefile
index 60c131cff6a15bb51a49c9edab95badf513ee0f6..6768dc6c2310837374e67381cfc729bed1fdaaef 100644
--- a/drivers/platform/arm64/Makefile
+++ b/drivers/platform/arm64/Makefile
@@ -6,6 +6,7 @@
#
obj-$(CONFIG_EC_ACER_ASPIRE1) += acer-aspire1-ec.o
+obj-$(CONFIG_EC_DELL_XPS) += dell-xps-ec.o
obj-$(CONFIG_EC_HUAWEI_GAOKUN) += huawei-gaokun-ec.o
obj-$(CONFIG_EC_LENOVO_YOGA_C630) += lenovo-yoga-c630.o
obj-$(CONFIG_EC_LENOVO_THINKPAD_T14S) += lenovo-thinkpad-t14s.o
diff --git a/drivers/platform/arm64/dell-xps-ec.c b/drivers/platform/arm64/dell-xps-ec.c
new file mode 100644
index 0000000000000000000000000000000000000000..5ea8f30931d8b61acbb948d8617dde3681fb8de3
--- /dev/null
+++ b/drivers/platform/arm64/dell-xps-ec.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2026, Aleksandrs Vinarskis <alex@vinarskis.com>
+ */
+
+#include <linux/array_size.h>
+#include <linux/devm-helpers.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/iio/consumer.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/workqueue.h>
+
+#define DELL_XPS_EC_SUSPEND_CMD 0xb9
+#define DELL_XPS_EC_SUSPEND_MSG_LEN 64
+
+#define DELL_XPS_EC_TEMP_CMD0 0xfb
+#define DELL_XPS_EC_TEMP_CMD1 0x20
+#define DELL_XPS_EC_TEMP_CMD3 0x02
+#define DELL_XPS_EC_TEMP_MSG_LEN 6
+#define DELL_XPS_EC_TEMP_INTERVAL_MS 100
+
+/*
+ * Format:
+ * - header/unknown (2 bytes)
+ * - per-thermistor entries (3 bytes): thermistor_id, param1, param2
+ */
+static const u8 dell_xps_ec_thermistor_profile[] = {
+ 0xff, 0x54,
+ 0x01, 0x00, 0x2b, /* sys_therm0 */
+ 0x02, 0x44, 0x2a, /* sys_therm1 */
+ 0x03, 0x44, 0x2b, /* sys_therm2 */
+ 0x04, 0x44, 0x28, /* sys_therm3 */
+ 0x05, 0x55, 0x2a, /* sys_therm4 */
+ 0x06, 0x44, 0x26, /* sys_therm5 */
+ 0x07, 0x44, 0x2b, /* sys_therm6 */
+};
+
+/*
+ * Mapping from IIO channel name to EC command byte
+ */
+static const struct {
+ const char *name;
+ u8 cmd;
+} dell_xps_ec_therms[] = {
+ /* TODO: 0x01 is sent only occasionally, likely TZ98 or TZ4 */
+ { "sys_therm0", 0x02 },
+ { "sys_therm1", 0x03 },
+ { "sys_therm2", 0x04 },
+ { "sys_therm3", 0x05 },
+ { "sys_therm4", 0x06 },
+ { "sys_therm5", 0x07 },
+ { "sys_therm6", 0x08 },
+};
+
+struct dell_xps_ec {
+ struct device *dev;
+ struct i2c_client *client;
+ struct iio_channel *therm_channels[ARRAY_SIZE(dell_xps_ec_therms)];
+ struct delayed_work temp_work;
+};
+
+static int dell_xps_ec_suspend_cmd(struct dell_xps_ec *ec, bool suspend)
+{
+ u8 buf[DELL_XPS_EC_SUSPEND_MSG_LEN] = {};
+ int ret;
+
+ buf[0] = DELL_XPS_EC_SUSPEND_CMD;
+ buf[1] = suspend ? 0x01 : 0x00;
+ /* bytes 2..63 remain zero */
+
+ ret = i2c_master_send(ec->client, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int dell_xps_ec_send_temp(struct dell_xps_ec *ec, u8 cmd_byte,
+ int milli_celsius)
+{
+ u8 buf[DELL_XPS_EC_TEMP_MSG_LEN];
+ u16 deci_celsius;
+ int ret;
+
+ /* Convert milli-Celsius to deci-Celsius (Celsius * 10) */
+ deci_celsius = milli_celsius / 100;
+
+ buf[0] = DELL_XPS_EC_TEMP_CMD0;
+ buf[1] = DELL_XPS_EC_TEMP_CMD1;
+ buf[2] = cmd_byte;
+ buf[3] = DELL_XPS_EC_TEMP_CMD3;
+ buf[4] = deci_celsius & 0xff; /* LSB */
+ buf[5] = (deci_celsius >> 8) & 0xff; /* MSB */
+
+ ret = i2c_master_send(ec->client, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void dell_xps_ec_temp_work_fn(struct work_struct *work)
+{
+ struct dell_xps_ec *ec = container_of(work, struct dell_xps_ec,
+ temp_work.work);
+ int val, ret, i;
+
+ for (i = 0; i < ARRAY_SIZE(dell_xps_ec_therms); i++) {
+ if (!ec->therm_channels[i])
+ continue;
+
+ ret = iio_read_channel_processed(ec->therm_channels[i], &val);
+ if (ret < 0) {
+ dev_err_ratelimited(ec->dev,
+ "Failed to read thermistor %s: %d\n",
+ dell_xps_ec_therms[i].name, ret);
+ continue;
+ }
+
+ ret = dell_xps_ec_send_temp(ec, dell_xps_ec_therms[i].cmd, val);
+ if (ret < 0) {
+ dev_err_ratelimited(ec->dev,
+ "Failed to send temp for %s: %d\n",
+ dell_xps_ec_therms[i].name, ret);
+ }
+ }
+
+ schedule_delayed_work(&ec->temp_work,
+ msecs_to_jiffies(DELL_XPS_EC_TEMP_INTERVAL_MS));
+}
+
+static irqreturn_t dell_xps_ec_irq_handler(int irq, void *data)
+{
+ struct dell_xps_ec *ec = data;
+
+ /*
+ * TODO: IRQ is fired on lid-close. Follow Windows example to read out
+ * the thermistor thresholds and potentially fan speeds.
+ */
+ dev_info_ratelimited(ec->dev, "IRQ triggered! (irq=%d)\n", irq);
+
+ return IRQ_HANDLED;
+}
+
+static int dell_xps_ec_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct dell_xps_ec *ec;
+ int ret, i;
+
+ ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL);
+ if (!ec)
+ return -ENOMEM;
+
+ ec->dev = dev;
+ ec->client = client;
+ i2c_set_clientdata(client, ec);
+
+ /* Set default thermistor profile */
+ ret = i2c_master_send(client, dell_xps_ec_thermistor_profile,
+ sizeof(dell_xps_ec_thermistor_profile));
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to set thermistor profile\n");
+
+ /* Get IIO channels for thermistors */
+ for (i = 0; i < ARRAY_SIZE(dell_xps_ec_therms); i++) {
+ ec->therm_channels[i] = devm_iio_channel_get(dev,
+ dell_xps_ec_therms[i].name);
+ if (IS_ERR(ec->therm_channels[i])) {
+ ret = PTR_ERR(ec->therm_channels[i]);
+ ec->therm_channels[i] = NULL;
+ if (ret == -EPROBE_DEFER)
+ return ret;
+ dev_warn(dev, "Thermistor %s not available: %d\n",
+ dell_xps_ec_therms[i].name, ret);
+ }
+ }
+
+ /* Start periodic temperature reporting */
+ ret = devm_delayed_work_autocancel(dev, &ec->temp_work,
+ dell_xps_ec_temp_work_fn);
+ if (ret)
+ return ret;
+ schedule_delayed_work(&ec->temp_work,
+ msecs_to_jiffies(DELL_XPS_EC_TEMP_INTERVAL_MS));
+ dev_info(dev, "Started periodic temperature reporting to EC every %d ms\n",
+ DELL_XPS_EC_TEMP_INTERVAL_MS);
+
+ /* Request IRQ for EC events */
+ ret = devm_request_threaded_irq(dev, client->irq, NULL,
+ dell_xps_ec_irq_handler,
+ IRQF_ONESHOT, dev_name(dev), ec);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to request IRQ\n");
+
+ return 0;
+}
+
+/*
+ * Notify EC of suspend
+ *
+ * This will:
+ * - Ramp down the fans
+ * - Cut power to display/trackpad/keyboard/touch row
+ * - Periodically (?) power them back, such that wake-up source still works
+ */
+static int dell_xps_ec_suspend(struct device *dev)
+{
+ struct dell_xps_ec *ec = dev_get_drvdata(dev);
+
+ cancel_delayed_work_sync(&ec->temp_work);
+
+ return dell_xps_ec_suspend_cmd(ec, true);
+}
+
+/*
+ * Notify EC of resume
+ *
+ * This will undo the suspend actions
+ * Without the resume signal, device would wake up but be forced back into
+ * suspend by EC within seconds
+ */
+static int dell_xps_ec_resume(struct device *dev)
+{
+ struct dell_xps_ec *ec = dev_get_drvdata(dev);
+ int ret;
+
+ ret = dell_xps_ec_suspend_cmd(ec, false);
+ if (ret)
+ return ret;
+
+ schedule_delayed_work(&ec->temp_work,
+ msecs_to_jiffies(DELL_XPS_EC_TEMP_INTERVAL_MS));
+ return 0;
+}
+
+static const struct of_device_id dell_xps_ec_of_match[] = {
+ { .compatible = "dell,xps13-9345-ec" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, dell_xps_ec_of_match);
+
+static const struct i2c_device_id dell_xps_ec_i2c_id[] = {
+ { "dell-xps-ec" },
+ {}
+};
+MODULE_DEVICE_TABLE(i2c, dell_xps_ec_i2c_id);
+
+static const struct dev_pm_ops dell_xps_ec_pm_ops = {
+ SYSTEM_SLEEP_PM_OPS(dell_xps_ec_suspend, dell_xps_ec_resume)
+};
+
+static struct i2c_driver dell_xps_ec_driver = {
+ .driver = {
+ .name = "dell-xps-ec",
+ .of_match_table = dell_xps_ec_of_match,
+ .pm = &dell_xps_ec_pm_ops,
+ },
+ .probe = dell_xps_ec_probe,
+ .id_table = dell_xps_ec_i2c_id,
+};
+module_i2c_driver(dell_xps_ec_driver);
+
+MODULE_AUTHOR("Aleksandrs Vinarskis <alex@vinarskis.com>");
+MODULE_DESCRIPTION("Dell XPS 13 9345 Embedded Controller");
+MODULE_LICENSE("GPL");
--
2.53.0
^ permalink raw reply related
* [PATCH 1/4] dt-bindings: platform: introduce EC for Dell XPS 13 9345
From: Aleksandrs Vinarskis @ 2026-04-01 7:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans de Goede, Ilpo Järvinen,
Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett
In-Reply-To: <20260401-dell-xps-9345-ec-v1-0-afa5cacd49be@vinarskis.com>
Add bindings for Embedded Controller (EC) in Dell XPS 13 9345 (platform
codename 'tributo'). It may be partially or fully compatible with EC
found in Snapdragon-based Dell Latitude, Inspiron ('thena').
Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com>
---
.../embedded-controller/dell,xps13-9345-ec.yaml | 86 ++++++++++++++++++++++
MAINTAINERS | 5 ++
2 files changed, 91 insertions(+)
diff --git a/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..30dc6dcd8c9f0312fdb4eafdef96bf0ce4975798
--- /dev/null
+++ b/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/embedded-controller/dell,xps13-9345-ec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Dell XPS 13 9345 Embedded Controller
+
+maintainers:
+ - Aleksandrs Vinarskis <alex@vinarskis.com>
+
+description:
+ The Dell XPS 13 9345 has an Embedded Controller (EC) which handles thermal and power
+ management. It is communicating with SoC over multiple i2c busses. Particular driver
+ is for EC subsystem that handles fan speed control, thermal shutdown, peripherals
+ supply including trackpad, touch-row, display.
+
+properties:
+ compatible:
+ const: dell,xps13-9345-ec
+
+ reg:
+ const: 0x3b
+
+ interrupts:
+ maxItems: 1
+
+ io-channels:
+ description:
+ ADC channels connected to the 7 onboard thermistors on PMK8550.
+ EC requires frequent thermal readings of these channels to perform
+ automated fan speed control.
+ items:
+ - description: ADC channel for sys_therm0
+ - description: ADC channel for sys_therm1
+ - description: ADC channel for sys_therm2
+ - description: ADC channel for sys_therm3
+ - description: ADC channel for sys_therm4
+ - description: ADC channel for sys_therm5
+ - description: ADC channel for sys_therm6
+
+ io-channel-names:
+ items:
+ - const: sys_therm0
+ - const: sys_therm1
+ - const: sys_therm2
+ - const: sys_therm3
+ - const: sys_therm4
+ - const: sys_therm5
+ - const: sys_therm6
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - io-channels
+ - io-channel-names
+
+additionalProperties: false
+
+examples:
+ - |+
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ embedded-controller@3b {
+ compatible = "dell,xps13-9345-ec";
+ reg = <0x3b>;
+ interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_LOW>;
+
+ io-channels = <&pmk8550_vadc PM8350_ADC7_GPIO3_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_GPIO4_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM5_100K_PU(1)>;
+ io-channel-names = "sys_therm0", "sys_therm1", "sys_therm2",
+ "sys_therm3", "sys_therm4", "sys_therm5",
+ "sys_therm6";
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index ff935e197c2153a9c52c94d6ead1df54543a36d4..fe3f2fc4fbc087d8041f97708fbb93722f7d1882 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7236,6 +7236,11 @@ S: Maintained
F: Documentation/ABI/testing/sysfs-class-firmware-attributes
F: drivers/platform/x86/dell/dell-wmi-sysman/
+DELL XPS EMBEDDED CONTROLLER DRIVER
+M: Aleksandrs Vinarskis <alex@vinarskis.com>
+S: Maintained
+F: Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml
+
DELTA AHE-50DC FAN CONTROL MODULE DRIVER
M: Zev Weiss <zev@bewilderbeest.net>
L: linux-hwmon@vger.kernel.org
--
2.53.0
^ permalink raw reply related
* [PATCH 4/4] arm64: dts: qcom: x1e80100-dell-xps13-9345: introduce EC
From: Aleksandrs Vinarskis @ 2026-04-01 7:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans de Goede, Ilpo Järvinen,
Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett
In-Reply-To: <20260401-dell-xps-9345-ec-v1-0-afa5cacd49be@vinarskis.com>
Describe embedded controller, its interrupt and required thermal zones.
Add EC's reset GPIO to reserved range, as triggering it during device
operation leads to unrecoverable and unusable state.
Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com>
---
.../boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 91 +++++++++++++++++++++-
1 file changed, 89 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts
index ce7b10ea89b6dcb2a4a65c114037f4c90a4b0c6d..32e7134316709f5574d43d9edd83c77fb7d23451 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@@ -759,8 +760,29 @@ retimer_ss0_con_sbu_out: endpoint {
&i2c5 {
clock-frequency = <100000>;
- status = "disabled";
- /* EC @0x3b */
+ status = "okay";
+
+ embedded-controller@3b {
+ compatible = "dell,xps13-9345-ec";
+ reg = <0x3b>;
+
+ interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&ec_int_n_default>;
+ pinctrl-names = "default";
+
+ io-channels = <&pmk8550_vadc PM8350_ADC7_GPIO3_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_GPIO4_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM5_100K_PU(1)>;
+
+ io-channel-names = "sys_therm0", "sys_therm1", "sys_therm2",
+ "sys_therm3", "sys_therm4", "sys_therm5",
+ "sys_therm6";
+ };
};
&i2c7 {
@@ -1025,6 +1047,64 @@ rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
};
};
+&pmk8550_vadc {
+ /* sys_therm0, around DRAM */
+ channel@14c {
+ reg = <PM8350_ADC7_GPIO3_100K_PU(1)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ label = "sys_therm0";
+ };
+
+ /* sys_therm1, around left Type-C charging controller */
+ channel@14d {
+ reg = <PM8350_ADC7_GPIO4_100K_PU(1)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ label = "sys_therm1";
+ };
+
+ /* sys_therm2, around upper-left side of motherboard */
+ channel@144 {
+ reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ label = "sys_therm2";
+ };
+
+ /* sys_therm3, around right Type-C charging controller */
+ channel@145 {
+ reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ label = "sys_therm3";
+ };
+
+ /* sys_therm4, around SSD connector */
+ channel@146 {
+ reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ label = "sys_therm4";
+ };
+
+ /* sys_therm5, around battery charging circuit */
+ channel@147 {
+ reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ label = "sys_therm5";
+ };
+
+ /* sys_therm6, around keyboard */
+ channel@148 {
+ reg = <PM8350_ADC7_AMUX_THM5_100K_PU(1)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ label = "sys_therm6";
+ };
+};
+
&qupv3_0 {
status = "okay";
};
@@ -1071,6 +1151,7 @@ &smb2360_1_eusb2_repeater {
&tlmm {
gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */
+ <65 1>, /* EC Reset */
<76 4>, /* SPI19 (TZ Protected) */
<238 1>; /* UFS Reset */
@@ -1081,6 +1162,12 @@ cam_indicator_en: cam-indicator-en-state {
bias-disable;
};
+ ec_int_n_default: ec-int-n-state {
+ pins = "gpio66";
+ function = "gpio";
+ bias-disable;
+ };
+
edp_bl_en: edp-bl-en-state {
pins = "gpio74";
function = "gpio";
--
2.53.0
^ permalink raw reply related
* [PATCH 0/4] Introduce EC driver for Snapdragon X1E based Dell XPS 13 9345
From: Aleksandrs Vinarskis @ 2026-04-01 7:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans de Goede, Ilpo Järvinen,
Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett
This series adds Embedded Controller (EC) driver for Dell XPS 13 9345.
While EC appears to control most of device's peripherals, particular
driver addresses power and thermal managment issues. Key operational
principle involves initial thermistor constants configuration followed
by a periodic reporting of these onboard thermistor values from across
the motherboard to the EC. The latter then handles fan ramp-up/
ramp-down internally. Suspend/Resume must be likewise propagated to EC
for power management.
The driver was developed primarily by analyzing ACPI DSDT's _DSM and
i2c dumps of communication between SoC and EC during various stages of
operation (bootup, suspend, resume).
With EC driver in place, the following issues are addressed:
1. Fans were not properly cooling the laptop, would kick in late and
spin lazily, resulting in heavy throttling. With EC driver fans
start sooner and hit high RPM under heavy load.
2. Fans were not stopping once SoC temperature dropped, they would keep
slowly spinning irrespective of suspend and/or closed lid until the
next powercycle. With EC driver shortly after SoC temperature drops,
thermistors temperature drops, and fans ramp-down.
3. Keyboard and touch row backlight were not turning off during
suspend - only lid close would power off the touch row. With EC
driver behavior matches that of Windows, suspending device with lid
open powers off the peripherals.
As thermistor readout depends on pmic's ADCs, this series introduces
EC driver and its schema, adds missing ADC to hamoa-pmics, and finally
adds thermistor and EC nodes to x1e80100-dell-xps13-9345.dts.
Additional findings:
- Max fan speed depends on Dell's power mode settings, configurable in
BIOS or using Windows app (relies on ACPI-WMI). It appears best
cooling performance is achieved under 'Ultra Performance' profile.
- When the said power mode is changed using Windows app, EC IRQ is
triggered. Windows performs what appears to be thermistor contants
readout, though its not obvious what it is used for.
- Given similarities between Dell XPS 13 series (codename 'tributo')
and Snapdragon-based Latitude, Inspiron ('thena'), including matching
EC address and response to suspend/resume command the EC driver can
be likely used for both, though in-depth testing on 'thena' is
required.
Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com>
---
Aleksandrs Vinarskis (4):
dt-bindings: platform: introduce EC for Dell XPS 13 9345
platform: arm64: dell-xps-ec: new driver
arm64: dts: qcom: hamoa-pmics: define VADC for pmk8550
arm64: dts: qcom: x1e80100-dell-xps13-9345: introduce EC
.../embedded-controller/dell,xps13-9345-ec.yaml | 86 +++++++
MAINTAINERS | 6 +
arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 11 +
.../boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 91 ++++++-
drivers/platform/arm64/Kconfig | 12 +
drivers/platform/arm64/Makefile | 1 +
drivers/platform/arm64/dell-xps-ec.c | 269 +++++++++++++++++++++
7 files changed, 474 insertions(+), 2 deletions(-)
---
base-commit: 3b058d1aeeeff27a7289529c4944291613b364e9
change-id: 20260331-dell-xps-9345-ec-e5f49d1bef61
Best regards,
--
Aleksandrs Vinarskis <alex@vinarskis.com>
^ permalink raw reply
* [PATCH] arm64: dts: qcom: kodiak: increase fastrpc compute-cb session slots
From: Jianping Li @ 2026-04-01 7:33 UTC (permalink / raw)
To: andersson, konradybcio, robh, krzk+dt
Cc: Jianping Li, conor+dt, linux-arm-msm, devicetree, linux-kernel,
ekansh.gupta
Some workloads on Kodiak can exhaust FastRPC sessions when multiple
compute clients open contexts concurrently, leading to -EBUSY failures.
Describe the compute context bank with qcom,nsessions = <5> so the
driver can provision enough session slots for the compute-cb instance.
Signed-off-by: Jianping Li <jianping.li@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 6079e67ea829..5bd20909f9db 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -4465,6 +4465,7 @@ compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1805 0x0>;
+ qcom,nsessions = <5>;
dma-coherent;
};
};
--
2.43.0
^ permalink raw reply related
* Re: [PATCH net-next v2 1/9] net: dsa: add tag driver for LAN9645X
From: Jens Emil Schulz Ostergaard @ 2026-04-01 7:31 UTC (permalink / raw)
To: Jakub Kicinski
Cc: UNGLinuxDriver, andrew, olteanv, davem, edumazet, pabeni, horms,
robh, krzk+dt, conor+dt, woojung.huh, linux, Steen.Hegelund,
daniel.machon, linux-kernel, netdev, devicetree
In-Reply-To: <20260329195620.2789042-1-kuba@kernel.org>
On Sun, 2026-03-29 at 12:56 -0700, Jakub Kicinski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> This is an AI-generated review of your patch. The human sending this
> email has considered the AI review valid, or at least plausible.
> ---
> net: dsa: add tag driver for LAN9645X
>
> Add a tag driver for LAN9645x switches using a front port as the CPU port
> (NPI port). The driver configures a long prefix for extraction and no
> prefix for injection to handle the internal frame header (IFH).
>
> > diff --git a/net/dsa/tag_lan9645x.c b/net/dsa/tag_lan9645x.c
> > new file mode 100644
> > index 000000000000..9130fb0d61be
> > --- /dev/null
> > +++ b/net/dsa/tag_lan9645x.c
>
> [ ... ]
>
> > +static void lan9645x_xmit_get_vlan_info(struct sk_buff *skb,
> > + struct net_device *br,
> > + u32 *vlan_tci, u32 *tag_type)
> > +{
> > + struct vlan_ethhdr *hdr;
> > + u16 proto, tci;
> > +
> > + if (!br || !br_vlan_enabled(br)) {
> > + *vlan_tci = 0;
> > + *tag_type = LAN9645X_IFH_TAG_TYPE_C;
> > + return;
> > + }
> > +
> > + hdr = (struct vlan_ethhdr *)skb_mac_header(skb);
> > + br_vlan_get_proto(br, &proto);
> > +
> > + if (ntohs(hdr->h_vlan_proto) == proto) {
> > + vlan_remove_tag(skb, &tci);
>
> Is it possible for a maliciously crafted packet (e.g., via AF_PACKET) to have a
> length of 14 bytes with h_vlan_proto set to ETH_P_8021Q?
>
> If so, vlan_remove_tag() would read vhdr->h_vlan_TCI at offset 14, causing an
> out-of-bounds read.
>
> Furthermore, if the packet contains fragments and the VLAN header is not in the
> linear data area, vlan_remove_tag() could corrupt the SKB when shifting the MAC
> header.
>
> Would it be safer to use skb_vlan_untag() instead?
>
I think skb_vlan_untag is for the rx path, and will not make sense here. But I
can add a check like
if (skb_headlen(skb) >= VLAN_ETH_HLEN &&
ntohs(hdr->h_vlan_proto) == proto) {
vlan_remove_tag(skb, &tci);
*vlan_tci = tci;
} else {
so we know the linear data area has the bytes.
> > + *vlan_tci = tci;
> > + } else {
> > + rcu_read_lock();
> > + br_vlan_get_pvid_rcu(br, &tci);
> > + rcu_read_unlock();
> > + *vlan_tci = tci;
> > + }
> > +
> > + *tag_type = (proto != ETH_P_8021Q) ? LAN9645X_IFH_TAG_TYPE_S :
> > + LAN9645X_IFH_TAG_TYPE_C;
> > +}
>
> [ ... ]
>
> > +static struct sk_buff *lan9645x_rcv(struct sk_buff *skb,
> > + struct net_device *ndev)
> > +{
> > + u32 src_port, qos_class, vlan_tci, tag_type, popcnt, etype_ofs;
> > + u8 *orig_skb_data = skb->data;
> > + struct dsa_port *dp;
> > + u32 ifh_gap_len = 0;
> > + u16 vlan_tpid;
> > + u8 *ifh;
> > +
> > + /* DSA master already consumed DMAC,SMAC,ETYPE from long prefix. Go back
> > + * to beginning of frame.
> > + */
> > + skb_push(skb, ETH_HLEN);
> > + /* IFH starts after our long prefix */
> > + ifh = skb_pull(skb, LAN9645X_LONG_PREFIX_LEN);
>
> Could skb_pull() return NULL here if skb->len is less than 16 bytes?
>
> If it returns NULL, the blind dereference of ifh in the subsequent
> lan9645x_ifh_get() calls would cause a NULL pointer dereference.
>
> Additionally, is the 44-byte tag (16-byte prefix + 28-byte IFH) guaranteed to
> be in the linear data buffer (skb->data)?
>
> Without calling pskb_may_pull(skb, LAN9645X_TOTAL_TAG_LEN) first, accessing it
> via the ifh pointer might result in out-of-bounds reads if the packet payload
> is in paged fragments.
>
I can add pskb_may_pull calls to ensure skb->data is availble.
> > +
> > + popcnt = lan9645x_ifh_get(ifh, IFH_POP_CNT, IFH_POP_CNT_SZ);
> > + etype_ofs = lan9645x_ifh_get(ifh, IFH_ETYPE_OFS, IFH_ETYPE_OFS_SZ);
> > + src_port = lan9645x_ifh_get(ifh, IFH_SRCPORT, IFH_SRCPORT_SZ);
> --
> pw-bot: cr
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: trivial-devices: Add sony,aps-379
From: Krzysztof Kozlowski @ 2026-04-01 7:30 UTC (permalink / raw)
To: Chris Packham
Cc: robh, krzk+dt, conor+dt, linux, devicetree, linux-hwmon,
linux-kernel
In-Reply-To: <20260401024214.804237-2-chris.packham@alliedtelesis.co.nz>
On Wed, Apr 01, 2026 at 03:42:11PM +1300, Chris Packham wrote:
> Add the compatible string for the sony,aps-379. This is a simple PMBus
> (I2C) device that requires no additional attributes.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 19/19] gpio: add GPIO controller found on Waveshare DSI TOUCH panels
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
The Waveshare DSI TOUCH family of panels has separate on-board GPIO
controller, which controls power supplies to the panel and the touch
screen and provides reset pins for both the panel and the touchscreen.
Also it provides a simple PWM controller for panel backlight. Add
support for this GPIO controller.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpio/Kconfig | 10 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-waveshare-dsi.c | 220 ++++++++++++++++++++++++++++++++++++++
3 files changed, 231 insertions(+)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 4c3f6ec336c1..f0bb5cdebf9b 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -804,6 +804,16 @@ config GPIO_VISCONTI
help
Say yes here to support GPIO on Tohisba Visconti.
+config GPIO_WAVESHARE_DSI_TOUCH
+ tristate "Waveshare GPIO controller for DSI panels"
+ depends on BACKLIGHT_CLASS_DEVICE
+ depends on I2C
+ select REGMAP_I2C
+ help
+ Enable support for the GPIO and PWM controller found on Waveshare DSI
+ TOUCH panel kits. It provides GPIOs (used for regulator control and
+ resets) and backlight support.
+
config GPIO_WCD934X
tristate "Qualcomm Technologies Inc WCD9340/WCD9341 GPIO controller driver"
depends on MFD_WCD934X
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 20d4a57afdaa..75ce89fc3b93 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -207,6 +207,7 @@ obj-$(CONFIG_GPIO_VIRTUSER) += gpio-virtuser.o
obj-$(CONFIG_GPIO_VIRTIO) += gpio-virtio.o
obj-$(CONFIG_GPIO_VISCONTI) += gpio-visconti.o
obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o
+obj-$(CONFIG_GPIO_WAVESHARE_DSI_TOUCH) += gpio-waveshare-dsi.o
obj-$(CONFIG_GPIO_WCD934X) += gpio-wcd934x.o
obj-$(CONFIG_GPIO_WHISKEY_COVE) += gpio-wcove.o
obj-$(CONFIG_GPIO_WINBOND) += gpio-winbond.o
diff --git a/drivers/gpio/gpio-waveshare-dsi.c b/drivers/gpio/gpio-waveshare-dsi.c
new file mode 100644
index 000000000000..30fe7569c150
--- /dev/null
+++ b/drivers/gpio/gpio-waveshare-dsi.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Waveshare International Limited
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/backlight.h>
+#include <linux/err.h>
+#include <linux/fb.h>
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+/* I2C registers of the microcontroller. */
+#define REG_TP 0x94
+#define REG_LCD 0x95
+#define REG_PWM 0x96
+#define REG_SIZE 0x97
+#define REG_ID 0x98
+#define REG_VERSION 0x99
+
+enum {
+ GPIO_AVDD = 0,
+ GPIO_PANEL_RESET = 1,
+ GPIO_BL_ENABLE = 2,
+ GPIO_IOVCC = 4,
+ GPIO_VCC = 8,
+ GPIO_TS_RESET = 9,
+ NUM_GPIO = 16,
+};
+
+struct waveshare_gpio {
+ struct mutex dir_lock;
+ struct mutex pwr_lock;
+ struct regmap *regmap;
+ u16 poweron_state;
+
+ struct gpio_chip gc;
+};
+
+static const struct regmap_config waveshare_gpio_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = REG_PWM,
+};
+
+static int waveshare_gpio_get(struct waveshare_gpio *state, unsigned int offset)
+{
+ u16 pwr_state;
+
+ mutex_lock(&state->pwr_lock);
+ pwr_state = state->poweron_state & BIT(offset);
+ mutex_unlock(&state->pwr_lock);
+
+ return !!pwr_state;
+}
+
+static int waveshare_gpio_set(struct waveshare_gpio *state, unsigned int offset, int value)
+{
+ u16 last_val;
+
+ mutex_lock(&state->pwr_lock);
+
+ last_val = state->poweron_state;
+ if (value)
+ last_val |= BIT(offset);
+ else
+ last_val &= ~BIT(offset);
+
+ state->poweron_state = last_val;
+
+ regmap_write(state->regmap, REG_TP, last_val >> 8);
+ regmap_write(state->regmap, REG_LCD, last_val & 0xff);
+
+ mutex_unlock(&state->pwr_lock);
+
+ return 0;
+}
+
+static int waveshare_gpio_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+ return GPIO_LINE_DIRECTION_OUT;
+}
+
+static int waveshare_gpio_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct waveshare_gpio *state = gpiochip_get_data(gc);
+
+ return waveshare_gpio_get(state, offset);
+}
+
+static int waveshare_gpio_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
+{
+ struct waveshare_gpio *state = gpiochip_get_data(gc);
+
+ return waveshare_gpio_set(state, offset, value);
+}
+
+static int waveshare_gpio_update_status(struct backlight_device *bl)
+{
+ struct waveshare_gpio *state = bl_get_data(bl);
+ int brightness = backlight_get_brightness(bl);
+
+ waveshare_gpio_set(state, GPIO_BL_ENABLE, brightness);
+
+ return regmap_write(state->regmap, REG_PWM, brightness);
+}
+
+static const struct backlight_ops waveshare_gpio_bl = {
+ .update_status = waveshare_gpio_update_status,
+};
+
+static int waveshare_gpio_i2c_read(struct i2c_client *client, u8 reg, unsigned int *buf)
+{
+ int val;
+
+ val = i2c_smbus_read_byte_data(client, reg);
+ if (val < 0)
+ return val;
+
+ *buf = val;
+
+ return 0;
+}
+
+static int waveshare_gpio_probe(struct i2c_client *i2c)
+{
+ struct backlight_properties props = {};
+ struct waveshare_gpio *state;
+ struct device *dev = &i2c->dev;
+ struct backlight_device *bl;
+ struct regmap *regmap;
+ unsigned int data;
+ int ret;
+
+ state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
+ if (!state)
+ return -ENOMEM;
+
+ ret = devm_mutex_init(dev, &state->dir_lock);
+ if (ret)
+ return ret;
+
+ ret = devm_mutex_init(dev, &state->pwr_lock);
+ if (ret)
+ return ret;
+
+ i2c_set_clientdata(i2c, state);
+
+ regmap = devm_regmap_init_i2c(i2c, &waveshare_gpio_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap), "Failed to allocate register map\n");
+
+ ret = waveshare_gpio_i2c_read(i2c, REG_ID, &data);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to read register\n");
+
+ dev_dbg(dev, "waveshare panel hw id = 0x%x\n", data);
+
+ ret = waveshare_gpio_i2c_read(i2c, REG_SIZE, &data);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to read register\n");
+
+ dev_dbg(dev, "waveshare panel size = %d\n", data);
+
+ ret = waveshare_gpio_i2c_read(i2c, REG_VERSION, &data);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to read register\n");
+
+ dev_dbg(dev, "waveshare panel mcu version = 0x%x\n", data);
+
+ state->poweron_state = BIT(GPIO_TS_RESET);
+ regmap_write(regmap, REG_TP, state->poweron_state >> 8);
+ regmap_write(regmap, REG_LCD, state->poweron_state & 0xff);
+ msleep(20);
+
+ state->regmap = regmap;
+ state->gc.parent = dev;
+ state->gc.label = i2c->name;
+ state->gc.owner = THIS_MODULE;
+ state->gc.base = -1;
+ state->gc.ngpio = NUM_GPIO;
+
+ /* it is output only */
+ state->gc.get = waveshare_gpio_gpio_get;
+ state->gc.set = waveshare_gpio_gpio_set;
+ state->gc.get_direction = waveshare_gpio_gpio_get_direction;
+ state->gc.can_sleep = true;
+
+ ret = devm_gpiochip_add_data(dev, &state->gc, state);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to create gpiochip\n");
+
+ props.type = BACKLIGHT_RAW;
+ props.max_brightness = 255;
+ props.brightness = 255;
+ bl = devm_backlight_device_register(dev, dev_name(dev), dev, state,
+ &waveshare_gpio_bl, &props);
+ return PTR_ERR_OR_ZERO(bl);
+}
+
+static const struct of_device_id waveshare_gpio_dt_ids[] = {
+ { .compatible = "waveshare,dsi-touch-gpio" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, waveshare_gpio_dt_ids);
+
+static struct i2c_driver waveshare_gpio_regulator_driver = {
+ .driver = {
+ .name = "waveshare-regulator",
+ .of_match_table = of_match_ptr(waveshare_gpio_dt_ids),
+ },
+ .probe = waveshare_gpio_probe,
+};
+
+module_i2c_driver(waveshare_gpio_regulator_driver);
+
+MODULE_DESCRIPTION("GPIO controller driver for Waveshare DSI touch panels");
+MODULE_LICENSE("GPL");
--
2.47.3
^ permalink raw reply related
* [PATCH 18/19] dt-bindings: gpio: describe Waveshare GPIO controller
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
The Waveshare DSI TOUCH family of panels has separate on-board GPIO
controller, which controls power supplies to the panel and the touch
screen and provides reset pins for both the panel and the touchscreen.
Also it provides a simple PWM controller for panel backlight.
Add bindings for these GPIO controllers. As overall integration might be
not very obvious (and it differs significantly from the bindings used by
the original drivers), provide complete example with the on-board
regulators and the DSI panel.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../bindings/gpio/waveshare,dsi-touch-gpio.yaml | 100 +++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml b/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml
new file mode 100644
index 000000000000..2e622b668f2f
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/waveshare,dsi-touch-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Waveshare GPIO controller on DSI TOUCH panels
+
+maintainers:
+ - Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
+
+description:
+ Waveshare DSI TOUCH panel kits contain separate GPIO controller for toggling
+ power supplies and panel / touchscreen resets.
+
+properties:
+ compatible:
+ const: waveshare,dsi-touch-gpio
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wsgpio: gpio@45 {
+ compatible = "waveshare,dsi-touch-gpio";
+ reg = <0x45>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ panel_avdd: regulator-panel-avdd {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-avdd";
+ gpios = <&wsgpio 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ panel_iovcc: regulator-panel-iovcc {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-iovcc";
+ gpios = <&wsgpio 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ panel_vcc: regulator-panel-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-vcc";
+ gpios = <&wsgpio 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_panel: dsi_panel@0 {
+ reg = <0>;
+ compatible = "waveshare,8.0-dsi-touch-a", "jadard,jd9365da-h3";
+ reset-gpio = <&wsgpio 1 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&panel_avdd>;
+ iovcc-supply = <&panel_iovcc>;
+ backlight = <&wsgpio>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+
+ port {
+ dsi_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+...
--
2.47.3
^ permalink raw reply related
* [PATCH 17/19] drm/panel: add driver for Waveshare 8.8" DSI TOUCH-A panel
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Add driver for the panel found on Waveshare 8.8" DSI TOUCH-A kit. It
uses ota7290b IC as a controller.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/Kconfig | 12 ++
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-focaltech-ota7290b.c | 208 +++++++++++++++++++++++
3 files changed, 221 insertions(+)
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index ba527b4d7737..979109c27b9b 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -144,6 +144,18 @@ config DRM_PANEL_FEIYANG_FY07024DI26A30D
Say Y if you want to enable support for panels based on the
Feiyang FY07024DI26A30-D MIPI-DSI interface.
+config DRM_PANEL_FOCALTECH_OTA7290B
+ tristate "Focaltech OTA7290B"
+ depends on DRM_MIPI_DSI
+ depends on I2C
+ depends on BACKLIGHT_CLASS_DEVICE
+ select DRM_KMS_HELPER
+ help
+ Enable support for panels using OTA7290B as a controller (for
+ example, Waveshare 12.3" DSI TOUCH-A panel). Say Y here if you want
+ to enable support for this panel. To compile this driver as a module,
+ choose M here.
+
config DRM_PANEL_DSI_CM
tristate "Generic DSI command mode panels"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index a4291dc3905b..0d694acbfbb6 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_DRM_PANEL_EBBG_FT8719) += panel-ebbg-ft8719.o
obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o
obj-$(CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02) += panel-feixin-k101-im2ba02.o
obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o
+obj-$(CONFIG_DRM_PANEL_FOCALTECH_OTA7290B) += panel-focaltech-ota7290b.o
obj-$(CONFIG_DRM_PANEL_HIMAX_HX8279) += panel-himax-hx8279.o
obj-$(CONFIG_DRM_PANEL_HIMAX_HX83102) += panel-himax-hx83102.o
obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112A) += panel-himax-hx83112a.o
diff --git a/drivers/gpu/drm/panel/panel-focaltech-ota7290b.c b/drivers/gpu/drm/panel/panel-focaltech-ota7290b.c
new file mode 100644
index 000000000000..991d6a4caf17
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-focaltech-ota7290b.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Waveshare International Limited
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_probe_helper.h>
+
+struct ota7290b {
+ struct drm_panel panel;
+ struct mipi_dsi_device *dsi;
+
+ struct regulator *power;
+ struct gpio_desc *reset;
+ struct regulator *avdd;
+ struct regulator *iovcc;
+
+ enum drm_panel_orientation orientation;
+};
+
+static inline struct ota7290b *panel_to_ota(struct drm_panel *panel)
+{
+ return container_of(panel, struct ota7290b, panel);
+}
+
+static int ota7290b_prepare(struct drm_panel *panel)
+{
+ struct ota7290b *ctx = panel_to_ota(panel);
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+ int ret;
+
+ if (ctx->iovcc) {
+ ret = regulator_enable(ctx->iovcc);
+ if (ret)
+ dev_err(panel->dev, "failed to enable IO regulator: %d\n", ret);
+ }
+
+ if (ctx->avdd) {
+ ret = regulator_enable(ctx->avdd);
+ if (ret)
+ dev_err(panel->dev, "failed to enable AVDD regulator: %d\n", ret);
+ }
+
+ if (ctx->reset) {
+ gpiod_set_value_cansleep(ctx->reset, 0);
+ msleep(60);
+ gpiod_set_value_cansleep(ctx->reset, 1);
+ msleep(60);
+ gpiod_set_value_cansleep(ctx->reset, 0);
+ msleep(60);
+ }
+
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+ mipi_dsi_msleep(&dsi_ctx, 120);
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ mipi_dsi_msleep(&dsi_ctx, 50);
+
+ if (dsi_ctx.accum_err < 0)
+ dev_err(panel->dev, "failed to init panel: %d\n", ret);
+
+ return dsi_ctx.accum_err;
+}
+
+static int ota7290b_unprepare(struct drm_panel *panel)
+{
+ struct ota7290b *ctx = panel_to_ota(panel);
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+ mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
+ mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
+
+ if (ctx->reset) {
+ gpiod_set_value_cansleep(ctx->reset, 1);
+ msleep(5);
+ }
+
+ if (ctx->avdd)
+ regulator_disable(ctx->avdd);
+
+ if (ctx->iovcc)
+ regulator_disable(ctx->iovcc);
+
+ return 0;
+}
+
+static const struct drm_display_mode waveshare_dsi_touch_8_8_a_mode = {
+ .clock = 75000,
+
+ .hdisplay = 480,
+ .hsync_start = 480 + 50,
+ .hsync_end = 480 + 50 + 50,
+ .htotal = 480 + 50 + 50 + 50,
+
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 20,
+ .vsync_end = 1920 + 20 + 20,
+ .vtotal = 1920 + 20 + 20 + 20,
+
+ .width_mm = 68,
+ .height_mm = 219,
+ .type = DRM_MODE_TYPE_DRIVER,
+};
+
+static int ota7290b_get_modes(struct drm_panel *panel,
+ struct drm_connector *connector)
+{
+ return drm_connector_helper_get_modes_fixed(connector, &waveshare_dsi_touch_8_8_a_mode);
+}
+
+static enum drm_panel_orientation ota7290b_get_orientation(struct drm_panel *panel)
+{
+ struct ota7290b *ctx = panel_to_ota(panel);
+
+ return ctx->orientation;
+}
+
+static const struct drm_panel_funcs ota7290b_funcs = {
+ .prepare = ota7290b_prepare,
+ .unprepare = ota7290b_unprepare,
+ .get_modes = ota7290b_get_modes,
+ .get_orientation = ota7290b_get_orientation,
+};
+
+static int ota7290b_probe(struct mipi_dsi_device *dsi)
+{
+ struct ota7290b *ctx;
+ int ret;
+
+ ctx = devm_drm_panel_alloc(&dsi->dev, struct ota7290b, panel,
+ &ota7290b_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+ if (!ctx)
+ return -ENOMEM;
+ mipi_dsi_set_drvdata(dsi, ctx);
+ ctx->dsi = dsi;
+
+ ctx->reset = devm_gpiod_get_optional(&dsi->dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(ctx->reset))
+ return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset),
+ "Couldn't get our reset GPIO\n");
+
+ ctx->iovcc = devm_regulator_get_optional(&dsi->dev, "iovcc");
+ if (IS_ERR(ctx->iovcc))
+ return dev_err_probe(&dsi->dev, PTR_ERR(ctx->iovcc),
+ "Couldn't get our iovcc supply\n");
+
+ ctx->avdd = devm_regulator_get_optional(&dsi->dev, "avdd");
+ if (IS_ERR(ctx->avdd))
+ return dev_err_probe(&dsi->dev, PTR_ERR(ctx->avdd),
+ "Couldn't get our avdd supply\n");
+
+ ret = of_drm_get_panel_orientation(
+ dsi->dev.of_node, &ctx->orientation);
+ if (ret) {
+ dev_err(&dsi->dev, "%pOF: failed to get orientation: %d\n",
+ dsi->dev.of_node, ret);
+ return ret;
+ }
+
+ ret = drm_panel_of_backlight(&ctx->panel);
+ if (ret)
+ return ret;
+
+ ctx->panel.prepare_prev_first = true;
+
+ ret = devm_drm_panel_add(&dsi->dev, &ctx->panel);
+ if (ret)
+ return ret;
+
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_HSE |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+ dsi->format = MIPI_DSI_FMT_RGB888,
+ dsi->lanes = 2;
+
+ return devm_mipi_dsi_attach(&dsi->dev, dsi);
+}
+
+static const struct of_device_id ota7290b_of_match[] = {
+ { .compatible = "waveshare,8.8-dsi-touch-a", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, ota7290b_of_match);
+
+static struct mipi_dsi_driver ota7290b_driver = {
+ .probe = ota7290b_probe,
+ .driver = {
+ .name = "focaltech-ota7290b",
+ .of_match_table = ota7290b_of_match,
+ },
+};
+module_mipi_dsi_driver(ota7290b_driver);
+
+MODULE_DESCRIPTION("Panel driver for Focaltech OTA7290B panels");
+MODULE_LICENSE("GPL");
--
2.47.3
^ permalink raw reply related
* [PATCH 16/19] drm/panel: add devm_drm_panel_add() helper
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Add devm_drm_panel_add(), devres-managed version of drm_panel_add().
It's not uncommon for the panel drivers to use devres functions for most
of the resources. Provide corresponding replacement for drm_panel_add().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/drm_panel.c | 23 +++++++++++++++++++++++
include/drm/drm_panel.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
index d1e6598ea3bc..a6029b699b73 100644
--- a/drivers/gpu/drm/drm_panel.c
+++ b/drivers/gpu/drm/drm_panel.c
@@ -101,6 +101,29 @@ void drm_panel_remove(struct drm_panel *panel)
}
EXPORT_SYMBOL(drm_panel_remove);
+static void drm_panel_add_release(void *data)
+{
+ drm_panel_remove(data);
+}
+
+/**
+ * devm_drm_panel_add - add a panel to the global registry using devres
+ * @panel: panel to add
+ *
+ * Add a panel to the global registry so that it can be looked
+ * up by display drivers. The panel to be added must have been
+ * allocated by devm_drm_panel_alloc(). Unlike drm_panel_add() with this
+ * function there is no need to call drm_panel_remove(), it will be called
+ * automatically.
+ */
+int devm_drm_panel_add(struct device *dev, struct drm_panel *panel)
+{
+ drm_panel_add(panel);
+
+ return devm_add_action_or_reset(dev, drm_panel_add_release, panel);
+}
+EXPORT_SYMBOL(devm_drm_panel_add);
+
/**
* drm_panel_prepare - power on a panel
* @panel: DRM panel
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 2407bfa60236..1fb9148dd095 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -329,6 +329,7 @@ void drm_panel_put(struct drm_panel *panel);
void drm_panel_add(struct drm_panel *panel);
void drm_panel_remove(struct drm_panel *panel);
+int devm_drm_panel_add(struct device *dev, struct drm_panel *panel);
void drm_panel_prepare(struct drm_panel *panel);
void drm_panel_unprepare(struct drm_panel *panel);
--
2.47.3
^ permalink raw reply related
* [PATCH 15/19] drm/panel: ilitek-ili9881c: support Waveshare 7.0" DSI panel
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Enable support for Waveshare 7.0" DSI TOUCH-A panel. It requires
additional voltage regulator, iovcc.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 251 +++++++++++++++++++++++++-
1 file changed, 249 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
index 947b47841b01..0652cdb57d11 100644
--- a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
+++ b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
@@ -52,6 +52,7 @@ struct ili9881c {
const struct ili9881c_desc *desc;
struct regulator *power;
+ struct regulator *iovcc;
struct gpio_desc *reset;
enum drm_panel_orientation orientation;
@@ -1997,6 +1998,205 @@ static const struct ili9881c_instr bsd1218_a101kl68_init[] = {
ILI9881C_COMMAND_INSTR(0xd3, 0x3f),
};
+static const struct ili9881c_instr waveshare_7inch_a_init[] = {
+ ILI9881C_SWITCH_PAGE_INSTR(3),
+ ILI9881C_COMMAND_INSTR(0x01, 0x00),
+ ILI9881C_COMMAND_INSTR(0x02, 0x00),
+ ILI9881C_COMMAND_INSTR(0x03, 0x73),
+ ILI9881C_COMMAND_INSTR(0x04, 0x00),
+ ILI9881C_COMMAND_INSTR(0x05, 0x00),
+ ILI9881C_COMMAND_INSTR(0x06, 0x0a),
+ ILI9881C_COMMAND_INSTR(0x07, 0x00),
+ ILI9881C_COMMAND_INSTR(0x08, 0x00),
+ ILI9881C_COMMAND_INSTR(0x09, 0x61),
+ ILI9881C_COMMAND_INSTR(0x0a, 0x00),
+ ILI9881C_COMMAND_INSTR(0x0b, 0x00),
+ ILI9881C_COMMAND_INSTR(0x0c, 0x01),
+ ILI9881C_COMMAND_INSTR(0x0d, 0x00),
+ ILI9881C_COMMAND_INSTR(0x0e, 0x00),
+ ILI9881C_COMMAND_INSTR(0x0f, 0x61),
+ ILI9881C_COMMAND_INSTR(0x10, 0x61),
+ ILI9881C_COMMAND_INSTR(0x11, 0x00),
+ ILI9881C_COMMAND_INSTR(0x12, 0x00),
+ ILI9881C_COMMAND_INSTR(0x13, 0x00),
+ ILI9881C_COMMAND_INSTR(0x14, 0x00),
+ ILI9881C_COMMAND_INSTR(0x15, 0x00),
+ ILI9881C_COMMAND_INSTR(0x16, 0x00),
+ ILI9881C_COMMAND_INSTR(0x17, 0x00),
+ ILI9881C_COMMAND_INSTR(0x18, 0x00),
+ ILI9881C_COMMAND_INSTR(0x19, 0x00),
+ ILI9881C_COMMAND_INSTR(0x1a, 0x00),
+ ILI9881C_COMMAND_INSTR(0x1b, 0x00),
+ ILI9881C_COMMAND_INSTR(0x1c, 0x00),
+ ILI9881C_COMMAND_INSTR(0x1d, 0x00),
+ ILI9881C_COMMAND_INSTR(0x1e, 0x40),
+ ILI9881C_COMMAND_INSTR(0x1f, 0x80),
+ ILI9881C_COMMAND_INSTR(0x20, 0x06),
+ ILI9881C_COMMAND_INSTR(0x21, 0x01),
+ ILI9881C_COMMAND_INSTR(0x22, 0x00),
+ ILI9881C_COMMAND_INSTR(0x23, 0x00),
+ ILI9881C_COMMAND_INSTR(0x24, 0x00),
+ ILI9881C_COMMAND_INSTR(0x25, 0x00),
+ ILI9881C_COMMAND_INSTR(0x26, 0x00),
+ ILI9881C_COMMAND_INSTR(0x27, 0x00),
+ ILI9881C_COMMAND_INSTR(0x28, 0x33),
+ ILI9881C_COMMAND_INSTR(0x29, 0x03),
+ ILI9881C_COMMAND_INSTR(0x2a, 0x00),
+ ILI9881C_COMMAND_INSTR(0x2b, 0x00),
+ ILI9881C_COMMAND_INSTR(0x2c, 0x00),
+ ILI9881C_COMMAND_INSTR(0x2d, 0x00),
+ ILI9881C_COMMAND_INSTR(0x2e, 0x00),
+ ILI9881C_COMMAND_INSTR(0x2f, 0x00),
+ ILI9881C_COMMAND_INSTR(0x30, 0x00),
+ ILI9881C_COMMAND_INSTR(0x31, 0x00),
+ ILI9881C_COMMAND_INSTR(0x32, 0x00),
+ ILI9881C_COMMAND_INSTR(0x33, 0x00),
+ ILI9881C_COMMAND_INSTR(0x34, 0x04),
+ ILI9881C_COMMAND_INSTR(0x35, 0x00),
+ ILI9881C_COMMAND_INSTR(0x36, 0x00),
+ ILI9881C_COMMAND_INSTR(0x37, 0x00),
+ ILI9881C_COMMAND_INSTR(0x38, 0x3c),
+ ILI9881C_COMMAND_INSTR(0x39, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3a, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3b, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3c, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3d, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3e, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3f, 0x00),
+ ILI9881C_COMMAND_INSTR(0x40, 0x00),
+ ILI9881C_COMMAND_INSTR(0x41, 0x00),
+ ILI9881C_COMMAND_INSTR(0x42, 0x00),
+ ILI9881C_COMMAND_INSTR(0x43, 0x00),
+ ILI9881C_COMMAND_INSTR(0x44, 0x00),
+ ILI9881C_COMMAND_INSTR(0x50, 0x10),
+ ILI9881C_COMMAND_INSTR(0x51, 0x32),
+ ILI9881C_COMMAND_INSTR(0x52, 0x54),
+ ILI9881C_COMMAND_INSTR(0x53, 0x76),
+ ILI9881C_COMMAND_INSTR(0x54, 0x98),
+ ILI9881C_COMMAND_INSTR(0x55, 0xba),
+ ILI9881C_COMMAND_INSTR(0x56, 0x10),
+ ILI9881C_COMMAND_INSTR(0x57, 0x32),
+ ILI9881C_COMMAND_INSTR(0x58, 0x54),
+ ILI9881C_COMMAND_INSTR(0x59, 0x76),
+ ILI9881C_COMMAND_INSTR(0x5a, 0x98),
+ ILI9881C_COMMAND_INSTR(0x5b, 0xba),
+ ILI9881C_COMMAND_INSTR(0x5c, 0xdc),
+ ILI9881C_COMMAND_INSTR(0x5d, 0xfe),
+ ILI9881C_COMMAND_INSTR(0x5e, 0x00),
+ ILI9881C_COMMAND_INSTR(0x5f, 0x0e),
+ ILI9881C_COMMAND_INSTR(0x60, 0x0f),
+ ILI9881C_COMMAND_INSTR(0x61, 0x0c),
+ ILI9881C_COMMAND_INSTR(0x62, 0x0d),
+ ILI9881C_COMMAND_INSTR(0x63, 0x06),
+ ILI9881C_COMMAND_INSTR(0x64, 0x07),
+ ILI9881C_COMMAND_INSTR(0x65, 0x02),
+ ILI9881C_COMMAND_INSTR(0x66, 0x02),
+ ILI9881C_COMMAND_INSTR(0x67, 0x02),
+ ILI9881C_COMMAND_INSTR(0x68, 0x02),
+ ILI9881C_COMMAND_INSTR(0x69, 0x01),
+ ILI9881C_COMMAND_INSTR(0x6a, 0x00),
+ ILI9881C_COMMAND_INSTR(0x6b, 0x02),
+ ILI9881C_COMMAND_INSTR(0x6c, 0x15),
+ ILI9881C_COMMAND_INSTR(0x6d, 0x14),
+ ILI9881C_COMMAND_INSTR(0x6e, 0x02),
+ ILI9881C_COMMAND_INSTR(0x6f, 0x02),
+ ILI9881C_COMMAND_INSTR(0x70, 0x02),
+ ILI9881C_COMMAND_INSTR(0x71, 0x02),
+ ILI9881C_COMMAND_INSTR(0x72, 0x02),
+ ILI9881C_COMMAND_INSTR(0x73, 0x02),
+ ILI9881C_COMMAND_INSTR(0x74, 0x02),
+ ILI9881C_COMMAND_INSTR(0x75, 0x0e),
+ ILI9881C_COMMAND_INSTR(0x76, 0x0f),
+ ILI9881C_COMMAND_INSTR(0x77, 0x0c),
+ ILI9881C_COMMAND_INSTR(0x78, 0x0d),
+ ILI9881C_COMMAND_INSTR(0x79, 0x06),
+ ILI9881C_COMMAND_INSTR(0x7a, 0x07),
+ ILI9881C_COMMAND_INSTR(0x7b, 0x02),
+ ILI9881C_COMMAND_INSTR(0x7c, 0x02),
+ ILI9881C_COMMAND_INSTR(0x7d, 0x02),
+ ILI9881C_COMMAND_INSTR(0x7e, 0x02),
+ ILI9881C_COMMAND_INSTR(0x7f, 0x01),
+ ILI9881C_COMMAND_INSTR(0x80, 0x00),
+ ILI9881C_COMMAND_INSTR(0x81, 0x02),
+ ILI9881C_COMMAND_INSTR(0x82, 0x14),
+ ILI9881C_COMMAND_INSTR(0x83, 0x15),
+ ILI9881C_COMMAND_INSTR(0x84, 0x02),
+ ILI9881C_COMMAND_INSTR(0x85, 0x02),
+ ILI9881C_COMMAND_INSTR(0x86, 0x02),
+ ILI9881C_COMMAND_INSTR(0x87, 0x02),
+ ILI9881C_COMMAND_INSTR(0x88, 0x02),
+ ILI9881C_COMMAND_INSTR(0x89, 0x02),
+ ILI9881C_COMMAND_INSTR(0x8a, 0x02),
+
+ ILI9881C_SWITCH_PAGE_INSTR(4),
+ ILI9881C_COMMAND_INSTR(0x38, 0x01),
+ ILI9881C_COMMAND_INSTR(0x39, 0x00),
+ ILI9881C_COMMAND_INSTR(0x6c, 0x15),
+ ILI9881C_COMMAND_INSTR(0x6e, 0x2a),
+ ILI9881C_COMMAND_INSTR(0x6f, 0x33),
+ ILI9881C_COMMAND_INSTR(0x3a, 0x94),
+ ILI9881C_COMMAND_INSTR(0x8d, 0x14),
+ ILI9881C_COMMAND_INSTR(0x87, 0xba),
+ ILI9881C_COMMAND_INSTR(0x26, 0x76),
+ ILI9881C_COMMAND_INSTR(0xb2, 0xd1),
+ ILI9881C_COMMAND_INSTR(0xb5, 0x06),
+ ILI9881C_COMMAND_INSTR(0x3b, 0x98),
+
+ ILI9881C_SWITCH_PAGE_INSTR(1),
+ ILI9881C_COMMAND_INSTR(0x22, 0x0a),
+ ILI9881C_COMMAND_INSTR(0x31, 0x00),
+ ILI9881C_COMMAND_INSTR(0x53, 0x71),
+ ILI9881C_COMMAND_INSTR(0x55, 0x8f),
+ ILI9881C_COMMAND_INSTR(0x40, 0x33),
+ ILI9881C_COMMAND_INSTR(0x50, 0x96),
+ ILI9881C_COMMAND_INSTR(0x51, 0x96),
+ ILI9881C_COMMAND_INSTR(0x60, 0x23),
+ ILI9881C_COMMAND_INSTR(0xa0, 0x08),
+ ILI9881C_COMMAND_INSTR(0xa1, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xa2, 0x2a),
+ ILI9881C_COMMAND_INSTR(0xa3, 0x10),
+ ILI9881C_COMMAND_INSTR(0xa4, 0x15),
+ ILI9881C_COMMAND_INSTR(0xa5, 0x28),
+ ILI9881C_COMMAND_INSTR(0xa6, 0x1c),
+ ILI9881C_COMMAND_INSTR(0xa7, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xa8, 0x7e),
+ ILI9881C_COMMAND_INSTR(0xa9, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xaa, 0x29),
+ ILI9881C_COMMAND_INSTR(0xab, 0x6b),
+ ILI9881C_COMMAND_INSTR(0xac, 0x1a),
+ ILI9881C_COMMAND_INSTR(0xad, 0x18),
+ ILI9881C_COMMAND_INSTR(0xae, 0x4b),
+ ILI9881C_COMMAND_INSTR(0xaf, 0x20),
+ ILI9881C_COMMAND_INSTR(0xb0, 0x27),
+ ILI9881C_COMMAND_INSTR(0xb1, 0x50),
+ ILI9881C_COMMAND_INSTR(0xb2, 0x64),
+ ILI9881C_COMMAND_INSTR(0xb3, 0x39),
+ ILI9881C_COMMAND_INSTR(0xc0, 0x08),
+ ILI9881C_COMMAND_INSTR(0xc1, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xc2, 0x2a),
+ ILI9881C_COMMAND_INSTR(0xc3, 0x10),
+ ILI9881C_COMMAND_INSTR(0xc4, 0x15),
+ ILI9881C_COMMAND_INSTR(0xc5, 0x28),
+ ILI9881C_COMMAND_INSTR(0xc6, 0x1c),
+ ILI9881C_COMMAND_INSTR(0xc7, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xc8, 0x7e),
+ ILI9881C_COMMAND_INSTR(0xc9, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xca, 0x29),
+ ILI9881C_COMMAND_INSTR(0xcb, 0x6b),
+ ILI9881C_COMMAND_INSTR(0xcc, 0x1a),
+ ILI9881C_COMMAND_INSTR(0xcd, 0x18),
+ ILI9881C_COMMAND_INSTR(0xce, 0x4b),
+ ILI9881C_COMMAND_INSTR(0xcf, 0x20),
+ ILI9881C_COMMAND_INSTR(0xd0, 0x27),
+ ILI9881C_COMMAND_INSTR(0xd1, 0x50),
+ ILI9881C_COMMAND_INSTR(0xd2, 0x64),
+ ILI9881C_COMMAND_INSTR(0xd3, 0x39),
+
+ ILI9881C_SWITCH_PAGE_INSTR(0),
+ ILI9881C_COMMAND_INSTR(0x3a, 0x77),
+ ILI9881C_COMMAND_INSTR(0x36, 0x00),
+};
+
static inline struct ili9881c *panel_to_ili9881c(struct drm_panel *panel)
{
return container_of(panel, struct ili9881c, panel);
@@ -2035,9 +2235,19 @@ static int ili9881c_prepare(struct drm_panel *panel)
int ret;
/* Power the panel */
+ if (ctx->iovcc) {
+ ret = regulator_enable(ctx->iovcc);
+ if (ret)
+ return ret;
+ }
+
+ msleep(5);
ret = regulator_enable(ctx->power);
- if (ret)
- return ret;
+ if (ret) {
+ mctx.accum_err = ret;
+ goto disable_iovcc;
+ }
+
msleep(5);
/* And reset it */
@@ -2074,6 +2284,9 @@ static int ili9881c_prepare(struct drm_panel *panel)
disable_power:
regulator_disable(ctx->power);
+disable_iovcc:
+ if (ctx->iovcc)
+ regulator_disable(ctx->iovcc);
return mctx.accum_err;
}
@@ -2085,6 +2298,8 @@ static int ili9881c_unprepare(struct drm_panel *panel)
mipi_dsi_dcs_set_display_off_multi(&mctx);
mipi_dsi_dcs_enter_sleep_mode_multi(&mctx);
regulator_disable(ctx->power);
+ if (ctx->iovcc)
+ regulator_disable(ctx->iovcc);
gpiod_set_value_cansleep(ctx->reset, 1);
return 0;
@@ -2260,6 +2475,23 @@ static const struct drm_display_mode bsd1218_a101kl68_default_mode = {
.height_mm = 170,
};
+static const struct drm_display_mode waveshare_7inch_a_mode = {
+ .clock = 83333,
+
+ .hdisplay = 720,
+ .hsync_start = 720 + 120,
+ .hsync_end = 720 + 120 + 100,
+ .htotal = 720 + 120 + 100 + 100,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 10,
+ .vsync_end = 1280 + 10 + 10,
+ .vtotal = 1280 + 10 + 10 + 10,
+
+ .width_mm = 85,
+ .height_mm = 154,
+};
+
static int ili9881c_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
@@ -2329,6 +2561,11 @@ static int ili9881c_dsi_probe(struct mipi_dsi_device *dsi)
return dev_err_probe(&dsi->dev, PTR_ERR(ctx->power),
"Couldn't get our power regulator\n");
+ ctx->iovcc = devm_regulator_get_optional(&dsi->dev, "iovcc");
+ if (IS_ERR(ctx->iovcc))
+ return dev_err_probe(&dsi->dev, PTR_ERR(ctx->iovcc),
+ "Couldn't get our iovcc regulator\n");
+
ctx->reset = devm_gpiod_get_optional(&dsi->dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(ctx->reset))
return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset),
@@ -2454,6 +2691,15 @@ static const struct ili9881c_desc bsd1218_a101kl68_desc = {
.lanes = 4,
};
+static const struct ili9881c_desc waveshare_7inch_a_desc = {
+ .init = waveshare_7inch_a_init,
+ .init_length = ARRAY_SIZE(waveshare_7inch_a_init),
+ .mode = &waveshare_7inch_a_mode,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_HSE |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+ .lanes = 2,
+};
+
static const struct of_device_id ili9881c_of_match[] = {
{ .compatible = "bananapi,lhr050h41", .data = &lhr050h41_desc },
{ .compatible = "bestar,bsd1218-a101kl68", .data = &bsd1218_a101kl68_desc },
@@ -2462,6 +2708,7 @@ static const struct of_device_id ili9881c_of_match[] = {
{ .compatible = "tdo,tl050hdv35", .data = &tl050hdv35_desc },
{ .compatible = "wanchanglong,w552946aaa", .data = &w552946aaa_desc },
{ .compatible = "wanchanglong,w552946aba", .data = &w552946aba_desc },
+ { .compatible = "waveshare,7.0-dsi-touch-a", .data = &waveshare_7inch_a_desc },
{ .compatible = "ampire,am8001280g", .data = &am8001280g_desc },
{ .compatible = "raspberrypi,dsi-5inch", &rpi_5inch_desc },
{ .compatible = "raspberrypi,dsi-7inch", &rpi_7inch_desc },
--
2.47.3
^ permalink raw reply related
* [PATCH 14/19] drm/panel: jadard-jd9365da-h3: support Waveshare DSI panels
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Add configuration for Waveshare DSI panels using JD9365 controller.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 1524 ++++++++++++++++++++--
1 file changed, 1440 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index 11b7e07c1af8..e9a461239301 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -21,6 +21,8 @@
#include <linux/of.h>
#include <linux/regulator/consumer.h>
+#include <video/mipi_display.h>
+
struct jadard;
struct jadard_panel_desc {
@@ -1599,115 +1601,1469 @@ static const struct jadard_panel_desc taiguan_xti05101_01a_desc = {
.enter_sleep_to_reset_down_delay_ms = 100,
};
-static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
+static int waveshare_3_4_c_init(struct jadard *jadard)
{
- struct device *dev = &dsi->dev;
- const struct jadard_panel_desc *desc;
- struct jadard *jadard;
- int ret;
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
- jadard = devm_drm_panel_alloc(dev, struct jadard, panel, &jadard_funcs,
- DRM_MODE_CONNECTOR_DSI);
- if (IS_ERR(jadard))
- return PTR_ERR(jadard);
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ jadard_enable_standard_cmds(&dsi_ctx);
- desc = of_device_get_match_data(dev);
+ jd9365da_switch_page(&dsi_ctx, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xd0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xd0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x64);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0xc7);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x18);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x14);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x1b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x56);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x33);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x25);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x16);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x2f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x32);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x53);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x31);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x0f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x56);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x33);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x25);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x16);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x2f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x32);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x53);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x31);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x0f);
- if (desc->mode_flags)
- dsi->mode_flags = desc->mode_flags;
- else
- dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
- MIPI_DSI_MODE_VIDEO_BURST |
- MIPI_DSI_MODE_NO_EOT_PACKET;
+ jd9365da_switch_page(&dsi_ctx, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x42);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);
- dsi->format = desc->format;
- dsi->lanes = desc->lanes;
- if (!dsi->lanes) {
- dsi->lanes = drm_of_get_data_lanes_count_remote(dsi->dev.of_node, 0, -1, 2, 4);
- if (dsi->lanes < 0)
- return dsi->lanes;
- }
- dev_dbg(&dsi->dev, "lanes: %d\n", dsi->lanes);
+ jd9365da_switch_page(&dsi_ctx, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0xa6);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xd9);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x33);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);
- jadard->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
- if (IS_ERR(jadard->reset))
- return dev_err_probe(&dsi->dev, PTR_ERR(jadard->reset),
- "failed to get our reset GPIO\n");
+ jd9365da_switch_page(&dsi_ctx, 0x00);
- jadard->vdd = devm_regulator_get(dev, "vdd");
- if (IS_ERR(jadard->vdd))
- return dev_err_probe(&dsi->dev, PTR_ERR(jadard->vdd),
- "failed to get vdd regulator\n");
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+ msleep(120);
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ msleep(5);
+ mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
- jadard->vccio = devm_regulator_get(dev, "vccio");
- if (IS_ERR(jadard->vccio))
- return dev_err_probe(&dsi->dev, PTR_ERR(jadard->vccio),
- "failed to get vccio regulator\n");
+ return dsi_ctx.accum_err;
+}
- ret = of_drm_get_panel_orientation(dev->of_node, &jadard->orientation);
- if (ret < 0)
- return dev_err_probe(dev, ret, "failed to get orientation\n");
+static const struct jadard_panel_desc waveshare_3_4_inch_c_desc = {
+ .mode_2ln = &(const struct drm_display_mode) {
+ .clock = (800 + 40 + 20 + 20) * (800 + 24 + 4 + 12) * 60 / 1000,
- ret = drm_panel_of_backlight(&jadard->panel);
- if (ret)
- return ret;
+ .hdisplay = 800,
+ .hsync_start = 800 + 40,
+ .hsync_end = 800 + 40 + 20,
+ .htotal = 800 + 40 + 20 + 20,
- jadard->panel.prepare_prev_first = true;
+ .vdisplay = 800,
+ .vsync_start = 800 + 24,
+ .vsync_end = 800 + 24 + 4,
+ .vtotal = 800 + 24 + 4 + 12,
- drm_panel_add(&jadard->panel);
+ .width_mm = 88,
+ .height_mm = 88,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .lanes = 2,
+ .format = MIPI_DSI_FMT_RGB888,
+ .init = waveshare_3_4_c_init,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+};
- mipi_dsi_set_drvdata(dsi, jadard);
- jadard->dsi = dsi;
- jadard->desc = desc;
+static int waveshare_4_0_c_init(struct jadard *jadard)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
- ret = mipi_dsi_attach(dsi);
- if (ret < 0)
- drm_panel_remove(&jadard->panel);
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ jadard_enable_standard_cmds(&dsi_ctx);
- return ret;
-}
+ jd9365da_switch_page(&dsi_ctx, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xd0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xd0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x64);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0xc7);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x18);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x14);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x1b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x56);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x33);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x25);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x16);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x2f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x32);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x53);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x31);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x0f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x56);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x33);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x25);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x16);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x2f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x32);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x53);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x31);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x0f);
-static void jadard_dsi_remove(struct mipi_dsi_device *dsi)
-{
- struct jadard *jadard = mipi_dsi_get_drvdata(dsi);
+ jd9365da_switch_page(&dsi_ctx, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x42);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);
- mipi_dsi_detach(dsi);
- drm_panel_remove(&jadard->panel);
+ jd9365da_switch_page(&dsi_ctx, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0xa6);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xd9);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x33);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+ msleep(120);
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ msleep(5);
+ mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+
+ return dsi_ctx.accum_err;
}
-static const struct of_device_id jadard_of_match[] = {
- {
- .compatible = "anbernic,rg-ds-display-bottom",
- .data = &anbernic_rgds_display_desc
- },
- {
- .compatible = "anbernic,rg-ds-display-top",
- .data = &anbernic_rgds_display_desc
- },
- {
- .compatible = "chongzhou,cz101b4001",
- .data = &cz101b4001_desc
- },
- {
- .compatible = "kingdisplay,kd101ne3-40ti",
- .data = &kingdisplay_kd101ne3_40ti_desc
- },
- {
- .compatible = "melfas,lmfbx101117480",
- .data = &melfas_lmfbx101117480_desc
- },
- {
- .compatible = "radxa,display-10hd-ad001",
- .data = &cz101b4001_desc
+static const struct jadard_panel_desc waveshare_4_0_inch_c_desc = {
+ .mode_2ln = &(const struct drm_display_mode) {
+ .clock = (720 + 40 + 20 + 20) * (720 + 24 + 4 + 12) * 60 / 1000,
+
+ .hdisplay = 720,
+ .hsync_start = 720 + 40,
+ .hsync_end = 720 + 40 + 20,
+ .htotal = 720 + 40 + 20 + 20,
+
+ .vdisplay = 720,
+ .vsync_start = 720 + 24,
+ .vsync_end = 720 + 24 + 4,
+ .vtotal = 720 + 24 + 4 + 12,
+
+ .width_mm = 88,
+ .height_mm = 88,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
},
- {
- .compatible = "radxa,display-8hd-ad002",
- .data = &radxa_display_8hd_ad002_desc
+ .lanes = 2,
+ .format = MIPI_DSI_FMT_RGB888,
+ .init = waveshare_4_0_c_init,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+};
+
+static int waveshare_8_0_a_init(struct jadard *jadard)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ jadard_enable_standard_cmds(&dsi_ctx);
+
+ jd9365da_switch_page(&dsi_ctx, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7e);
+ else
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xb7);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xb7);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x70);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xa9);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x78);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x63);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x54);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x23);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x62);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10);
+
+ jd9365da_switch_page(&dsi_ctx, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x56);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xf8);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xd5);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x7b);
+
+ jd9365da_switch_page(&dsi_ctx, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x2a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59);
+ if (jadard->dsi->lanes != 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);
+ }
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+ msleep(120);
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ msleep(60);
+
+ return 0;
+}
+
+static const struct drm_display_mode waveshare_8_0_a_mode = {
+ .clock = (800 + 40 + 20 + 20) * (1280 + 30 + 12 + 4) * 60 / 1000,
+
+ .hdisplay = 800,
+ .hsync_start = 800 + 40,
+ .hsync_end = 800 + 40 + 20,
+ .htotal = 800 + 40 + 20 + 20,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 30,
+ .vsync_end = 1280 + 30 + 12,
+ .vtotal = 1280 + 30 + 12 + 4,
+
+ .width_mm = 107,
+ .height_mm = 172,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct jadard_panel_desc waveshare_8_0_inch_a_desc = {
+ .mode_4ln = &waveshare_8_0_a_mode,
+ .mode_2ln = &waveshare_8_0_a_mode,
+ .format = MIPI_DSI_FMT_RGB888,
+ .init = waveshare_8_0_a_init,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+};
+
+static int waveshare_10_1_b_init(struct jadard *jadard);
+
+static const struct jadard_panel_desc waveshare_9_0_inch_b_desc = {
+ .mode_4ln = &(const struct drm_display_mode) {
+ .clock = (720 + 60 + 60 + 4) * (1280 + 16 + 12 + 4) * 60 / 1000,
+
+ .hdisplay = 720,
+ .hsync_start = 720 + 60,
+ .hsync_end = 720 + 60 + 60,
+ .htotal = 720 + 60 + 60 + 4,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 16,
+ .vsync_end = 1280 + 16 + 12,
+ .vtotal = 1280 + 16 + 12 + 4,
+
+ .width_mm = 114,
+ .height_mm = 196,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .mode_2ln = &(const struct drm_display_mode) {
+ .clock = (720 + 50 + 50 + 50) * (1280 + 26 + 12 + 4) * 60 / 1000,
+
+ .hdisplay = 720,
+ .hsync_start = 720 + 50,
+ .hsync_end = 720 + 50 + 50,
+ .htotal = 720 + 50 + 50 + 50,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 26,
+ .vsync_end = 1280 + 26 + 12,
+ .vtotal = 1280 + 26 + 12 + 4,
+
+ .width_mm = 114,
+ .height_mm = 196,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .format = MIPI_DSI_FMT_RGB888,
+ .init = waveshare_10_1_b_init,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+};
+
+static const struct drm_display_mode waveshare_10_1_a_mode = {
+ .clock = (800 + 40 + 20 + 20) * (1280 + 20 + 20 + 4) * 60 / 1000,
+
+ .hdisplay = 800,
+ .hsync_start = 800 + 40,
+ .hsync_end = 800 + 40 + 20,
+ .htotal = 800 + 40 + 20 + 20,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 20,
+ .vsync_end = 1280 + 20 + 20,
+ .vtotal = 1280 + 20 + 20 + 4,
+
+ .width_mm = 135,
+ .height_mm = 216,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static int waveshare_10_1_a_init(struct jadard *jadard)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ jadard_enable_standard_cmds(&dsi_ctx);
+
+ jd9365da_switch_page(&dsi_ctx, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3b);
+ else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x38);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x38);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xaf);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xaf);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0d);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x6b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x5c);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x6a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x5b);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4f);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2b);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2a);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x5a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0f);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x59);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x3a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x26);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5c);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5b);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4f);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2b);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2a);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x63);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x62);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x52);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x5a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0f);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x59);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x3a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x26);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);
+
+ jd9365da_switch_page(&dsi_ctx, 0x02);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x37);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x42);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x42);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x77);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x77);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x48);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f);
+ else
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x16);
+ else
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x34);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1d);
+ else
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xdd);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3f);
+ else
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x14);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x82);
+
+ jd9365da_switch_page(&dsi_ctx, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);
+ if (jadard->dsi->lanes != 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);
+ }
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe7, 0x0c);
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+ msleep(120);
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ msleep(60);
+
+ return dsi_ctx.accum_err;
+}
+
+static const struct jadard_panel_desc waveshare_10_1_inch_a_desc = {
+ .mode_4ln = &waveshare_10_1_a_mode,
+ .mode_2ln = &waveshare_10_1_a_mode,
+ .format = MIPI_DSI_FMT_RGB888,
+ .init = waveshare_10_1_a_init,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+};
+
+static int waveshare_10_1_b_init(struct jadard *jadard)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ jadard_enable_standard_cmds(&dsi_ctx);
+
+ jd9365da_switch_page(&dsi_ctx, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x3f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xbf);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xbf);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x74);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x7e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x24);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xa9);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x38);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x65);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x52);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x14);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x25);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x23);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x3f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x34);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x27);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x24);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x18);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x65);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x52);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x14);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x25);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x23);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x3f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x34);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x27);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x24);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x18);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);
+
+ jd9365da_switch_page(&dsi_ctx, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x51);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x51);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x51);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x66);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x13);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x66);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xe3);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xd5);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x21);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x66);
+
+ jd9365da_switch_page(&dsi_ctx, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);
+
+ jd9365da_switch_page(&dsi_ctx, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1d);
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+ msleep(120);
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ msleep(5);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_TEAR_ON);
+
+ return 0;
+}
+
+static const struct jadard_panel_desc waveshare_10_1_inch_b_desc = {
+ .mode_4ln = &(const struct drm_display_mode) {
+ .clock = (720 + 60 + 60 + 4) * (1280 + 16 + 12 + 4) * 60 / 1000,
+
+ .hdisplay = 720,
+ .hsync_start = 720 + 60,
+ .hsync_end = 720 + 60 + 60,
+ .htotal = 720 + 60 + 60 + 4,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 16,
+ .vsync_end = 1280 + 16 + 12,
+ .vtotal = 1280 + 16 + 12 + 4,
+
+ .width_mm = 125,
+ .height_mm = 222,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .mode_2ln = &(const struct drm_display_mode) {
+ .clock = (720 + 50 + 50 + 50) * (1280 + 26 + 12 + 4) * 60 / 1000,
+
+ .hdisplay = 720,
+ .hsync_start = 720 + 50,
+ .hsync_end = 720 + 50 + 50,
+ .htotal = 720 + 50 + 50 + 50,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 26,
+ .vsync_end = 1280 + 26 + 12,
+ .vtotal = 1280 + 26 + 12 + 4,
+
+ .width_mm = 125,
+ .height_mm = 222,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .format = MIPI_DSI_FMT_RGB888,
+ .init = waveshare_10_1_b_init,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+};
+
+static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
+{
+ struct device *dev = &dsi->dev;
+ const struct jadard_panel_desc *desc;
+ struct jadard *jadard;
+ int ret;
+
+ jadard = devm_drm_panel_alloc(dev, struct jadard, panel, &jadard_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+ if (IS_ERR(jadard))
+ return PTR_ERR(jadard);
+
+ desc = of_device_get_match_data(dev);
+
+ if (desc->mode_flags)
+ dsi->mode_flags = desc->mode_flags;
+ else
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_NO_EOT_PACKET;
+
+ dsi->format = desc->format;
+ dsi->lanes = desc->lanes;
+ if (!dsi->lanes) {
+ dsi->lanes = drm_of_get_data_lanes_count_remote(dsi->dev.of_node, 0, -1, 2, 4);
+ if (dsi->lanes < 0)
+ return dsi->lanes;
+ }
+ dev_dbg(&dsi->dev, "lanes: %d\n", dsi->lanes);
+
+ jadard->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(jadard->reset))
+ return dev_err_probe(&dsi->dev, PTR_ERR(jadard->reset),
+ "failed to get our reset GPIO\n");
+
+ jadard->vdd = devm_regulator_get(dev, "vdd");
+ if (IS_ERR(jadard->vdd))
+ return dev_err_probe(&dsi->dev, PTR_ERR(jadard->vdd),
+ "failed to get vdd regulator\n");
+
+ jadard->vccio = devm_regulator_get(dev, "vccio");
+ if (IS_ERR(jadard->vccio))
+ return dev_err_probe(&dsi->dev, PTR_ERR(jadard->vccio),
+ "failed to get vccio regulator\n");
+
+ ret = of_drm_get_panel_orientation(dev->of_node, &jadard->orientation);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to get orientation\n");
+
+ ret = drm_panel_of_backlight(&jadard->panel);
+ if (ret)
+ return ret;
+
+ jadard->panel.prepare_prev_first = true;
+
+ drm_panel_add(&jadard->panel);
+
+ mipi_dsi_set_drvdata(dsi, jadard);
+ jadard->dsi = dsi;
+ jadard->desc = desc;
+
+ ret = mipi_dsi_attach(dsi);
+ if (ret < 0)
+ drm_panel_remove(&jadard->panel);
+
+ return ret;
+}
+
+static void jadard_dsi_remove(struct mipi_dsi_device *dsi)
+{
+ struct jadard *jadard = mipi_dsi_get_drvdata(dsi);
+
+ mipi_dsi_detach(dsi);
+ drm_panel_remove(&jadard->panel);
+}
+
+static const struct of_device_id jadard_of_match[] = {
+ {
+ .compatible = "anbernic,rg-ds-display-bottom",
+ .data = &anbernic_rgds_display_desc
+ },
+ {
+ .compatible = "anbernic,rg-ds-display-top",
+ .data = &anbernic_rgds_display_desc
+ },
+ {
+ .compatible = "chongzhou,cz101b4001",
+ .data = &cz101b4001_desc
+ },
+ {
+ .compatible = "kingdisplay,kd101ne3-40ti",
+ .data = &kingdisplay_kd101ne3_40ti_desc
+ },
+ {
+ .compatible = "melfas,lmfbx101117480",
+ .data = &melfas_lmfbx101117480_desc
+ },
+ {
+ .compatible = "radxa,display-10hd-ad001",
+ .data = &cz101b4001_desc
+ },
+ {
+ .compatible = "radxa,display-8hd-ad002",
+ .data = &radxa_display_8hd_ad002_desc
},
{
.compatible = "taiguanck,xti05101-01a",
.data = &taiguan_xti05101_01a_desc
},
+ {
+ .compatible = "waveshare,3.4-dsi-touch-c",
+ .data = &waveshare_3_4_inch_c_desc
+ },
+ {
+ .compatible = "waveshare,4.0-dsi-touch-c",
+ .data = &waveshare_4_0_inch_c_desc
+ },
+ {
+ .compatible = "waveshare,8.0-dsi-touch-a",
+ .data = &waveshare_8_0_inch_a_desc
+ },
+ {
+ .compatible = "waveshare,9.0-dsi-touch-b",
+ .data = &waveshare_9_0_inch_b_desc
+ },
+ {
+ .compatible = "waveshare,10.1-dsi-touch-a",
+ .data = &waveshare_10_1_inch_a_desc
+ },
+ {
+ .compatible = "waveshare,10.1-dsi-touch-b",
+ .data = &waveshare_10_1_inch_b_desc
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jadard_of_match);
--
2.47.3
^ permalink raw reply related
* [PATCH 13/19] drm/panel: jadard-jd9365da-h3: set prepare_prev_first
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Sending DSI commands from the prepare() callback requires DSI link to be
up at that point. For DSI hosts is guaranteed only if the panel driver
sets the .prepare_prev_first flag. Set it to let these panels work with
the DSI hosts which don't power on the link in their .mode_set callback.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index 5d9db2e1f28f..11b7e07c1af8 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -1652,6 +1652,8 @@ static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
if (ret)
return ret;
+ jadard->panel.prepare_prev_first = true;
+
drm_panel_add(&jadard->panel);
mipi_dsi_set_drvdata(dsi, jadard);
--
2.47.3
^ permalink raw reply related
* [PATCH 12/19] drm/panel: jadard-jd9365da-h3: support variable DSI configuration
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Several panels support attachment either using 4 DSI lanes or just 2. In
some cases, this requires a different panel mode to fulfill clock
requirements. Extend the driver to handle such cases by letting the
panel description to omit lanes specification and parsing number of
lanes from the DT.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 32 +++++++++++++++++-------
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index 1884ad2404cd..5d9db2e1f28f 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -10,6 +10,7 @@
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_modes.h>
+#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
@@ -23,7 +24,8 @@
struct jadard;
struct jadard_panel_desc {
- const struct drm_display_mode mode;
+ const struct drm_display_mode *mode_4ln;
+ const struct drm_display_mode *mode_2ln;
unsigned int lanes;
enum mipi_dsi_pixel_format format;
int (*init)(struct jadard *jadard);
@@ -57,7 +59,10 @@ static void jadard_enable_standard_cmds(struct mipi_dsi_multi_context *dsi_ctx)
mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe1, 0x93);
mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe2, 0x65);
mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe3, 0xf8);
- mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x03);
+ if (dsi_ctx->dsi->lanes == 2)
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x01);
+ else
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x03);
}
static inline struct jadard *panel_to_jadard(struct drm_panel *panel)
@@ -151,7 +156,10 @@ static int jadard_get_modes(struct drm_panel *panel,
{
struct jadard *jadard = panel_to_jadard(panel);
- return drm_connector_helper_get_modes_fixed(connector, &jadard->desc->mode);
+ if (jadard->dsi->lanes == 2)
+ return drm_connector_helper_get_modes_fixed(connector, jadard->desc->mode_2ln);
+ else
+ return drm_connector_helper_get_modes_fixed(connector, jadard->desc->mode_4ln);
}
static enum drm_panel_orientation jadard_panel_get_orientation(struct drm_panel *panel)
@@ -354,7 +362,7 @@ static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard)
};
static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = {
- .mode = {
+ .mode_4ln = &(const struct drm_display_mode) {
.clock = 70000,
.hdisplay = 800,
@@ -586,7 +594,7 @@ static int cz101b4001_init_cmds(struct jadard *jadard)
};
static const struct jadard_panel_desc cz101b4001_desc = {
- .mode = {
+ .mode_4ln = &(const struct drm_display_mode) {
.clock = 70000,
.hdisplay = 800,
@@ -819,7 +827,7 @@ static int kingdisplay_kd101ne3_init_cmds(struct jadard *jadard)
};
static const struct jadard_panel_desc kingdisplay_kd101ne3_40ti_desc = {
- .mode = {
+ .mode_4ln = &(const struct drm_display_mode) {
.clock = (800 + 24 + 24 + 24) * (1280 + 30 + 4 + 8) * 60 / 1000,
.hdisplay = 800,
@@ -1070,7 +1078,7 @@ static int melfas_lmfbx101117480_init_cmds(struct jadard *jadard)
};
static const struct jadard_panel_desc melfas_lmfbx101117480_desc = {
- .mode = {
+ .mode_4ln = &(const struct drm_display_mode) {
.clock = (800 + 24 + 24 + 24) * (1280 + 30 + 4 + 8) * 60 / 1000,
.hdisplay = 800,
@@ -1326,7 +1334,7 @@ static int anbernic_rgds_init_cmds(struct jadard *jadard)
};
static const struct jadard_panel_desc anbernic_rgds_display_desc = {
- .mode = {
+ .mode_4ln = &(const struct drm_display_mode) {
.clock = (640 + 260 + 220 + 260) * (480 + 10 + 2 + 16) * 60 / 1000,
.hdisplay = 640,
@@ -1562,7 +1570,7 @@ static int taiguan_xti05101_01a_init_cmds(struct jadard *jadard)
};
static const struct jadard_panel_desc taiguan_xti05101_01a_desc = {
- .mode = {
+ .mode_4ln = &(const struct drm_display_mode) {
.clock = (800 + 24 + 24 + 24) * (1280 + 30 + 4 + 8) * 60 / 1000,
.hdisplay = 800,
@@ -1614,6 +1622,12 @@ static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
dsi->format = desc->format;
dsi->lanes = desc->lanes;
+ if (!dsi->lanes) {
+ dsi->lanes = drm_of_get_data_lanes_count_remote(dsi->dev.of_node, 0, -1, 2, 4);
+ if (dsi->lanes < 0)
+ return dsi->lanes;
+ }
+ dev_dbg(&dsi->dev, "lanes: %d\n", dsi->lanes);
jadard->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(jadard->reset))
--
2.47.3
^ permalink raw reply related
* [PATCH 11/19] drm/panel: jadard-jd9365da-h3: use drm_connector_helper_get_modes_fixed
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Use existing helper instead of manually coding it.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/Kconfig | 1 +
drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 19 ++-----------------
2 files changed, 3 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d6863b28ddc5..ba527b4d7737 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -337,6 +337,7 @@ config DRM_PANEL_JADARD_JD9365DA_H3
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
+ select DRM_KMS_HELPER
help
Say Y here if you want to enable support for Jadard JD9365DA-H3
WXGA MIPI DSI panel. The panel support TFT dot matrix LCD with
diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index c33c611e03c0..1884ad2404cd 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -12,6 +12,7 @@
#include <drm/drm_modes.h>
#include <drm/drm_panel.h>
#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
#include <linux/gpio/consumer.h>
#include <linux/delay.h>
@@ -149,24 +150,8 @@ static int jadard_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
struct jadard *jadard = panel_to_jadard(panel);
- const struct drm_display_mode *desc_mode = &jadard->desc->mode;
- struct drm_display_mode *mode;
-
- mode = drm_mode_duplicate(connector->dev, desc_mode);
- if (!mode) {
- DRM_DEV_ERROR(&jadard->dsi->dev, "failed to add mode %ux%ux@%u\n",
- desc_mode->hdisplay, desc_mode->vdisplay,
- drm_mode_vrefresh(desc_mode));
- return -ENOMEM;
- }
-
- drm_mode_set_name(mode);
- drm_mode_probed_add(connector, mode);
-
- connector->display_info.width_mm = mode->width_mm;
- connector->display_info.height_mm = mode->height_mm;
- return 1;
+ return drm_connector_helper_get_modes_fixed(connector, &jadard->desc->mode);
}
static enum drm_panel_orientation jadard_panel_get_orientation(struct drm_panel *panel)
--
2.47.3
^ permalink raw reply related
* [PATCH 10/19] drm/panel: himax-hx8394: support Waveshare DSI panels
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Enable support for Waveshare 5.0" and 5.5" DSI TOUCH-A panels.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-himax-hx8394.c | 244 +++++++++++++++++++++++++++++
1 file changed, 244 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-himax-hx8394.c b/drivers/gpu/drm/panel/panel-himax-hx8394.c
index 1f23c50b6661..bf80354567df 100644
--- a/drivers/gpu/drm/panel/panel-himax-hx8394.c
+++ b/drivers/gpu/drm/panel/panel-himax-hx8394.c
@@ -44,6 +44,7 @@
#define HX8394_CMD_SETID 0xc3
#define HX8394_CMD_SETDDB 0xc4
#define HX8394_CMD_UNKNOWN2 0xc6
+#define HX8394_CMD_UNKNOWN6 0xc7
#define HX8394_CMD_SETCABC 0xc9
#define HX8394_CMD_SETCABCGAIN 0xca
#define HX8394_CMD_SETPANEL 0xcc
@@ -618,6 +619,247 @@ static const struct hx8394_panel_desc hl055fhav028c_desc = {
.init_sequence = hl055fhav028c_init_sequence,
};
+static void waveshare_5_0_inch_a_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
+{
+ /* 5.19.8 SETEXTC: Set extension command (B9h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC,
+ 0xff, 0x83, 0x94);
+
+ /* 5.19.2 SETPOWER: Set power (B1h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,
+ 0x48, 0x0a, 0x6a, 0x09, 0x33, 0x54, 0x71, 0x71, 0x2e, 0x45);
+
+ /* 5.19.9 SETMIPI: Set MIPI control (BAh) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI,
+ 0x61, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
+
+ /* 5.19.3 SETDISP: Set display related register (B2h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP,
+ 0x00, 0x80, 0x64, 0x0c, 0x06, 0x2f);
+
+ /* 5.19.4 SETCYC: Set display waveform cycles (B4h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC,
+ 0x1c, 0x78, 0x1c, 0x78, 0x1c, 0x78, 0x01, 0x0c, 0x86, 0x75,
+ 0x00, 0x3f, 0x1c, 0x78, 0x1c, 0x78, 0x1c, 0x78, 0x01, 0x0c,
+ 0x86);
+
+ /* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x32, 0x10,
+ 0x05, 0x00, 0x05, 0x32, 0x13, 0xc1, 0x00, 0x01, 0x32, 0x10,
+ 0x08, 0x00, 0x00, 0x37, 0x03, 0x07, 0x07, 0x37, 0x05, 0x05,
+ 0x37, 0x0c, 0x40);
+
+ /* 5.19.20 Set GIP Option1 (D5h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1,
+ 0x18, 0x18, 0x18, 0x18, 0x22, 0x23, 0x20, 0x21, 0x04, 0x05,
+ 0x06, 0x07, 0x00, 0x01, 0x02, 0x03, 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x19, 0x19, 0x19, 0x19);
+
+ /* 5.19.21 Set GIP Option2 (D6h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2,
+ 0x18, 0x18, 0x19, 0x19, 0x21, 0x20, 0x23, 0x22, 0x03, 0x02,
+ 0x01, 0x00, 0x07, 0x06, 0x05, 0x04, 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x19, 0x19, 0x18, 0x18);
+
+ /* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGAMMA,
+ 0x07, 0x08, 0x09, 0x0d, 0x10, 0x14, 0x16, 0x13, 0x24, 0x36,
+ 0x48, 0x4a, 0x58, 0x6f, 0x76, 0x80, 0x97, 0xa5, 0xa8, 0xb5,
+ 0xc6, 0x62, 0x63, 0x68, 0x6f, 0x72, 0x78, 0x7f, 0x7f, 0x00,
+ 0x02, 0x08, 0x0d, 0x0c, 0x0e, 0x0f, 0x10, 0x24, 0x36, 0x48,
+ 0x4a, 0x58, 0x6f, 0x78, 0x82, 0x99, 0xa4, 0xa0, 0xb1, 0xc0,
+ 0x5e, 0x5e, 0x64, 0x6b, 0x6c, 0x73, 0x7f, 0x7f);
+
+ /* 5.19.17 SETPANEL (CCh) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPANEL,
+ 0x0b);
+
+ /* Unknown command, not listed in the HX8394-F datasheet */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN1,
+ 0x1f, 0x73);
+
+ /* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETVCOM,
+ 0x6b, 0x6b);
+
+ /* Unknown command, not listed in the HX8394-F datasheet */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3,
+ 0x02);
+
+ /* 5.19.11 Set register bank (BDh) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
+ 0x01);
+
+ /* 5.19.2 SETPOWER: Set power (B1h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,
+ 0x00);
+
+ /* 5.19.11 Set register bank (BDh) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
+ 0x00);
+
+ /* Unknown command, not listed in the HX8394-F datasheet */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN5,
+ 0x40, 0x81, 0x50, 0x00, 0x1a, 0xfc, 0x01);
+};
+
+static const struct drm_display_mode waveshare_5_0_inch_a_mode = {
+ .clock = 70000,
+ .hdisplay = 720,
+ .hsync_start = 720 + 40,
+ .hsync_end = 720 + 40 + 20,
+ .htotal = 720 + 40 + 20 + 20,
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 30,
+ .vsync_end = 1280 + 30 + 10,
+ .vtotal = 1280 + 30 + 10 + 4,
+ .width_mm = 62,
+ .height_mm = 110,
+};
+
+static const struct hx8394_panel_desc waveshare_5_0_inch_a_desc = {
+ .mode = &waveshare_5_0_inch_a_mode,
+ .lanes = 2,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+ .format = MIPI_DSI_FMT_RGB888,
+ .init_sequence = waveshare_5_0_inch_a_init_sequence,
+};
+
+static const struct drm_display_mode waveshare_5_5_inch_a_mode = {
+ .clock = 65000,
+ .hdisplay = 720,
+ .hsync_start = 720 + 50,
+ .hsync_end = 720 + 50 + 50,
+ .htotal = 720 + 50 + 50 + 10,
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 15,
+ .vsync_end = 1280 + 15 + 12,
+ .vtotal = 1280 + 15 + 12 + 4,
+ .width_mm = 62,
+ .height_mm = 110,
+};
+
+static void waveshare_5_5_inch_a_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
+{
+ /* 5.19.8 SETEXTC: Set extension command (B9h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC,
+ 0xff, 0x83, 0x94);
+
+ /* 5.19.9 SETMIPI: Set MIPI control (BAh) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI,
+ 0x61, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
+
+ /* 5.19.2 SETPOWER: Set power (B1h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,
+ 0x48, 0x12, 0x72, 0x09, 0x32, 0x54, 0x71, 0x71, 0x57, 0x47);
+
+ /* 5.19.3 SETDISP: Set display related register (B2h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP,
+ 0x00, 0x80, 0x64, 0x0c, 0x0d, 0x2f);
+
+ /* 5.19.4 SETCYC: Set display waveform cycles (B4h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC,
+ 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c, 0x86, 0x75,
+ 0x00, 0x3f, 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c,
+ 0x86);
+
+ /* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETVCOM,
+ 0x86, 0x86);
+
+ /* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0,
+ 0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 0x0c, 0x00, 0x08, 0x10,
+ 0x08, 0x00, 0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a, 0x02, 0x15,
+ 0x06, 0x05, 0x06, 0x47, 0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07,
+ 0x07, 0x0c, 0x40);
+
+ /* 5.19.20 Set GIP Option1 (D5h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1,
+ 0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+ 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25, 0x18, 0x18,
+ 0x26, 0x27, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21,
+ 0x18, 0x18, 0x18, 0x18);
+
+ /* 5.19.21 Set GIP Option2 (D6h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2,
+ 0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02,
+ 0x01, 0x00, 0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20, 0x18, 0x18,
+ 0x27, 0x26, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x25, 0x24,
+ 0x18, 0x18, 0x18, 0x18);
+
+ /* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGAMMA,
+ 0x00, 0x13, 0x21, 0x28, 0x2b, 0x2e, 0x32, 0x2f, 0x61, 0x6e,
+ 0x7e, 0x7b, 0x80, 0x8f, 0x91, 0x93, 0x9d, 0x9d, 0x97, 0xa4,
+ 0xb1, 0x57, 0x55, 0x58, 0x5d, 0x60, 0x67, 0x74, 0x7f, 0x00,
+ 0x13, 0x21, 0x28, 0x2b, 0x2e, 0x32, 0x2f, 0x61, 0x6e, 0x7d,
+ 0x7b, 0x7f, 0x8e, 0x90, 0x93, 0x9c, 0x9d, 0x98, 0xa4, 0xb1,
+ 0x58, 0x55, 0x59, 0x5e, 0x61, 0x68, 0x76, 0x7f);
+
+ /* Unknown command, not listed in the HX8394-F datasheet */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN1,
+ 0x1f, 0x31);
+
+ /* 5.19.17 SETPANEL (CCh) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPANEL,
+ 0x07);
+
+ /* Unknown command, not listed in the HX8394-F datasheet */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3,
+ 0x02);
+
+ /* 5.19.11 Set register bank (BDh) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
+ 0x02);
+
+ /* Unknown command, not listed in the HX8394-F datasheet */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN4,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff);
+
+ /* 5.19.11 Set register bank (BDh) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
+ 0x00);
+
+ /* 5.19.11 Set register bank (BDh) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
+ 0x01);
+
+ /* 5.19.2 SETPOWER: Set power (B1h) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,
+ 0x00);
+
+ /* 5.19.11 Set register bank (BDh) */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
+ 0x00);
+
+ /* Unknown command, not listed in the HX8394-F datasheet */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN2,
+ 0xed);
+
+ /* Unknown command, not listed in the HX8394-F datasheet */
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN6,
+ 0x00, 0xc0);
+};
+
+static const struct hx8394_panel_desc waveshare_5_5_inch_a_desc = {
+ .mode = &waveshare_5_5_inch_a_mode,
+ .lanes = 2,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+ .format = MIPI_DSI_FMT_RGB888,
+ .init_sequence = waveshare_5_5_inch_a_init_sequence,
+};
+
static int hx8394_disable(struct drm_panel *panel)
{
struct hx8394 *ctx = panel_to_hx8394(panel);
@@ -815,6 +1057,8 @@ static const struct of_device_id hx8394_of_match[] = {
{ .compatible = "huiling,hl055fhav028c", .data = &hl055fhav028c_desc },
{ .compatible = "powkiddy,x55-panel", .data = &powkiddy_x55_desc },
{ .compatible = "microchip,ac40t08a-mipi-panel", .data = &mchp_ac40t08a_desc },
+ { .compatible = "waveshare,5.0-dsi-touch-a", .data = &waveshare_5_0_inch_a_desc },
+ { .compatible = "waveshare,5.5-dsi-touch-a", .data = &waveshare_5_5_inch_a_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, hx8394_of_match);
--
2.47.3
^ permalink raw reply related
* [PATCH 09/19] drm/panel: himax-hx8394: simplify hx8394_enable()
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Simplify hx8394_enable() function by using hx8394_disable() instead of
open-coding it and mipi_dsi_msleep() instead of manual checks.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-himax-hx8394.c | 41 ++++++++++--------------------
1 file changed, 14 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-himax-hx8394.c b/drivers/gpu/drm/panel/panel-himax-hx8394.c
index d64f3521eb15..1f23c50b6661 100644
--- a/drivers/gpu/drm/panel/panel-himax-hx8394.c
+++ b/drivers/gpu/drm/panel/panel-himax-hx8394.c
@@ -618,47 +618,34 @@ static const struct hx8394_panel_desc hl055fhav028c_desc = {
.init_sequence = hl055fhav028c_init_sequence,
};
-static int hx8394_enable(struct drm_panel *panel)
+static int hx8394_disable(struct drm_panel *panel)
{
struct hx8394 *ctx = panel_to_hx8394(panel);
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
- int ret;
-
- ctx->desc->init_sequence(&dsi_ctx);
-
- mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
-
- if (dsi_ctx.accum_err)
- return dsi_ctx.accum_err;
- /* Panel is operational 120 msec after reset */
- msleep(120);
-
- mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
- if (dsi_ctx.accum_err)
- goto sleep_in;
-
- return 0;
-
-sleep_in:
- ret = dsi_ctx.accum_err;
- dsi_ctx.accum_err = 0;
- /* This will probably fail, but let's try orderly power off anyway. */
mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
- mipi_dsi_msleep(&dsi_ctx, 50);
+ mipi_dsi_msleep(&dsi_ctx, 50); /* about 3 frames */
- return ret;
+ return dsi_ctx.accum_err;
}
-static int hx8394_disable(struct drm_panel *panel)
+static int hx8394_enable(struct drm_panel *panel)
{
struct hx8394 *ctx = panel_to_hx8394(panel);
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
- mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
- mipi_dsi_msleep(&dsi_ctx, 50); /* about 3 frames */
+ ctx->desc->init_sequence(&dsi_ctx);
+
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+
+ /* Panel is operational 120 msec after reset */
+ mipi_dsi_msleep(&dsi_ctx, 120);
+
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ if (dsi_ctx.accum_err)
+ hx8394_disable(panel);
return dsi_ctx.accum_err;
}
--
2.47.3
^ permalink raw reply related
* [PATCH 08/19] drm/panel: himax-hx8394: set prepare_prev_first
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Sending DSI commands from the prepare() callback requires DSI link to be
up at that point. For DSI hosts is guaranteed only if the panel driver
sets the .prepare_prev_first flag. Set it to let these panels work with
the DSI hosts which don't power on the link in their .mode_set callback.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-himax-hx8394.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-himax-hx8394.c b/drivers/gpu/drm/panel/panel-himax-hx8394.c
index c4d3e09a228d..d64f3521eb15 100644
--- a/drivers/gpu/drm/panel/panel-himax-hx8394.c
+++ b/drivers/gpu/drm/panel/panel-himax-hx8394.c
@@ -792,6 +792,8 @@ static int hx8394_probe(struct mipi_dsi_device *dsi)
if (ret)
return ret;
+ ctx->panel.prepare_prev_first = true;
+
drm_panel_add(&ctx->panel);
ret = mipi_dsi_attach(dsi);
--
2.47.3
^ permalink raw reply related
* [PATCH 07/19] drm/panel: himax-hx83102: support Waveshare 12.3" DSI panel
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Add support for the Waveshare 12.3" DSI TOUCH-A panel. According to the
vendor driver, it uses different mode_flags, so let the panel
descriptions override driver-wide defaults.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-himax-hx83102.c | 144 +++++++++++++++++++++++++++-
1 file changed, 142 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c b/drivers/gpu/drm/panel/panel-himax-hx83102.c
index 8b2a68ee851e..eab67893da86 100644
--- a/drivers/gpu/drm/panel/panel-himax-hx83102.c
+++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c
@@ -29,11 +29,14 @@
#define HX83102_UNKNOWN_B8 0xb8
#define HX83102_SETEXTC 0xb9
#define HX83102_SETMIPI 0xba
+#define HX83102_UNKNOWN_BB 0xbb
#define HX83102_SETVDC 0xbc
#define HX83102_SETBANK 0xbd
#define HX83102_UNKNOWN_BE 0xbe
#define HX83102_SETPTBA 0xbf
#define HX83102_SETSTBA 0xc0
+#define HX83102_UNKNOWN_C2 0xc2
+#define HX83102_UNKNOWN_C6 0xc6
#define HX83102_SETTCON 0xc7
#define HX83102_SETRAMDMY 0xc8
#define HX83102_SETPWM 0xc9
@@ -78,6 +81,7 @@ struct hx83102_panel_desc {
} size;
bool has_backlight;
+ unsigned long mode_flags;
int (*init)(struct hx83102 *ctx);
};
@@ -765,6 +769,111 @@ static int holitech_htf065h045_init(struct hx83102 *ctx)
return dsi_ctx.accum_err;
}
+/* This is HX83102-E, assuming commands are the same as the normal HX83102 */
+static int waveshare_12_3_a_init(struct hx83102 *ctx)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETEXTC, 0x83, 0x10, 0x2e);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BB, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x67, 0x2c, 0xff, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x11, 0x96, 0x89);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0x04, 0x03, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER,
+ 0x10, 0xfa, 0xaf, 0xaf, 0x33, 0x33, 0xb1, 0x4d, 0x2f, 0x36,
+ 0x36, 0x36, 0x36, 0x22, 0x21, 0x15, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP,
+ 0x00, 0xd0, 0x27, 0x80, 0x00, 0x14, 0x40, 0x2c, 0x32, 0x02,
+ 0x00, 0x00, 0x15, 0x20, 0xd7, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC,
+ 0x98, 0xa0, 0x01, 0x01, 0x98, 0xa0, 0x68, 0x50, 0x01, 0xc7,
+ 0x01, 0x58, 0x00, 0xff, 0x00, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B6, 0x4d, 0x4d, 0xe3);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x85, 0x80);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x33, 0x33);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,
+ 0x00, 0x00, 0x00, 0x00, 0x64, 0x04, 0x00, 0x08, 0x08, 0x27,
+ 0x27, 0x22, 0x2f, 0x15, 0x15, 0x04, 0x04, 0x32, 0x10, 0x13,
+ 0x00, 0x13, 0x32, 0x10, 0x1f, 0x00,
+ 0x02, 0x32, 0x17, 0xfd, 0x00, 0x10, 0x00, 0x00, 0x20,
+ 0x30, 0x01, 0x55, 0x21, 0x38, 0x01, 0x55, 0x0f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA,
+ 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64, 0x69, 0x6c, 0x64,
+ 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85, 0x9a, 0x97, 0x4d,
+ 0x56, 0x64, 0x70, 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64,
+ 0x69, 0x6c, 0x64, 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85,
+ 0x9a, 0x97, 0x4d, 0x56, 0x64, 0x76);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x9b, 0x01, 0x31);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK,
+ 0x80, 0x36, 0x12, 0x16, 0xc0, 0x28, 0x40, 0x84, 0x22);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,
+ 0x01, 0x00, 0xfc, 0x00, 0x00, 0x11, 0x10, 0x00, 0x0e, 0x00,
+ 0x01);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x4e, 0x00, 0x33, 0x11, 0x33, 0x88);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2, 0x00, 0x02);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA,
+ 0x23, 0x23, 0x22, 0x11, 0xa2, 0x17, 0x00, 0x80, 0x00, 0x00,
+ 0x08, 0x00, 0x63, 0x63);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C6, 0xf9);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY,
+ 0x00, 0x04, 0x04, 0x00, 0x00, 0x82, 0x13, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x07, 0x04, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x21, 0x20,
+ 0x01, 0x00, 0x03, 0x02, 0x05, 0x04, 0x07, 0x06, 0x1a, 0x1a,
+ 0x1a, 0x1a, 0x9a, 0x9a, 0x9a, 0x9a, 0x18, 0x18, 0x18, 0x18,
+ 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21, 0x20, 0x21,
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x1a, 0x1a,
+ 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x18, 0x18, 0x18, 0x18,
+ 0x20, 0x21, 0x20, 0x21, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,
+ 0x98, 0x98, 0x98, 0x98);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1,
+ 0x00, 0x34, 0x01, 0x88, 0x0e, 0xbe, 0x0f);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C2, 0x43, 0xff, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x80);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,
+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xaa, 0x80, 0x2a, 0xaa, 0xaa, 0xaa, 0xaa, 0x80,
+ 0x2a, 0xaa, 0xaa, 0xaa);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,
+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xf0, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf0);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
+
+ return dsi_ctx.accum_err;
+};
+
static const struct drm_display_mode starry_mode = {
.clock = 162680,
.hdisplay = 1200,
@@ -920,6 +1029,30 @@ static const struct hx83102_panel_desc holitech_htf065h045_desc = {
.init = holitech_htf065h045_init,
};
+static const struct drm_display_mode waveshare_12_3_a_mode = {
+ .clock = 95000,
+ .hdisplay = 720,
+ .hsync_start = 720 + 10,
+ .hsync_end = 720 + 10 + 10,
+ .htotal = 720 + 10 + 10 + 12,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 64,
+ .vsync_end = 1920 + 64 + 18,
+ .vtotal = 1920 + 64 + 18 + 4,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct hx83102_panel_desc waveshare_12_3_inch_a_desc = {
+ .modes = &waveshare_12_3_a_mode,
+ .size = {
+ .width_mm = 109,
+ .height_mm = 292,
+ },
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+ .init = waveshare_12_3_a_init,
+};
+
static int hx83102_enable(struct drm_panel *panel)
{
msleep(130);
@@ -1168,8 +1301,12 @@ static int hx83102_probe(struct mipi_dsi_device *dsi)
desc = of_device_get_match_data(&dsi->dev);
dsi->lanes = 4;
dsi->format = MIPI_DSI_FMT_RGB888;
- dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
- MIPI_DSI_MODE_LPM;
+ if (desc->mode_flags)
+ dsi->mode_flags = desc->mode_flags;
+ else
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM;
ctx->desc = desc;
ctx->dsi = dsi;
ret = hx83102_panel_add(ctx);
@@ -1220,6 +1357,9 @@ static const struct of_device_id hx83102_of_match[] = {
{ .compatible = "holitech,htf065h045",
.data = &holitech_htf065h045_desc
},
+ { .compatible = "waveshare,12.3-dsi-touch-a",
+ .data = &waveshare_12_3_inch_a_desc
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, hx83102_of_match);
--
2.47.3
^ permalink raw reply related
* [PATCH 06/19] drm/of: add helper to count data-lanes on a remote endpoint
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
If the DSI panel supports versatile lanes configuration, its driver
might require determining the number of DSI data lanes, which is usually
specified on the DSI host side of the OF graph. Add new helper as a
pair to drm_of_get_data_lanes_count_ep() that lets callers determine
number of data-lanes on the remote side of the OF graph.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/drm_of.c | 34 ++++++++++++++++++++++++++++++++++
include/drm/drm_of.h | 13 +++++++++++++
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
index 4f65ce729a47..ef6b09316963 100644
--- a/drivers/gpu/drm/drm_of.c
+++ b/drivers/gpu/drm/drm_of.c
@@ -558,6 +558,40 @@ int drm_of_get_data_lanes_count_ep(const struct device_node *port,
}
EXPORT_SYMBOL_GPL(drm_of_get_data_lanes_count_ep);
+/**
+ * drm_of_get_data_lanes_count_remote - Get DSI/(e)DP data lane count by endpoint
+ * @port: DT port node of the DSI/(e)DP source or sink
+ * @port_reg: identifier (value of reg property) of the parent port node
+ * @reg: identifier (value of reg property) of the endpoint node
+ * @min: minimum supported number of data lanes
+ * @max: maximum supported number of data lanes
+ *
+ * Count DT "data-lanes" property elements in the remote endpoint and check for
+ * validity. This variant uses endpoint specifier.
+ *
+ * Return:
+ * * min..max - positive integer count of "data-lanes" elements
+ * * -EINVAL - the "data-lanes" property is unsupported
+ * * -ENODEV - the "data-lanes" property is missing
+ */
+int drm_of_get_data_lanes_count_remote(const struct device_node *port,
+ int port_reg, int reg,
+ const unsigned int min,
+ const unsigned int max)
+{
+ struct device_node *endpoint, *remote;
+ int ret;
+
+ endpoint = of_graph_get_endpoint_by_regs(port, port_reg, reg);
+ remote = of_graph_get_remote_endpoint(endpoint);
+ of_node_put(endpoint);
+ ret = drm_of_get_data_lanes_count(remote, min, max);
+ of_node_put(remote);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(drm_of_get_data_lanes_count_remote);
+
#if IS_ENABLED(CONFIG_DRM_MIPI_DSI)
/**
diff --git a/include/drm/drm_of.h b/include/drm/drm_of.h
index f2f2bf82eff9..7bcc0ccfe0f4 100644
--- a/include/drm/drm_of.h
+++ b/include/drm/drm_of.h
@@ -62,6 +62,10 @@ int drm_of_get_data_lanes_count_ep(const struct device_node *port,
int port_reg, int reg,
const unsigned int min,
const unsigned int max);
+int drm_of_get_data_lanes_count_remote(const struct device_node *port,
+ int port_reg, int reg,
+ const unsigned int min,
+ const unsigned int max);
#else
static inline uint32_t drm_of_crtc_port_mask(struct drm_device *dev,
struct device_node *port)
@@ -140,6 +144,15 @@ drm_of_get_data_lanes_count_ep(const struct device_node *port,
{
return -EINVAL;
}
+
+static inline int
+drm_of_get_data_lanes_count_remote(const struct device_node *port,
+ int port_reg, int reg,
+ const unsigned int min,
+ const unsigned int max)
+{
+ return -EINVAL;
+}
#endif
#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DRM_MIPI_DSI)
--
2.47.3
^ permalink raw reply related
* [PATCH 05/19] dt-bindings: dipslay/panel: describe panels using Focaltech OTA7290B
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Add schema for the panels using Focaltech OTA7290B controller. For now
there is only one such panel, from the Waveshare 8.8 DSI TOUCH-A kit.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../bindings/display/panel/focaltech,ota7290b.yaml | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml b/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml
new file mode 100644
index 000000000000..da5237404dc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/focaltech,ota7290b.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Focaltech OTA7290B DSI panels
+
+maintainers:
+ - Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ - const: waveshare,8.88-dsi-touch-a
+
+ reg:
+ maxItems: 1
+
+ vdd-supply:
+ description: supply regulator for VDD, usually 3.3V
+
+ vdda-supply:
+ description: supply regulator for VDDA, 7-10V
+
+ vcc-supply:
+ description: supply regulator for VCCIO, usually 1.5V
+
+ reset-gpios: true
+ backlight: true
+ rotation: true
+ port: true
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+ - vccio-supply
+ - reset-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "waveshare,8.8-dsi-touch-a";
+ reg = <0>;
+ vdd-supply = <&vdd>;
+ vccio-supply = <&vccio>;
+ reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ backlight = <&backlight>;
+
+ port {
+ endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+ };
+
+...
+
--
2.47.3
^ permalink raw reply related
* [PATCH 04/19] dt-bindings: display/panel: ilitek,ili9881c: describe Waveshare panel
From: Dmitry Baryshkov @ 2026-04-01 7:26 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>
Describe Waveshare 7" DSI panel which uses ILI9881 as a panel
controller. This panel requires two voltags supplies, so add separate
iovcc supply.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml
index d979701a00a8..42e35986fbf6 100644
--- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml
@@ -24,6 +24,7 @@ properties:
- raspberrypi,dsi-7inch
- startek,kd050hdfia020
- tdo,tl050hdv35
+ - waveshare,7.0-dsi-touch-a
- wanchanglong,w552946aaa
- wanchanglong,w552946aba
- const: ilitek,ili9881c
@@ -34,6 +35,7 @@ properties:
backlight: true
port: true
power-supply: true
+ iovcc-supply: true
reset-gpios: true
rotation: true
--
2.47.3
^ permalink raw reply related
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