* Re: [PATCH v12 00/15] arm64/riscv: Add support for crashkernel CMA reservation
From: Borislav Petkov @ 2026-04-02 11:31 UTC (permalink / raw)
To: Jinjie Ruan
Cc: corbet, skhan, catalin.marinas, will, chenhuacai, kernel, maddy,
mpe, npiggin, chleroy, pjw, palmer, aou, alex, tglx, mingo,
dave.hansen, hpa, robh, saravanak, akpm, bhe, vgoyal, dyoung,
rdunlap, peterz, pawan.kumar.gupta, feng.tang, dapeng1.mi, kees,
elver, paulmck, lirongqing, rppt, leitao, ardb, jbohac, cfsworks,
tangyouling, sourabhjain, ritesh.list, hbathini, eajames, guoren,
songshuaishuai, kevin.brodsky, vishal.moola, junhui.liu, coxu,
fuqiang.wang, liaoyuanhong, takahiro.akashi, james.morse,
lizhengyu3, x86, linux-doc, linux-kernel, linux-arm-kernel,
loongarch, linuxppc-dev, linux-riscv, devicetree, kexec
In-Reply-To: <20260402072701.628293-1-ruanjinjie@huawei.com>
On Thu, Apr 02, 2026 at 03:26:46PM +0800, Jinjie Ruan wrote:
> The crash memory allocation, and the exclude of crashk_res, crashk_low_res
> and crashk_cma memory are almost identical across different architectures,
> This patch set handle them in crash core in a general way, which eliminate
> a lot of duplication code.
From: Documentation/process/submitting-patches.rst
"Don't get discouraged - or impatient
------------------------------------
After you have submitted your change, be patient and wait. Reviewers are
busy people and may not get to your patch right away.
Once upon a time, patches used to disappear into the void without comment,
but the development process works more smoothly than that now. You should
receive comments within a week or so; if that does not happen, make sure
that you have sent your patches to the right place. Wait for a minimum of
^^^^^^^^^^^^^^^^^^^^^
one week before resubmitting or pinging reviewers - possibly longer during
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
busy times like merge windows."
You need to be patient and send once a week and not spam people:
Feb 04 Jinjie Ruan ( :1.0K|) [PATCH v3 0/3] arm64/riscv: Add support for crashkernel CMA reservation
Feb 09 Jinjie Ruan ( :1.5K|) [PATCH v4 0/3] arm64/riscv: Add support for crashkernel CMA reservation
Feb 12 Jinjie Ruan ( :2.1K|) [PATCH v5 0/4] arm64/riscv: Add support for crashkernel CMA reservation
Feb 24 Jinjie Ruan ( :2.3K|) [PATCH v6 0/5] arm64/riscv: Add support for crashkernel CMA reservation
Feb 26 Jinjie Ruan ( :2.5K|) [PATCH v7 0/5] arm64/riscv: Add support for crashkernel CMA reservation
Mar 02 Jinjie Ruan ( :2.8K|) [PATCH v8 0/5] arm64/riscv: Add support for crashkernel CMA reservation
Mar 23 Jinjie Ruan ( :2.9K|) [PATCH v9 0/5] arm64/riscv: Add support for crashkernel CMA reservation
Mar 25 Jinjie Ruan ( :3.7K|) [PATCH v10 0/8] arm64/riscv: Add support for crashkernel CMA reservation
Mar 28 Jinjie Ruan ( :4.3K|) [PATCH v11 00/11] arm64/riscv: Add support for crashkernel CMA reservation
Apr 02 Jinjie Ruan ( :4.5K|) [PATCH v12 00/15] arm64/riscv: Add support for crashkernel CMA reservation
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
^ permalink raw reply
* [PATCH v1 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add clocks and resets nodes for JHB100 RISC-V BMC SoC. They contain
sys0crg/sys1crg/sys2crg/per0crg/per1crg/per2crg/per3crg.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jhb100.dtsi | 198 ++++++++++++++++++++++-
1 file changed, 195 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
index 4d03470f78ab..700d00f800bc 100644
--- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -4,6 +4,8 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <dt-bindings/reset/starfive,jhb100-crg.h>
/ {
compatible = "starfive,jhb100";
@@ -268,12 +270,96 @@ pmu {
<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */
};
- clk_uart: clk-uart {
- compatible = "fixed-clock"; /* Initial clock handler for UART */
+ osc: osc {
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
+ pll0: pll0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400000000>;
+ };
+
+ pll1: pll1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+
+ pll2: pll2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <903168000>;
+ };
+
+ pll4: pll4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100700000>;
+ };
+
+ pll5: pll5 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100700000>;
+ };
+
+ pll6: pll6 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400000000>;
+ };
+
+ pll7: pll7 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1950000000>;
+ };
+
+ per2_gmac2_rgmii_rx: per2-gmac2-rgmii-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per2_gmac2_rmii_ref: per2-gmac2-rmii-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ per2_gmac3_sgmii_tx: per2-gmac3-sgmii-tx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per2_gmac3_sgmii_rx: per2-gmac3-sgmii-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per3_gmac0_rmii_rclki: per3-gmac0-rmii-rclki {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ per3_gmac1_sgmii_tx: per3-gmac1-sgmii-tx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per3_gmac1_sgmii_rx: per3-gmac1-sgmii-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -315,12 +401,118 @@ bus_nioc: bus_nioc {
uart6: serial@11982000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x11982000 0x0 0x400>;
- clocks = <&clk_uart>, <&clk_uart>;
+ clocks = <&per0crg JHB100_PER0CLK_SCLK_UART6>,
+ <&per0crg JHB100_PER0CLK_APB_UART6>;
clock-names = "baudclk", "apb_pclk";
+ resets = <&per0crg JHB100_PER0RST_MAIN_RSTN_UART6>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
+
+ per0crg: clock-controller@11a08000 {
+ compatible = "starfive,jhb100-per0crg";
+ reg = <0x0 0x11a08000 0x0 0x1000>;
+ clocks = <&osc>, <&pll6>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER0_400>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER0_800>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER0_600>,
+ <&sys2crg JHB100_SYS2CLK_BMCPER0_200>;
+ clock-names = "osc", "pll6", "per0_400",
+ "per0_800", "per0_600",
+ "per0_200_init";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ per1crg: clock-controller@11b40000 {
+ compatible = "starfive,jhb100-per1crg";
+ reg = <0x0 0x11b40000 0x0 0x1000>;
+ clocks = <&pll7>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER1_600>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER1_800>,
+ <&sys2crg JHB100_SYS2CLK_BMCPER1_200>,
+ <&sys2crg JHB100_SYS2CLK_BMCPER1_143>;
+ clock-names = "pll7", "per1_600",
+ "per1_800", "per1_200",
+ "per1_143";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ per2crg: clock-controller@11bc0000 {
+ compatible = "starfive,jhb100-per2crg";
+ reg = <0x0 0x11bc0000 0x0 0x1000>;
+ clocks = <&sys0crg JHB100_SYS0CLK_BMCPER2_600>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER2_400>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER2_125>,
+ <&per2_gmac2_rgmii_rx>,
+ <&per2_gmac2_rmii_ref>,
+ <&per2_gmac3_sgmii_tx>,
+ <&per2_gmac3_sgmii_rx>,
+ <&osc>;
+ clock-names = "per2_600", "per2_400", "per2_125",
+ "per2_gmac2_rgmii_rx",
+ "per2_gmac2_rmii_ref",
+ "per2_gmac3_sgmii_tx",
+ "per2_gmac3_sgmii_rx",
+ "osc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ per3crg: clock-controller@11c40000 {
+ compatible = "starfive,jhb100-per3crg";
+ reg = <0x0 0x11c40000 0x0 0x1000>;
+ clocks = <&sys0crg JHB100_SYS0CLK_BMCPER3_600>,
+ <&sys1crg JHB100_SYS1CLK_BMCPER3_100>,
+ <&sys1crg JHB100_SYS1CLK_BMCPER3_125>,
+ <&per3_gmac0_rmii_rclki>,
+ <&per3_gmac1_sgmii_tx>,
+ <&per3_gmac1_sgmii_rx>,
+ <&osc>;
+ clock-names = "per3_600", "per3_100", "per3_125",
+ "per3_gmac0_rmii_rclki",
+ "per3_gmac1_sgmii_tx",
+ "per3_gmac1_sgmii_rx",
+ "osc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sys0crg: clock-controller@13000000 {
+ compatible = "starfive,jhb100-sys0crg";
+ reg = <0x0 0x13000000 0x0 0x4000>;
+ clocks = <&osc>, <&pll0>, <&pll1>,
+ <&pll2>;
+ clock-names = "osc", "pll0", "pll1", "pll2";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sys1crg: clock-controller@13004000 {
+ compatible = "starfive,jhb100-sys1crg";
+ reg = <0x0 0x13004000 0x0 0x4000>;
+ clocks = <&osc>, <&pll0>, <&pll1>,
+ <&pll2>, <&pll4>, <&pll5>,
+ <&sys0crg JHB100_SYS0CLK_NPU_600>;
+ clock-names = "osc", "pll0", "pll1", "pll2",
+ "pll4", "pll5", "sys1_npu_600";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sys2crg: clock-controller@13008000 {
+ compatible = "starfive,jhb100-sys2crg";
+ reg = <0x0 0x13008000 0x0 0x4000>;
+ clocks = <&osc>, <&pll1>,
+ <&sys0crg JHB100_SYS0CLK_GPU0_600>,
+ <&sys0crg JHB100_SYS0CLK_GPU1_600>;
+ clock-names = "osc", "pll1", "sys2_gpu0_600",
+ "sys2_gpu1_600";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
};
--
2.25.1
^ permalink raw reply related
* [PATCH v1 03/22] clk: starfive: Rename file name "jh71x0" to "common"
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
StarFive JHB100 shares a similar clock and reset design with JH7110.
To facilitate the reuse of the file and its functionalities, files
containing the "jh71x0" naming convention are renamed to use the
"common" wording.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 ++++----
drivers/clk/starfive/Makefile | 2 +-
.../{clk-starfive-jh71x0.c => clk-starfive-common.c} | 4 ++--
.../{clk-starfive-jh71x0.h => clk-starfive-common.h} | 4 ++--
drivers/clk/starfive/clk-starfive-jh7100-audio.c | 2 +-
drivers/clk/starfive/clk-starfive-jh7100.c | 2 +-
drivers/clk/starfive/clk-starfive-jh7110.h | 2 +-
7 files changed, 12 insertions(+), 12 deletions(-)
rename drivers/clk/starfive/{clk-starfive-jh71x0.c => clk-starfive-common.c} (99%)
rename drivers/clk/starfive/{clk-starfive-jh71x0.h => clk-starfive-common.h} (98%)
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index bd29358ffeec..ff8eace36e64 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -1,12 +1,12 @@
# SPDX-License-Identifier: GPL-2.0
-config CLK_STARFIVE_JH71X0
+config CLK_STARFIVE_COMMON
bool
config CLK_STARFIVE_JH7100
bool "StarFive JH7100 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
- select CLK_STARFIVE_JH71X0
+ select CLK_STARFIVE_COMMON
default ARCH_STARFIVE
help
Say yes here to support the clock controller on the StarFive JH7100
@@ -15,7 +15,7 @@ config CLK_STARFIVE_JH7100
config CLK_STARFIVE_JH7100_AUDIO
tristate "StarFive JH7100 audio clock support"
depends on CLK_STARFIVE_JH7100
- select CLK_STARFIVE_JH71X0
+ select CLK_STARFIVE_COMMON
default m if ARCH_STARFIVE
help
Say Y or M here to support the audio clocks on the StarFive JH7100
@@ -33,7 +33,7 @@ config CLK_STARFIVE_JH7110_SYS
bool "StarFive JH7110 system clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
select AUXILIARY_BUS
- select CLK_STARFIVE_JH71X0
+ select CLK_STARFIVE_COMMON
select RESET_STARFIVE_JH7110 if RESET_CONTROLLER
select CLK_STARFIVE_JH7110_PLL
default ARCH_STARFIVE
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 199ac0f37a2f..012f7ee83f8e 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
+obj-$(CONFIG_CLK_STARFIVE_COMMON) += clk-starfive-common.o
obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-common.c
similarity index 99%
rename from drivers/clk/starfive/clk-starfive-jh71x0.c
rename to drivers/clk/starfive/clk-starfive-common.c
index 80e9157347eb..4aecb65e9fd7 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.c
+++ b/drivers/clk/starfive/clk-starfive-common.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * StarFive JH71X0 Clock Generator Driver
+ * StarFive Clock Generator Driver
*
* Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
*/
@@ -10,7 +10,7 @@
#include <linux/device.h>
#include <linux/io.h>
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
{
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-common.h
similarity index 98%
rename from drivers/clk/starfive/clk-starfive-jh71x0.h
rename to drivers/clk/starfive/clk-starfive-common.h
index 9d5dec1d5cd1..f634c62c196a 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.h
+++ b/drivers/clk/starfive/clk-starfive-common.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CLK_STARFIVE_JH71X0_H
-#define __CLK_STARFIVE_JH71X0_H
+#ifndef __CLK_STARFIVE_COMMON_H
+#define __CLK_STARFIVE_COMMON_H
#include <linux/bits.h>
#include <linux/clk-provider.h>
diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
index 7de23f6749aa..4505d309f664 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -15,7 +15,7 @@
#include <dt-bindings/clock/starfive-jh7100-audio.h>
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
/* external clocks */
#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 03f6f26a15d8..bf82190b9c57 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -15,7 +15,7 @@
#include <dt-bindings/clock/starfive-jh7100.h>
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
/* external clocks */
#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h
index 0659adae4d76..6b1bdf860f00 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110.h
+++ b/drivers/clk/starfive/clk-starfive-jh7110.h
@@ -2,7 +2,7 @@
#ifndef __CLK_STARFIVE_JH7110_H
#define __CLK_STARFIVE_JH7110_H
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
/* top clocks of ISP/VOUT domain from JH7110 SYSCRG */
struct jh7110_top_sysclk {
--
2.25.1
^ permalink raw reply related
* [PATCH v1 00/22] Add basic clocks and resets for JHB100 SoC
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
The JHB100 SoC includes CRG (Clock and Reset Generator) for multiple
subsystems:
The JHB100 SoC is divided into multiple subsystems, and basically
each subsystem includes a CRG(Clock and Reset Generator):
- sys0crg/sys1crg/sys2crg/
- per0crg/per1crg/per2crg/per3crg/
- voutcrg
- vcecrg
- gpu0crg/gpu1crg
- cpucrg
- usbcrg
- host0crg/host1crg
- pcierpcrg
- husb0crg/husb1crg
- husbcmncrg
- husbd0crg/husbd1crg
- npucrg
In the current series, we will only add the following CRG:
- sys0crg/sys1crg/sys2crg/
- per0crg/per1crg/per2crg/per3crg/
The remaining CRG will be implemented in future series.
This series depends on the series:
https://lore.kernel.org/all/20260402084019.440708-1-changhuang.liang@starfivetech.com/
and it has been tested on the StarFive JHB100 EVB-1.
Changhuang Liang (18):
dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset
generator
clk: starfive: Add JHB100 System-0 clock generator driver
dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset
generator
clk: starfive: Add JHB100 System-1 clock generator driver
dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset
generator
clk: starfive: Add JHB100 System-2 clock generator driver
dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset
generator
clk: starfive: Introduce inverter and divider
clk: starfive: Expand the storage of clock parent index
clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver
dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset
generator
clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver
dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset
generator
clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver
dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset
generator
clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver
reset: starfive: Add StarFive JHB100 reset driver
riscv: dts: starfive: jhb100: Add clocks and resets nodes
Sia Jee Heng (4):
reset: starfive: Rename file name "jh71x0" to "common"
reset: starfive: Convert the word "jh71x0" to "starfive"
clk: starfive: Rename file name "jh71x0" to "common"
clk: starfive: Convert the word "jh71x0" to "starfive"
.../clock/starfive,jhb100-per0crg.yaml | 70 ++
.../clock/starfive,jhb100-per1crg.yaml | 70 ++
.../clock/starfive,jhb100-per2crg.yaml | 79 +++
.../clock/starfive,jhb100-per3crg.yaml | 78 +++
.../clock/starfive,jhb100-sys0crg.yaml | 63 ++
.../clock/starfive,jhb100-sys1crg.yaml | 71 ++
.../clock/starfive,jhb100-sys2crg.yaml | 64 ++
MAINTAINERS | 13 +
arch/riscv/boot/dts/starfive/jhb100.dtsi | 198 +++++-
drivers/clk/starfive/Kconfig | 67 +-
drivers/clk/starfive/Makefile | 10 +-
drivers/clk/starfive/clk-starfive-common.c | 351 ++++++++++
drivers/clk/starfive/clk-starfive-common.h | 135 ++++
.../clk/starfive/clk-starfive-jh7100-audio.c | 127 ++--
drivers/clk/starfive/clk-starfive-jh7100.c | 503 +++++++-------
.../clk/starfive/clk-starfive-jh7110-aon.c | 62 +-
.../clk/starfive/clk-starfive-jh7110-isp.c | 72 +-
.../clk/starfive/clk-starfive-jh7110-stg.c | 94 +--
.../clk/starfive/clk-starfive-jh7110-sys.c | 525 +++++++-------
.../clk/starfive/clk-starfive-jh7110-vout.c | 74 +-
drivers/clk/starfive/clk-starfive-jh7110.h | 4 +-
drivers/clk/starfive/clk-starfive-jh71x0.c | 339 ---------
drivers/clk/starfive/clk-starfive-jh71x0.h | 127 ----
.../clk/starfive/clk-starfive-jhb100-per0.c | 655 ++++++++++++++++++
.../clk/starfive/clk-starfive-jhb100-per1.c | 204 ++++++
.../clk/starfive/clk-starfive-jhb100-per2.c | 232 +++++++
.../clk/starfive/clk-starfive-jhb100-per3.c | 189 +++++
.../clk/starfive/clk-starfive-jhb100-sys0.c | 253 +++++++
.../clk/starfive/clk-starfive-jhb100-sys1.c | 157 +++++
.../clk/starfive/clk-starfive-jhb100-sys2.c | 178 +++++
drivers/clk/starfive/clk-starfive-jhb100.h | 11 +
drivers/reset/starfive/Kconfig | 15 +-
drivers/reset/starfive/Makefile | 3 +-
...rfive-jh71x0.c => reset-starfive-common.c} | 68 +-
.../reset/starfive/reset-starfive-common.h | 14 +
.../reset/starfive/reset-starfive-jh7100.c | 4 +-
.../reset/starfive/reset-starfive-jh7110.c | 8 +-
.../reset/starfive/reset-starfive-jh71x0.h | 14 -
.../reset/starfive/reset-starfive-jhb100.c | 121 ++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 542 +++++++++++++++
.../dt-bindings/reset/starfive,jhb100-crg.h | 193 ++++++
...rfive-jh71x0.h => reset-starfive-common.h} | 10 +-
42 files changed, 4805 insertions(+), 1262 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per2crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml
create mode 100644 drivers/clk/starfive/clk-starfive-common.c
create mode 100644 drivers/clk/starfive/clk-starfive-common.h
delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per0.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per1.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per2.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per3.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys1.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys2.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100.h
rename drivers/reset/starfive/{reset-starfive-jh71x0.c => reset-starfive-common.c} (55%)
create mode 100644 drivers/reset/starfive/reset-starfive-common.h
delete mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
create mode 100644 drivers/reset/starfive/reset-starfive-jhb100.c
create mode 100644 include/dt-bindings/clock/starfive,jhb100-crg.h
create mode 100644 include/dt-bindings/reset/starfive,jhb100-crg.h
rename include/soc/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (50%)
--
2.25.1
^ permalink raw reply
* [PATCH v4 1/3] dt-bindings: soc: renesas: Document MFIS IP core
From: Wolfram Sang @ 2026-04-02 11:27 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Krzysztof Kozlowski, Marek Vasut, linux-kernel, Wolfram Sang,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Conor Dooley, devicetree
In-Reply-To: <20260402112709.13002-1-wsa+renesas@sang-engineering.com>
Document the Renesas Multifunctional Interface (MFIS) as found on the
Renesas R-Car X5H (r8a78000) SoC. MFIS includes features like Mailbox/HW
Spinlock/Product Register/Error Injection/Error Detection and the likes.
Family-compatible values are not introduced here because MFIS is usually
very different per SoC.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes since v3:
* dropped superfluous constraints (Thanks, Geert!)
* added tags from Krzysztof and Geert (Thanks!)
.../soc/renesas/renesas,r8a78000-mfis.yaml | 187 ++++++++++++++++++
.../dt-bindings/soc/renesas,r8a78000-mfis.h | 28 +++
2 files changed, 215 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml
create mode 100644 include/dt-bindings/soc/renesas,r8a78000-mfis.h
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml
new file mode 100644
index 000000000000..eef8c0a59e9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/renesas/renesas,r8a78000-mfis.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas MFIS (Multifunctional Interface) controller
+
+maintainers:
+ - Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+description:
+ The Renesas Multifunctional Interface (MFIS) provides various functionality
+ like mailboxes, hardware spinlocks, product identification, error injection,
+ error detection and such. Parts of it can be used for communication between
+ different CPU cores. Those cores can be in various domains like AP, RT, or
+ SCP. Often multiple domain-specific MFIS instances exist in one SoC.
+
+properties:
+ compatible:
+ enum:
+ - renesas,r8a78000-mfis # R-Car X5H (AP<->AP, with PRR)
+ - renesas,r8a78000-mfis-scp # R-Car X5H (AP<->SCP, without PRR)
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: common
+ - const: mboxes
+
+ interrupts:
+ minItems: 32
+ maxItems: 128
+ description:
+ The interrupts raised by the remote doorbells.
+
+ interrupt-names:
+ minItems: 32
+ maxItems: 128
+ description:
+ An interrupt name is constructed with the prefix 'ch'. Then, the
+ channel number as specified in the documentation of the SoC. Finally,
+ the letter 'i' if the interrupt is raised by the IICR register. Or 'e'
+ if it is raised by the EICR register.
+
+ "#hwlock-cells":
+ const: 1
+
+ "#mbox-cells":
+ const: 2
+ description:
+ The first cell is the channel number as specified in the documentation
+ of the SoC. The second cell may specify flags as described in the file
+ <dt-bindings/soc/renesas,r8a78000-mfis.h>.
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r8a78000-mfis
+ then:
+ properties:
+ interrupts:
+ minItems: 128
+ interrupt-names:
+ minItems: 128
+ items:
+ pattern: "^ch[0-9]+[ie]$"
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r8a78000-mfis-scp
+ then:
+ properties:
+ interrupts:
+ maxItems: 32
+ interrupt-names:
+ maxItems: 32
+ items:
+ pattern: "^ch[0-9]+i$"
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - "#hwlock-cells"
+ - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ system-controller@189e0000 {
+ compatible = "renesas,r8a78000-mfis";
+ reg = <0x189e0000 0x1000>, <0x18800000 0x40000>;
+ reg-names = "common", "mboxes";
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e",
+ "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e",
+ "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e",
+ "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e",
+ "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e",
+ "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e",
+ "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e",
+ "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e",
+ "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e",
+ "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e",
+ "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e",
+ "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e",
+ "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e",
+ "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e",
+ "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e",
+ "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e";
+ #hwlock-cells = <1>;
+ #mbox-cells = <2>;
+ };
diff --git a/include/dt-bindings/soc/renesas,r8a78000-mfis.h b/include/dt-bindings/soc/renesas,r8a78000-mfis.h
new file mode 100644
index 000000000000..52e17fea1a03
--- /dev/null
+++ b/include/dt-bindings/soc/renesas,r8a78000-mfis.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H
+#define _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H
+
+/*
+ * Constants for the second mbox-cell of the Renesas MFIS IP core. To be treated
+ * as bit flags which can be ORed.
+ */
+
+/*
+ * MFIS HW design before r8a78001 requires a channel to be marked as either
+ * TX or RX.
+ */
+#define MFIS_CHANNEL_TX (0 << 0)
+#define MFIS_CHANNEL_RX (1 << 0)
+
+/*
+ * MFIS variants before r8a78001 work with pairs of IICR and EICR registers.
+ * Usually, it is specified in the datasheets which of the two a specific core
+ * should use. Then, it does not need extra description in DT. For plain MFIS
+ * of r8a78000, this is selectable, though. According to the system design and
+ * the firmware in use, these channels need to be marked. This is not needed
+ * with other versions of the MFIS, not even with MFIS-SCP of r8a78000.
+ */
+#define MFIS_CHANNEL_IICR (0 << 1)
+#define MFIS_CHANNEL_EICR (1 << 1)
+
+#endif
--
2.51.0
^ permalink raw reply related
* [PATCH v4 0/3] soc: renesas: add MFIS driver
From: Wolfram Sang @ 2026-04-02 11:27 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Krzysztof Kozlowski, Marek Vasut, linux-kernel, Wolfram Sang,
Conor Dooley, devicetree, Geert Uytterhoeven, Magnus Damm,
Rob Herring
Changes since v3:
* dropped superfluous constraints in patch 1 (Thanks, Geert!)
* use more 'unsigned int' instead of 'int' in patch 2
* re-ordered declarations to be more xmas-tree like in patch 2
(don't want to go farther than this)
* added tags from Krzysztof to patch 1 (Thanks!)
* added tags from Geert to patches 1+2 (Thanks!)
Renesas R-Car MFIS offers multiple features but most importantly
mailboxes and hwspinlocks. Because they share a common register space
and a common register unprotection mechanism, a single driver was chosen
to handle all dependencies. (MFD and auxiliary bus have been tried as
well, but they failed because of circular dependencies.)
In this first step, the driver implements common register access and a
mailbox controller. hwspinlock support will be added incrementally, once
the subsystem allows out-of-directory drivers (patches already under
review). This driver has been tested on a Renesas Ironhide board (R-Car
X5H) and is able to communicate with the SCP via mailboxes. Also, the
mailbox-test driver was used to confirm back-and-forth communication
between two application cores.
Because of its multifunctional nature, the driver lives in
drivers/soc/renesas. A branch (with some additions to enable it on R-Car
X5H) can be found here:
git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git renesas/x5h/mfis-single-driver
Thanks and happy hacking,
Wolfram
Wolfram Sang (3):
dt-bindings: soc: renesas: Document MFIS IP core
soc: renesas: Add Renesas R-Car MFIS driver
soc: renesas: add X5H PRR support
.../soc/renesas/renesas,r8a78000-mfis.yaml | 187 ++++++++++
drivers/soc/renesas/Kconfig | 9 +
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/rcar-mfis.c | 344 ++++++++++++++++++
drivers/soc/renesas/renesas-soc.c | 8 +-
.../dt-bindings/soc/renesas,r8a78000-mfis.h | 28 ++
6 files changed, 576 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml
create mode 100644 drivers/soc/renesas/rcar-mfis.c
create mode 100644 include/dt-bindings/soc/renesas,r8a78000-mfis.h
--
2.51.0
^ permalink raw reply
* Re: [PATCH 2/3] staging: iio: adis16203: align MODULE_LICENSE with SPDX identifier
From: Greg KH @ 2026-04-02 11:27 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Sheng Kun Chang, jic23, lars, Michael.Hennerich, dlechner,
nuno.sa, andy, robh, krzk+dt, conor+dt, linux-iio, linux-staging,
devicetree, linux-kernel
In-Reply-To: <ac4rpSyxTg2qPy86@ashevche-desk.local>
On Thu, Apr 02, 2026 at 11:41:09AM +0300, Andy Shevchenko wrote:
> On Wed, Apr 01, 2026 at 04:24:56PM +0000, Sheng Kun Chang wrote:
> > The SPDX license identifier is GPL-2.0+ (GPL v2 or later) but
> > MODULE_LICENSE was set to "GPL v2" which indicates GPL v2 only.
> > Change to "GPL" which means GPL v2 or later, matching the SPDX
> > header.
>
> This description has nothing to do with the macro parameter. GPL is new,
> GPL v2 is just legacy alias.
As Andy says, this is not true at all, please read include/module.h for
the details. Both MODULE_LICENSE() strings mean the exact same thing,
please do not change it unless you are the original author of the code.
thanks,
greg k-h
^ permalink raw reply
* Re: [PATCH v2] ASoC: codecs: wcd937x: Add conditional regulator control for wcd937x
From: Mark Brown @ 2026-04-02 11:23 UTC (permalink / raw)
To: karthik.s
Cc: Srinivas Kandagatla, Liam Girdwood, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
linux-sound, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260402072256.2811085-1-karthik.s@oss.qualcomm.com>
[-- Attachment #1: Type: text/plain, Size: 446 bytes --]
On Thu, Apr 02, 2026 at 12:52:56PM +0530, karthik.s wrote:
> Add has_always_on_supplies for managing regulators. Indicates that the
> codec power supplies are provided by the board as always-on rails and
> are not switchable by the codec or its associated regulators. This implies
> that the codec supply regulators are always enabled by the system and
> must not be requested or enabled by the codec driver.
Same issue, why would we want this?
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH v3 1/3] arm64: dts: qcom: sdm845-shift-axolotl: Enable sdcard
From: David Heidelberg @ 2026-04-02 11:22 UTC (permalink / raw)
To: Vladimir Zapolskiy, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Dylan Van Assche
Cc: linux-arm-msm, Petr Hodina, Casey Connolly, Dmitry Baryshkov,
Alexander Martinz, Konrad Dybcio, devicetree, linux-kernel,
phone-devel
In-Reply-To: <c099bf8f-7a29-4138-85a3-e2669807aca5@linaro.org>
On 02/04/2026 13:16, Vladimir Zapolskiy wrote:
> On 4/2/26 12:54, David Heidelberg via B4 Relay wrote:
>> From: Casey Connolly <casey.connolly@linaro.org>
>>
>> The SHIFT6mq features an sdcard slot, add it.
>>
>> Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Co-developed-by: David Heidelberg <david@ixit.cz>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
>> arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 44 +++++++++++++++++++++++
>> 1 file changed, 44 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/
>> boot/dts/qcom/sdm845-shift-axolotl.dts
>> index 740eb22550724..b05f04a621e5b 100644
>> --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
>> +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
>> @@ -600,6 +600,24 @@ &qupv3_id_1 {
>> status = "okay";
>> };
>> +&sdhc_2 {
>> + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
>
> If card detection is broken and disabled, then likely card detection
> GPIO can be omitted, no?
Could be, but current use, since it's broken, is to minimize power consumption
which we do by setting this GPIO with bias-disable and still documenting it's
presence.
David
>
>> + pinctrl-names = "default";
>> +
>> + vmmc-supply = <&vreg_l21a_2p95>;
>> + vqmmc-supply = <&vreg_l13a_2p95>;
>> +
>> + bus-width = <4>;
>> + /*
>> + * Card detection is broken, but because the battery must be removed
>> + * to insert the card, we use this rather than the broken-cd property
>> + * which would just waste CPU cycles polling.
>> + */
>> + non-removable;
>> +
>> + status = "okay";
>> +};
>> +
>> &slpi_pas {
>> firmware-name = "qcom/sdm845/SHIFT/axolotl/slpi.mbn";
>> @@ -609,6 +627,32 @@ &slpi_pas {
>> &tlmm {
>> gpio-reserved-ranges = <0 4>, <81 4>;
>> + sdc2_default_state: sdc2-default-state {
>> + clk-pins {
>> + pins = "sdc2_clk";
>> + drive-strength = <16>;
>> + bias-disable;
>> + };
>> +
>> + cmd-pins {
>> + pins = "sdc2_cmd";
>> + drive-strength = <10>;
>> + bias-pull-up;
>> + };
>> +
>> + data-pins {
>> + pins = "sdc2_data";
>> + drive-strength = <10>;
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + sdc2_card_det_n: sd-card-det-n-state {
>> + pins = "gpio126";
>> + function = "gpio";
>> + bias-disable;
>> + };
>> +
>> sde_dsi_active: sde-dsi-active-state {
>> pins = "gpio6", "gpio11";
>> function = "gpio";
>>
>
--
David Heidelberg
^ permalink raw reply
* Re: [PATCH v1] ASoC: codecs: wcd937x: Add conditional regulator control for wcd937x
From: Mark Brown @ 2026-04-02 11:22 UTC (permalink / raw)
To: karthik.s
Cc: Srinivas Kandagatla, Liam Girdwood, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
linux-arm-msm, linux-sound, devicetree, linux-kernel
In-Reply-To: <20260402070854.2804291-1-karthik.s@oss.qualcomm.com>
[-- Attachment #1: Type: text/plain, Size: 603 bytes --]
On Thu, Apr 02, 2026 at 12:38:54PM +0530, karthik.s wrote:
> Add has_always_on_supplies for managing regulators. Indicates that
> the codec supply regulators are always enabled by the system and
> must not be requested or enabled by the codec driver.
> + qcom,always-on-supply:
> + type: boolean
> + description: Indicates that the codec supply regulators are always enabled
> + by the system and must not be requested or enabled by the codec
> + driver.
> +
Why would we want that? The regulator core already has perfectly good
support for always on supplies.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH v5 5/9] riscv: dts: spacemit: k1: add SD card controller and pinctrl support
From: Troy Mitchell @ 2026-04-02 11:21 UTC (permalink / raw)
To: Iker Pedrosa, Troy Mitchell
Cc: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Adrian Hunter, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Yixun Lan, Michael Opdenacker,
Javier Martinez Canillas, linux-mmc, devicetree, linux-riscv,
spacemit, linux-kernel, Anand Moon, Trevor Gamblin
In-Reply-To: <CABdCQ=MFcDPnzcYUEkbQyu_0qZt=aDD04p1kyxCMuVt7Av_P1Q@mail.gmail.com>
On Wed Apr 1, 2026 at 4:53 PM CST, Iker Pedrosa wrote:
> El lun, 30 mar 2026 a las 11:08, Troy Mitchell
> (<troy.mitchell@linux.dev>) escribió:
>>
>> On Mon, Mar 30, 2026 at 16:38:06 CST, Iker Pedrosa wrote:
>> > Add SD card controller infrastructure for SpacemiT K1 SoC with complete
>> > pinctrl support for both standard and UHS modes.
>> >
>> > - Add sdhci0 controller definition with clocks, resets and interrupts
>> > - Add mmc1_cfg pinctrl for 3.3V standard SD operation
>> > - Add mmc1_uhs_cfg pinctrl for 1.8V UHS high-speed operation
>> > - Configure appropriate drive strength and power-source properties
>> >
>> > This provides complete SD card infrastructure that K1-based boards can
>> > enable.
>> >
>> > Tested-by: Anand Moon <linux.amoon@gmail.com>
>> > Tested-by: Trevor Gamblin <tgamblin@baylibre.com>
>> > Signed-off-by: Iker Pedrosa <ikerpedrosam@gmail.com>
>> > ---
>> > arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 40 ++++++++++++++++++++++++++++
>> > arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++++
>> > 2 files changed, 53 insertions(+)
>> >
>> > diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
>> > index b13dcb10f4d66022d27307de73a6ea3287e97441..8d82011f1af666fb78c282a2abcc0cb88f962053 100644
>> > --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
>> > +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
>> > @@ -570,4 +570,44 @@ pwm14-1-pins {
>> > drive-strength = <32>;
>> > };
>> > };
>> > +
>> > + mmc1_cfg: mmc1-cfg {
>> > + mmc1-data-cmd-pins {
>> > + pinmux = <K1_PADCONF(104, 0)>, /* mmc1_d3 */
>> > + <K1_PADCONF(105, 0)>, /* mmc1_d2 */
>> > + <K1_PADCONF(106, 0)>, /* mmc1_d1 */
>> > + <K1_PADCONF(107, 0)>, /* mmc1_d0 */
>> > + <K1_PADCONF(108, 0)>; /* mmc1_cmd */
>> > + bias-pull-up = <1>;
>> > + drive-strength = <7>;
>> I'm a bit concerned about this value. Looking at the downstream 6.6 code, 3.3V uses DS4,
>> which equals 13mA. Since 7mA maps to DS0, what's the reasoning for using it here?
^^^^ wrong current
>> Do we have any documentation or measurement to back this up?
>
> Thank you for catching this! You're absolutely right to question these
> drive strength values.
>
> Looking back at my development process, I remember hitting signal
> integrity issues in the early stages of this driver development. As a
> quick solution, I lowered the drive strength values, which seemed to
> resolve the immediate problems, and I moved on without revisiting the
> electrical characteristics.
>
> After your feedback, I investigated this properly by comparing with
> the vendor kernel. It uses:
> - 3.3V mode: PAD_3V_DS4 (19mA)
> - 1.8V UHS mode: PAD_1V8_DS3 (42mA)
>
> My original values were indeed backwards from both electrical theory
> and proven vendor implementation. Testing with the corrected values
> (19mA/42mA) confirms SD card is working.
>
> I'll send v6 with the corrected drive strength values: drive-strength
> = <19> for 3.3V and drive-strength = <42> for 1.8V UHS modes.
Yes, 19mA for 3.3V and 42mA for 1.8V are correct.
I realized I cited an incorrect value in my previous message (the 13mA).
Please CC me when you send v6.
- Troy
^ permalink raw reply
* Re: [PATCH v3 1/3] arm64: dts: qcom: sdm845-shift-axolotl: Enable sdcard
From: Vladimir Zapolskiy @ 2026-04-02 11:16 UTC (permalink / raw)
To: david, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Dylan Van Assche
Cc: linux-arm-msm, Petr Hodina, Casey Connolly, Dmitry Baryshkov,
Alexander Martinz, Konrad Dybcio, devicetree, linux-kernel,
phone-devel
In-Reply-To: <20260402-axolotl-misc-p1-v3-1-8934e9db6831@ixit.cz>
On 4/2/26 12:54, David Heidelberg via B4 Relay wrote:
> From: Casey Connolly <casey.connolly@linaro.org>
>
> The SHIFT6mq features an sdcard slot, add it.
>
> Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Co-developed-by: David Heidelberg <david@ixit.cz>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 44 +++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
> index 740eb22550724..b05f04a621e5b 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
> +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
> @@ -600,6 +600,24 @@ &qupv3_id_1 {
> status = "okay";
> };
>
> +&sdhc_2 {
> + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
If card detection is broken and disabled, then likely card detection
GPIO can be omitted, no?
> + pinctrl-names = "default";
> +
> + vmmc-supply = <&vreg_l21a_2p95>;
> + vqmmc-supply = <&vreg_l13a_2p95>;
> +
> + bus-width = <4>;
> + /*
> + * Card detection is broken, but because the battery must be removed
> + * to insert the card, we use this rather than the broken-cd property
> + * which would just waste CPU cycles polling.
> + */
> + non-removable;
> +
> + status = "okay";
> +};
> +
> &slpi_pas {
> firmware-name = "qcom/sdm845/SHIFT/axolotl/slpi.mbn";
>
> @@ -609,6 +627,32 @@ &slpi_pas {
> &tlmm {
> gpio-reserved-ranges = <0 4>, <81 4>;
>
> + sdc2_default_state: sdc2-default-state {
> + clk-pins {
> + pins = "sdc2_clk";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc2_cmd";
> + drive-strength = <10>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc2_data";
> + drive-strength = <10>;
> + bias-pull-up;
> + };
> + };
> +
> + sdc2_card_det_n: sd-card-det-n-state {
> + pins = "gpio126";
> + function = "gpio";
> + bias-disable;
> + };
> +
> sde_dsi_active: sde-dsi-active-state {
> pins = "gpio6", "gpio11";
> function = "gpio";
>
--
Best wishes,
Vladimir
^ permalink raw reply
* [PATCH v1 3/5] dt-bindings: interrupt-controller: Add StarFive JHB100 plic
From: Changhuang Liang @ 2026-04-02 8:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Samuel Holland, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Daniel Lezcano, Emil Renner Berthing
Cc: Yixun Lan, Joel Stanley, Drew Fustini, Darshan Prajapati,
Guodong Xu, Michal Simek, Junhui Liu, Heinrich Schuchardt,
E Shattow, Icenowy Zheng, Anup Patel, linux-kernel, devicetree,
linux-riscv, Ji Sheng Teoh, Hal Feng, Ley Foon Tan,
Changhuang Liang, Michael Zhu
In-Reply-To: <20260402084019.440708-1-changhuang.liang@starfivetech.com>
From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Add compatible string for StarFive JHB100 plic.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index e0267223887e..49d63100bf87 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,7 @@ properties:
- spacemit,k1-plic
- starfive,jh7100-plic
- starfive,jh7110-plic
+ - starfive,jhb100-plic
- tenstorrent,blackhole-plic
- const: sifive,plic-1.0.0
- items:
--
2.25.1
^ permalink raw reply related
* [PATCH v1 18/22] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add driver for the StarFive JHB100 Peripheral-2 clock controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-per2.c | 232 ++++++++++++++++++
3 files changed, 241 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per2.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 72cf314c6cfc..01d6d325dcd0 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -89,6 +89,14 @@ config CLK_STARFIVE_JHB100_PER1
Say yes here to support the peripheral-1 clock controller
on the StarFive JHB100 SoC.
+config CLK_STARFIVE_JHB100_PER2
+ bool "StarFive JHB100 peripheral-2 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS0
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the peripheral-2 clock controller
+ on the StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 51511086a727..044e1942ccfa 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per2.c b/drivers/clk/starfive/clk-starfive-jhb100-per2.c
new file mode 100644
index 000000000000..42b9dbd11618
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-per2.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 Peripheral-2 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_PER2CLK_NUM_CLKS (JHB100_PER2CLK_MAIN_ICG_EN_GMAC3 + 1)
+
+/* external clocks */
+#define JHB100_PER2CLK_600 (JHB100_PER2CLK_NUM_CLKS + 0)
+#define JHB100_PER2CLK_400 (JHB100_PER2CLK_NUM_CLKS + 1)
+#define JHB100_PER2CLK_125 (JHB100_PER2CLK_NUM_CLKS + 2)
+#define JHB100_PER2CLK_GMAC2_RGMII_RX (JHB100_PER2CLK_NUM_CLKS + 3)
+#define JHB100_PER2CLK_GMAC2_RMII_REF (JHB100_PER2CLK_NUM_CLKS + 4)
+#define JHB100_PER2CLK_OSC (JHB100_PER2CLK_NUM_CLKS + 5)
+#define JHB100_PER2CLK_GMAC3_SGMII_TX (JHB100_PER2CLK_NUM_CLKS + 6)
+#define JHB100_PER2CLK_GMAC3_SGMII_RX (JHB100_PER2CLK_NUM_CLKS + 7)
+
+static const struct starfive_clk_data jhb100_per2crg_clk_data[] = {
+ STARFIVE__DIV(JHB100_PER2CLK_300, "per2_300", 2,
+ JHB100_PER2CLK_600),
+ STARFIVE__DIV(JHB100_PER2CLK_100, "per2_100", 4,
+ JHB100_PER2CLK_400),
+ STARFIVE__DIV(JHB100_PER2CLK_50, "per2_50", 2,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC2_RMII_50, "gmac2_rmii_50", 2,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN0_CORE_DIV, "can0_core_div", 20,
+ JHB100_PER2CLK_400),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN1_CORE_DIV, "can1_core_div", 20,
+ JHB100_PER2CLK_400),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN0_TIMER, "can0_timer", 100,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN1_TIMER, "can1_timer", 100,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_RTC_CORE_DIV, "rtc_core_div", 763,
+ JHB100_PER2CLK_OSC),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_RMII_MUX_DLY, "gmac2_rmii_mux_dly", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_REF,
+ JHB100_PER2CLK_GMAC2_RMII_50),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC2_RMII_DIV, "gmac2_rmii_div", 20,
+ JHB100_PER2CLK_GMAC2_RMII_MUX_DLY),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_RGMII_125_MUX, "gmac2_rgmii_125_mux", 0, 2,
+ JHB100_PER2CLK_GMAC2_RGMII_RX,
+ JHB100_PER2CLK_125),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC2_RGMII_DIV, "gmac2_rgmii_div", 50,
+ JHB100_PER2CLK_125),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_TX_MUX, "gmac2_tx_mux", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_DIV,
+ JHB100_PER2CLK_GMAC2_RGMII_DIV),
+ STARFIVE__INV(JHB100_PER2CLK_GMAC2_TX_180_BUF, "gmac2_tx_180_buf",
+ JHB100_PER2CLK_GMAC2_TX_MUX),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_RX_MUX_DLY, "gmac2_rx_mux_dly", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_DIV,
+ JHB100_PER2CLK_GMAC2_RGMII_125_MUX),
+ STARFIVE__INV(JHB100_PER2CLK_GMAC2_RX_180_BUF, "gmac2_rx_180_buf",
+ JHB100_PER2CLK_GMAC2_RX_MUX_DLY),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY, "gmac2_txck_mux_dly", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_50,
+ JHB100_PER2CLK_GMAC2_TX_MUX),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC3_TX_125_MUX, "gmac3_tx_125_mux", 0, 2,
+ JHB100_PER2CLK_GMAC3_SGMII_TX,
+ JHB100_PER2CLK_125),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC3_RX_125_MUX, "gmac3_rx_125_mux", 0, 2,
+ JHB100_PER2CLK_GMAC3_SGMII_RX,
+ JHB100_PER2CLK_125),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC3_TX_DIV, "gmac3_tx_div", 50,
+ JHB100_PER2CLK_GMAC3_TX_125_MUX),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC3_RX_DIV, "gmac3_rx_div", 50,
+ JHB100_PER2CLK_GMAC3_RX_125_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_SENSORS_PERIPH2, "sensors_periph2", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_FAN_TACH_PCLK, "fan_tach_pclk", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_I, "ether0_rmiiandrgmii_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_TX_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_I, "ether0_rmiiandrgmii_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RX_MUX_DLY),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_180_I, "ether0_rmiiandrgmii_tx_180_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_TX_180_BUF),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_180_I, "ether0_rmiiandrgmii_rx_180_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RX_180_BUF),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_PTP_REF_I, "ether0_rmiiandrgmii_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_50),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RMII_I, "ether0_rmiiandrgmii_rmii_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RMII_MUX_DLY),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_CSR_I, "ether0_rmiiandrgmii_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_ACLK_I, "ether0_rmiiandrgmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_300),
+ STARFIVE_GATE(JHB100_PER2CLK_RMIIANDRGMII_IOMUX_GMAC2_TXCK, "rmiiandrgmii_iomux_gmac2_txck",
+ CLK_IS_CRITICAL, JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_TX_I, "ether1_sgmii_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_TX_DIV),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_RX_I, "ether1_sgmii_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_RX_DIV),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_TX_125_I, "ether1_sgmii_tx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_TX_125_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_RX_125_I, "ether1_sgmii_rx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_RX_125_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_PTP_REF_I, "ether1_sgmii_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_50),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_CSR_I, "ether1_sgmii_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_ACLK_I, "ether1_sgmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_300),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_PHY_PCLK_I, "ether1_sgmii_phy_pclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_REF_25_I, "ether1_sgmii_ref_25_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_OSC),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_CAN0, "main_icg_en_can0", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_CAN1, "main_icg_en_can1", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_DMAC_8CH, "main_icg_en_dmac_8ch", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_RTC_SCAN, "main_icg_en_rtc_scan", CLK_IS_CRITICAL,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_ADC0, "main_icg_en_adc0", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_ADC1, "main_icg_en_adc1", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_GMAC2, "main_icg_en_gmac2", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_GMAC3, "main_icg_en_gmac3", 0,
+ JHB100_PER2CLK_100),
+};
+
+static int jhb100_per2crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_PER2CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_PER2CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_PER2CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_per2crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_per2crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_per2crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_per2crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_PER2CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_PER2CLK_600)
+ parents[i].fw_name = "per2_600";
+ else if (pidx == JHB100_PER2CLK_400)
+ parents[i].fw_name = "per2_400";
+ else if (pidx == JHB100_PER2CLK_125)
+ parents[i].fw_name = "per2_125";
+ else if (pidx == JHB100_PER2CLK_GMAC2_RGMII_RX)
+ parents[i].fw_name = "per2_gmac2_rgmii_rx";
+ else if (pidx == JHB100_PER2CLK_GMAC2_RMII_REF)
+ parents[i].fw_name = "per2_gmac2_rmii_ref";
+ else if (pidx == JHB100_PER2CLK_GMAC3_SGMII_TX)
+ parents[i].fw_name = "per2_gmac3_sgmii_tx";
+ else if (pidx == JHB100_PER2CLK_GMAC3_SGMII_RX)
+ parents[i].fw_name = "per2_gmac3_sgmii_rx";
+ else if (pidx == JHB100_PER2CLK_OSC)
+ parents[i].fw_name = "osc";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-per2", 0);
+}
+
+static const struct of_device_id jhb100_per2crg_match[] = {
+ { .compatible = "starfive,jhb100-per2crg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per2crg_match);
+
+static struct platform_driver jhb100_per2crg_driver = {
+ .probe = jhb100_per2crg_probe,
+ .driver = {
+ .name = "clk-starfive-jhb100-per2",
+ .of_match_table = jhb100_per2crg_match,
+ },
+};
+module_platform_driver(jhb100_per2crg_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 Peripheral-2 Clock Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related
* [PATCH v1 16/22] clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add driver for the StarFive JHB100 Peripheral-1 clock controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-per1.c | 204 ++++++++++++++++++
3 files changed, 213 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per1.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index adf97444f460..72cf314c6cfc 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -81,6 +81,14 @@ config CLK_STARFIVE_JHB100_PER0
Say yes here to support the peripheral-0 clock controller
on the StarFive JHB100 SoC.
+config CLK_STARFIVE_JHB100_PER1
+ bool "StarFive JHB100 peripheral-1 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS2
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the peripheral-1 clock controller
+ on the StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 2f605d0fd6da..51511086a727 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per1.c b/drivers/clk/starfive/clk-starfive-jhb100-per1.c
new file mode 100644
index 000000000000..c5c1cff5d9a8
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-per1.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 Peripheral-1 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_PER1CLK_NUM_CLKS (JHB100_PER1CLK_MAIN_ICG_EN_UFS + 1)
+
+/* external clocks */
+#define JHB100_PER1CLK_143 (JHB100_PER1CLK_NUM_CLKS + 0)
+#define JHB100_PER1CLK_200 (JHB100_PER1CLK_NUM_CLKS + 1)
+#define JHB100_PER1CLK_600 (JHB100_PER1CLK_NUM_CLKS + 2)
+#define JHB100_PER1CLK_800 (JHB100_PER1CLK_NUM_CLKS + 3)
+#define JHB100_PER1CLK_PLL7 (JHB100_PER1CLK_NUM_CLKS + 4)
+
+static const struct starfive_clk_data jhb100_per1crg_clk_data[] = {
+ STARFIVE__DIV(JHB100_PER1CLK_100, "per1_100", 8, JHB100_PER1CLK_600),
+ STARFIVE__DIV(JHB100_PER1CLK_1, "per1_1", 100, JHB100_PER1CLK_100),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN0, "200_divn0", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN1, "200_divn1", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN2, "200_divn2", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN3, "200_divn3", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_CCLK_DIV, "200_cclk_div", 2046,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO0_PCLK, "sgpio0_pclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO0_DCLK, "sgpio0_dclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO1_PCLK, "sgpio1_pclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO1_DCLK, "sgpio1_dclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_EMMC0_BCLK, "emmc0_bclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_EMMC0_CCLK, "emmc0_cclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC1_1CH_CORE, "dmac1_1ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC1_1CH_ACLK, "dmac1_1ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC2_1CH_CORE, "dmac2_1ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC2_1CH_ACLK, "dmac2_1ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC3_1CH_CORE, "dmac3_1ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC3_1CH_ACLK, "dmac3_1ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC0_2CH_CORE, "dmac0_2ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC0_2CH_ACLK, "dmac0_2ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_REF, "ufs_ref", 75,
+ JHB100_PER1CLK_PLL7),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_300, "ufs_300", 2,
+ JHB100_PER1CLK_600),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_150, "ufs_150", 12,
+ JHB100_PER1CLK_600),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_400, "ufs_400", 2,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_75, "ufs_75", 2,
+ JHB100_PER1CLK_UFS_150),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_37_5, "ufs_37_5", 2,
+ JHB100_PER1CLK_UFS_75),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_7_5, "ufs_7_5", 10,
+ JHB100_PER1CLK_UFS_75),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_1_875, "ufs_1_875", 4,
+ JHB100_PER1CLK_UFS_7_5),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_7_143, "ufs_7_143", 20,
+ JHB100_PER1CLK_143),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_3_5715, "ufs_3_5715", 2,
+ JHB100_PER1CLK_UFS_7_143),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC0, "main_icg_en_sfc0", CLK_IS_CRITICAL,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC1, "main_icg_en_sfc1", CLK_IS_CRITICAL,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC2, "main_icg_en_sfc2", CLK_IS_CRITICAL,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SPI0, "main_icg_en_spi0", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_EMMC0, "main_icg_en_emmc0", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SGPIO0, "main_icg_en_sgpio0", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SGPIO1, "main_icg_en_sgpio1", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SENSORS_PERIPH1, "main_icg_en_sensors_periph1", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC0, "main_icg_en_dmac_sfc0",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC1, "main_icg_en_dmac_sfc1",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC2, "main_icg_en_dmac_sfc2",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SPI0, "main_icg_en_dmac_spi0",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_RAS, "main_icg_en_ras", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_UFS, "main_icg_en_ufs", 0,
+ JHB100_PER1CLK_100),
+};
+
+static int jhb100_per1crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_PER1CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_PER1CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_PER1CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_per1crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_per1crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_per1crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_per1crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_PER1CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_PER1CLK_600)
+ parents[i].fw_name = "per1_600";
+ else if (pidx == JHB100_PER1CLK_200)
+ parents[i].fw_name = "per1_200";
+ else if (pidx == JHB100_PER1CLK_800)
+ parents[i].fw_name = "per1_800";
+ else if (pidx == JHB100_PER1CLK_143)
+ parents[i].fw_name = "per1_143";
+ else if (pidx == JHB100_PER1CLK_PLL7)
+ parents[i].fw_name = "pll7";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-per1", 0);
+}
+
+static const struct of_device_id jhb100_per1crg_match[] = {
+ { .compatible = "starfive,jhb100-per1crg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per1crg_match);
+
+static struct platform_driver jhb100_per1crg_driver = {
+ .probe = jhb100_per1crg_probe,
+ .driver = {
+ .name = "clk-starfive-jhb100-per1",
+ .of_match_table = jhb100_per1crg_match,
+ },
+};
+module_platform_driver(jhb100_per1crg_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 Peripheral-1 Clock Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related
* [PATCH v1 20/22] clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add driver for the StarFive JHB100 Peripheral-3 clock controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-per3.c | 189 ++++++++++++++++++
3 files changed, 198 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per3.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 01d6d325dcd0..c612f1ede7d7 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -97,6 +97,14 @@ config CLK_STARFIVE_JHB100_PER2
Say yes here to support the peripheral-2 clock controller
on the StarFive JHB100 SoC.
+config CLK_STARFIVE_JHB100_PER3
+ bool "StarFive JHB100 peripheral-3 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS1
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the peripheral-3 clock controller
+ on the StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 044e1942ccfa..f00690f0cdad 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PER3) += clk-starfive-jhb100-per3.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per3.c b/drivers/clk/starfive/clk-starfive-jhb100-per3.c
new file mode 100644
index 000000000000..5533bb481f6d
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-per3.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 Peripheral-3 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_PER3CLK_NUM_CLKS (JHB100_PER3CLK_MAIN_ICG_EN_GMAC1 + 1)
+
+/* external clocks */
+#define JHB100_PER3CLK_100 (JHB100_PER3CLK_NUM_CLKS + 0)
+#define JHB100_PER3CLK_125 (JHB100_PER3CLK_NUM_CLKS + 1)
+#define JHB100_PER3CLK_600 (JHB100_PER3CLK_NUM_CLKS + 2)
+#define JHB100_PER3CLK_OSC (JHB100_PER3CLK_NUM_CLKS + 3)
+#define JHB100_PER3CLK_GMAC0_RMII_RCLKI (JHB100_PER3CLK_NUM_CLKS + 4)
+#define JHB100_PER3CLK_GMAC1_SGMII_TX (JHB100_PER3CLK_NUM_CLKS + 5)
+#define JHB100_PER3CLK_GMAC1_SGMII_RX (JHB100_PER3CLK_NUM_CLKS + 6)
+
+static const struct starfive_clk_data jhb100_per3crg_clk_data[] = {
+ STARFIVE__DIV(JHB100_PER3CLK_300, "per3_300", 256,
+ JHB100_PER3CLK_600),
+ STARFIVE__DIV(JHB100_PER3CLK_200, "per3_200", 256,
+ JHB100_PER3CLK_600),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC1_PTP_REF, "gmac1_ptp_ref", 2,
+ JHB100_PER3CLK_100),
+ STARFIVE__MUX(JHB100_PER3CLK_GMAC1_TX_125_MUX, "gmac1_tx_125_mux", 0, 2,
+ JHB100_PER3CLK_GMAC1_SGMII_TX,
+ JHB100_PER3CLK_125),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC1_TX, "gmac1_tx", 50,
+ JHB100_PER3CLK_GMAC1_TX_125_MUX),
+ STARFIVE__MUX(JHB100_PER3CLK_GMAC1_RX_125_MUX, "gmac1_rx_125_mux", 0, 2,
+ JHB100_PER3CLK_GMAC1_SGMII_RX,
+ JHB100_PER3CLK_125),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC1_RX, "gmac1_rx", 50,
+ JHB100_PER3CLK_GMAC1_RX_125_MUX),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC0_PTP_REF, "gmac0_ptp_ref", 2,
+ JHB100_PER3CLK_100),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC0_RMII_PLL, "gmac0_rmii_pll", 2,
+ JHB100_PER3CLK_100),
+ STARFIVE__MUX(JHB100_PER3CLK_GMAC0_RMII_MUX, "gmac0_rmii_mux", 0, 2,
+ JHB100_PER3CLK_GMAC0_RMII_PLL,
+ JHB100_PER3CLK_GMAC0_RMII_RCLKI),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2, "gmac0_rmii_mux_div2", 20,
+ JHB100_PER3CLK_GMAC0_RMII_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_TX_I, "ether0_rmii_clk_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RX_I, "ether0_rmii_clk_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_PTP_REF_I, "ether0_rmii_clk_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_PTP_REF),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RMII_I, "ether0_rmii_clk_rmii_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_CSR_I, "ether0_rmii_clk_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_ACLK_I, "ether0_rmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_300),
+ STARFIVE_GATE(JHB100_PER3CLK_GMAC0_RMII_RCLKO, "gmac0_rmii_rclko",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_PLL),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_I, "ether0_sgmii_clk_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_I, "ether0_sgmii_clk_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_125_I, "ether0_sgmii_clk_tx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX_125_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_125_I, "ether0_sgmii_clk_rx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX_125_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_PTP_REF_I, "ether0_sgmii_clk_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_PTP_REF),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_REF_25_I, "ether0_sgmii_clk_ref_25_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_OSC),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_CSR_I, "ether0_sgmii_clk_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_ACLK_I, "ether0_sgmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_300),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_PHY_PCLK_I, "ether0_sgmii_phy_pclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_SENSORS_PERIPH3, "main_icg_en_sensors_periph3", 0,
+ JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI0, "main_icg_en_peci0", 0,
+ JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI1, "main_icg_en_peci1", 0,
+ JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC0, "main_icg_en_gmac0",
+ CLK_IS_CRITICAL, JHB100_PER3CLK_100),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC1, "main_icg_en_gmac1",
+ CLK_IS_CRITICAL, JHB100_PER3CLK_100),
+};
+
+static int jhb100_per3crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_PER3CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_PER3CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_PER3CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_per3crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_per3crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_per3crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_per3crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_PER3CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_PER3CLK_100)
+ parents[i].fw_name = "per3_100";
+ else if (pidx == JHB100_PER3CLK_125)
+ parents[i].fw_name = "per3_125";
+ else if (pidx == JHB100_PER3CLK_600)
+ parents[i].fw_name = "per3_600";
+ else if (pidx == JHB100_PER3CLK_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JHB100_PER3CLK_GMAC0_RMII_RCLKI)
+ parents[i].fw_name = "per3_gmac0_rmii_rclki";
+ else if (pidx == JHB100_PER3CLK_GMAC1_SGMII_TX)
+ parents[i].fw_name = "per3_gmac1_sgmii_tx";
+ else if (pidx == JHB100_PER3CLK_GMAC1_SGMII_RX)
+ parents[i].fw_name = "per3_gmac1_sgmii_rx";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-per3", 0);
+}
+
+static const struct of_device_id jhb100_per3crg_match[] = {
+ { .compatible = "starfive,jhb100-per3crg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per3crg_match);
+
+static struct platform_driver jhb100_per3crg_driver = {
+ .probe = jhb100_per3crg_probe,
+ .driver = {
+ .name = "clk-starfive-jhb100-per3",
+ .of_match_table = jhb100_per3crg_match,
+ },
+};
+module_platform_driver(jhb100_per3crg_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 Peripheral-3 Clock Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related
* [PATCH v1 21/22] reset: starfive: Add StarFive JHB100 reset driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add auxiliary reset driver to support StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 6 +
drivers/reset/starfive/Kconfig | 9 ++
drivers/reset/starfive/Makefile | 1 +
.../reset/starfive/reset-starfive-jhb100.c | 121 ++++++++++++++++++
4 files changed, 137 insertions(+)
create mode 100644 drivers/reset/starfive/reset-starfive-jhb100.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 3af9d79b7daf..4ddf8ba2e60d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25319,6 +25319,12 @@ L: linux-riscv@lists.infradead.org
S: Maintained
F: arch/riscv/boot/dts/starfive/jhb100*
+STARFIVE JHB100 RESET CONTROLLER DRIVERS
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: drivers/reset/starfive/reset-starfive-jhb1*
+F: include/dt-bindings/reset/starfive,jhb1*.h
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index 29fbcf1a7d83..6f9a0f24f9b9 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -19,3 +19,12 @@ config RESET_STARFIVE_JH7110
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7110 SoC.
+
+config RESET_STARFIVE_JHB100
+ bool "StarFive JHB100 Reset Driver"
+ depends on CLK_STARFIVE_JHB100_SYS0
+ select AUXILIARY_BUS
+ select RESET_STARFIVE_COMMON
+ default ARCH_STARFIVE
+ help
+ This enables the reset controller driver for the StarFive JHB100 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index 582e4c160bd4..217002302a9f 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_RESET_STARFIVE_COMMON) += reset-starfive-common.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
+obj-$(CONFIG_RESET_STARFIVE_JHB100) += reset-starfive-jhb100.o
diff --git a/drivers/reset/starfive/reset-starfive-jhb100.c b/drivers/reset/starfive/reset-starfive-jhb100.c
new file mode 100644
index 000000000000..ab5e0f2a684f
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jhb100.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Reset driver for the StarFive JHB110 SoC
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/reset/starfive,jhb100-crg.h>
+#include <linux/auxiliary_bus.h>
+#include <soc/starfive/reset-starfive-common.h>
+
+#include "reset-starfive-common.h"
+
+#define NUM_RESETS(x) ((x) + 1)
+
+struct jhb100_reset_info {
+ unsigned int nr_resets;
+ unsigned int assert_offset;
+ unsigned int status_offset;
+};
+
+static const struct jhb100_reset_info jhb100_sys0_info = {
+ .nr_resets = NUM_RESETS(JHB100_SYS0RST_BMCUSB_RSTN_CRG),
+ .assert_offset = 0x12c,
+ .status_offset = 0x130,
+};
+
+static const struct jhb100_reset_info jhb100_sys1_info = {
+ .nr_resets = NUM_RESETS(JHB100_SYS1RST_BMCPERIPH3_RSTN_BUS),
+ .assert_offset = 0x54,
+ .status_offset = 0x58,
+};
+
+static const struct jhb100_reset_info jhb100_sys2_info = {
+ .nr_resets = NUM_RESETS(JHB100_SYS2RST_GPU1_HOST_PCIE_RST_N),
+ .assert_offset = 0x88,
+ .status_offset = 0x8c,
+};
+
+static const struct jhb100_reset_info jhb100_periph0_info = {
+ .nr_resets = NUM_RESETS(JHB100_PER0RST_UART_MUX_REG_WRAP),
+ .assert_offset = 0x554,
+ .status_offset = 0x560,
+};
+
+static const struct jhb100_reset_info jhb100_periph1_info = {
+ .nr_resets = NUM_RESETS(JHB100_PER1RST_MAIN_RSTN_PERIPH1_RAS),
+ .assert_offset = 0x134,
+ .status_offset = 0x138,
+};
+
+static const struct jhb100_reset_info jhb100_periph2_info = {
+ .nr_resets = NUM_RESETS(JHB100_PER2RST_MAIN_RSTN_PERIPH2_SENSORS),
+ .assert_offset = 0x11c,
+ .status_offset = 0x120,
+};
+
+static const struct jhb100_reset_info jhb100_periph3_info = {
+ .nr_resets = NUM_RESETS(JHB100_PER3RST_IOMUX_PRESETN),
+ .assert_offset = 0x98,
+ .status_offset = 0x9c,
+};
+
+static int jhb100_reset_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct jhb100_reset_info *info = (struct jhb100_reset_info *)(id->driver_data);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
+ void __iomem *base = rdev->base;
+
+ if (!info || !base)
+ return -ENODEV;
+
+ return reset_starfive_register(&adev->dev, adev->dev.parent->of_node,
+ base + info->assert_offset,
+ base + info->status_offset,
+ NULL, info->nr_resets, NULL);
+}
+
+static const struct auxiliary_device_id jhb100_reset_ids[] = {
+ {
+ .name = "clk_starfive_jhb100_sys0.r-sys0",
+ .driver_data = (kernel_ulong_t)&jhb100_sys0_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-sys1",
+ .driver_data = (kernel_ulong_t)&jhb100_sys1_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-sys2",
+ .driver_data = (kernel_ulong_t)&jhb100_sys2_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-per0",
+ .driver_data = (kernel_ulong_t)&jhb100_periph0_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-per1",
+ .driver_data = (kernel_ulong_t)&jhb100_periph1_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-per2",
+ .driver_data = (kernel_ulong_t)&jhb100_periph2_info,
+ },
+ {
+ .name = "clk_starfive_jhb100_sys0.r-per3",
+ .driver_data = (kernel_ulong_t)&jhb100_periph3_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(auxiliary, jhb100_reset_ids);
+
+static struct auxiliary_driver jhb100_reset_driver = {
+ .probe = jhb100_reset_probe,
+ .id_table = jhb100_reset_ids,
+};
+module_auxiliary_driver(jhb100_reset_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 reset driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related
* [PATCH v1 06/22] clk: starfive: Add JHB100 System-0 clock generator driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add support for JHB100 System-0 clock generator (SYS0CRG).
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 7 +
drivers/clk/starfive/Kconfig | 11 +
drivers/clk/starfive/Makefile | 2 +
.../clk/starfive/clk-starfive-jhb100-sys0.c | 253 ++++++++++++++++++
drivers/clk/starfive/clk-starfive-jhb100.h | 11 +
5 files changed, 284 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100.h
diff --git a/MAINTAINERS b/MAINTAINERS
index b1892a480c31..3af9d79b7daf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25306,6 +25306,13 @@ S: Supported
F: Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
F: drivers/irqchip/irq-starfive-jh8100-intc.c
+STARFIVE JHB100 CLOCK DRIVERS
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: Documentation/devicetree/bindings/clock/starfive,jhb1*.yaml
+F: drivers/clk/starfive/clk-starfive-jhb1*
+F: include/dt-bindings/clock/starfive,jhb1*.h
+
STARFIVE JHB100 DEVICETREES
M: Changhuang Liang <changhuang.liang@starfivetech.com>
L: linux-riscv@lists.infradead.org
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index ff8eace36e64..7926e02ccd7d 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -72,3 +72,14 @@ config CLK_STARFIVE_JH7110_VOUT
help
Say yes here to support the Video-Output clock controller
on the StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JHB100_SYS0
+ bool "StarFive JHB100 system-0 clock support"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select AUXILIARY_BUS
+ select CLK_STARFIVE_COMMON
+ select RESET_STARFIVE_JHB100 if RESET_CONTROLLER
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the system-0 clock controller on the
+ StarFive JHB100 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 012f7ee83f8e..2c5e66d1d44e 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -10,3 +10,5 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
+
+obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys0.c b/drivers/clk/starfive/clk-starfive-jhb100-sys0.c
new file mode 100644
index 000000000000..00299b161e2b
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-sys0.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 System-0 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/auxiliary_bus.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <soc/starfive/reset-starfive-common.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_SYS0CLK_NUM_CLKS (JHB100_SYS0CLK_GPU1_600 + 1)
+
+/* external clocks */
+#define JHB100_SYS0CLK_OSC (JHB100_SYS0CLK_NUM_CLKS + 0)
+#define JHB100_SYS0CLK_PLL0 (JHB100_SYS0CLK_NUM_CLKS + 1)
+#define JHB100_SYS0CLK_PLL1 (JHB100_SYS0CLK_NUM_CLKS + 2)
+#define JHB100_SYS0CLK_PLL2 (JHB100_SYS0CLK_NUM_CLKS + 3)
+
+static const struct starfive_clk_data jhb100_sys0crg_clk_data[] __initconst = {
+ /* bmcpcierp */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPCIERP_600, "bmcpcierp_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPCIERP_100, "bmcpcierp_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_PCIE_REF_CML, "pcie_ref_cml", 24,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_DATA_INIT, "bmcpcierp_ncnoc_data_init",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_600),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG_INIT, "bmcpcierp_ncnoc_cfg_init",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_100),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_TARG, "bmcpcierp_ncnoc_targ",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_600),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_PCU, "bmcpcierp_pcu",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_OSC),
+ /* hostss0 */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS0_100, "hostss0_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS0_600, "hostss0_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS0_PHY_SCAN_400, "hostss0_phy_scan_400", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_GPIO_ESPI0_66, "gpio_espi0_66", 14,
+ JHB100_SYS0CLK_PLL2),
+ /* bmcusb */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCUSB_600, "bmcusb_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCUSB_200, "bmcusb_200", 6,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCUSB_SCANCLK, "bmcusb_scanclk", 5,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCUSB_480M_SCANCLK, "bmcusb_480m_scanclk",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCUSB_SCANCLK),
+ /* vce */
+ STARFIVE__DIV(JHB100_SYS0CLK_VCE_600, "vce_600", 10,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_VCE_100, "vce_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ /* bmcperiph2 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_600, "bmcper2_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_100, "bmcper2_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_400, "bmcper2_400", 8,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_125, "bmcper2_125", 10,
+ JHB100_SYS0CLK_PLL1),
+ /* hostss1 */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS1_600, "hostss1_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400, "hostss1_phy_scan_400", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE_GATE(JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400_ICG_BUF,
+ "hostss1_phy_scan_400_icg_buf", CLK_IS_CRITICAL,
+ JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400),
+ /* npu */
+ STARFIVE__DIV(JHB100_SYS0CLK_NPU_600, "npu_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* vout */
+ STARFIVE__DIV(JHB100_SYS0CLK_VOUT_600, "vout_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_VOUT_AUX, "vout_aux", 150,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph3 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER3_600, "bmcper3_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* hostusb */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTUSB_600, "hostusb_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* hostusbcmn */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTUSBCMN_480, "hostusbcmn_480", 5,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph1 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER1_600, "bmcper1_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER1_800, "bmcper1_800", 4,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph0 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER0_600, "bmcper0_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER0_400, "bmcper0_400", 8,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER0_800, "bmcper0_800", 8,
+ JHB100_SYS0CLK_PLL0),
+ /* gpu0 */
+ STARFIVE__DIV(JHB100_SYS0CLK_GPU0_600, "gpu0_600", 10,
+ JHB100_SYS0CLK_PLL0),
+ /* gpu1 */
+ STARFIVE__DIV(JHB100_SYS0CLK_GPU1_600, "gpu1_600", 10,
+ JHB100_SYS0CLK_PLL0),
+};
+
+static void jhb100_reset_unregister_adev(void *_adev)
+{
+ struct auxiliary_device *adev = _adev;
+
+ auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
+}
+
+static void jhb100_reset_adev_release(struct device *dev)
+{
+ struct auxiliary_device *adev = to_auxiliary_dev(dev);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
+
+ kfree(rdev);
+}
+
+int jhb100_reset_controller_register(struct starfive_clk_priv *priv,
+ const char *adev_name,
+ u32 adev_id)
+{
+ struct starfive_reset_adev *rdev;
+ struct auxiliary_device *adev;
+ int ret;
+
+ rdev = kzalloc_obj(*rdev);
+ if (!rdev)
+ return -ENOMEM;
+
+ rdev->base = priv->base;
+
+ adev = &rdev->adev;
+ adev->name = adev_name;
+ adev->dev.parent = priv->dev;
+ adev->dev.release = jhb100_reset_adev_release;
+ adev->id = adev_id;
+
+ ret = auxiliary_device_init(adev);
+ if (ret)
+ return ret;
+
+ ret = auxiliary_device_add(adev);
+ if (ret) {
+ auxiliary_device_uninit(adev);
+ return ret;
+ }
+
+ return devm_add_action_or_reset(priv->dev,
+ jhb100_reset_unregister_adev, adev);
+}
+EXPORT_SYMBOL_GPL(jhb100_reset_controller_register);
+
+static int __init jhb100_sys0crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_SYS0CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_SYS0CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_SYS0CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_sys0crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_sys0crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_sys0crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_sys0crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_SYS0CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_SYS0CLK_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JHB100_SYS0CLK_PLL0)
+ parents[i].fw_name = "pll0";
+ else if (pidx == JHB100_SYS0CLK_PLL1)
+ parents[i].fw_name = "pll1";
+ else
+ parents[i].fw_name = "pll2";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-sys0", 0);
+}
+
+static const struct of_device_id jhb100_sys0crg_match[] = {
+ { .compatible = "starfive,jhb100-sys0crg" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jhb100_sys0crg_driver = {
+ .driver = {
+ .name = "clk-starfive-jhb100-sys0",
+ .of_match_table = jhb100_sys0crg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jhb100_sys0crg_driver, jhb100_sys0crg_probe);
diff --git a/drivers/clk/starfive/clk-starfive-jhb100.h b/drivers/clk/starfive/clk-starfive-jhb100.h
new file mode 100644
index 000000000000..6c5cb3e9c610
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CLK_STARFIVE_JHB100_H
+#define __CLK_STARFIVE_JHB100_H
+
+#include "clk-starfive-common.h"
+
+int jhb100_reset_controller_register(struct starfive_clk_priv *priv,
+ const char *adev_name,
+ u32 adev_id);
+
+#endif
--
2.25.1
^ permalink raw reply related
* [PATCH v1 15/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add bindings for the Peripheral-1 clock and reset generator (PER1CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clock/starfive,jhb100-per1crg.yaml | 70 +++++++++++++++++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 60 ++++++++++++++++
.../dt-bindings/reset/starfive,jhb100-crg.h | 20 ++++++
3 files changed, 150 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml
new file mode 100644
index 000000000000..517c6dd2b19f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jhb100-per1crg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-1 Clock and Reset Generator
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jhb100-per1crg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PLL7
+ - description: Peripheral-1 600MHz
+ - description: Peripheral-1 800MHz
+ - description: Peripheral-1 200MHz
+ - description: Peripheral-1 143MHz
+
+ clock-names:
+ items:
+ - const: pll7
+ - const: per1_600
+ - const: per1_800
+ - const: per1_200
+ - const: per1_143
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jhb100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@11b40000 {
+ compatible = "starfive,jhb100-per1crg";
+ reg = <0x11b40000 0x1000>;
+ clocks = <&pll7>,
+ <&sys0crg 68>,
+ <&sys0crg 69>,
+ <&sys2crg 19>,
+ <&sys2crg 22>;
+ clock-names = "pll7", "per1_600",
+ "per1_800", "per1_200",
+ "per1_143";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 104f302b7103..95345d104585 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -387,4 +387,64 @@
#define JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_DMAC 339
#define JHB100_PER0CLK_MAIN_ICG_EN_TRNG 340
+/* PER1CRG clocks */
+#define JHB100_PER1CLK_100 0
+#define JHB100_PER1CLK_1 1
+#define JHB100_PER1CLK_200_DIVN0 2
+#define JHB100_PER1CLK_200_DIVN1 3
+#define JHB100_PER1CLK_200_DIVN2 4
+#define JHB100_PER1CLK_200_DIVN3 5
+#define JHB100_PER1CLK_200_CCLK_DIV 6
+
+#define JHB100_PER1CLK_SGPIO0_PCLK 15
+#define JHB100_PER1CLK_SGPIO0_DCLK 16
+#define JHB100_PER1CLK_SGPIO1_PCLK 17
+#define JHB100_PER1CLK_SGPIO1_DCLK 18
+
+#define JHB100_PER1CLK_EMMC0_BCLK 22
+
+#define JHB100_PER1CLK_EMMC0_CCLK 25
+
+#define JHB100_PER1CLK_DMAC1_1CH_CORE 29
+
+#define JHB100_PER1CLK_DMAC1_1CH_ACLK 31
+
+#define JHB100_PER1CLK_DMAC2_1CH_CORE 33
+
+#define JHB100_PER1CLK_DMAC2_1CH_ACLK 35
+
+#define JHB100_PER1CLK_DMAC3_1CH_CORE 37
+
+#define JHB100_PER1CLK_DMAC3_1CH_ACLK 39
+
+#define JHB100_PER1CLK_DMAC0_2CH_CORE 41
+
+#define JHB100_PER1CLK_DMAC0_2CH_ACLK 43
+
+#define JHB100_PER1CLK_UFS_REF 45
+#define JHB100_PER1CLK_UFS_300 46
+#define JHB100_PER1CLK_UFS_150 47
+#define JHB100_PER1CLK_UFS_400 48
+#define JHB100_PER1CLK_UFS_75 49
+#define JHB100_PER1CLK_UFS_37_5 50
+#define JHB100_PER1CLK_UFS_7_5 51
+#define JHB100_PER1CLK_UFS_1_875 52
+#define JHB100_PER1CLK_UFS_7_143 53
+#define JHB100_PER1CLK_UFS_3_5715 54
+
+#define JHB100_PER1CLK_MAIN_ICG_EN_SFC0 63
+#define JHB100_PER1CLK_MAIN_ICG_EN_SFC1 64
+#define JHB100_PER1CLK_MAIN_ICG_EN_SFC2 65
+#define JHB100_PER1CLK_MAIN_ICG_EN_SPI0 66
+#define JHB100_PER1CLK_MAIN_ICG_EN_SGPIO0 67
+#define JHB100_PER1CLK_MAIN_ICG_EN_SGPIO1 68
+#define JHB100_PER1CLK_MAIN_ICG_EN_SENSORS_PERIPH1 69
+#define JHB100_PER1CLK_MAIN_ICG_EN_EMMC0 70
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC0 71
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC1 72
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC2 73
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SPI0 74
+#define JHB100_PER1CLK_MAIN_ICG_EN_RAS 75
+#define JHB100_PER1CLK_MAIN_ICG_EN_UFS 76
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index bb5238cb02f6..57977d5b4018 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -143,4 +143,24 @@
#define JHB100_PER0RST_GPIO_IOMUX_PRESETN 74
#define JHB100_PER0RST_UART_MUX_REG_WRAP 75
+/* PER1CRG resets */
+#define JHB100_PER1RST_IOMUX_PRESETN 0
+#define JHB100_PER1RST_SYSCON_PRESETN 1
+#define JHB100_PER1RST_MAIN_RSTN_SFC0 2
+#define JHB100_PER1RST_MAIN_RSTN_SFC1 3
+#define JHB100_PER1RST_MAIN_RSTN_SFC2 4
+#define JHB100_PER1RST_MAIN_RSTN_SPI0 5
+#define JHB100_PER1RST_MAIN_RSTN_PERIPH1_SENSORS 6
+#define JHB100_PER1RST_MAIN_RSTN_SGPIO0 7
+#define JHB100_PER1RST_MAIN_RSTN_SGPIO1 8
+#define JHB100_PER1RST_MAIN_RSTN_EMMC0 9
+
+#define JHB100_PER1RST_MAIN_RSTN_UFS 11
+#define JHB100_PER1RST_MAIN_RSTN_UFS_PHY 12
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC0 13
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC1 14
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC2 15
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SPI0 16
+#define JHB100_PER1RST_MAIN_RSTN_PERIPH1_RAS 17
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
--
2.25.1
^ permalink raw reply related
* [PATCH v1 13/22] clk: starfive: Expand the storage of clock parent index
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Expand the storage of clock parent index for per0 domain, which parent
index over 255. So change u8 to u16.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/clk-starfive-common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
index fd9bf6f20152..8edc6c516451 100644
--- a/drivers/clk/starfive/clk-starfive-common.h
+++ b/drivers/clk/starfive/clk-starfive-common.h
@@ -26,7 +26,7 @@ struct starfive_clk_data {
const char *name;
unsigned long flags;
u32 max;
- u8 parents[4];
+ u16 parents[4];
};
#define STARFIVE_GATE(_idx, _name, _flags, _parent) \
--
2.25.1
^ permalink raw reply related
* [PATCH v1 10/22] clk: starfive: Add JHB100 System-2 clock generator driver
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Add support for JHB100 System-2 clock generator (SYS2CRG).
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-sys2.c | 178 ++++++++++++++++++
3 files changed, 187 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys2.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index b6042bcb5992..729bdfce7b8a 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -91,3 +91,11 @@ config CLK_STARFIVE_JHB100_SYS1
help
Say yes here to support the system-1 clock controller on the
StarFive JHB100 SoC.
+
+config CLK_STARFIVE_JHB100_SYS2
+ bool "StarFive JHB100 system-2 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS0
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the system-2 clock controller on the
+ StarFive JHB100 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index b3571e2f0555..90b6390296bd 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys2.c b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c
new file mode 100644
index 000000000000..5111f139a1c3
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 System-2 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_SYS2CLK_NUM_CLKS (JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 + 1)
+
+/* external clocks */
+#define JHB100_SYS2CLK_OSC (JHB100_SYS2CLK_NUM_CLKS + 0)
+#define JHB100_SYS2CLK_PLL1 (JHB100_SYS2CLK_NUM_CLKS + 1)
+#define JHB100_SYS2CLK_GPU0_600 (JHB100_SYS2CLK_NUM_CLKS + 2)
+#define JHB100_SYS2CLK_GPU1_600 (JHB100_SYS2CLK_NUM_CLKS + 3)
+
+static const struct starfive_clk_data jhb100_sys2crg_clk_data[] __initconst = {
+ /* jtag mst*/
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_200, "jtagm0_200", 6,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_200, "jtagm1_200", 6,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_100, "jtagm0_100", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_100, "jtagm1_100", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_ATPG_TCLOCK, "jtagm0_atpg_tclock", 2,
+ JHB100_SYS2CLK_JTAGM0_100),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_ATPG_TCLOCK, "jtagm1_atpg_tclock", 2,
+ JHB100_SYS2CLK_JTAGM1_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_HCLK, "jtag0_mst_wrap_hclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_200),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_CLK_JTAG, "jtag0_mst_wrap_clk_jtag",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_200),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_APB_PCLK, "jtag0_mst_wrap_apb_pclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_ATPG_TCLOCK, "jtag0_mst_wrap_atpg_tclock",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_HCLK, "jtag1_mst_wrap_hclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_200),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_CLK_JTAG, "jtag1_mst_wrap_clk_jtag",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_200),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_APB_PCLK, "jtag1_mst_wrap_apb_pclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_ATPG_TCLOCK, "jtag1_mst_wrap_atpg_tclock",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_100),
+ /* hostusbcmn */
+ STARFIVE__DIV(JHB100_SYS2CLK_HOSTUSB_100, "hostusb_100", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_HOSTUSBCMN_500, "hostusbcmn_500", 4,
+ JHB100_SYS2CLK_PLL1),
+ /* bmcperiph1 */
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_200, "bmcper1_200", 6,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_250, "bmcper1_250", 5,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_143_DFT, "bmcper1_143_dft", 8,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE_GATE(JHB100_SYS2CLK_BMCPER1_143, "bmcper1_143", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_BMCPER1_143_DFT),
+ /* bmcperiph0 */
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER0_200, "bmcper0_200", 6,
+ JHB100_SYS2CLK_PLL1),
+ /* gpu0 */
+ STARFIVE__DIV(JHB100_SYS2CLK_GPU0_100, "gpu0_100", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU0_BUS_CLK, "gpu0_bus_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU0_600),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU0_APB_CLK, "gpu0_apb_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU0_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU0_OSC_CLK, "gpu0_osc_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_OSC),
+ /* gpu1 */
+ STARFIVE__DIV(JHB100_SYS2CLK_GPU1_100, "gpu1_100", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU1_BUS_CLK, "gpu1_bus_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU1_600),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU1_APB_CLK, "gpu1_apb_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU1_100),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU1_OSC_CLK, "gpu1_osc_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_OSC),
+ /* main icg */
+ STARFIVE_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0, "main_icg_en_jtag0", 0,
+ JHB100_SYS2CLK_JTAGM0_200),
+ STARFIVE_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1, "main_icg_en_jtag1", 0,
+ JHB100_SYS2CLK_JTAGM1_200),
+};
+
+static int __init jhb100_sys2crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_SYS2CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_SYS2CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_SYS2CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_sys2crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_sys2crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_sys2crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_sys2crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_SYS2CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_SYS2CLK_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JHB100_SYS2CLK_PLL1)
+ parents[i].fw_name = "pll1";
+ else if (pidx == JHB100_SYS2CLK_GPU0_600)
+ parents[i].fw_name = "sys2_gpu0_600";
+ else
+ parents[i].fw_name = "sys2_gpu1_600";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-sys2", 0);
+}
+
+static const struct of_device_id jhb100_sys2crg_match[] = {
+ { .compatible = "starfive,jhb100-sys2crg" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jhb100_sys2crg_driver = {
+ .driver = {
+ .name = "clk-starfive-jhb100-sys2",
+ .of_match_table = jhb100_sys2crg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jhb100_sys2crg_driver, jhb100_sys2crg_probe);
--
2.25.1
^ permalink raw reply related
* [PATCH v1 12/22] clk: starfive: Introduce inverter and divider
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
Introduce inverter and divider for starfive clocks.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/clk-starfive-common.c | 12 ++++++++++++
drivers/clk/starfive/clk-starfive-common.h | 8 ++++++++
2 files changed, 20 insertions(+)
diff --git a/drivers/clk/starfive/clk-starfive-common.c b/drivers/clk/starfive/clk-starfive-common.c
index 9c0eb7a50d1e..d84b326c9aed 100644
--- a/drivers/clk/starfive/clk-starfive-common.c
+++ b/drivers/clk/starfive/clk-starfive-common.c
@@ -298,6 +298,15 @@ static const struct clk_ops starfive_clk_inv_ops = {
.debug_init = starfive_clk_debug_init,
};
+static const struct clk_ops starfive_clk_idiv_ops = {
+ .get_phase = starfive_clk_get_phase,
+ .set_phase = starfive_clk_set_phase,
+ .recalc_rate = starfive_clk_recalc_rate,
+ .determine_rate = starfive_clk_determine_rate,
+ .set_rate = starfive_clk_set_rate,
+ .debug_init = starfive_clk_debug_init,
+};
+
const struct clk_ops *starfive_clk_ops(u32 max)
{
if (max & STARFIVE_CLK_DIV_MASK) {
@@ -308,6 +317,9 @@ const struct clk_ops *starfive_clk_ops(u32 max)
}
if (max & STARFIVE_CLK_ENABLE)
return &starfive_clk_gdiv_ops;
+ else if (max & STARFIVE_CLK_INVERT)
+ return &starfive_clk_idiv_ops;
+
if (max == STARFIVE_CLK_FRAC_MAX)
return &starfive_clk_fdiv_ops;
return &starfive_clk_div_ops;
diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
index a03824e9e75f..fd9bf6f20152 100644
--- a/drivers/clk/starfive/clk-starfive-common.h
+++ b/drivers/clk/starfive/clk-starfive-common.h
@@ -103,6 +103,14 @@ struct starfive_clk_data {
.parents = { [0] = _parent }, \
}
+#define STARFIVE_IDIV(_idx, _name, _flags, _max, _parent) \
+[_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = STARFIVE_CLK_INVERT | (_max), \
+ .parents = { [0] = _parent }, \
+}
+
struct starfive_clk {
struct clk_hw hw;
unsigned int idx;
--
2.25.1
^ permalink raw reply related
* [PATCH v1 01/22] reset: starfive: Rename file name "jh71x0" to "common"
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
StarFive JHB100 shares a similar clock and reset design with JH7110.
To facilitate the reuse of the file and its functionalities, files
containing the "jh71x0" naming convention are renamed to use the
"common" wording.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/clk-starfive-jh7110-sys.c | 2 +-
drivers/reset/starfive/Kconfig | 6 +++---
drivers/reset/starfive/Makefile | 2 +-
.../{reset-starfive-jh71x0.c => reset-starfive-common.c} | 4 ++--
.../{reset-starfive-jh71x0.h => reset-starfive-common.h} | 6 +++---
drivers/reset/starfive/reset-starfive-jh7100.c | 2 +-
drivers/reset/starfive/reset-starfive-jh7110.c | 4 ++--
.../{reset-starfive-jh71x0.h => reset-starfive-common.h} | 4 ++--
8 files changed, 15 insertions(+), 15 deletions(-)
rename drivers/reset/starfive/{reset-starfive-jh71x0.c => reset-starfive-common.c} (97%)
rename drivers/reset/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (75%)
rename include/soc/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (81%)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 03c17cd2032f..edf4c45e6ff0 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -14,7 +14,7 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
-#include <soc/starfive/reset-starfive-jh71x0.h>
+#include <soc/starfive/reset-starfive-common.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index d832339f61bc..29fbcf1a7d83 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -1,12 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only
-config RESET_STARFIVE_JH71X0
+config RESET_STARFIVE_COMMON
bool
config RESET_STARFIVE_JH7100
bool "StarFive JH7100 Reset Driver"
depends on ARCH_STARFIVE || COMPILE_TEST
- select RESET_STARFIVE_JH71X0
+ select RESET_STARFIVE_COMMON
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7100 SoC.
@@ -15,7 +15,7 @@ config RESET_STARFIVE_JH7110
bool "StarFive JH7110 Reset Driver"
depends on CLK_STARFIVE_JH7110_SYS
select AUXILIARY_BUS
- select RESET_STARFIVE_JH71X0
+ select RESET_STARFIVE_COMMON
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7110 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index 7a44b66fb9d5..582e4c160bd4 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
+obj-$(CONFIG_RESET_STARFIVE_COMMON) += reset-starfive-common.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-common.c
similarity index 97%
rename from drivers/reset/starfive/reset-starfive-jh71x0.c
rename to drivers/reset/starfive/reset-starfive-common.c
index 29ce3486752f..d615c4a68cc0 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
+++ b/drivers/reset/starfive/reset-starfive-common.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Reset driver for the StarFive JH71X0 SoCs
+ * Reset driver for the StarFive SoCs
*
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
@@ -12,7 +12,7 @@
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
-#include "reset-starfive-jh71x0.h"
+#include "reset-starfive-common.h"
struct jh71x0_reset {
struct reset_controller_dev rcdev;
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-common.h
similarity index 75%
rename from drivers/reset/starfive/reset-starfive-jh71x0.h
rename to drivers/reset/starfive/reset-starfive-common.h
index db7d39a87f87..266acc4b2caf 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
+++ b/drivers/reset/starfive/reset-starfive-common.h
@@ -3,12 +3,12 @@
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
-#ifndef __RESET_STARFIVE_JH71X0_H
-#define __RESET_STARFIVE_JH71X0_H
+#ifndef __RESET_STARFIVE_COMMON_H
+#define __RESET_STARFIVE_COMMON_H
int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
void __iomem *assert, void __iomem *status,
const u32 *asserted, unsigned int nr_resets,
struct module *owner);
-#endif /* __RESET_STARFIVE_JH71X0_H */
+#endif /* __RESET_STARFIVE_COMMON_H */
diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
index 2a56f7fd4ba7..546dea2e5811 100644
--- a/drivers/reset/starfive/reset-starfive-jh7100.c
+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
@@ -8,7 +8,7 @@
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
-#include "reset-starfive-jh71x0.h"
+#include "reset-starfive-common.h"
#include <dt-bindings/reset/starfive-jh7100.h>
diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
index 29a43f0f2ad6..87dba01491ae 100644
--- a/drivers/reset/starfive/reset-starfive-jh7110.c
+++ b/drivers/reset/starfive/reset-starfive-jh7110.c
@@ -7,9 +7,9 @@
#include <linux/auxiliary_bus.h>
-#include <soc/starfive/reset-starfive-jh71x0.h>
+#include <soc/starfive/reset-starfive-common.h>
-#include "reset-starfive-jh71x0.h"
+#include "reset-starfive-common.h"
#include <dt-bindings/reset/starfive,jh7110-crg.h>
diff --git a/include/soc/starfive/reset-starfive-jh71x0.h b/include/soc/starfive/reset-starfive-common.h
similarity index 81%
rename from include/soc/starfive/reset-starfive-jh71x0.h
rename to include/soc/starfive/reset-starfive-common.h
index 47b486ececc5..56d8f413cf18 100644
--- a/include/soc/starfive/reset-starfive-jh71x0.h
+++ b/include/soc/starfive/reset-starfive-common.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __SOC_STARFIVE_RESET_JH71X0_H
-#define __SOC_STARFIVE_RESET_JH71X0_H
+#ifndef __SOC_STARFIVE_RESET_COMMON_H
+#define __SOC_STARFIVE_RESET_COMMON_H
#include <linux/auxiliary_bus.h>
#include <linux/compiler_types.h>
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v12 02/15] powerpc/crash: Fix possible memory leak in update_crash_elfcorehdr()
From: Sourabh Jain @ 2026-04-02 10:57 UTC (permalink / raw)
To: Jinjie Ruan, corbet, skhan, catalin.marinas, will, chenhuacai,
kernel, maddy, mpe, npiggin, chleroy, pjw, palmer, aou, alex,
tglx, mingo, bp, dave.hansen, hpa, robh, saravanak, akpm, bhe,
vgoyal, dyoung, rdunlap, peterz, pawan.kumar.gupta, feng.tang,
dapeng1.mi, kees, elver, paulmck, lirongqing, rppt, leitao, ardb,
jbohac, cfsworks, tangyouling, ritesh.list, hbathini, eajames,
guoren, songshuaishuai, kevin.brodsky, vishal.moola, junhui.liu,
coxu, fuqiang.wang, liaoyuanhong, takahiro.akashi, james.morse,
lizhengyu3, x86, linux-doc, linux-kernel, linux-arm-kernel,
loongarch, linuxppc-dev, linux-riscv, devicetree, kexec
In-Reply-To: <20260402072701.628293-3-ruanjinjie@huawei.com>
On 02/04/26 12:56, Jinjie Ruan wrote:
> In get_crash_memory_ranges(), if crash_exclude_mem_range() failed
> after realloc_mem_ranges() has successfully allocated the cmem
> memory, it just returns an error but leaves cmem pointing to
> the allocated memory, nor is it freed in the caller
> update_crash_elfcorehdr(), which cause a memory leak, goto out
> to free the cmem.
>
> Cc: Sourabh Jain <sourabhjain@linux.ibm.com>
> Cc: Hari Bathini <hbathini@linux.ibm.com>
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Fixes: 849599b702ef ("powerpc/crash: add crash memory hotplug support")
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
> ---
> arch/powerpc/kexec/crash.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kexec/crash.c b/arch/powerpc/kexec/crash.c
> index a325c1c02f96..1d12cef8e1e0 100644
> --- a/arch/powerpc/kexec/crash.c
> +++ b/arch/powerpc/kexec/crash.c
> @@ -440,7 +440,7 @@ static void update_crash_elfcorehdr(struct kimage *image, struct memory_notify *
> ret = get_crash_memory_ranges(&cmem);
> if (ret) {
> pr_err("Failed to get crash mem range\n");
> - return;
> + goto out;
> }
>
> /*
Thanks for fixing this Jinjie.
Feel free to add:
Reviewed-by: Sourabh Jain <sourabhjain@linux.ibm.com>
- Sourabh Jain
^ permalink raw reply
* [PATCH v1 02/22] reset: starfive: Convert the word "jh71x0" to "starfive"
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Function names that consist of the 'jh71x0' naming convention are
renamed to use the 'starfive' wording.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clk/starfive/clk-starfive-jh7110-sys.c | 4 +-
.../reset/starfive/reset-starfive-common.c | 64 +++++++++----------
.../reset/starfive/reset-starfive-common.h | 8 +--
.../reset/starfive/reset-starfive-jh7100.c | 2 +-
.../reset/starfive/reset-starfive-jh7110.c | 4 +-
include/soc/starfive/reset-starfive-common.h | 6 +-
6 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index edf4c45e6ff0..17fd061ee196 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -334,7 +334,7 @@ static void jh7110_reset_unregister_adev(void *_adev)
static void jh7110_reset_adev_release(struct device *dev)
{
struct auxiliary_device *adev = to_auxiliary_dev(dev);
- struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
kfree(rdev);
}
@@ -343,7 +343,7 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
const char *adev_name,
u32 adev_id)
{
- struct jh71x0_reset_adev *rdev;
+ struct starfive_reset_adev *rdev;
struct auxiliary_device *adev;
int ret;
diff --git a/drivers/reset/starfive/reset-starfive-common.c b/drivers/reset/starfive/reset-starfive-common.c
index d615c4a68cc0..772bdf6763d1 100644
--- a/drivers/reset/starfive/reset-starfive-common.c
+++ b/drivers/reset/starfive/reset-starfive-common.c
@@ -14,7 +14,7 @@
#include "reset-starfive-common.h"
-struct jh71x0_reset {
+struct starfive_reset {
struct reset_controller_dev rcdev;
/* protect registers against concurrent read-modify-write */
spinlock_t lock;
@@ -23,16 +23,16 @@ struct jh71x0_reset {
const u32 *asserted;
};
-static inline struct jh71x0_reset *
-jh71x0_reset_from(struct reset_controller_dev *rcdev)
+static inline struct starfive_reset *
+starfive_reset_from(struct reset_controller_dev *rcdev)
{
- return container_of(rcdev, struct jh71x0_reset, rcdev);
+ return container_of(rcdev, struct starfive_reset, rcdev);
}
-static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
+static int starfive_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
{
- struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
+ struct starfive_reset *data = starfive_reset_from(rcdev);
unsigned long offset = id / 32;
u32 mask = BIT(id % 32);
void __iomem *reg_assert = data->assert + offset * sizeof(u32);
@@ -61,34 +61,34 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
return ret;
}
-static int jh71x0_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
- return jh71x0_reset_update(rcdev, id, true);
+ return starfive_reset_update(rcdev, id, true);
}
-static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
- return jh71x0_reset_update(rcdev, id, false);
+ return starfive_reset_update(rcdev, id, false);
}
-static int jh71x0_reset_reset(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
int ret;
- ret = jh71x0_reset_assert(rcdev, id);
+ ret = starfive_reset_assert(rcdev, id);
if (ret)
return ret;
- return jh71x0_reset_deassert(rcdev, id);
+ return starfive_reset_deassert(rcdev, id);
}
-static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
- struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
+ struct starfive_reset *data = starfive_reset_from(rcdev);
unsigned long offset = id / 32;
u32 mask = BIT(id % 32);
void __iomem *reg_status = data->status + offset * sizeof(u32);
@@ -100,25 +100,25 @@ static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
return !((value ^ data->asserted[offset]) & mask);
}
-static const struct reset_control_ops jh71x0_reset_ops = {
- .assert = jh71x0_reset_assert,
- .deassert = jh71x0_reset_deassert,
- .reset = jh71x0_reset_reset,
- .status = jh71x0_reset_status,
+static const struct reset_control_ops starfive_reset_ops = {
+ .assert = starfive_reset_assert,
+ .deassert = starfive_reset_deassert,
+ .reset = starfive_reset_reset,
+ .status = starfive_reset_status,
};
-int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
- void __iomem *assert, void __iomem *status,
- const u32 *asserted, unsigned int nr_resets,
- struct module *owner)
+int reset_starfive_register(struct device *dev, struct device_node *of_node,
+ void __iomem *assert, void __iomem *status,
+ const u32 *asserted, unsigned int nr_resets,
+ struct module *owner)
{
- struct jh71x0_reset *data;
+ struct starfive_reset *data;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
- data->rcdev.ops = &jh71x0_reset_ops;
+ data->rcdev.ops = &starfive_reset_ops;
data->rcdev.owner = owner;
data->rcdev.nr_resets = nr_resets;
data->rcdev.dev = dev;
@@ -131,4 +131,4 @@ int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_no
return devm_reset_controller_register(dev, &data->rcdev);
}
-EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
+EXPORT_SYMBOL_GPL(reset_starfive_register);
diff --git a/drivers/reset/starfive/reset-starfive-common.h b/drivers/reset/starfive/reset-starfive-common.h
index 266acc4b2caf..83461b22ee55 100644
--- a/drivers/reset/starfive/reset-starfive-common.h
+++ b/drivers/reset/starfive/reset-starfive-common.h
@@ -6,9 +6,9 @@
#ifndef __RESET_STARFIVE_COMMON_H
#define __RESET_STARFIVE_COMMON_H
-int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
- void __iomem *assert, void __iomem *status,
- const u32 *asserted, unsigned int nr_resets,
- struct module *owner);
+int reset_starfive_register(struct device *dev, struct device_node *of_node,
+ void __iomem *assert, void __iomem *status,
+ const u32 *asserted, unsigned int nr_resets,
+ struct module *owner);
#endif /* __RESET_STARFIVE_COMMON_H */
diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
index 546dea2e5811..122ac6c3893b 100644
--- a/drivers/reset/starfive/reset-starfive-jh7100.c
+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
@@ -51,7 +51,7 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
- return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
+ return reset_starfive_register(&pdev->dev, pdev->dev.of_node,
base + JH7100_RESET_ASSERT0,
base + JH7100_RESET_STATUS0,
jh7100_reset_asserted,
diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
index 87dba01491ae..c4dd21761e53 100644
--- a/drivers/reset/starfive/reset-starfive-jh7110.c
+++ b/drivers/reset/starfive/reset-starfive-jh7110.c
@@ -53,13 +53,13 @@ static int jh7110_reset_probe(struct auxiliary_device *adev,
const struct auxiliary_device_id *id)
{
struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data);
- struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
void __iomem *base = rdev->base;
if (!info || !base)
return -ENODEV;
- return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
+ return reset_starfive_register(&adev->dev, adev->dev.parent->of_node,
base + info->assert_offset,
base + info->status_offset,
NULL,
diff --git a/include/soc/starfive/reset-starfive-common.h b/include/soc/starfive/reset-starfive-common.h
index 56d8f413cf18..16df46a074bc 100644
--- a/include/soc/starfive/reset-starfive-common.h
+++ b/include/soc/starfive/reset-starfive-common.h
@@ -6,12 +6,12 @@
#include <linux/compiler_types.h>
#include <linux/container_of.h>
-struct jh71x0_reset_adev {
+struct starfive_reset_adev {
void __iomem *base;
struct auxiliary_device adev;
};
-#define to_jh71x0_reset_adev(_adev) \
- container_of((_adev), struct jh71x0_reset_adev, adev)
+#define to_starfive_reset_adev(_adev) \
+ container_of((_adev), struct starfive_reset_adev, adev)
#endif
--
2.25.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox