* [PATCh v3 3/8] arm64: dts: renesas: rzv2h: Add audio clock inputs
From: John Madieu @ 2026-04-02 16:31 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Biju Das,
john.madieu, linux-renesas-soc, linux-clk, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com>
Model external audio clock inputs as CPG input clocks for RZ/V2H family
SoCs (RZ/V2H, RZ/V2N, RZ/G3E), allowing the Audio Clock Generator (ADG)
to derive internal audio clocks from these external sources.
The clock frequencies are board-specific and must be overridden in the
board DTS files.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2: No changes
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 27 ++++++++++++++++++++--
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 27 ++++++++++++++++++++--
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 27 ++++++++++++++++++++--
3 files changed, 75 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 95a4e30a064d..1ff48c8f98e1 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -14,6 +14,27 @@ / {
#size-cells = <2>;
interrupt-parent = <&gic>;
+ audio_clka: audio-clka {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ audio_clkb: audio-clkb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ audio_clkc: audio-clkc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
audio_extal_clk: audio-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -270,8 +291,10 @@ pinctrl: pinctrl@10410000 {
cpg: clock-controller@10420000 {
compatible = "renesas,r9a09g047-cpg";
reg = <0 0x10420000 0 0x10000>;
- clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
- clock-names = "audio_extal", "rtxin", "qextal";
+ clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>,
+ <&audio_clka>, <&audio_clkb>, <&audio_clkc>;
+ clock-names = "audio_extal", "rtxin", "qextal",
+ "audio_clka", "audio_clkb", "audio_clkc";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index 40525470194e..d2ac78006f15 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -32,6 +32,27 @@ / {
#size-cells = <2>;
interrupt-parent = <&gic>;
+ audio_clka: audio-clka {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ audio_clkb: audio-clkb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ audio_clkc: audio-clkc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
audio_extal_clk: audio-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -293,8 +314,10 @@ pinctrl: pinctrl@10410000 {
cpg: clock-controller@10420000 {
compatible = "renesas,r9a09g056-cpg";
reg = <0 0x10420000 0 0x10000>;
- clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
- clock-names = "audio_extal", "rtxin", "qextal";
+ clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>,
+ <&audio_clka>, <&audio_clkb>, <&audio_clkc>;
+ clock-names = "audio_extal", "rtxin", "qextal",
+ "audio_clka", "audio_clkb", "audio_clkc";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 9581af58024e..e15b47dc93d4 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -14,6 +14,27 @@ / {
#size-cells = <2>;
interrupt-parent = <&gic>;
+ audio_clka: audio-clka {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ audio_clkb: audio-clkb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ audio_clkc: audio-clkc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
audio_extal_clk: audio-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -275,8 +296,10 @@ pinctrl: pinctrl@10410000 {
cpg: clock-controller@10420000 {
compatible = "renesas,r9a09g057-cpg";
reg = <0 0x10420000 0 0x10000>;
- clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
- clock-names = "audio_extal", "rtxin", "qextal";
+ clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>,
+ <&audio_clka>, <&audio_clkb>, <&audio_clkc>;
+ clock-names = "audio_extal", "rtxin", "qextal",
+ "audio_clka", "audio_clkb", "audio_clkc";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
--
2.25.1
^ permalink raw reply related
* [PATCh v3 2/8] clk: renesas: r9a09g047: Add audio clock and reset support
From: John Madieu @ 2026-04-02 16:31 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Biju Das,
john.madieu, linux-renesas-soc, linux-clk, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com>
Add clock and reset entries for audio-related modules on the RZ/G3E SoC.
Target modules are:
- SSIU (Serial Sound Interface Unit) with SSI ch0-ch9
- SCU (Sampling Rate Converter Unit) with SRC ch0-ch9, DVC ch0-ch1,
CTU/MIX ch0-ch1
- ADMAC (Audio DMA Controller)
- ADG (Audio Clock Generator) with divider input clocks and audio
master clock outputs
While at it, reorder plldty_div16 to group it with other plldty fixed
dividers.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2: No changes
drivers/clk/renesas/r9a09g047-cpg.c | 129 +++++++++++++++++++++++++++-
1 file changed, 128 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index e59ac4a05a7f..2d7e58f155f6 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -22,6 +22,9 @@ enum clk_ids {
CLK_AUDIO_EXTAL,
CLK_RTXIN,
CLK_QEXTAL,
+ CLK_AUDIO_CLKA,
+ CLK_AUDIO_CLKB,
+ CLK_AUDIO_CLKC,
/* PLL Clocks */
CLK_PLLCM33,
@@ -34,6 +37,8 @@ enum clk_ids {
/* Internal Core Clocks */
CLK_PLLCM33_DIV3,
CLK_PLLCM33_DIV4,
+ CLK_PLLCM33_DIV4_DDIV2,
+ CLK_PLLCM33_DIV4_DDIV2_DIV2,
CLK_PLLCM33_DIV5,
CLK_PLLCM33_DIV16,
CLK_PLLCM33_GEAR,
@@ -41,15 +46,19 @@ enum clk_ids {
CLK_SMUX2_XSPI_CLK1,
CLK_PLLCM33_XSPI,
CLK_PLLCLN_DIV2,
+ CLK_PLLCLN_DIV4,
CLK_PLLCLN_DIV8,
CLK_PLLCLN_DIV16,
CLK_PLLCLN_DIV20,
+ CLK_PLLCLN_DIV32,
CLK_PLLCLN_DIV64,
CLK_PLLCLN_DIV256,
CLK_PLLCLN_DIV1024,
CLK_PLLDTY_ACPU,
CLK_PLLDTY_ACPU_DIV2,
CLK_PLLDTY_ACPU_DIV4,
+ CLK_PLLDTY_DIV2,
+ CLK_PLLDTY_DIV4,
CLK_PLLDTY_DIV8,
CLK_PLLDTY_RCPU,
CLK_PLLDTY_RCPU_DIV4,
@@ -64,6 +73,7 @@ enum clk_ids {
CLK_PLLDTY_DIV16,
CLK_PLLVDO_CRU0,
CLK_PLLVDO_GPU,
+ CLK_CDIV5_MAINOSC,
/* Module Clocks */
MOD_CLK_BASE,
@@ -120,6 +130,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
DEF_INPUT("rtxin", CLK_RTXIN),
DEF_INPUT("qextal", CLK_QEXTAL),
+ DEF_INPUT("audio_clka", CLK_AUDIO_CLKA),
+ DEF_INPUT("audio_clkb", CLK_AUDIO_CLKB),
+ DEF_INPUT("audio_clkc", CLK_AUDIO_CLKC),
/* PLL Clocks */
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
@@ -135,6 +148,11 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
+ DEF_DDIV(".pllcm33_div4_ddiv2", CLK_PLLCM33_DIV4_DDIV2, CLK_PLLCM33_DIV4,
+ CDDIV0_DIVCTL1, dtable_2_64),
+ DEF_FIXED(".pllcm33_div4_ddiv2_div2", CLK_PLLCM33_DIV4_DDIV2_DIV2,
+ CLK_PLLCM33_DIV4_DDIV2, 1, 2),
+
DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
@@ -142,9 +160,11 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
dtable_2_16),
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
+ DEF_FIXED(".pllcln_div4", CLK_PLLCLN_DIV4, CLK_PLLCLN, 1, 4),
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
+ DEF_FIXED(".pllcln_div32", CLK_PLLCLN_DIV32, CLK_PLLCLN, 1, 32),
DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),
DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),
DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),
@@ -152,7 +172,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+ DEF_FIXED(".plldty_div2", CLK_PLLDTY_DIV2, CLK_PLLDTY, 1, 2),
+ DEF_FIXED(".plldty_div4", CLK_PLLDTY_DIV4, CLK_PLLDTY, 1, 4),
DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
+ DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
@@ -164,9 +187,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
- DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
+ DEF_FIXED(".cdiv5_mainosc", CLK_CDIV5_MAINOSC, CLK_QEXTAL, 1, 5),
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
@@ -460,6 +483,96 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
BUS_MSTOP(3, BIT(4))),
DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
BUS_MSTOP(2, BIT(15))),
+ DEF_MOD("ssif_clk", CLK_PLLCLN_DIV8, 15, 5, 7, 21,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("scu_clk", CLK_PLLCLN_DIV8, 15, 6, 7, 22,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("scu_clkx2", CLK_PLLCLN_DIV4, 15, 7, 7, 23,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("admac_clk", CLK_PLLCLN_DIV8, 15, 8, 7, 24,
+ BUS_MSTOP(2, BIT(5))),
+ DEF_MOD("adg_clks1", CLK_PLLCLN_DIV8, 15, 9, 7, 25,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_clk_200m", CLK_PLLCLN_DIV8, 15, 10, 7, 26,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_audio_clka", CLK_AUDIO_CLKA, 15, 11, 7, 27,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_audio_clkb", CLK_AUDIO_CLKB, 15, 12, 7, 28,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_audio_clkc", CLK_AUDIO_CLKC, 15, 13, 7, 29,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi0_clk", CLK_PLLCLN_DIV8, 22, 0, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi1_clk", CLK_PLLCLN_DIV8, 22, 1, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi2_clk", CLK_PLLCLN_DIV8, 22, 2, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi3_clk", CLK_PLLCLN_DIV8, 22, 3, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi4_clk", CLK_PLLCLN_DIV8, 22, 4, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi5_clk", CLK_PLLCLN_DIV8, 22, 5, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi6_clk", CLK_PLLCLN_DIV8, 22, 6, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi7_clk", CLK_PLLCLN_DIV8, 22, 7, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi8_clk", CLK_PLLCLN_DIV8, 22, 8, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi9_clk", CLK_PLLCLN_DIV8, 22, 9, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("dvc0_clk", CLK_PLLCLN_DIV8, 23, 0, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("dvc1_clk", CLK_PLLCLN_DIV8, 23, 1, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("ctu0_mix0_clk", CLK_PLLCLN_DIV8, 23, 2, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("ctu1_mix1_clk", CLK_PLLCLN_DIV8, 23, 3, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src0_clk", CLK_PLLCLN_DIV8, 23, 4, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src1_clk", CLK_PLLCLN_DIV8, 23, 5, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src2_clk", CLK_PLLCLN_DIV8, 23, 6, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src3_clk", CLK_PLLCLN_DIV8, 23, 7, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src4_clk", CLK_PLLCLN_DIV8, 23, 8, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src5_clk", CLK_PLLCLN_DIV8, 23, 9, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src6_clk", CLK_PLLCLN_DIV8, 23, 10, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src7_clk", CLK_PLLCLN_DIV8, 23, 11, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src8_clk", CLK_PLLCLN_DIV8, 23, 12, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src9_clk", CLK_PLLCLN_DIV8, 23, 13, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("scu_supply_clk", CLK_PLLCLN_DIV8, 23, 14, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("ssif_supply_clk", CLK_PLLCLN_DIV8, 24, 0, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi0_clk", CLK_PLLCLN_DIV8, 24, 1, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi1_clk", CLK_PLLCLN_DIV8, 24, 2, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi2_clk", CLK_PLLCLN_DIV8, 24, 3, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi3_clk", CLK_PLLCLN_DIV8, 24, 4, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi4_clk", CLK_PLLCLN_DIV8, 24, 5, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi5_clk", CLK_PLLCLN_DIV8, 24, 6, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi6_clk", CLK_PLLCLN_DIV8, 24, 7, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi7_clk", CLK_PLLCLN_DIV8, 24, 8, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi8_clk", CLK_PLLCLN_DIV8, 24, 9, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi9_clk", CLK_PLLCLN_DIV8, 24, 10, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
};
static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -538,6 +651,20 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */
DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */
DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */
+ DEF_RST(14, 1, 6, 18), /* SSIF_0_ASYNC_RESET_SSI */
+ DEF_RST(14, 2, 6, 19), /* SSIF_0_SYNC_RESET_SSI0 */
+ DEF_RST(14, 3, 6, 20), /* SSIF_0_SYNC_RESET_SSI1 */
+ DEF_RST(14, 4, 6, 21), /* SSIF_0_SYNC_RESET_SSI2 */
+ DEF_RST(14, 5, 6, 22), /* SSIF_0_SYNC_RESET_SSI3 */
+ DEF_RST(14, 6, 6, 23), /* SSIF_0_SYNC_RESET_SSI4 */
+ DEF_RST(14, 7, 6, 24), /* SSIF_0_SYNC_RESET_SSI5 */
+ DEF_RST(14, 8, 6, 25), /* SSIF_0_SYNC_RESET_SSI6 */
+ DEF_RST(14, 9, 6, 26), /* SSIF_0_SYNC_RESET_SSI7 */
+ DEF_RST(14, 10, 6, 27), /* SSIF_0_SYNC_RESET_SSI8 */
+ DEF_RST(14, 11, 6, 28), /* SSIF_0_SYNC_RESET_SSI9 */
+ DEF_RST(14, 12, 6, 29), /* SCU_RESET_SRU */
+ DEF_RST(14, 13, 6, 30), /* ADMAC_ARESETN */
+ DEF_RST(14, 14, 6, 31), /* ADG_RST_RESET_ADG */
DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
};
--
2.25.1
^ permalink raw reply related
* [PATCh v3 1/8] dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family
From: John Madieu @ 2026-04-02 16:31 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Biju Das,
john.madieu, linux-renesas-soc, linux-clk, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com>
RZ/V2H, RZ/V2N, and RZ/G3E support external audio clock inputs
(AUDIO_CLKA, AUDIO_CLKB, AUDIO_CLKC) that can be used by the Audio Clock
Generator (ADG) to derive internal audio clocks. These clocks are optional
and their frequencies are set by the board.
Update the bindings to allow these optional clocks for all RZ/V2H family
SoCs.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2: Remove maxItems as it not needed with items lists.
.../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
index f261445bf341..d9cf62f5224e 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
@@ -26,16 +26,24 @@ properties:
maxItems: 1
clocks:
+ minItems: 3
items:
- description: AUDIO_EXTAL clock input
- description: RTXIN clock input
- description: QEXTAL clock input
+ - description: AUDIO_CLKA clock input
+ - description: AUDIO_CLKB clock input
+ - description: AUDIO_CLKC clock input
clock-names:
+ minItems: 3
items:
- const: audio_extal
- const: rtxin
- const: qextal
+ - const: audio_clka
+ - const: audio_clkb
+ - const: audio_clkc
'#clock-cells':
description: |
--
2.25.1
^ permalink raw reply related
* [PATCh v3 0/8] arm64: dts: renesas: Add RZ/G3E audio enablement
From: John Madieu @ 2026-04-02 16:31 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Biju Das,
john.madieu, linux-renesas-soc, linux-clk, devicetree,
linux-kernel, John Madieu
Add device tree support and board enablement for audio on the
RZ/G3E SMARC EVK with a Dialog DA7212 codec.
This series includes:
- CPG clock binding update for optional audio clock inputs
- CPG driver support for RZ/G3E audio clocks and resets
- Audio clock input nodes for RZ/V2H family DTSIs
- R-Car Sound node for RZ/G3E SoC DTSI
- Board-level enablement: I2C1, Versa3 clock generator, audio
pinmux, and DA7212 codec on SMARC EVK
Audio configuration on SMARC EVK:
- Codec: Dialog DA7212 on I2C1
- Playback: SSI3
- Capture: SSI4 -> SRC0 -> DVC0
- MCLK: 12.288MHz from Versa3 clock generator
- Format: I2S, R-Car Sound as clock master
- SSI4 shares clock pins with SSI3 (shared-pin)
Changes:
v3:
- Splitout from v2 [1]
- No code changes
v2:
- Fix Rob's comment on maxItems not needed with items lists.
- Drop DMA ACK second cell from DT specifier
[1]: https://lore.kernel.org/all/20260402090524.9137-1-john.madieu.xa@bp.renesas.com/
John Madieu (8):
dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family
clk: renesas: r9a09g047: Add audio clock and reset support
arm64: dts: renesas: rzv2h: Add audio clock inputs
arm64: dts: renesas: r9a09g047: Add RZ/G3E Sound support
arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator
arm64: dts: renesas: rzg3e-smarc-som: Add I2C1 support
arm64: dts: renesas: rzg3e-smarc-som: add audio pinmux definitions
arm64: dts: renesas: r9a09g047e57-smarc: add DA7212 audio codec
support
.../bindings/clock/renesas,rzv2h-cpg.yaml | 8 +
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 529 +++++++++++++++++-
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 114 ++++
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 27 +-
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 27 +-
.../boot/dts/renesas/rzg3e-smarc-som.dtsi | 44 ++
drivers/clk/renesas/r9a09g047-cpg.c | 129 ++++-
7 files changed, 871 insertions(+), 7 deletions(-)
--
2.25.1
^ permalink raw reply
* [PATCh v3 14/14] ASoC: rsnd: Add system suspend/resume support
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
Add per-module suspend/resume functions following the existing driver
architecture where each module manages its own resources in its own
file. core.c provides common clock/reset helpers and orchestrates the
calls in the correct order (reverse probe for suspend, probe order
for resume).
Infrastructure clocks (ADG, audmacpp, SCU) are managed globally
using optional APIs to remain transparent to platforms that don't
specify these clocks/resets.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2:
- Distribute suspend/resume into per-module files (ssi.c, ssiu.c, src.c,
ctu.c, mix.c, dvc.c, adg.c, dma.c) instead of monolithic loops in core.c,
following Morimoto-san's architecture suggestion
sound/soc/renesas/rcar/adg.c | 16 +++++++++++++
sound/soc/renesas/rcar/core.c | 43 +++++++++++++++++++++++++++++++++--
sound/soc/renesas/rcar/ctu.c | 20 ++++++++++++++++
sound/soc/renesas/rcar/dma.c | 12 ++++++++++
sound/soc/renesas/rcar/dvc.c | 20 ++++++++++++++++
sound/soc/renesas/rcar/mix.c | 20 ++++++++++++++++
sound/soc/renesas/rcar/rsnd.h | 22 ++++++++++++++++++
sound/soc/renesas/rcar/src.c | 26 +++++++++++++++++++++
sound/soc/renesas/rcar/ssi.c | 20 ++++++++++++++++
sound/soc/renesas/rcar/ssiu.c | 20 ++++++++++++++++
10 files changed, 217 insertions(+), 2 deletions(-)
diff --git a/sound/soc/renesas/rcar/adg.c b/sound/soc/renesas/rcar/adg.c
index d73f29bc9de7..b84627c0f32d 100644
--- a/sound/soc/renesas/rcar/adg.c
+++ b/sound/soc/renesas/rcar/adg.c
@@ -930,3 +930,19 @@ void rsnd_adg_remove(struct rsnd_priv *priv)
/* It should be called after rsnd_adg_clk_disable() */
rsnd_adg_null_clk_clean(priv);
}
+
+void rsnd_adg_suspend(struct rsnd_priv *priv)
+{
+ struct rsnd_mod *mod = rsnd_adg_mod_get(priv);
+
+ if (mod)
+ rsnd_suspend_clk_reset(mod->clk, mod->rstc);
+}
+
+void rsnd_adg_resume(struct rsnd_priv *priv)
+{
+ struct rsnd_mod *mod = rsnd_adg_mod_get(priv);
+
+ if (mod)
+ rsnd_resume_clk_reset(mod->clk, mod->rstc);
+}
diff --git a/sound/soc/renesas/rcar/core.c b/sound/soc/renesas/rcar/core.c
index d85c614af598..ff19c49b57e8 100644
--- a/sound/soc/renesas/rcar/core.c
+++ b/sound/soc/renesas/rcar/core.c
@@ -961,7 +961,8 @@ static int rsnd_soc_hw_rule_channels(struct snd_pcm_hw_params *params,
static const struct snd_pcm_hardware rsnd_pcm_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
- SNDRV_PCM_INFO_MMAP_VALID,
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_RESUME,
.buffer_bytes_max = 64 * 1024,
.period_bytes_min = 32,
.period_bytes_max = 8192,
@@ -2058,11 +2059,35 @@ static void rsnd_remove(struct platform_device *pdev)
remove_func[i](priv);
}
+void rsnd_suspend_clk_reset(struct clk *clk, struct reset_control *rstc)
+{
+ clk_unprepare(clk);
+ reset_control_assert(rstc);
+}
+
+void rsnd_resume_clk_reset(struct clk *clk, struct reset_control *rstc)
+{
+ reset_control_deassert(rstc);
+ clk_prepare(clk);
+}
+
static int rsnd_suspend(struct device *dev)
{
struct rsnd_priv *priv = dev_get_drvdata(dev);
+ /*
+ * Reverse order of probe:
+ * ADG -> DVC -> MIX -> CTU -> SRC -> SSIU -> SSI -> DMA
+ */
rsnd_adg_clk_disable(priv);
+ rsnd_adg_suspend(priv);
+ rsnd_dvc_suspend(priv);
+ rsnd_mix_suspend(priv);
+ rsnd_ctu_suspend(priv);
+ rsnd_src_suspend(priv);
+ rsnd_ssiu_suspend(priv);
+ rsnd_ssi_suspend(priv);
+ rsnd_dma_suspend(priv);
return 0;
}
@@ -2071,7 +2096,21 @@ static int rsnd_resume(struct device *dev)
{
struct rsnd_priv *priv = dev_get_drvdata(dev);
- return rsnd_adg_clk_enable(priv);
+ /*
+ * Same order as probe:
+ * DMA -> SSI -> SSIU -> SRC -> CTU -> MIX -> DVC -> ADG
+ */
+ rsnd_dma_resume(priv);
+ rsnd_ssi_resume(priv);
+ rsnd_ssiu_resume(priv);
+ rsnd_src_resume(priv);
+ rsnd_ctu_resume(priv);
+ rsnd_mix_resume(priv);
+ rsnd_dvc_resume(priv);
+ rsnd_adg_resume(priv);
+ rsnd_adg_clk_enable(priv);
+
+ return 0;
}
static const struct dev_pm_ops rsnd_pm_ops = {
diff --git a/sound/soc/renesas/rcar/ctu.c b/sound/soc/renesas/rcar/ctu.c
index 81bba6a1af6e..73795d5b2817 100644
--- a/sound/soc/renesas/rcar/ctu.c
+++ b/sound/soc/renesas/rcar/ctu.c
@@ -383,3 +383,23 @@ void rsnd_ctu_remove(struct rsnd_priv *priv)
rsnd_mod_quit(rsnd_mod_get(ctu));
}
}
+
+void rsnd_ctu_suspend(struct rsnd_priv *priv)
+{
+ struct rsnd_ctu *ctu;
+ int i;
+
+ for_each_rsnd_ctu(ctu, priv, i)
+ rsnd_suspend_clk_reset(rsnd_mod_get(ctu)->clk,
+ rsnd_mod_get(ctu)->rstc);
+}
+
+void rsnd_ctu_resume(struct rsnd_priv *priv)
+{
+ struct rsnd_ctu *ctu;
+ int i;
+
+ for_each_rsnd_ctu(ctu, priv, i)
+ rsnd_resume_clk_reset(rsnd_mod_get(ctu)->clk,
+ rsnd_mod_get(ctu)->rstc);
+}
diff --git a/sound/soc/renesas/rcar/dma.c b/sound/soc/renesas/rcar/dma.c
index 5b63206361ef..b1b07072cf8e 100644
--- a/sound/soc/renesas/rcar/dma.c
+++ b/sound/soc/renesas/rcar/dma.c
@@ -984,3 +984,15 @@ int rsnd_dma_probe(struct rsnd_priv *priv)
/* dummy mem mod for debug */
return rsnd_mod_init(NULL, &mem, &mem_ops, NULL, NULL, 0, 0);
}
+
+void rsnd_dma_suspend(struct rsnd_priv *priv)
+{
+ clk_disable_unprepare(priv->audmapp_clk);
+ rsnd_suspend_clk_reset(NULL, priv->audmapp_rstc);
+}
+
+void rsnd_dma_resume(struct rsnd_priv *priv)
+{
+ rsnd_resume_clk_reset(NULL, priv->audmapp_rstc);
+ clk_prepare_enable(priv->audmapp_clk);
+}
diff --git a/sound/soc/renesas/rcar/dvc.c b/sound/soc/renesas/rcar/dvc.c
index bf7146ceb5f6..0e81fdf0e97b 100644
--- a/sound/soc/renesas/rcar/dvc.c
+++ b/sound/soc/renesas/rcar/dvc.c
@@ -386,3 +386,23 @@ void rsnd_dvc_remove(struct rsnd_priv *priv)
rsnd_mod_quit(rsnd_mod_get(dvc));
}
}
+
+void rsnd_dvc_suspend(struct rsnd_priv *priv)
+{
+ struct rsnd_dvc *dvc;
+ int i;
+
+ for_each_rsnd_dvc(dvc, priv, i)
+ rsnd_suspend_clk_reset(rsnd_mod_get(dvc)->clk,
+ rsnd_mod_get(dvc)->rstc);
+}
+
+void rsnd_dvc_resume(struct rsnd_priv *priv)
+{
+ struct rsnd_dvc *dvc;
+ int i;
+
+ for_each_rsnd_dvc(dvc, priv, i)
+ rsnd_resume_clk_reset(rsnd_mod_get(dvc)->clk,
+ rsnd_mod_get(dvc)->rstc);
+}
diff --git a/sound/soc/renesas/rcar/mix.c b/sound/soc/renesas/rcar/mix.c
index 566e9b2a488c..42bb07ade3c8 100644
--- a/sound/soc/renesas/rcar/mix.c
+++ b/sound/soc/renesas/rcar/mix.c
@@ -350,3 +350,23 @@ void rsnd_mix_remove(struct rsnd_priv *priv)
rsnd_mod_quit(rsnd_mod_get(mix));
}
}
+
+void rsnd_mix_suspend(struct rsnd_priv *priv)
+{
+ struct rsnd_mix *mix;
+ int i;
+
+ for_each_rsnd_mix(mix, priv, i)
+ rsnd_suspend_clk_reset(rsnd_mod_get(mix)->clk,
+ rsnd_mod_get(mix)->rstc);
+}
+
+void rsnd_mix_resume(struct rsnd_priv *priv)
+{
+ struct rsnd_mix *mix;
+ int i;
+
+ for_each_rsnd_mix(mix, priv, i)
+ rsnd_resume_clk_reset(rsnd_mod_get(mix)->clk,
+ rsnd_mod_get(mix)->rstc);
+}
diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h
index ddaac350a049..4b62e051e3e1 100644
--- a/sound/soc/renesas/rcar/rsnd.h
+++ b/sound/soc/renesas/rcar/rsnd.h
@@ -921,4 +921,26 @@ void rsnd_debugfs_mod_reg_show(struct seq_file *m, struct rsnd_mod *mod,
#define rsnd_debugfs_probe NULL
#endif
+/* PM helpers */
+void rsnd_suspend_clk_reset(struct clk *clk, struct reset_control *rstc);
+void rsnd_resume_clk_reset(struct clk *clk, struct reset_control *rstc);
+
+/* Per-module suspend/resume */
+void rsnd_ssi_suspend(struct rsnd_priv *priv);
+void rsnd_ssi_resume(struct rsnd_priv *priv);
+void rsnd_ssiu_suspend(struct rsnd_priv *priv);
+void rsnd_ssiu_resume(struct rsnd_priv *priv);
+void rsnd_src_suspend(struct rsnd_priv *priv);
+void rsnd_src_resume(struct rsnd_priv *priv);
+void rsnd_ctu_suspend(struct rsnd_priv *priv);
+void rsnd_ctu_resume(struct rsnd_priv *priv);
+void rsnd_mix_suspend(struct rsnd_priv *priv);
+void rsnd_mix_resume(struct rsnd_priv *priv);
+void rsnd_dvc_suspend(struct rsnd_priv *priv);
+void rsnd_dvc_resume(struct rsnd_priv *priv);
+void rsnd_adg_suspend(struct rsnd_priv *priv);
+void rsnd_adg_resume(struct rsnd_priv *priv);
+void rsnd_dma_suspend(struct rsnd_priv *priv);
+void rsnd_dma_resume(struct rsnd_priv *priv);
+
#endif /* RSND_H */
diff --git a/sound/soc/renesas/rcar/src.c b/sound/soc/renesas/rcar/src.c
index e1f609589406..51190deaeee0 100644
--- a/sound/soc/renesas/rcar/src.c
+++ b/sound/soc/renesas/rcar/src.c
@@ -832,3 +832,29 @@ void rsnd_src_remove(struct rsnd_priv *priv)
rsnd_mod_quit(rsnd_mod_get(src));
}
}
+
+void rsnd_src_suspend(struct rsnd_priv *priv)
+{
+ struct rsnd_src *src;
+ int i;
+
+ for_each_rsnd_src(src, priv, i)
+ rsnd_suspend_clk_reset(rsnd_mod_get(src)->clk,
+ rsnd_mod_get(src)->rstc);
+
+ clk_disable_unprepare(priv->clk_scu_x2);
+ clk_disable_unprepare(priv->clk_scu);
+}
+
+void rsnd_src_resume(struct rsnd_priv *priv)
+{
+ struct rsnd_src *src;
+ int i;
+
+ clk_prepare_enable(priv->clk_scu);
+ clk_prepare_enable(priv->clk_scu_x2);
+
+ for_each_rsnd_src(src, priv, i)
+ rsnd_resume_clk_reset(rsnd_mod_get(src)->clk,
+ rsnd_mod_get(src)->rstc);
+}
diff --git a/sound/soc/renesas/rcar/ssi.c b/sound/soc/renesas/rcar/ssi.c
index c61750922aff..f5333c9e7c33 100644
--- a/sound/soc/renesas/rcar/ssi.c
+++ b/sound/soc/renesas/rcar/ssi.c
@@ -1279,3 +1279,23 @@ void rsnd_ssi_remove(struct rsnd_priv *priv)
rsnd_mod_quit(rsnd_mod_get(ssi));
}
}
+
+void rsnd_ssi_suspend(struct rsnd_priv *priv)
+{
+ struct rsnd_ssi *ssi;
+ int i;
+
+ for_each_rsnd_ssi(ssi, priv, i)
+ rsnd_suspend_clk_reset(rsnd_mod_get(ssi)->clk,
+ rsnd_mod_get(ssi)->rstc);
+}
+
+void rsnd_ssi_resume(struct rsnd_priv *priv)
+{
+ struct rsnd_ssi *ssi;
+ int i;
+
+ for_each_rsnd_ssi(ssi, priv, i)
+ rsnd_resume_clk_reset(rsnd_mod_get(ssi)->clk,
+ rsnd_mod_get(ssi)->rstc);
+}
diff --git a/sound/soc/renesas/rcar/ssiu.c b/sound/soc/renesas/rcar/ssiu.c
index 1462f02c2a7f..9cb9d12cee1f 100644
--- a/sound/soc/renesas/rcar/ssiu.c
+++ b/sound/soc/renesas/rcar/ssiu.c
@@ -614,3 +614,23 @@ void rsnd_ssiu_remove(struct rsnd_priv *priv)
rsnd_mod_quit(rsnd_mod_get(ssiu));
}
}
+
+void rsnd_ssiu_suspend(struct rsnd_priv *priv)
+{
+ struct rsnd_ssiu *ssiu;
+ int i;
+
+ for_each_rsnd_ssiu(ssiu, priv, i)
+ rsnd_suspend_clk_reset(rsnd_mod_get(ssiu)->clk,
+ rsnd_mod_get(ssiu)->rstc);
+}
+
+void rsnd_ssiu_resume(struct rsnd_priv *priv)
+{
+ struct rsnd_ssiu *ssiu;
+ int i;
+
+ for_each_rsnd_ssiu(ssiu, priv, i)
+ rsnd_resume_clk_reset(rsnd_mod_get(ssiu)->clk,
+ rsnd_mod_get(ssiu)->rstc);
+}
--
2.25.1
^ permalink raw reply related
* [PATCh v3 13/14] ASoC: rsnd: Export rsnd_ssiu_mod_get() for PM support
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
Remove the static qualifier from rsnd_ssiu_mod_get() and export it
via rsnd.h.
This is preparation for system suspend/resume support, where the PM
callbacks need to access SSIU modules to manage their clock and reset
state.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2: New patch, resulting from a split of the previous one
sound/soc/renesas/rcar/rsnd.h | 1 +
sound/soc/renesas/rcar/ssiu.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h
index 3860e1c4943f..ddaac350a049 100644
--- a/sound/soc/renesas/rcar/rsnd.h
+++ b/sound/soc/renesas/rcar/rsnd.h
@@ -815,6 +815,7 @@ int rsnd_ssi_is_dma_mode(struct rsnd_mod *mod);
int __rsnd_ssi_is_pin_sharing(struct rsnd_mod *mod);
#define rsnd_ssi_of_node(priv) rsnd_parse_of_node(priv, RSND_NODE_SSI)
+struct rsnd_mod *rsnd_ssiu_mod_get(struct rsnd_priv *priv, int id);
void rsnd_parse_connect_ssi(struct rsnd_dai *rdai,
struct device_node *playback,
struct device_node *capture);
diff --git a/sound/soc/renesas/rcar/ssiu.c b/sound/soc/renesas/rcar/ssiu.c
index f377d9414633..1462f02c2a7f 100644
--- a/sound/soc/renesas/rcar/ssiu.c
+++ b/sound/soc/renesas/rcar/ssiu.c
@@ -434,7 +434,7 @@ static struct rsnd_mod_ops rsnd_ssiu_ops_gen2 = {
DEBUG_INFO
};
-static struct rsnd_mod *rsnd_ssiu_mod_get(struct rsnd_priv *priv, int id)
+struct rsnd_mod *rsnd_ssiu_mod_get(struct rsnd_priv *priv, int id)
{
if (WARN_ON(id < 0 || id >= rsnd_ssiu_nr(priv)))
id = 0;
--
2.25.1
^ permalink raw reply related
* [PATCh v3 12/14] ASoC: rsnd: Add rsnd_adg_mod_get() for PM support
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
Add rsnd_adg_mod_get() to retrieve the ADG module handle.
This is preparation for system suspend/resume support, where the PM
callbacks need to access the ADG module to manage its clock and reset
state. Other modules (SSI, SRC, CTU, MIX, DVC) already have their
getters exported.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2: Moved export part into a new patch (the next one)
sound/soc/renesas/rcar/adg.c | 10 ++++++++++
sound/soc/renesas/rcar/rsnd.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/sound/soc/renesas/rcar/adg.c b/sound/soc/renesas/rcar/adg.c
index 131a60689f6d..d73f29bc9de7 100644
--- a/sound/soc/renesas/rcar/adg.c
+++ b/sound/soc/renesas/rcar/adg.c
@@ -906,6 +906,16 @@ int rsnd_adg_probe(struct rsnd_priv *priv)
return 0;
}
+struct rsnd_mod *rsnd_adg_mod_get(struct rsnd_priv *priv)
+{
+ struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
+
+ if (!adg)
+ return NULL;
+
+ return rsnd_mod_get(adg);
+}
+
void rsnd_adg_remove(struct rsnd_priv *priv)
{
struct device *dev = rsnd_priv_to_dev(priv);
diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h
index 8700b39b535e..3860e1c4943f 100644
--- a/sound/soc/renesas/rcar/rsnd.h
+++ b/sound/soc/renesas/rcar/rsnd.h
@@ -618,6 +618,7 @@ int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
#define rsnd_adg_clk_disable(priv) rsnd_adg_clk_control(priv, 0)
int rsnd_adg_clk_control(struct rsnd_priv *priv, int enable);
void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m);
+struct rsnd_mod *rsnd_adg_mod_get(struct rsnd_priv *priv);
/*
* R-Car sound priv
--
2.25.1
^ permalink raw reply related
* [PATCh v3 11/14] ASoC: rsnd: src: Add SRC reset and clock support for RZ/G3E
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
The RZ/G3E SoC requires explicit SCU (Sampling Rate Converter Unit)
reset and clock management unlike previous R-Car generations:
- scu_clk: SCU module clock
- scu_clkx2: SCU double-rate clock
- scu_supply_clk: SCU supply clock
Without these clocks enabled, the SRC module cannot operate on RZ/G3E.
Add support for the shared SCU reset controller used by the SRC modules
on the Renesas RZ/G3E SoC. All SRC instances are gated by the same "scu"
reset line.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2: No changes
sound/soc/renesas/rcar/rsnd.h | 7 ++++++
sound/soc/renesas/rcar/src.c | 45 +++++++++++++++++++++++++++++++++--
2 files changed, 50 insertions(+), 2 deletions(-)
diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h
index 2c5738926093..8700b39b535e 100644
--- a/sound/soc/renesas/rcar/rsnd.h
+++ b/sound/soc/renesas/rcar/rsnd.h
@@ -632,6 +632,13 @@ struct rsnd_priv {
struct clk *audmapp_clk;
struct reset_control *audmapp_rstc;
+ /*
+ * Below values will be filled in rsnd_src_probe()
+ */
+ struct clk *clk_scu;
+ struct clk *clk_scu_x2;
+ struct clk *clk_scu_supply;
+
spinlock_t lock;
unsigned int ssiu_busif_count;
unsigned long flags;
diff --git a/sound/soc/renesas/rcar/src.c b/sound/soc/renesas/rcar/src.c
index 8b58cc20e7a8..e1f609589406 100644
--- a/sound/soc/renesas/rcar/src.c
+++ b/sound/soc/renesas/rcar/src.c
@@ -516,6 +516,7 @@ static int rsnd_src_init(struct rsnd_mod *mod,
struct rsnd_priv *priv)
{
struct rsnd_src *src = rsnd_mod_to_src(mod);
+ struct device *dev = rsnd_priv_to_dev(priv);
int ret;
/* reset sync convert_rate */
@@ -526,6 +527,12 @@ static int rsnd_src_init(struct rsnd_mod *mod,
if (ret < 0)
return ret;
+ ret = clk_prepare_enable(priv->clk_scu_supply);
+ if (ret) {
+ dev_err(dev, "Cannot enable scu_supply_clk\n");
+ return ret;
+ }
+
rsnd_src_activation(mod);
rsnd_src_init_convert_rate(io, mod);
@@ -549,6 +556,8 @@ static int rsnd_src_quit(struct rsnd_mod *mod,
src->sync.val =
src->current_sync_rate = 0;
+ clk_disable_unprepare(priv->clk_scu_supply);
+
return 0;
}
@@ -711,8 +720,9 @@ struct rsnd_mod *rsnd_src_mod_get(struct rsnd_priv *priv, int id)
int rsnd_src_probe(struct rsnd_priv *priv)
{
- struct device_node *node;
struct device *dev = rsnd_priv_to_dev(priv);
+ struct reset_control *rstc;
+ struct device_node *node;
struct rsnd_src *src;
struct clk *clk;
char name[RSND_SRC_NAME_SIZE];
@@ -737,6 +747,27 @@ int rsnd_src_probe(struct rsnd_priv *priv)
priv->src_nr = nr;
priv->src = src;
+ priv->clk_scu = devm_clk_get_optional_enabled(dev, "scu");
+ if (IS_ERR(priv->clk_scu)) {
+ ret = dev_err_probe(dev, PTR_ERR(priv->clk_scu),
+ "failed to get scu clock\n");
+ goto rsnd_src_probe_done;
+ }
+
+ priv->clk_scu_x2 = devm_clk_get_optional_enabled(dev, "scu_x2");
+ if (IS_ERR(priv->clk_scu_x2)) {
+ ret = dev_err_probe(dev, PTR_ERR(priv->clk_scu_x2),
+ "failed to get scu_x2 clock\n");
+ goto rsnd_src_probe_done;
+ }
+
+ priv->clk_scu_supply = devm_clk_get_optional(dev, "scu_supply");
+ if (IS_ERR(priv->clk_scu_supply)) {
+ ret = dev_err_probe(dev, PTR_ERR(priv->clk_scu_supply),
+ "failed to get scu_supply clock\n");
+ goto rsnd_src_probe_done;
+ }
+
i = 0;
for_each_child_of_node_scoped(node, np) {
if (!of_device_is_available(np))
@@ -759,6 +790,16 @@ int rsnd_src_probe(struct rsnd_priv *priv)
goto rsnd_src_probe_done;
}
+ /*
+ * RZ/G3E uses a shared SCU reset controller for all SRC modules.
+ * R-Car platforms typically don't have SRC reset controls.
+ */
+ rstc = devm_reset_control_get_optional_shared(dev, "scu");
+ if (IS_ERR(rstc)) {
+ ret = PTR_ERR(rstc);
+ goto rsnd_src_probe_done;
+ }
+
clk = devm_clk_get(dev, name);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
@@ -766,7 +807,7 @@ int rsnd_src_probe(struct rsnd_priv *priv)
}
ret = rsnd_mod_init(priv, rsnd_mod_get(src),
- &rsnd_src_ops, clk, NULL, RSND_MOD_SRC, i);
+ &rsnd_src_ops, clk, rstc, RSND_MOD_SRC, i);
if (ret)
goto rsnd_src_probe_done;
--
2.25.1
^ permalink raw reply related
* [PATCh v3 10/14] ASoC: rsnd: adg: Add per-SSI ADG and SSIF supply clock management
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
RZ/G3E's ADG module requires explicit clock management for SSI audio
interfaces that differs from R-Car Gen2/Gen3/Gen4:
- Per-SSI ADG clocks (adg.ssi.N) for each SSI module
- A shared SSIF supply clock for the SSI subsystem
These clocks are acquired using optional APIs, making them transparent
to platforms that do not require them.
Additionally, since rsnd_adg_ssi_clk_try_start() is called from the
trigger path (atomic context), clk_prepare_enable() cannot be used
directly as clk_prepare() may sleep. Split clock handling into:
- hw_params: clk_prepare() - sleepable context
- trigger (start): clk_enable() - atomic safe
- trigger (stop): clk_disable() - atomic safe
- hw_free: clk_unprepare() - sleepable context
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2: No changes
sound/soc/renesas/rcar/adg.c | 99 ++++++++++++++++++++++++++++++++++-
sound/soc/renesas/rcar/rsnd.h | 2 +
sound/soc/renesas/rcar/ssi.c | 18 +++++++
3 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/sound/soc/renesas/rcar/adg.c b/sound/soc/renesas/rcar/adg.c
index cbb5c4432a2d..131a60689f6d 100644
--- a/sound/soc/renesas/rcar/adg.c
+++ b/sound/soc/renesas/rcar/adg.c
@@ -19,6 +19,9 @@
#define CLKOUT3 3
#define CLKOUTMAX 4
+/* Maximum SSI count for per-SSI clocks */
+#define ADG_SSI_MAX 10
+
#define BRGCKR_31 (1 << 31)
#define BRRx_MASK(x) (0x3FF & x)
@@ -34,6 +37,9 @@ struct rsnd_adg {
struct clk *adg;
struct clk *clkin[CLKINMAX];
struct clk *clkout[CLKOUTMAX];
+ /* RZ/G3E: per-SSI ADG clocks (adg.ssi.0 through adg.ssi.9) */
+ struct clk *clk_adg_ssi[ADG_SSI_MAX];
+ struct clk *clk_ssif_supply;
struct clk *null_clk;
struct clk_onecell_data onecell;
struct rsnd_mod mod;
@@ -341,10 +347,58 @@ int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
return -EIO;
}
+/*
+ * RZ/G3E: Prepare SSI clocks - call from hw_params (can sleep)
+ */
+int rsnd_adg_ssi_clk_prepare(struct rsnd_mod *ssi_mod)
+{
+ struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
+ struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
+ struct device *dev = rsnd_priv_to_dev(priv);
+ int id = rsnd_mod_id(ssi_mod);
+ int ret;
+
+ ret = clk_prepare(adg->clk_adg_ssi[id]);
+ if (ret) {
+ dev_err(dev, "Cannot prepare adg.ssi.%d ADG clock\n", id);
+ return ret;
+ }
+
+ ret = clk_prepare(adg->clk_ssif_supply);
+ if (ret) {
+ dev_err(dev, "Cannot prepare SSIF supply clock\n");
+ clk_unprepare(adg->clk_adg_ssi[id]);
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * RZ/G3E: Unprepare SSI clocks - call from hw_free (can sleep)
+ */
+void rsnd_adg_ssi_clk_unprepare(struct rsnd_mod *ssi_mod)
+{
+ struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
+ struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
+ int id = rsnd_mod_id(ssi_mod);
+
+ clk_unprepare(adg->clk_adg_ssi[id]);
+ clk_unprepare(adg->clk_ssif_supply);
+}
+
int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
{
+ struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
+ struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
+ int id = rsnd_mod_id(ssi_mod);
+
rsnd_adg_set_ssi_clk(ssi_mod, 0);
+ /* RZ/G3E: only disable here, unprepare is done in hw_free */
+ clk_disable(adg->clk_adg_ssi[id]);
+ clk_disable(adg->clk_ssif_supply);
+
return 0;
}
@@ -354,7 +408,8 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
- int data;
+ int id = rsnd_mod_id(ssi_mod);
+ int ret, data;
u32 ckr = 0;
data = rsnd_adg_clk_query(priv, rate);
@@ -376,6 +431,18 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
(ckr) ? adg->brg_rate[ADG_HZ_48] :
adg->brg_rate[ADG_HZ_441]);
+ /*
+ * RZ/G3E: enable per-SSI and supply clocks
+ * Prepare was done in hw_params
+ */
+ ret = clk_enable(adg->clk_adg_ssi[id]);
+ if (ret)
+ dev_warn(dev, "Cannot enable adg.ssi.%d ADG clock\n", id);
+
+ ret = clk_enable(adg->clk_ssif_supply);
+ if (ret)
+ dev_warn(dev, "Cannot enable SSIF supply clock\n");
+
return 0;
}
@@ -769,6 +836,31 @@ void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m)
#define rsnd_adg_clk_dbg_info(priv, m)
#endif
+static int rsnd_adg_get_ssi_clks(struct rsnd_priv *priv)
+{
+ struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
+ struct device *dev = rsnd_priv_to_dev(priv);
+ char name[16];
+ int i;
+
+ /* SSIF supply clock */
+ adg->clk_ssif_supply = devm_clk_get_optional(dev, "ssif_supply");
+ if (IS_ERR(adg->clk_ssif_supply))
+ return dev_err_probe(dev, PTR_ERR(adg->clk_ssif_supply),
+ "failed to get ssif_supply clock\n");
+
+ /* Per-SSI ADG clocks */
+ for (i = 0; i < ADG_SSI_MAX; i++) {
+ snprintf(name, sizeof(name), "adg.ssi.%d", i);
+ adg->clk_adg_ssi[i] = devm_clk_get_optional(dev, name);
+ if (IS_ERR(adg->clk_adg_ssi[i]))
+ return dev_err_probe(dev, PTR_ERR(adg->clk_adg_ssi[i]),
+ "failed to get %s clock\n", name);
+ }
+
+ return 0;
+}
+
int rsnd_adg_probe(struct rsnd_priv *priv)
{
struct reset_control *rstc;
@@ -800,6 +892,11 @@ int rsnd_adg_probe(struct rsnd_priv *priv)
if (ret)
return ret;
+ /* RZ/G3E-specific: per-SSI ADG and SSIF supply clocks */
+ ret = rsnd_adg_get_ssi_clks(priv);
+ if (ret)
+ return ret;
+
ret = rsnd_adg_clk_enable(priv);
if (ret)
return ret;
diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h
index 5c5be0f64cb1..2c5738926093 100644
--- a/sound/soc/renesas/rcar/rsnd.h
+++ b/sound/soc/renesas/rcar/rsnd.h
@@ -602,6 +602,8 @@ void __iomem *rsnd_gen_get_base_addr(struct rsnd_priv *priv, int reg_id);
* R-Car ADG
*/
int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate);
+int rsnd_adg_ssi_clk_prepare(struct rsnd_mod *ssi_mod);
+void rsnd_adg_ssi_clk_unprepare(struct rsnd_mod *ssi_mod);
int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod);
int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate);
int rsnd_adg_probe(struct rsnd_priv *priv);
diff --git a/sound/soc/renesas/rcar/ssi.c b/sound/soc/renesas/rcar/ssi.c
index c65435551283..c61750922aff 100644
--- a/sound/soc/renesas/rcar/ssi.c
+++ b/sound/soc/renesas/rcar/ssi.c
@@ -537,6 +537,7 @@ static int rsnd_ssi_hw_params(struct rsnd_mod *mod,
{
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
unsigned int fmt_width = snd_pcm_format_width(params_format(params));
+ int ret;
if (fmt_width > rdai->chan_width) {
struct rsnd_priv *priv = rsnd_io_to_priv(io);
@@ -546,6 +547,21 @@ static int rsnd_ssi_hw_params(struct rsnd_mod *mod,
return -EINVAL;
}
+ /* RZ/G3E: prepare clocks here (can sleep) */
+ ret = rsnd_adg_ssi_clk_prepare(mod);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int rsnd_ssi_hw_free(struct rsnd_mod *mod,
+ struct rsnd_dai_stream *io,
+ struct snd_pcm_substream *substream)
+{
+ /* RZ/G3E: unprepare clocks here (can sleep) */
+ rsnd_adg_ssi_clk_unprepare(mod);
+
return 0;
}
@@ -956,6 +972,7 @@ static struct rsnd_mod_ops rsnd_ssi_pio_ops = {
.pointer = rsnd_ssi_pio_pointer,
.pcm_new = rsnd_ssi_pcm_new,
.hw_params = rsnd_ssi_hw_params,
+ .hw_free = rsnd_ssi_hw_free,
.get_status = rsnd_ssi_get_status,
};
@@ -1070,6 +1087,7 @@ static struct rsnd_mod_ops rsnd_ssi_dma_ops = {
.pcm_new = rsnd_ssi_pcm_new,
.fallback = rsnd_ssi_fallback,
.hw_params = rsnd_ssi_hw_params,
+ .hw_free = rsnd_ssi_hw_free,
.get_status = rsnd_ssi_get_status,
DEBUG_INFO
};
--
2.25.1
^ permalink raw reply related
* [PATCh v3 09/14] ASoC: rsnd: Add ADG reset support for RZ/G3E
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
RZ/G3E requires the ADG reset line to be deasserted for the audio
subsystem to operate. The ADG module clock is already managed via
rsnd_adg_clk_enable/disable() through adg->adg, so no additional
clock handling is needed.
Add support for the optional "adg" reset control on Renesas RZ/G3E SoC.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
changes:
v3: No changes
v2: No changes
sound/soc/renesas/rcar/adg.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/sound/soc/renesas/rcar/adg.c b/sound/soc/renesas/rcar/adg.c
index 0105c60a144e..cbb5c4432a2d 100644
--- a/sound/soc/renesas/rcar/adg.c
+++ b/sound/soc/renesas/rcar/adg.c
@@ -771,6 +771,7 @@ void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m)
int rsnd_adg_probe(struct rsnd_priv *priv)
{
+ struct reset_control *rstc;
struct rsnd_adg *adg;
struct device *dev = rsnd_priv_to_dev(priv);
int ret;
@@ -779,8 +780,13 @@ int rsnd_adg_probe(struct rsnd_priv *priv)
if (!adg)
return -ENOMEM;
+ rstc = devm_reset_control_get_optional_exclusive(dev, "adg");
+ if (IS_ERR(rstc))
+ return dev_err_probe(dev, PTR_ERR(rstc),
+ "failed to get adg reset\n");
+
ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
- NULL, NULL, 0, 0);
+ NULL, rstc, 0, 0);
if (ret)
return ret;
--
2.25.1
^ permalink raw reply related
* [PATCh v3 08/14] ASoC: rsnd: Add SSI reset support for RZ/G3E platforms
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
Add SSI reset support for the Renesas RZ/G3E SoC, which differs from earlier
generations in several ways:
- The SSI block always operates in BUSIF mode; RZ/G3E does not implement
the SSITDR/SSIRDR registers used by R-Car Gen2/Gen3/Gen4 for direct SSI
DMA. Consequently, all audio data must pass through BUSIF.
- Each SSI instance has its own reset line, exposed using per-SSI names
such as "ssi0", "ssi1", etc., rather than a single shared reset.
To support these differences, rsnd_ssi_use_busif() always return 1 on
RZ/G3E, ensuring that the driver consistently selects the BUSIF DMA path.
While at it, update the reset acquisition logic to request the appropriate
per-SSI reset controller based on the SSI instance name.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2:
- Drop rsnd_dma_detach() from rsnd_ssi_common_remove() upon NULL pointer
dereference on R-Car Gen3/Gen4 (reported by Geert)
- Drop RSND_SSI_ALWAYS_BUSIF flag; use direct rsnd_is_rzg3e() check instead
sound/soc/renesas/rcar/ssi.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/sound/soc/renesas/rcar/ssi.c b/sound/soc/renesas/rcar/ssi.c
index c06cebb36170..c65435551283 100644
--- a/sound/soc/renesas/rcar/ssi.c
+++ b/sound/soc/renesas/rcar/ssi.c
@@ -1158,6 +1158,7 @@ int __rsnd_ssi_is_pin_sharing(struct rsnd_mod *mod)
int rsnd_ssi_probe(struct rsnd_priv *priv)
{
+ struct reset_control *rstc;
struct device_node *node;
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_mod_ops *ops;
@@ -1207,6 +1208,16 @@ int rsnd_ssi_probe(struct rsnd_priv *priv)
goto rsnd_ssi_probe_done;
}
+ /*
+ * RZ/G3E uses per-SSI reset controllers.
+ * R-Car platforms typically don't have SSI reset controls.
+ */
+ rstc = devm_reset_control_get_optional(dev, name);
+ if (IS_ERR(rstc)) {
+ ret = PTR_ERR(rstc);
+ goto rsnd_ssi_probe_done;
+ }
+
if (of_property_read_bool(np, "shared-pin"))
rsnd_flags_set(ssi, RSND_SSI_CLK_PIN_SHARE);
@@ -1225,7 +1236,7 @@ int rsnd_ssi_probe(struct rsnd_priv *priv)
ops = &rsnd_ssi_dma_ops;
ret = rsnd_mod_init(priv, rsnd_mod_get(ssi), ops, clk,
- NULL, RSND_MOD_SSI, i);
+ rstc, RSND_MOD_SSI, i);
if (ret)
goto rsnd_ssi_probe_done;
--
2.25.1
^ permalink raw reply related
* [PATCh v3 07/14] ASoC: rsnd: ssui: Add RZ/G3E SSIU BUSIF support
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
Add support for the SSIU found on the Renesas RZ/G3E SoC, which
provides a different BUSIF layout compared to earlier generations:
- SSI0-SSI4: 4 BUSIF instances each (BUSIF0-3)
- SSI5-SSI8: 1 BUSIF instance each (BUSIF0 only)
- SSI9: 4 BUSIF instances (BUSIF0-3)
- Total: 28 BUSIFs
RZ/G3E also differs from Gen2/Gen3 implementations in that only two
pairs of BUSIF error-status registers are available instead of four,
and the SSI always operates in BUSIF mode with no PIO fallback.
Rather than scattering SoC-specific checks across functional code,
introduce an extra capability flags in the match data:
- RSND_SSIU_BUSIF_STATUS_COUNT_2: only two BUSIF error-status
register pairs are present. Used in rsnd_ssiu_busif_err_irq_ctrl()
and rsnd_ssiu_busif_err_status_clear() to limit register iteration.
Future SoCs sharing these constraints can set the flags without
requiring code changes.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2:
- Droped RSND_SSI_ALWAYS_BUSIF flag; PIO is only enabled explicitly,
so no guard needed; use direct rsnd_is_rzg3e() check for skipping
SSI_MODE0 instead
sound/soc/renesas/rcar/core.c | 4 ++-
sound/soc/renesas/rcar/rsnd.h | 2 ++
sound/soc/renesas/rcar/ssiu.c | 47 +++++++++++++++++++++--------------
3 files changed, 34 insertions(+), 19 deletions(-)
diff --git a/sound/soc/renesas/rcar/core.c b/sound/soc/renesas/rcar/core.c
index 8d0c5440cb70..d85c614af598 100644
--- a/sound/soc/renesas/rcar/core.c
+++ b/sound/soc/renesas/rcar/core.c
@@ -107,7 +107,8 @@ static const struct of_device_id rsnd_of_match[] = {
{ .compatible = "renesas,rcar_sound-gen4", .data = (void *)RSND_GEN4 },
/* Special Handling */
{ .compatible = "renesas,rcar_sound-r8a77990", .data = (void *)(RSND_GEN3 | RSND_SOC_E) },
- { .compatible = "renesas,r9a09g047-sound", .data = (void *)(RSND_RZ3 | RSND_RZG3E) },
+ { .compatible = "renesas,r9a09g047-sound", .data = (void *)(RSND_RZ3 | RSND_RZG3E |
+ RSND_SSIU_BUSIF_STATUS_COUNT_2) },
{},
};
MODULE_DEVICE_TABLE(of, rsnd_of_match);
@@ -1960,6 +1961,7 @@ static int rsnd_probe(struct platform_device *pdev)
priv->pdev = pdev;
priv->flags = (unsigned long)of_device_get_match_data(dev);
+ priv->ssiu_busif_count = rsnd_flags_has(priv, RSND_SSIU_BUSIF_STATUS_COUNT_2) ? 2 : 4;
spin_lock_init(&priv->lock);
/*
diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h
index 4ff410a96336..5c5be0f64cb1 100644
--- a/sound/soc/renesas/rcar/rsnd.h
+++ b/sound/soc/renesas/rcar/rsnd.h
@@ -631,6 +631,7 @@ struct rsnd_priv {
struct reset_control *audmapp_rstc;
spinlock_t lock;
+ unsigned int ssiu_busif_count;
unsigned long flags;
#define RSND_GEN_MASK (0xF << 0)
#define RSND_GEN1 (1 << 0)
@@ -642,6 +643,7 @@ struct rsnd_priv {
#define RSND_RZ_MASK (0xFF << 8)
#define RSND_RZ3 (3 << 8)
#define RSND_RZG3E (1 << 12)
+#define RSND_SSIU_BUSIF_STATUS_COUNT_2 BIT(16) /* Only 2 BUSIF error-status register pairs */
/*
* below value will be filled on rsnd_gen_probe()
*/
diff --git a/sound/soc/renesas/rcar/ssiu.c b/sound/soc/renesas/rcar/ssiu.c
index 0cfa84fe5ea8..f377d9414633 100644
--- a/sound/soc/renesas/rcar/ssiu.c
+++ b/sound/soc/renesas/rcar/ssiu.c
@@ -29,31 +29,32 @@ struct rsnd_ssiu {
i++)
/*
- * SSI Gen2 Gen3 Gen4
- * 0 BUSIF0-3 BUSIF0-7 BUSIF0-7
- * 1 BUSIF0-3 BUSIF0-7
- * 2 BUSIF0-3 BUSIF0-7
- * 3 BUSIF0 BUSIF0-7
- * 4 BUSIF0 BUSIF0-7
- * 5 BUSIF0 BUSIF0
- * 6 BUSIF0 BUSIF0
- * 7 BUSIF0 BUSIF0
- * 8 BUSIF0 BUSIF0
- * 9 BUSIF0-3 BUSIF0-7
- * total 22 52 8
+ * SSI Gen2 Gen3 Gen4 RZ/G3E
+ * 0 BUSIF0-3 BUSIF0-7 BUSIF0-7 BUSIF0-3
+ * 1 BUSIF0-3 BUSIF0-7 BUSIF0-3
+ * 2 BUSIF0-3 BUSIF0-7 BUSIF0-3
+ * 3 BUSIF0 BUSIF0-7 BUSIF0-3
+ * 4 BUSIF0 BUSIF0-7 BUSIF0-3
+ * 5 BUSIF0 BUSIF0 BUSIF0
+ * 6 BUSIF0 BUSIF0 BUSIF0
+ * 7 BUSIF0 BUSIF0 BUSIF0
+ * 8 BUSIF0 BUSIF0 BUSIF0
+ * 9 BUSIF0-3 BUSIF0-7 BUSIF0-3
+ * total 22 52 8 28
*/
static const int gen2_id[] = { 0, 4, 8, 12, 13, 14, 15, 16, 17, 18 };
static const int gen3_id[] = { 0, 8, 16, 24, 32, 40, 41, 42, 43, 44 };
static const int gen4_id[] = { 0 };
+static const int rzg3e_id[] = { 0, 4, 8, 12, 16, 20, 21, 22, 23, 24 };
/* enable busif buffer over/under run interrupt. */
#define rsnd_ssiu_busif_err_irq_enable(mod) rsnd_ssiu_busif_err_irq_ctrl(mod, 1)
#define rsnd_ssiu_busif_err_irq_disable(mod) rsnd_ssiu_busif_err_irq_ctrl(mod, 0)
static void rsnd_ssiu_busif_err_irq_ctrl(struct rsnd_mod *mod, int enable)
{
+ struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
int id = rsnd_mod_id(mod);
int shift, offset;
- int i;
switch (id) {
case 0:
@@ -72,7 +73,7 @@ static void rsnd_ssiu_busif_err_irq_ctrl(struct rsnd_mod *mod, int enable)
return;
}
- for (i = 0; i < 4; i++) {
+ for (unsigned int i = 0; i < priv->ssiu_busif_count; i++) {
enum rsnd_reg reg = SSI_SYS_INT_ENABLE((i * 2) + offset);
u32 val = 0xf << (shift * 4);
u32 sys_int_enable = rsnd_mod_read(mod, reg);
@@ -87,10 +88,10 @@ static void rsnd_ssiu_busif_err_irq_ctrl(struct rsnd_mod *mod, int enable)
bool rsnd_ssiu_busif_err_status_clear(struct rsnd_mod *mod)
{
+ struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
bool error = false;
int id = rsnd_mod_id(mod);
int shift, offset;
- int i;
switch (id) {
case 0:
@@ -109,7 +110,7 @@ bool rsnd_ssiu_busif_err_status_clear(struct rsnd_mod *mod)
goto out;
}
- for (i = 0; i < 4; i++) {
+ for (unsigned int i = 0; i < priv->ssiu_busif_count; i++) {
u32 reg = SSI_SYS_STATUS(i * 2) + offset;
u32 status = rsnd_mod_read(mod, reg);
u32 val = 0xf << (shift * 4);
@@ -160,7 +161,8 @@ static int rsnd_ssiu_init(struct rsnd_mod *mod,
/*
* SSI_MODE0
*/
- rsnd_mod_bset(mod, SSI_MODE0, (1 << id), !use_busif << id);
+ if (!rsnd_is_rzg3e(priv))
+ rsnd_mod_bset(mod, SSI_MODE0, (1 << id), !use_busif << id);
/*
* SSI_MODE1 / SSI_MODE2
@@ -510,6 +512,7 @@ int rsnd_ssiu_probe(struct rsnd_priv *priv)
{
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *node __free(device_node) = rsnd_ssiu_of_node(priv);
+ struct reset_control *rstc;
struct rsnd_ssiu *ssiu;
struct rsnd_mod_ops *ops;
const int *list = NULL;
@@ -558,12 +561,20 @@ int rsnd_ssiu_probe(struct rsnd_priv *priv)
} else if (rsnd_is_gen4(priv)) {
list = gen4_id;
nr = ARRAY_SIZE(gen4_id);
+ } else if (rsnd_is_rzg3e(priv)) {
+ list = rzg3e_id;
+ nr = ARRAY_SIZE(rzg3e_id);
} else {
dev_err(dev, "unknown SSIU\n");
return -ENODEV;
}
}
+ /* Acquire shared reset once for all SSIU modules */
+ rstc = devm_reset_control_get_optional_shared(dev, "ssi-all");
+ if (IS_ERR(rstc))
+ rstc = NULL;
+
for_each_rsnd_ssiu(ssiu, priv, i) {
int ret;
@@ -586,7 +597,7 @@ int rsnd_ssiu_probe(struct rsnd_priv *priv)
}
ret = rsnd_mod_init(priv, rsnd_mod_get(ssiu),
- ops, NULL, NULL, RSND_MOD_SSIU, i);
+ ops, NULL, rstc, RSND_MOD_SSIU, i);
if (ret)
return ret;
}
--
2.25.1
^ permalink raw reply related
* [PATCh v3 06/14] ASoC: rsnd: Add RZ/G3E DMA address calculation support
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
RZ/G3E has different DMA register base addresses and offset
calculations compared to R-Car platforms.
Add dedicated rsnd_rzg3e_dma_addr() function with dispatch from
rsnd_dma_addr(), following the existing per-generation pattern.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2:
- Split into separate patches: one for DMA address support, one for
audmac-pp clock/reset management
- Replace ternary macro wrappers with dedicated rsnd_rzg3e_dma_addr()
function dispatched from rsnd_dma_addr(), following existing
rsnd_gen4_dma_addr() pattern
sound/soc/renesas/rcar/dma.c | 137 +++++++++++++++++++++++++++++------
1 file changed, 113 insertions(+), 24 deletions(-)
diff --git a/sound/soc/renesas/rcar/dma.c b/sound/soc/renesas/rcar/dma.c
index 0afe4636b005..5b63206361ef 100644
--- a/sound/soc/renesas/rcar/dma.c
+++ b/sound/soc/renesas/rcar/dma.c
@@ -496,7 +496,35 @@ static struct rsnd_mod_ops rsnd_dmapp_ops = {
* SSIU: 0xec541000 / 0xec100000 / 0xec100000 / 0xec400000 / 0xec400000
* SCU : 0xec500000 / 0xec000000 / 0xec004000 / 0xec300000 / 0xec304000
* CMD : 0xec500000 / / 0xec008000 0xec308000
+ *
+ * ex) G3E case
+ * mod / DMAC in / DMAC out / DMAC PP in / DMAC pp out
+ * SSI : 0x13C31000 / 0x13C40000 / 0x13C40000
+ * SSIU: 0x13C31000 / 0x13C40000 / 0x13C40000 / 0xEC400000 / 0xEC400000
+ * SCU : 0x13C00000 / 0x13C10000 / 0x13C14000 / 0xEC300000 / 0xEC304000
+ * CMD : 0x13C00000 / / 0x13C18000 0xEC308000
*/
+
+/* RZ/G3E DMA address macros */
+#define RDMA_SSI_I_N_G3E(addr, i) (addr ##_reg + 0x0000F000 + (0x1000 * i))
+#define RDMA_SSI_O_N_G3E(addr, i) (addr ##_reg + 0x0000F000 + (0x1000 * i))
+
+#define RDMA_SSIU_I_N_G3E(addr, i, j) (addr ##_reg + 0x0000F000 + (0x1000 * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) * ((j) / 4)))
+#define RDMA_SSIU_O_N_G3E(addr, i, j) RDMA_SSIU_I_N_G3E(addr, i, j)
+
+#define RDMA_SSIU_I_P_G3E(addr, i, j) (addr ##_reg + 0xD87CF000 + (0x1000 * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) * ((j) / 4)))
+#define RDMA_SSIU_O_P_G3E(addr, i, j) RDMA_SSIU_I_P_G3E(addr, i, j)
+
+#define RDMA_SRC_I_N_G3E(addr, i) (addr ##_reg + 0x00010000 + (0x400 * i))
+#define RDMA_SRC_O_N_G3E(addr, i) (addr ##_reg + 0x00014000 + (0x400 * i))
+
+#define RDMA_SRC_I_P_G3E(addr, i) (addr ##_reg + 0xD8700000 + (0x400 * i))
+#define RDMA_SRC_O_P_G3E(addr, i) (addr ##_reg + 0xD8704000 + (0x400 * i))
+
+#define RDMA_CMD_O_N_G3E(addr, i) (addr ##_reg + 0x00018000 + (0x400 * i))
+#define RDMA_CMD_O_P_G3E(addr, i) (addr ##_reg + 0xD8708000 + (0x400 * i))
+
+/* R-Car DMA address macros */
#define RDMA_SSI_I_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0x8)
#define RDMA_SSI_O_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0xc)
@@ -515,15 +543,18 @@ static struct rsnd_mod_ops rsnd_dmapp_ops = {
#define RDMA_CMD_O_N(addr, i) (addr ##_reg - 0x004f8000 + (0x400 * i))
#define RDMA_CMD_O_P(addr, i) (addr ##_reg - 0x001f8000 + (0x400 * i))
+struct rsnd_dma_addr {
+ dma_addr_t out_addr;
+ dma_addr_t in_addr;
+};
+
static dma_addr_t
-rsnd_gen2_dma_addr(struct rsnd_dai_stream *io,
- struct rsnd_mod *mod,
- int is_play, int is_from)
+rsnd_dma_addr_lookup(struct rsnd_dai_stream *io,
+ struct rsnd_mod *mod,
+ const struct rsnd_dma_addr tbl[3][2][3],
+ int is_play, int is_from)
{
- struct rsnd_priv *priv = rsnd_io_to_priv(io);
- struct device *dev = rsnd_priv_to_dev(priv);
- phys_addr_t ssi_reg = rsnd_gen_get_phy_addr(priv, RSND_BASE_SSI);
- phys_addr_t src_reg = rsnd_gen_get_phy_addr(priv, RSND_BASE_SCU);
+ struct device *dev = rsnd_priv_to_dev(rsnd_io_to_priv(io));
int is_ssi = !!(rsnd_io_to_mod_ssi(io) == mod) ||
!!(rsnd_io_to_mod_ssiu(io) == mod);
int use_src = !!rsnd_io_to_mod_src(io);
@@ -531,11 +562,77 @@ rsnd_gen2_dma_addr(struct rsnd_dai_stream *io,
!!rsnd_io_to_mod_mix(io) ||
!!rsnd_io_to_mod_ctu(io);
int id = rsnd_mod_id(mod);
+
+ /* it shouldn't happen */
+ if (use_cmd && !use_src)
+ dev_err(dev, "DVC is selected without SRC\n");
+
+ /* use SSIU or SSI? */
+ if (is_ssi && rsnd_ssi_use_busif(io))
+ is_ssi++;
+
+ dev_dbg(dev, "dma%d addr : is_ssi=%d use_src=%d use_cmd=%d\n",
+ id, is_ssi, use_src, use_cmd);
+
+ return is_from ?
+ tbl[is_ssi][is_play][use_src + use_cmd].out_addr :
+ tbl[is_ssi][is_play][use_src + use_cmd].in_addr;
+}
+
+static dma_addr_t
+rsnd_rzg3e_dma_addr(struct rsnd_dai_stream *io,
+ struct rsnd_mod *mod, int is_play, int is_from)
+{
+ struct rsnd_priv *priv = rsnd_io_to_priv(io);
+ phys_addr_t ssi_reg = rsnd_gen_get_phy_addr(priv, RSND_BASE_SSI);
+ phys_addr_t src_reg = rsnd_gen_get_phy_addr(priv, RSND_BASE_SCU);
+ int id = rsnd_mod_id(mod);
int busif = rsnd_mod_id_sub(rsnd_io_to_mod_ssiu(io));
- struct dma_addr {
- dma_addr_t out_addr;
- dma_addr_t in_addr;
- } dma_addrs[3][2][3] = {
+ const struct rsnd_dma_addr tbl[3][2][3] = {
+ /* SRC */
+ /* Capture */
+ {{{ 0, 0, },
+ { RDMA_SRC_O_N_G3E(src, id), RDMA_SRC_I_P_G3E(src, id) },
+ { RDMA_CMD_O_N_G3E(src, id), RDMA_SRC_I_P_G3E(src, id) } },
+ /* Playback */
+ {{ 0, 0 },
+ { RDMA_SRC_O_P_G3E(src, id), RDMA_SRC_I_N_G3E(src, id) },
+ { RDMA_CMD_O_P_G3E(src, id), RDMA_SRC_I_N_G3E(src, id) } }
+ },
+ /* SSI */
+ /* Capture */
+ {{{ RDMA_SSI_O_N_G3E(ssi, id), 0 },
+ { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 },
+ { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 } },
+ /* Playback */
+ {{ 0, RDMA_SSI_I_N_G3E(ssi, id) },
+ { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) },
+ { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) } }
+ },
+ /* SSIU */
+ /* Capture */
+ {{{ RDMA_SSIU_O_N_G3E(ssi, id, busif), 0 },
+ { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 },
+ { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 } },
+ /* Playback */
+ {{ 0, RDMA_SSIU_I_N_G3E(ssi, id, busif) },
+ { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) },
+ { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) } } },
+ };
+
+ return rsnd_dma_addr_lookup(io, mod, tbl, is_play, is_from);
+}
+
+static dma_addr_t
+rsnd_gen2_dma_addr(struct rsnd_dai_stream *io,
+ struct rsnd_mod *mod, int is_play, int is_from)
+{
+ struct rsnd_priv *priv = rsnd_io_to_priv(io);
+ phys_addr_t ssi_reg = rsnd_gen_get_phy_addr(priv, RSND_BASE_SSI);
+ phys_addr_t src_reg = rsnd_gen_get_phy_addr(priv, RSND_BASE_SCU);
+ int id = rsnd_mod_id(mod);
+ int busif = rsnd_mod_id_sub(rsnd_io_to_mod_ssiu(io));
+ const struct rsnd_dma_addr tbl[3][2][3] = {
/* SRC */
/* Capture */
{{{ 0, 0 },
@@ -574,20 +671,10 @@ rsnd_gen2_dma_addr(struct rsnd_dai_stream *io,
* out of calculation rule
*/
if ((id == 9) && (busif >= 4))
- dev_err(dev, "This driver doesn't support SSI%d-%d, so far",
- id, busif);
-
- /* it shouldn't happen */
- if (use_cmd && !use_src)
- dev_err(dev, "DVC is selected without SRC\n");
-
- /* use SSIU or SSI ? */
- if (is_ssi && rsnd_ssi_use_busif(io))
- is_ssi++;
+ dev_err(rsnd_priv_to_dev(priv),
+ "This driver doesn't support SSI%d-%d, so far", id, busif);
- return (is_from) ?
- dma_addrs[is_ssi][is_play][use_src + use_cmd].out_addr :
- dma_addrs[is_ssi][is_play][use_src + use_cmd].in_addr;
+ return rsnd_dma_addr_lookup(io, mod, tbl, is_play, is_from);
}
/*
@@ -636,6 +723,8 @@ static dma_addr_t rsnd_dma_addr(struct rsnd_dai_stream *io,
return 0;
else if (rsnd_is_gen4(priv))
return rsnd_gen4_dma_addr(io, mod, is_play, is_from);
+ else if (rsnd_is_rzg3e(priv))
+ return rsnd_rzg3e_dma_addr(io, mod, is_play, is_from);
else
return rsnd_gen2_dma_addr(io, mod, is_play, is_from);
}
--
2.25.1
^ permalink raw reply related
* [PATCh v3 05/14] ASoC: rsnd: Add audmacpp clock and reset support for RZ/G3E
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
RZ/G3E requires additional audmapp clock and reset lines for
Audio DMA-PP operation.
Add global audmacpp clock/reset management in rsnd_dma_probe()
using optional APIs to remain transparent to other platforms.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2: New patch
sound/soc/renesas/rcar/dma.c | 14 ++++++++++++++
sound/soc/renesas/rcar/rsnd.h | 7 +++++++
2 files changed, 21 insertions(+)
diff --git a/sound/soc/renesas/rcar/dma.c b/sound/soc/renesas/rcar/dma.c
index 68c859897e68..0afe4636b005 100644
--- a/sound/soc/renesas/rcar/dma.c
+++ b/sound/soc/renesas/rcar/dma.c
@@ -864,6 +864,20 @@ int rsnd_dma_probe(struct rsnd_priv *priv)
if (rsnd_is_gen4(priv))
goto audmapp_end;
+ /* for RZ/G3E */
+ priv->audmapp_rstc =
+ devm_reset_control_get_optional_exclusive_deasserted(dev, "audmapp");
+ if (IS_ERR(priv->audmapp_rstc)) {
+ return dev_err_probe(dev, PTR_ERR(priv->audmapp_rstc),
+ "failed to get audmapp reset\n");
+ }
+
+ priv->audmapp_clk = devm_clk_get_optional_enabled(dev, "audmapp");
+ if (IS_ERR(priv->audmapp_clk)) {
+ return dev_err_probe(dev, PTR_ERR(priv->audmapp_clk),
+ "failed to get audmapp clock\n");
+ }
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audmapp");
if (!res) {
dev_err(dev, "lack of audmapp in DT\n");
diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h
index 7c5eb575209c..4ff410a96336 100644
--- a/sound/soc/renesas/rcar/rsnd.h
+++ b/sound/soc/renesas/rcar/rsnd.h
@@ -623,6 +623,13 @@ void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m);
struct rsnd_priv {
struct platform_device *pdev;
+
+ /*
+ * below value will be filled on rsnd_dma_probe()
+ */
+ struct clk *audmapp_clk;
+ struct reset_control *audmapp_rstc;
+
spinlock_t lock;
unsigned long flags;
#define RSND_GEN_MASK (0xF << 0)
--
2.25.1
^ permalink raw reply related
* [PATCh v3 04/14] ASoC: rsnd: Add RZ/G3E SoC probing and register map
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
RZ/G3E audio subsystem has a different register layout compared to
R-Car Gen2/Gen3/Gen4, as described below:
- Different base address organization (SCU, ADG, SSIU, SSI as
separate regions accessed by name)
- Additional registers: AUDIO_CLK_SEL3, SSI_MODE3, SSI_CONTROL2
- Different register offsets within each region
Add RZ/G3E SoC's audio subsystem register layouts and probe support.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2:
- Reuse existing RSND_BASE_xxx defines instead of RZ/G3E-specific ones;
- Fix ADG regmap init region count and collapse to single-line calls.
- Move RSND_RZG3E flag to separate bit range (xx << 8/12) to reserve
(x << 0) for future R-Car Gen5, using Morimoto-san's RSND_RZ_MASK scheme.
sound/soc/renesas/rcar/core.c | 1 +
sound/soc/renesas/rcar/gen.c | 180 ++++++++++++++++++++++++++++++++++
sound/soc/renesas/rcar/rsnd.h | 8 +-
3 files changed, 188 insertions(+), 1 deletion(-)
diff --git a/sound/soc/renesas/rcar/core.c b/sound/soc/renesas/rcar/core.c
index 6de576736507..8d0c5440cb70 100644
--- a/sound/soc/renesas/rcar/core.c
+++ b/sound/soc/renesas/rcar/core.c
@@ -107,6 +107,7 @@ static const struct of_device_id rsnd_of_match[] = {
{ .compatible = "renesas,rcar_sound-gen4", .data = (void *)RSND_GEN4 },
/* Special Handling */
{ .compatible = "renesas,rcar_sound-r8a77990", .data = (void *)(RSND_GEN3 | RSND_SOC_E) },
+ { .compatible = "renesas,r9a09g047-sound", .data = (void *)(RSND_RZ3 | RSND_RZG3E) },
{},
};
MODULE_DEVICE_TABLE(of, rsnd_of_match);
diff --git a/sound/soc/renesas/rcar/gen.c b/sound/soc/renesas/rcar/gen.c
index d1f20cde66be..05d5f656fb01 100644
--- a/sound/soc/renesas/rcar/gen.c
+++ b/sound/soc/renesas/rcar/gen.c
@@ -464,6 +464,184 @@ static int rsnd_gen1_probe(struct rsnd_priv *priv)
return ret_adg | ret_ssi;
}
+/*
+ * RZ/G3E Generation
+ */
+static int rsnd_rzg3e_probe(struct rsnd_priv *priv)
+{
+ static const struct rsnd_regmap_field_conf conf_ssiu[] = {
+ RSND_GEN_S_REG(SSI_MODE1, 0x804),
+ RSND_GEN_S_REG(SSI_MODE2, 0x808),
+ RSND_GEN_S_REG(SSI_MODE3, 0x80c),
+ RSND_GEN_S_REG(SSI_CONTROL, 0x810),
+ RSND_GEN_S_REG(SSI_CONTROL2, 0x814),
+ RSND_GEN_S_REG(SSI_SYS_STATUS0, 0x840),
+ RSND_GEN_S_REG(SSI_SYS_STATUS1, 0x844),
+ RSND_GEN_S_REG(SSI_SYS_STATUS2, 0x848),
+ RSND_GEN_S_REG(SSI_SYS_STATUS3, 0x84c),
+ RSND_GEN_S_REG(SSI_SYS_INT_ENABLE0, 0x850),
+ RSND_GEN_S_REG(SSI_SYS_INT_ENABLE1, 0x854),
+ RSND_GEN_S_REG(SSI_SYS_INT_ENABLE2, 0x858),
+ RSND_GEN_S_REG(SSI_SYS_INT_ENABLE3, 0x85c),
+ RSND_GEN_M_REG(SSI_BUSIF0_MODE, 0x0, 0x80),
+ RSND_GEN_M_REG(SSI_BUSIF0_ADINR, 0x4, 0x80),
+ RSND_GEN_M_REG(SSI_BUSIF0_DALIGN, 0x8, 0x80),
+ RSND_GEN_M_REG(SSI_BUSIF1_MODE, 0x20, 0x80),
+ RSND_GEN_M_REG(SSI_BUSIF1_ADINR, 0x24, 0x80),
+ RSND_GEN_M_REG(SSI_BUSIF1_DALIGN, 0x28, 0x80),
+ RSND_GEN_M_REG(SSI_BUSIF2_MODE, 0x40, 0x80),
+ RSND_GEN_M_REG(SSI_BUSIF2_ADINR, 0x44, 0x80),
+ RSND_GEN_M_REG(SSI_BUSIF2_DALIGN, 0x48, 0x80),
+ RSND_GEN_M_REG(SSI_BUSIF3_MODE, 0x60, 0x80),
+ RSND_GEN_M_REG(SSI_BUSIF3_ADINR, 0x64, 0x80),
+ RSND_GEN_M_REG(SSI_BUSIF3_DALIGN, 0x68, 0x80),
+ RSND_GEN_M_REG(SSI_MODE, 0xc, 0x80),
+ RSND_GEN_M_REG(SSI_CTRL, 0x10, 0x80),
+ RSND_GEN_M_REG(SSI_INT_ENABLE, 0x18, 0x80),
+ RSND_GEN_S_REG(SSI9_BUSIF0_MODE, 0x480),
+ RSND_GEN_S_REG(SSI9_BUSIF0_ADINR, 0x484),
+ RSND_GEN_S_REG(SSI9_BUSIF0_DALIGN, 0x488),
+ RSND_GEN_S_REG(SSI9_BUSIF1_MODE, 0x4a0),
+ RSND_GEN_S_REG(SSI9_BUSIF1_ADINR, 0x4a4),
+ RSND_GEN_S_REG(SSI9_BUSIF1_DALIGN, 0x4a8),
+ RSND_GEN_S_REG(SSI9_BUSIF2_MODE, 0x4c0),
+ RSND_GEN_S_REG(SSI9_BUSIF2_ADINR, 0x4c4),
+ RSND_GEN_S_REG(SSI9_BUSIF2_DALIGN, 0x4c8),
+ RSND_GEN_S_REG(SSI9_BUSIF3_MODE, 0x4e0),
+ RSND_GEN_S_REG(SSI9_BUSIF3_ADINR, 0x4e4),
+ RSND_GEN_S_REG(SSI9_BUSIF3_DALIGN, 0x4e8),
+ };
+ static const struct rsnd_regmap_field_conf conf_scu[] = {
+ RSND_GEN_M_REG(SRC_I_BUSIF_MODE, 0x0, 0x20),
+ RSND_GEN_M_REG(SRC_O_BUSIF_MODE, 0x4, 0x20),
+ RSND_GEN_M_REG(SRC_BUSIF_DALIGN, 0x8, 0x20),
+ RSND_GEN_M_REG(SRC_ROUTE_MODE0, 0xc, 0x20),
+ RSND_GEN_M_REG(SRC_CTRL, 0x10, 0x20),
+ RSND_GEN_M_REG(SRC_INT_ENABLE0, 0x18, 0x20),
+ RSND_GEN_M_REG(CMD_BUSIF_MODE, 0x184, 0x20),
+ RSND_GEN_M_REG(CMD_BUSIF_DALIGN, 0x188, 0x20),
+ RSND_GEN_M_REG(CMD_ROUTE_SLCT, 0x18c, 0x20),
+ RSND_GEN_M_REG(CMD_CTRL, 0x190, 0x20),
+ RSND_GEN_S_REG(SCU_SYS_STATUS0, 0x1c8),
+ RSND_GEN_S_REG(SCU_SYS_INT_EN0, 0x1cc),
+ RSND_GEN_S_REG(SCU_SYS_STATUS1, 0x1d0),
+ RSND_GEN_S_REG(SCU_SYS_INT_EN1, 0x1d4),
+ RSND_GEN_M_REG(SRC_SWRSR, 0x200, 0x40),
+ RSND_GEN_M_REG(SRC_SRCIR, 0x204, 0x40),
+ RSND_GEN_M_REG(SRC_ADINR, 0x214, 0x40),
+ RSND_GEN_M_REG(SRC_IFSCR, 0x21c, 0x40),
+ RSND_GEN_M_REG(SRC_IFSVR, 0x220, 0x40),
+ RSND_GEN_M_REG(SRC_SRCCR, 0x224, 0x40),
+ RSND_GEN_M_REG(SRC_BSDSR, 0x22c, 0x40),
+ RSND_GEN_M_REG(SRC_BSISR, 0x238, 0x40),
+ RSND_GEN_M_REG(CTU_SWRSR, 0x500, 0x100),
+ RSND_GEN_M_REG(CTU_CTUIR, 0x504, 0x100),
+ RSND_GEN_M_REG(CTU_ADINR, 0x508, 0x100),
+ RSND_GEN_M_REG(CTU_CPMDR, 0x510, 0x100),
+ RSND_GEN_M_REG(CTU_SCMDR, 0x514, 0x100),
+ RSND_GEN_M_REG(CTU_SV00R, 0x518, 0x100),
+ RSND_GEN_M_REG(CTU_SV01R, 0x51c, 0x100),
+ RSND_GEN_M_REG(CTU_SV02R, 0x520, 0x100),
+ RSND_GEN_M_REG(CTU_SV03R, 0x524, 0x100),
+ RSND_GEN_M_REG(CTU_SV04R, 0x528, 0x100),
+ RSND_GEN_M_REG(CTU_SV05R, 0x52c, 0x100),
+ RSND_GEN_M_REG(CTU_SV06R, 0x530, 0x100),
+ RSND_GEN_M_REG(CTU_SV07R, 0x534, 0x100),
+ RSND_GEN_M_REG(CTU_SV10R, 0x538, 0x100),
+ RSND_GEN_M_REG(CTU_SV11R, 0x53c, 0x100),
+ RSND_GEN_M_REG(CTU_SV12R, 0x540, 0x100),
+ RSND_GEN_M_REG(CTU_SV13R, 0x544, 0x100),
+ RSND_GEN_M_REG(CTU_SV14R, 0x548, 0x100),
+ RSND_GEN_M_REG(CTU_SV15R, 0x54c, 0x100),
+ RSND_GEN_M_REG(CTU_SV16R, 0x550, 0x100),
+ RSND_GEN_M_REG(CTU_SV17R, 0x554, 0x100),
+ RSND_GEN_M_REG(CTU_SV20R, 0x558, 0x100),
+ RSND_GEN_M_REG(CTU_SV21R, 0x55c, 0x100),
+ RSND_GEN_M_REG(CTU_SV22R, 0x560, 0x100),
+ RSND_GEN_M_REG(CTU_SV23R, 0x564, 0x100),
+ RSND_GEN_M_REG(CTU_SV24R, 0x568, 0x100),
+ RSND_GEN_M_REG(CTU_SV25R, 0x56c, 0x100),
+ RSND_GEN_M_REG(CTU_SV26R, 0x570, 0x100),
+ RSND_GEN_M_REG(CTU_SV27R, 0x574, 0x100),
+ RSND_GEN_M_REG(CTU_SV30R, 0x578, 0x100),
+ RSND_GEN_M_REG(CTU_SV31R, 0x57c, 0x100),
+ RSND_GEN_M_REG(CTU_SV32R, 0x580, 0x100),
+ RSND_GEN_M_REG(CTU_SV33R, 0x584, 0x100),
+ RSND_GEN_M_REG(CTU_SV34R, 0x588, 0x100),
+ RSND_GEN_M_REG(CTU_SV35R, 0x58c, 0x100),
+ RSND_GEN_M_REG(CTU_SV36R, 0x590, 0x100),
+ RSND_GEN_M_REG(CTU_SV37R, 0x594, 0x100),
+ RSND_GEN_M_REG(MIX_SWRSR, 0xd00, 0x40),
+ RSND_GEN_M_REG(MIX_MIXIR, 0xd04, 0x40),
+ RSND_GEN_M_REG(MIX_ADINR, 0xd08, 0x40),
+ RSND_GEN_M_REG(MIX_MIXMR, 0xd10, 0x40),
+ RSND_GEN_M_REG(MIX_MVPDR, 0xd14, 0x40),
+ RSND_GEN_M_REG(MIX_MDBAR, 0xd18, 0x40),
+ RSND_GEN_M_REG(MIX_MDBBR, 0xd1c, 0x40),
+ RSND_GEN_M_REG(MIX_MDBCR, 0xd20, 0x40),
+ RSND_GEN_M_REG(MIX_MDBDR, 0xd24, 0x40),
+ RSND_GEN_M_REG(MIX_MDBER, 0xd28, 0x40),
+ RSND_GEN_M_REG(DVC_SWRSR, 0xe00, 0x100),
+ RSND_GEN_M_REG(DVC_DVUIR, 0xe04, 0x100),
+ RSND_GEN_M_REG(DVC_ADINR, 0xe08, 0x100),
+ RSND_GEN_M_REG(DVC_DVUCR, 0xe10, 0x100),
+ RSND_GEN_M_REG(DVC_ZCMCR, 0xe14, 0x100),
+ RSND_GEN_M_REG(DVC_VRCTR, 0xe18, 0x100),
+ RSND_GEN_M_REG(DVC_VRPDR, 0xe1c, 0x100),
+ RSND_GEN_M_REG(DVC_VRDBR, 0xe20, 0x100),
+ RSND_GEN_M_REG(DVC_VOL0R, 0xe28, 0x100),
+ RSND_GEN_M_REG(DVC_VOL1R, 0xe2c, 0x100),
+ RSND_GEN_M_REG(DVC_VOL2R, 0xe30, 0x100),
+ RSND_GEN_M_REG(DVC_VOL3R, 0xe34, 0x100),
+ RSND_GEN_M_REG(DVC_VOL4R, 0xe38, 0x100),
+ RSND_GEN_M_REG(DVC_VOL5R, 0xe3c, 0x100),
+ RSND_GEN_M_REG(DVC_VOL6R, 0xe40, 0x100),
+ RSND_GEN_M_REG(DVC_VOL7R, 0xe44, 0x100),
+ RSND_GEN_M_REG(DVC_DVUER, 0xe48, 0x100),
+ };
+ static const struct rsnd_regmap_field_conf conf_adg[] = {
+ RSND_GEN_S_REG(BRRA, 0x00),
+ RSND_GEN_S_REG(BRRB, 0x04),
+ RSND_GEN_S_REG(BRGCKR, 0x08),
+ RSND_GEN_S_REG(AUDIO_CLK_SEL0, 0x0c),
+ RSND_GEN_S_REG(AUDIO_CLK_SEL1, 0x10),
+ RSND_GEN_S_REG(AUDIO_CLK_SEL2, 0x14),
+ RSND_GEN_S_REG(AUDIO_CLK_SEL3, 0x18),
+ RSND_GEN_S_REG(DIV_EN, 0x30),
+ RSND_GEN_S_REG(SRCIN_TIMSEL0, 0x34),
+ RSND_GEN_S_REG(SRCIN_TIMSEL1, 0x38),
+ RSND_GEN_S_REG(SRCIN_TIMSEL2, 0x3c),
+ RSND_GEN_S_REG(SRCIN_TIMSEL3, 0x40),
+ RSND_GEN_S_REG(SRCIN_TIMSEL4, 0x44),
+ RSND_GEN_S_REG(SRCOUT_TIMSEL0, 0x48),
+ RSND_GEN_S_REG(SRCOUT_TIMSEL1, 0x4c),
+ RSND_GEN_S_REG(SRCOUT_TIMSEL2, 0x50),
+ RSND_GEN_S_REG(SRCOUT_TIMSEL3, 0x54),
+ RSND_GEN_S_REG(SRCOUT_TIMSEL4, 0x58),
+ RSND_GEN_S_REG(CMDOUT_TIMSEL, 0x5c),
+ };
+ static const struct rsnd_regmap_field_conf conf_ssi[] = {
+ RSND_GEN_M_REG(SSICR, 0x00, 0x40),
+ RSND_GEN_M_REG(SSISR, 0x04, 0x40),
+ RSND_GEN_M_REG(SSIWSR, 0x20, 0x40),
+ };
+ int ret;
+
+ ret = rsnd_gen_regmap_init(priv, 10, RSND_BASE_SCU, "scu", conf_scu);
+ if (ret < 0)
+ return ret;
+
+ ret = rsnd_gen_regmap_init(priv, 1, RSND_BASE_ADG, "adg", conf_adg);
+ if (ret < 0)
+ return ret;
+
+ ret = rsnd_gen_regmap_init(priv, 10, RSND_BASE_SSIU, "ssiu", conf_ssiu);
+ if (ret < 0)
+ return ret;
+
+ return rsnd_gen_regmap_init(priv, 10, RSND_BASE_SSI, "ssi", conf_ssi);
+}
+
/*
* Gen
*/
@@ -487,6 +665,8 @@ int rsnd_gen_probe(struct rsnd_priv *priv)
ret = rsnd_gen2_probe(priv);
else if (rsnd_is_gen4(priv))
ret = rsnd_gen4_probe(priv);
+ else if (rsnd_is_rzg3e(priv))
+ ret = rsnd_rzg3e_probe(priv);
if (ret < 0)
dev_err(dev, "unknown generation R-Car sound device\n");
diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h
index cd7e7df62298..7c5eb575209c 100644
--- a/sound/soc/renesas/rcar/rsnd.h
+++ b/sound/soc/renesas/rcar/rsnd.h
@@ -143,13 +143,16 @@ enum rsnd_reg {
AUDIO_CLK_SEL0,
AUDIO_CLK_SEL1,
AUDIO_CLK_SEL2,
+ AUDIO_CLK_SEL3,
/* SSIU */
SSI_MODE,
SSI_MODE0,
SSI_MODE1,
SSI_MODE2,
+ SSI_MODE3,
SSI_CONTROL,
+ SSI_CONTROL2,
SSI_CTRL,
SSI_BUSIF0_MODE,
SSI_BUSIF1_MODE,
@@ -629,7 +632,9 @@ struct rsnd_priv {
#define RSND_GEN4 (4 << 0)
#define RSND_SOC_MASK (0xFF << 4)
#define RSND_SOC_E (1 << 4) /* E1/E2/E3 */
-
+#define RSND_RZ_MASK (0xFF << 8)
+#define RSND_RZ3 (3 << 8)
+#define RSND_RZG3E (1 << 12)
/*
* below value will be filled on rsnd_gen_probe()
*/
@@ -708,6 +713,7 @@ struct rsnd_priv {
#define rsnd_is_gen3_e3(priv) (((priv)->flags & \
(RSND_GEN_MASK | RSND_SOC_MASK)) == \
(RSND_GEN3 | RSND_SOC_E))
+#define rsnd_is_rzg3e(priv) (((priv)->flags & RSND_RZ_MASK) == (RSND_RZ3 | RSND_RZG3E))
#define rsnd_flags_has(p, f) ((p)->flags & (f))
#define rsnd_flags_set(p, f) ((p)->flags |= (f))
--
2.25.1
^ permalink raw reply related
* [PATCh v3 03/14] ASoC: rsnd: Add reset controller support to rsnd_mod
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
The RZ/G3E SoC requires per-module reset control for the audio subsystem.
Add reset controller support to struct rsnd_mod and update rsnd_mod_init()
to accept and handle a reset_control parameter.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2: No changes
sound/soc/renesas/rcar/adg.c | 2 +-
sound/soc/renesas/rcar/cmd.c | 2 +-
sound/soc/renesas/rcar/core.c | 14 +++++++++++++-
sound/soc/renesas/rcar/ctu.c | 2 +-
sound/soc/renesas/rcar/dma.c | 4 ++--
sound/soc/renesas/rcar/dvc.c | 2 +-
sound/soc/renesas/rcar/mix.c | 2 +-
sound/soc/renesas/rcar/rsnd.h | 3 +++
sound/soc/renesas/rcar/src.c | 2 +-
sound/soc/renesas/rcar/ssi.c | 2 +-
sound/soc/renesas/rcar/ssiu.c | 2 +-
11 files changed, 26 insertions(+), 11 deletions(-)
diff --git a/sound/soc/renesas/rcar/adg.c b/sound/soc/renesas/rcar/adg.c
index 8641b73d1f77..0105c60a144e 100644
--- a/sound/soc/renesas/rcar/adg.c
+++ b/sound/soc/renesas/rcar/adg.c
@@ -780,7 +780,7 @@ int rsnd_adg_probe(struct rsnd_priv *priv)
return -ENOMEM;
ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
- NULL, 0, 0);
+ NULL, NULL, 0, 0);
if (ret)
return ret;
diff --git a/sound/soc/renesas/rcar/cmd.c b/sound/soc/renesas/rcar/cmd.c
index 8d9a1e345a22..13beef389797 100644
--- a/sound/soc/renesas/rcar/cmd.c
+++ b/sound/soc/renesas/rcar/cmd.c
@@ -171,7 +171,7 @@ int rsnd_cmd_probe(struct rsnd_priv *priv)
for_each_rsnd_cmd(cmd, priv, i) {
int ret = rsnd_mod_init(priv, rsnd_mod_get(cmd),
- &rsnd_cmd_ops, NULL,
+ &rsnd_cmd_ops, NULL, NULL,
RSND_MOD_CMD, i);
if (ret)
return ret;
diff --git a/sound/soc/renesas/rcar/core.c b/sound/soc/renesas/rcar/core.c
index 69fb19964a71..6de576736507 100644
--- a/sound/soc/renesas/rcar/core.c
+++ b/sound/soc/renesas/rcar/core.c
@@ -90,6 +90,7 @@
*
*/
+#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/of_graph.h>
#include "rsnd.h"
@@ -196,18 +197,29 @@ int rsnd_mod_init(struct rsnd_priv *priv,
struct rsnd_mod *mod,
struct rsnd_mod_ops *ops,
struct clk *clk,
+ struct reset_control *rstc,
enum rsnd_mod_type type,
int id)
{
- int ret = clk_prepare(clk);
+ int ret;
+ ret = clk_prepare_enable(clk);
if (ret)
return ret;
+ ret = reset_control_deassert(rstc);
+ if (ret) {
+ clk_disable_unprepare(clk);
+ return ret;
+ }
+
+ clk_disable(clk);
+
mod->id = id;
mod->ops = ops;
mod->type = type;
mod->clk = clk;
+ mod->rstc = rstc;
mod->priv = priv;
return 0;
diff --git a/sound/soc/renesas/rcar/ctu.c b/sound/soc/renesas/rcar/ctu.c
index bd4c61f9fb3c..81bba6a1af6e 100644
--- a/sound/soc/renesas/rcar/ctu.c
+++ b/sound/soc/renesas/rcar/ctu.c
@@ -360,7 +360,7 @@ int rsnd_ctu_probe(struct rsnd_priv *priv)
}
ret = rsnd_mod_init(priv, rsnd_mod_get(ctu), &rsnd_ctu_ops,
- clk, RSND_MOD_CTU, i);
+ clk, NULL, RSND_MOD_CTU, i);
if (ret)
goto rsnd_ctu_probe_done;
diff --git a/sound/soc/renesas/rcar/dma.c b/sound/soc/renesas/rcar/dma.c
index 2035ce06fe4c..68c859897e68 100644
--- a/sound/soc/renesas/rcar/dma.c
+++ b/sound/soc/renesas/rcar/dma.c
@@ -803,7 +803,7 @@ static int rsnd_dma_alloc(struct rsnd_dai_stream *io, struct rsnd_mod *mod,
*dma_mod = rsnd_mod_get(dma);
- ret = rsnd_mod_init(priv, *dma_mod, ops, NULL,
+ ret = rsnd_mod_init(priv, *dma_mod, ops, NULL, NULL,
type, dma_id);
if (ret < 0)
return ret;
@@ -879,5 +879,5 @@ int rsnd_dma_probe(struct rsnd_priv *priv)
priv->dma = dmac;
/* dummy mem mod for debug */
- return rsnd_mod_init(NULL, &mem, &mem_ops, NULL, 0, 0);
+ return rsnd_mod_init(NULL, &mem, &mem_ops, NULL, NULL, 0, 0);
}
diff --git a/sound/soc/renesas/rcar/dvc.c b/sound/soc/renesas/rcar/dvc.c
index 988cbddbc611..bf7146ceb5f6 100644
--- a/sound/soc/renesas/rcar/dvc.c
+++ b/sound/soc/renesas/rcar/dvc.c
@@ -364,7 +364,7 @@ int rsnd_dvc_probe(struct rsnd_priv *priv)
}
ret = rsnd_mod_init(priv, rsnd_mod_get(dvc), &rsnd_dvc_ops,
- clk, RSND_MOD_DVC, i);
+ clk, NULL, RSND_MOD_DVC, i);
if (ret)
goto rsnd_dvc_probe_done;
diff --git a/sound/soc/renesas/rcar/mix.c b/sound/soc/renesas/rcar/mix.c
index aea74e703305..566e9b2a488c 100644
--- a/sound/soc/renesas/rcar/mix.c
+++ b/sound/soc/renesas/rcar/mix.c
@@ -328,7 +328,7 @@ int rsnd_mix_probe(struct rsnd_priv *priv)
}
ret = rsnd_mod_init(priv, rsnd_mod_get(mix), &rsnd_mix_ops,
- clk, RSND_MOD_MIX, i);
+ clk, NULL, RSND_MOD_MIX, i);
if (ret)
goto rsnd_mix_probe_done;
diff --git a/sound/soc/renesas/rcar/rsnd.h b/sound/soc/renesas/rcar/rsnd.h
index 04c70690f7a2..cd7e7df62298 100644
--- a/sound/soc/renesas/rcar/rsnd.h
+++ b/sound/soc/renesas/rcar/rsnd.h
@@ -15,6 +15,7 @@
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/reset.h>
#include <linux/sh_dma.h>
#include <linux/workqueue.h>
#include <sound/soc.h>
@@ -353,6 +354,7 @@ struct rsnd_mod {
struct rsnd_mod_ops *ops;
struct rsnd_priv *priv;
struct clk *clk;
+ struct reset_control *rstc;
u32 status;
};
/*
@@ -420,6 +422,7 @@ int rsnd_mod_init(struct rsnd_priv *priv,
struct rsnd_mod *mod,
struct rsnd_mod_ops *ops,
struct clk *clk,
+ struct reset_control *rstc,
enum rsnd_mod_type type,
int id);
void rsnd_mod_quit(struct rsnd_mod *mod);
diff --git a/sound/soc/renesas/rcar/src.c b/sound/soc/renesas/rcar/src.c
index 6a3dbc84f474..8b58cc20e7a8 100644
--- a/sound/soc/renesas/rcar/src.c
+++ b/sound/soc/renesas/rcar/src.c
@@ -766,7 +766,7 @@ int rsnd_src_probe(struct rsnd_priv *priv)
}
ret = rsnd_mod_init(priv, rsnd_mod_get(src),
- &rsnd_src_ops, clk, RSND_MOD_SRC, i);
+ &rsnd_src_ops, clk, NULL, RSND_MOD_SRC, i);
if (ret)
goto rsnd_src_probe_done;
diff --git a/sound/soc/renesas/rcar/ssi.c b/sound/soc/renesas/rcar/ssi.c
index 0420041e282c..c06cebb36170 100644
--- a/sound/soc/renesas/rcar/ssi.c
+++ b/sound/soc/renesas/rcar/ssi.c
@@ -1225,7 +1225,7 @@ int rsnd_ssi_probe(struct rsnd_priv *priv)
ops = &rsnd_ssi_dma_ops;
ret = rsnd_mod_init(priv, rsnd_mod_get(ssi), ops, clk,
- RSND_MOD_SSI, i);
+ NULL, RSND_MOD_SSI, i);
if (ret)
goto rsnd_ssi_probe_done;
diff --git a/sound/soc/renesas/rcar/ssiu.c b/sound/soc/renesas/rcar/ssiu.c
index 244fb833292a..0cfa84fe5ea8 100644
--- a/sound/soc/renesas/rcar/ssiu.c
+++ b/sound/soc/renesas/rcar/ssiu.c
@@ -586,7 +586,7 @@ int rsnd_ssiu_probe(struct rsnd_priv *priv)
}
ret = rsnd_mod_init(priv, rsnd_mod_get(ssiu),
- ops, NULL, RSND_MOD_SSIU, i);
+ ops, NULL, NULL, RSND_MOD_SSIU, i);
if (ret)
return ret;
}
--
2.25.1
^ permalink raw reply related
* [PATCh v3 02/14] ASoC: dt-bindings: Add RZ/G3E (R9A09G047) sound binding
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
The RZ/G3E shares the same audio IP as the R-Car variants but differs
in several aspects: it supports up to 5 DMA controllers per audio
channel, requires additional clocks (47 total including per-SSI ADG
clocks, SCU domain clocks and SSIF supply) and additional reset lines
(14 total including SCU, ADG and Audio DMAC peri-peri resets).
Add a dedicated devicetree binding for the RZ/G3E sound controller.
The binding references the common renesas,rsnd-common.yaml schema for
shared property and subnode definitions.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2: New patch
.../sound/renesas,r9a09g047-sound.yaml | 371 ++++++++++++++++++
1 file changed, 371 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/renesas,r9a09g047-sound.yaml
diff --git a/Documentation/devicetree/bindings/sound/renesas,r9a09g047-sound.yaml b/Documentation/devicetree/bindings/sound/renesas,r9a09g047-sound.yaml
new file mode 100644
index 000000000000..1dfe9bab3382
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/renesas,r9a09g047-sound.yaml
@@ -0,0 +1,371 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/renesas,r9a09g047-sound.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E Sound Controller
+
+maintainers:
+ - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ - John Madieu <john.madieu.xa@bp.renesas.com>
+
+description:
+ The RZ/G3E (R9A09G047) integrates an R-Car compatible sound controller
+ with extended DMA channel support (up to 5 DMACs per direction), additional
+ clock domains, and additional reset lines compared to the R-Car Gen2/Gen3
+ variants.
+
+allOf:
+ - $ref: renesas,rsnd-common.yaml#
+
+properties:
+ compatible:
+ const: renesas,r9a09g047-sound
+
+ reg:
+ maxItems: 5
+
+ reg-names:
+ items:
+ - const: scu
+ - const: adg
+ - const: ssiu
+ - const: ssi
+ - const: audmapp
+
+ clocks:
+ maxItems: 47
+
+ clock-names:
+ items:
+ - const: ssi-all
+ - const: ssi.9
+ - const: ssi.8
+ - const: ssi.7
+ - const: ssi.6
+ - const: ssi.5
+ - const: ssi.4
+ - const: ssi.3
+ - const: ssi.2
+ - const: ssi.1
+ - const: ssi.0
+ - const: src.9
+ - const: src.8
+ - const: src.7
+ - const: src.6
+ - const: src.5
+ - const: src.4
+ - const: src.3
+ - const: src.2
+ - const: src.1
+ - const: src.0
+ - const: mix.1
+ - const: mix.0
+ - const: ctu.1
+ - const: ctu.0
+ - const: dvc.0
+ - const: dvc.1
+ - const: clk_a
+ - const: clk_b
+ - const: clk_c
+ - const: clk_i
+ - const: ssif_supply
+ - const: scu
+ - const: scu_x2
+ - const: scu_supply
+ - const: adg.ssi.9
+ - const: adg.ssi.8
+ - const: adg.ssi.7
+ - const: adg.ssi.6
+ - const: adg.ssi.5
+ - const: adg.ssi.4
+ - const: adg.ssi.3
+ - const: adg.ssi.2
+ - const: adg.ssi.1
+ - const: adg.ssi.0
+ - const: audmapp
+ - const: adg
+
+ resets:
+ maxItems: 14
+
+ reset-names:
+ items:
+ - const: ssi-all
+ - const: ssi.9
+ - const: ssi.8
+ - const: ssi.7
+ - const: ssi.6
+ - const: ssi.5
+ - const: ssi.4
+ - const: ssi.3
+ - const: ssi.2
+ - const: ssi.1
+ - const: ssi.0
+ - const: scu
+ - const: adg
+ - const: audmapp
+
+ rcar_sound,dvc:
+ description: DVC subnode.
+ type: object
+ patternProperties:
+ "^dvc-[0-1]$":
+ type: object
+ additionalProperties: false
+ properties:
+ dmas:
+ maxItems: 5
+ dma-names:
+ maxItems: 5
+ allOf:
+ - items:
+ enum:
+ - tx
+ required:
+ - dmas
+ - dma-names
+ additionalProperties: false
+
+ rcar_sound,src:
+ description: SRC subnode.
+ type: object
+ patternProperties:
+ "^src-[0-9]$":
+ type: object
+ additionalProperties: false
+ properties:
+ interrupts:
+ maxItems: 1
+ dmas:
+ maxItems: 10
+ dma-names:
+ maxItems: 10
+ allOf:
+ - items:
+ enum:
+ - tx
+ - rx
+ additionalProperties: false
+
+ rcar_sound,ssiu:
+ description: SSIU subnode.
+ type: object
+ patternProperties:
+ "^ssiu-[0-9]+$":
+ type: object
+ additionalProperties: false
+ properties:
+ dmas:
+ maxItems: 10
+ dma-names:
+ maxItems: 10
+ allOf:
+ - items:
+ enum:
+ - tx
+ - rx
+ required:
+ - dmas
+ - dma-names
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ snd_rzg3e: sound@13c00000 {
+ #sound-dai-cells = <1>;
+ #clock-cells = <0>;
+ compatible = "renesas,r9a09g047-sound";
+ reg = <0x13c00000 0x10000>,
+ <0x13c20000 0x10000>,
+ <0x13c30000 0x1000>,
+ <0x13c31000 0x1f000>,
+ <0x13c50000 0x10000>;
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg 245>,
+ <&cpg 394>, <&cpg 393>,
+ <&cpg 392>, <&cpg 391>,
+ <&cpg 390>, <&cpg 389>,
+ <&cpg 388>, <&cpg 387>,
+ <&cpg 386>, <&cpg 385>,
+ <&cpg 381>, <&cpg 380>,
+ <&cpg 379>, <&cpg 378>,
+ <&cpg 377>, <&cpg 376>,
+ <&cpg 375>, <&cpg 374>,
+ <&cpg 373>, <&cpg 372>,
+ <&cpg 371>, <&cpg 370>,
+ <&cpg 371>, <&cpg 370>,
+ <&cpg 368>, <&cpg 369>,
+ <&audio_clk_a>, <&audio_clk_b>,
+ <&audio_clk_c>, <&audio_clk_i>,
+ <&cpg 384>,
+ <&cpg 246>, <&cpg 247>,
+ <&cpg 382>,
+ <&cpg 361>, <&cpg 360>,
+ <&cpg 359>, <&cpg 358>,
+ <&cpg 357>, <&cpg 356>,
+ <&cpg 355>, <&cpg 354>,
+ <&cpg 353>, <&cpg 352>,
+ <&cpg 248>, <&cpg 249>;
+
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8",
+ "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4",
+ "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8",
+ "src.7", "src.6",
+ "src.5", "src.4",
+ "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b",
+ "clk_c", "clk_i",
+ "ssif_supply",
+ "scu", "scu_x2",
+ "scu_supply",
+ "adg.ssi.9", "adg.ssi.8",
+ "adg.ssi.7", "adg.ssi.6",
+ "adg.ssi.5", "adg.ssi.4",
+ "adg.ssi.3", "adg.ssi.2",
+ "adg.ssi.1", "adg.ssi.0",
+ "audmapp", "adg";
+
+ power-domains = <&cpg>;
+
+ resets = <&cpg 225>,
+ <&cpg 235>, <&cpg 234>, <&cpg 233>, <&cpg 232>,
+ <&cpg 231>, <&cpg 230>, <&cpg 229>, <&cpg 228>,
+ <&cpg 227>, <&cpg 226>,
+ <&cpg 236>, <&cpg 238>, <&cpg 237>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "scu", "adg", "audmapp";
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 889 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>;
+ shared-pin;
+ };
+ };
+
+ rcar_sound,ssiu {
+ ssiu30: ssiu-12 {
+ dmas = <&dmac0 0x1d79>, <&dmac0 0x1d7a>,
+ <&dmac1 0x1d79>, <&dmac1 0x1d7a>,
+ <&dmac2 0x1d79>, <&dmac2 0x1d7a>,
+ <&dmac3 0x1d79>, <&dmac3 0x1d7a>,
+ <&dmac4 0x1d79>, <&dmac4 0x1d7a>;
+ dma-names = "tx", "rx", "tx", "rx", "tx", "rx",
+ "tx", "rx", "tx", "rx";
+ };
+ ssiu40: ssiu-16 {
+ dmas = <&dmac0 0x1d81>, <&dmac0 0x1d82>,
+ <&dmac1 0x1d81>, <&dmac1 0x1d82>,
+ <&dmac2 0x1d81>, <&dmac2 0x1d82>,
+ <&dmac3 0x1d81>, <&dmac3 0x1d82>,
+ <&dmac4 0x1d81>, <&dmac4 0x1d82>;
+ dma-names = "tx", "rx", "tx", "rx", "tx", "rx",
+ "tx", "rx", "tx", "rx";
+ };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac0 0x1d9f>, <&dmac0 0x1da9>,
+ <&dmac1 0x1d9f>, <&dmac1 0x1da9>,
+ <&dmac2 0x1d9f>, <&dmac2 0x1da9>,
+ <&dmac3 0x1d9f>, <&dmac3 0x1da9>,
+ <&dmac4 0x1d9f>, <&dmac4 0x1da9>;
+ dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
+ "rx", "tx", "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac0 0x1da0>, <&dmac0 0x1daa>,
+ <&dmac1 0x1da0>, <&dmac1 0x1daa>,
+ <&dmac2 0x1da0>, <&dmac2 0x1daa>,
+ <&dmac3 0x1da0>, <&dmac3 0x1daa>,
+ <&dmac4 0x1da0>, <&dmac4 0x1daa>;
+ dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
+ "rx", "tx", "rx", "tx";
+ };
+ };
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&dmac0 0x1db3>,
+ <&dmac1 0x1db3>,
+ <&dmac2 0x1db3>,
+ <&dmac3 0x1db3>,
+ <&dmac4 0x1db3>;
+ dma-names = "tx", "tx", "tx", "tx", "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&dmac0 0x1db4>,
+ <&dmac1 0x1db4>,
+ <&dmac2 0x1db4>,
+ <&dmac3 0x1db4>,
+ <&dmac4 0x1db4>;
+ dma-names = "tx", "tx", "tx", "tx", "tx";
+ };
+ };
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi3>, <&src1>, <&dvc1>;
+ capture = <&ssi4>, <&src0>, <&dvc0>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rsnd_port0: port@0 {
+ reg = <0>;
+ rsnd_endpoint0: endpoint {
+ remote-endpoint = <&codec_endpoint>;
+ dai-format = "i2s";
+ bitclock-master = <&rsnd_endpoint0>;
+ frame-master = <&rsnd_endpoint0>;
+ playback = <&ssi3>, <&src1>, <&dvc1>;
+ capture = <&ssi4>, <&src0>, <&dvc0>;
+ };
+ };
+ };
+ };
+
+ codec {
+ port {
+ codec_endpoint: endpoint {
+ remote-endpoint = <&rsnd_endpoint0>;
+ };
+ };
+ };
--
2.25.1
^ permalink raw reply related
* [PATCh v3 01/14] ASoC: dt-bindings: renesas,rsnd: Split into generic and SoC-specific parts
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
In-Reply-To: <20260402162436.12059-1-john.madieu.xa@bp.renesas.com>
The current renesas,rsnd.yaml binding file handles all supported SoCs
in a single schema, resulting in deeply nested if/else/then constructs
that become increasingly difficult to maintain. Each new SoC addition
amplifies this complexity, making reviews harder and diffs noisier than
they need to be.
Refactor the binding by extracting the common properties shared across
all SoCs into a dedicated renesas,rsnd-common.yaml schema, and keeping
only SoC-specific constraints (required nodes, port counts, clock names,
etc.) in per-SoC or per-family files that $ref the common part.
This prepares the ground for upcoming SoCs such as the RZ/G3E, which
introduces a different set of audio resources compared to existing
R-Car Gen variants. With the split in place, adding RZ/G3E support
becomes a self-contained change that neither bloats a monolithic schema
nor buries new constraints inside ever-deeper conditional blocks.
No functional change in validation behaviour for existing device trees.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v3: No changes
v2: New patch
.../bindings/sound/renesas,rsnd-common.yaml | 196 +++++++++++
.../bindings/sound/renesas,rsnd.yaml | 319 +++++-------------
2 files changed, 274 insertions(+), 241 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/renesas,rsnd-common.yaml
diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd-common.yaml b/Documentation/devicetree/bindings/sound/renesas,rsnd-common.yaml
new file mode 100644
index 000000000000..ec6bf644d1a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/renesas,rsnd-common.yaml
@@ -0,0 +1,196 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/renesas,rsnd-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car/RZ Sound Common Properties
+
+maintainers:
+ - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+
+description:
+ Common property and subnode definitions shared by Renesas R-Car and RZ
+ sound controller bindings.
+
+select: false
+
+properties:
+ compatible: true
+
+ reg: true
+
+ reg-names: true
+
+ "#sound-dai-cells":
+ description:
+ Must be 0 for a single-DAI system and 1 for a multi-DAI system.
+ enum: [0, 1]
+
+ "#clock-cells":
+ description:
+ Must be 0 when the system has audio_clkout and 1 when it has
+ audio_clkout0/1/2/3.
+ enum: [0, 1]
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ clock-frequency:
+ description: Audio clock output frequency for audio_clkout0/1/2/3.
+
+ clkout-lr-asynchronous:
+ description: audio_clkoutn is asynchronous with lr-clock.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ power-domains: true
+
+ resets: true
+
+ reset-names: true
+
+ clocks: true
+
+ clock-names: true
+
+ port:
+ $ref: audio-graph-port.yaml#/definitions/port-base
+ unevaluatedProperties: false
+ patternProperties:
+ "^endpoint(@[0-9a-f]+)?$":
+ $ref: audio-graph-port.yaml#/definitions/endpoint-base
+ properties:
+ playback:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ capture:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ unevaluatedProperties: false
+
+ rcar_sound,dvc:
+ description: DVC subnode.
+ type: object
+ patternProperties:
+ "^dvc-[0-1]$":
+ type: object
+ additionalProperties: false
+ properties:
+ dmas: true
+ dma-names: true
+ required:
+ - dmas
+ - dma-names
+ additionalProperties: false
+
+ rcar_sound,mix:
+ description: MIX subnode.
+ type: object
+ patternProperties:
+ "^mix-[0-1]$":
+ type: object
+ additionalProperties: false
+ additionalProperties: false
+
+ rcar_sound,ctu:
+ description: CTU subnode.
+ type: object
+ patternProperties:
+ "^ctu-[0-7]$":
+ type: object
+ additionalProperties: false
+ additionalProperties: false
+
+ rcar_sound,src:
+ description: SRC subnode.
+ type: object
+ patternProperties:
+ "^src-[0-9]$":
+ type: object
+ additionalProperties: false
+ properties:
+ interrupts:
+ maxItems: 1
+ dmas: true
+ dma-names: true
+ additionalProperties: false
+
+ rcar_sound,ssiu:
+ description: SSIU subnode.
+ type: object
+ patternProperties:
+ "^ssiu-[0-9]+$":
+ type: object
+ additionalProperties: false
+ properties:
+ dmas: true
+ dma-names: true
+ required:
+ - dmas
+ - dma-names
+ additionalProperties: false
+
+ rcar_sound,ssi:
+ description: SSI subnode.
+ type: object
+ patternProperties:
+ "^ssi-[0-9]$":
+ type: object
+ additionalProperties: false
+ properties:
+ interrupts:
+ maxItems: 1
+ dmas: true
+ dma-names: true
+ shared-pin:
+ description: Shared clock pin.
+ $ref: /schemas/types.yaml#/definitions/flag
+ pio-transfer:
+ description: PIO transfer mode.
+ $ref: /schemas/types.yaml#/definitions/flag
+ no-busif:
+ description: BUSIF is not used for the mem-to-SSI via DMA case.
+ $ref: /schemas/types.yaml#/definitions/flag
+ required:
+ - interrupts
+ additionalProperties: false
+
+patternProperties:
+ 'rcar_sound,dai(@[0-9a-f]+)?$':
+ description: DAI subnode.
+ type: object
+ patternProperties:
+ "^dai([0-9]+)?$":
+ type: object
+ additionalProperties: false
+ properties:
+ playback:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ capture:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ anyOf:
+ - required:
+ - playback
+ - required:
+ - capture
+ additionalProperties: false
+
+ 'ports(@[0-9a-f]+)?$':
+ $ref: audio-graph-port.yaml#/definitions/port-base
+ unevaluatedProperties: false
+ patternProperties:
+ '^port(@[0-9a-f]+)?$':
+ $ref: "#/properties/port"
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+allOf:
+ - $ref: dai-common.yaml#
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml
index e8a2acb92646..0d989922a5b4 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml
+++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml
@@ -9,8 +9,11 @@ title: Renesas R-Car Sound Driver
maintainers:
- Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
-properties:
+description:
+ Binding for Renesas R-Car Gen1/Gen2/Gen3/Gen4 and RZ/G1/G2 sound
+ controllers using the standard RSND layout.
+properties:
compatible:
oneOf:
# for Gen1 SoC
@@ -67,34 +70,6 @@ properties:
minItems: 1
maxItems: 5
- "#sound-dai-cells":
- description: |
- it must be 0 if your system is using single DAI
- it must be 1 if your system is using multi DAIs
- This is used on simple-audio-card
- enum: [0, 1]
-
- "#clock-cells":
- description: |
- it must be 0 if your system has audio_clkout
- it must be 1 if your system has audio_clkout0/1/2/3
- enum: [0, 1]
-
- "#address-cells":
- const: 1
-
- "#size-cells":
- const: 0
-
- clock-frequency:
- description: for audio_clkout0/1/2/3
-
- clkout-lr-asynchronous:
- description: audio_clkoutn is asynchronizes with lr-clock.
- $ref: /schemas/types.yaml#/definitions/flag
-
- power-domains: true
-
resets:
minItems: 1
maxItems: 11
@@ -109,181 +84,45 @@ properties:
maxItems: 31
clock-names:
- description: List of necessary clock names.
- # details are defined below
-
- # ports is below
- port:
- $ref: audio-graph-port.yaml#/definitions/port-base
- unevaluatedProperties: false
- patternProperties:
- "^endpoint(@[0-9a-f]+)?":
- $ref: audio-graph-port.yaml#/definitions/endpoint-base
- properties:
- playback:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- capture:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- unevaluatedProperties: false
-
- rcar_sound,dvc:
- description: DVC subnode.
- type: object
- patternProperties:
- "^dvc-[0-1]$":
- type: object
- additionalProperties: false
-
- properties:
- dmas:
- maxItems: 1
- dma-names:
- const: tx
- required:
- - dmas
- - dma-names
- additionalProperties: false
-
- rcar_sound,mix:
- description: MIX subnode.
- type: object
- patternProperties:
- "^mix-[0-1]$":
- type: object
- additionalProperties: false
- additionalProperties: false
-
- rcar_sound,ctu:
- description: CTU subnode.
- type: object
- patternProperties:
- "^ctu-[0-7]$":
- type: object
- additionalProperties: false
- additionalProperties: false
-
- rcar_sound,src:
- description: SRC subnode.
- type: object
- patternProperties:
- "^src-[0-9]$":
- type: object
- additionalProperties: false
-
- properties:
- interrupts:
- maxItems: 1
- dmas:
- maxItems: 2
- dma-names:
- allOf:
- - items:
- enum:
- - tx
- - rx
- additionalProperties: false
-
- rcar_sound,ssiu:
- description: SSIU subnode.
- type: object
- patternProperties:
- "^ssiu-[0-9]+$":
- type: object
- additionalProperties: false
-
- properties:
- dmas:
- maxItems: 2
- dma-names:
- allOf:
- - items:
- enum:
- - tx
- - rx
- required:
- - dmas
- - dma-names
- additionalProperties: false
-
- rcar_sound,ssi:
- description: SSI subnode.
- type: object
- patternProperties:
- "^ssi-[0-9]$":
- type: object
- additionalProperties: false
-
- properties:
- interrupts:
- maxItems: 1
- dmas:
- minItems: 2
- maxItems: 4
- dma-names:
- allOf:
- - items:
- enum:
- - tx
- - rx
- - txu # if no ssiu node
- - rxu # if no ssiu node
-
- shared-pin:
- description: shared clock pin
- $ref: /schemas/types.yaml#/definitions/flag
- pio-transfer:
- description: PIO transfer mode
- $ref: /schemas/types.yaml#/definitions/flag
- no-busif:
- description: BUSIF is not used when [mem -> SSI] via DMA case
- $ref: /schemas/types.yaml#/definitions/flag
- required:
- - interrupts
- additionalProperties: false
+ description: List of clock names.
+ minItems: 1
+ maxItems: 31
+
+ "#sound-dai-cells": true
+
+ "#clock-cells": true
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+ clock-frequency: true
+
+ clkout-lr-asynchronous: true
+
+ power-domains: true
+
+ port: true
+
+ rcar_sound,dvc: true
+
+ rcar_sound,mix: true
+
+ rcar_sound,ctu: true
+
+ rcar_sound,src: true
+
+ rcar_sound,ssiu: true
+
+ rcar_sound,ssi: true
patternProperties:
- # For DAI base
- 'rcar_sound,dai(@[0-9a-f]+)?$':
- description: DAI subnode.
- type: object
- patternProperties:
- "^dai([0-9]+)?$":
- type: object
- additionalProperties: false
-
- properties:
- playback:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- capture:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- anyOf:
- - required:
- - playback
- - required:
- - capture
- additionalProperties: false
-
- 'ports(@[0-9a-f]+)?$':
- $ref: audio-graph-port.yaml#/definitions/port-base
- unevaluatedProperties: false
- patternProperties:
- '^port(@[0-9a-f]+)?$':
- $ref: "#/properties/port"
-
-required:
- - compatible
- - reg
- - reg-names
- - clocks
- - clock-names
+ 'rcar_sound,dai(@[0-9a-f]+)?$': true
+ 'ports(@[0-9a-f]+)?$': true
allOf:
- - $ref: dai-common.yaml#
+ - $ref: renesas,rsnd-common.yaml#
- # --------------------
- # reg/reg-names
- # --------------------
- # for Gen1
- if:
properties:
compatible:
@@ -295,11 +134,10 @@ allOf:
maxItems: 3
reg-names:
items:
- enum:
- - sru
- - ssi
- - adg
- # for Gen2/Gen3
+ - const: sru
+ - const: ssi
+ - const: adg
+
- if:
properties:
compatible:
@@ -310,16 +148,34 @@ allOf:
then:
properties:
reg:
- minItems: 5
+ maxItems: 5
reg-names:
items:
- enum:
- - scu
- - adg
- - ssiu
- - ssi
- - audmapp
- # for Gen4
+ - const: scu
+ - const: adg
+ - const: ssiu
+ - const: ssi
+ - const: audmapp
+ resets:
+ maxItems: 11
+ reset-names:
+ items:
+ oneOf:
+ - const: ssi-all
+ - pattern: '^ssi\.[0-9]$'
+ clocks:
+ maxItems: 31
+ clock-names:
+ items:
+ oneOf:
+ - const: ssi-all
+ - pattern: '^ssi\.[0-9]$'
+ - pattern: '^src\.[0-9]$'
+ - pattern: '^mix\.[0-1]$'
+ - pattern: '^ctu\.[0-1]$'
+ - pattern: '^dvc\.[0-1]$'
+ - pattern: '^clk_(a|b|c|i)$'
+
- if:
properties:
compatible:
@@ -336,38 +192,19 @@ allOf:
- ssiu
- ssi
- sdmc
-
- # --------------------
- # clock-names
- # --------------------
- - if:
- properties:
- compatible:
- contains:
- const: renesas,rcar_sound-gen4
- then:
- properties:
- clock-names:
- maxItems: 3
+ resets:
+ maxItems: 2
+ reset-names:
items:
- enum:
- - ssi.0
- - ssiu.0
- - clkin
- else:
- properties:
+ - const: ssiu.0
+ - const: ssi.0
+ clocks:
+ maxItems: 3
clock-names:
- minItems: 1
- maxItems: 31
items:
- oneOf:
- - const: ssi-all
- - pattern: '^ssi\.[0-9]$'
- - pattern: '^src\.[0-9]$'
- - pattern: '^mix\.[0-1]$'
- - pattern: '^ctu\.[0-1]$'
- - pattern: '^dvc\.[0-1]$'
- - pattern: '^clk_(a|b|c|i)$'
+ - const: ssiu.0
+ - const: ssi.0
+ - const: clkin
unevaluatedProperties: false
--
2.25.1
^ permalink raw reply related
* [PATCh v3 00/14] ASoC: rsnd: Add RZ/G3E audio driver support
From: John Madieu @ 2026-04-02 16:24 UTC (permalink / raw)
To: Kuninori Morimoto, Mark Brown, Liam Girdwood, Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai, Magnus Damm, Philipp Zabel, Claudiu Beznea,
Biju Das, john.madieu, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, John Madieu
Add audio support for the Renesas RZ/G3E SoC to the R-Car Sound
driver. The RZ/G3E audio subsystem is based on R-Car Sound IP but
has several differences requiring dedicated handling:
- SSI operates exclusively in BUSIF mode (no PIO)
- 2-4 BUSIF channels per SSI (layout differs from R-Car)
- Separate register regions for SCU, ADG, SSIU, SSI accessed by name
- Per-SSI ADG and SSIF supply clocks
- Dedicated audmacpp clock/reset for Audio DMAC peri-peri
- Per-SSI and per-module reset controllers via CPG
This new series is an independent subset of v2 [1] with only ASoC-specific
patches.
Changes:
v3:
- Split out from v2 series [1] to ASoC-specific patchset.
v2:
- Split of rsnd.yaml into common and R-Car-specific schemas
- Introduce RZ/G3E sound binding as a standalone schema
- Addressed Kuninori'comments, details are in individual patches
[1] https://lore.kernel.org/all/20260402090524.9137-1-john.madieu.xa@bp.renesas.com/
John Madieu (14):
ASoC: dt-bindings: renesas,rsnd: Split into generic and SoC-specific
parts
ASoC: dt-bindings: Add RZ/G3E (R9A09G047) sound binding
ASoC: rsnd: Add reset controller support to rsnd_mod
ASoC: rsnd: Add RZ/G3E SoC probing and register map
ASoC: rsnd: Add audmacpp clock and reset support for RZ/G3E
ASoC: rsnd: Add RZ/G3E DMA address calculation support
ASoC: rsnd: ssui: Add RZ/G3E SSIU BUSIF support
ASoC: rsnd: Add SSI reset support for RZ/G3E platforms
ASoC: rsnd: Add ADG reset support for RZ/G3E
ASoC: rsnd: adg: Add per-SSI ADG and SSIF supply clock management
ASoC: rsnd: src: Add SRC reset and clock support for RZ/G3E
ASoC: rsnd: Add rsnd_adg_mod_get() for PM support
ASoC: rsnd: Export rsnd_ssiu_mod_get() for PM support
ASoC: rsnd: Add system suspend/resume support
.../sound/renesas,r9a09g047-sound.yaml | 371 ++++++++++++++++++
.../bindings/sound/renesas,rsnd-common.yaml | 196 +++++++++
.../bindings/sound/renesas,rsnd.yaml | 319 ++++-----------
sound/soc/renesas/rcar/adg.c | 133 ++++++-
sound/soc/renesas/rcar/cmd.c | 2 +-
sound/soc/renesas/rcar/core.c | 60 ++-
sound/soc/renesas/rcar/ctu.c | 22 +-
sound/soc/renesas/rcar/dma.c | 167 ++++++--
sound/soc/renesas/rcar/dvc.c | 22 +-
sound/soc/renesas/rcar/gen.c | 180 +++++++++
sound/soc/renesas/rcar/mix.c | 22 +-
sound/soc/renesas/rcar/rsnd.h | 53 ++-
sound/soc/renesas/rcar/src.c | 71 +++-
sound/soc/renesas/rcar/ssi.c | 51 ++-
sound/soc/renesas/rcar/ssiu.c | 69 +++-
15 files changed, 1439 insertions(+), 299 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/renesas,r9a09g047-sound.yaml
create mode 100644 Documentation/devicetree/bindings/sound/renesas,rsnd-common.yaml
--
2.25.1
^ permalink raw reply
* Re: [PATCH] arm64: dts: imx8mp-phyboard-pollux: Add HDMI support
From: Paul Kocialkowski @ 2026-04-02 16:12 UTC (permalink / raw)
To: Yannic Moog
Cc: devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
In-Reply-To: <573e4ebd9679517086a6b4acb162d72463429f35.camel@phytec.de>
[-- Attachment #1: Type: text/plain, Size: 3212 bytes --]
Hi Yannic,
On Wed 01 Apr 26, 12:06, Yannic Moog wrote:
> On Tue, 2026-03-31 at 00:37 +0200, Paul Kocialkowski wrote:
> > The PHYTEC phyBOARD Pollux comes with a HDMI port on the base board.
> > Add the required device-tree nodes to enable support for it.
>
> "Only" video is supported, but it does work. You could add that to the description since audio is
> also supported upstream and part of HDMI.
You're right, I didn't think about the audio part.
I'll add it in the next iteration.
All the best,
Paul
> Yannic
>
> >
> > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
>
> Reviewed-by: Yannic Moog <y.moog@phytec.de>
> Tested-by: Yannic Moog <y.moog@phytec.de>
>
> > ---
> > .../freescale/imx8mp-phyboard-pollux-rdk.dts | 47 +++++++++++++++++++
> > 1 file changed, 47 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> > index 0fe52c73fc8f..0d52f29813f1 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> > @@ -38,6 +38,18 @@ fan0: fan {
> > #cooling-cells = <2>;
> > };
> >
> > + hdmi-connector {
> > + compatible = "hdmi-connector";
> > + label = "hdmi";
> > + type = "a";
> > +
> > + port {
> > + hdmi_connector_in: endpoint {
> > + remote-endpoint = <&hdmi_tx_out>;
> > + };
> > + };
> > + };
> > +
> > panel_lvds1: panel-lvds1 {
> > /* compatible panel in overlay */
> > backlight = <&backlight_lvds1>;
> > @@ -201,6 +213,28 @@ &flexcan2 {
> > status = "okay";
> > };
> >
> > +&hdmi_pvi {
> > + status = "okay";
> > +};
> > +
> > +&hdmi_tx {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_hdmi>;
> > + status = "okay";
> > +
> > + ports {
> > + port@1 {
> > + hdmi_tx_out: endpoint {
> > + remote-endpoint = <&hdmi_connector_in>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&hdmi_tx_phy {
> > + status = "okay";
> > +};
> > +
> > &i2c2 {
> > clock-frequency = <400000>;
> > pinctrl-names = "default", "gpio";
> > @@ -244,6 +278,10 @@ &i2c3 {
> > scl-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > };
> >
> > +&lcdif3 {
> > + status = "okay";
> > +};
> > +
> > &ldb_lvds_ch1 {
> > remote-endpoint = <&panel1_in>;
> > };
> > @@ -444,6 +482,15 @@ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
> > >;
> > };
> >
> > + pinctrl_hdmi: hdmigrp {
> > + fsl,pins = <
> > + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3
> > + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3
> > + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0
> > x19
> > + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0
> > x19
> > + >;
> > + };
> > +
> > pinctrl_i2c2: i2c2grp {
> > fsl,pins = <
> > MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
--
Paul Kocialkowski,
Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/
Expert in multimedia, graphics and embedded hardware support with Linux.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* [PATCH v3 6/6] phy: realtek: Make configs available for MACH_REALTEK_RTL
From: Rustam Adilov @ 2026-04-02 15:44 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel
Cc: Rustam Adilov
In-Reply-To: <20260402154414.196012-1-adilov@disroot.org>
Add the MACH_REALTEK_RTL to the if statement to make the config
options available for Realtek RTL SoCs as well.
Signed-off-by: Rustam Adilov <adilov@disroot.org>
---
drivers/phy/realtek/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/realtek/Kconfig b/drivers/phy/realtek/Kconfig
index 75ac7e7c31ae..76f9215d8b94 100644
--- a/drivers/phy/realtek/Kconfig
+++ b/drivers/phy/realtek/Kconfig
@@ -3,7 +3,7 @@
# Phy drivers for Realtek platforms
#
-if ARCH_REALTEK || COMPILE_TEST
+if ARCH_REALTEK || MACH_REALTEK_RTL || COMPILE_TEST
config PHY_RTK_RTD_USB2PHY
tristate "Realtek RTD USB2 PHY Transceiver Driver"
@@ -29,4 +29,4 @@ config PHY_RTK_RTD_USB3PHY
DWC3 USB IP. This driver will do the PHY initialization
of the parameters.
-endif # ARCH_REALTEK || COMPILE_TEST
+endif # ARCH_REALTEK || MACH_REALTEK_RTL || COMPILE_TEST
--
2.53.0
^ permalink raw reply related
* [PATCH v3 5/6] phy: realtek: usb2: add support for RTL9607C USB2 PHY
From: Rustam Adilov @ 2026-04-02 15:44 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel
Cc: Rustam Adilov, Michael Zavertkin
In-Reply-To: <20260402154414.196012-1-adilov@disroot.org>
Add support for the usb2 phy of RTL9607C series based SoCs.
Add the macros and phy config struct for rtl9607.
RTL9607C requires to clear a "force host disconnect" bit in the
specific register (which is at an offset from reg_wrap_vstatus)
before proceeding with phy parameter writes.
Add the bool variable to the driver data struct and hide this whole
procedure under the if statement that checks this new variable.
Co-developed-by: Michael Zavertkin <misha.zavertkin@mail.ru>
Signed-off-by: Michael Zavertkin <misha.zavertkin@mail.ru>
Signed-off-by: Rustam Adilov <adilov@disroot.org>
---
drivers/phy/realtek/phy-rtk-usb2.c | 45 ++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-rtk-usb2.c
index 288c8e9e1384..4983dd604b62 100644
--- a/drivers/phy/realtek/phy-rtk-usb2.c
+++ b/drivers/phy/realtek/phy-rtk-usb2.c
@@ -26,6 +26,12 @@
#define PHY_VCTRL_SHIFT 8
#define PHY_REG_DATA_MASK 0xff
+#define PHY_9607_VSTS_BUSY BIT(17)
+#define PHY_9607_NEW_REG_REQ BIT(13)
+
+#define PHY_9607_FORCE_DISCONNECT_REG 0x10
+#define PHY_9607_FORCE_DISCONNECT_BIT BIT(5)
+
#define GET_LOW_NIBBLE(addr) ((addr) & 0x0f)
#define GET_HIGH_NIBBLE(addr) (((addr) & 0xf0) >> 4)
@@ -109,6 +115,7 @@ struct phy_cfg {
u32 (*read)(void __iomem *reg);
void (*write)(u32 val, void __iomem *reg);
+ bool force_host_disconnect;
};
struct phy_parameter {
@@ -621,6 +628,16 @@ static int do_rtk_phy_init(struct rtk_phy *rtk_phy, int index)
goto do_toggle;
}
+ if (phy_cfg->force_host_disconnect) {
+ /* disable force-host-disconnect */
+ u32 temp = readl(phy_reg->reg_wrap_vstatus + PHY_9607_FORCE_DISCONNECT_REG);
+
+ temp &= ~PHY_9607_FORCE_DISCONNECT_BIT;
+ writel(temp, phy_reg->reg_wrap_vstatus + PHY_9607_FORCE_DISCONNECT_REG);
+
+ msleep(10);
+ }
+
/* Set page 0 */
phy_data_page = phy_cfg->page0;
rtk_phy_set_page(phy_reg, 0);
@@ -1386,6 +1403,33 @@ static const struct phy_cfg rtd1315e_phy_cfg = {
.write = rtk_usb2phy_write,
};
+static const struct phy_cfg rtl9607_phy_cfg = {
+ .page0_size = MAX_USB_PHY_PAGE0_DATA_SIZE,
+ .page0 = { [0] = {0xe0, 0x95},
+ [4] = {0xe4, 0x6a},
+ [12] = {0xf3, 0x31}, },
+ .page1_size = MAX_USB_PHY_PAGE1_DATA_SIZE,
+ .page1 = { [0] = {0xe0, 0x26}, },
+ .page2_size = MAX_USB_PHY_PAGE2_DATA_SIZE,
+ .page2 = { [7] = {0xe7, 0x33}, },
+ .num_phy = 1,
+ .check_efuse_version = CHECK_EFUSE_V2,
+ .efuse_dc_driving_rate = EFUS_USB_DC_CAL_RATE,
+ .dc_driving_mask = 0x1f,
+ .efuse_dc_disconnect_rate = EFUS_USB_DC_DIS_RATE,
+ .dc_disconnect_mask = 0xf,
+ .usb_dc_disconnect_at_page0 = true,
+ .do_toggle = true,
+ .driving_updated_for_dev_dis = 0x8,
+ .is_double_sensitivity_mode = true,
+ .vstatus_offset = 0xc,
+ .vstatus_busy = PHY_9607_VSTS_BUSY,
+ .new_reg_req = PHY_9607_NEW_REG_REQ,
+ .read = rtk_usb2phy_read_le,
+ .write = rtk_usb2phy_write_le,
+ .force_host_disconnect = true,
+};
+
static const struct of_device_id usbphy_rtk_dt_match[] = {
{ .compatible = "realtek,rtd1295-usb2phy", .data = &rtd1295_phy_cfg },
{ .compatible = "realtek,rtd1312c-usb2phy", .data = &rtd1312c_phy_cfg },
@@ -1396,6 +1440,7 @@ static const struct of_device_id usbphy_rtk_dt_match[] = {
{ .compatible = "realtek,rtd1395-usb2phy-2port", .data = &rtd1395_phy_cfg_2port },
{ .compatible = "realtek,rtd1619-usb2phy", .data = &rtd1619_phy_cfg },
{ .compatible = "realtek,rtd1619b-usb2phy", .data = &rtd1619b_phy_cfg },
+ { .compatible = "realtek,rtl9607-usb2phy", .data = &rtl9607_phy_cfg },
{},
};
MODULE_DEVICE_TABLE(of, usbphy_rtk_dt_match);
--
2.53.0
^ permalink raw reply related
* [PATCH v3 4/6] phy: realtek: usb2: introduce reset controller struct
From: Rustam Adilov @ 2026-04-02 15:44 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel
Cc: Rustam Adilov, Michael Zavertkin
In-Reply-To: <20260402154414.196012-1-adilov@disroot.org>
In RTL9607C, there is so called "IP Enable Controller" which resemble
reset controller with reset lines and is used for various things like
USB, PCIE, GMAC and such.
Introduce the reset_control struct to this driver to handle deasserting
usb2 phy reset line.
Make use of the function devm_reset_control_array_get_optional_exclusive()
function to get the reset controller and since existing RTD SoCs don't
specify the resets we can have a cleaner code.
Co-developed-by: Michael Zavertkin <misha.zavertkin@mail.ru>
Signed-off-by: Michael Zavertkin <misha.zavertkin@mail.ru>
Signed-off-by: Rustam Adilov <adilov@disroot.org>
---
drivers/phy/realtek/phy-rtk-usb2.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-rtk-usb2.c
index f6670ac6346d..288c8e9e1384 100644
--- a/drivers/phy/realtek/phy-rtk-usb2.c
+++ b/drivers/phy/realtek/phy-rtk-usb2.c
@@ -17,6 +17,7 @@
#include <linux/sys_soc.h>
#include <linux/mfd/syscon.h>
#include <linux/phy/phy.h>
+#include <linux/reset.h>
#include <linux/usb.h>
/* GUSB2PHYACCn register */
@@ -130,6 +131,7 @@ struct rtk_phy {
struct phy_cfg *phy_cfg;
int num_phy;
struct phy_parameter *phy_parameter;
+ struct reset_control *phy_rst;
struct dentry *debug_dir;
};
@@ -604,6 +606,15 @@ static int do_rtk_phy_init(struct rtk_phy *rtk_phy, int index)
phy_parameter = &((struct phy_parameter *)rtk_phy->phy_parameter)[index];
phy_reg = &phy_parameter->phy_reg;
+ if (rtk_phy->phy_rst) {
+ int ret = reset_control_deassert(rtk_phy->phy_rst);
+
+ if (ret)
+ return ret;
+
+ msleep(5);
+ }
+
if (phy_cfg->use_default_parameter) {
dev_dbg(rtk_phy->dev, "%s phy#%d use default parameter\n",
__func__, index);
@@ -1071,6 +1082,11 @@ static int rtk_usb2phy_probe(struct platform_device *pdev)
rtk_phy->num_phy = phy_cfg->num_phy;
+ rtk_phy->phy_rst = devm_reset_control_array_get_optional_exclusive(dev);
+ if (IS_ERR(rtk_phy->phy_rst))
+ return dev_err_probe(dev, PTR_ERR(rtk_phy->phy_rst),
+ "usb2 phy resets are not working\n");
+
ret = parse_phy_data(rtk_phy);
if (ret)
goto err;
--
2.53.0
^ permalink raw reply related
* [PATCH v3 3/6] dt-bindings: phy: realtek,usb2phy.yaml: extend for resets and RTL9607C support
From: Rustam Adilov @ 2026-04-02 15:44 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel
Cc: Rustam Adilov
In-Reply-To: <20260402154414.196012-1-adilov@disroot.org>
Add the "realtek,rtl9607-usb2phy" compatible for USB2 PHY on the RTL9607C
SoC series.
Add a resets property to properties to describe the usb2phy reset line.
In RTL9607C, USB2 PHY reset line is from "IP Enable controller" which is
multipurpose and handle activating various SoC peripherals.
It is unclear whether RTD SoCs have something similar to that so set
the resets to false for these devices.
RTL9607C requires the "resets" to be specified so add the corresponding
if check for the "realtek,rtl9607-usb2phy" compatible.
Signed-off-by: Rustam Adilov <adilov@disroot.org>
---
.../bindings/phy/realtek,usb2phy.yaml | 25 ++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml b/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml
index 9911ada39ee7..7b50833c8e19 100644
--- a/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml
+++ b/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml
@@ -11,7 +11,8 @@ maintainers:
- Stanley Chang <stanley_chang@realtek.com>
description: |
- Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoCs.
+ Realtek USB 2.0 PHY support the digital home center (DHC) RTD and
+ RTL9607C series SoCs.
The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs
support multiple XHCI controllers. One PHY device node maps to one XHCI
controller.
@@ -57,6 +58,12 @@ description: |
XHCI controller#1 -- usb2phy -- phy#0
XHCI controller#2 -- usb2phy -- phy#0
+ RTL9607C SoCs USB
+ The USB architecture includes OHCI and EHCI controllers.
+ Both of them map to one USB2.0 PHY.
+ OHCI controller#0 -- usb2phy -- phy#0
+ EHCI controller#0 -- usb2phy -- phy#0
+
properties:
compatible:
enum:
@@ -69,6 +76,7 @@ properties:
- realtek,rtd1395-usb2phy-2port
- realtek,rtd1619-usb2phy
- realtek,rtd1619b-usb2phy
+ - realtek,rtl9607-usb2phy
reg:
items:
@@ -130,6 +138,9 @@ properties:
minimum: -8
maximum: 8
+ resets:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -157,6 +168,18 @@ allOf:
then:
properties:
realtek,driving-level-compensate: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - realtek,rtl9607-usb2phy
+ then:
+ required:
+ - resets
+ else:
+ properties:
+ resets: false
additionalProperties: false
--
2.53.0
^ permalink raw reply related
* [PATCH v3 2/6] phy: realtek: usb2: introduce read and write functions to driver data
From: Rustam Adilov @ 2026-04-02 15:44 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanley Chang, linux-phy, devicetree, linux-kernel
Cc: Rustam Adilov, Michael Zavertkin
In-Reply-To: <20260402154414.196012-1-adilov@disroot.org>
RTL9607C is a big endian SoC but has little endian USB host controller and
thus, reads and writes to the reg_gusb2phyacc0 should go through
le32_to_cpu and cpu_to_le32 functions respectively. This doesn't apply to
vstatus register though.
To handle this situation, introduce read and write functions to the driver
data and create 2 variations of reads and write function with le32 function
in it and without.
Adjust all instances of utmi_wait_register function to now include the read
function as one of its arguments.
Assign the existing phy configuration for RTD SoCs to the default read
and write functions.
Co-developed-by: Michael Zavertkin <misha.zavertkin@mail.ru>
Signed-off-by: Michael Zavertkin <misha.zavertkin@mail.ru>
Signed-off-by: Rustam Adilov <adilov@disroot.org>
---
drivers/phy/realtek/phy-rtk-usb2.c | 75 ++++++++++++++++++++++++------
1 file changed, 62 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-rtk-usb2.c
index f5d2f0c3376a..f6670ac6346d 100644
--- a/drivers/phy/realtek/phy-rtk-usb2.c
+++ b/drivers/phy/realtek/phy-rtk-usb2.c
@@ -67,6 +67,9 @@ struct phy_reg {
int vstatus_offset;
int vstatus_busy;
int new_reg_req;
+
+ u32 (*read)(void __iomem *reg);
+ void (*write)(u32 val, void __iomem *reg);
};
struct phy_data {
@@ -102,6 +105,9 @@ struct phy_cfg {
int vstatus_offset;
int vstatus_busy;
int new_reg_req;
+
+ u32 (*read)(void __iomem *reg);
+ void (*write)(u32 val, void __iomem *reg);
};
struct phy_parameter {
@@ -128,6 +134,28 @@ struct rtk_phy {
struct dentry *debug_dir;
};
+static u32 rtk_usb2phy_read(void __iomem *reg)
+{
+ return readl(reg);
+}
+
+static u32 rtk_usb2phy_read_le(void __iomem *reg)
+{
+ return le32_to_cpu(readl(reg));
+}
+
+static void rtk_usb2phy_write(u32 val, void __iomem *reg)
+{
+ writel(val, reg);
+}
+
+static void rtk_usb2phy_write_le(u32 val, void __iomem *reg)
+{
+ u32 tmp = cpu_to_le32(val);
+
+ writel(tmp, reg);
+}
+
/* mapping 0xE0 to 0 ... 0xE7 to 7, 0xF0 to 8 ,,, 0xF7 to 15 */
static inline int page_addr_to_array_index(u8 addr)
{
@@ -144,12 +172,13 @@ static inline u8 array_index_to_page_addr(int index)
#define PHY_IO_TIMEOUT_USEC (50000)
#define PHY_IO_DELAY_US (100)
-static inline int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
+static inline int utmi_wait_register(u32 (*read)(void __iomem *reg), void __iomem *reg, u32 mask,
+ u32 result)
{
int ret;
unsigned int val;
- ret = read_poll_timeout(readl, val, ((val & mask) == result),
+ ret = read_poll_timeout(read, val, ((val & mask) == result),
PHY_IO_DELAY_US, PHY_IO_TIMEOUT_USEC, false, reg);
if (ret) {
pr_err("%s can't program USB phy\n", __func__);
@@ -168,25 +197,25 @@ static char rtk_phy_read(struct phy_reg *phy_reg, char addr)
addr -= OFFEST_PHY_READ;
/* polling until VBusy == 0 */
- ret = utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
+ ret = utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
if (ret)
return (char)ret;
/* VCtrl = low nibble of addr, and set PHY_NEW_REG_REQ */
val = phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT);
- writel(val, reg_gusb2phyacc0);
- ret = utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
+ phy_reg->write(val, reg_gusb2phyacc0);
+ ret = utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
if (ret)
return (char)ret;
/* VCtrl = high nibble of addr, and set PHY_NEW_REG_REQ */
val = phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT);
- writel(val, reg_gusb2phyacc0);
- ret = utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
+ phy_reg->write(val, reg_gusb2phyacc0);
+ ret = utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
if (ret)
return (char)ret;
- val = readl(reg_gusb2phyacc0);
+ val = phy_reg->read(reg_gusb2phyacc0);
return (char)(val & PHY_REG_DATA_MASK);
}
@@ -202,23 +231,23 @@ static int rtk_phy_write(struct phy_reg *phy_reg, char addr, char data)
/* write data to VStatusOut2 (data output to phy) */
writel((u32)data << shift_bits, reg_wrap_vstatus + phy_reg->vstatus_offset);
- ret = utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
+ ret = utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
if (ret)
return ret;
/* VCtrl = low nibble of addr, set PHY_NEW_REG_REQ */
val = phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT);
- writel(val, reg_gusb2phyacc0);
- ret = utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
+ phy_reg->write(val, reg_gusb2phyacc0);
+ ret = utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
if (ret)
return ret;
/* VCtrl = high nibble of addr, set PHY_NEW_REG_REQ */
val = phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT);
- writel(val, reg_gusb2phyacc0);
- ret = utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
+ phy_reg->write(val, reg_gusb2phyacc0);
+ ret = utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vstatus_busy, 0);
if (ret)
return ret;
@@ -984,6 +1013,8 @@ static int parse_phy_data(struct rtk_phy *rtk_phy)
phy_parameter->phy_reg.vstatus_offset = phy_cfg->vstatus_offset;
phy_parameter->phy_reg.vstatus_busy = phy_cfg->vstatus_busy;
phy_parameter->phy_reg.new_reg_req = phy_cfg->new_reg_req;
+ phy_parameter->phy_reg.read = phy_cfg->read;
+ phy_parameter->phy_reg.write = phy_cfg->write;
if (of_property_read_bool(np, "realtek,inverse-hstx-sync-clock"))
phy_parameter->inverse_hstx_sync_clock = true;
@@ -1098,6 +1129,8 @@ static const struct phy_cfg rtd1295_phy_cfg = {
.vstatus_offset = 0,
.vstatus_busy = PHY_VSTS_BUSY,
.new_reg_req = PHY_NEW_REG_REQ,
+ .read = rtk_usb2phy_read,
+ .write = rtk_usb2phy_write,
};
static const struct phy_cfg rtd1395_phy_cfg = {
@@ -1125,6 +1158,8 @@ static const struct phy_cfg rtd1395_phy_cfg = {
.vstatus_offset = 0,
.vstatus_busy = PHY_VSTS_BUSY,
.new_reg_req = PHY_NEW_REG_REQ,
+ .read = rtk_usb2phy_read,
+ .write = rtk_usb2phy_write,
};
static const struct phy_cfg rtd1395_phy_cfg_2port = {
@@ -1152,6 +1187,8 @@ static const struct phy_cfg rtd1395_phy_cfg_2port = {
.vstatus_offset = 0,
.vstatus_busy = PHY_VSTS_BUSY,
.new_reg_req = PHY_NEW_REG_REQ,
+ .read = rtk_usb2phy_read,
+ .write = rtk_usb2phy_write,
};
static const struct phy_cfg rtd1619_phy_cfg = {
@@ -1177,6 +1214,8 @@ static const struct phy_cfg rtd1619_phy_cfg = {
.vstatus_offset = 0,
.vstatus_busy = PHY_VSTS_BUSY,
.new_reg_req = PHY_NEW_REG_REQ,
+ .read = rtk_usb2phy_read,
+ .write = rtk_usb2phy_write,
};
static const struct phy_cfg rtd1319_phy_cfg = {
@@ -1206,6 +1245,8 @@ static const struct phy_cfg rtd1319_phy_cfg = {
.vstatus_offset = 0,
.vstatus_busy = PHY_VSTS_BUSY,
.new_reg_req = PHY_NEW_REG_REQ,
+ .read = rtk_usb2phy_read,
+ .write = rtk_usb2phy_write,
};
static const struct phy_cfg rtd1312c_phy_cfg = {
@@ -1234,6 +1275,8 @@ static const struct phy_cfg rtd1312c_phy_cfg = {
.vstatus_offset = 0,
.vstatus_busy = PHY_VSTS_BUSY,
.new_reg_req = PHY_NEW_REG_REQ,
+ .read = rtk_usb2phy_read,
+ .write = rtk_usb2phy_write,
};
static const struct phy_cfg rtd1619b_phy_cfg = {
@@ -1262,6 +1305,8 @@ static const struct phy_cfg rtd1619b_phy_cfg = {
.vstatus_offset = 0,
.vstatus_busy = PHY_VSTS_BUSY,
.new_reg_req = PHY_NEW_REG_REQ,
+ .read = rtk_usb2phy_read,
+ .write = rtk_usb2phy_write,
};
static const struct phy_cfg rtd1319d_phy_cfg = {
@@ -1290,6 +1335,8 @@ static const struct phy_cfg rtd1319d_phy_cfg = {
.vstatus_offset = 0,
.vstatus_busy = PHY_VSTS_BUSY,
.new_reg_req = PHY_NEW_REG_REQ,
+ .read = rtk_usb2phy_read,
+ .write = rtk_usb2phy_write,
};
static const struct phy_cfg rtd1315e_phy_cfg = {
@@ -1319,6 +1366,8 @@ static const struct phy_cfg rtd1315e_phy_cfg = {
.vstatus_offset = 0,
.vstatus_busy = PHY_VSTS_BUSY,
.new_reg_req = PHY_NEW_REG_REQ,
+ .read = rtk_usb2phy_read,
+ .write = rtk_usb2phy_write,
};
static const struct of_device_id usbphy_rtk_dt_match[] = {
--
2.53.0
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