* [PATCH v2 2/3] clk: qcom: Add support for GXCLK for Milos
From: Luca Weiss @ 2026-04-03 12:03 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Luca Weiss, Jagadeesh Kona, Taniya Das
In-Reply-To: <20260403-milos-gxclkctl-v2-0-95eb94a7d0a4@fairphone.com>
GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing
clocks for the GPU subsystem on GX power domain. The GX clock controller
driver manages only the GX GDSC and the rest of the resources of the
controller are managed by the firmware.
We can use the existing kaanapali driver for Milos as well since the
GX_CLKCTL_GX_GDSC supported by the Linux driver requires the same
configuration.
Reviewed-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
drivers/clk/qcom/Makefile | 2 +-
drivers/clk/qcom/gxclkctl-kaanapali.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index b818fd5af8bf..13e7892ba39a 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -187,7 +187,7 @@ obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o
obj-$(CONFIG_SM_GPUCC_8750) += gpucc-sm8750.o gxclkctl-kaanapali.o
-obj-$(CONFIG_SM_GPUCC_MILOS) += gpucc-milos.o
+obj-$(CONFIG_SM_GPUCC_MILOS) += gpucc-milos.o gxclkctl-kaanapali.o
obj-$(CONFIG_SM_LPASSCC_6115) += lpasscc-sm6115.o
obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o
diff --git a/drivers/clk/qcom/gxclkctl-kaanapali.c b/drivers/clk/qcom/gxclkctl-kaanapali.c
index 40d856378a74..7b0af0ba1e68 100644
--- a/drivers/clk/qcom/gxclkctl-kaanapali.c
+++ b/drivers/clk/qcom/gxclkctl-kaanapali.c
@@ -53,6 +53,7 @@ static const struct qcom_cc_desc gx_clkctl_kaanapali_desc = {
static const struct of_device_id gx_clkctl_kaanapali_match_table[] = {
{ .compatible = "qcom,glymur-gxclkctl" },
{ .compatible = "qcom,kaanapali-gxclkctl" },
+ { .compatible = "qcom,milos-gxclkctl" },
{ .compatible = "qcom,sm8750-gxclkctl" },
{ }
};
--
2.53.0
^ permalink raw reply related
* [PATCH v2 1/3] dt-bindings: clock: qcom: document the Milos GX clock controller
From: Luca Weiss @ 2026-04-03 12:03 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Luca Weiss
In-Reply-To: <20260403-milos-gxclkctl-v2-0-95eb94a7d0a4@fairphone.com>
Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and
Power domains (GDSC), but the requirement from the SW driver is to use
the GDSC power domain from the clock controller to recover the GPU
firmware in case of any failure/hangs. The rest of the resources of the
clock controller are being used by the firmware of GPU. This module
exposes the GDSC power domains which helps the recovery of Graphics
subsystem.
Milos can re-use the qcom,kaanapali-gxclkctl.h header due to similarity
of the hardware block, and also re-use of the Linux driver.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
.../bindings/clock/qcom,milos-gxclkctl.yaml | 61 ++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml
new file mode 100644
index 000000000000..3a9721abdd26
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,milos-gxclkctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Power Domain Controller on Milos
+
+maintainers:
+ - Luca Weiss <luca.weiss@fairphone.com>
+
+description: |
+ Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and
+ Power domains (GDSC). This module provides the power domains control
+ of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem.
+
+ See also:
+ include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,milos-gxclkctl
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ description:
+ Power domains required for the clock controller to operate
+ items:
+ - description: GFX power domain
+ - description: GPUCC(CX) power domain
+
+ '#power-domain-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - '#power-domain-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@3d64000 {
+ compatible = "qcom,milos-gxclkctl";
+ reg = <0x0 0x03d64000 0x0 0x6000>;
+ power-domains = <&rpmhpd RPMHPD_GFX>,
+ <&gpucc 0>;
+ #power-domain-cells = <1>;
+ };
+ };
+...
--
2.53.0
^ permalink raw reply related
* [PATCH v2 0/3] Add support for GXCLK for Milos
From: Luca Weiss @ 2026-04-03 12:03 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Luca Weiss, Jagadeesh Kona, Taniya Das,
Konrad Dybcio
Similar to other new SoCs, Milos also contains the GXCLKCTL block that
we need to control for GPU. Add support for it.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes in v2:
- Update casing of binding title, reg goes as second property (Krzysztof)
- Rebase on linux-next
- Pick up tags
- Link to v1: https://lore.kernel.org/r/20260306-milos-gxclkctl-v1-0-00b09ee159a7@fairphone.com
---
Luca Weiss (3):
dt-bindings: clock: qcom: document the Milos GX clock controller
clk: qcom: Add support for GXCLK for Milos
arm64: dts: qcom: milos: Add GX clock controller
.../bindings/clock/qcom,milos-gxclkctl.yaml | 61 ++++++++++++++++++++++
arch/arm64/boot/dts/qcom/milos.dtsi | 10 ++++
drivers/clk/qcom/Makefile | 2 +-
drivers/clk/qcom/gxclkctl-kaanapali.c | 1 +
4 files changed, 73 insertions(+), 1 deletion(-)
---
base-commit: 83acad05dee54a5cff0c98dd7962e55d4c6b145a
change-id: 20260306-milos-gxclkctl-8a8372d6a1e0
Best regards,
--
Luca Weiss <luca.weiss@fairphone.com>
^ permalink raw reply
* [PATCH] arm64: dts: qcom: sm8750: Enable cpufreq cooling devices
From: Aastha Pandey via B4 Relay @ 2026-04-03 11:56 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aastha Pandey
From: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
Add cooling-cells property to the CPU nodes to support cpufreq
cooling devices.
Signed-off-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 18fb52c14acd..417f28d8c919 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -42,6 +42,7 @@ cpu0: cpu@0 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
@@ -58,6 +59,7 @@ cpu1: cpu@100 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
};
cpu2: cpu@200 {
@@ -68,6 +70,7 @@ cpu2: cpu@200 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
};
cpu3: cpu@300 {
@@ -78,6 +81,7 @@ cpu3: cpu@300 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
};
cpu4: cpu@400 {
@@ -88,6 +92,7 @@ cpu4: cpu@400 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd4>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
};
cpu5: cpu@500 {
@@ -98,6 +103,7 @@ cpu5: cpu@500 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd5>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
};
cpu6: cpu@10000 {
@@ -108,6 +114,7 @@ cpu6: cpu@10000 {
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
l2_1: l2-cache {
compatible = "cache";
@@ -124,6 +131,7 @@ cpu7: cpu@10100 {
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
};
cpu-map {
---
base-commit: cc13002a9f984d37906e9476f3e532a8cdd126f5
change-id: 20260403-cpufreq-a47fe1986469
Best regards,
--
Aastha Pandey <aastha.pandey@oss.qualcomm.com>
^ permalink raw reply related
* Re: [PATCH v3 8/9] driver core: Replace dev->of_node_reused with DEV_FLAG_OF_NODE_REUSED
From: Mark Brown @ 2026-04-03 11:56 UTC (permalink / raw)
To: Douglas Anderson
Cc: Greg Kroah-Hartman, Rafael J . Wysocki, Danilo Krummrich,
Alan Stern, Robin Murphy, Leon Romanovsky, Paul Burton,
Saravana Kannan, Alexander Lobakin, Eric Dumazet, Toshi Kani,
Christoph Hellwig, Alexey Kardashevskiy, Johan Hovold,
alexander.stein, andrew, andrew, andriy.shevchenko, astewart,
bhelgaas, brgl, davem, devicetree, driver-core, hkallweit1,
jirislaby, joel, kees, kuba, lgirdwood, linux-arm-kernel,
linux-aspeed, linux-kernel, linux-pci, linux-serial, linux-usb,
linux, mani, netdev, pabeni, robh
In-Reply-To: <20260402174925.v3.8.I806b8636cd3724f6cd1f5e199318ab8694472d90@changeid>
[-- Attachment #1: Type: text/plain, Size: 282 bytes --]
On Thu, Apr 02, 2026 at 05:49:54PM -0700, Douglas Anderson wrote:
> In C, bitfields are not necessarily safe to modify from multiple
> threads without locking. Switch "of_node_reused" over to the "flags"
> field so modifications are safe.
Acked-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply
* Re: [PATCH 1/1] dt-bindings: timer: fsl,imxgpt: add compatible string fsl,imx25-epit
From: Mark Brown @ 2026-04-03 11:43 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Frank Li, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
open list:CLOCKSOURCE, CLOCKEVENT DRIVERS,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Stephen Rothwell
In-Reply-To: <77a77b79-a489-41a8-98c0-00242cbdf24f@oss.qualcomm.com>
[-- Attachment #1: Type: text/plain, Size: 424 bytes --]
On Fri, Apr 03, 2026 at 10:15:49AM +0200, Daniel Lezcano wrote:
> On 4/3/26 10:00, Frank Li wrote:
> > Can't find it at linux-next master branch, anything wrong!
> The patch is in timer/next but may be linux-next disabled my branch
I have a timers/drivers/next branch in your git tree in -next but
no record of anything else. That branch was last updated on January
20th. If you want something else adding let me know.
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^ permalink raw reply
* Re: [PATCH v3 3/3] input: touchscreen: st1232: add system wakeup support
From: Bui Duc Phuc @ 2026-04-03 11:39 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Magnus Damm, Wolfram Sang, Jeff LaBundy, Bastian Hecht,
Javier Carrasco, linux-input, devicetree, linux-renesas-soc,
linux-kernel
In-Reply-To: <CAMuHMdW6y4MkCYR-rgn=FA38ZUE_X=3oQWNOvfdyMo=D5_xoxA@mail.gmail.com>
Hi Dmitry, Geert,
Thank you, Dmitry, for the review and the explanation. You are
absolutely right; I realized the I2C core handles this automatically,
which is tại sao I dropped those changes in the v4 series [1] as Geert
mentioned.
Thank you, Geert, for pointing that out and for your support.
While working on this, I also noticed similar redundant wakeup
handling in the mpr121 driver and sent a cleanup patch to remove
it [2].
[1] https://lore.kernel.org/20260309000319.74880-1-phucduc.bui@gmail.com
[2] https://lore.kernel.org/all/20260309071413.92709-1-phucduc.bui@gmail.com/
Thanks,
Phuc
On Thu, Apr 2, 2026 at 1:56 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Dmitry,
>
> On Thu, 2 Apr 2026 at 07:17, Dmitry Torokhov <dmitry.torokhov@gmail.com> wrote:
> > On Fri, Mar 06, 2026 at 06:19:12PM +0700, phucduc.bui@gmail.com wrote:
> > > From: bui duc phuc <phucduc.bui@gmail.com>
> > >
> > > The ST1232 touchscreen controller can generate an interrupt when the
> > > panel is touched, which may be used as a wakeup source for the system.
> > >
> > > Add support for system wakeup by initializing the device wakeup
> > > capability in probe() based on the "wakeup-source" device property.
> > > When wakeup is enabled, the driver enables IRQ wake during suspend
> > > so that touch events can wake the system.
> > >
> > > If wakeup is not enabled, the driver retains the existing behavior of
> > > disabling the IRQ and powering down the controller during suspend.
> >
> > I do not believe this patch is needed: i2c core already handles
> > "wakeup-source" property and manages wakeup IRQ.
>
> No, it is not needed, as mentioned in the cover letter of v4[1],
> and as tested by me[2].
>
> [1] https://lore.kernel.org/20260309000319.74880-1-phucduc.bui@gmail.com
> [2] https://lore.kernel.org/CAMuHMdUqiaP=COTkKU_jK6Hdii+YJ5+zXnxFkOOnhLri5NakTw@mail.gmail.com
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply
* [PATCH v3] Add remoteproc PAS loader for SoCCP on Glymur DT
From: Ananthu C V @ 2026-04-03 11:39 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Sibi Sankar, Ananthu C V
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++++
arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
index 2852d257ac8c..3fdf8dbbde02 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
@@ -560,6 +560,13 @@ &pon_resin {
status = "okay";
};
+&remoteproc_soccp {
+ firmware-name = "qcom/glymur/soccp.mbn",
+ "qcom/glymur/soccp_dtb.mbn";
+
+ status = "okay";
+};
+
&tlmm {
gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */
<10 2>, /* OOB UART */
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index f23cf81ddb77..f7f3374a5e08 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -2264,6 +2264,53 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
};
};
+ remoteproc_soccp: remoteproc-soccp@d00000 {
+ compatible = "qcom,glymur-soccp-pas", "qcom,kaanapali-soccp-pas";
+ reg = <0x0 0x00d00000 0x0 0x200000>;
+
+ interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "pong";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+
+ memory-region = <&soccp_mem>,
+ <&soccpdtb_mem>;
+
+ qcom,smem-states = <&soccp_smp2p_out 0>,
+ <&soccp_smp2p_out 8>;
+ qcom,smem-state-names = "stop",
+ "ping";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <19>;
+ label = "soccp";
+
+ };
+ };
+
usb_hs_phy: phy@fa0000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
---
base-commit: bd0f139e5fc11182777b81cefc3893ea508544ec
change-id: 20260403-glymur-soccp-2ca25f3b30e2
prerequisite-message-id: <20260326-knp-soccp-dt-v1-0-a60c2ae36e9b@oss.qualcomm.com>
prerequisite-patch-id: fa390011ee531589a7ad14250d158f497622efbd
prerequisite-patch-id: 93e7fca58a5c06edefa624ec2b006dd80f4749a8
prerequisite-patch-id: 99a3b6a7fcd061267b40097ad25f652ebe0a4c7b
Best regards,
--
Ananthu C V <ananthu.cv@oss.qualcomm.com>
^ permalink raw reply related
* [PATCH linux-next v1 3/3] riscv: dts: spacemit: k1-bananapi-f3: Correct USB hub power hierarchy
From: Anand Moon @ 2026-03-25 8:16 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:RISC-V ARCHITECTURE,
open list:RISC-V SPACEMIT SoC Support, open list
Cc: Anand Moon, Han Gao, Ze Huang, Chukun Pan
In-Reply-To: <20260325081700.1502-1-linux.amoon@gmail.com>
Link the usb3_hub_5v regulator to the USB controller’s vbus-supply to
ensure the USB 3.0 stack is properly powered as per the schematics.
In addition, align the USB hub regulator with the board schematics
by renaming it to VCC5V0_HUB and marking it as regulator-always-on
to maintain power stability.
Cc: Han Gao <gaohan@iscas.ac.cn>
Cc: Ze Huang <huang.ze@linux.dev>
Cc: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index c35f4763c800..3dbdf53b6d8e 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -83,9 +83,10 @@ reg_5v_vbus: regulator-usb3-vbus-5v {
usb3_hub_5v: regulator-usb3-hub-5v {
compatible = "regulator-fixed";
- regulator-name = "USB30_HUB";
+ regulator-name = "VCC5V0_HUB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
+ regulator-always-on;
vin-supply = <®_vcc5v0_sys>;
gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
enable-active-high;
@@ -361,6 +362,7 @@ &usb_dwc3 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
+ vbus-supply = <&usb3_hub_5v>;
status = "okay";
hub_2_0: hub@1 {
--
2.53.0
^ permalink raw reply related
* [PATCH linux-next v1 2/3] riscv: dts: spacemit: k1-bananapi-f3: Update USB regulator on onboard usb and lable
From: Anand Moon @ 2026-03-25 8:16 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yixun Lan,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:RISC-V SPACEMIT SoC Support,
open list:RISC-V SPACEMIT SoC Support, open list
Cc: Anand Moon, Han Gao, Ze Huang, Chukun Pan
In-Reply-To: <20260325081700.1502-1-linux.amoon@gmail.com>
Update the USB regulator labels to align with the board schematics and
power hierarchy. This change renames the regulator to reg_5v_vbus and
its name to 5V_VBUS. Additionally, it fixes the vdd-supply references
for both the USB 2.0 and 3.0 hub nodes to ensure they correctly point
to the 5V_VBUS input source as per the board schematics.
Cc: Han Gao <gaohan@iscas.ac.cn>
Cc: Ze Huang <huang.ze@linux.dev>
Cc: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 9727ecdd9f6b..c35f4763c800 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -70,9 +70,9 @@ reg_vcc_4v: regulator-vcc-4v {
vin-supply = <®_dc_in>;
};
- regulator-usb3-vbus-5v {
+ reg_5v_vbus: regulator-usb3-vbus-5v {
compatible = "regulator-fixed";
- regulator-name = "USB30_VBUS";
+ regulator-name = "5V_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
@@ -366,7 +366,7 @@ &usb_dwc3 {
hub_2_0: hub@1 {
compatible = "usb2109,2817";
reg = <0x1>;
- vdd-supply = <&usb3_hub_5v>;
+ vdd-supply = <®_5v_vbus>;
peer-hub = <&hub_3_0>;
reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
};
@@ -374,7 +374,7 @@ hub_2_0: hub@1 {
hub_3_0: hub@2 {
compatible = "usb2109,817";
reg = <0x2>;
- vdd-supply = <&usb3_hub_5v>;
+ vdd-supply = <®_5v_vbus>;
peer-hub = <&hub_2_0>;
reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
};
--
2.53.0
^ permalink raw reply related
* [PATCH linux-next v1 1/3] riscv: dts: spacemit: k1-bananapi-f3: Add vcc5v0_sys regulator for Banana Pi F3
From: Anand Moon @ 2026-03-25 8:16 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yixun Lan,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:RISC-V SPACEMIT SoC Support,
open list:RISC-V SPACEMIT SoC Support, open list
Cc: Anand Moon, Han Gao, Ze Huang, Chukun Pan
In-Reply-To: <20260325081700.1502-1-linux.amoon@gmail.com>
Define the system 5V fixed regulator (vcc5v0_sys) supplied by the
DC input. As per the schematics, vcc5v0_sys is the input power source
for the VCC5V0_HUB and 5V_VBUS reglators. Update these regulators
to correctly reference vcc5v0_sys as their parent (vin-supply).
Cc: Han Gao <gaohan@iscas.ac.cn>
Cc: Ze Huang <huang.ze@linux.dev>
Cc: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 5790d927b93d..9727ecdd9f6b 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -50,6 +50,16 @@ reg_dc_in: regulator-dc-in-12v {
regulator-always-on;
};
+ reg_vcc5v0_sys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <®_dc_in>;
+ };
+
reg_vcc_4v: regulator-vcc-4v {
compatible = "regulator-fixed";
regulator-name = "vcc_4v";
@@ -66,6 +76,7 @@ regulator-usb3-vbus-5v {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
+ vin-supply = <®_vcc5v0_sys>;
gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@@ -75,6 +86,7 @@ usb3_hub_5v: regulator-usb3-hub-5v {
regulator-name = "USB30_HUB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
+ vin-supply = <®_vcc5v0_sys>;
gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
--
2.53.0
^ permalink raw reply related
* [PATCH linux-next v1 0/3] spacemit: k1-bananapi-f3: Fix the power source of USB3 nodes
From: Anand Moon @ 2026-03-25 8:16 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yixun Lan,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:RISC-V SPACEMIT SoC Support,
open list:RISC-V SPACEMIT SoC Support, open list
Cc: Anand Moon
Following changes fix the power source of USB 3 on K1-Bananapi-F3
development board.
Bananapi F3 schematics.
[1] https://drive.google.com/file/d/19iLJ5xnCB_oK8VeQjkPGjzAn39WYyylv/view (page 24)
Use this patch now we can enable USB hub
[2] https://lore.kernel.org/all/20260326100010.3588454-2-amadeus@jmu.edu.cn/
check regulator_summary for more details
$ cat /sys/kernel/debug/regulator/regulator_summary
dc_in_12v 3 2 0 unknown 12000mV 0mA 12000mV 12000mV
vcc5v0_sys 3 2 0 unknown 5000mV 0mA 5000mV 5000mV
5V_VBUS 2 1 0 unknown 5000mV 0mA 5000mV 5000mV
c0a00000.usb:hub@1-vdd 1 0mA 0mV 0mV
VCC5V0_HUB 2 1 0 unknown 5000mV 0mA 5000mV 5000mV
c0a00000.usb-vbus 1 0mA 0mV 0mV
vcc_4v 1 0 0 unknown 4000mV 0mA 4000mV 4000mV
Thanks
-Anand
Anand Moon (3):
riscv: dts: spacemit: k1-bananapi-f3: Add vcc5v0_sys regulator for
Banana Pi F3
riscv: dts: spacemit: k1-bananapi-f3: Update USB regulator on onboard
usb and lable
riscv: dts: spacemit: k1-bananapi-f3: Correct USB hub power hierarchy
.../boot/dts/spacemit/k1-bananapi-f3.dts | 24 +++++++++++++++----
1 file changed, 19 insertions(+), 5 deletions(-)
base-commit: cc13002a9f984d37906e9476f3e532a8cdd126f5
--
2.53.0
^ permalink raw reply
* Re: [PATCH v6 1/3] riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2
From: Troy Mitchell @ 2026-04-03 11:34 UTC (permalink / raw)
To: Han Gao, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao,
Troy Mitchell
In-Reply-To: <894c94e9d087c6a924146bda9a5649c424de320b.1775214644.git.gaohan@iscas.ac.cn>
On Fri, Apr 03, 2026 at 19:18:21 CST, Han Gao wrote:
> The adapter is used to access the SpacemiT P1 PMIC present in this board.
>
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> ---
> arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> index 7b7331cb3c72..93880ba7bdfe 100644
> --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> @@ -87,6 +87,12 @@ &pdma {
> status = "okay";
> };
>
> +&i2c8 {
> + pinctrl-0 = <&i2c8_cfg>;
> + pinctrl-names = "default";
Please keep pinctrl-names before pinctrl-0 to maintain consistency with the rest of the file.
- Troy
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: iio: dac: add support for Microchip MCP48FEB02 to MCP47FEB02
From: Conor Dooley @ 2026-04-03 11:32 UTC (permalink / raw)
To: Ariana Lazar
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jonathan Cameron,
Conor Dooley, linux-iio, devicetree, linux-kernel
In-Reply-To: <20260403-mcp47feb02-fix2-v1-1-da60c773550e@microchip.com>
[-- Attachment #1: Type: text/plain, Size: 3020 bytes --]
On Fri, Apr 03, 2026 at 01:50:13PM +0300, Ariana Lazar wrote:
> This is the device tree schema for iio driver for Microchip
> MCP48FxBy1/2/4/8 series of buffered voltage output Digital-to-Analog
> Converters with nonvolatile or volatile memory on top of MCP47FEB02.
> The families support up to 8 output channels and have 8-bit, 10-bit or
> 12-bit resolution.
>
> The I2C (MCP47F(E/V)BXX) and SPI (MCP48F(E/V)BXX) DAC families were merged
> into the same dt-binding file.
>
> Fixes: 4ba12d304175 ("dt-bindings: iio: dac: adding support for Microchip MCP47FEB02")
> Signed-off-by: Ariana Lazar <ariana.lazar@microchip.com>
> Link: https://lore.kernel.org/all/20260216-shiny-itunes-00a31d1f4db7@spud/
The fixes tag here is not appropriate, you didn't do anything wrong
originally*, this just adds new devices.
*other than the channel number thing, but that should be handled in
isolation I think, if my read on the rationale for your change is
correct.
> ---
> .../bindings/iio/dac/microchip,mcp47feb02.yaml | 291 +++++++++++++++------
> MAINTAINERS | 1 -
> 2 files changed, 217 insertions(+), 75 deletions(-)
> reg:
> maxItems: 1
>
> + spi-max-frequency:
> + maximum: 10000000
> +
> "#address-cells":
> const: 1
>
> @@ -111,7 +172,7 @@ properties:
> - for single-channel device: Vout0;
> - for dual-channel device: Vout0, Vout1;
> - for quad-channel device: Vout0, Vout2;
> - - for octal-channel device: Vout0, Vout2, Vout6, Vout8;
> + - for octal-channel device: Vout0, Vout2, Vout4, Vout6;
>
> vref1-supply:
> description: |
> @@ -141,7 +202,7 @@ properties:
> description:
> Enable buffering of the external Vref/Vref0 pin in cases where the
> external reference voltage does not have sufficient current capability in
> - order not to drop it’s voltage when connected to the internal resistor
> + order not to drop its voltage when connected to the internal resistor
> ladder circuit.
>
> microchip,vref1-buffered:
> @@ -149,7 +210,7 @@ properties:
> description:
> Enable buffering of the external Vref1 pin in cases where the external
> reference voltage does not have sufficient current capability in order not
> - to drop it’s voltage when connected to the internal resistor ladder
> + to drop its voltage when connected to the internal resistor ladder
> circuit.
>
> patternProperties:
> @@ -161,8 +222,7 @@ patternProperties:
> properties:
> reg:
> description: The channel number.
> - minItems: 1
> - maxItems: 8
> + maxItems: 1
Why is this changing? Was it originally a mistake and what you wanted
was a max of 8 but only one entry?
>
> label:
> description: Unique name to identify which channel this is.
> @@ -178,6 +238,13 @@ required:
> - vdd-supply
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^ permalink raw reply
* Re: [PATCh v3 07/14] ASoC: rsnd: ssui: Add RZ/G3E SSIU BUSIF support
From: Mark Brown @ 2026-04-03 11:32 UTC (permalink / raw)
To: Kuninori Morimoto
Cc: John Madieu, Liam Girdwood, Geert Uytterhoeven, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
Magnus Damm, Philipp Zabel, Claudiu Beznea, Biju Das, john.madieu,
linux-sound, linux-renesas-soc, devicetree, linux-kernel
In-Reply-To: <87jyuog7u9.wl-kuninori.morimoto.gx@renesas.com>
[-- Attachment #1: Type: text/plain, Size: 901 bytes --]
On Fri, Apr 03, 2026 at 01:18:07AM +0000, Kuninori Morimoto wrote:
> > > @@ -160,7 +161,8 @@ static int rsnd_ssiu_init(struct rsnd_mod *mod,
> > > /*
> > > * SSI_MODE0
> > > */
> > > - rsnd_mod_bset(mod, SSI_MODE0, (1 << id), !use_busif << id);
> > > + if (!rsnd_is_rzg3e(priv))
> > > + rsnd_mod_bset(mod, SSI_MODE0, (1 << id), !use_busif << id);
> > Perhaps should be a capability flag like the changelog said?
> Have or not have registers are depending on the each SoC, and (probably)
> there's no regularity to it.
> And SoC special handling is needed not only for the register settings.
> There is no clear rule on this driver for now.
> Handling it by flag is one the idea, but rsnd_is_xxx() is enough for now.
> Because it is easy to find SoC specific handling part by "grep rsnd_is_"
To be clear I don't mind either way, it's just that the changelog and
the change don't line up.
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^ permalink raw reply
* [PATCH 3/3] ASoC: renesas: fsi: Fix hang by enabling SPU clock
From: phucduc.bui @ 2026-04-03 11:26 UTC (permalink / raw)
To: kuninori.morimoto.gx, broonie
Cc: lgirdwood, robh, krzk+dt, conor+dt, geert+renesas, magnus.damm,
perex, tiwai, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, bui duc phuc
In-Reply-To: <20260403112655.167593-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
The FSI on r8a7740 requires the SPU clock to be enabled
before accessing its registers.
Without this clock, register access may lead to a system
hang.
Retrieve the "spu" clock in probe and enable it during
DAI startup. Disable the clock on shutdown to match the
audio stream lifecycle.
This ensures safe register access and prevents system
hangs during audio playback.
This is required even if the FSI functional clock is
enabled, as internal units depend on the SPU clock.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
sound/soc/renesas/fsi.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c
index 1491c2f2cc96..44bd1c1e6294 100644
--- a/sound/soc/renesas/fsi.c
+++ b/sound/soc/renesas/fsi.c
@@ -292,6 +292,7 @@ struct fsi_master {
void __iomem *base;
struct fsi_priv fsia;
struct fsi_priv fsib;
+ struct clk *clk_spu;
const struct fsi_core *core;
spinlock_t lock;
};
@@ -1554,6 +1555,11 @@ static int fsi_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsi_priv *fsi = fsi_get_priv(substream);
+ int ret;
+
+ ret = clk_prepare_enable(fsi->master->clk_spu);
+ if (ret)
+ return ret;
fsi_clk_invalid(fsi);
@@ -1566,6 +1572,7 @@ static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
struct fsi_priv *fsi = fsi_get_priv(substream);
fsi_clk_invalid(fsi);
+ clk_disable_unprepare(fsi->master->clk_spu);
}
static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
@@ -1963,6 +1970,13 @@ static int fsi_probe(struct platform_device *pdev)
master->core = core;
spin_lock_init(&master->lock);
+ /* SPU clock is required for FSI register access */
+ master->clk_spu = devm_clk_get(&pdev->dev, "spu");
+ if (IS_ERR(master->clk_spu)) {
+ dev_err(&pdev->dev, "Failed to get spu clock\n");
+ return PTR_ERR(master->clk_spu);
+ }
+
/* FSI A setting */
fsi = &master->fsia;
fsi->base = master->base;
--
2.43.0
^ permalink raw reply related
* [PATCH 2/3] arm: dts: renesas: r8a7740-armadillo800eva: Add spu clock to FSI
From: phucduc.bui @ 2026-04-03 11:26 UTC (permalink / raw)
To: kuninori.morimoto.gx, broonie
Cc: lgirdwood, robh, krzk+dt, conor+dt, geert+renesas, magnus.damm,
perex, tiwai, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, bui duc phuc
In-Reply-To: <20260403112655.167593-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
The FSI on r8a7740 requires the SPU clock to be enabled
before accessing its registers.
Without this clock, register access may lead to a system
hang.
Describe the "spu" clock in the FSI node.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
arch/arm/boot/dts/renesas/r8a7740.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi
index d13ab86c3ab4..9cae87a1979c 100644
--- a/arch/arm/boot/dts/renesas/r8a7740.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi
@@ -393,7 +393,8 @@ sh_fsi2: sound@fe1f0000 {
compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
reg = <0xfe1f0000 0x400>;
interrupts = <GIC_SPI 9 0x4>;
- clocks = <&mstp3_clks R8A7740_CLK_FSI>;
+ clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>;
+ clock-names = "fsi", "spu";
power-domains = <&pd_a4mp>;
status = "disabled";
};
--
2.43.0
^ permalink raw reply related
* [PATCH 1/3] dt-bindings: sound: renesas,fsi: Add support for multiple clocks
From: phucduc.bui @ 2026-04-03 11:26 UTC (permalink / raw)
To: kuninori.morimoto.gx, broonie
Cc: lgirdwood, robh, krzk+dt, conor+dt, geert+renesas, magnus.damm,
perex, tiwai, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, bui duc phuc
In-Reply-To: <20260403112655.167593-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
The FSI on r8a7740 requires the SPU clock to be enabled
before accessing its registers.
Without this clock, register access may lead to a system
hang.
Add support for the "spu" clock so it can be managed by
the driver.
The binding is also extended to allow additional clocks,
as FSIB may require more clock inputs, while FSIA
typically uses fewer.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
.../devicetree/bindings/sound/renesas,fsi.yaml | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
index df91991699a7..225cd8d369bb 100644
--- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
+++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
@@ -38,7 +38,11 @@ properties:
maxItems: 1
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 8
+
+ clock-names:
+ description: List of necessary clock names.
power-domains:
maxItems: 1
@@ -77,7 +81,11 @@ examples:
compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
reg = <0xfe1f0000 0x400>;
interrupts = <GIC_SPI 9 0x4>;
- clocks = <&mstp3_clks R8A7740_CLK_FSI>;
+ clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>,
+ <&fsia_clk>, <&fsib_clk>, <&fsidiva_clk>,
+ <&fsidivb_clk>,<&fsiack_clk>,<&fsibck_clk>;
+ clock-names = "fsi", "spu", "icka", "ickb",
+ "diva", "divb", "xcka", "xckb";
power-domains = <&pd_a4mp>;
#sound-dai-cells = <1>;
--
2.43.0
^ permalink raw reply related
* [PATCH 0/3] ASoC: renesas: fsi: Fix system hang by adding SPU clock
From: phucduc.bui @ 2026-04-03 11:26 UTC (permalink / raw)
To: kuninori.morimoto.gx, broonie
Cc: lgirdwood, robh, krzk+dt, conor+dt, geert+renesas, magnus.damm,
perex, tiwai, linux-sound, linux-renesas-soc, devicetree,
linux-kernel, bui duc phuc
From: bui duc phuc <phucduc.bui@gmail.com>
Hi all,
The FSI on r8a7740 requires the SPU clock to be enabled
before accessing its internal registers. Without this clock,
register access may lead to a system hang, even when the FSI
functional clock itself is properly enabled.
This series adds support for the SPU clock and updates the
bindings to allow multiple clocks. The driver retrieves the
SPU clock and enables it during DAI startup, then disables
it on shutdown to match the audio stream lifecycle.
The binding is also extended to support additional clocks,
as FSIB may require more clock inputs, while FSIA typically
uses fewer.
This has been tested on r8a7740 (Armadillo800eva) and fixes
system hangs observed during audio playback.
Patch overview:
[1/3] dt-bindings: sound: renesas,fsi: Add support for multiple clocks
[2/3] arm: dts: renesas: r8a7740-armadillo800eva: Add spu clock to FSI
[3/3] ASoC: renesas: fsi: Fix hang by enabling SPU clock
Thanks,
Phuc
bui duc phuc (3):
dt-bindings: sound: renesas,fsi: Add support for multiple clocks
arm: dts: renesas: r8a7740-armadillo800eva: Add spu clock to FSI
ASoC: renesas: fsi: Fix hang by enabling SPU clock
.../devicetree/bindings/sound/renesas,fsi.yaml | 12 ++++++++++--
arch/arm/boot/dts/renesas/r8a7740.dtsi | 3 ++-
sound/soc/renesas/fsi.c | 14 ++++++++++++++
3 files changed, 26 insertions(+), 3 deletions(-)
--
2.43.0
^ permalink raw reply
* [PATCH v2 3/3] iio: adc: qcom-pm8xxx-xoadc: add support for reading channel labels
From: Antony Kurniawan Soemardi @ 2026-04-03 9:23 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko
Cc: linux-arm-msm, devicetree, linux-kernel, linux-iio, phone-devel,
Antony Kurniawan Soemardi
In-Reply-To: <20260403-pm8xxx-xoadc-label-v2-0-29b50bf821e6@smankusors.com>
Implement the .read_label callback to allow userspace to identify ADC
channels via the "label" property in the device tree. The name field in
pm8xxx_chan_info is renamed to label to better reflect its purpose. If
no label is provided in the device tree, it defaults to the hardware
datasheet name.
The change has been tested on Sony Xperia SP (PM8921).
Signed-off-by: Antony Kurniawan Soemardi <linux@smankusors.com>
---
drivers/iio/adc/qcom-pm8xxx-xoadc.c | 24 +++++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/iio/adc/qcom-pm8xxx-xoadc.c b/drivers/iio/adc/qcom-pm8xxx-xoadc.c
index d63af84bf44776c9c7106a43473b1678496247cb..f473c5e0c5a217bb4a3773177b6e02f0603d7de6 100644
--- a/drivers/iio/adc/qcom-pm8xxx-xoadc.c
+++ b/drivers/iio/adc/qcom-pm8xxx-xoadc.c
@@ -369,7 +369,7 @@ static const struct xoadc_channel pm8921_xoadc_channels[] = {
/**
* struct pm8xxx_chan_info - ADC channel information
- * @name: name of this channel
+ * @label: label of this channel from device tree (defaults to datasheet name if not specified)
* @hwchan: pointer to hardware channel information (muxing & scaling settings)
* @calibration: whether to use absolute or ratiometric calibration
* @decimation: 0,1,2,3
@@ -377,7 +377,7 @@ static const struct xoadc_channel pm8921_xoadc_channels[] = {
* calibration: 0, 1, 2, 4, 5.
*/
struct pm8xxx_chan_info {
- const char *name;
+ const char *label;
const struct xoadc_channel *hwchan;
enum vadc_calibration calibration;
u8 decimation:2;
@@ -446,7 +446,7 @@ static int pm8xxx_read_channel_rsv(struct pm8xxx_xoadc *adc,
u8 lsb, msb;
dev_dbg(adc->dev, "read channel \"%s\", amux %d, prescale/mux: %d, rsv %d\n",
- ch->name, ch->hwchan->amux_channel, ch->hwchan->pre_scale_mux, rsv);
+ ch->label, ch->hwchan->amux_channel, ch->hwchan->pre_scale_mux, rsv);
mutex_lock(&adc->lock);
@@ -719,8 +719,20 @@ static int pm8xxx_fwnode_xlate(struct iio_dev *indio_dev,
return -EINVAL;
}
+static int pm8xxx_read_label(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, char *label)
+{
+ struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
+ struct pm8xxx_chan_info *ch = pm8xxx_get_channel(adc, chan->address);
+
+ if (!ch)
+ return -EINVAL;
+ return sysfs_emit(label, "%s\n", ch->label);
+}
+
static const struct iio_info pm8xxx_xoadc_info = {
.fwnode_xlate = pm8xxx_fwnode_xlate,
+ .read_label = pm8xxx_read_label,
.read_raw = pm8xxx_read_raw,
};
@@ -764,7 +776,9 @@ static int pm8xxx_xoadc_parse_channel(struct device *dev,
pre_scale_mux, amux_channel);
return -EINVAL;
}
- ch->name = name;
+ ret = fwnode_property_read_string(fwnode, "label", &ch->label);
+ if (ret)
+ ch->label = hwchan->datasheet_name;
ch->hwchan = hwchan;
/* Everyone seems to use absolute calibration except in special cases */
ch->calibration = VADC_CALIB_ABSOLUTE;
@@ -806,7 +820,7 @@ static int pm8xxx_xoadc_parse_channel(struct device *dev,
dev_dbg(dev,
"channel [PRESCALE/MUX: %02x AMUX: %02x] \"%s\" ref voltage: %d, decimation %d prescale %d/%d, scale function %d\n",
- hwchan->pre_scale_mux, hwchan->amux_channel, ch->name,
+ hwchan->pre_scale_mux, hwchan->amux_channel, ch->label,
ch->amux_ip_rsv, ch->decimation, hwchan->prescale.numerator,
hwchan->prescale.denominator, hwchan->scale_fn_type);
--
2.34.1
^ permalink raw reply related
* [PATCH v6 3/3] riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
From: Han Gao @ 2026-04-03 11:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao
In-Reply-To: <cover.1775214644.git.gaohan@iscas.ac.cn>
Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the
OrangePi RV2 board.
The board utilizes a Genesys Logic GL3523 USB3.0 hub.
Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and
PHY-related Device Tree nodes for the OrangePi RV2.
Co-developed-by: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 69 +++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index 98b1d47053d2..5d4e278695c3 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -23,6 +23,16 @@ chosen {
stdout-path = "serial0";
};
+ pcie_vcc3v3: regulator-pcie-vcc3v3 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>;
+ regulator-name = "pcie_vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v0>;
+ };
+
vcc_5v0: regulator-vcc-5v0 {
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
@@ -54,6 +64,10 @@ led1 {
};
};
+&combo_phy {
+ status = "okay";
+};
+
ð0 {
phy-handle = <&rgmii0>;
phy-mode = "rgmii-id";
@@ -224,8 +238,63 @@ dldo7 {
};
};
+&pcie1_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_3_cfg>;
+ status = "okay";
+};
+
+&pcie1_port {
+ phys = <&pcie1_phy>;
+ vpcie3v3-supply = <&pcie_vcc3v3>;
+};
+
+&pcie1 {
+ vpcie3v3-supply = <&pcie_vcc3v3>;
+ status = "okay";
+};
+
+&pcie2_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_4_cfg>;
+ status = "okay";
+};
+
+&pcie2_port {
+ phys = <&pcie2_phy>;
+};
+
+&pcie2 {
+ vpcie3v3-supply = <&pcie_vcc3v3>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vdd-supply = <&vcc_5v0>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb5e3,610";
+ reg = <0x1>;
+ peer-hub = <&hub_3_0>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb5e3,620";
+ reg = <0x2>;
+ peer-hub = <&hub_2_0>;
+ };
+};
--
2.47.3
^ permalink raw reply related
* [PATCH v6 2/3] riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2
From: Han Gao @ 2026-04-03 11:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao
In-Reply-To: <cover.1775214644.git.gaohan@iscas.ac.cn>
Define the DC power input and the 4v power as fixed regulator supplies.
Define the SpacemiT P1 PMIC voltage regulators and their constraints.
Co-developed-by: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 131 ++++++++++++++++++
1 file changed, 131 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index 93880ba7bdfe..98b1d47053d2 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -23,6 +23,25 @@ chosen {
stdout-path = "serial0";
};
+ vcc_5v0: regulator-vcc-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc4v0: regulator-vcc4v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc4v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ vin-supply = <&vcc_5v0>;
+ };
+
leds {
compatible = "gpio-leds";
@@ -91,6 +110,118 @@ &i2c8 {
pinctrl-0 = <&i2c8_cfg>;
pinctrl-names = "default";
status = "okay";
+
+ pmic@41 {
+ compatible = "spacemit,p1";
+ reg = <0x41>;
+ interrupts = <64>;
+ vin1-supply = <&vcc4v0>;
+ vin2-supply = <&vcc4v0>;
+ vin3-supply = <&vcc4v0>;
+ vin4-supply = <&vcc4v0>;
+ vin5-supply = <&vcc4v0>;
+ vin6-supply = <&vcc4v0>;
+ aldoin-supply = <&vcc4v0>;
+ dldoin1-supply = <&buck5>;
+ dldoin2-supply = <&buck5>;
+
+ regulators {
+ buck1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck3_1v8: buck3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck4_3v3: buck4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck5: buck5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ aldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ aldo2 {
+ /* not connected */
+ };
+
+ aldo3 {
+ /* not connected */
+ };
+
+ aldo4 {
+ /* not connected */
+ };
+
+ dldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ dldo2 {
+ /* not connected */
+ };
+
+ dldo3 {
+ /* not connected */
+ };
+
+ dldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo7 {
+ /* not connected */
+ };
+ };
+ };
};
&uart0 {
--
2.47.3
^ permalink raw reply related
* [PATCH v6 1/3] riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2
From: Han Gao @ 2026-04-03 11:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao
In-Reply-To: <cover.1775214644.git.gaohan@iscas.ac.cn>
The adapter is used to access the SpacemiT P1 PMIC present in this board.
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index 7b7331cb3c72..93880ba7bdfe 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -87,6 +87,12 @@ &pdma {
status = "okay";
};
+&i2c8 {
+ pinctrl-0 = <&i2c8_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
--
2.47.3
^ permalink raw reply related
* [PATCH v6 0/3] riscv: dts: spacemit: Add PMIC regulators usb pcie
From: Han Gao @ 2026-04-03 11:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao
Changes in v5:
- patch 2:
restore floating nodes and mark as 'not connected'
- patch 3:
remove vcc5v0_usb30
reorder pcie_vcc3v3 and add vin-supply
remove redundant vpcie3v3-supply from pcie2
update hub vdd-supply based on Chukun's patch
- Link to v5: https://lore.kernel.org/linux-riscv/cover.1775148159.git.gaohan@iscas.ac.cn/
Han Gao (3):
riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2
riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2
riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 206 ++++++++++++++++++
1 file changed, 206 insertions(+)
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
prerequisite-patch-id: ef6e9c7b5854d0c08066b72f9a7868db8c2140eb
prerequisite-patch-id: cfe3800f8c791ec4c63e070af9628e88e0fc31b9
prerequisite-patch-id: b76493e625ae257c8adcd67874178458420e4d47
prerequisite-patch-id: 88e01dc92c83bd88ddeb78891d3088209fed8d6b
prerequisite-patch-id: 60336d10ab8322c70596d0f046b6b5c54bb24b54
prerequisite-patch-id: 68c4d869548687dc115dd91e2ffb8f4c11482d86
prerequisite-patch-id: fdadcf964c2cb3406160edb579d99a8d5695f8e6
prerequisite-patch-id: 73b9e745338b0499b849fa4f7f9508987ab39a59
prerequisite-patch-id: cd26770c2160c3c31a406bd8a6b01ab666180ae0
prerequisite-patch-id: e5dfddc32cefae195692da8b80e19adf086e4ad7
prerequisite-patch-id: 7fd53cbe4977598f26148a4bb1cf692bbdb79a09
prerequisite-patch-id: 96ebac57bb29619b97fe95422206a685825618e9
prerequisite-patch-id: 00fac16b52f60383db3140e2885f3f7f8d14dd1a
prerequisite-patch-id: 3b7a60047b922c48e93599f621cb738856f42354
prerequisite-patch-id: 275c030b963be05dd1041451f539a130ce614277
prerequisite-patch-id: 93963424b0871e64276af0e0b2199b52e29b4603
prerequisite-patch-id: 8383188b1c01ed6280629faaa29c37d699ade241
prerequisite-patch-id: 5f8126b912b924d63d4a1e0c5eb42d212eb0d369
prerequisite-patch-id: e80af628a2e0b5f2eeb3cb1b5e7133d08bdd2c4e
prerequisite-patch-id: 0234a6dca15eb91f98a45a46604ce5b4935048a5
--
2.47.3
^ permalink raw reply
* [PATCH v5 5/5] riscv64: dts: sophgo: add initial Milk-V Duo S board support
From: Joshua Milas @ 2026-04-03 11:15 UTC (permalink / raw)
To: tglx, robh, krzk+dt, conor+dt, pjw, samuel.holland, unicorn_wang,
inochiama, daniel.lezcano, palmer, aou, alex, liujingqi,
alexander.sverdlin, rabenda.cn, dlan, chao.wei, anup
Cc: josh.milas, linux-kernel, devicetree, linux-riscv, sophgo,
hanguidong02, michael.opdenacker
In-Reply-To: <20260403111516.379795-1-josh.milas@gmail.com>
This adds initial riscv support for the Milk-V Duo S board
[1] making it possible to boot Linux to the command line.
Link: https://milkv.io/duo-s [1]
Signed-off-by: Joshua Milas <josh.milas@gmail.com>
---
arch/riscv/boot/dts/sophgo/Makefile | 1 +
.../boot/dts/sophgo/sg2000-milkv-duo-s.dts | 85 +++++++++++++++++++
2 files changed, 86 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/sg2000-milkv-duo-s.dts
diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
index 6f65526d4193b..58cc6b70d8de4 100644
--- a/arch/riscv/boot/dts/sophgo/Makefile
+++ b/arch/riscv/boot/dts/sophgo/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
+dtb-$(CONFIG_ARCH_SOPHGO) += sg2000-milkv-duo-s.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
diff --git a/arch/riscv/boot/dts/sophgo/sg2000-milkv-duo-s.dts b/arch/riscv/boot/dts/sophgo/sg2000-milkv-duo-s.dts
new file mode 100644
index 0000000000000..8632470f43ab0
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2000-milkv-duo-s.dts
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "sg2000.dtsi"
+
+/ {
+ model = "Milk-V Duo S";
+ compatible = "milkv,duo-s", "sophgo,sg2000";
+
+ aliases {
+ i2c4 = &i2c4;
+ mmc0 = &sdhci0;
+ serial0 = &uart0;
+ spi3 = &spi3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&osc {
+ clock-frequency = <25000000>;
+};
+
+&dmac {
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <4>;
+ no-1-8-v;
+ cap-mmc-hw-reset;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+&sdhci0 {
+ bus-width = <4>;
+ no-1-8-v;
+ disable-wp;
+ status = "okay";
+};
+
+&sdhci1 {
+ bus-width = <4>;
+ cap-sdio-irq;
+ no-mmc;
+ no-sd;
+ non-removable;
+ status = "okay";
+};
+
+&spi3 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb {
+ dr_mode = "host";
+ status = "okay";
+};
+
--
2.53.0
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