* [PATCH 2/2] arm64: dts: qcom: milos: Add IMEM node
From: Luca Weiss @ 2026-04-03 15:00 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss
In-Reply-To: <20260403-milos-imem-v1-0-4244ebb47017@fairphone.com>
Add a node for the IMEM found on Milos, which contains pil-reloc-info
and the modem tables for IPA, among others.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/milos.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 4a64a98a434b..1c045743ef77 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -2289,6 +2289,25 @@ scl-pins {
};
};
+ sram@14680000 {
+ compatible = "qcom,milos-imem", "syscon", "simple-mfd";
+ reg = <0x0 0x14680000 0x0 0x2c000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0x14680000 0x2c000>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+
+ ipa_modem_tables: modem-tables@3000 {
+ reg = <0x3000 0x2000>;
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x15000000 0x0 0x100000>;
--
2.53.0
^ permalink raw reply related
* [PATCH 0/2] Describe IMEM on Milos
From: Luca Weiss @ 2026-04-03 15:00 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss
Add a compatible and describe the IMEM for the Milos SoC.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Luca Weiss (2):
dt-bindings: sram: qcom,imem: Add the Milos compatible
arm64: dts: qcom: milos: Add IMEM node
Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 +
arch/arm64/boot/dts/qcom/milos.dtsi | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
---
base-commit: 83acad05dee54a5cff0c98dd7962e55d4c6b145a
change-id: 20260403-milos-imem-3a034224946a
Best regards,
--
Luca Weiss <luca.weiss@fairphone.com>
^ permalink raw reply
* [PATCH 1/2] dt-bindings: sram: qcom,imem: Add the Milos compatible
From: Luca Weiss @ 2026-04-03 15:00 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss
In-Reply-To: <20260403-milos-imem-v1-0-4244ebb47017@fairphone.com>
Add compatible for Milos SoC IMEM.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml
index c63026904061..38488e28a6b4 100644
--- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml
+++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml
@@ -19,6 +19,7 @@ properties:
- enum:
- qcom,apq8064-imem
- qcom,ipq5424-imem
+ - qcom,milos-imem
- qcom,msm8226-imem
- qcom,msm8974-imem
- qcom,msm8976-imem
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v2] dt-bindings: rtc: add olpc,xo1-rtc to trivial-rtc
From: Alexandre Belloni @ 2026-04-03 14:57 UTC (permalink / raw)
To: Anushka Badhe
Cc: conor+dt, devicetree, dsd, krzk+dt, linux-kernel, linux-rtc, robh
In-Reply-To: <20260325093003.44051-1-anushkabadhe@gmail.com>
On Wed, 25 Mar 2026 15:00:03 +0530, Anushka Badhe wrote:
> Add the OLPC XO-1 RTC compatible string to the trivial-rtc schema
> instead of creating a standalone binding file, as it only requires
> a compatible property with no additional configuration.
Applied, thanks!
[1/1] dt-bindings: rtc: add olpc,xo1-rtc to trivial-rtc
https://git.kernel.org/abelloni/c/d1b091aaba8c
Best regards,
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH v6 06/10] clk: realtek: Add support for mux clock
From: Brian Masney @ 2026-04-03 14:54 UTC (permalink / raw)
To: Yu-Chun Lin
Cc: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12,
afaerber, jyanchou, devicetree, linux-clk, linux-kernel,
linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang,
stanley_chang
In-Reply-To: <20260402073957.2742459-7-eleanor.lin@realtek.com>
Hi Yu-Chun and Cheng-Yu,
On Thu, Apr 02, 2026 at 03:39:53PM +0800, Yu-Chun Lin wrote:
> From: Cheng-Yu Lee <cylee12@realtek.com>
>
> Add a simple regmap-based clk_ops implementation for Realtek mux clocks.
>
> The implementation supports parent selection and rate determination through
> regmap-backed register access.
>
> Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com>
> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> ---
> Changes in v6:
> - Add the headers used in c file to follow the "Include What You Use" principle.
> ---
> drivers/clk/realtek/Makefile | 1 +
> drivers/clk/realtek/clk-regmap-mux.c | 48 ++++++++++++++++++++++++++++
> drivers/clk/realtek/clk-regmap-mux.h | 43 +++++++++++++++++++++++++
> 3 files changed, 92 insertions(+)
> create mode 100644 drivers/clk/realtek/clk-regmap-mux.c
> create mode 100644 drivers/clk/realtek/clk-regmap-mux.h
>
> diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
> index 74375f8127ac..f90dc57fcfdb 100644
> --- a/drivers/clk/realtek/Makefile
> +++ b/drivers/clk/realtek/Makefile
> @@ -5,4 +5,5 @@ clk-rtk-y += common.o
>
> clk-rtk-y += clk-pll.o
> clk-rtk-y += clk-regmap-gate.o
> +clk-rtk-y += clk-regmap-mux.o
> clk-rtk-y += freq_table.o
> diff --git a/drivers/clk/realtek/clk-regmap-mux.c b/drivers/clk/realtek/clk-regmap-mux.c
> new file mode 100644
> index 000000000000..068b056d61f0
> --- /dev/null
> +++ b/drivers/clk/realtek/clk-regmap-mux.c
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2017 Realtek Semiconductor Corporation
> + * Author: Cheng-Yu Lee <cylee12@realtek.com>
> + */
> +
> +#include <linux/regmap.h>
> +#include <linux/clk-provider.h>
Sort the includes.
> +#include "clk-regmap-mux.h"
> +
> +static u8 clk_regmap_mux_get_parent(struct clk_hw *hw)
> +{
> + struct clk_regmap_mux *clkm = to_clk_regmap_mux(hw);
> + int num_parents = clk_hw_get_num_parents(hw);
> + u32 val;
> + int ret;
> +
> + ret = regmap_read(clkm->clkr.regmap, clkm->mux_ofs, &val);
> + if (ret)
> + return 0;
This is another case where it'd be nice to get the get_parent
declaration fixed. Stephen recently linked to some work of his from 2022
here.
https://lore.kernel.org/linux-clk/177431305509.5403.15386021337517970667@lazor/
There's nothing for you to do right now.
> +
> + val = val >> clkm->shift & clkm->mask;
I know there's the order of operations, however for clarity I would just
include some () here to make it clear the expected order.
> +
> + if (val >= num_parents)
Remove newline before if.
> + return 0;
> +
> + return val;
Or you could just use a ternary operator:
return val >= num_parents ? 0 : val;
> +}
> +
> +static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> + struct clk_regmap_mux *clkm = to_clk_regmap_mux(hw);
> +
> + return regmap_update_bits(clkm->clkr.regmap, clkm->mux_ofs,
> + clkm->mask << clkm->shift, index << clkm->shift);
> +}
> +
> +const struct clk_ops rtk_clk_regmap_mux_ops = {
> + .set_parent = clk_regmap_mux_set_parent,
> + .get_parent = clk_regmap_mux_get_parent,
> + .determine_rate = __clk_mux_determine_rate,
> +};
> +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_mux_ops, "REALTEK_CLK");
> +
> +const struct clk_ops rtk_clk_regmap_mux_ro_ops = {
> + .get_parent = clk_regmap_mux_get_parent,
> +};
> +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_mux_ro_ops, "REALTEK_CLK");
rtk_clk_regmap_mux_ro_ops is exported, however the declaration is not actually
declared in any header files.
Brian
^ permalink raw reply
* Re: (subset) [PATCH v3 1/5] dt-bindings: rtc: sc2731: Add compatible for SC2730
From: Alexandre Belloni @ 2026-04-03 14:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Orson Zhai,
Baolin Wang, Chunyan Zhang, Lee Jones, Pavel Machek,
Liam Girdwood, Mark Brown, Sebastian Reichel, Otto Pflüger
Cc: linux-rtc, devicetree, linux-kernel, linux-leds, linux-pm
In-Reply-To: <20260329-sc27xx-mfd-cells-v3-1-9158dee41f74@abscue.de>
On Sun, 29 Mar 2026 09:27:45 +0200, Otto Pflüger wrote:
> The RTC block found in the SC2730 PMIC is compatible with the one found
> in the SC2731 PMIC.
Applied, thanks!
[1/5] dt-bindings: rtc: sc2731: Add compatible for SC2730
https://git.kernel.org/abelloni/c/b2b0dcaa28d2
Best regards,
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH v6 04/10] clk: realtek: Add support for phase locked loops (PLLs)
From: Brian Masney @ 2026-04-03 14:44 UTC (permalink / raw)
To: Yu-Chun Lin
Cc: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12,
afaerber, jyanchou, devicetree, linux-clk, linux-kernel,
linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang,
stanley_chang
In-Reply-To: <20260402073957.2742459-5-eleanor.lin@realtek.com>
Hi Cheng-Yu and Yu-Chun,
On Thu, Apr 02, 2026 at 03:39:51PM +0800, Yu-Chun Lin wrote:
> From: Cheng-Yu Lee <cylee12@realtek.com>
>
> Provide a full set of PLL operations for programmable PLLs and a read-only
> variant for fixed or hardware-managed PLLs.
>
> Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com>
> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> ---
> +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_pll *clkp = to_clk_pll(hw);
> + const struct freq_table *fv;
> + int ret;
> +
> + fv = ftbl_find_by_rate(clkp->freq_tbl, rate);
> + if (!fv || fv->rate != rate)
> + return -EINVAL;
> +
> + if (clkp->seq_pre_set_freq) {
> + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_pre_set_freq,
> + clkp->num_seq_pre_set_freq);
> + if (ret)
> + return ret;
> + }
> +
> + ret = regmap_update_bits(clkp->clkr.regmap, clkp->freq_reg,
> + clkp->freq_mask, fv->val);
> + if (ret)
> + return ret;
> +
> + if (clkp->seq_post_set_freq) {
> + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_post_set_freq,
> + clkp->num_seq_post_set_freq);
> + if (ret)
> + return ret;
> + }
> +
> + if (is_power_on(clkp)) {
> + ret = wait_freq_ready(clkp);
I should have checked Sashiko before I hit send on my last review.
https://sashiko.dev/#/patchset/20260402073957.2742459-1-eleanor.lin%40realtek.com
It suggested the following:
In the Common Clock Framework, .set_rate executes under the prepare_lock
mutex, while .enable and .disable execute under the enable_lock spinlock.
Could an interleaved clk_pll_enable() corrupt the hardware state by running
its seq_power_on sequence concurrently with these multi-step register
updates?
There also appears to be a potential race condition later in this function:
if (is_power_on(clkp)) {
ret = wait_freq_ready(clkp);
...
}
If .disable() powers off the PLL right before wait_freq_ready() is called,
will wait_freq_ready() poll a disabled PLL and erroneously return
-ETIMEDOUT? Is a private spinlock needed to serialize these operations?
Brian
^ permalink raw reply
* Re: [PATCH] arm64: dts: ti: k3-j721e-main: Update delay select values for MMC1/2 subsystems
From: Romain Naour @ 2026-04-03 14:42 UTC (permalink / raw)
To: Moteen Shah, devicetree, linux-arm-kernel, linux-omap
Cc: conor+dt, krzk+dt, robh, kristo, vigneshr, nm, stable
In-Reply-To: <8d4a2839-5b1e-479e-a462-dbbc3d016020@ti.com>
Hello Moteen, All,
Le 31/03/2026 à 14:19, Moteen Shah a écrit :
> Hey Romain,
>
> Thanks for the patch
>
> On 19/02/26 02:08, Romain Naour wrote:
>> The previous SPRSP36J datasheet recommends to set ti,otap-del-sel-sd-hs
>> value to 0 for MMC1 and MMC2 interfaces. These values were updated in
>> kernel 6.5. As a result we have some occasional regression with ultra
>> high speed DDR50 SDXC cards while mounting the rootfs:
>
> This error shouldn't be limited to just DDR50, were you seeing similar behavior
> with other speed modes?
I have a followup patch to enable back the SDR104 support with j721e SoC (SR 1.1
and 2.0) and I noticed the same behavior with some "specific" SDcards.
The J721e SR 1.0 doesn't support SDR104 due to an errata.
Nowadays, even the TI J721e EVM board revA (reference board) uses a SR1.1 SoC.
See the post on TI forum with further analysis:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1626659/dra829j-q1-mmcsd-ultra-high-speed-uhs-modes-issues
It turnout that the kernel is not able to detect UHS speed with some SDcards
vendors after uboot initialized them with UHS speed (SDR104). I'm not sure why.
Still, the datasheet was updated with a new set of timing values for HS and
legacy speed.
Maybe I should remove the part about SD card initialization issues, it may be
related to another issue.
>>
>> mmc1: error -110 whilst initialising SD card
>>
>> A similar issue may occur with u-boot after a reboot while
>> initialising the SD card:
>>
>> mmc_init: -110, time 67
>>
>> Update the delay values for legacy and high speed modes, based on
>> the latest revised datasheet SPRSP36K released in April 2024 [1].
>>
>> (MMC1/2 - SD/SDIO Interface): Updated/Changed the
>> "OTAPDLYENA, DELAY ENABLE" and "OTAPDLYSEL, DELAY VALUE" for the
>> Default Speed and High Speed modes from "0x0" to "0x1"
>>
>> [1] Table 6-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in
>> https://www.ti.com/lit/ds/symlink/tda4vm.pdf,
>> (SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024)
>>
>> Cc: stable@vger.kernel.org # 6.5+
>> Fixes: af398252d68e ("arm64: dts: ti: k3-j721e-main: Update delay select
>> values for MMC subsystems")
>> Signed-off-by: Romain Naour <romain.naour@smile.fr>
>> ---
>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/
>> ti/k3-j721e-main.dtsi
>> index d5fd30a01032..418e6010ef1f 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -1643,8 +1643,8 @@ main_sdhci1: mmc@4fb0000 {
>> clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
>> assigned-clocks = <&k3_clks 92 0>;
>> assigned-clock-parents = <&k3_clks 92 1>;
>> - ti,otap-del-sel-legacy = <0x0>;
>> - ti,otap-del-sel-sd-hs = <0x0>;
>> + ti,otap-del-sel-legacy = <0x1>;
>> + ti,otap-del-sel-sd-hs = <0x1>;
>> ti,otap-del-sel-sdr12 = <0xf>;
>> ti,otap-del-sel-sdr25 = <0xf>;
>> ti,otap-del-sel-sdr50 = <0xc>;
>> @@ -1671,8 +1671,8 @@ main_sdhci2: mmc@4f98000 {
>> clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
>> assigned-clocks = <&k3_clks 93 0>;
>> assigned-clock-parents = <&k3_clks 93 1>;
>> - ti,otap-del-sel-legacy = <0x0>;
>> - ti,otap-del-sel-sd-hs = <0x0>;
>> + ti,otap-del-sel-legacy = <0x1>;
>> + ti,otap-del-sel-sd-hs = <0x1>;
>> ti,otap-del-sel-sdr12 = <0xf>;
>> ti,otap-del-sel-sdr25 = <0xf>;
>> ti,otap-del-sel-sdr50 = <0xc>;
>
>
> Reviewed-by: Moteen Shah <m-shah@ti.com>
Thanks!
Best regards,
Romain
>
> Regards,
> Moteen
>
^ permalink raw reply
* Re: [PATCH 1/1] dt-bindings: timer: fsl,imxgpt: add compatible string fsl,imx25-epit
From: Daniel Lezcano @ 2026-04-03 14:40 UTC (permalink / raw)
To: Mark Brown
Cc: Frank Li, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
open list:CLOCKSOURCE, CLOCKEVENT DRIVERS,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Stephen Rothwell
In-Reply-To: <3ba9e33e-8d58-469c-9c21-5861c0f6c5eb@sirena.org.uk>
On 4/3/26 13:43, Mark Brown wrote:
> On Fri, Apr 03, 2026 at 10:15:49AM +0200, Daniel Lezcano wrote:
>> On 4/3/26 10:00, Frank Li wrote:
>
>>> Can't find it at linux-next master branch, anything wrong!
>
>> The patch is in timer/next but may be linux-next disabled my branch
>
> I have a timers/drivers/next branch in your git tree in -next but
> no record of anything else. That branch was last updated on January
> 20th. If you want something else adding let me know.
No it is ok, I had a confusion in my branches. I updated the wrong one.
Now it is fixed.
Thanks
^ permalink raw reply
* Re: [PATCH v6 05/10] clk: realtek: Add support for gate clock
From: Brian Masney @ 2026-04-03 14:40 UTC (permalink / raw)
To: Yu-Chun Lin
Cc: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12,
afaerber, jyanchou, devicetree, linux-clk, linux-kernel,
linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang,
stanley_chang
In-Reply-To: <20260402073957.2742459-6-eleanor.lin@realtek.com>
Hi Cheng-Yu,
On Thu, Apr 02, 2026 at 03:39:52PM +0800, Yu-Chun Lin wrote:
> From: Cheng-Yu Lee <cylee12@realtek.com>
>
> Introduce clk_regmap_gate_ops supporting enable, disable, is_enabled, and
> disable_unused for standard regmap gate clocks.
disable_unused is not implemented below.
>
> Add clk_regmap_gate_ro_ops as a read-only variant exposing only is_enabled.
>
> Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com>
> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> ---
> Changes in v6:
> - Add the headers used in c file to follow the "Include What You Use" principle.
> ---
> drivers/clk/realtek/Makefile | 2 +
> drivers/clk/realtek/clk-regmap-gate.c | 69 +++++++++++++++++++++++++++
> drivers/clk/realtek/clk-regmap-gate.h | 65 +++++++++++++++++++++++++
> 3 files changed, 136 insertions(+)
> create mode 100644 drivers/clk/realtek/clk-regmap-gate.c
> create mode 100644 drivers/clk/realtek/clk-regmap-gate.h
>
> diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
> index a89ad77993e9..74375f8127ac 100644
> --- a/drivers/clk/realtek/Makefile
> +++ b/drivers/clk/realtek/Makefile
> @@ -2,5 +2,7 @@
> obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o
>
> clk-rtk-y += common.o
> +
> clk-rtk-y += clk-pll.o
> +clk-rtk-y += clk-regmap-gate.o
> clk-rtk-y += freq_table.o
> diff --git a/drivers/clk/realtek/clk-regmap-gate.c b/drivers/clk/realtek/clk-regmap-gate.c
> new file mode 100644
> index 000000000000..8738d6c6f8dd
> --- /dev/null
> +++ b/drivers/clk/realtek/clk-regmap-gate.c
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2017 Realtek Semiconductor Corporation
> + * Author: Cheng-Yu Lee <cylee12@realtek.com>
> + */
> +
> +#include <linux/regmap.h>
> +#include <linux/bits.h>
> +#include "clk-regmap-gate.h"
> +#include <linux/clk-provider.h>
linux/clk-provider.h needs to be included before clk-regmap-gate.h.
Also Sashiko reports that linux/export.h should also be included.
https://sashiko.dev/#/patchset/20260402073957.2742459-1-eleanor.lin%40realtek.com
Brian
^ permalink raw reply
* Re: [PATCH v6 04/10] clk: realtek: Add support for phase locked loops (PLLs)
From: Brian Masney @ 2026-04-03 14:34 UTC (permalink / raw)
To: Yu-Chun Lin
Cc: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12,
afaerber, jyanchou, devicetree, linux-clk, linux-kernel,
linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang,
stanley_chang
In-Reply-To: <20260402073957.2742459-5-eleanor.lin@realtek.com>
Hi Cheng-Yu,
On Thu, Apr 02, 2026 at 03:39:51PM +0800, Yu-Chun Lin wrote:
> From: Cheng-Yu Lee <cylee12@realtek.com>
>
> Provide a full set of PLL operations for programmable PLLs and a read-only
> variant for fixed or hardware-managed PLLs.
>
> Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com>
> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> ---
> Changes in v6:
> - Add the headers used in c file to follow the "Include What You Use" principle.
> - Move to_clk_pll() from clk-pll.h to clk-pll.c to limit its scope.
> ---
> drivers/clk/realtek/Makefile | 2 +
> drivers/clk/realtek/clk-pll.c | 164 +++++++++++++++++++++++++++++++
> drivers/clk/realtek/clk-pll.h | 42 ++++++++
> drivers/clk/realtek/freq_table.c | 36 +++++++
> drivers/clk/realtek/freq_table.h | 21 ++++
> 5 files changed, 265 insertions(+)
> create mode 100644 drivers/clk/realtek/clk-pll.c
> create mode 100644 drivers/clk/realtek/clk-pll.h
> create mode 100644 drivers/clk/realtek/freq_table.c
> create mode 100644 drivers/clk/realtek/freq_table.h
>
> diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
> index 377ec776ee47..a89ad77993e9 100644
> --- a/drivers/clk/realtek/Makefile
> +++ b/drivers/clk/realtek/Makefile
> @@ -2,3 +2,5 @@
> obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o
>
> clk-rtk-y += common.o
> +clk-rtk-y += clk-pll.o
> +clk-rtk-y += freq_table.o
> diff --git a/drivers/clk/realtek/clk-pll.c b/drivers/clk/realtek/clk-pll.c
> new file mode 100644
> index 000000000000..44730b22a94c
> --- /dev/null
> +++ b/drivers/clk/realtek/clk-pll.c
> @@ -0,0 +1,164 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2024 Realtek Semiconductor Corporation
> + * Author: Cheng-Yu Lee <cylee12@realtek.com>
> + */
> +
> +#include <linux/regmap.h>
> +#include "clk-pll.h"
> +
> +#define TIMEOUT 2000
> +
> +static inline struct clk_pll *to_clk_pll(struct clk_hw *hw)
> +{
> + struct clk_regmap *clkr = to_clk_regmap(hw);
> +
> + return container_of(clkr, struct clk_pll, clkr);
> +}
> +
> +static int wait_freq_ready(struct clk_pll *clkp)
> +{
> + u32 pollval;
> +
> + if (!clkp->freq_ready_valid)
> + return 0;
> +
> + return regmap_read_poll_timeout_atomic(clkp->clkr.regmap, clkp->freq_ready_reg, pollval,
> + (pollval & clkp->freq_ready_mask)
> + == clkp->freq_ready_val, 0, TIMEOUT);
I would put the "(pollval & clkp->freq_ready_mask) == clkp->freq_ready_val" on
the same line to improve readability. You can go out to 100 characters.
Also should the delay be greater than 0 to avoid tons of constant
retries?
> +}
> +
> +static bool is_power_on(struct clk_pll *clkp)
> +{
> + u32 val;
> +
> + if (!clkp->power_reg)
> + return true;
> +
> + if (regmap_read(clkp->clkr.regmap, clkp->power_reg, &val))
> + return true;
Is the intention if there is an error, then it marks it as success?
> +
> + return (val & clkp->power_mask) == clkp->power_val_on;
> +}
> +
> +static void clk_pll_disable(struct clk_hw *hw)
> +{
> + struct clk_pll *clkp = to_clk_pll(hw);
> +
> + if (!clkp->seq_power_off)
> + return;
> +
> + regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_power_off,
> + clkp->num_seq_power_off);
> +}
> +
> +static int clk_pll_is_enabled(struct clk_hw *hw)
> +{
> + struct clk_pll *clkp = to_clk_pll(hw);
> +
> + return is_power_on(clkp);
> +}
> +
> +static int clk_pll_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + struct clk_pll *clkp = to_clk_pll(hw);
> + const struct freq_table *ftblv = NULL;
> +
> + ftblv = ftbl_find_by_rate(clkp->freq_tbl, req->rate);
> + if (!ftblv)
> + return -EINVAL;
> +
> + req->rate = ftblv->rate;
> + return 0;
Add newline before return.
> +}
> +
> +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct clk_pll *clkp = to_clk_pll(hw);
> + const struct freq_table *fv;
> + u32 freq_val;
> +
> + if (regmap_read(clkp->clkr.regmap, clkp->freq_reg, &freq_val))
> + return 0;
> +
> + freq_val &= clkp->freq_mask;
> +
> + fv = ftbl_find_by_val_with_mask(clkp->freq_tbl, clkp->freq_mask,
> + freq_val);
> + return fv ? fv->rate : 0;
Add newline before return.
> +}
> +
> +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_pll *clkp = to_clk_pll(hw);
> + const struct freq_table *fv;
> + int ret;
> +
> + fv = ftbl_find_by_rate(clkp->freq_tbl, rate);
> + if (!fv || fv->rate != rate)
> + return -EINVAL;
> +
> + if (clkp->seq_pre_set_freq) {
> + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_pre_set_freq,
> + clkp->num_seq_pre_set_freq);
> + if (ret)
> + return ret;
> + }
> +
> + ret = regmap_update_bits(clkp->clkr.regmap, clkp->freq_reg,
> + clkp->freq_mask, fv->val);
> + if (ret)
> + return ret;
> +
> + if (clkp->seq_post_set_freq) {
> + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_post_set_freq,
> + clkp->num_seq_post_set_freq);
> + if (ret)
> + return ret;
> + }
> +
> + if (is_power_on(clkp)) {
> + ret = wait_freq_ready(clkp);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int clk_pll_enable(struct clk_hw *hw)
> +{
> + struct clk_pll *clkp = to_clk_pll(hw);
> + int ret;
> +
> + if (!clkp->seq_power_on)
> + return 0;
> +
> + if (is_power_on(clkp))
> + return 0;
> +
> + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_power_on,
> + clkp->num_seq_power_on);
> + if (ret)
> + return ret;
> +
> + return wait_freq_ready(clkp);
> +}
> +
> +const struct clk_ops rtk_clk_pll_ops = {
> + .enable = clk_pll_enable,
> + .disable = clk_pll_disable,
> + .is_enabled = clk_pll_is_enabled,
> + .recalc_rate = clk_pll_recalc_rate,
> + .determine_rate = clk_pll_determine_rate,
> + .set_rate = clk_pll_set_rate,
> +};
> +EXPORT_SYMBOL_NS_GPL(rtk_clk_pll_ops, "REALTEK_CLK");
> +
> +const struct clk_ops rtk_clk_pll_ro_ops = {
> + .recalc_rate = clk_pll_recalc_rate,
> +};
> +EXPORT_SYMBOL_NS_GPL(rtk_clk_pll_ro_ops, "REALTEK_CLK");
> diff --git a/drivers/clk/realtek/clk-pll.h b/drivers/clk/realtek/clk-pll.h
> new file mode 100644
> index 000000000000..00884585a242
> --- /dev/null
> +++ b/drivers/clk/realtek/clk-pll.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2017-2019 Realtek Semiconductor Corporation
> + * Author: Cheng-Yu Lee <cylee12@realtek.com>
> + */
> +
> +#ifndef __CLK_REALTEK_CLK_PLL_H
> +#define __CLK_REALTEK_CLK_PLL_H
> +
> +#include "common.h"
> +#include "freq_table.h"
> +
> +struct reg_sequence;
> +
> +struct clk_pll {
> + struct clk_regmap clkr;
> + const struct reg_sequence *seq_power_on;
> + u32 num_seq_power_on;
> + const struct reg_sequence *seq_power_off;
> + u32 num_seq_power_off;
> + const struct reg_sequence *seq_pre_set_freq;
> + u32 num_seq_pre_set_freq;
> + const struct reg_sequence *seq_post_set_freq;
> + u32 num_seq_post_set_freq;
> + const struct freq_table *freq_tbl;
> + u32 freq_reg;
> + u32 freq_mask;
> + u32 freq_ready_valid;
> + u32 freq_ready_mask;
> + u32 freq_ready_reg;
> + u32 freq_ready_val;
> + u32 power_reg;
> + u32 power_mask;
> + u32 power_val_on;
> +};
> +
> +#define __clk_pll_hw(_ptr) __clk_regmap_hw(&(_ptr)->clkr)
> +
> +extern const struct clk_ops rtk_clk_pll_ops;
> +extern const struct clk_ops rtk_clk_pll_ro_ops;
> +
> +#endif /* __CLK_REALTEK_CLK_PLL_H */
> diff --git a/drivers/clk/realtek/freq_table.c b/drivers/clk/realtek/freq_table.c
> new file mode 100644
> index 000000000000..272a10e75a54
> --- /dev/null
> +++ b/drivers/clk/realtek/freq_table.c
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#include <linux/bitops.h>
> +#include "freq_table.h"
> +
> +const struct freq_table *ftbl_find_by_rate(const struct freq_table *ftbl,
> + unsigned long rate)
> +{
> + unsigned long best_rate = 0;
> + const struct freq_table *best = NULL;
Put variables in reverse Christmas tree order.
> +
> + for (; !IS_FREQ_TABLE_END(ftbl); ftbl++) {
> + if (ftbl->rate == rate)
> + return ftbl;
> +
> + if (ftbl->rate > rate)
> + continue;
> +
> + if (ftbl->rate > best_rate) {
> + best_rate = ftbl->rate;
> + best = ftbl;
> + }
> + }
> +
> + return best;
> +}
> +
> +const struct freq_table *
> +ftbl_find_by_val_with_mask(const struct freq_table *ftbl, u32 mask, u32 value)
> +{
> + for (; !IS_FREQ_TABLE_END(ftbl); ftbl++) {
> + if ((ftbl->val & mask) == (value & mask))
> + return ftbl;
> + }
> + return NULL;
> +};
> diff --git a/drivers/clk/realtek/freq_table.h b/drivers/clk/realtek/freq_table.h
> new file mode 100644
> index 000000000000..6d9116651105
> --- /dev/null
> +++ b/drivers/clk/realtek/freq_table.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +struct freq_table {
> + u32 val;
> + unsigned long rate;
> +};
> +
> +/* ofs check */
> +#define CLK_OFS_INVALID -1
> +#define CLK_OFS_IS_VALID(_ofs) ((_ofs) != CLK_OFS_INVALID)
Is this used anywhere?
Brian
> +
> +#define FREQ_TABLE_END \
> + { \
> + .rate = 0 \
> + }
> +#define IS_FREQ_TABLE_END(_f) ((_f)->rate == 0)
> +
> +const struct freq_table *ftbl_find_by_rate(const struct freq_table *ftbl,
> + unsigned long rate);
> +const struct freq_table *
> +ftbl_find_by_val_with_mask(const struct freq_table *ftbl, u32 mask, u32 value);
> --
> 2.34.1
>
^ permalink raw reply
* [PATCH 3/3] arm64: dts: broadcom: rp1: Add PWM node
From: Andrea della Porta @ 2026-04-03 14:31 UTC (permalink / raw)
To: Uwe Kleine-König, linux-pwm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, Andrea della Porta,
devicetree, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Naushir Patuck, Stanimir Varbanov
In-Reply-To: <cover.1775223441.git.andrea.porta@suse.com>
From: Stanimir Varbanov <svarbanov@suse.de>
The RP1 chipset used on the Raspberry Pi 5 features an integrated
PWM controller to drive the cooling fan.
Add the corresponding DT node for this PWM controller.
Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
Co-developed-by: Andrea della Porta <andrea.porta@suse.com>
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
---
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 12 ++++++++++++
arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 10 ++++++++++
2 files changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
index 2856082814462..a4e5ba23bf536 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
@@ -64,12 +64,24 @@ phy1: ethernet-phy@1 {
};
&rp1_gpio {
+ fan_pwm_default_state: fan-pwm-default-state {
+ function = "pwm1";
+ pins = "gpio45";
+ bias-pull-down;
+ };
+
usb_vbus_default_state: usb-vbus-default-state {
function = "vbus1";
groups = "vbus1";
};
};
+&rp1_pwm {
+ pinctrl-0 = <&fan_pwm_default_state>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&rp1_usb0 {
pinctrl-0 = <&usb_vbus_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
index 5a815c3797945..7e78501e62b0c 100644
--- a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
+++ b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
@@ -56,6 +56,16 @@ rp1_eth: ethernet@40100000 {
#size-cells = <0>;
};
+ rp1_pwm: pwm@4009c000 {
+ compatible = "raspberrypi,rp1-pwm";
+ reg = <0x00 0x4009c000 0x0 0x100>;
+ clocks = <&rp1_clocks RP1_CLK_PWM1>;
+ assigned-clocks = <&rp1_clocks RP1_CLK_PWM1>;
+ assigned-clock-rates = <50000000>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
rp1_usb0: usb@40200000 {
compatible = "snps,dwc3";
reg = <0x00 0x40200000 0x0 0x100000>;
--
2.35.3
^ permalink raw reply related
* [PATCH 2/3] pwm: rp1: Add RP1 PWM controller driver
From: Andrea della Porta @ 2026-04-03 14:31 UTC (permalink / raw)
To: Uwe Kleine-König, linux-pwm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, Andrea della Porta,
devicetree, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Naushir Patuck, Stanimir Varbanov
In-Reply-To: <cover.1775223441.git.andrea.porta@suse.com>
From: Naushir Patuck <naush@raspberrypi.com>
The Raspberry Pi RP1 southbridge features an embedded PWM
controller with 4 output channels, alongside an RPM interface
to read the fan speed on the Raspberry Pi 5.
Add the supporting driver.
Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
Co-developed-by: Stanimir Varbanov <svarbanov@suse.de>
Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
---
drivers/pwm/Kconfig | 10 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-rp1.c | 244 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 255 insertions(+)
create mode 100644 drivers/pwm/pwm-rp1.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 6f3147518376a..22e4fc6385da2 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -625,6 +625,16 @@ config PWM_ROCKCHIP
Generic PWM framework driver for the PWM controller found on
Rockchip SoCs.
+config PWM_RP1
+ tristate "RP1 PWM support"
+ depends on MISC_RP1 || COMPILE_TEST
+ depends on HWMON
+ help
+ PWM framework driver for Raspberry Pi RP1 controller
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-rp1.
+
config PWM_SAMSUNG
tristate "Samsung PWM support"
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 0dc0d2b69025d..895a7c42fe9c0 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_PWM_RENESAS_RZG2L_GPT) += pwm-rzg2l-gpt.o
obj-$(CONFIG_PWM_RENESAS_RZ_MTU3) += pwm-rz-mtu3.o
obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
+obj-$(CONFIG_PWM_RP1) += pwm-rp1.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
diff --git a/drivers/pwm/pwm-rp1.c b/drivers/pwm/pwm-rp1.c
new file mode 100644
index 0000000000000..0a1c1c1dd27e9
--- /dev/null
+++ b/drivers/pwm/pwm-rp1.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * pwm-rp1.c
+ *
+ * Raspberry Pi RP1 PWM.
+ *
+ * Copyright © 2026 Raspberry Pi Ltd.
+ *
+ * Author: Naushir Patuck (naush@raspberrypi.com)
+ *
+ * Based on the pwm-bcm2835 driver by:
+ * Bart Tanghe <bart.tanghe@thomasmore.be>
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/hwmon.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+
+#define PWM_GLOBAL_CTRL 0x000
+#define PWM_CHANNEL_CTRL(x) (0x014 + ((x) * 0x10))
+#define PWM_RANGE(x) (0x018 + ((x) * 0x10))
+#define PWM_PHASE(x) (0x01C + ((x) * 0x10))
+#define PWM_DUTY(x) (0x020 + ((x) * 0x10))
+
+/* 8:FIFO_POP_MASK + 0:Trailing edge M/S modulation */
+#define PWM_CHANNEL_DEFAULT (BIT(8) + BIT(0))
+#define PWM_CHANNEL_ENABLE(x) BIT(x)
+#define PWM_POLARITY BIT(3)
+#define SET_UPDATE BIT(31)
+#define PWM_MODE_MASK GENMASK(1, 0)
+
+#define NUM_PWMS 4
+
+struct rp1_pwm {
+ void __iomem *base;
+ struct clk *clk;
+};
+
+static const struct hwmon_channel_info * const rp1_fan_hwmon_info[] = {
+ HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT),
+ NULL
+};
+
+static umode_t rp1_fan_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+ umode_t mode = 0;
+
+ if (type == hwmon_fan && attr == hwmon_fan_input)
+ mode = 0444;
+
+ return mode;
+}
+
+static int rp1_fan_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
+ u32 attr, int channel, long *val)
+{
+ struct rp1_pwm *rp1 = dev_get_drvdata(dev);
+
+ if (type != hwmon_fan || attr != hwmon_fan_input)
+ return -EOPNOTSUPP;
+
+ *val = readl(rp1->base + PWM_PHASE(2));
+
+ return 0;
+}
+
+static const struct hwmon_ops rp1_fan_hwmon_ops = {
+ .is_visible = rp1_fan_hwmon_is_visible,
+ .read = rp1_fan_hwmon_read,
+};
+
+static const struct hwmon_chip_info rp1_fan_hwmon_chip_info = {
+ .ops = &rp1_fan_hwmon_ops,
+ .info = rp1_fan_hwmon_info,
+};
+
+static void rp1_pwm_apply_config(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);
+ u32 value;
+
+ value = readl(rp1->base + PWM_GLOBAL_CTRL);
+ value |= SET_UPDATE;
+ writel(value, rp1->base + PWM_GLOBAL_CTRL);
+}
+
+static int rp1_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);
+
+ writel(PWM_CHANNEL_DEFAULT, rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
+ return 0;
+}
+
+static void rp1_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);
+ u32 value;
+
+ value = readl(rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
+ value &= ~PWM_MODE_MASK;
+ writel(value, rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
+
+ rp1_pwm_apply_config(chip, pwm);
+}
+
+static int rp1_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);
+ unsigned long clk_rate = clk_get_rate(rp1->clk);
+ unsigned long clk_period;
+ u32 value;
+
+ if (!clk_rate) {
+ dev_err(&chip->dev, "failed to get clock rate\n");
+ return -EINVAL;
+ }
+
+ /* set period and duty cycle */
+ clk_period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, clk_rate);
+
+ writel(DIV_ROUND_CLOSEST(state->duty_cycle, clk_period),
+ rp1->base + PWM_DUTY(pwm->hwpwm));
+
+ writel(DIV_ROUND_CLOSEST(state->period, clk_period),
+ rp1->base + PWM_RANGE(pwm->hwpwm));
+
+ /* set polarity */
+ value = readl(rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
+ if (state->polarity == PWM_POLARITY_NORMAL)
+ value &= ~PWM_POLARITY;
+ else
+ value |= PWM_POLARITY;
+ writel(value, rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
+
+ /* enable/disable */
+ value = readl(rp1->base + PWM_GLOBAL_CTRL);
+ if (state->enabled)
+ value |= PWM_CHANNEL_ENABLE(pwm->hwpwm);
+ else
+ value &= ~PWM_CHANNEL_ENABLE(pwm->hwpwm);
+ writel(value, rp1->base + PWM_GLOBAL_CTRL);
+
+ rp1_pwm_apply_config(chip, pwm);
+
+ return 0;
+}
+
+static const struct pwm_ops rp1_pwm_ops = {
+ .request = rp1_pwm_request,
+ .free = rp1_pwm_free,
+ .apply = rp1_pwm_apply,
+};
+
+static int rp1_pwm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device *hwmon_dev;
+ struct pwm_chip *chip;
+ struct rp1_pwm *rp1;
+ int ret;
+
+ chip = devm_pwmchip_alloc(dev, NUM_PWMS, sizeof(*rp1));
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
+
+ rp1 = pwmchip_get_drvdata(chip);
+
+ rp1->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rp1->base))
+ return PTR_ERR(rp1->base);
+
+ rp1->clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(rp1->clk))
+ return dev_err_probe(dev, PTR_ERR(rp1->clk), "clock not found\n");
+
+ ret = devm_clk_rate_exclusive_get(dev, rp1->clk);
+ if (ret)
+ return dev_err_probe(dev, ret, "fail to get exclusive rate\n");
+
+ chip->ops = &rp1_pwm_ops;
+
+ platform_set_drvdata(pdev, chip);
+
+ ret = devm_pwmchip_add(dev, chip);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register PWM chip\n");
+
+ hwmon_dev = devm_hwmon_device_register_with_info(dev, "rp1_fan_tach", rp1,
+ &rp1_fan_hwmon_chip_info,
+ NULL);
+
+ if (IS_ERR(hwmon_dev))
+ return dev_err_probe(dev, PTR_ERR(hwmon_dev),
+ "failed to register hwmon fan device\n");
+
+ return 0;
+}
+
+static int rp1_pwm_suspend(struct device *dev)
+{
+ struct rp1_pwm *rp1 = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(rp1->clk);
+
+ return 0;
+}
+
+static int rp1_pwm_resume(struct device *dev)
+{
+ struct rp1_pwm *rp1 = dev_get_drvdata(dev);
+
+ return clk_prepare_enable(rp1->clk);
+}
+
+static DEFINE_SIMPLE_DEV_PM_OPS(rp1_pwm_pm_ops, rp1_pwm_suspend, rp1_pwm_resume);
+
+static const struct of_device_id rp1_pwm_of_match[] = {
+ { .compatible = "raspberrypi,rp1-pwm" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rp1_pwm_of_match);
+
+static struct platform_driver rp1_pwm_driver = {
+ .probe = rp1_pwm_probe,
+ .driver = {
+ .name = "rp1-pwm",
+ .of_match_table = rp1_pwm_of_match,
+ .pm = pm_ptr(&rp1_pwm_pm_ops),
+ },
+};
+module_platform_driver(rp1_pwm_driver);
+
+MODULE_DESCRIPTION("RP1 PWM driver");
+MODULE_AUTHOR("Naushir Patuck <naush@raspberrypi.com>");
+MODULE_LICENSE("GPL");
--
2.35.3
^ permalink raw reply related
* [PATCH 1/3] dt-bindings: pwm: Add Raspberry Pi RP1 PWM controller
From: Andrea della Porta @ 2026-04-03 14:31 UTC (permalink / raw)
To: Uwe Kleine-König, linux-pwm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, Andrea della Porta,
devicetree, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Naushir Patuck, Stanimir Varbanov
In-Reply-To: <cover.1775223441.git.andrea.porta@suse.com>
From: Naushir Patuck <naush@raspberrypi.com>
Add the devicetree binding documentation for the PWM
controller found in the Raspberry Pi RP1 chipset.
Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
Co-developed-by: Stanimir Varbanov <svarbanov@suse.de>
Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
---
.../bindings/pwm/raspberrypi,rp1-pwm.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/raspberrypi,rp1-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/raspberrypi,rp1-pwm.yaml b/Documentation/devicetree/bindings/pwm/raspberrypi,rp1-pwm.yaml
new file mode 100644
index 0000000000000..d6b3f52561636
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/raspberrypi,rp1-pwm.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/raspberrypi,rp1-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Raspberry Pi RP1 PWM controller
+
+maintainers:
+ - Naushir Patuck <naush@raspberrypi.com>
+
+allOf:
+ - $ref: pwm.yaml#
+
+description: |
+ The PWM peripheral is a flexible waveform generator with a
+ variety of operational modes. It has the following features:
+ - four independent output channels
+ - 32-bit counter widths
+ - Seven output generation modes
+ - Optional per-channel output inversion
+ - Optional duty-cycle data FIFO with DMA support
+ - Optional sigma-delta noise shaping engine
+
+properties:
+ compatible:
+ const: raspberrypi,rp1-pwm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm@98000 {
+ compatible = "raspberrypi,rp1-pwm";
+ reg = <0x98000 0x100>;
+ clocks = <&rp1_clocks 17>;
+ #pwm-cells = <3>;
+ };
--
2.35.3
^ permalink raw reply related
* [PATCH 0/3] Add RP1 PWM controller support
From: Andrea della Porta @ 2026-04-03 14:31 UTC (permalink / raw)
To: Uwe Kleine-König, linux-pwm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, Andrea della Porta,
devicetree, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Naushir Patuck, Stanimir Varbanov
This patchset adds support for the PWM controller found on the
Raspberry Pi RP1 southbridge. This is necessary to operate the
cooling fan connected to one of the PWM channels.
The tachometer pin for the fan speed is managed by the firmware
running on the RP1's M-core. It uses the PHASE2 register
to report the RPM, which is then exported by this driver as a
hwmon device.
Subsequent patches will add the CPU thermal zone, which acts as
a consumer of the PWM device.
Best regards,
Andrea
Naushir Patuck (2):
dt-bindings: pwm: Add Raspberry Pi RP1 PWM controller
pwm: rp1: Add RP1 PWM controller driver
Stanimir Varbanov (1):
arm64: dts: broadcom: rp1: Add PWM node
.../bindings/pwm/raspberrypi,rp1-pwm.yaml | 52 ++++
.../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 12 +
arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 10 +
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-rp1.c | 244 ++++++++++++++++++
6 files changed, 329 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/raspberrypi,rp1-pwm.yaml
create mode 100644 drivers/pwm/pwm-rp1.c
--
2.35.3
^ permalink raw reply
* Re: [PATCH v6 03/10] clk: realtek: Introduce a common probe()
From: Brian Masney @ 2026-04-03 14:21 UTC (permalink / raw)
To: Yu-Chun Lin
Cc: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12,
afaerber, jyanchou, devicetree, linux-clk, linux-kernel,
linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang,
stanley_chang
In-Reply-To: <20260402073957.2742459-4-eleanor.lin@realtek.com>
Hi Cheng-Yu,
On Thu, Apr 02, 2026 at 03:39:50PM +0800, Cheng-Yu Lee wrote:
> Add rtk_clk_probe() to set up the shared regmap, register clock hardware,
> and add the clock provider.
>
> Additionally, if the "#reset-cells" property is present in the device tree,
> it creates and registers an auxiliary device using the provided aux_name.
> This allows the dedicated reset driver to bind to this device, enabling
> both clock and reset drivers to share the same regmap.
>
> Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com>
> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> ---
> Changes in v6:
> - Replace direct reset controller initialization with auxiliary device creation.
> - Add aux_name parameter to rtk_clk_probe() to register the reset auxiliary device.
> - Simplify rtk_clk_desc because reset data is handled entirely by the auxiliary reset driver.
> - In Kconfig, change "depends on RESET_CONTROLLER" to "select RESET_CONTROLLER"
> - Remove unused includes headers and added <linux/auxiliary_bus.h>.
> ---
> MAINTAINERS | 1 +
> drivers/clk/Kconfig | 1 +
> drivers/clk/Makefile | 1 +
> drivers/clk/realtek/Kconfig | 28 +++++++++++++++
> drivers/clk/realtek/Makefile | 4 +++
> drivers/clk/realtek/common.c | 67 ++++++++++++++++++++++++++++++++++++
> drivers/clk/realtek/common.h | 37 ++++++++++++++++++++
> 7 files changed, 139 insertions(+)
> create mode 100644 drivers/clk/realtek/Kconfig
> create mode 100644 drivers/clk/realtek/Makefile
> create mode 100644 drivers/clk/realtek/common.c
> create mode 100644 drivers/clk/realtek/common.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8f355896583b..8318156a02b5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -22240,6 +22240,7 @@ L: devicetree@vger.kernel.org
> L: linux-clk@vger.kernel.org
> S: Supported
> F: Documentation/devicetree/bindings/clock/realtek*
> +F: drivers/clk/realtek/*
> F: drivers/reset/realtek/*
> F: include/dt-bindings/clock/realtek*
> F: include/dt-bindings/reset/realtek*
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 3d803b4cf5c1..d60f6415b0a3 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -519,6 +519,7 @@ source "drivers/clk/nuvoton/Kconfig"
> source "drivers/clk/pistachio/Kconfig"
> source "drivers/clk/qcom/Kconfig"
> source "drivers/clk/ralink/Kconfig"
> +source "drivers/clk/realtek/Kconfig"
> source "drivers/clk/renesas/Kconfig"
> source "drivers/clk/rockchip/Kconfig"
> source "drivers/clk/samsung/Kconfig"
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index f7bce3951a30..69b84d1e7bcc 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -140,6 +140,7 @@ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/
> obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
> obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
> obj-y += ralink/
> +obj-$(CONFIG_COMMON_CLK_REALTEK) += realtek/
> obj-y += renesas/
> obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
> obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
> diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig
> new file mode 100644
> index 000000000000..bc47d3f1c452
> --- /dev/null
> +++ b/drivers/clk/realtek/Kconfig
> @@ -0,0 +1,28 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +config COMMON_CLK_REALTEK
> + bool "Clock driver for Realtek SoCs"
> + depends on ARCH_REALTEK || COMPILE_TEST
> + default ARCH_REALTEK
> + help
> + Enable the common clock framework infrastructure for Realtek
> + system-on-chip platforms.
> +
> + This provides the base support required by individual Realtek
> + clock controller drivers to expose clocks to peripheral devices.
> +
> + If you have a Realtek-based platform, say Y.
> +
> +if COMMON_CLK_REALTEK
> +
> +config RTK_CLK_COMMON
> + tristate "Realtek Clock Common"
> + select RESET_CONTROLLER
> + select RESET_RTK_COMMON
select AUXILIARY_BUS ?
> + help
> + Common helper code shared by Realtek clock controller drivers.
> +
> + This provides utility functions and data structures used by
> + multiple Realtek clock implementations, and include integration
> + with reset controllers where required.
> +
> +endif
> diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
> new file mode 100644
> index 000000000000..377ec776ee47
> --- /dev/null
> +++ b/drivers/clk/realtek/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o
> +
> +clk-rtk-y += common.o
> diff --git a/drivers/clk/realtek/common.c b/drivers/clk/realtek/common.c
> new file mode 100644
> index 000000000000..c5aea15a3714
> --- /dev/null
> +++ b/drivers/clk/realtek/common.c
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2019 Realtek Semiconductor Corporation
If you are making changes here, should the copyrights be updated to
include 2026?
> + * Author: Cheng-Yu Lee <cylee12@realtek.com>
> + */
> +
> +#include <linux/auxiliary_bus.h>
> +#include <linux/device.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include "common.h"
> +
> +static int rtk_reset_controller_register(struct device *dev, const char *aux_name)
> +{
> + struct auxiliary_device *adev;
> +
> + if (!of_property_present(dev->of_node, "#reset-cells"))
> + return 0;
> +
> + adev = devm_auxiliary_device_create(dev, aux_name, NULL);
> +
> + if (IS_ERR(adev))
> + return PTR_ERR(adev);
> + return 0;
Add newline before return.
> +}
> +
> +int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc *desc,
> + const char *aux_name)
> +{
> + int i, ret;
> + struct regmap *regmap;
> + struct device *dev = &pdev->dev;
Put variables in reverse Christmas tree order.
> +
> + regmap = device_node_to_regmap(pdev->dev.of_node);
> + if (IS_ERR(regmap))
> + return dev_err_probe(dev, PTR_ERR(regmap), "failed to get regmap\n");
> +
> + for (i = 0; i < desc->num_clks; i++)
> + desc->clks[i]->regmap = regmap;
> +
> + for (i = 0; i < desc->clk_data->num; i++) {
> + struct clk_hw *hw = desc->clk_data->hws[i];
> +
> + if (!hw)
> + continue;
> +
> + ret = devm_clk_hw_register(dev, hw);
> +
> + if (ret) {
Remove newline before if.
> + dev_warn(dev, "failed to register hw of clk%d: %d\n", i,
> + ret);
> + desc->clk_data->hws[i] = NULL;
This chunk doesn't take into account probe deferrals.
Brian
^ permalink raw reply
* Re: [PATCH v7 1/3] soc: qcom: ice: Add OPP-based clock scaling support for ICE
From: Abhinaba Rakshit @ 2026-04-03 14:17 UTC (permalink / raw)
To: Harshal Dev
Cc: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Manivannan Sadhasivam, James E.J. Bottomley, Martin K. Petersen,
Neeraj Soni, linux-arm-msm, linux-crypto, devicetree,
linux-kernel, linux-scsi
In-Reply-To: <a616c056-f9aa-420c-a543-7f1539e9e886@oss.qualcomm.com>
On Mon, Mar 30, 2026 at 08:09:35PM +0530, Harshal Dev wrote:
> > +/**
> > + * qcom_ice_scale_clk() - Scale ICE clock for DVFS-aware operations
> > + * @ice: ICE driver data
> > + * @target_freq: requested frequency in Hz
> > + * @round_ceil: when true, selects nearest freq >= @target_freq;
> > + * otherwise, selects nearest freq <= @target_freq
> > + *
> > + * Selects an OPP frequency based on @target_freq and the rounding direction
> > + * specified by @round_ceil, then programs it using dev_pm_opp_set_rate(),
> > + * including any voltage or power-domain transitions handled by the OPP
> > + * framework. Updates ice->core_clk_freq on success.
> > + *
> > + * Return: 0 on success; -EOPNOTSUPP if no OPP table; -EINVAL in-case of
> > + * incorrect flags; or error from dev_pm_opp_set_rate()/OPP lookup.
> > + */
> > +int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq,
> > + bool round_ceil)
>
> Any particular reason for choosing round_ceil? Using round_floor would have
> saved the need for caller to pass negation of scale_up.
There isn’t a strong technical reason for choosing round_ceil specifically.
The choice was mainly influenced by the earlier discussion here:
https://lore.kernel.org/all/15495f8a-37b0-4768-9ee1-05fd6c70034e@oss.qualcomm.com/
Also, this helper isn’t necessarily limited to the current caller.
We might see additional users in the future where the semantics align more
naturally with flags like scale_down, which map cleanly to a round_ceil‑style selection.
That said, I agree that using round_floor could simplify the current callsite by
avoiding the negation of scale_up.
I don’t have a strong objection to switching it if you feel that would be
more cleaner for now.
> > +{
> > + unsigned long ice_freq = target_freq;
> > + struct dev_pm_opp *opp;
> > + int ret;
> > +
> > + if (!ice->has_opp)
> > + return -EOPNOTSUPP;
> > +
> > + if (round_ceil)
> > + opp = dev_pm_opp_find_freq_ceil(ice->dev, &ice_freq);
> > + else
> > + opp = dev_pm_opp_find_freq_floor(ice->dev, &ice_freq);
> > +
> > + if (IS_ERR(opp))
> > + return PTR_ERR(opp);
> > + dev_pm_opp_put(opp);
> > +
> > + ret = dev_pm_opp_set_rate(ice->dev, ice_freq);
> > + if (!ret)
> > + ice->core_clk_freq = ice_freq;
>
> Nit: Follow same error handling pattern everywhere in the driver.
> if (ret) {
> dev_err(dev, "error");
> return ret;
> }
Ack
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(qcom_ice_scale_clk);
> > +
> > static struct qcom_ice *qcom_ice_create(struct device *dev,
> > - void __iomem *base)
> > + void __iomem *base,
> > + bool is_legacy_binding)
>
> You don't need to introduce is_legacy_binding.
>
> Since you only need to add the OPP table when this function gets called from ICE probe,
> you should not touch this function. Instead, you should call devm_pm_opp_of_add_table()
> in ICE probe before calling qcom_ice_create() then once qcom_ice_create() is success, you
> can store the clk rate in the returned qcom_ice *engine ptr by calling clk_get_rate().
This was added as part of the review comment from Krzysztof:
https://lore.kernel.org/all/20260128-daft-seriema-of-promotion-c50eb5@quoll/
While I agree moving this to qcom_ice_probe would be more cleaner without needing
to change the API, most of our initializing code for driver by parsing the DT node
happens through qcom_ice_create, which keeps qcom_ice_probe much simpler.
Please let me know, if you think otherwise.
Also, I don't see any reason for moving the clk_get_rate() logic to qcom_ice_probe
though as it will not be set on legacy targets in that case.
> > {
> > struct qcom_ice *engine;
> > + int err;
> >
> > if (!qcom_scm_is_available())
> > return ERR_PTR(-EPROBE_DEFER);
> > @@ -584,6 +640,26 @@ static struct qcom_ice *qcom_ice_create(struct device *dev,
> > if (IS_ERR(engine->core_clk))
> > return ERR_CAST(engine->core_clk);
> >
> > + /*
> > + * Register the OPP table only when ICE is described as a standalone
> > + * device node. Older platforms place ICE inside the storage controller
> > + * node, so they don't need an OPP table here, as they are handled in
> > + * storage controller.
> > + */
> > + if (!is_legacy_binding) {
> > + /* OPP table is optional */
> > + err = devm_pm_opp_of_add_table(dev);
> > + if (err && err != -ENODEV) {
> > + dev_err(dev, "Invalid OPP table in Device tree\n");
> > + return ERR_PTR(err);
> > + }
> > + engine->has_opp = (err == 0);
>
> Let's keep it readable and simple. engine->has_opps = true; here and false in error handle above.
Well there are 3 cases to it:
1. err == 0 which implies devm_pm_opp_of_add_table is successful and we can set engine->has_opp =true.
2. err == -ENODEV which implies there is no opp table in the DT node.
In that case, we don't fail the driver simply go ahead and log in the check below.
This is done since OPP-table is optional.
3. err == any other error code. Something very wrong happened with devm_pm_opp_of_add_table
and driver should fail.
Hence, we have the condition (err == 0) for setting has_opp flag.
> > +
> > + if (!engine->has_opp)
> > + dev_info(dev, "ICE OPP table is not registered, please update your DT\n");
>
> Since OPP table is optional, I don't understand the reason for requesting the user to add one.
This was added as part of the review comment from Konrad:
https://lore.kernel.org/all/15495f8a-37b0-4768-9ee1-05fd6c70034e@oss.qualcomm.com/
OPP-table are mostly optional across kernel and I guess, this warning helps developers
to go ahead and update with the OPP-table.
Abhinaba Rakshit
^ permalink raw reply
* Re: [PATCH v5 3/3] riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
From: Yixun Lan @ 2026-04-03 14:16 UTC (permalink / raw)
To: Chukun Pan
Cc: gaohan, alex, aou, conor+dt, devicetree, krzk+dt, linux-kernel,
linux-riscv, palmer, pjw, rabenda.cn, robh, spacemit
In-Reply-To: <20260403095036.231761-1-amadeus@jmu.edu.cn>
Hi Chukun,
On 17:50 Fri 03 Apr , Chukun Pan wrote:
> Hi,
>
> > + pcie_vcc_3v3: regulator-pcie-vcc3v3 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "pcie_vcc3v3";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + gpio = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + };
>
> I would like to maintain the same property order as the
> regulator below,
..
> and add vin-supply:
>
I think Krzysztof will have objection on this, which isn't used by any
device, so not really useful, see similar comment for "reg_dc_in" here
https://lore.kernel.org/all/6530526f-59ca-4753-a068-46c62a1a1fed@kernel.org/
> ```
> pcie_vcc3v3: pcie-vcc3v3 {
please keep "regulator-" prefix, which is
pcie_vcc_3v3: regulator-pcie-vcc3v3 {
> compatible = "regulator-fixed";
> enable-active-high;
> gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>;
> regulator-name = "pcie_vcc3v3";
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> vin-supply = <&vcc_5v0>;
I'm not sure if there is any enforced rules on this? I can understand you
are trying to sort them in alphabet order.. but I would personally
prefer old way - in slightly logical order.. but I do have no strong
preference..
> };
> ```
>
> > +&pcie1 {
> > + vpcie3v3-supply = <&pcie_vcc_3v3>;
>
> > +&pcie2 {
> > + vpcie3v3-supply = <&pcie_vcc_3v3>;
>
> I think vpcie3v3-supply is not needed here. [1]
You right, can you send a patch to fix the same issue in tree?
I was trying to fix vpcie3v3 warning, but realized not fixed all..
>
> > + hub_2_0: hub@1 {
> > + compatible = "usb5e3,610";
> > + reg = <0x1>;
> > + peer-hub = <&hub_3_0>;
> > + vdd-supply = <&vcc5v0_usb30>;
>
> vdd-supply = <&vcc_5v0>;
right, I agree
>
> Please refer to the schematic. [2]
>
> [1] https://lore.kernel.org/linux-pci/u53qfrubgrcamiz35ox6lcdpp5bbzfwcsic466z5r6yyx6xz3n@c64nw2pegtfe/
> [2] https://drive.google.com/drive/folders/1pcI_U0C3VJKTCg8A1zj08CwNbohnONSR
>
> Thanks,
> Chukun
--
Yixun Lan (dlan)
^ permalink raw reply
* [PATCH 6/7] clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
From: Taniya Das <taniya.das@oss.qualcomm.com>
The global clock controller on the Nord SoC is partitioned into
GCC, SE_GCC, NE_GCC, and NW_GCC. Introduce driver support for each
of these controllers.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
[Shawn: Drop include of <linux/of.h> as the driver doesn't use any OF APIs]
Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-nord.c | 1901 +++++++++++++++++++++++++++++++++++++++
drivers/clk/qcom/negcc-nord.c | 1987 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/qcom/nwgcc-nord.c | 688 ++++++++++++++
drivers/clk/qcom/segcc-nord.c | 1609 +++++++++++++++++++++++++++++++++
6 files changed, 6196 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 10c74db7e072f560f4bc26f81b4378034d1f9bf6..87efdf67124b3e1c2b6c5b976ef404aaa2ab5c23 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -145,6 +145,16 @@ config CLK_KAANAPALI_VIDEOCC
Say Y if you want to support video devices and functionality such as
video encode/decode.
+config CLK_NORD_GCC
+ tristate "Nord Global Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ select QCOM_GDSC
+ help
+ Support for the global clock controller on Nord devices.
+ Say Y if you want to use peripheral devices such as UART,
+ SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination
+ of GCC, SE_GCC, NE_GCC and NW_GCC.
+
config CLK_X1E80100_CAMCC
tristate "X1E80100 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1a7ff1986b834f48dbaa2fd8c2559f0046ea7579..397261e9e387b4a1612296822076c1c001787ad7 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o
+obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o
obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o
obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
diff --git a/drivers/clk/qcom/gcc-nord.c b/drivers/clk/qcom/gcc-nord.c
new file mode 100644
index 0000000000000000000000000000000000000000..ab24ebeadbdd23b2094d915bd8a8c83ae91e0e4f
--- /dev/null
+++ b/drivers/clk/qcom/gcc-nord.c
@@ -0,0 +1,1901 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,nord-gcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "clk-regmap-phy-mux.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ DT_BI_TCXO,
+ DT_SLEEP_CLK,
+ DT_PCIE_A_PIPE_CLK,
+ DT_PCIE_B_PIPE_CLK,
+ DT_PCIE_C_PIPE_CLK,
+ DT_PCIE_D_PIPE_CLK,
+};
+
+enum {
+ P_BI_TCXO,
+ P_GCC_GPLL0_OUT_EVEN,
+ P_GCC_GPLL0_OUT_MAIN,
+ P_PCIE_A_PIPE_CLK,
+ P_PCIE_B_PIPE_CLK,
+ P_PCIE_C_PIPE_CLK,
+ P_PCIE_D_PIPE_CLK,
+ P_SLEEP_CLK,
+};
+
+static struct clk_alpha_pll gcc_gpll0 = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .enable_reg = 0x9d020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gpll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_gcc_gpll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gpll0_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct parent_map gcc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_GCC_GPLL0_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gcc_gpll0.clkr.hw },
+ { .hw = &gcc_gpll0_out_even.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const struct clk_parent_data gcc_parent_data_1[] = {
+ { .index = DT_BI_TCXO },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_SLEEP_CLK, 5 },
+ { P_GCC_GPLL0_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_2[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gcc_gpll0.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+ { .hw = &gcc_gpll0_out_even.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_GPLL0_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data gcc_parent_data_3[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gcc_gpll0.clkr.hw },
+};
+
+static struct clk_regmap_phy_mux gcc_pcie_a_pipe_clk_src = {
+ .reg = 0x49094,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_pipe_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_A_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
+ },
+ },
+};
+
+static struct clk_regmap_phy_mux gcc_pcie_b_pipe_clk_src = {
+ .reg = 0x4a094,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_pipe_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_B_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
+ },
+ },
+};
+
+static struct clk_regmap_phy_mux gcc_pcie_c_pipe_clk_src = {
+ .reg = 0x4b094,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_pipe_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_C_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
+ },
+ },
+};
+
+static struct clk_regmap_phy_mux gcc_pcie_d_pipe_clk_src = {
+ .reg = 0x4c094,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_pipe_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_D_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
+ F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_gp1_clk_src = {
+ .cmd_rcgr = 0x30004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gp1_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_gp2_clk_src = {
+ .cmd_rcgr = 0x31004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gp2_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_a_aux_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie_a_aux_clk_src = {
+ .cmd_rcgr = 0x49098,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_aux_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_a_phy_aux_clk_src = {
+ .cmd_rcgr = 0x4d020,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_a_phy_rchng_clk_src[] = {
+ F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie_a_phy_rchng_clk_src = {
+ .cmd_rcgr = 0x4907c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_phy_rchng_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_b_aux_clk_src = {
+ .cmd_rcgr = 0x4a098,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_aux_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_b_phy_aux_clk_src = {
+ .cmd_rcgr = 0x4e020,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_b_phy_rchng_clk_src = {
+ .cmd_rcgr = 0x4a07c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_phy_rchng_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_c_aux_clk_src = {
+ .cmd_rcgr = 0x4b098,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_aux_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_c_phy_aux_clk_src = {
+ .cmd_rcgr = 0x4f020,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_c_phy_rchng_clk_src = {
+ .cmd_rcgr = 0x4b07c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_phy_rchng_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_d_aux_clk_src = {
+ .cmd_rcgr = 0x4c098,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_aux_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_d_phy_aux_clk_src = {
+ .cmd_rcgr = 0x50020,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_d_phy_rchng_clk_src = {
+ .cmd_rcgr = 0x4c07c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_phy_rchng_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_noc_refgen_clk_src = {
+ .cmd_rcgr = 0x52094,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_refgen_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie_noc_safety_clk_src = {
+ .cmd_rcgr = 0x520ac,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_safety_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
+ F(40000000, P_GCC_GPLL0_OUT_MAIN, 15, 0, 0),
+ F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pdm2_clk_src = {
+ .cmd_rcgr = 0x1a010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pdm2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pdm2_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src[] = {
+ F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
+ F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
+ F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
+ F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
+ F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
+ F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
+ F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
+ F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
+ F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
+ F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
+ F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
+ F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
+ F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
+ F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = {
+ .name = "gcc_qupv3_wrap3_qspi_ref_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = {
+ .cmd_rcgr = 0x23174,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &gcc_qupv3_wrap3_qspi_ref_clk_src_init,
+};
+
+static struct clk_regmap_div gcc_qupv3_wrap3_s0_clk_src = {
+ .reg = 0x2316c,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap3_s0_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+ .halt_reg = 0x1f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_boot_rom_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x30000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x30000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gp1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_gp1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x31000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x31000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gp2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_gp2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmu_0_tcu_vote_clk = {
+ .halt_reg = 0x7d094,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x7d094,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_mmu_0_tcu_vote_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_a_aux_clk = {
+ .halt_reg = 0x49058,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x49058,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(14),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_a_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_a_cfg_ahb_clk = {
+ .halt_reg = 0x49054,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x49054,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(13),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_a_dti_qtc_clk = {
+ .halt_reg = 0x49018,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x49018,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(8),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_dti_qtc_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_a_mstr_axi_clk = {
+ .halt_reg = 0x49040,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x49040,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(12),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_mstr_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_a_phy_aux_clk = {
+ .halt_reg = 0x4d01c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(12),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_a_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_a_phy_rchng_clk = {
+ .halt_reg = 0x49078,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x49078,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(16),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_phy_rchng_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_a_phy_rchng_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_a_pipe_clk = {
+ .halt_reg = 0x49068,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x49068,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(15),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_pipe_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_a_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_a_slv_axi_clk = {
+ .halt_reg = 0x4902c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x4902c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(11),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_slv_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_a_slv_q2a_axi_clk = {
+ .halt_reg = 0x49024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x49024,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(10),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_a_slv_q2a_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_b_aux_clk = {
+ .halt_reg = 0x4a058,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(23),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_b_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_b_cfg_ahb_clk = {
+ .halt_reg = 0x4a054,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x4a054,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(22),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_b_dti_qtc_clk = {
+ .halt_reg = 0x4a018,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x4a018,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(17),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_dti_qtc_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_b_mstr_axi_clk = {
+ .halt_reg = 0x4a040,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x4a040,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(21),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_mstr_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_b_phy_aux_clk = {
+ .halt_reg = 0x4e01c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(13),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_b_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_b_phy_rchng_clk = {
+ .halt_reg = 0x4a078,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(25),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_phy_rchng_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_b_phy_rchng_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_b_pipe_clk = {
+ .halt_reg = 0x4a068,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(24),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_pipe_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_b_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_b_slv_axi_clk = {
+ .halt_reg = 0x4a02c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x4a02c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(20),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_slv_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_b_slv_q2a_axi_clk = {
+ .halt_reg = 0x4a024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(19),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_b_slv_q2a_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_c_aux_clk = {
+ .halt_reg = 0x4b058,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_c_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_c_cfg_ahb_clk = {
+ .halt_reg = 0x4b054,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x4b054,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(31),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_c_dti_qtc_clk = {
+ .halt_reg = 0x4b018,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x4b018,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(26),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_dti_qtc_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_c_mstr_axi_clk = {
+ .halt_reg = 0x4b040,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x4b040,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(30),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_mstr_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_c_phy_aux_clk = {
+ .halt_reg = 0x4f01c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(14),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_c_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_c_phy_rchng_clk = {
+ .halt_reg = 0x4b078,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(2),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_phy_rchng_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_c_phy_rchng_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_c_pipe_clk = {
+ .halt_reg = 0x4b068,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(1),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_pipe_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_c_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_c_slv_axi_clk = {
+ .halt_reg = 0x4b02c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x4b02c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(29),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_slv_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_c_slv_q2a_axi_clk = {
+ .halt_reg = 0x4b024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d008,
+ .enable_mask = BIT(28),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_c_slv_q2a_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_d_aux_clk = {
+ .halt_reg = 0x4c058,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(9),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_d_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_d_cfg_ahb_clk = {
+ .halt_reg = 0x4c054,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x4c054,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(8),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_d_dti_qtc_clk = {
+ .halt_reg = 0x4c018,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x4c018,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(3),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_dti_qtc_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_d_mstr_axi_clk = {
+ .halt_reg = 0x4c040,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x4c040,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(7),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_mstr_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_d_phy_aux_clk = {
+ .halt_reg = 0x5001c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(16),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_d_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_d_phy_rchng_clk = {
+ .halt_reg = 0x4c078,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(11),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_phy_rchng_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_d_phy_rchng_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_d_pipe_clk = {
+ .halt_reg = 0x4c068,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(10),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_pipe_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_d_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_d_slv_axi_clk = {
+ .halt_reg = 0x4c02c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x4c02c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(6),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_slv_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_d_slv_q2a_axi_clk = {
+ .halt_reg = 0x4c024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(5),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_d_slv_q2a_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_link_ahb_clk = {
+ .halt_reg = 0x52464,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x52464,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_link_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_link_xo_clk = {
+ .halt_reg = 0x52468,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x52468,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x52468,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_link_xo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_async_bridge_clk = {
+ .halt_reg = 0x52048,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x52048,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d018,
+ .enable_mask = BIT(18),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_async_bridge_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_cnoc_sf_qx_clk = {
+ .halt_reg = 0x52040,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x52040,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(24),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_cnoc_sf_qx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_m_cfg_clk = {
+ .halt_reg = 0x52060,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x52060,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d018,
+ .enable_mask = BIT(4),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_m_cfg_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_m_pdb_clk = {
+ .halt_reg = 0x52084,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x52084,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d018,
+ .enable_mask = BIT(8),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_m_pdb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_mstr_axi_clk = {
+ .halt_reg = 0x52050,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x52050,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(25),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_mstr_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_pwrctl_clk = {
+ .halt_reg = 0x52080,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d018,
+ .enable_mask = BIT(7),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_pwrctl_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_qosgen_extref_clk = {
+ .halt_reg = 0x52074,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(19),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_qosgen_extref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_refgen_clk = {
+ .halt_reg = 0x52078,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x52078,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_refgen_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_noc_refgen_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_s_cfg_clk = {
+ .halt_reg = 0x52064,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d018,
+ .enable_mask = BIT(5),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_s_cfg_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_s_pdb_clk = {
+ .halt_reg = 0x5208c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x5208c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d018,
+ .enable_mask = BIT(9),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_s_pdb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_safety_clk = {
+ .halt_reg = 0x5207c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5207c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_safety_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_noc_safety_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_slave_axi_clk = {
+ .halt_reg = 0x52058,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x52058,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(26),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_slave_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_tsctr_clk = {
+ .halt_reg = 0x52070,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(18),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_tsctr_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_noc_xo_clk = {
+ .halt_reg = 0x52068,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d018,
+ .enable_mask = BIT(6),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_noc_xo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+ .halt_reg = 0x1a00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1a00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pdm2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pdm2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+ .halt_reg = 0x1a004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x1a004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pdm_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_xo4_clk = {
+ .halt_reg = 0x1a008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1a008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pdm_xo4_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = {
+ .halt_reg = 0x23020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d000,
+ .enable_mask = BIT(24),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap3_core_2x_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap3_core_clk = {
+ .halt_reg = 0x2300c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d000,
+ .enable_mask = BIT(23),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap3_core_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap3_m_clk = {
+ .halt_reg = 0x23004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x23004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d000,
+ .enable_mask = BIT(22),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap3_m_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap3_qspi_ref_clk = {
+ .halt_reg = 0x23170,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d000,
+ .enable_mask = BIT(26),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap3_qspi_ref_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap3_s0_clk = {
+ .halt_reg = 0x2315c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9d000,
+ .enable_mask = BIT(25),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap3_s0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap3_s_ahb_clk = {
+ .halt_reg = 0x23008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x23008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9d010,
+ .enable_mask = BIT(15),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap3_s_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_smmu_pcie_qtc_vote_clk = {
+ .halt_reg = 0x7d0b8,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x7d0b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_smmu_pcie_qtc_vote_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc gcc_pcie_a_gdsc = {
+ .gdscr = 0x49004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .collapse_ctrl = 0x8d02c,
+ .collapse_mask = BIT(1),
+ .pd = {
+ .name = "gcc_pcie_a_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
+};
+
+static struct gdsc gcc_pcie_a_phy_gdsc = {
+ .gdscr = 0x4d004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .collapse_ctrl = 0x8d02c,
+ .collapse_mask = BIT(5),
+ .pd = {
+ .name = "gcc_pcie_a_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
+};
+
+static struct gdsc gcc_pcie_b_gdsc = {
+ .gdscr = 0x4a004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .collapse_ctrl = 0x8d02c,
+ .collapse_mask = BIT(2),
+ .pd = {
+ .name = "gcc_pcie_b_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
+};
+
+static struct gdsc gcc_pcie_b_phy_gdsc = {
+ .gdscr = 0x4e004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .collapse_ctrl = 0x8d02c,
+ .collapse_mask = BIT(6),
+ .pd = {
+ .name = "gcc_pcie_b_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
+};
+
+static struct gdsc gcc_pcie_c_gdsc = {
+ .gdscr = 0x4b004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .collapse_ctrl = 0x8d02c,
+ .collapse_mask = BIT(3),
+ .pd = {
+ .name = "gcc_pcie_c_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
+};
+
+static struct gdsc gcc_pcie_c_phy_gdsc = {
+ .gdscr = 0x4f004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .collapse_ctrl = 0x8d02c,
+ .collapse_mask = BIT(7),
+ .pd = {
+ .name = "gcc_pcie_c_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
+};
+
+static struct gdsc gcc_pcie_d_gdsc = {
+ .gdscr = 0x4c004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .collapse_ctrl = 0x8d02c,
+ .collapse_mask = BIT(4),
+ .pd = {
+ .name = "gcc_pcie_d_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
+};
+
+static struct gdsc gcc_pcie_d_phy_gdsc = {
+ .gdscr = 0x50004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .collapse_ctrl = 0x8d02c,
+ .collapse_mask = BIT(8),
+ .pd = {
+ .name = "gcc_pcie_d_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
+};
+
+static struct gdsc gcc_pcie_noc_gdsc = {
+ .gdscr = 0x52004,
+ .gds_hw_ctrl = 0x52018,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .collapse_ctrl = 0x8d02c,
+ .collapse_mask = BIT(0),
+ .pd = {
+ .name = "gcc_pcie_noc_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
+};
+
+static struct clk_regmap *gcc_nord_clocks[] = {
+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
+ [GCC_GPLL0] = &gcc_gpll0.clkr,
+ [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
+ [GCC_MMU_0_TCU_VOTE_CLK] = &gcc_mmu_0_tcu_vote_clk.clkr,
+ [GCC_PCIE_A_AUX_CLK] = &gcc_pcie_a_aux_clk.clkr,
+ [GCC_PCIE_A_AUX_CLK_SRC] = &gcc_pcie_a_aux_clk_src.clkr,
+ [GCC_PCIE_A_CFG_AHB_CLK] = &gcc_pcie_a_cfg_ahb_clk.clkr,
+ [GCC_PCIE_A_DTI_QTC_CLK] = &gcc_pcie_a_dti_qtc_clk.clkr,
+ [GCC_PCIE_A_MSTR_AXI_CLK] = &gcc_pcie_a_mstr_axi_clk.clkr,
+ [GCC_PCIE_A_PHY_AUX_CLK] = &gcc_pcie_a_phy_aux_clk.clkr,
+ [GCC_PCIE_A_PHY_AUX_CLK_SRC] = &gcc_pcie_a_phy_aux_clk_src.clkr,
+ [GCC_PCIE_A_PHY_RCHNG_CLK] = &gcc_pcie_a_phy_rchng_clk.clkr,
+ [GCC_PCIE_A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_a_phy_rchng_clk_src.clkr,
+ [GCC_PCIE_A_PIPE_CLK] = &gcc_pcie_a_pipe_clk.clkr,
+ [GCC_PCIE_A_PIPE_CLK_SRC] = &gcc_pcie_a_pipe_clk_src.clkr,
+ [GCC_PCIE_A_SLV_AXI_CLK] = &gcc_pcie_a_slv_axi_clk.clkr,
+ [GCC_PCIE_A_SLV_Q2A_AXI_CLK] = &gcc_pcie_a_slv_q2a_axi_clk.clkr,
+ [GCC_PCIE_B_AUX_CLK] = &gcc_pcie_b_aux_clk.clkr,
+ [GCC_PCIE_B_AUX_CLK_SRC] = &gcc_pcie_b_aux_clk_src.clkr,
+ [GCC_PCIE_B_CFG_AHB_CLK] = &gcc_pcie_b_cfg_ahb_clk.clkr,
+ [GCC_PCIE_B_DTI_QTC_CLK] = &gcc_pcie_b_dti_qtc_clk.clkr,
+ [GCC_PCIE_B_MSTR_AXI_CLK] = &gcc_pcie_b_mstr_axi_clk.clkr,
+ [GCC_PCIE_B_PHY_AUX_CLK] = &gcc_pcie_b_phy_aux_clk.clkr,
+ [GCC_PCIE_B_PHY_AUX_CLK_SRC] = &gcc_pcie_b_phy_aux_clk_src.clkr,
+ [GCC_PCIE_B_PHY_RCHNG_CLK] = &gcc_pcie_b_phy_rchng_clk.clkr,
+ [GCC_PCIE_B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_b_phy_rchng_clk_src.clkr,
+ [GCC_PCIE_B_PIPE_CLK] = &gcc_pcie_b_pipe_clk.clkr,
+ [GCC_PCIE_B_PIPE_CLK_SRC] = &gcc_pcie_b_pipe_clk_src.clkr,
+ [GCC_PCIE_B_SLV_AXI_CLK] = &gcc_pcie_b_slv_axi_clk.clkr,
+ [GCC_PCIE_B_SLV_Q2A_AXI_CLK] = &gcc_pcie_b_slv_q2a_axi_clk.clkr,
+ [GCC_PCIE_C_AUX_CLK] = &gcc_pcie_c_aux_clk.clkr,
+ [GCC_PCIE_C_AUX_CLK_SRC] = &gcc_pcie_c_aux_clk_src.clkr,
+ [GCC_PCIE_C_CFG_AHB_CLK] = &gcc_pcie_c_cfg_ahb_clk.clkr,
+ [GCC_PCIE_C_DTI_QTC_CLK] = &gcc_pcie_c_dti_qtc_clk.clkr,
+ [GCC_PCIE_C_MSTR_AXI_CLK] = &gcc_pcie_c_mstr_axi_clk.clkr,
+ [GCC_PCIE_C_PHY_AUX_CLK] = &gcc_pcie_c_phy_aux_clk.clkr,
+ [GCC_PCIE_C_PHY_AUX_CLK_SRC] = &gcc_pcie_c_phy_aux_clk_src.clkr,
+ [GCC_PCIE_C_PHY_RCHNG_CLK] = &gcc_pcie_c_phy_rchng_clk.clkr,
+ [GCC_PCIE_C_PHY_RCHNG_CLK_SRC] = &gcc_pcie_c_phy_rchng_clk_src.clkr,
+ [GCC_PCIE_C_PIPE_CLK] = &gcc_pcie_c_pipe_clk.clkr,
+ [GCC_PCIE_C_PIPE_CLK_SRC] = &gcc_pcie_c_pipe_clk_src.clkr,
+ [GCC_PCIE_C_SLV_AXI_CLK] = &gcc_pcie_c_slv_axi_clk.clkr,
+ [GCC_PCIE_C_SLV_Q2A_AXI_CLK] = &gcc_pcie_c_slv_q2a_axi_clk.clkr,
+ [GCC_PCIE_D_AUX_CLK] = &gcc_pcie_d_aux_clk.clkr,
+ [GCC_PCIE_D_AUX_CLK_SRC] = &gcc_pcie_d_aux_clk_src.clkr,
+ [GCC_PCIE_D_CFG_AHB_CLK] = &gcc_pcie_d_cfg_ahb_clk.clkr,
+ [GCC_PCIE_D_DTI_QTC_CLK] = &gcc_pcie_d_dti_qtc_clk.clkr,
+ [GCC_PCIE_D_MSTR_AXI_CLK] = &gcc_pcie_d_mstr_axi_clk.clkr,
+ [GCC_PCIE_D_PHY_AUX_CLK] = &gcc_pcie_d_phy_aux_clk.clkr,
+ [GCC_PCIE_D_PHY_AUX_CLK_SRC] = &gcc_pcie_d_phy_aux_clk_src.clkr,
+ [GCC_PCIE_D_PHY_RCHNG_CLK] = &gcc_pcie_d_phy_rchng_clk.clkr,
+ [GCC_PCIE_D_PHY_RCHNG_CLK_SRC] = &gcc_pcie_d_phy_rchng_clk_src.clkr,
+ [GCC_PCIE_D_PIPE_CLK] = &gcc_pcie_d_pipe_clk.clkr,
+ [GCC_PCIE_D_PIPE_CLK_SRC] = &gcc_pcie_d_pipe_clk_src.clkr,
+ [GCC_PCIE_D_SLV_AXI_CLK] = &gcc_pcie_d_slv_axi_clk.clkr,
+ [GCC_PCIE_D_SLV_Q2A_AXI_CLK] = &gcc_pcie_d_slv_q2a_axi_clk.clkr,
+ [GCC_PCIE_LINK_AHB_CLK] = &gcc_pcie_link_ahb_clk.clkr,
+ [GCC_PCIE_LINK_XO_CLK] = &gcc_pcie_link_xo_clk.clkr,
+ [GCC_PCIE_NOC_ASYNC_BRIDGE_CLK] = &gcc_pcie_noc_async_bridge_clk.clkr,
+ [GCC_PCIE_NOC_CNOC_SF_QX_CLK] = &gcc_pcie_noc_cnoc_sf_qx_clk.clkr,
+ [GCC_PCIE_NOC_M_CFG_CLK] = &gcc_pcie_noc_m_cfg_clk.clkr,
+ [GCC_PCIE_NOC_M_PDB_CLK] = &gcc_pcie_noc_m_pdb_clk.clkr,
+ [GCC_PCIE_NOC_MSTR_AXI_CLK] = &gcc_pcie_noc_mstr_axi_clk.clkr,
+ [GCC_PCIE_NOC_PWRCTL_CLK] = &gcc_pcie_noc_pwrctl_clk.clkr,
+ [GCC_PCIE_NOC_QOSGEN_EXTREF_CLK] = &gcc_pcie_noc_qosgen_extref_clk.clkr,
+ [GCC_PCIE_NOC_REFGEN_CLK] = &gcc_pcie_noc_refgen_clk.clkr,
+ [GCC_PCIE_NOC_REFGEN_CLK_SRC] = &gcc_pcie_noc_refgen_clk_src.clkr,
+ [GCC_PCIE_NOC_S_CFG_CLK] = &gcc_pcie_noc_s_cfg_clk.clkr,
+ [GCC_PCIE_NOC_S_PDB_CLK] = &gcc_pcie_noc_s_pdb_clk.clkr,
+ [GCC_PCIE_NOC_SAFETY_CLK] = &gcc_pcie_noc_safety_clk.clkr,
+ [GCC_PCIE_NOC_SAFETY_CLK_SRC] = &gcc_pcie_noc_safety_clk_src.clkr,
+ [GCC_PCIE_NOC_SLAVE_AXI_CLK] = &gcc_pcie_noc_slave_axi_clk.clkr,
+ [GCC_PCIE_NOC_TSCTR_CLK] = &gcc_pcie_noc_tsctr_clk.clkr,
+ [GCC_PCIE_NOC_XO_CLK] = &gcc_pcie_noc_xo_clk.clkr,
+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+ [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+ [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
+ [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr,
+ [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr,
+ [GCC_QUPV3_WRAP3_M_CLK] = &gcc_qupv3_wrap3_m_clk.clkr,
+ [GCC_QUPV3_WRAP3_QSPI_REF_CLK] = &gcc_qupv3_wrap3_qspi_ref_clk.clkr,
+ [GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr,
+ [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr,
+ [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr,
+ [GCC_QUPV3_WRAP3_S_AHB_CLK] = &gcc_qupv3_wrap3_s_ahb_clk.clkr,
+ [GCC_SMMU_PCIE_QTC_VOTE_CLK] = &gcc_smmu_pcie_qtc_vote_clk.clkr,
+};
+
+static struct gdsc *gcc_nord_gdscs[] = {
+ [GCC_PCIE_A_GDSC] = &gcc_pcie_a_gdsc,
+ [GCC_PCIE_A_PHY_GDSC] = &gcc_pcie_a_phy_gdsc,
+ [GCC_PCIE_B_GDSC] = &gcc_pcie_b_gdsc,
+ [GCC_PCIE_B_PHY_GDSC] = &gcc_pcie_b_phy_gdsc,
+ [GCC_PCIE_C_GDSC] = &gcc_pcie_c_gdsc,
+ [GCC_PCIE_C_PHY_GDSC] = &gcc_pcie_c_phy_gdsc,
+ [GCC_PCIE_D_GDSC] = &gcc_pcie_d_gdsc,
+ [GCC_PCIE_D_PHY_GDSC] = &gcc_pcie_d_phy_gdsc,
+ [GCC_PCIE_NOC_GDSC] = &gcc_pcie_noc_gdsc,
+};
+
+static const struct qcom_reset_map gcc_nord_resets[] = {
+ [GCC_PCIE_A_BCR] = { 0x49000 },
+ [GCC_PCIE_A_LINK_DOWN_BCR] = { 0xb9000 },
+ [GCC_PCIE_A_NOCSR_COM_PHY_BCR] = { 0xb900c },
+ [GCC_PCIE_A_PHY_BCR] = { 0x4d000 },
+ [GCC_PCIE_A_PHY_CFG_AHB_BCR] = { 0xb9014 },
+ [GCC_PCIE_A_PHY_COM_BCR] = { 0xb9018 },
+ [GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR] = { 0xb9010 },
+ [GCC_PCIE_B_BCR] = { 0x4a000 },
+ [GCC_PCIE_B_LINK_DOWN_BCR] = { 0xba000 },
+ [GCC_PCIE_B_NOCSR_COM_PHY_BCR] = { 0xba008 },
+ [GCC_PCIE_B_PHY_BCR] = { 0x4e000 },
+ [GCC_PCIE_B_PHY_CFG_AHB_BCR] = { 0xba010 },
+ [GCC_PCIE_B_PHY_COM_BCR] = { 0xba014 },
+ [GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR] = { 0xba00c },
+ [GCC_PCIE_C_BCR] = { 0x4b000 },
+ [GCC_PCIE_C_LINK_DOWN_BCR] = { 0xbb07c },
+ [GCC_PCIE_C_NOCSR_COM_PHY_BCR] = { 0xbb084 },
+ [GCC_PCIE_C_PHY_BCR] = { 0x4f000 },
+ [GCC_PCIE_C_PHY_CFG_AHB_BCR] = { 0xbb08c },
+ [GCC_PCIE_C_PHY_COM_BCR] = { 0xbb090 },
+ [GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR] = { 0xbb088 },
+ [GCC_PCIE_D_BCR] = { 0x4c000 },
+ [GCC_PCIE_D_LINK_DOWN_BCR] = { 0xbc000 },
+ [GCC_PCIE_D_NOCSR_COM_PHY_BCR] = { 0xbc008 },
+ [GCC_PCIE_D_PHY_BCR] = { 0x50000 },
+ [GCC_PCIE_D_PHY_CFG_AHB_BCR] = { 0xbc010 },
+ [GCC_PCIE_D_PHY_COM_BCR] = { 0xbc014 },
+ [GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR] = { 0xbc00c },
+ [GCC_PCIE_NOC_BCR] = { 0x52000 },
+ [GCC_PDM_BCR] = { 0x1a000 },
+ [GCC_QUPV3_WRAPPER_3_BCR] = { 0x23000 },
+ [GCC_TCSR_PCIE_BCR] = { 0xb901c },
+};
+
+static const struct clk_rcg_dfs_data gcc_nord_dfs_clocks[] = {
+ DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src),
+};
+
+static const struct regmap_config gcc_nord_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1f41f0,
+ .fast_io = true,
+};
+
+static struct qcom_cc_driver_data gcc_nord_driver_data = {
+ .dfs_rcgs = gcc_nord_dfs_clocks,
+ .num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks),
+};
+
+static const struct qcom_cc_desc gcc_nord_desc = {
+ .config = &gcc_nord_regmap_config,
+ .clks = gcc_nord_clocks,
+ .num_clks = ARRAY_SIZE(gcc_nord_clocks),
+ .resets = gcc_nord_resets,
+ .num_resets = ARRAY_SIZE(gcc_nord_resets),
+ .gdscs = gcc_nord_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_nord_gdscs),
+ .driver_data = &gcc_nord_driver_data,
+};
+
+static const struct of_device_id gcc_nord_match_table[] = {
+ { .compatible = "qcom,nord-gcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_nord_match_table);
+
+static int gcc_nord_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &gcc_nord_desc);
+}
+
+static struct platform_driver gcc_nord_driver = {
+ .probe = gcc_nord_probe,
+ .driver = {
+ .name = "gcc-nord",
+ .of_match_table = gcc_nord_match_table,
+ },
+};
+
+static int __init gcc_nord_init(void)
+{
+ return platform_driver_register(&gcc_nord_driver);
+}
+subsys_initcall(gcc_nord_init);
+
+static void __exit gcc_nord_exit(void)
+{
+ platform_driver_unregister(&gcc_nord_driver);
+}
+module_exit(gcc_nord_exit);
+
+MODULE_DESCRIPTION("QTI GCC NORD Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/qcom/negcc-nord.c b/drivers/clk/qcom/negcc-nord.c
new file mode 100644
index 0000000000000000000000000000000000000000..1aa24e2784e536e6b6e76f488abd0e2fcc435380
--- /dev/null
+++ b/drivers/clk/qcom/negcc-nord.c
@@ -0,0 +1,1987 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,nord-negcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "clk-regmap-phy-mux.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ DT_BI_TCXO,
+ DT_SLEEP_CLK,
+ DT_UFS_PHY_RX_SYMBOL_0_CLK,
+ DT_UFS_PHY_RX_SYMBOL_1_CLK,
+ DT_UFS_PHY_TX_SYMBOL_0_CLK,
+ DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK,
+ DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK,
+};
+
+enum {
+ P_BI_TCXO,
+ P_NE_GCC_GPLL0_OUT_EVEN,
+ P_NE_GCC_GPLL0_OUT_MAIN,
+ P_NE_GCC_GPLL2_OUT_MAIN,
+ P_SLEEP_CLK,
+ P_UFS_PHY_RX_SYMBOL_0_CLK,
+ P_UFS_PHY_RX_SYMBOL_1_CLK,
+ P_UFS_PHY_TX_SYMBOL_0_CLK,
+ P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK,
+ P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK,
+};
+
+static struct clk_alpha_pll ne_gcc_gpll0 = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gpll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_ne_gcc_gpll0_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv ne_gcc_gpll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_ne_gcc_gpll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_ne_gcc_gpll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gpll0_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static struct clk_alpha_pll ne_gcc_gpll2 = {
+ .offset = 0x2000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(2),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gpll2",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+ },
+ },
+};
+
+static const struct parent_map ne_gcc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_NE_GCC_GPLL0_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data ne_gcc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &ne_gcc_gpll0.clkr.hw },
+};
+
+static const struct parent_map ne_gcc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_NE_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_NE_GCC_GPLL0_OUT_EVEN, 5 },
+};
+
+static const struct clk_parent_data ne_gcc_parent_data_1[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &ne_gcc_gpll0.clkr.hw },
+ { .hw = &ne_gcc_gpll0_out_even.clkr.hw },
+};
+
+static const struct parent_map ne_gcc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_NE_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_NE_GCC_GPLL2_OUT_MAIN, 3 },
+};
+
+static const struct clk_parent_data ne_gcc_parent_data_2[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &ne_gcc_gpll0.clkr.hw },
+ { .hw = &ne_gcc_gpll2.clkr.hw },
+};
+
+static const struct parent_map ne_gcc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const struct clk_parent_data ne_gcc_parent_data_3[] = {
+ { .index = DT_BI_TCXO },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map ne_gcc_parent_map_4[] = {
+ { P_BI_TCXO, 0 },
+ { P_NE_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const struct clk_parent_data ne_gcc_parent_data_4[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &ne_gcc_gpll0.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map ne_gcc_parent_map_5[] = {
+ { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data ne_gcc_parent_data_5[] = {
+ { .index = DT_BI_TCXO },
+};
+
+static const struct parent_map ne_gcc_parent_map_6[] = {
+ { P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 },
+ { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data ne_gcc_parent_data_6[] = {
+ { .index = DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK },
+ { .index = DT_BI_TCXO },
+};
+
+static const struct parent_map ne_gcc_parent_map_7[] = {
+ { P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 },
+ { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data ne_gcc_parent_data_7[] = {
+ { .index = DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK },
+ { .index = DT_BI_TCXO },
+};
+
+static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_0_clk_src = {
+ .reg = 0x33068,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_rx_symbol_0_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
+ },
+ },
+};
+
+static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_1_clk_src = {
+ .reg = 0x330f0,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_rx_symbol_1_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
+ },
+ },
+};
+
+static struct clk_regmap_phy_mux ne_gcc_ufs_phy_tx_symbol_0_clk_src = {
+ .reg = 0x33058,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_tx_symbol_0_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
+ },
+ },
+};
+
+static struct clk_regmap_mux ne_gcc_usb3_prim_phy_pipe_clk_src = {
+ .reg = 0x2a078,
+ .shift = 0,
+ .width = 2,
+ .parent_map = ne_gcc_parent_map_6,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb3_prim_phy_pipe_clk_src",
+ .parent_data = ne_gcc_parent_data_6,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_6),
+ .ops = &clk_regmap_mux_closest_ops,
+ },
+ },
+};
+
+static struct clk_regmap_mux ne_gcc_usb3_sec_phy_pipe_clk_src = {
+ .reg = 0x2c078,
+ .shift = 0,
+ .width = 2,
+ .parent_map = ne_gcc_parent_map_7,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb3_sec_phy_pipe_clk_src",
+ .parent_data = ne_gcc_parent_data_7,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_7),
+ .ops = &clk_regmap_mux_closest_ops,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_ne_gcc_gp1_clk_src[] = {
+ F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
+ F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ne_gcc_gp1_clk_src = {
+ .cmd_rcgr = 0x21004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_4,
+ .freq_tbl = ftbl_ne_gcc_gp1_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gp1_clk_src",
+ .parent_data = ne_gcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_4),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 ne_gcc_gp2_clk_src = {
+ .cmd_rcgr = 0x22004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_4,
+ .freq_tbl = ftbl_ne_gcc_gp1_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gp2_clk_src",
+ .parent_data = ne_gcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_4),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s0_clk_src[] = {
+ F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625),
+ F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625),
+ F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75),
+ F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25),
+ F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375),
+ F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75),
+ F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
+ F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
+ F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15),
+ F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25),
+ F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(102400000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 64, 375),
+ F(112000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 14, 75),
+ F(117964800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625),
+ F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
+ { }
+};
+
+static struct clk_init_data ne_gcc_qupv3_wrap2_s0_clk_src_init = {
+ .name = "ne_gcc_qupv3_wrap2_s0_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s0_clk_src = {
+ .cmd_rcgr = 0x3816c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s0_clk_src_init,
+};
+
+static struct clk_init_data ne_gcc_qupv3_wrap2_s1_clk_src_init = {
+ .name = "ne_gcc_qupv3_wrap2_s1_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s1_clk_src = {
+ .cmd_rcgr = 0x382a8,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s1_clk_src_init,
+};
+
+static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s2_clk_src[] = {
+ F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625),
+ F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625),
+ F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75),
+ F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25),
+ F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375),
+ F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75),
+ F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
+ F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
+ F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15),
+ F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25),
+ F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ { }
+};
+
+static struct clk_init_data ne_gcc_qupv3_wrap2_s2_clk_src_init = {
+ .name = "ne_gcc_qupv3_wrap2_s2_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s2_clk_src = {
+ .cmd_rcgr = 0x383e4,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s2_clk_src_init,
+};
+
+static struct clk_init_data ne_gcc_qupv3_wrap2_s3_clk_src_init = {
+ .name = "ne_gcc_qupv3_wrap2_s3_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s3_clk_src = {
+ .cmd_rcgr = 0x38520,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s3_clk_src_init,
+};
+
+static struct clk_init_data ne_gcc_qupv3_wrap2_s4_clk_src_init = {
+ .name = "ne_gcc_qupv3_wrap2_s4_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s4_clk_src = {
+ .cmd_rcgr = 0x3865c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s4_clk_src_init,
+};
+
+static struct clk_init_data ne_gcc_qupv3_wrap2_s5_clk_src_init = {
+ .name = "ne_gcc_qupv3_wrap2_s5_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s5_clk_src = {
+ .cmd_rcgr = 0x38798,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s5_clk_src_init,
+};
+
+static struct clk_init_data ne_gcc_qupv3_wrap2_s6_clk_src_init = {
+ .name = "ne_gcc_qupv3_wrap2_s6_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s6_clk_src = {
+ .cmd_rcgr = 0x388d4,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s6_clk_src_init,
+};
+
+static const struct freq_tbl ftbl_ne_gcc_sdcc4_apps_clk_src[] = {
+ F(37500000, P_NE_GCC_GPLL0_OUT_MAIN, 16, 0, 0),
+ F(50000000, P_NE_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
+ F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ne_gcc_sdcc4_apps_clk_src = {
+ .cmd_rcgr = 0x1801c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_sdcc4_apps_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_sdcc4_apps_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_floor_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ne_gcc_ufs_phy_axi_clk_src[] = {
+ F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
+ F(201500000, P_NE_GCC_GPLL2_OUT_MAIN, 4, 0, 0),
+ F(300000000, P_NE_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
+ F(403000000, P_NE_GCC_GPLL2_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ne_gcc_ufs_phy_axi_clk_src = {
+ .cmd_rcgr = 0x33034,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_2,
+ .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_axi_clk_src",
+ .parent_data = ne_gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 ne_gcc_ufs_phy_ice_core_clk_src = {
+ .cmd_rcgr = 0x3308c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_2,
+ .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_ice_core_clk_src",
+ .parent_data = ne_gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ne_gcc_ufs_phy_phy_aux_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ne_gcc_ufs_phy_phy_aux_clk_src = {
+ .cmd_rcgr = 0x330c0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_5,
+ .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_phy_aux_clk_src",
+ .parent_data = ne_gcc_parent_data_5,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_5),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 ne_gcc_ufs_phy_unipro_core_clk_src = {
+ .cmd_rcgr = 0x330a4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_2,
+ .freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_unipro_core_clk_src",
+ .parent_data = ne_gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ne_gcc_usb20_master_clk_src[] = {
+ F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
+ F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ne_gcc_usb20_master_clk_src = {
+ .cmd_rcgr = 0x31030,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_usb20_master_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb20_master_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 ne_gcc_usb20_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x31048,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb20_mock_utmi_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ne_gcc_usb31_prim_master_clk_src[] = {
+ F(85714286, P_NE_GCC_GPLL0_OUT_MAIN, 7, 0, 0),
+ F(133333333, P_NE_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
+ F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
+ F(240000000, P_NE_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ne_gcc_usb31_prim_master_clk_src = {
+ .cmd_rcgr = 0x2a038,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_1,
+ .freq_tbl = ftbl_ne_gcc_usb31_prim_master_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_prim_master_clk_src",
+ .parent_data = ne_gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 ne_gcc_usb31_prim_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x2a050,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_prim_mock_utmi_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 ne_gcc_usb31_sec_master_clk_src = {
+ .cmd_rcgr = 0x2c038,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_usb31_prim_master_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_sec_master_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 ne_gcc_usb31_sec_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x2c050,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_0,
+ .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_sec_mock_utmi_clk_src",
+ .parent_data = ne_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 ne_gcc_usb3_prim_phy_aux_clk_src = {
+ .cmd_rcgr = 0x2a07c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_3,
+ .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb3_prim_phy_aux_clk_src",
+ .parent_data = ne_gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 ne_gcc_usb3_sec_phy_aux_clk_src = {
+ .cmd_rcgr = 0x2c07c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = ne_gcc_parent_map_3,
+ .freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb3_sec_phy_aux_clk_src",
+ .parent_data = ne_gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_regmap_div ne_gcc_usb20_mock_utmi_postdiv_clk_src = {
+ .reg = 0x31060,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb20_mock_utmi_postdiv_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb20_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src = {
+ .reg = 0x2a068,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_prim_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src = {
+ .reg = 0x2c068,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_sec_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch ne_gcc_aggre_noc_ufs_phy_axi_clk = {
+ .halt_reg = 0x330f4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x330f4,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x330f4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_aggre_noc_ufs_phy_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_ufs_phy_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_aggre_noc_usb2_axi_clk = {
+ .halt_reg = 0x31068,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x31068,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x31068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_aggre_noc_usb2_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb20_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_aggre_noc_usb3_prim_axi_clk = {
+ .halt_reg = 0x2a098,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x2a098,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2a098,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_aggre_noc_usb3_prim_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_aggre_noc_usb3_sec_axi_clk = {
+ .halt_reg = 0x2c098,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x2c098,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2c098,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_aggre_noc_usb3_sec_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_sec_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_ahb2phy_clk = {
+ .halt_reg = 0x30004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x30004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x30004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ahb2phy_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_cnoc_usb2_axi_clk = {
+ .halt_reg = 0x31064,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x31064,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x31064,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_cnoc_usb2_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb20_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_cnoc_usb3_prim_axi_clk = {
+ .halt_reg = 0x2a094,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x2a094,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2a094,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_cnoc_usb3_prim_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_cnoc_usb3_sec_axi_clk = {
+ .halt_reg = 0x2c094,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x2c094,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2c094,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_cnoc_usb3_sec_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_sec_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_frq_measure_ref_clk = {
+ .halt_reg = 0x20008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x20008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_frq_measure_ref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_gp1_clk = {
+ .halt_reg = 0x21000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x21000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gp1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_gp1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_gp2_clk = {
+ .halt_reg = 0x22000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x22000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gp2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_gp2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_gpu_2_cfg_clk = {
+ .halt_reg = 0x34004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x34004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x34004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gpu_2_cfg_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_gpu_2_gpll0_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(19),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gpu_2_gpll0_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_gpu_2_gpll0_div_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(20),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gpu_2_gpll0_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_gpll0_out_even.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_gpu_2_hscnoc_gfx_clk = {
+ .halt_reg = 0x34014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x34014,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x34014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gpu_2_hscnoc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_gpu_2_smmu_vote_clk = {
+ .halt_reg = 0x57028,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_gpu_2_smmu_vote_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_qupv3_wrap2_core_2x_clk = {
+ .halt_reg = 0x38020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(1),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_qupv3_wrap2_core_2x_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_qupv3_wrap2_core_clk = {
+ .halt_reg = 0x3800c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_qupv3_wrap2_core_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_qupv3_wrap2_m_ahb_clk = {
+ .halt_reg = 0x38004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x38004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(30),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_qupv3_wrap2_m_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_qupv3_wrap2_s0_clk = {
+ .halt_reg = 0x3815c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(2),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_qupv3_wrap2_s0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_qupv3_wrap2_s1_clk = {
+ .halt_reg = 0x38298,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(3),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_qupv3_wrap2_s1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_qupv3_wrap2_s2_clk = {
+ .halt_reg = 0x383d4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(4),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_qupv3_wrap2_s2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_qupv3_wrap2_s3_clk = {
+ .halt_reg = 0x38510,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(5),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_qupv3_wrap2_s3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_qupv3_wrap2_s4_clk = {
+ .halt_reg = 0x3864c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(6),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_qupv3_wrap2_s4_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_qupv3_wrap2_s5_clk = {
+ .halt_reg = 0x38788,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(7),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_qupv3_wrap2_s5_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_qupv3_wrap2_s6_clk = {
+ .halt_reg = 0x388c4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(8),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_qupv3_wrap2_s6_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_qupv3_wrap2_s_ahb_clk = {
+ .halt_reg = 0x38008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x38008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(31),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_qupv3_wrap2_s_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_sdcc4_apps_clk = {
+ .halt_reg = 0x18004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x18004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_sdcc4_apps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_sdcc4_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_sdcc4_axi_clk = {
+ .halt_reg = 0x18014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x18014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_sdcc4_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_ufs_phy_ahb_clk = {
+ .halt_reg = 0x33028,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x33028,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x33028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_ufs_phy_axi_clk = {
+ .halt_reg = 0x33018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x33018,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x33018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_ufs_phy_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_ufs_phy_ice_core_clk = {
+ .halt_reg = 0x3307c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x3307c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x3307c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_ice_core_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_ufs_phy_ice_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_ufs_phy_phy_aux_clk = {
+ .halt_reg = 0x330bc,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x330bc,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x330bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_ufs_phy_rx_symbol_0_clk = {
+ .halt_reg = 0x33030,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x33030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_rx_symbol_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_ufs_phy_rx_symbol_1_clk = {
+ .halt_reg = 0x330d8,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x330d8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_rx_symbol_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_ufs_phy_tx_symbol_0_clk = {
+ .halt_reg = 0x3302c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x3302c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_tx_symbol_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_ufs_phy_unipro_core_clk = {
+ .halt_reg = 0x3306c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x3306c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x3306c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_ufs_phy_unipro_core_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb20_master_clk = {
+ .halt_reg = 0x31018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x31018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb20_master_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb20_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb20_mock_utmi_clk = {
+ .halt_reg = 0x3102c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3102c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb20_mock_utmi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb20_sleep_clk = {
+ .halt_reg = 0x31028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x31028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb20_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb31_prim_atb_clk = {
+ .halt_reg = 0x2a018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2a018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_prim_atb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb31_prim_eud_ahb_clk = {
+ .halt_reg = 0x2a02c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x2a02c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2a02c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_prim_eud_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb31_prim_master_clk = {
+ .halt_reg = 0x2a01c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a01c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_prim_master_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb31_prim_mock_utmi_clk = {
+ .halt_reg = 0x2a034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a034,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_prim_mock_utmi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb31_prim_sleep_clk = {
+ .halt_reg = 0x2a030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_prim_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb31_sec_atb_clk = {
+ .halt_reg = 0x2c018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2c018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_sec_atb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb31_sec_eud_ahb_clk = {
+ .halt_reg = 0x2c02c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x2c02c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2c02c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_sec_eud_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb31_sec_master_clk = {
+ .halt_reg = 0x2c01c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c01c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_sec_master_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_sec_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb31_sec_mock_utmi_clk = {
+ .halt_reg = 0x2c034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c034,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_sec_mock_utmi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb31_sec_sleep_clk = {
+ .halt_reg = 0x2c030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb31_sec_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb3_prim_phy_aux_clk = {
+ .halt_reg = 0x2a06c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a06c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb3_prim_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb3_prim_phy_com_aux_clk = {
+ .halt_reg = 0x2a070,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a070,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb3_prim_phy_com_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb3_prim_phy_pipe_clk = {
+ .halt_reg = 0x2a074,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x2a074,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2a074,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb3_prim_phy_pipe_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb3_sec_phy_aux_clk = {
+ .halt_reg = 0x2c06c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c06c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb3_sec_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb3_sec_phy_com_aux_clk = {
+ .halt_reg = 0x2c070,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c070,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb3_sec_phy_com_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ne_gcc_usb3_sec_phy_pipe_clk = {
+ .halt_reg = 0x2c074,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x2c074,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2c074,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ne_gcc_usb3_sec_phy_pipe_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &ne_gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc ne_gcc_ufs_mem_phy_gdsc = {
+ .gdscr = 0x32000,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .pd = {
+ .name = "ne_gcc_ufs_mem_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc ne_gcc_ufs_phy_gdsc = {
+ .gdscr = 0x33004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "ne_gcc_ufs_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc ne_gcc_usb20_prim_gdsc = {
+ .gdscr = 0x31004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "ne_gcc_usb20_prim_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc ne_gcc_usb31_prim_gdsc = {
+ .gdscr = 0x2a004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "ne_gcc_usb31_prim_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc ne_gcc_usb31_sec_gdsc = {
+ .gdscr = 0x2c004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "ne_gcc_usb31_sec_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc ne_gcc_usb3_phy_gdsc = {
+ .gdscr = 0x2b00c,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .pd = {
+ .name = "ne_gcc_usb3_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc ne_gcc_usb3_sec_phy_gdsc = {
+ .gdscr = 0x2d00c,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .pd = {
+ .name = "ne_gcc_usb3_sec_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct clk_regmap *ne_gcc_nord_clocks[] = {
+ [NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK] = &ne_gcc_aggre_noc_ufs_phy_axi_clk.clkr,
+ [NE_GCC_AGGRE_NOC_USB2_AXI_CLK] = &ne_gcc_aggre_noc_usb2_axi_clk.clkr,
+ [NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK] = &ne_gcc_aggre_noc_usb3_prim_axi_clk.clkr,
+ [NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK] = &ne_gcc_aggre_noc_usb3_sec_axi_clk.clkr,
+ [NE_GCC_AHB2PHY_CLK] = &ne_gcc_ahb2phy_clk.clkr,
+ [NE_GCC_CNOC_USB2_AXI_CLK] = &ne_gcc_cnoc_usb2_axi_clk.clkr,
+ [NE_GCC_CNOC_USB3_PRIM_AXI_CLK] = &ne_gcc_cnoc_usb3_prim_axi_clk.clkr,
+ [NE_GCC_CNOC_USB3_SEC_AXI_CLK] = &ne_gcc_cnoc_usb3_sec_axi_clk.clkr,
+ [NE_GCC_FRQ_MEASURE_REF_CLK] = &ne_gcc_frq_measure_ref_clk.clkr,
+ [NE_GCC_GP1_CLK] = &ne_gcc_gp1_clk.clkr,
+ [NE_GCC_GP1_CLK_SRC] = &ne_gcc_gp1_clk_src.clkr,
+ [NE_GCC_GP2_CLK] = &ne_gcc_gp2_clk.clkr,
+ [NE_GCC_GP2_CLK_SRC] = &ne_gcc_gp2_clk_src.clkr,
+ [NE_GCC_GPLL0] = &ne_gcc_gpll0.clkr,
+ [NE_GCC_GPLL0_OUT_EVEN] = &ne_gcc_gpll0_out_even.clkr,
+ [NE_GCC_GPLL2] = &ne_gcc_gpll2.clkr,
+ [NE_GCC_GPU_2_CFG_CLK] = &ne_gcc_gpu_2_cfg_clk.clkr,
+ [NE_GCC_GPU_2_GPLL0_CLK_SRC] = &ne_gcc_gpu_2_gpll0_clk_src.clkr,
+ [NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &ne_gcc_gpu_2_gpll0_div_clk_src.clkr,
+ [NE_GCC_GPU_2_HSCNOC_GFX_CLK] = &ne_gcc_gpu_2_hscnoc_gfx_clk.clkr,
+ [NE_GCC_GPU_2_SMMU_VOTE_CLK] = &ne_gcc_gpu_2_smmu_vote_clk.clkr,
+ [NE_GCC_QUPV3_WRAP2_CORE_2X_CLK] = &ne_gcc_qupv3_wrap2_core_2x_clk.clkr,
+ [NE_GCC_QUPV3_WRAP2_CORE_CLK] = &ne_gcc_qupv3_wrap2_core_clk.clkr,
+ [NE_GCC_QUPV3_WRAP2_M_AHB_CLK] = &ne_gcc_qupv3_wrap2_m_ahb_clk.clkr,
+ [NE_GCC_QUPV3_WRAP2_S0_CLK] = &ne_gcc_qupv3_wrap2_s0_clk.clkr,
+ [NE_GCC_QUPV3_WRAP2_S0_CLK_SRC] = &ne_gcc_qupv3_wrap2_s0_clk_src.clkr,
+ [NE_GCC_QUPV3_WRAP2_S1_CLK] = &ne_gcc_qupv3_wrap2_s1_clk.clkr,
+ [NE_GCC_QUPV3_WRAP2_S1_CLK_SRC] = &ne_gcc_qupv3_wrap2_s1_clk_src.clkr,
+ [NE_GCC_QUPV3_WRAP2_S2_CLK] = &ne_gcc_qupv3_wrap2_s2_clk.clkr,
+ [NE_GCC_QUPV3_WRAP2_S2_CLK_SRC] = &ne_gcc_qupv3_wrap2_s2_clk_src.clkr,
+ [NE_GCC_QUPV3_WRAP2_S3_CLK] = &ne_gcc_qupv3_wrap2_s3_clk.clkr,
+ [NE_GCC_QUPV3_WRAP2_S3_CLK_SRC] = &ne_gcc_qupv3_wrap2_s3_clk_src.clkr,
+ [NE_GCC_QUPV3_WRAP2_S4_CLK] = &ne_gcc_qupv3_wrap2_s4_clk.clkr,
+ [NE_GCC_QUPV3_WRAP2_S4_CLK_SRC] = &ne_gcc_qupv3_wrap2_s4_clk_src.clkr,
+ [NE_GCC_QUPV3_WRAP2_S5_CLK] = &ne_gcc_qupv3_wrap2_s5_clk.clkr,
+ [NE_GCC_QUPV3_WRAP2_S5_CLK_SRC] = &ne_gcc_qupv3_wrap2_s5_clk_src.clkr,
+ [NE_GCC_QUPV3_WRAP2_S6_CLK] = &ne_gcc_qupv3_wrap2_s6_clk.clkr,
+ [NE_GCC_QUPV3_WRAP2_S6_CLK_SRC] = &ne_gcc_qupv3_wrap2_s6_clk_src.clkr,
+ [NE_GCC_QUPV3_WRAP2_S_AHB_CLK] = &ne_gcc_qupv3_wrap2_s_ahb_clk.clkr,
+ [NE_GCC_SDCC4_APPS_CLK] = &ne_gcc_sdcc4_apps_clk.clkr,
+ [NE_GCC_SDCC4_APPS_CLK_SRC] = &ne_gcc_sdcc4_apps_clk_src.clkr,
+ [NE_GCC_SDCC4_AXI_CLK] = &ne_gcc_sdcc4_axi_clk.clkr,
+ [NE_GCC_UFS_PHY_AHB_CLK] = &ne_gcc_ufs_phy_ahb_clk.clkr,
+ [NE_GCC_UFS_PHY_AXI_CLK] = &ne_gcc_ufs_phy_axi_clk.clkr,
+ [NE_GCC_UFS_PHY_AXI_CLK_SRC] = &ne_gcc_ufs_phy_axi_clk_src.clkr,
+ [NE_GCC_UFS_PHY_ICE_CORE_CLK] = &ne_gcc_ufs_phy_ice_core_clk.clkr,
+ [NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &ne_gcc_ufs_phy_ice_core_clk_src.clkr,
+ [NE_GCC_UFS_PHY_PHY_AUX_CLK] = &ne_gcc_ufs_phy_phy_aux_clk.clkr,
+ [NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &ne_gcc_ufs_phy_phy_aux_clk_src.clkr,
+ [NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &ne_gcc_ufs_phy_rx_symbol_0_clk.clkr,
+ [NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &ne_gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
+ [NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &ne_gcc_ufs_phy_rx_symbol_1_clk.clkr,
+ [NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &ne_gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
+ [NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &ne_gcc_ufs_phy_tx_symbol_0_clk.clkr,
+ [NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &ne_gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
+ [NE_GCC_UFS_PHY_UNIPRO_CORE_CLK] = &ne_gcc_ufs_phy_unipro_core_clk.clkr,
+ [NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &ne_gcc_ufs_phy_unipro_core_clk_src.clkr,
+ [NE_GCC_USB20_MASTER_CLK] = &ne_gcc_usb20_master_clk.clkr,
+ [NE_GCC_USB20_MASTER_CLK_SRC] = &ne_gcc_usb20_master_clk_src.clkr,
+ [NE_GCC_USB20_MOCK_UTMI_CLK] = &ne_gcc_usb20_mock_utmi_clk.clkr,
+ [NE_GCC_USB20_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb20_mock_utmi_clk_src.clkr,
+ [NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &ne_gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
+ [NE_GCC_USB20_SLEEP_CLK] = &ne_gcc_usb20_sleep_clk.clkr,
+ [NE_GCC_USB31_PRIM_ATB_CLK] = &ne_gcc_usb31_prim_atb_clk.clkr,
+ [NE_GCC_USB31_PRIM_EUD_AHB_CLK] = &ne_gcc_usb31_prim_eud_ahb_clk.clkr,
+ [NE_GCC_USB31_PRIM_MASTER_CLK] = &ne_gcc_usb31_prim_master_clk.clkr,
+ [NE_GCC_USB31_PRIM_MASTER_CLK_SRC] = &ne_gcc_usb31_prim_master_clk_src.clkr,
+ [NE_GCC_USB31_PRIM_MOCK_UTMI_CLK] = &ne_gcc_usb31_prim_mock_utmi_clk.clkr,
+ [NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb31_prim_mock_utmi_clk_src.clkr,
+ [NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
+ &ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr,
+ [NE_GCC_USB31_PRIM_SLEEP_CLK] = &ne_gcc_usb31_prim_sleep_clk.clkr,
+ [NE_GCC_USB31_SEC_ATB_CLK] = &ne_gcc_usb31_sec_atb_clk.clkr,
+ [NE_GCC_USB31_SEC_EUD_AHB_CLK] = &ne_gcc_usb31_sec_eud_ahb_clk.clkr,
+ [NE_GCC_USB31_SEC_MASTER_CLK] = &ne_gcc_usb31_sec_master_clk.clkr,
+ [NE_GCC_USB31_SEC_MASTER_CLK_SRC] = &ne_gcc_usb31_sec_master_clk_src.clkr,
+ [NE_GCC_USB31_SEC_MOCK_UTMI_CLK] = &ne_gcc_usb31_sec_mock_utmi_clk.clkr,
+ [NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb31_sec_mock_utmi_clk_src.clkr,
+ [NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =
+ &ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr,
+ [NE_GCC_USB31_SEC_SLEEP_CLK] = &ne_gcc_usb31_sec_sleep_clk.clkr,
+ [NE_GCC_USB3_PRIM_PHY_AUX_CLK] = &ne_gcc_usb3_prim_phy_aux_clk.clkr,
+ [NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &ne_gcc_usb3_prim_phy_aux_clk_src.clkr,
+ [NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &ne_gcc_usb3_prim_phy_com_aux_clk.clkr,
+ [NE_GCC_USB3_PRIM_PHY_PIPE_CLK] = &ne_gcc_usb3_prim_phy_pipe_clk.clkr,
+ [NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &ne_gcc_usb3_prim_phy_pipe_clk_src.clkr,
+ [NE_GCC_USB3_SEC_PHY_AUX_CLK] = &ne_gcc_usb3_sec_phy_aux_clk.clkr,
+ [NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &ne_gcc_usb3_sec_phy_aux_clk_src.clkr,
+ [NE_GCC_USB3_SEC_PHY_COM_AUX_CLK] = &ne_gcc_usb3_sec_phy_com_aux_clk.clkr,
+ [NE_GCC_USB3_SEC_PHY_PIPE_CLK] = &ne_gcc_usb3_sec_phy_pipe_clk.clkr,
+ [NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &ne_gcc_usb3_sec_phy_pipe_clk_src.clkr,
+};
+
+static struct gdsc *ne_gcc_nord_gdscs[] = {
+ [NE_GCC_UFS_MEM_PHY_GDSC] = &ne_gcc_ufs_mem_phy_gdsc,
+ [NE_GCC_UFS_PHY_GDSC] = &ne_gcc_ufs_phy_gdsc,
+ [NE_GCC_USB20_PRIM_GDSC] = &ne_gcc_usb20_prim_gdsc,
+ [NE_GCC_USB31_PRIM_GDSC] = &ne_gcc_usb31_prim_gdsc,
+ [NE_GCC_USB31_SEC_GDSC] = &ne_gcc_usb31_sec_gdsc,
+ [NE_GCC_USB3_PHY_GDSC] = &ne_gcc_usb3_phy_gdsc,
+ [NE_GCC_USB3_SEC_PHY_GDSC] = &ne_gcc_usb3_sec_phy_gdsc,
+};
+
+static const struct qcom_reset_map ne_gcc_nord_resets[] = {
+ [NE_GCC_GPU_2_BCR] = { 0x34000 },
+ [NE_GCC_QUPV3_WRAPPER_2_BCR] = { 0x38000 },
+ [NE_GCC_SDCC4_BCR] = { 0x18000 },
+ [NE_GCC_UFS_PHY_BCR] = { 0x33000 },
+ [NE_GCC_USB20_PRIM_BCR] = { 0x31000 },
+ [NE_GCC_USB31_PRIM_BCR] = { 0x2a000 },
+ [NE_GCC_USB31_SEC_BCR] = { 0x2c000 },
+ [NE_GCC_USB3_DP_PHY_PRIM_BCR] = { 0x2b008 },
+ [NE_GCC_USB3_DP_PHY_SEC_BCR] = { 0x2d008 },
+ [NE_GCC_USB3_PHY_PRIM_BCR] = { 0x2b000 },
+ [NE_GCC_USB3_PHY_SEC_BCR] = { 0x2d000 },
+ [NE_GCC_USB3PHY_PHY_PRIM_BCR] = { 0x2b004 },
+ [NE_GCC_USB3PHY_PHY_SEC_BCR] = { 0x2d004 },
+};
+
+static const struct clk_rcg_dfs_data ne_gcc_nord_dfs_clocks[] = {
+ DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s0_clk_src),
+ DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s1_clk_src),
+ DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s2_clk_src),
+ DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s3_clk_src),
+ DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s4_clk_src),
+ DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s5_clk_src),
+ DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s6_clk_src),
+};
+
+static const struct regmap_config ne_gcc_nord_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xf41f0,
+ .fast_io = true,
+};
+
+static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap)
+{
+ /* FORCE_MEM_CORE_ON for ne_gcc_ufs_phy_ice_core_clk and ne_gcc_ufs_phy_axi_clk */
+ qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_ice_core_clk, true);
+ qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true);
+}
+
+static struct qcom_cc_driver_data ne_gcc_nord_driver_data = {
+ .dfs_rcgs = ne_gcc_nord_dfs_clocks,
+ .num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks),
+ .clk_regs_configure = clk_nord_regs_configure,
+};
+
+static const struct qcom_cc_desc ne_gcc_nord_desc = {
+ .config = &ne_gcc_nord_regmap_config,
+ .clks = ne_gcc_nord_clocks,
+ .num_clks = ARRAY_SIZE(ne_gcc_nord_clocks),
+ .resets = ne_gcc_nord_resets,
+ .num_resets = ARRAY_SIZE(ne_gcc_nord_resets),
+ .gdscs = ne_gcc_nord_gdscs,
+ .num_gdscs = ARRAY_SIZE(ne_gcc_nord_gdscs),
+ .driver_data = &ne_gcc_nord_driver_data,
+};
+
+static const struct of_device_id ne_gcc_nord_match_table[] = {
+ { .compatible = "qcom,nord-negcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ne_gcc_nord_match_table);
+
+static int ne_gcc_nord_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &ne_gcc_nord_desc);
+}
+
+static struct platform_driver ne_gcc_nord_driver = {
+ .probe = ne_gcc_nord_probe,
+ .driver = {
+ .name = "negcc-nord",
+ .of_match_table = ne_gcc_nord_match_table,
+ },
+};
+
+module_platform_driver(ne_gcc_nord_driver);
+
+MODULE_DESCRIPTION("QTI NEGCC NORD Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/qcom/nwgcc-nord.c b/drivers/clk/qcom/nwgcc-nord.c
new file mode 100644
index 0000000000000000000000000000000000000000..163ab63c872bc7d5132d68bf0ec3e05f5814974d
--- /dev/null
+++ b/drivers/clk/qcom/nwgcc-nord.c
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,nord-nwgcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "reset.h"
+
+enum {
+ DT_BI_TCXO,
+ DT_SLEEP_CLK,
+};
+
+enum {
+ P_BI_TCXO,
+ P_NW_GCC_GPLL0_OUT_EVEN,
+ P_NW_GCC_GPLL0_OUT_MAIN,
+ P_SLEEP_CLK,
+};
+
+static struct clk_alpha_pll nw_gcc_gpll0 = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gpll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_nw_gcc_gpll0_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv nw_gcc_gpll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_nw_gcc_gpll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_nw_gcc_gpll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gpll0_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nw_gcc_gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct parent_map nw_gcc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_NW_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_SLEEP_CLK, 5 },
+ { P_NW_GCC_GPLL0_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data nw_gcc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &nw_gcc_gpll0.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+ { .hw = &nw_gcc_gpll0_out_even.clkr.hw },
+};
+
+static const struct freq_tbl ftbl_nw_gcc_gp1_clk_src[] = {
+ F(60000000, P_NW_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
+ F(100000000, P_NW_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(200000000, P_NW_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nw_gcc_gp1_clk_src = {
+ .cmd_rcgr = 0x20004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = nw_gcc_parent_map_0,
+ .freq_tbl = ftbl_nw_gcc_gp1_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gp1_clk_src",
+ .parent_data = nw_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nw_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 nw_gcc_gp2_clk_src = {
+ .cmd_rcgr = 0x21004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = nw_gcc_parent_map_0,
+ .freq_tbl = ftbl_nw_gcc_gp1_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gp2_clk_src",
+ .parent_data = nw_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nw_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_branch nw_gcc_acmu_mux_clk = {
+ .halt_reg = 0x1f01c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f01c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_acmu_mux_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_camera_hf_axi_clk = {
+ .halt_reg = 0x16008,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x16008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x16008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_camera_hf_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_camera_sf_axi_clk = {
+ .halt_reg = 0x1601c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x1601c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1601c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_camera_sf_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_camera_trig_clk = {
+ .halt_reg = 0x16034,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x16034,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x16034,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_camera_trig_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_disp_0_hf_axi_clk = {
+ .halt_reg = 0x18008,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x18008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x18008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_disp_0_hf_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_disp_0_trig_clk = {
+ .halt_reg = 0x1801c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x1801c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1801c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_disp_0_trig_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_disp_1_hf_axi_clk = {
+ .halt_reg = 0x19008,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x19008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x19008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_disp_1_hf_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_disp_1_trig_clk = {
+ .halt_reg = 0x1901c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x1901c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1901c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_disp_1_trig_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_dprx0_axi_hf_clk = {
+ .halt_reg = 0x29004,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x29004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x29004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_dprx0_axi_hf_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_dprx1_axi_hf_clk = {
+ .halt_reg = 0x2a004,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x2a004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_dprx1_axi_hf_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_eva_axi0_clk = {
+ .halt_reg = 0x1b008,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x1b008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1b008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_eva_axi0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_eva_axi0c_clk = {
+ .halt_reg = 0x1b01c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x1b01c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1b01c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_eva_axi0c_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_eva_trig_clk = {
+ .halt_reg = 0x1b028,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x1b028,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1b028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_eva_trig_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_frq_measure_ref_clk = {
+ .halt_reg = 0x1f008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_frq_measure_ref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_gp1_clk = {
+ .halt_reg = 0x20000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x20000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gp1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nw_gcc_gp1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_gp2_clk = {
+ .halt_reg = 0x21000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x21000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gp2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nw_gcc_gp2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_gpu_2_gpll0_clk_src = {
+ .halt_reg = 0x24150,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x24150,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x76000,
+ .enable_mask = BIT(6),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gpu_2_gpll0_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nw_gcc_gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_gpu_2_gpll0_div_clk_src = {
+ .halt_reg = 0x24158,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x24158,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x76000,
+ .enable_mask = BIT(7),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gpu_2_gpll0_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nw_gcc_gpll0_out_even.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_gpu_2_hscnoc_gfx_clk = {
+ .halt_reg = 0x2400c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x2400c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2400c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gpu_2_hscnoc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_gpu_gpll0_clk_src = {
+ .halt_reg = 0x23150,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x23150,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x76000,
+ .enable_mask = BIT(4),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gpu_gpll0_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nw_gcc_gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_gpu_gpll0_div_clk_src = {
+ .halt_reg = 0x23158,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x23158,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x76000,
+ .enable_mask = BIT(5),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gpu_gpll0_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nw_gcc_gpll0_out_even.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_gpu_hscnoc_gfx_clk = {
+ .halt_reg = 0x2300c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x2300c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gpu_hscnoc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_gpu_smmu_vote_clk = {
+ .halt_reg = 0x86038,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x86038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_gpu_smmu_vote_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_hscnoc_gpu_2_axi_clk = {
+ .halt_reg = 0x24160,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x24160,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x24160,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_hscnoc_gpu_2_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_hscnoc_gpu_axi_clk = {
+ .halt_reg = 0x23160,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x23160,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x23160,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_hscnoc_gpu_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_mmu_1_tcu_vote_clk = {
+ .halt_reg = 0x86040,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x86040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_mmu_1_tcu_vote_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_video_axi0_clk = {
+ .halt_reg = 0x1a008,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x1a008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1a008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_video_axi0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_video_axi0c_clk = {
+ .halt_reg = 0x1a01c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x1a01c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1a01c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_video_axi0c_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nw_gcc_video_axi1_clk = {
+ .halt_reg = 0x1a030,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x1a030,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1a030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nw_gcc_video_axi1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *nw_gcc_nord_clocks[] = {
+ [NW_GCC_ACMU_MUX_CLK] = &nw_gcc_acmu_mux_clk.clkr,
+ [NW_GCC_CAMERA_HF_AXI_CLK] = &nw_gcc_camera_hf_axi_clk.clkr,
+ [NW_GCC_CAMERA_SF_AXI_CLK] = &nw_gcc_camera_sf_axi_clk.clkr,
+ [NW_GCC_CAMERA_TRIG_CLK] = &nw_gcc_camera_trig_clk.clkr,
+ [NW_GCC_DISP_0_HF_AXI_CLK] = &nw_gcc_disp_0_hf_axi_clk.clkr,
+ [NW_GCC_DISP_0_TRIG_CLK] = &nw_gcc_disp_0_trig_clk.clkr,
+ [NW_GCC_DISP_1_HF_AXI_CLK] = &nw_gcc_disp_1_hf_axi_clk.clkr,
+ [NW_GCC_DISP_1_TRIG_CLK] = &nw_gcc_disp_1_trig_clk.clkr,
+ [NW_GCC_DPRX0_AXI_HF_CLK] = &nw_gcc_dprx0_axi_hf_clk.clkr,
+ [NW_GCC_DPRX1_AXI_HF_CLK] = &nw_gcc_dprx1_axi_hf_clk.clkr,
+ [NW_GCC_EVA_AXI0_CLK] = &nw_gcc_eva_axi0_clk.clkr,
+ [NW_GCC_EVA_AXI0C_CLK] = &nw_gcc_eva_axi0c_clk.clkr,
+ [NW_GCC_EVA_TRIG_CLK] = &nw_gcc_eva_trig_clk.clkr,
+ [NW_GCC_FRQ_MEASURE_REF_CLK] = &nw_gcc_frq_measure_ref_clk.clkr,
+ [NW_GCC_GP1_CLK] = &nw_gcc_gp1_clk.clkr,
+ [NW_GCC_GP1_CLK_SRC] = &nw_gcc_gp1_clk_src.clkr,
+ [NW_GCC_GP2_CLK] = &nw_gcc_gp2_clk.clkr,
+ [NW_GCC_GP2_CLK_SRC] = &nw_gcc_gp2_clk_src.clkr,
+ [NW_GCC_GPLL0] = &nw_gcc_gpll0.clkr,
+ [NW_GCC_GPLL0_OUT_EVEN] = &nw_gcc_gpll0_out_even.clkr,
+ [NW_GCC_GPU_2_GPLL0_CLK_SRC] = &nw_gcc_gpu_2_gpll0_clk_src.clkr,
+ [NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &nw_gcc_gpu_2_gpll0_div_clk_src.clkr,
+ [NW_GCC_GPU_2_HSCNOC_GFX_CLK] = &nw_gcc_gpu_2_hscnoc_gfx_clk.clkr,
+ [NW_GCC_GPU_GPLL0_CLK_SRC] = &nw_gcc_gpu_gpll0_clk_src.clkr,
+ [NW_GCC_GPU_GPLL0_DIV_CLK_SRC] = &nw_gcc_gpu_gpll0_div_clk_src.clkr,
+ [NW_GCC_GPU_HSCNOC_GFX_CLK] = &nw_gcc_gpu_hscnoc_gfx_clk.clkr,
+ [NW_GCC_GPU_SMMU_VOTE_CLK] = &nw_gcc_gpu_smmu_vote_clk.clkr,
+ [NW_GCC_HSCNOC_GPU_2_AXI_CLK] = &nw_gcc_hscnoc_gpu_2_axi_clk.clkr,
+ [NW_GCC_HSCNOC_GPU_AXI_CLK] = &nw_gcc_hscnoc_gpu_axi_clk.clkr,
+ [NW_GCC_MMU_1_TCU_VOTE_CLK] = &nw_gcc_mmu_1_tcu_vote_clk.clkr,
+ [NW_GCC_VIDEO_AXI0_CLK] = &nw_gcc_video_axi0_clk.clkr,
+ [NW_GCC_VIDEO_AXI0C_CLK] = &nw_gcc_video_axi0c_clk.clkr,
+ [NW_GCC_VIDEO_AXI1_CLK] = &nw_gcc_video_axi1_clk.clkr,
+};
+
+static const struct qcom_reset_map nw_gcc_nord_resets[] = {
+ [NW_GCC_CAMERA_BCR] = { 0x16000 },
+ [NW_GCC_DISPLAY_0_BCR] = { 0x18000 },
+ [NW_GCC_DISPLAY_1_BCR] = { 0x19000 },
+ [NW_GCC_DPRX0_BCR] = { 0x29000 },
+ [NW_GCC_DPRX1_BCR] = { 0x2a000 },
+ [NW_GCC_EVA_BCR] = { 0x1b000 },
+ [NW_GCC_GPU_2_BCR] = { 0x24000 },
+ [NW_GCC_GPU_BCR] = { 0x23000 },
+ [NW_GCC_VIDEO_BCR] = { 0x1a000 },
+};
+
+static u32 nw_gcc_nord_critical_cbcrs[] = {
+ 0x16004, /* NW_GCC_CAMERA_AHB_CLK */
+ 0x16030, /* NW_GCC_CAMERA_XO_CLK */
+ 0x18004, /* NW_GCC_DISP_0_AHB_CLK */
+ 0x19004, /* NW_GCC_DISP_1_AHB_CLK */
+ 0x29018, /* NW_GCC_DPRX0_CFG_AHB_CLK */
+ 0x2a018, /* NW_GCC_DPRX1_CFG_AHB_CLK */
+ 0x1b004, /* NW_GCC_EVA_AHB_CLK */
+ 0x1b024, /* NW_GCC_EVA_XO_CLK */
+ 0x23004, /* NW_GCC_GPU_CFG_AHB_CLK */
+ 0x24004, /* NW_GCC_GPU_2_CFG_AHB_CLK */
+ 0x1a004, /* NW_GCC_VIDEO_AHB_CLK */
+ 0x1a044, /* NW_GCC_VIDEO_XO_CLK */
+};
+
+static struct qcom_cc_driver_data nw_gcc_nord_driver_data = {
+ .clk_cbcrs = nw_gcc_nord_critical_cbcrs,
+ .num_clk_cbcrs = ARRAY_SIZE(nw_gcc_nord_critical_cbcrs),
+};
+
+static const struct regmap_config nw_gcc_nord_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xf41f0,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc nw_gcc_nord_desc = {
+ .config = &nw_gcc_nord_regmap_config,
+ .clks = nw_gcc_nord_clocks,
+ .num_clks = ARRAY_SIZE(nw_gcc_nord_clocks),
+ .resets = nw_gcc_nord_resets,
+ .num_resets = ARRAY_SIZE(nw_gcc_nord_resets),
+ .driver_data = &nw_gcc_nord_driver_data,
+};
+
+static const struct of_device_id nw_gcc_nord_match_table[] = {
+ { .compatible = "qcom,nord-nwgcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, nw_gcc_nord_match_table);
+
+static int nw_gcc_nord_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &nw_gcc_nord_desc);
+}
+
+static struct platform_driver nw_gcc_nord_driver = {
+ .probe = nw_gcc_nord_probe,
+ .driver = {
+ .name = "nwgcc-nord",
+ .of_match_table = nw_gcc_nord_match_table,
+ },
+};
+
+module_platform_driver(nw_gcc_nord_driver);
+
+MODULE_DESCRIPTION("QTI NWGCC NORD Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/qcom/segcc-nord.c b/drivers/clk/qcom/segcc-nord.c
new file mode 100644
index 0000000000000000000000000000000000000000..1aab0999de4dde7262bd694f7d7f955b2a9cb66e
--- /dev/null
+++ b/drivers/clk/qcom/segcc-nord.c
@@ -0,0 +1,1609 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,nord-segcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ DT_BI_TCXO,
+ DT_SLEEP_CLK,
+};
+
+enum {
+ P_BI_TCXO,
+ P_SE_GCC_GPLL0_OUT_EVEN,
+ P_SE_GCC_GPLL0_OUT_MAIN,
+ P_SE_GCC_GPLL2_OUT_MAIN,
+ P_SE_GCC_GPLL4_OUT_MAIN,
+ P_SE_GCC_GPLL5_OUT_MAIN,
+ P_SLEEP_CLK,
+};
+
+static struct clk_alpha_pll se_gcc_gpll0 = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_gpll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_se_gcc_gpll0_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv se_gcc_gpll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_se_gcc_gpll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_se_gcc_gpll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_gpll0_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static struct clk_alpha_pll se_gcc_gpll2 = {
+ .offset = 0x2000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(2),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_gpll2",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll se_gcc_gpll4 = {
+ .offset = 0x4000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(4),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_gpll4",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll se_gcc_gpll5 = {
+ .offset = 0x5000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(5),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_gpll5",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+ },
+ },
+};
+
+static const struct parent_map se_gcc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_SE_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_SE_GCC_GPLL0_OUT_EVEN, 2 },
+};
+
+static const struct clk_parent_data se_gcc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &se_gcc_gpll0.clkr.hw },
+ { .hw = &se_gcc_gpll0_out_even.clkr.hw },
+};
+
+static const struct parent_map se_gcc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_SE_GCC_GPLL0_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data se_gcc_parent_data_1[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &se_gcc_gpll0.clkr.hw },
+};
+
+static const struct parent_map se_gcc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_SE_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const struct clk_parent_data se_gcc_parent_data_2[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &se_gcc_gpll0.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map se_gcc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_SE_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_SE_GCC_GPLL5_OUT_MAIN, 3 },
+ { P_SE_GCC_GPLL4_OUT_MAIN, 5 },
+ { P_SE_GCC_GPLL2_OUT_MAIN, 6 },
+};
+
+static const struct clk_parent_data se_gcc_parent_data_3[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &se_gcc_gpll0.clkr.hw },
+ { .hw = &se_gcc_gpll5.clkr.hw },
+ { .hw = &se_gcc_gpll4.clkr.hw },
+ { .hw = &se_gcc_gpll2.clkr.hw },
+};
+
+static const struct parent_map se_gcc_parent_map_4[] = {
+ { P_BI_TCXO, 0 },
+ { P_SE_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_SE_GCC_GPLL0_OUT_EVEN, 2 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const struct clk_parent_data se_gcc_parent_data_4[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &se_gcc_gpll0.clkr.hw },
+ { .hw = &se_gcc_gpll0_out_even.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct freq_tbl ftbl_se_gcc_eee_emac0_clk_src[] = {
+ F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
+ F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 se_gcc_eee_emac0_clk_src = {
+ .cmd_rcgr = 0x240b8,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_2,
+ .freq_tbl = ftbl_se_gcc_eee_emac0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_eee_emac0_clk_src",
+ .parent_data = se_gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 se_gcc_eee_emac1_clk_src = {
+ .cmd_rcgr = 0x250b8,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_2,
+ .freq_tbl = ftbl_se_gcc_eee_emac0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_eee_emac1_clk_src",
+ .parent_data = se_gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_se_gcc_emac0_phy_aux_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 se_gcc_emac0_phy_aux_clk_src = {
+ .cmd_rcgr = 0x24030,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_2,
+ .freq_tbl = ftbl_se_gcc_emac0_phy_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_phy_aux_clk_src",
+ .parent_data = se_gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_se_gcc_emac0_ptp_clk_src[] = {
+ F(150000000, P_SE_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
+ F(250000000, P_SE_GCC_GPLL5_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 se_gcc_emac0_ptp_clk_src = {
+ .cmd_rcgr = 0x24084,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_3,
+ .freq_tbl = ftbl_se_gcc_emac0_ptp_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_ptp_clk_src",
+ .parent_data = se_gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_se_gcc_emac0_rgmii_clk_src[] = {
+ F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
+ F(120000000, P_SE_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
+ F(250000000, P_SE_GCC_GPLL5_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 se_gcc_emac0_rgmii_clk_src = {
+ .cmd_rcgr = 0x2406c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_3,
+ .freq_tbl = ftbl_se_gcc_emac0_rgmii_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_rgmii_clk_src",
+ .parent_data = se_gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 se_gcc_emac1_phy_aux_clk_src = {
+ .cmd_rcgr = 0x25030,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_2,
+ .freq_tbl = ftbl_se_gcc_emac0_phy_aux_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_phy_aux_clk_src",
+ .parent_data = se_gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 se_gcc_emac1_ptp_clk_src = {
+ .cmd_rcgr = 0x25084,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_3,
+ .freq_tbl = ftbl_se_gcc_emac0_ptp_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_ptp_clk_src",
+ .parent_data = se_gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 se_gcc_emac1_rgmii_clk_src = {
+ .cmd_rcgr = 0x2506c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_3,
+ .freq_tbl = ftbl_se_gcc_emac0_rgmii_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_rgmii_clk_src",
+ .parent_data = se_gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_se_gcc_gp1_clk_src[] = {
+ F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
+ F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(200000000, P_SE_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 se_gcc_gp1_clk_src = {
+ .cmd_rcgr = 0x19004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_4,
+ .freq_tbl = ftbl_se_gcc_gp1_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_gp1_clk_src",
+ .parent_data = se_gcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_4),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 se_gcc_gp2_clk_src = {
+ .cmd_rcgr = 0x1a004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_4,
+ .freq_tbl = ftbl_se_gcc_gp1_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_gp2_clk_src",
+ .parent_data = se_gcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_4),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_se_gcc_qupv3_wrap0_s0_clk_src[] = {
+ F(7372800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625),
+ F(14745600, P_SE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(29491200, P_SE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625),
+ F(32000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 75),
+ F(48000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 25),
+ F(51200000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 32, 375),
+ F(64000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 8, 75),
+ F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
+ F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
+ F(80000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 15),
+ F(96000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 25),
+ F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(102400000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 64, 375),
+ F(112000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 14, 75),
+ F(117964800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625),
+ F(120000000, P_SE_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
+ { }
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap0_s0_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap0_s0_clk_src",
+ .parent_data = se_gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap0_s0_clk_src = {
+ .cmd_rcgr = 0x2616c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_1,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap0_s0_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap0_s1_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap0_s1_clk_src",
+ .parent_data = se_gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap0_s1_clk_src = {
+ .cmd_rcgr = 0x262a8,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_1,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap0_s1_clk_src_init,
+};
+
+static const struct freq_tbl ftbl_se_gcc_qupv3_wrap0_s2_clk_src[] = {
+ F(7372800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625),
+ F(14745600, P_SE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(29491200, P_SE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625),
+ F(32000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 75),
+ F(48000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 25),
+ F(51200000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 32, 375),
+ F(64000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 8, 75),
+ F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
+ F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
+ F(80000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 15),
+ F(96000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 25),
+ F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ { }
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap0_s2_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap0_s2_clk_src",
+ .parent_data = se_gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap0_s2_clk_src = {
+ .cmd_rcgr = 0x263e4,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_1,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap0_s2_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap0_s3_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap0_s3_clk_src",
+ .parent_data = se_gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap0_s3_clk_src = {
+ .cmd_rcgr = 0x26520,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_1,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap0_s3_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap0_s4_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap0_s4_clk_src",
+ .parent_data = se_gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap0_s4_clk_src = {
+ .cmd_rcgr = 0x2665c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_1,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap0_s4_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap0_s5_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap0_s5_clk_src",
+ .parent_data = se_gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap0_s5_clk_src = {
+ .cmd_rcgr = 0x26798,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_1,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap0_s5_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap0_s6_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap0_s6_clk_src",
+ .parent_data = se_gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap0_s6_clk_src = {
+ .cmd_rcgr = 0x268d4,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_1,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap0_s6_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap1_s0_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap1_s0_clk_src",
+ .parent_data = se_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap1_s0_clk_src = {
+ .cmd_rcgr = 0x2716c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_0,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap1_s0_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap1_s1_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap1_s1_clk_src",
+ .parent_data = se_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap1_s1_clk_src = {
+ .cmd_rcgr = 0x272a8,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_0,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap1_s1_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap1_s2_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap1_s2_clk_src",
+ .parent_data = se_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap1_s2_clk_src = {
+ .cmd_rcgr = 0x273e4,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_0,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap1_s2_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap1_s3_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap1_s3_clk_src",
+ .parent_data = se_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap1_s3_clk_src = {
+ .cmd_rcgr = 0x27520,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_0,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap1_s3_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap1_s4_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap1_s4_clk_src",
+ .parent_data = se_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap1_s4_clk_src = {
+ .cmd_rcgr = 0x2765c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_0,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap1_s4_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap1_s5_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap1_s5_clk_src",
+ .parent_data = se_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap1_s5_clk_src = {
+ .cmd_rcgr = 0x27798,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_0,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap1_s5_clk_src_init,
+};
+
+static struct clk_init_data se_gcc_qupv3_wrap1_s6_clk_src_init = {
+ .name = "se_gcc_qupv3_wrap1_s6_clk_src",
+ .parent_data = se_gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_no_init_park_ops,
+};
+
+static struct clk_rcg2 se_gcc_qupv3_wrap1_s6_clk_src = {
+ .cmd_rcgr = 0x278d4,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = se_gcc_parent_map_0,
+ .freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &se_gcc_qupv3_wrap1_s6_clk_src_init,
+};
+
+static struct clk_branch se_gcc_eee_emac0_clk = {
+ .halt_reg = 0x240b4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x240b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_eee_emac0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_eee_emac0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_eee_emac1_clk = {
+ .halt_reg = 0x250b4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x250b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_eee_emac1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_eee_emac1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac0_axi_clk = {
+ .halt_reg = 0x2401c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x2401c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2401c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac0_cc_sgmiiphy_rx_clk = {
+ .halt_reg = 0x24064,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x24064,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_cc_sgmiiphy_rx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac0_cc_sgmiiphy_tx_clk = {
+ .halt_reg = 0x2405c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2405c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_cc_sgmiiphy_tx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac0_phy_aux_clk = {
+ .halt_reg = 0x2402c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2402c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_emac0_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac0_ptp_clk = {
+ .halt_reg = 0x24048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x24048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_ptp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_emac0_ptp_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac0_rgmii_clk = {
+ .halt_reg = 0x24058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x24058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_rgmii_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_emac0_rgmii_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac0_rpcs_rx_clk = {
+ .halt_reg = 0x240a8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x240a8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_rpcs_rx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac0_rpcs_tx_clk = {
+ .halt_reg = 0x240a4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x240a4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_rpcs_tx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac0_xgxs_rx_clk = {
+ .halt_reg = 0x240b0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x240b0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_xgxs_rx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac0_xgxs_tx_clk = {
+ .halt_reg = 0x240ac,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x240ac,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac0_xgxs_tx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac1_axi_clk = {
+ .halt_reg = 0x2501c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x2501c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x2501c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac1_cc_sgmiiphy_rx_clk = {
+ .halt_reg = 0x25064,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25064,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_cc_sgmiiphy_rx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac1_cc_sgmiiphy_tx_clk = {
+ .halt_reg = 0x2505c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2505c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_cc_sgmiiphy_tx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac1_phy_aux_clk = {
+ .halt_reg = 0x2502c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2502c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_emac1_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac1_ptp_clk = {
+ .halt_reg = 0x25048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_ptp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_emac1_ptp_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac1_rgmii_clk = {
+ .halt_reg = 0x25058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_rgmii_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_emac1_rgmii_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac1_rpcs_rx_clk = {
+ .halt_reg = 0x250a8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x250a8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_rpcs_rx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac1_rpcs_tx_clk = {
+ .halt_reg = 0x250a4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x250a4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_rpcs_tx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac1_xgxs_rx_clk = {
+ .halt_reg = 0x250b0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x250b0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_xgxs_rx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_emac1_xgxs_tx_clk = {
+ .halt_reg = 0x250ac,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x250ac,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_emac1_xgxs_tx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_frq_measure_ref_clk = {
+ .halt_reg = 0x18008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x18008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_frq_measure_ref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_gp1_clk = {
+ .halt_reg = 0x19000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_gp1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_gp1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_gp2_clk = {
+ .halt_reg = 0x1a000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1a000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_gp2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_gp2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_mmu_2_tcu_vote_clk = {
+ .halt_reg = 0x57040,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_mmu_2_tcu_vote_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap0_core_2x_clk = {
+ .halt_reg = 0x26020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(15),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap0_core_2x_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap0_core_clk = {
+ .halt_reg = 0x2600c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(14),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap0_core_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap0_m_ahb_clk = {
+ .halt_reg = 0x26004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x26004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(12),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap0_m_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap0_s0_clk = {
+ .halt_reg = 0x2615c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(16),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap0_s0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap0_s1_clk = {
+ .halt_reg = 0x26298,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(17),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap0_s1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap0_s2_clk = {
+ .halt_reg = 0x263d4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(18),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap0_s2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap0_s3_clk = {
+ .halt_reg = 0x26510,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(19),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap0_s3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap0_s4_clk = {
+ .halt_reg = 0x2664c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(20),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap0_s4_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap0_s5_clk = {
+ .halt_reg = 0x26788,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(21),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap0_s5_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap0_s6_clk = {
+ .halt_reg = 0x268c4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(22),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap0_s6_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap0_s_ahb_clk = {
+ .halt_reg = 0x26008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x26008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(13),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap0_s_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap1_core_2x_clk = {
+ .halt_reg = 0x27020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(26),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap1_core_2x_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap1_core_clk = {
+ .halt_reg = 0x2700c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(25),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap1_core_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap1_m_ahb_clk = {
+ .halt_reg = 0x27004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x27004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(23),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap1_m_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap1_s0_clk = {
+ .halt_reg = 0x2715c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(27),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap1_s0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap1_s1_clk = {
+ .halt_reg = 0x27298,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(28),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap1_s1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap1_s2_clk = {
+ .halt_reg = 0x273d4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(29),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap1_s2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap1_s3_clk = {
+ .halt_reg = 0x27510,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(30),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap1_s3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap1_s4_clk = {
+ .halt_reg = 0x2764c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(31),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap1_s4_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap1_s5_clk = {
+ .halt_reg = 0x27788,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap1_s5_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap1_s6_clk = {
+ .halt_reg = 0x278c4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(1),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap1_s6_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &se_gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch se_gcc_qupv3_wrap1_s_ahb_clk = {
+ .halt_reg = 0x27008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x27008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x57000,
+ .enable_mask = BIT(24),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "se_gcc_qupv3_wrap1_s_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc se_gcc_emac0_gdsc = {
+ .gdscr = 0x24004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "se_gcc_emac0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc se_gcc_emac1_gdsc = {
+ .gdscr = 0x25004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "se_gcc_emac1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct clk_regmap *se_gcc_nord_clocks[] = {
+ [SE_GCC_EEE_EMAC0_CLK] = &se_gcc_eee_emac0_clk.clkr,
+ [SE_GCC_EEE_EMAC0_CLK_SRC] = &se_gcc_eee_emac0_clk_src.clkr,
+ [SE_GCC_EEE_EMAC1_CLK] = &se_gcc_eee_emac1_clk.clkr,
+ [SE_GCC_EEE_EMAC1_CLK_SRC] = &se_gcc_eee_emac1_clk_src.clkr,
+ [SE_GCC_EMAC0_AXI_CLK] = &se_gcc_emac0_axi_clk.clkr,
+ [SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac0_cc_sgmiiphy_rx_clk.clkr,
+ [SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac0_cc_sgmiiphy_tx_clk.clkr,
+ [SE_GCC_EMAC0_PHY_AUX_CLK] = &se_gcc_emac0_phy_aux_clk.clkr,
+ [SE_GCC_EMAC0_PHY_AUX_CLK_SRC] = &se_gcc_emac0_phy_aux_clk_src.clkr,
+ [SE_GCC_EMAC0_PTP_CLK] = &se_gcc_emac0_ptp_clk.clkr,
+ [SE_GCC_EMAC0_PTP_CLK_SRC] = &se_gcc_emac0_ptp_clk_src.clkr,
+ [SE_GCC_EMAC0_RGMII_CLK] = &se_gcc_emac0_rgmii_clk.clkr,
+ [SE_GCC_EMAC0_RGMII_CLK_SRC] = &se_gcc_emac0_rgmii_clk_src.clkr,
+ [SE_GCC_EMAC0_RPCS_RX_CLK] = &se_gcc_emac0_rpcs_rx_clk.clkr,
+ [SE_GCC_EMAC0_RPCS_TX_CLK] = &se_gcc_emac0_rpcs_tx_clk.clkr,
+ [SE_GCC_EMAC0_XGXS_RX_CLK] = &se_gcc_emac0_xgxs_rx_clk.clkr,
+ [SE_GCC_EMAC0_XGXS_TX_CLK] = &se_gcc_emac0_xgxs_tx_clk.clkr,
+ [SE_GCC_EMAC1_AXI_CLK] = &se_gcc_emac1_axi_clk.clkr,
+ [SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac1_cc_sgmiiphy_rx_clk.clkr,
+ [SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac1_cc_sgmiiphy_tx_clk.clkr,
+ [SE_GCC_EMAC1_PHY_AUX_CLK] = &se_gcc_emac1_phy_aux_clk.clkr,
+ [SE_GCC_EMAC1_PHY_AUX_CLK_SRC] = &se_gcc_emac1_phy_aux_clk_src.clkr,
+ [SE_GCC_EMAC1_PTP_CLK] = &se_gcc_emac1_ptp_clk.clkr,
+ [SE_GCC_EMAC1_PTP_CLK_SRC] = &se_gcc_emac1_ptp_clk_src.clkr,
+ [SE_GCC_EMAC1_RGMII_CLK] = &se_gcc_emac1_rgmii_clk.clkr,
+ [SE_GCC_EMAC1_RGMII_CLK_SRC] = &se_gcc_emac1_rgmii_clk_src.clkr,
+ [SE_GCC_EMAC1_RPCS_RX_CLK] = &se_gcc_emac1_rpcs_rx_clk.clkr,
+ [SE_GCC_EMAC1_RPCS_TX_CLK] = &se_gcc_emac1_rpcs_tx_clk.clkr,
+ [SE_GCC_EMAC1_XGXS_RX_CLK] = &se_gcc_emac1_xgxs_rx_clk.clkr,
+ [SE_GCC_EMAC1_XGXS_TX_CLK] = &se_gcc_emac1_xgxs_tx_clk.clkr,
+ [SE_GCC_FRQ_MEASURE_REF_CLK] = &se_gcc_frq_measure_ref_clk.clkr,
+ [SE_GCC_GP1_CLK] = &se_gcc_gp1_clk.clkr,
+ [SE_GCC_GP1_CLK_SRC] = &se_gcc_gp1_clk_src.clkr,
+ [SE_GCC_GP2_CLK] = &se_gcc_gp2_clk.clkr,
+ [SE_GCC_GP2_CLK_SRC] = &se_gcc_gp2_clk_src.clkr,
+ [SE_GCC_GPLL0] = &se_gcc_gpll0.clkr,
+ [SE_GCC_GPLL0_OUT_EVEN] = &se_gcc_gpll0_out_even.clkr,
+ [SE_GCC_GPLL2] = &se_gcc_gpll2.clkr,
+ [SE_GCC_GPLL4] = &se_gcc_gpll4.clkr,
+ [SE_GCC_GPLL5] = &se_gcc_gpll5.clkr,
+ [SE_GCC_MMU_2_TCU_VOTE_CLK] = &se_gcc_mmu_2_tcu_vote_clk.clkr,
+ [SE_GCC_QUPV3_WRAP0_CORE_2X_CLK] = &se_gcc_qupv3_wrap0_core_2x_clk.clkr,
+ [SE_GCC_QUPV3_WRAP0_CORE_CLK] = &se_gcc_qupv3_wrap0_core_clk.clkr,
+ [SE_GCC_QUPV3_WRAP0_M_AHB_CLK] = &se_gcc_qupv3_wrap0_m_ahb_clk.clkr,
+ [SE_GCC_QUPV3_WRAP0_S0_CLK] = &se_gcc_qupv3_wrap0_s0_clk.clkr,
+ [SE_GCC_QUPV3_WRAP0_S0_CLK_SRC] = &se_gcc_qupv3_wrap0_s0_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP0_S1_CLK] = &se_gcc_qupv3_wrap0_s1_clk.clkr,
+ [SE_GCC_QUPV3_WRAP0_S1_CLK_SRC] = &se_gcc_qupv3_wrap0_s1_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP0_S2_CLK] = &se_gcc_qupv3_wrap0_s2_clk.clkr,
+ [SE_GCC_QUPV3_WRAP0_S2_CLK_SRC] = &se_gcc_qupv3_wrap0_s2_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP0_S3_CLK] = &se_gcc_qupv3_wrap0_s3_clk.clkr,
+ [SE_GCC_QUPV3_WRAP0_S3_CLK_SRC] = &se_gcc_qupv3_wrap0_s3_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP0_S4_CLK] = &se_gcc_qupv3_wrap0_s4_clk.clkr,
+ [SE_GCC_QUPV3_WRAP0_S4_CLK_SRC] = &se_gcc_qupv3_wrap0_s4_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP0_S5_CLK] = &se_gcc_qupv3_wrap0_s5_clk.clkr,
+ [SE_GCC_QUPV3_WRAP0_S5_CLK_SRC] = &se_gcc_qupv3_wrap0_s5_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP0_S6_CLK] = &se_gcc_qupv3_wrap0_s6_clk.clkr,
+ [SE_GCC_QUPV3_WRAP0_S6_CLK_SRC] = &se_gcc_qupv3_wrap0_s6_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP0_S_AHB_CLK] = &se_gcc_qupv3_wrap0_s_ahb_clk.clkr,
+ [SE_GCC_QUPV3_WRAP1_CORE_2X_CLK] = &se_gcc_qupv3_wrap1_core_2x_clk.clkr,
+ [SE_GCC_QUPV3_WRAP1_CORE_CLK] = &se_gcc_qupv3_wrap1_core_clk.clkr,
+ [SE_GCC_QUPV3_WRAP1_M_AHB_CLK] = &se_gcc_qupv3_wrap1_m_ahb_clk.clkr,
+ [SE_GCC_QUPV3_WRAP1_S0_CLK] = &se_gcc_qupv3_wrap1_s0_clk.clkr,
+ [SE_GCC_QUPV3_WRAP1_S0_CLK_SRC] = &se_gcc_qupv3_wrap1_s0_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP1_S1_CLK] = &se_gcc_qupv3_wrap1_s1_clk.clkr,
+ [SE_GCC_QUPV3_WRAP1_S1_CLK_SRC] = &se_gcc_qupv3_wrap1_s1_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP1_S2_CLK] = &se_gcc_qupv3_wrap1_s2_clk.clkr,
+ [SE_GCC_QUPV3_WRAP1_S2_CLK_SRC] = &se_gcc_qupv3_wrap1_s2_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP1_S3_CLK] = &se_gcc_qupv3_wrap1_s3_clk.clkr,
+ [SE_GCC_QUPV3_WRAP1_S3_CLK_SRC] = &se_gcc_qupv3_wrap1_s3_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP1_S4_CLK] = &se_gcc_qupv3_wrap1_s4_clk.clkr,
+ [SE_GCC_QUPV3_WRAP1_S4_CLK_SRC] = &se_gcc_qupv3_wrap1_s4_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP1_S5_CLK] = &se_gcc_qupv3_wrap1_s5_clk.clkr,
+ [SE_GCC_QUPV3_WRAP1_S5_CLK_SRC] = &se_gcc_qupv3_wrap1_s5_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP1_S6_CLK] = &se_gcc_qupv3_wrap1_s6_clk.clkr,
+ [SE_GCC_QUPV3_WRAP1_S6_CLK_SRC] = &se_gcc_qupv3_wrap1_s6_clk_src.clkr,
+ [SE_GCC_QUPV3_WRAP1_S_AHB_CLK] = &se_gcc_qupv3_wrap1_s_ahb_clk.clkr,
+};
+
+static struct gdsc *se_gcc_nord_gdscs[] = {
+ [SE_GCC_EMAC0_GDSC] = &se_gcc_emac0_gdsc,
+ [SE_GCC_EMAC1_GDSC] = &se_gcc_emac1_gdsc,
+};
+
+static const struct qcom_reset_map se_gcc_nord_resets[] = {
+ [SE_GCC_EMAC0_BCR] = { 0x24000 },
+ [SE_GCC_EMAC1_BCR] = { 0x25000 },
+ [SE_GCC_QUPV3_WRAPPER_0_BCR] = { 0x26000 },
+ [SE_GCC_QUPV3_WRAPPER_1_BCR] = { 0x27000 },
+};
+
+static const struct clk_rcg_dfs_data se_gcc_nord_dfs_clocks[] = {
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s0_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s1_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s2_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s3_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s4_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s5_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s6_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s0_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s1_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s2_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s3_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s4_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s5_clk_src),
+ DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s6_clk_src),
+};
+
+static const struct regmap_config se_gcc_nord_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xf41f0,
+ .fast_io = true,
+};
+
+static struct qcom_cc_driver_data se_gcc_nord_driver_data = {
+ .dfs_rcgs = se_gcc_nord_dfs_clocks,
+ .num_dfs_rcgs = ARRAY_SIZE(se_gcc_nord_dfs_clocks),
+};
+
+static const struct qcom_cc_desc se_gcc_nord_desc = {
+ .config = &se_gcc_nord_regmap_config,
+ .clks = se_gcc_nord_clocks,
+ .num_clks = ARRAY_SIZE(se_gcc_nord_clocks),
+ .resets = se_gcc_nord_resets,
+ .num_resets = ARRAY_SIZE(se_gcc_nord_resets),
+ .gdscs = se_gcc_nord_gdscs,
+ .num_gdscs = ARRAY_SIZE(se_gcc_nord_gdscs),
+ .driver_data = &se_gcc_nord_driver_data,
+};
+
+static const struct of_device_id se_gcc_nord_match_table[] = {
+ { .compatible = "qcom,nord-segcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, se_gcc_nord_match_table);
+
+static int se_gcc_nord_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &se_gcc_nord_desc);
+}
+
+static struct platform_driver se_gcc_nord_driver = {
+ .probe = se_gcc_nord_probe,
+ .driver = {
+ .name = "segcc-nord",
+ .of_match_table = se_gcc_nord_match_table,
+ },
+};
+
+module_platform_driver(se_gcc_nord_driver);
+
+MODULE_DESCRIPTION("QTI SEGCC NORD Driver");
+MODULE_LICENSE("GPL");
--
2.47.3
^ permalink raw reply related
* [PATCH 7/7] arm64: defconfig: enable clock controller drivers for Qualcomm Nord
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
Enable the clock controller drivers for Nord platform from Qualcomm.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 163b7f0314c90fc45eb6c4aa5e8faa549c60fdf7..f1a3333bb07482ef4f8b4ea9154b0f2c74587a04 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1483,6 +1483,8 @@ CONFIG_CLK_KAANAPALI_GCC=y
CONFIG_CLK_KAANAPALI_GPUCC=m
CONFIG_CLK_KAANAPALI_TCSRCC=m
CONFIG_CLK_KAANAPALI_VIDEOCC=m
+CONFIG_CLK_NORD_GCC=y
+CONFIG_CLK_NORD_TCSRCC=y
CONFIG_CLK_X1E80100_CAMCC=m
CONFIG_CLK_X1E80100_DISPCC=m
CONFIG_CLK_X1E80100_GCC=y
--
2.47.3
^ permalink raw reply related
* [PATCH 5/7] clk: qcom: rpmh: Add support for Nord rpmh clocks
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski, Prasanna Tolety
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
From: Prasanna Tolety <quic_ptolety@quicinc.com>
Add RPMH clock support for the Nord SoC to allow enable/disable of the
clocks.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
drivers/clk/qcom/clk-rpmh.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 6a54481cc6ae175b8238117eefb4f38af0ec40a4..0c423a72662ede52a3ec93679859ae5697a9d7c4 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -349,6 +349,10 @@ DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2);
DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a1, "lnbclka1", 1);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a1, "lnbclka2", 1);
+DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a1, "lnbclka3", 1);
+
DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2);
@@ -965,6 +969,21 @@ static const struct clk_rpmh_desc clk_rpmh_eliza = {
.num_clks = ARRAY_SIZE(eliza_rpmh_clocks),
};
+static struct clk_hw *nord_rpmh_clocks[] = {
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a1.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a1_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a1.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a1_ao.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_nord = {
+ .clks = nord_rpmh_clocks,
+ .num_clks = ARRAY_SIZE(nord_rpmh_clocks),
+};
+
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@@ -1054,6 +1073,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
}
static const struct of_device_id clk_rpmh_match_table[] = {
+ { .compatible = "qcom,nord-rpmh-clk", .data = &clk_rpmh_nord},
{ .compatible = "qcom,eliza-rpmh-clk", .data = &clk_rpmh_eliza},
{ .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
{ .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
--
2.47.3
^ permalink raw reply related
* [PATCH 4/7] clk: qcom: Add TCSR clock driver for Nord SoC
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
From: Taniya Das <taniya.das@oss.qualcomm.com>
Add a clock driver for the TCSR clock controller found on Nord SoC,
which provides refclks for PCIE, USB, SGMII, UFS subsystems.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
[Shawn:
- Use compatible qcom,nord-tcsrcc
- Drop include of <linux/of.h> as the driver doesn't use any OF APIs]
Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/tcsrcc-nord.c | 337 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 345 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8f55f10261ec2dd4add61101c5619cc4516f7d66..10c74db7e072f560f4bc26f81b4378034d1f9bf6 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -674,6 +674,13 @@ config QCS_GCC_404
Say Y if you want to use multimedia devices or peripheral
devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
+config CLK_NORD_TCSRCC
+ tristate "Nord TCSR Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ help
+ Support for the TCSR clock controller on Nord devices.
+ Say Y if you want to use peripheral devices such as PCIe, USB, UFS etc.
+
config SA_CAMCC_8775P
tristate "SA8775P Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 103d6c4b860ccbc6b4ad552e9e6af43298a4474d..1a7ff1986b834f48dbaa2fd8c2559f0046ea7579 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o
+obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o
obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
diff --git a/drivers/clk/qcom/tcsrcc-nord.c b/drivers/clk/qcom/tcsrcc-nord.c
new file mode 100644
index 0000000000000000000000000000000000000000..ed0f4909158f6e7e073e111549a8740f6a7fc94c
--- /dev/null
+++ b/drivers/clk/qcom/tcsrcc-nord.c
@@ -0,0 +1,337 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,nord-tcsrcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "reset.h"
+
+enum {
+ DT_BI_TCXO_PAD,
+};
+
+static struct clk_branch tcsr_dp_rx_0_clkref_en = {
+ .halt_reg = 0xa008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xa008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_rx_0_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_dp_rx_1_clkref_en = {
+ .halt_reg = 0xb008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xb008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_rx_1_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_dp_tx_0_clkref_en = {
+ .halt_reg = 0xc008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xc008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_tx_0_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_dp_tx_1_clkref_en = {
+ .halt_reg = 0xd008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xd008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_tx_1_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_dp_tx_2_clkref_en = {
+ .halt_reg = 0xe008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xe008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_tx_2_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_dp_tx_3_clkref_en = {
+ .halt_reg = 0xf008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xf008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_dp_tx_3_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_pcie_clkref_en = {
+ .halt_reg = 0x8,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_pcie_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_ufs_clkref_en = {
+ .halt_reg = 0x3008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x3008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_ufs_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb2_0_clkref_en = {
+ .halt_reg = 0x4008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x4008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb2_0_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb2_1_clkref_en = {
+ .halt_reg = 0x5008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb2_1_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb2_2_clkref_en = {
+ .halt_reg = 0x6008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x6008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb2_2_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb3_0_clkref_en = {
+ .halt_reg = 0x8008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x8008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb3_0_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb3_1_clkref_en = {
+ .halt_reg = 0x7008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x7008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb3_1_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_ux_sgmii_0_clkref_en = {
+ .halt_reg = 0x1008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_ux_sgmii_0_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_ux_sgmii_1_clkref_en = {
+ .halt_reg = 0x2008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_ux_sgmii_1_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *tcsr_cc_nord_clocks[] = {
+ [TCSR_DP_RX_0_CLKREF_EN] = &tcsr_dp_rx_0_clkref_en.clkr,
+ [TCSR_DP_RX_1_CLKREF_EN] = &tcsr_dp_rx_1_clkref_en.clkr,
+ [TCSR_DP_TX_0_CLKREF_EN] = &tcsr_dp_tx_0_clkref_en.clkr,
+ [TCSR_DP_TX_1_CLKREF_EN] = &tcsr_dp_tx_1_clkref_en.clkr,
+ [TCSR_DP_TX_2_CLKREF_EN] = &tcsr_dp_tx_2_clkref_en.clkr,
+ [TCSR_DP_TX_3_CLKREF_EN] = &tcsr_dp_tx_3_clkref_en.clkr,
+ [TCSR_PCIE_CLKREF_EN] = &tcsr_pcie_clkref_en.clkr,
+ [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
+ [TCSR_USB2_0_CLKREF_EN] = &tcsr_usb2_0_clkref_en.clkr,
+ [TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr,
+ [TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr,
+ [TCSR_USB3_0_CLKREF_EN] = &tcsr_usb3_0_clkref_en.clkr,
+ [TCSR_USB3_1_CLKREF_EN] = &tcsr_usb3_1_clkref_en.clkr,
+ [TCSR_UX_SGMII_0_CLKREF_EN] = &tcsr_ux_sgmii_0_clkref_en.clkr,
+ [TCSR_UX_SGMII_1_CLKREF_EN] = &tcsr_ux_sgmii_1_clkref_en.clkr,
+};
+
+static const struct regmap_config tcsr_cc_nord_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xf008,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc tcsr_cc_nord_desc = {
+ .config = &tcsr_cc_nord_regmap_config,
+ .clks = tcsr_cc_nord_clocks,
+ .num_clks = ARRAY_SIZE(tcsr_cc_nord_clocks),
+};
+
+static const struct of_device_id tcsr_cc_nord_match_table[] = {
+ { .compatible = "qcom,nord-tcsrcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, tcsr_cc_nord_match_table);
+
+static int tcsr_cc_nord_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &tcsr_cc_nord_desc);
+}
+
+static struct platform_driver tcsr_cc_nord_driver = {
+ .probe = tcsr_cc_nord_probe,
+ .driver = {
+ .name = "tcsrcc-nord",
+ .of_match_table = tcsr_cc_nord_match_table,
+ },
+};
+
+module_platform_driver(tcsr_cc_nord_driver);
+
+MODULE_DESCRIPTION("QTI TCSRCC NORD Driver");
+MODULE_LICENSE("GPL");
--
2.47.3
^ permalink raw reply related
* [PATCH 3/7] dt-bindings: clock: qcom: Add Nord Global Clock Controller
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
From: Taniya Das <taniya.das@oss.qualcomm.com>
Add device tree bindings for the global clock controller on Qualcomm
Nord platform. The global clock controller on Nord SoC is divided into
multiple clock controllers (GCC,SE_GCC,NE_GCC and NW_GCC). Add each of
the bindings to define the clock controllers.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
.../devicetree/bindings/clock/qcom,nord-gcc.yaml | 58 ++++++++
.../devicetree/bindings/clock/qcom,nord-negcc.yaml | 60 +++++++++
.../devicetree/bindings/clock/qcom,nord-nwgcc.yaml | 55 ++++++++
include/dt-bindings/clock/qcom,nord-gcc.h | 147 +++++++++++++++++++++
include/dt-bindings/clock/qcom,nord-negcc.h | 124 +++++++++++++++++
include/dt-bindings/clock/qcom,nord-nwgcc.h | 69 ++++++++++
include/dt-bindings/clock/qcom,nord-segcc.h | 98 ++++++++++++++
7 files changed, 611 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..e35136722a931ef76f80d36ad2bc07fe618490d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on Nord SoC.
+
+ See also: include/dt-bindings/clock/qcom,nord-gcc.h
+
+properties:
+ compatible:
+ const: qcom,nord-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: PCIE A Pipe clock source
+ - description: PCIE B Pipe clock source
+ - description: PCIE C Pipe clock source
+ - description: PCIE D Pipe clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,nord-gcc";
+ reg = <0x00100000 0x1f4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&pcie_a_pipe_clk>,
+ <&pcie_b_pipe_clk>,
+ <&pcie_c_pipe_clk>,
+ <&pcie_d_pipe_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml b/Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..749389f65ee14999b3a195256e34f486e9aace1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-negcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global North East Clock & Reset Controller on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control (NE) module provides the clocks, resets
+ and power domains on Nord SoC.
+
+ See also: include/dt-bindings/clock/qcom,nord-negcc.h
+
+properties:
+ compatible:
+ const: qcom,nord-negcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: UFS Phy Rx symbol 0 clock source
+ - description: UFS Phy Rx symbol 1 clock source
+ - description: UFS Phy Tx symbol 0 clock source
+ - description: USB3 Phy sec wrapper pipe clock source
+ - description: USB3 Phy wrapper pipe clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@8900000 {
+ compatible = "qcom,nord-negcc";
+ reg = <0x08900000 0xf4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&ufs_phy_rx_symbol_0_clk>,
+ <&ufs_phy_rx_symbol_1_clk>,
+ <&ufs_phy_tx_symbol_0_clk>,
+ <&usb3_phy_sec_pipe_clk>,
+ <&usb3_phy_pipe_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml b/Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..ce33f966bdfdf0b0ccebc40944e3d961c79c6fe0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global North West and South East Clock & Reset Controller
+ on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control (NW, SE) module provides the clocks, resets
+ and power domains on Nord SoC.
+
+ See also:
+ include/dt-bindings/clock/qcom,nord-nwgcc.h
+ include/dt-bindings/clock/qcom,nord-segcc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,nord-nwgcc
+ - qcom,nord-segcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@8b00000 {
+ compatible = "qcom,nord-nwgcc";
+ reg = <0x08b00000 0xf4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/include/dt-bindings/clock/qcom,nord-gcc.h b/include/dt-bindings/clock/qcom,nord-gcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..8fbde162c8598d75b42136350fb23b33c29c339f
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-gcc.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
+
+/* GCC clocks */
+#define GCC_BOOT_ROM_AHB_CLK 0
+#define GCC_GP1_CLK 1
+#define GCC_GP1_CLK_SRC 2
+#define GCC_GP2_CLK 3
+#define GCC_GP2_CLK_SRC 4
+#define GCC_GPLL0 5
+#define GCC_GPLL0_OUT_EVEN 6
+#define GCC_MMU_0_TCU_VOTE_CLK 7
+#define GCC_PCIE_A_AUX_CLK 8
+#define GCC_PCIE_A_AUX_CLK_SRC 9
+#define GCC_PCIE_A_CFG_AHB_CLK 10
+#define GCC_PCIE_A_DTI_QTC_CLK 11
+#define GCC_PCIE_A_MSTR_AXI_CLK 12
+#define GCC_PCIE_A_PHY_AUX_CLK 13
+#define GCC_PCIE_A_PHY_AUX_CLK_SRC 14
+#define GCC_PCIE_A_PHY_RCHNG_CLK 15
+#define GCC_PCIE_A_PHY_RCHNG_CLK_SRC 16
+#define GCC_PCIE_A_PIPE_CLK 17
+#define GCC_PCIE_A_PIPE_CLK_SRC 18
+#define GCC_PCIE_A_SLV_AXI_CLK 19
+#define GCC_PCIE_A_SLV_Q2A_AXI_CLK 20
+#define GCC_PCIE_B_AUX_CLK 21
+#define GCC_PCIE_B_AUX_CLK_SRC 22
+#define GCC_PCIE_B_CFG_AHB_CLK 23
+#define GCC_PCIE_B_DTI_QTC_CLK 24
+#define GCC_PCIE_B_MSTR_AXI_CLK 25
+#define GCC_PCIE_B_PHY_AUX_CLK 26
+#define GCC_PCIE_B_PHY_AUX_CLK_SRC 27
+#define GCC_PCIE_B_PHY_RCHNG_CLK 28
+#define GCC_PCIE_B_PHY_RCHNG_CLK_SRC 29
+#define GCC_PCIE_B_PIPE_CLK 30
+#define GCC_PCIE_B_PIPE_CLK_SRC 31
+#define GCC_PCIE_B_SLV_AXI_CLK 32
+#define GCC_PCIE_B_SLV_Q2A_AXI_CLK 33
+#define GCC_PCIE_C_AUX_CLK 34
+#define GCC_PCIE_C_AUX_CLK_SRC 35
+#define GCC_PCIE_C_CFG_AHB_CLK 36
+#define GCC_PCIE_C_DTI_QTC_CLK 37
+#define GCC_PCIE_C_MSTR_AXI_CLK 38
+#define GCC_PCIE_C_PHY_AUX_CLK 39
+#define GCC_PCIE_C_PHY_AUX_CLK_SRC 40
+#define GCC_PCIE_C_PHY_RCHNG_CLK 41
+#define GCC_PCIE_C_PHY_RCHNG_CLK_SRC 42
+#define GCC_PCIE_C_PIPE_CLK 43
+#define GCC_PCIE_C_PIPE_CLK_SRC 44
+#define GCC_PCIE_C_SLV_AXI_CLK 45
+#define GCC_PCIE_C_SLV_Q2A_AXI_CLK 46
+#define GCC_PCIE_D_AUX_CLK 47
+#define GCC_PCIE_D_AUX_CLK_SRC 48
+#define GCC_PCIE_D_CFG_AHB_CLK 49
+#define GCC_PCIE_D_DTI_QTC_CLK 50
+#define GCC_PCIE_D_MSTR_AXI_CLK 51
+#define GCC_PCIE_D_PHY_AUX_CLK 52
+#define GCC_PCIE_D_PHY_AUX_CLK_SRC 53
+#define GCC_PCIE_D_PHY_RCHNG_CLK 54
+#define GCC_PCIE_D_PHY_RCHNG_CLK_SRC 55
+#define GCC_PCIE_D_PIPE_CLK 56
+#define GCC_PCIE_D_PIPE_CLK_SRC 57
+#define GCC_PCIE_D_SLV_AXI_CLK 58
+#define GCC_PCIE_D_SLV_Q2A_AXI_CLK 59
+#define GCC_PCIE_LINK_AHB_CLK 60
+#define GCC_PCIE_LINK_XO_CLK 61
+#define GCC_PCIE_NOC_ASYNC_BRIDGE_CLK 62
+#define GCC_PCIE_NOC_CNOC_SF_QX_CLK 63
+#define GCC_PCIE_NOC_M_CFG_CLK 64
+#define GCC_PCIE_NOC_M_PDB_CLK 65
+#define GCC_PCIE_NOC_MSTR_AXI_CLK 66
+#define GCC_PCIE_NOC_PWRCTL_CLK 67
+#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 68
+#define GCC_PCIE_NOC_REFGEN_CLK 69
+#define GCC_PCIE_NOC_REFGEN_CLK_SRC 70
+#define GCC_PCIE_NOC_S_CFG_CLK 71
+#define GCC_PCIE_NOC_S_PDB_CLK 72
+#define GCC_PCIE_NOC_SAFETY_CLK 73
+#define GCC_PCIE_NOC_SAFETY_CLK_SRC 74
+#define GCC_PCIE_NOC_SLAVE_AXI_CLK 75
+#define GCC_PCIE_NOC_TSCTR_CLK 76
+#define GCC_PCIE_NOC_XO_CLK 77
+#define GCC_PDM2_CLK 78
+#define GCC_PDM2_CLK_SRC 79
+#define GCC_PDM_AHB_CLK 80
+#define GCC_PDM_XO4_CLK 81
+#define GCC_QUPV3_WRAP3_CORE_2X_CLK 82
+#define GCC_QUPV3_WRAP3_CORE_CLK 83
+#define GCC_QUPV3_WRAP3_M_CLK 84
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 85
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 86
+#define GCC_QUPV3_WRAP3_S0_CLK 87
+#define GCC_QUPV3_WRAP3_S0_CLK_SRC 88
+#define GCC_QUPV3_WRAP3_S_AHB_CLK 89
+#define GCC_SMMU_PCIE_QTC_VOTE_CLK 90
+
+/* GCC power domains */
+#define GCC_PCIE_A_GDSC 0
+#define GCC_PCIE_A_PHY_GDSC 1
+#define GCC_PCIE_B_GDSC 2
+#define GCC_PCIE_B_PHY_GDSC 3
+#define GCC_PCIE_C_GDSC 4
+#define GCC_PCIE_C_PHY_GDSC 5
+#define GCC_PCIE_D_GDSC 6
+#define GCC_PCIE_D_PHY_GDSC 7
+#define GCC_PCIE_NOC_GDSC 8
+
+/* GCC resets */
+#define GCC_PCIE_A_BCR 0
+#define GCC_PCIE_A_LINK_DOWN_BCR 1
+#define GCC_PCIE_A_NOCSR_COM_PHY_BCR 2
+#define GCC_PCIE_A_PHY_BCR 3
+#define GCC_PCIE_A_PHY_CFG_AHB_BCR 4
+#define GCC_PCIE_A_PHY_COM_BCR 5
+#define GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR 6
+#define GCC_PCIE_B_BCR 7
+#define GCC_PCIE_B_LINK_DOWN_BCR 8
+#define GCC_PCIE_B_NOCSR_COM_PHY_BCR 9
+#define GCC_PCIE_B_PHY_BCR 10
+#define GCC_PCIE_B_PHY_CFG_AHB_BCR 11
+#define GCC_PCIE_B_PHY_COM_BCR 12
+#define GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR 13
+#define GCC_PCIE_C_BCR 14
+#define GCC_PCIE_C_LINK_DOWN_BCR 15
+#define GCC_PCIE_C_NOCSR_COM_PHY_BCR 16
+#define GCC_PCIE_C_PHY_BCR 17
+#define GCC_PCIE_C_PHY_CFG_AHB_BCR 18
+#define GCC_PCIE_C_PHY_COM_BCR 19
+#define GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR 20
+#define GCC_PCIE_D_BCR 21
+#define GCC_PCIE_D_LINK_DOWN_BCR 22
+#define GCC_PCIE_D_NOCSR_COM_PHY_BCR 23
+#define GCC_PCIE_D_PHY_BCR 24
+#define GCC_PCIE_D_PHY_CFG_AHB_BCR 25
+#define GCC_PCIE_D_PHY_COM_BCR 26
+#define GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR 27
+#define GCC_PCIE_NOC_BCR 28
+#define GCC_PDM_BCR 29
+#define GCC_QUPV3_WRAPPER_3_BCR 30
+#define GCC_TCSR_PCIE_BCR 31
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-negcc.h b/include/dt-bindings/clock/qcom,nord-negcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..95f333d8e1aa7cf1e386b6926380b2c853f7cf43
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-negcc.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H
+
+/* NE_GCC clocks */
+#define NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK 0
+#define NE_GCC_AGGRE_NOC_USB2_AXI_CLK 1
+#define NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK 2
+#define NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK 3
+#define NE_GCC_AHB2PHY_CLK 4
+#define NE_GCC_CNOC_USB2_AXI_CLK 5
+#define NE_GCC_CNOC_USB3_PRIM_AXI_CLK 6
+#define NE_GCC_CNOC_USB3_SEC_AXI_CLK 7
+#define NE_GCC_FRQ_MEASURE_REF_CLK 8
+#define NE_GCC_GP1_CLK 9
+#define NE_GCC_GP1_CLK_SRC 10
+#define NE_GCC_GP2_CLK 11
+#define NE_GCC_GP2_CLK_SRC 12
+#define NE_GCC_GPLL0 13
+#define NE_GCC_GPLL0_OUT_EVEN 14
+#define NE_GCC_GPLL2 15
+#define NE_GCC_GPU_2_CFG_CLK 16
+#define NE_GCC_GPU_2_GPLL0_CLK_SRC 17
+#define NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC 18
+#define NE_GCC_GPU_2_HSCNOC_GFX_CLK 19
+#define NE_GCC_GPU_2_SMMU_VOTE_CLK 20
+#define NE_GCC_QUPV3_WRAP2_CORE_2X_CLK 21
+#define NE_GCC_QUPV3_WRAP2_CORE_CLK 22
+#define NE_GCC_QUPV3_WRAP2_M_AHB_CLK 23
+#define NE_GCC_QUPV3_WRAP2_S0_CLK 24
+#define NE_GCC_QUPV3_WRAP2_S0_CLK_SRC 25
+#define NE_GCC_QUPV3_WRAP2_S1_CLK 26
+#define NE_GCC_QUPV3_WRAP2_S1_CLK_SRC 27
+#define NE_GCC_QUPV3_WRAP2_S2_CLK 28
+#define NE_GCC_QUPV3_WRAP2_S2_CLK_SRC 29
+#define NE_GCC_QUPV3_WRAP2_S3_CLK 30
+#define NE_GCC_QUPV3_WRAP2_S3_CLK_SRC 31
+#define NE_GCC_QUPV3_WRAP2_S4_CLK 32
+#define NE_GCC_QUPV3_WRAP2_S4_CLK_SRC 33
+#define NE_GCC_QUPV3_WRAP2_S5_CLK 34
+#define NE_GCC_QUPV3_WRAP2_S5_CLK_SRC 35
+#define NE_GCC_QUPV3_WRAP2_S6_CLK 36
+#define NE_GCC_QUPV3_WRAP2_S6_CLK_SRC 37
+#define NE_GCC_QUPV3_WRAP2_S_AHB_CLK 38
+#define NE_GCC_SDCC4_APPS_CLK 39
+#define NE_GCC_SDCC4_APPS_CLK_SRC 40
+#define NE_GCC_SDCC4_AXI_CLK 41
+#define NE_GCC_UFS_PHY_AHB_CLK 42
+#define NE_GCC_UFS_PHY_AXI_CLK 43
+#define NE_GCC_UFS_PHY_AXI_CLK_SRC 44
+#define NE_GCC_UFS_PHY_ICE_CORE_CLK 45
+#define NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC 46
+#define NE_GCC_UFS_PHY_PHY_AUX_CLK 47
+#define NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC 48
+#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK 49
+#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 50
+#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK 51
+#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 52
+#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK 53
+#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 54
+#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK 55
+#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 56
+#define NE_GCC_USB20_MASTER_CLK 57
+#define NE_GCC_USB20_MASTER_CLK_SRC 58
+#define NE_GCC_USB20_MOCK_UTMI_CLK 59
+#define NE_GCC_USB20_MOCK_UTMI_CLK_SRC 60
+#define NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 61
+#define NE_GCC_USB20_SLEEP_CLK 62
+#define NE_GCC_USB31_PRIM_ATB_CLK 63
+#define NE_GCC_USB31_PRIM_EUD_AHB_CLK 64
+#define NE_GCC_USB31_PRIM_MASTER_CLK 65
+#define NE_GCC_USB31_PRIM_MASTER_CLK_SRC 66
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK 67
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC 68
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 69
+#define NE_GCC_USB31_PRIM_SLEEP_CLK 70
+#define NE_GCC_USB31_SEC_ATB_CLK 71
+#define NE_GCC_USB31_SEC_EUD_AHB_CLK 72
+#define NE_GCC_USB31_SEC_MASTER_CLK 73
+#define NE_GCC_USB31_SEC_MASTER_CLK_SRC 74
+#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK 75
+#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC 76
+#define NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 77
+#define NE_GCC_USB31_SEC_SLEEP_CLK 78
+#define NE_GCC_USB3_PRIM_PHY_AUX_CLK 79
+#define NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC 80
+#define NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK 81
+#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK 82
+#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 83
+#define NE_GCC_USB3_SEC_PHY_AUX_CLK 84
+#define NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC 85
+#define NE_GCC_USB3_SEC_PHY_COM_AUX_CLK 86
+#define NE_GCC_USB3_SEC_PHY_PIPE_CLK 87
+#define NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC 88
+
+/* NE_GCC power domains */
+#define NE_GCC_UFS_MEM_PHY_GDSC 0
+#define NE_GCC_UFS_PHY_GDSC 1
+#define NE_GCC_USB20_PRIM_GDSC 2
+#define NE_GCC_USB31_PRIM_GDSC 3
+#define NE_GCC_USB31_SEC_GDSC 4
+#define NE_GCC_USB3_PHY_GDSC 5
+#define NE_GCC_USB3_SEC_PHY_GDSC 6
+
+/* NE_GCC resets */
+#define NE_GCC_GPU_2_BCR 0
+#define NE_GCC_QUPV3_WRAPPER_2_BCR 1
+#define NE_GCC_SDCC4_BCR 2
+#define NE_GCC_UFS_PHY_BCR 3
+#define NE_GCC_USB20_PRIM_BCR 4
+#define NE_GCC_USB31_PRIM_BCR 5
+#define NE_GCC_USB31_SEC_BCR 6
+#define NE_GCC_USB3_DP_PHY_PRIM_BCR 7
+#define NE_GCC_USB3_DP_PHY_SEC_BCR 8
+#define NE_GCC_USB3_PHY_PRIM_BCR 9
+#define NE_GCC_USB3_PHY_SEC_BCR 10
+#define NE_GCC_USB3PHY_PHY_PRIM_BCR 11
+#define NE_GCC_USB3PHY_PHY_SEC_BCR 12
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-nwgcc.h b/include/dt-bindings/clock/qcom,nord-nwgcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..b6253dd2aa85a3152f99447a60a6f8a3e85d8f3c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-nwgcc.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
+
+/* NW_GCC clocks */
+#define NW_GCC_ACMU_MUX_CLK 0
+#define NW_GCC_CAMERA_AHB_CLK 1
+#define NW_GCC_CAMERA_HF_AXI_CLK 2
+#define NW_GCC_CAMERA_SF_AXI_CLK 3
+#define NW_GCC_CAMERA_TRIG_CLK 4
+#define NW_GCC_CAMERA_XO_CLK 5
+#define NW_GCC_DISP_0_AHB_CLK 6
+#define NW_GCC_DISP_0_HF_AXI_CLK 7
+#define NW_GCC_DISP_0_TRIG_CLK 8
+#define NW_GCC_DISP_1_AHB_CLK 9
+#define NW_GCC_DISP_1_HF_AXI_CLK 10
+#define NW_GCC_DISP_1_TRIG_CLK 11
+#define NW_GCC_DPRX0_AXI_HF_CLK 12
+#define NW_GCC_DPRX0_CFG_AHB_CLK 13
+#define NW_GCC_DPRX1_AXI_HF_CLK 14
+#define NW_GCC_DPRX1_CFG_AHB_CLK 15
+#define NW_GCC_EVA_AHB_CLK 16
+#define NW_GCC_EVA_AXI0_CLK 17
+#define NW_GCC_EVA_AXI0C_CLK 18
+#define NW_GCC_EVA_TRIG_CLK 19
+#define NW_GCC_EVA_XO_CLK 20
+#define NW_GCC_FRQ_MEASURE_REF_CLK 21
+#define NW_GCC_GP1_CLK 22
+#define NW_GCC_GP1_CLK_SRC 23
+#define NW_GCC_GP2_CLK 24
+#define NW_GCC_GP2_CLK_SRC 25
+#define NW_GCC_GPLL0 26
+#define NW_GCC_GPLL0_OUT_EVEN 27
+#define NW_GCC_GPU_2_CFG_AHB_CLK 28
+#define NW_GCC_GPU_2_GPLL0_CLK_SRC 29
+#define NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC 30
+#define NW_GCC_GPU_2_HSCNOC_GFX_CLK 31
+#define NW_GCC_GPU_CFG_AHB_CLK 32
+#define NW_GCC_GPU_GPLL0_CLK_SRC 33
+#define NW_GCC_GPU_GPLL0_DIV_CLK_SRC 34
+#define NW_GCC_GPU_HSCNOC_GFX_CLK 35
+#define NW_GCC_GPU_SMMU_VOTE_CLK 36
+#define NW_GCC_HSCNOC_GPU_2_AXI_CLK 37
+#define NW_GCC_HSCNOC_GPU_AXI_CLK 38
+#define NW_GCC_MMU_1_TCU_VOTE_CLK 39
+#define NW_GCC_VIDEO_AHB_CLK 40
+#define NW_GCC_VIDEO_AXI0_CLK 41
+#define NW_GCC_VIDEO_AXI0C_CLK 42
+#define NW_GCC_VIDEO_AXI1_CLK 43
+#define NW_GCC_VIDEO_XO_CLK 44
+
+/* NW_GCC power domains */
+
+/* NW_GCC resets */
+#define NW_GCC_CAMERA_BCR 0
+#define NW_GCC_DISPLAY_0_BCR 1
+#define NW_GCC_DISPLAY_1_BCR 2
+#define NW_GCC_DPRX0_BCR 3
+#define NW_GCC_DPRX1_BCR 4
+#define NW_GCC_EVA_BCR 5
+#define NW_GCC_GPU_2_BCR 6
+#define NW_GCC_GPU_BCR 7
+#define NW_GCC_VIDEO_BCR 8
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-segcc.h b/include/dt-bindings/clock/qcom,nord-segcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..f0f7422af692d05417d126c1011a22faf3bdc611
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-segcc.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
+
+/* SE_GCC clocks */
+#define SE_GCC_EEE_EMAC0_CLK 0
+#define SE_GCC_EEE_EMAC0_CLK_SRC 1
+#define SE_GCC_EEE_EMAC1_CLK 2
+#define SE_GCC_EEE_EMAC1_CLK_SRC 3
+#define SE_GCC_EMAC0_AXI_CLK 4
+#define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5
+#define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6
+#define SE_GCC_EMAC0_PHY_AUX_CLK 7
+#define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8
+#define SE_GCC_EMAC0_PTP_CLK 9
+#define SE_GCC_EMAC0_PTP_CLK_SRC 10
+#define SE_GCC_EMAC0_RGMII_CLK 11
+#define SE_GCC_EMAC0_RGMII_CLK_SRC 12
+#define SE_GCC_EMAC0_RPCS_RX_CLK 13
+#define SE_GCC_EMAC0_RPCS_TX_CLK 14
+#define SE_GCC_EMAC0_XGXS_RX_CLK 15
+#define SE_GCC_EMAC0_XGXS_TX_CLK 16
+#define SE_GCC_EMAC1_AXI_CLK 17
+#define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18
+#define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19
+#define SE_GCC_EMAC1_PHY_AUX_CLK 20
+#define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21
+#define SE_GCC_EMAC1_PTP_CLK 22
+#define SE_GCC_EMAC1_PTP_CLK_SRC 23
+#define SE_GCC_EMAC1_RGMII_CLK 24
+#define SE_GCC_EMAC1_RGMII_CLK_SRC 25
+#define SE_GCC_EMAC1_RPCS_RX_CLK 26
+#define SE_GCC_EMAC1_RPCS_TX_CLK 27
+#define SE_GCC_EMAC1_XGXS_RX_CLK 28
+#define SE_GCC_EMAC1_XGXS_TX_CLK 29
+#define SE_GCC_FRQ_MEASURE_REF_CLK 30
+#define SE_GCC_GP1_CLK 31
+#define SE_GCC_GP1_CLK_SRC 32
+#define SE_GCC_GP2_CLK 33
+#define SE_GCC_GP2_CLK_SRC 34
+#define SE_GCC_GPLL0 35
+#define SE_GCC_GPLL0_OUT_EVEN 36
+#define SE_GCC_GPLL2 37
+#define SE_GCC_GPLL4 38
+#define SE_GCC_GPLL5 39
+#define SE_GCC_MMU_2_TCU_VOTE_CLK 40
+#define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41
+#define SE_GCC_QUPV3_WRAP0_CORE_CLK 42
+#define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43
+#define SE_GCC_QUPV3_WRAP0_S0_CLK 44
+#define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45
+#define SE_GCC_QUPV3_WRAP0_S1_CLK 46
+#define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47
+#define SE_GCC_QUPV3_WRAP0_S2_CLK 48
+#define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49
+#define SE_GCC_QUPV3_WRAP0_S3_CLK 50
+#define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51
+#define SE_GCC_QUPV3_WRAP0_S4_CLK 52
+#define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53
+#define SE_GCC_QUPV3_WRAP0_S5_CLK 54
+#define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55
+#define SE_GCC_QUPV3_WRAP0_S6_CLK 56
+#define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57
+#define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58
+#define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59
+#define SE_GCC_QUPV3_WRAP1_CORE_CLK 60
+#define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61
+#define SE_GCC_QUPV3_WRAP1_S0_CLK 62
+#define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC 63
+#define SE_GCC_QUPV3_WRAP1_S1_CLK 64
+#define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC 65
+#define SE_GCC_QUPV3_WRAP1_S2_CLK 66
+#define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC 67
+#define SE_GCC_QUPV3_WRAP1_S3_CLK 68
+#define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC 69
+#define SE_GCC_QUPV3_WRAP1_S4_CLK 70
+#define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC 71
+#define SE_GCC_QUPV3_WRAP1_S5_CLK 72
+#define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC 73
+#define SE_GCC_QUPV3_WRAP1_S6_CLK 74
+#define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC 75
+#define SE_GCC_QUPV3_WRAP1_S_AHB_CLK 76
+
+/* SE_GCC power domains */
+#define SE_GCC_EMAC0_GDSC 0
+#define SE_GCC_EMAC1_GDSC 1
+
+/* SE_GCC resets */
+#define SE_GCC_EMAC0_BCR 0
+#define SE_GCC_EMAC1_BCR 1
+#define SE_GCC_QUPV3_WRAPPER_0_BCR 2
+#define SE_GCC_QUPV3_WRAPPER_1_BCR 3
+
+#endif
--
2.47.3
^ permalink raw reply related
* [PATCH 2/7] dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
From: Taniya Das <taniya.das@oss.qualcomm.com>
Add bindings and update documentation compatible for RPMh clock
controller on Nord SoC.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
index 9690169baa4697bbd3ab9197f9661368a0827bf7..a2c404a579812dae073241ea71b63e55e798e80e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
@@ -21,6 +21,7 @@ properties:
- qcom,glymur-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,milos-rpmh-clk
+ - qcom,nord-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
- qcom,sa8775p-rpmh-clk
--
2.47.3
^ permalink raw reply related
* [PATCH 1/7] dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
From: Bartosz Golaszewski @ 2026-04-03 14:10 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Bartosz Golaszewski
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
From: Taniya Das <taniya.das@oss.qualcomm.com>
The Nord SoC TCSR block provides CLKREF clocks for DP, PCIe, UFS, SGMII
and USB.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
[Shawn: Use compatible qcom,nord-tcsrcc rather than qcom,nord-tcsr]
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
.../bindings/clock/qcom,sm8550-tcsr.yaml | 2 ++
include/dt-bindings/clock/qcom,nord-tcsrcc.h | 26 ++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
index ae9aef0e54e8b8b85bc70e6096d524447091f39e..1ccdf4b0f5dd390417821494cdb97d8f4ed26c58 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
@@ -17,6 +17,7 @@ description: |
See also:
- include/dt-bindings/clock/qcom,eliza-tcsr.h
- include/dt-bindings/clock/qcom,glymur-tcsr.h
+ - include/dt-bindings/clock/qcom,nord-tcsrcc.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
@@ -29,6 +30,7 @@ properties:
- qcom,glymur-tcsr
- qcom,kaanapali-tcsr
- qcom,milos-tcsr
+ - qcom,nord-tcsrcc
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
diff --git a/include/dt-bindings/clock/qcom,nord-tcsrcc.h b/include/dt-bindings/clock/qcom,nord-tcsrcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..3f0e2ff7acc72c10d00488c48ec17af8ea6de06e
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-tcsrcc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H
+
+/* TCSR_CC clocks */
+#define TCSR_DP_RX_0_CLKREF_EN 0
+#define TCSR_DP_RX_1_CLKREF_EN 1
+#define TCSR_DP_TX_0_CLKREF_EN 2
+#define TCSR_DP_TX_1_CLKREF_EN 3
+#define TCSR_DP_TX_2_CLKREF_EN 4
+#define TCSR_DP_TX_3_CLKREF_EN 5
+#define TCSR_PCIE_CLKREF_EN 6
+#define TCSR_UFS_CLKREF_EN 7
+#define TCSR_USB2_0_CLKREF_EN 8
+#define TCSR_USB2_1_CLKREF_EN 9
+#define TCSR_USB2_2_CLKREF_EN 10
+#define TCSR_USB3_0_CLKREF_EN 11
+#define TCSR_USB3_1_CLKREF_EN 12
+#define TCSR_UX_SGMII_0_CLKREF_EN 13
+#define TCSR_UX_SGMII_1_CLKREF_EN 14
+
+#endif
--
2.47.3
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