* RE: [PATCh v3 09/14] ASoC: rsnd: Add ADG reset support for RZ/G3E
From: John Madieu @ 2026-04-03 19:30 UTC (permalink / raw)
To: geert
Cc: Kuninori Morimoto, Mark Brown, Liam Girdwood, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
magnus.damm, Philipp Zabel, Claudiu.Beznea, Biju Das,
john.madieu@gmail.com, linux-sound@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <CAMuHMdUHzcq_f8t0hi-FjiG2FByNmx8k2sz9-QEqzroLSWqXNg@mail.gmail.com>
Hi Geert,
Thanks for the review.
> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Friday, April 3, 2026 9:37 AM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCh v3 09/14] ASoC: rsnd: Add ADG reset support for RZ/G3E
>
> Hi John,
>
> On Thu, 2 Apr 2026 at 18:53, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > RZ/G3E requires the ADG reset line to be deasserted for the audio
> > subsystem to operate. The ADG module clock is already managed via
> > rsnd_adg_clk_enable/disable() through adg->adg, so no additional clock
> > handling is needed.
> >
> > Add support for the optional "adg" reset control on Renesas RZ/G3E SoC.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/sound/soc/renesas/rcar/adg.c
> > +++ b/sound/soc/renesas/rcar/adg.c
> > @@ -771,6 +771,7 @@ void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv,
> > struct seq_file *m)
> >
> > int rsnd_adg_probe(struct rsnd_priv *priv) {
> > + struct reset_control *rstc;
> > struct rsnd_adg *adg;
> > struct device *dev = rsnd_priv_to_dev(priv);
> > int ret;
> > @@ -779,8 +780,13 @@ int rsnd_adg_probe(struct rsnd_priv *priv)
> > if (!adg)
> > return -ENOMEM;
> >
> > + rstc = devm_reset_control_get_optional_exclusive(dev, "adg");
> > + if (IS_ERR(rstc))
> > + return dev_err_probe(dev, PTR_ERR(rstc),
> > + "failed to get adg reset\n");
>
> Given this file already uses lines longer than 80 characters, the above
> statement would fit on a single line.
Agreed. I'll collapse both the dev_err_probe() and rsnd_mod_init()
calls to single lines.
Regards,
John.
>
> > +
> > ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
> > - NULL, NULL, 0, 0);
> > + NULL, rstc, 0, 0);
>
> This one fits for sure.
>
> > if (ret)
> > return ret;
> >
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 4/7] arm64: dts: qcom: milos: Split up uart11 pinctrl
From: Dmitry Baryshkov @ 2026-04-03 19:32 UTC (permalink / raw)
To: Luca Weiss
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Koskovich, Liam Girdwood, Mark Brown,
Bartosz Golaszewski, Marcel Holtmann, Luiz Augusto von Dentz,
Balakrishna Godavarthi, Rocky Liao, Johannes Berg, Jeff Johnson,
~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, devicetree, linux-bluetooth, linux-wireless, ath11k
In-Reply-To: <20260403-milos-fp6-bt-wifi-v2-4-393322b27c5f@fairphone.com>
On Fri, Apr 03, 2026 at 03:52:50PM +0200, Luca Weiss wrote:
> In order to set the pinctrl for the individual CTS, RTS, TX and RX pins,
> split up the pinctrl configuration into 4 nodes so that boards can set
> some properties separately.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> arch/arm64/boot/dts/qcom/milos.dtsi | 28 ++++++++++++++++++----------
> 1 file changed, 18 insertions(+), 10 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 5/7] arm64: dts: qcom: milos: Add WCN6755 WiFi node
From: Dmitry Baryshkov @ 2026-04-03 19:33 UTC (permalink / raw)
To: Luca Weiss
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Koskovich, Liam Girdwood, Mark Brown,
Bartosz Golaszewski, Marcel Holtmann, Luiz Augusto von Dentz,
Balakrishna Godavarthi, Rocky Liao, Johannes Berg, Jeff Johnson,
~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, devicetree, linux-bluetooth, linux-wireless, ath11k
In-Reply-To: <20260403-milos-fp6-bt-wifi-v2-5-393322b27c5f@fairphone.com>
On Fri, Apr 03, 2026 at 03:52:51PM +0200, Luca Weiss wrote:
> Add a node for the WCN6755 WiFi found with the Milos SoC.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> arch/arm64/boot/dts/qcom/milos.dtsi | 46 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 6/7] arm64: dts: qcom: milos-fairphone-fp6: Enable Bluetooth
From: Dmitry Baryshkov @ 2026-04-03 19:33 UTC (permalink / raw)
To: Luca Weiss
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Koskovich, Liam Girdwood, Mark Brown,
Bartosz Golaszewski, Marcel Holtmann, Luiz Augusto von Dentz,
Balakrishna Godavarthi, Rocky Liao, Johannes Berg, Jeff Johnson,
~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, devicetree, linux-bluetooth, linux-wireless, ath11k
In-Reply-To: <20260403-milos-fp6-bt-wifi-v2-6-393322b27c5f@fairphone.com>
On Fri, Apr 03, 2026 at 03:52:52PM +0200, Luca Weiss wrote:
> Add the nodes to describe the WCN6755 chip with its PMU and Bluetooth
> parts.
>
> Thanks to Alexander Koskovich for helping with the bringup, adding
> 'clocks' to the PMU node to make Bluetooth work.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 174 +++++++++++++++++++++++
> 1 file changed, 174 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 7/7] arm64: dts: qcom: milos-fairphone-fp6: Enable WiFi
From: Dmitry Baryshkov @ 2026-04-03 19:35 UTC (permalink / raw)
To: Luca Weiss
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Koskovich, Liam Girdwood, Mark Brown,
Bartosz Golaszewski, Marcel Holtmann, Luiz Augusto von Dentz,
Balakrishna Godavarthi, Rocky Liao, Johannes Berg, Jeff Johnson,
~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, devicetree, linux-bluetooth, linux-wireless, ath11k
In-Reply-To: <20260403-milos-fp6-bt-wifi-v2-7-393322b27c5f@fairphone.com>
On Fri, Apr 03, 2026 at 03:52:53PM +0200, Luca Weiss wrote:
> Configure and enable the WiFi node, and add the required pinctrl to
> provide the sleep clock from the PMK8550 (PMK7635) to WCN6755.
>
> Thanks to Alexander Koskovich for helping with the bringup, adding
> the missing pinctrl to make the WPSS stop crashing.
>
> Link: https://lore.kernel.org/linux-arm-msm/DBF7OWAWQ94M.FSCP4DPF8ZJY@fairphone.com/
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> index db72418b7195..d8ac495ca7c8 100644
> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> @@ -242,7 +242,7 @@ wcn6750-pmu {
>
> clocks = <&rpmhcc RPMH_RF_CLK1>;
>
> - pinctrl-0 = <&bluetooth_enable_default>;
> + pinctrl-0 = <&bluetooth_enable_default>, <&pmk8550_sleep_clk_default>;
> pinctrl-names = "default";
>
> regulators {
> @@ -766,6 +766,17 @@ &pmiv0104_eusb2_repeater {
> qcom,tune-usb2-preem = /bits/ 8 <0x6>;
> };
>
> +&pmk8550_gpios {
> + pmk8550_sleep_clk_default: sleep-clk-default-state {
> + pins = "gpio5";
> + function = "func1";
> + input-disable;
> + output-enable;
Hmm, if it's a sleep_clk, should it not be handled via the power
sequencer?
> + bias-disable;
> + power-source = <0>;
> + };
> +};
> +
> &pmr735b_gpios {
> s1j_enable_default: s1j-enable-default-state {
> pins = "gpio1";
> @@ -1049,3 +1060,9 @@ &usb_1_hsphy {
>
> status = "okay";
> };
> +
> +&wifi {
> + qcom,calibration-variant = "Fairphone_Gen_6";
> +
> + status = "okay";
> +};
>
> --
> 2.53.0
>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sc8280xp: Add ADSP FastRPC node
From: Dmitry Baryshkov @ 2026-04-03 19:49 UTC (permalink / raw)
To: Pengyu Luo
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260403120753.105869-1-mitltlatltl@gmail.com>
On Fri, Apr 03, 2026 at 08:07:52PM +0800, Pengyu Luo wrote:
> Add the FastRPC node to enable offloading compute tasks to the ADSP
> via the FastRPC framework.
>
> Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 27 ++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 2/3] pinctrl: qcom: add the TLMM driver for the Nord platforms
From: Dmitry Baryshkov @ 2026-04-03 19:57 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Richard Cochran, Bartosz Golaszewski, Shawn Guo,
Arnd Bergmann, linux-arm-msm, linux-gpio, devicetree,
linux-kernel
In-Reply-To: <20260403-nord-tlmm-v1-2-4864f400c700@oss.qualcomm.com>
On Fri, Apr 03, 2026 at 03:27:56PM +0200, Bartosz Golaszewski wrote:
> Add support for the TLMM controller on the Qualcomm Nord platform.
>
> Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> ---
> drivers/pinctrl/qcom/Kconfig.msm | 7 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-nord.c | 3297 +++++++++++++++++++++++++++++++++++
> 3 files changed, 3305 insertions(+)
>
I didn't perform a complete cross-check, but looks okay from my PoV.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 3/3] arm64: defconfig: enable the Qualcomm Nord TLMM driver
From: Dmitry Baryshkov @ 2026-04-03 19:57 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Richard Cochran, Bartosz Golaszewski, Shawn Guo,
Arnd Bergmann, linux-arm-msm, linux-gpio, devicetree,
linux-kernel
In-Reply-To: <20260403-nord-tlmm-v1-3-4864f400c700@oss.qualcomm.com>
On Fri, Apr 03, 2026 at 03:27:57PM +0200, Bartosz Golaszewski wrote:
> This is required to boot linux on the Nord platforms from Qualcomm.
No, we don't enable configs for 'platforms'. Please specify, which
device needs it.
>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 163b7f0314c90fc45eb6c4aa5e8faa549c60fdf7..31f8cd7cde6fcc8c8da8e69950dd4976ae04cfc4 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -675,6 +675,7 @@ CONFIG_PINCTRL_QDF2XXX=y
> CONFIG_PINCTRL_QDU1000=y
> CONFIG_PINCTRL_RP1=m
> CONFIG_PINCTRL_SA8775P=y
> +CONFIG_PINCTRL_NORD=y
> CONFIG_PINCTRL_SC7180=y
> CONFIG_PINCTRL_SC7280=y
> CONFIG_PINCTRL_SC8180X=y
>
> --
> 2.47.3
>
--
With best wishes
Dmitry
^ permalink raw reply
* RE: [PATCh v3 10/14] ASoC: rsnd: adg: Add per-SSI ADG and SSIF supply clock management
From: John Madieu @ 2026-04-03 20:00 UTC (permalink / raw)
To: Kuninori Morimoto
Cc: Mark Brown, Liam Girdwood, Geert Uytterhoeven, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
magnus.damm, Philipp Zabel, Claudiu.Beznea, Biju Das,
john.madieu@gmail.com, linux-sound@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <87ika8g74p.wl-kuninori.morimoto.gx@renesas.com>
Hi Kuninori,
Thanks for your review.
> -----Original Message-----
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Sent: Friday, April 3, 2026 3:33 AM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCh v3 10/14] ASoC: rsnd: adg: Add per-SSI ADG and SSIF
> supply clock management
>
>
> Hi John
>
> > RZ/G3E's ADG module requires explicit clock management for SSI audio
> > interfaces that differs from R-Car Gen2/Gen3/Gen4:
> >
> > - Per-SSI ADG clocks (adg.ssi.N) for each SSI module
> > - A shared SSIF supply clock for the SSI subsystem
> >
> > These clocks are acquired using optional APIs, making them transparent
> > to platforms that do not require them.
> >
> > Additionally, since rsnd_adg_ssi_clk_try_start() is called from the
> > trigger path (atomic context), clk_prepare_enable() cannot be used
> > directly as clk_prepare() may sleep. Split clock handling into:
> >
> > - hw_params: clk_prepare() - sleepable context
> > - trigger (start): clk_enable() - atomic safe
> > - trigger (stop): clk_disable() - atomic safe
> > - hw_free: clk_unprepare() - sleepable context
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> (snip)
> > +int rsnd_adg_ssi_clk_prepare(struct rsnd_mod *ssi_mod) {
> > + struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
> > + struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
> > + struct device *dev = rsnd_priv_to_dev(priv);
> > + int id = rsnd_mod_id(ssi_mod);
> > + int ret;
> > +
> > + ret = clk_prepare(adg->clk_adg_ssi[id]);
> > + if (ret) {
> > + dev_err(dev, "Cannot prepare adg.ssi.%d ADG clock\n", id);
> > + return ret;
> > + }
> > +
> > + ret = clk_prepare(adg->clk_ssif_supply);
> > + if (ret) {
> > + dev_err(dev, "Cannot prepare SSIF supply clock\n");
> > + clk_unprepare(adg->clk_adg_ssi[id]);
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * RZ/G3E: Unprepare SSI clocks - call from hw_free (can sleep) */
> > +void rsnd_adg_ssi_clk_unprepare(struct rsnd_mod *ssi_mod) {
> > + struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
> > + struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
> > + int id = rsnd_mod_id(ssi_mod);
> > +
> > + clk_unprepare(adg->clk_adg_ssi[id]);
> > + clk_unprepare(adg->clk_ssif_supply);
> > +}
>
> Can't we done clk_{un}prepare() at rsnd_adg_clk_control() ?
> It is the function that ADG is calling clk_{un}prepare().
> Performing similar processes in multiple locations makes maintenance
> difficult.
>
This solves both issues (raised by Mark) cleanly.
I'll move the clk_prepare/unprepared for the per-SSI ADG clocks
and SSIF supply clock into rsnd_adg_clk_control(), which already
manages other ADG clocks. Prepare happens once at probe (and resume),
unprepare at remove (and suspend), and the trigger path only needs
clk_enable/disable() which is atomic-safe.
This eliminates the hw_params prepare leak concern entirely.
Regards,
John
> Thank you for your help !!
>
> Best regards
> ---
> Kuninori Morimoto
^ permalink raw reply
* Re: [PATCH v2 2/3] clk: qcom: Add support for GXCLK for Milos
From: Dmitry Baryshkov @ 2026-04-03 20:02 UTC (permalink / raw)
To: Luca Weiss
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Alexander Koskovich, ~postmarketos/upstreaming, phone-devel,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
Jagadeesh Kona, Taniya Das
In-Reply-To: <20260403-milos-gxclkctl-v2-2-95eb94a7d0a4@fairphone.com>
On Fri, Apr 03, 2026 at 02:03:47PM +0200, Luca Weiss wrote:
> GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing
> clocks for the GPU subsystem on GX power domain. The GX clock controller
> driver manages only the GX GDSC and the rest of the resources of the
> controller are managed by the firmware.
>
> We can use the existing kaanapali driver for Milos as well since the
> GX_CLKCTL_GX_GDSC supported by the Linux driver requires the same
> configuration.
>
> Reviewed-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> drivers/clk/qcom/Makefile | 2 +-
> drivers/clk/qcom/gxclkctl-kaanapali.c | 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* RE: [PATCh v3 10/14] ASoC: rsnd: adg: Add per-SSI ADG and SSIF supply clock management
From: John Madieu @ 2026-04-03 20:02 UTC (permalink / raw)
To: Mark Brown
Cc: Kuninori Morimoto, Liam Girdwood, Geert Uytterhoeven, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
magnus.damm, Philipp Zabel, Claudiu.Beznea, Biju Das,
john.madieu@gmail.com, linux-sound@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <9182f54f-c413-4337-ad72-4a847dd58fa5@sirena.org.uk>
Hi Mark,
Thanks for your review.
> -----Original Message-----
> From: Mark Brown <broonie@kernel.org>
> Sent: Thursday, April 2, 2026 8:03 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCh v3 10/14] ASoC: rsnd: adg: Add per-SSI ADG and SSIF
> supply clock management
>
> On Thu, Apr 02, 2026 at 06:24:32PM +0200, John Madieu wrote:
>
> > @@ -376,6 +431,18 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod
> *ssi_mod, unsigned int rate)
> > (ckr) ? adg->brg_rate[ADG_HZ_48] :
> > adg->brg_rate[ADG_HZ_441]);
> >
> > + /*
> > + * RZ/G3E: enable per-SSI and supply clocks
> > + * Prepare was done in hw_params
> > + */
> > + ret = clk_enable(adg->clk_adg_ssi[id]);
> > + if (ret)
> > + dev_warn(dev, "Cannot enable adg.ssi.%d ADG clock\n", id);
> > +
> > + ret = clk_enable(adg->clk_ssif_supply);
> > + if (ret)
> > + dev_warn(dev, "Cannot enable SSIF supply clock\n");
> > +
>
> Should we not return an error if we can't start the clocks for some
> reason?
Agreed.
I'll return proper errors with cleanup on clk_enable() failure.
Regards,
John
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8750: Enable cpufreq cooling devices
From: Dmitry Baryshkov @ 2026-04-03 20:04 UTC (permalink / raw)
To: aastha.pandey
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260403-cpufreq-v1-1-9d465988c3f9@oss.qualcomm.com>
On Fri, Apr 03, 2026 at 05:26:33PM +0530, Aastha Pandey via B4 Relay wrote:
> From: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
>
> Add cooling-cells property to the CPU nodes to support cpufreq
> cooling devices.
>
> Signed-off-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* RE: [PATCh v3 10/14] ASoC: rsnd: adg: Add per-SSI ADG and SSIF supply clock management
From: John Madieu @ 2026-04-03 20:05 UTC (permalink / raw)
To: Mark Brown
Cc: Kuninori Morimoto, Liam Girdwood, Geert Uytterhoeven, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
magnus.damm, Philipp Zabel, Claudiu.Beznea, Biju Das,
john.madieu@gmail.com, linux-sound@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <812b7823-7891-4f99-a4e9-07f52849b1db@sirena.org.uk>
Hi Mark,
Thanks for the review.
> -----Original Message-----
> From: Mark Brown <broonie@kernel.org>
> Sent: Thursday, April 2, 2026 8:06 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCh v3 10/14] ASoC: rsnd: adg: Add per-SSI ADG and SSIF
> supply clock management
>
> On Thu, Apr 02, 2026 at 06:24:32PM +0200, John Madieu wrote:
>
> >
> > +/*
> > + * RZ/G3E: Prepare SSI clocks - call from hw_params (can sleep) */
> > +int rsnd_adg_ssi_clk_prepare(struct rsnd_mod *ssi_mod) {
>
> > + ret = clk_prepare(adg->clk_adg_ssi[id]);
>
> One other issue here: hw_params() can be called multiple times without
> starting a stream, this might lead to leaks of clk_prepare().
Thanks for letting me know. I'll address that when implementing what
Koninori has suggested. This should normally not be an issue anymore in
v4.
Regards,
John
^ permalink raw reply
* Re: [PATCH v2 2/3] arm64: dts: qcom: kaanpaali: Add USB support for MTP platform
From: Akhil P Oommen @ 2026-04-03 20:09 UTC (permalink / raw)
To: Krishna Kurapati
Cc: linux-arm-msm, devicetree, linux-kernel, Ronak Raheja,
Jingyi Wang, Konrad Dybcio, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <20260329175249.2946508-3-krishna.kurapati@oss.qualcomm.com>
On 3/29/2026 11:22 PM, Krishna Kurapati wrote:
> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>
> Enable USB support on Kaanapali MTP variant. Enable USB controller in
> device mode till glink node is added.
>
> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 27 ++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> index a603f3056d83..38269aebdf03 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> @@ -82,6 +82,11 @@ key-volume-up {
> };
> };
>
> + pmih0108_e1_eusb2_repeater {
> + vdd18-supply = <&vreg_l15b_1p8>;
> + vdd3-supply = <&vreg_l5b_3p1>;
> + };
> +
> sound {
> compatible = "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard";
> model = "Kaanapali-MTP";
> @@ -1326,3 +1331,25 @@ &ufs_mem_phy {
>
> status = "okay";
> };
> +
> +&usb {
> + dr_mode = "peripheral";
I can see that the usb port in the MTP support 'host' mode too. Should
this be 'otg'?
-Akhil
> +
> + status = "okay";
> +};
> +
> +&usb_hsphy {
> + vdd-supply = <&vreg_l4f_0p8>;
> + vdda12-supply = <&vreg_l1d_1p2>;
> +
> + phys = <&pmih0108_e1_eusb2_repeater>;
> +
> + status = "okay";
> +};
> +
> +&usb_dp_qmpphy {
> + vdda-phy-supply = <&vreg_l1d_1p2>;
> + vdda-pll-supply = <&vreg_l4f_0p8>;
> +
> + status = "okay";
> +};
^ permalink raw reply
* Re: [PATCH 0/2] Add USB Ethernet controller (LAN7500) node in VAR-SOM-OM44 devicetree
From: Jakub Kicinski @ 2026-04-03 20:18 UTC (permalink / raw)
To: Thomas Richard
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Paolo Abeni,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Thomas Petazzoni, netdev, devicetree, linux-kernel, linux-omap
In-Reply-To: <20260403-b4-var-som-om44-lan7500-v1-0-0dadde850143@bootlin.com>
On Fri, 03 Apr 2026 21:02:22 +0200 Thomas Richard wrote:
> The goal of this series is to add the USB Ethernet controller node in the
> VAR-SOM-OM44 devicetree in order to allow the bootloader to patch the
> devicetree and pass a MAC address to the smsc75xx driver. This was also a
> good opportunity to create the schema file for LAN75XX devices.
But there's no driver for it yet, right?
IDK what the best practices are here, just unusual to see a schema
without a driver, is all.
^ permalink raw reply
* Re: [PATCH v2 2/3] arm64: dts: qcom: kaanpaali: Add USB support for MTP platform
From: Dmitry Baryshkov @ 2026-04-03 20:20 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Krishna Kurapati, linux-arm-msm, devicetree, linux-kernel,
Ronak Raheja, Jingyi Wang, Konrad Dybcio, Bjorn Andersson,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <10a9a474-7612-478e-9fb2-85b7b01ec7f6@oss.qualcomm.com>
On Sat, Apr 04, 2026 at 01:39:50AM +0530, Akhil P Oommen wrote:
> On 3/29/2026 11:22 PM, Krishna Kurapati wrote:
> > From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> >
> > Enable USB support on Kaanapali MTP variant. Enable USB controller in
> > device mode till glink node is added.
> >
> > Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> > Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 27 ++++++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> >
> > +
> > +&usb {
> > + dr_mode = "peripheral";
>
> I can see that the usb port in the MTP support 'host' mode too. Should
> this be 'otg'?
It's stated in the commit message: OTG requires glink, which is not
available yet.
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 7/7] arm64: defconfig: enable clock controller drivers for Qualcomm Nord
From: Dmitry Baryshkov @ 2026-04-03 20:21 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi, linux-arm-msm,
linux-clk, devicetree, linux-kernel, netdev
In-Reply-To: <20260403-nord-clks-v1-7-018af14979fd@oss.qualcomm.com>
On Fri, Apr 03, 2026 at 04:10:55PM +0200, Bartosz Golaszewski wrote:
> Enable the clock controller drivers for Nord platform from Qualcomm.
Same comment. It can't be enabled for the 'platform'.
>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> ---
> arch/arm64/configs/defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 163b7f0314c90fc45eb6c4aa5e8faa549c60fdf7..f1a3333bb07482ef4f8b4ea9154b0f2c74587a04 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1483,6 +1483,8 @@ CONFIG_CLK_KAANAPALI_GCC=y
> CONFIG_CLK_KAANAPALI_GPUCC=m
> CONFIG_CLK_KAANAPALI_TCSRCC=m
> CONFIG_CLK_KAANAPALI_VIDEOCC=m
> +CONFIG_CLK_NORD_GCC=y
> +CONFIG_CLK_NORD_TCSRCC=y
> CONFIG_CLK_X1E80100_CAMCC=m
> CONFIG_CLK_X1E80100_DISPCC=m
> CONFIG_CLK_X1E80100_GCC=y
>
> --
> 2.47.3
>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 5/7] clk: qcom: rpmh: Add support for Nord rpmh clocks
From: Dmitry Baryshkov @ 2026-04-03 20:22 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi, linux-arm-msm,
linux-clk, devicetree, linux-kernel, netdev, Prasanna Tolety
In-Reply-To: <20260403-nord-clks-v1-5-018af14979fd@oss.qualcomm.com>
On Fri, Apr 03, 2026 at 04:10:53PM +0200, Bartosz Golaszewski wrote:
> From: Prasanna Tolety <quic_ptolety@quicinc.com>
>
> Add RPMH clock support for the Nord SoC to allow enable/disable of the
> clocks.
>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> ---
> drivers/clk/qcom/clk-rpmh.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 5/7] clk: qcom: rpmh: Add support for Nord rpmh clocks
From: Dmitry Baryshkov @ 2026-04-03 20:22 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, Taniya Das,
Richard Cochran, Shawn Guo, Deepti Jaggi, linux-arm-msm,
linux-clk, devicetree, linux-kernel, netdev, Prasanna Tolety
In-Reply-To: <20260403-nord-clks-v1-5-018af14979fd@oss.qualcomm.com>
On Fri, Apr 03, 2026 at 04:10:53PM +0200, Bartosz Golaszewski wrote:
> From: Prasanna Tolety <quic_ptolety@quicinc.com>
>
> Add RPMH clock support for the Nord SoC to allow enable/disable of the
> clocks.
>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> ---
> drivers/clk/qcom/clk-rpmh.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> @@ -1054,6 +1073,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
> }
>
> static const struct of_device_id clk_rpmh_match_table[] = {
> + { .compatible = "qcom,nord-rpmh-clk", .data = &clk_rpmh_nord},
I R-B'ed already, but then I noticed. Please keep the list sorted out.
> { .compatible = "qcom,eliza-rpmh-clk", .data = &clk_rpmh_eliza},
> { .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
> { .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
>
> --
> 2.47.3
>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v3] Add remoteproc PAS loader for SoCCP on Glymur DT
From: Dmitry Baryshkov @ 2026-04-03 20:25 UTC (permalink / raw)
To: Ananthu C V
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Sibi Sankar
In-Reply-To: <20260403-glymur-soccp-v3-1-f0e8d57f11ba@oss.qualcomm.com>
On Fri, Apr 03, 2026 at 04:39:05AM -0700, Ananthu C V wrote:
> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++++
> arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++++++
> 2 files changed, 54 insertions(+)
Missing commit message.
Also, as this is adding SocCP, can we get pmic glink device?
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: arm: qcom: Add monaco-evk-ac support
From: Dmitry Baryshkov @ 2026-04-03 20:28 UTC (permalink / raw)
To: Umang Chheda
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Richard Cochran, linux-arm-msm, devicetree,
linux-kernel, netdev
In-Reply-To: <0f2612b8-5c44-4934-a625-27a66eeb7bdd@oss.qualcomm.com>
On Fri, Apr 03, 2026 at 04:14:28PM +0530, Umang Chheda wrote:
> Hello Dmitry,
>
> On 4/1/2026 5:06 PM, Dmitry Baryshkov wrote:
> > On Wed, Apr 01, 2026 at 12:14:42AM +0530, Umang Chheda wrote:
> >> Introduce bindings for the monaco-evk-ac IoT board, which is
> >> based on the monaco-ac (QCS8300-AC) SoC variant.
> >
> > If it is a different SoC SKU, should it be reflected in the SoC compat
> > strings?
>
> Monaco‑AC does not introduce any S/W differences compared to Monaco SoC
> -- All IP blocks and bindings remain identical from S/W PoV, Hence
> haven't included the SoC SKU in the SoC compat strings.
>
> Hope this is okay ? Your view on this ?
You are descibing -AC as the main difference between the kits, but then
you say that -AC doesn't bring new software interfaces. What is the
difference then between monako-evk and the -ac variant?
Also, from the naming point of view, it is monako-ac-evk, not the other
way.
>
> >
> >>
> >> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
> >> ---
> >> Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
> >> 1 file changed, 1 insertion(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> >> index ca880c105f3b..c76365a89687 100644
> >> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> >> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> >> @@ -918,6 +918,7 @@ properties:
> >> - enum:
> >> - arduino,monza
> >> - qcom,monaco-evk
> >> + - qcom,monaco-evk-ac
> >> - qcom,qcs8300-ride
> >> - const: qcom,qcs8300
> >>
> >>
> >> --
> >> 2.34.1
> >>
> >
>
> Thanks,
> Umang
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 0/2] Add USB Ethernet controller (LAN7500) node in VAR-SOM-OM44 devicetree
From: Nicolai Buchwitz @ 2026-04-03 20:33 UTC (permalink / raw)
To: Jakub Kicinski
Cc: Thomas Richard, Andrew Lunn, David S. Miller, Eric Dumazet,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Aaro Koskinen, Andreas Kemnade, Kevin Hilman, Roger Quadros,
Tony Lindgren, Thomas Petazzoni, netdev, devicetree, linux-kernel,
linux-omap
In-Reply-To: <20260403131801.359be561@kernel.org>
On 3.4.2026 22:18, Jakub Kicinski wrote:
> On Fri, 03 Apr 2026 21:02:22 +0200 Thomas Richard wrote:
>> The goal of this series is to add the USB Ethernet controller node in
>> the
>> VAR-SOM-OM44 devicetree in order to allow the bootloader to patch the
>> devicetree and pass a MAC address to the smsc75xx driver. This was
>> also a
>> good opportunity to create the schema file for LAN75XX devices.
>
> But there's no driver for it yet, right?
> IDK what the best practices are here, just unusual to see a schema
> without a driver, is all.
The smsc75xx driver has been in the tree since 2010 (d0cad871703b) and
already reads local-mac-address/mac-address from devicetree via
platform_get_ethdev_address() in smsc75xx_init_mac_address(), so the
binding should be covered on the driver side.
^ permalink raw reply
* RE: [PATCh v3 14/14] ASoC: rsnd: Add system suspend/resume support
From: John Madieu @ 2026-04-03 20:40 UTC (permalink / raw)
To: Kuninori Morimoto
Cc: Mark Brown, Liam Girdwood, Geert Uytterhoeven, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
magnus.damm, Philipp Zabel, Claudiu.Beznea, Biju Das,
john.madieu@gmail.com, linux-sound@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <87eckwg67x.wl-kuninori.morimoto.gx@renesas.com>
Hi Kuninori,
Thanks for your review.
> -----Original Message-----
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Sent: Friday, April 3, 2026 3:53 AM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCh v3 14/14] ASoC: rsnd: Add system suspend/resume
> support
>
>
> Hi John
>
> > Add per-module suspend/resume functions following the existing driver
> > architecture where each module manages its own resources in its own
> > file. core.c provides common clock/reset helpers and orchestrates the
> > calls in the correct order (reverse probe for suspend, probe order for
> > resume).
> >
> > Infrastructure clocks (ADG, audmacpp, SCU) are managed globally using
> > optional APIs to remain transparent to platforms that don't specify
> > these clocks/resets.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> (snip)
> > +/* Per-module suspend/resume */
> > +void rsnd_ssi_suspend(struct rsnd_priv *priv); void
> > +rsnd_ssi_resume(struct rsnd_priv *priv); void
> > +rsnd_ssiu_suspend(struct rsnd_priv *priv); void
> > +rsnd_ssiu_resume(struct rsnd_priv *priv); void
> > +rsnd_src_suspend(struct rsnd_priv *priv); void rsnd_src_resume(struct
> > +rsnd_priv *priv); void rsnd_ctu_suspend(struct rsnd_priv *priv); void
> > +rsnd_ctu_resume(struct rsnd_priv *priv); void rsnd_mix_suspend(struct
> > +rsnd_priv *priv); void rsnd_mix_resume(struct rsnd_priv *priv); void
> > +rsnd_dvc_suspend(struct rsnd_priv *priv); void rsnd_dvc_resume(struct
> > +rsnd_priv *priv); void rsnd_adg_suspend(struct rsnd_priv *priv); void
> > +rsnd_adg_resume(struct rsnd_priv *priv); void rsnd_dma_suspend(struct
> > +rsnd_priv *priv); void rsnd_dma_resume(struct rsnd_priv *priv);
>
> rsnd.h is categorizing definition for each IPs.
> Please merge above into existing area.
Agreed. I'll distribute each suspend/resume declaration into its respective
section following the probe/remove pattern.
Regards,
John
>
> Thank you for your help !!
>
> Best regards
> ---
> Kuninori Morimoto
^ permalink raw reply
* RE: [PATCh v3 13/14] ASoC: rsnd: Export rsnd_ssiu_mod_get() for PM support
From: John Madieu @ 2026-04-03 20:41 UTC (permalink / raw)
To: Kuninori Morimoto
Cc: Mark Brown, Liam Girdwood, Geert Uytterhoeven, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
magnus.damm, Philipp Zabel, Claudiu.Beznea, Biju Das,
john.madieu@gmail.com, linux-sound@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <87cy0gg5wl.wl-kuninori.morimoto.gx@renesas.com>
Hi Kuninori,
Thanks for your review.
> -----Original Message-----
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Sent: Friday, April 3, 2026 4:00 AM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Cc: Mark Brown <broonie@kernel.org>; Liam Girdwood <lgirdwood@gmail.com>;
> Geert Uytterhoeven <geert+renesas@glider.be>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
> <conor+dt@kernel.org>; Jaroslav Kysela <perex@perex.cz>; Takashi Iwai
> <tiwai@suse.com>; magnus.damm <magnus.damm@gmail.com>; Philipp Zabel
> <p.zabel@pengutronix.de>; Claudiu.Beznea <claudiu.beznea@tuxon.dev>; Biju
> Das <biju.das.jz@bp.renesas.com>; john.madieu@gmail.com; linux-
> sound@vger.kernel.org; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCh v3 13/14] ASoC: rsnd: Export rsnd_ssiu_mod_get() for
> PM support
>
>
> Hi John
>
> > Remove the static qualifier from rsnd_ssiu_mod_get() and export it via
> > rsnd.h.
> >
> > This is preparation for system suspend/resume support, where the PM
> > callbacks need to access SSIU modules to manage their clock and reset
> > state.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
>
> Is rsnd_ssiu_mod_get() really used ?
> I can't find it on [14/14]
You're right. I'll simply drop this patch.
Regards,
John.
>
> Thank you for your help !!
>
> Best regards
> ---
> Kuninori Morimoto
^ permalink raw reply
* RE: [PATCh v3 11/14] ASoC: rsnd: src: Add SRC reset and clock support for RZ/G3E
From: John Madieu @ 2026-04-03 21:00 UTC (permalink / raw)
To: Kuninori Morimoto
Cc: Mark Brown, Liam Girdwood, Geert Uytterhoeven, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
magnus.damm, Philipp Zabel, Claudiu.Beznea, Biju Das,
john.madieu@gmail.com, linux-sound@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <87h5psg6w9.wl-kuninori.morimoto.gx@renesas.com>
Hi Kuninori,
Thanks for your review.
> -----Original Message-----
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Sent: Friday, April 3, 2026 3:39 AM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCh v3 11/14] ASoC: rsnd: src: Add SRC reset and clock
> support for RZ/G3E
>
>
> Hi John
>
> > The RZ/G3E SoC requires explicit SCU (Sampling Rate Converter Unit)
> > reset and clock management unlike previous R-Car generations:
> >
> > - scu_clk: SCU module clock
> > - scu_clkx2: SCU double-rate clock
> > - scu_supply_clk: SCU supply clock
> >
> > Without these clocks enabled, the SRC module cannot operate on RZ/G3E.
> > Add support for the shared SCU reset controller used by the SRC
> > modules on the Renesas RZ/G3E SoC. All SRC instances are gated by the
> same "scu"
> > reset line.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> (snip)
> > diff --git a/sound/soc/renesas/rcar/rsnd.h
> > b/sound/soc/renesas/rcar/rsnd.h index 2c5738926093..8700b39b535e
> > 100644
> > --- a/sound/soc/renesas/rcar/rsnd.h
> > +++ b/sound/soc/renesas/rcar/rsnd.h
> > @@ -632,6 +632,13 @@ struct rsnd_priv {
> > struct clk *audmapp_clk;
> > struct reset_control *audmapp_rstc;
> >
> > + /*
> > + * Below values will be filled in rsnd_src_probe()
> > + */
> > + struct clk *clk_scu;
> > + struct clk *clk_scu_x2;
> > + struct clk *clk_scu_supply;
>
> It is SRC specific.
> Please move it to rsnd_src instead of rsnd_priv.
Agreed. However, since rsnd_src is a per-SRC instance structure,
I'll rather have these variables static in src.c, as the clocks
are shared across all SRC instances but used only in that file.
I hope this is fine for you ?
>
> > @@ -711,8 +720,9 @@ struct rsnd_mod *rsnd_src_mod_get(struct rsnd_priv
> > *priv, int id)
> >
> > int rsnd_src_probe(struct rsnd_priv *priv) {
> > - struct device_node *node;
> > struct device *dev = rsnd_priv_to_dev(priv);
> > + struct reset_control *rstc;
> > + struct device_node *node;
>
> Very nitpick. No need to move *node :)
>
Noted. I'll keep the original declaration.
Regards,
John
> Thank you for your help !!
>
> Best regards
> ---
> Kuninori Morimoto
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