* [PATCH v3 1/2] leds: ltc3208: add driver
From: Jan Carlo Roleda @ 2026-04-06 7:17 UTC (permalink / raw)
To: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-kernel, linux-leds, devicetree, Jan Carlo Roleda
In-Reply-To: <20260406-upstream-ltc3208-v3-0-7f0b1d20ee7a@analog.com>
Kernel driver implementation for LTC3208 Multidisplay LED Driver
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
---
MAINTAINERS | 7 ++
drivers/leds/Kconfig | 11 ++
drivers/leds/Makefile | 1 +
drivers/leds/leds-ltc3208.c | 298 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 317 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 55af015174a5..48bae02057d5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15126,6 +15126,13 @@ W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
F: drivers/iio/temperature/ltc2983.c
+LTC3208 LED DRIVER
+M: Jan Carlo Roleda <jancarlo.roleda@analog.com>
+L: linux-leds@vger.kernel.org
+S: Maintained
+W: https://ez.analog.com/linux-software-drivers
+F: drivers/leds/leds-ltc3208.c
+
LTC4282 HARDWARE MONITOR DRIVER
M: Nuno Sa <nuno.sa@analog.com>
L: linux-hwmon@vger.kernel.org
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 597d7a79c988..867b120ea8ba 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -1029,6 +1029,17 @@ config LEDS_ACER_A500
This option enables support for the Power Button LED of
Acer Iconia Tab A500.
+config LEDS_LTC3208
+ tristate "LED Driver for Analog Devices LTC3208"
+ depends on LEDS_CLASS && I2C
+ select REGMAP_I2C
+ help
+ Say Y to enable the LTC3208 LED driver.
+ This supports the LED device LTC3208.
+
+ To compile this driver as a module, choose M here: the module will
+ be called ltc3208.
+
source "drivers/leds/blink/Kconfig"
comment "Flash and Torch LED drivers"
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 8fdb45d5b439..b08b539112b6 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_LEDS_LP8788) += leds-lp8788.o
obj-$(CONFIG_LEDS_LP8860) += leds-lp8860.o
obj-$(CONFIG_LEDS_LP8864) += leds-lp8864.o
obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o
+obj-$(CONFIG_LEDS_LTC3208) += leds-ltc3208.o
obj-$(CONFIG_LEDS_MAX5970) += leds-max5970.o
obj-$(CONFIG_LEDS_MAX77650) += leds-max77650.o
obj-$(CONFIG_LEDS_MAX77705) += leds-max77705.o
diff --git a/drivers/leds/leds-ltc3208.c b/drivers/leds/leds-ltc3208.c
new file mode 100644
index 000000000000..65e65cd73d73
--- /dev/null
+++ b/drivers/leds/leds-ltc3208.c
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * LED driver for Analog Devices LTC3208 Multi-Display Driver
+ *
+ * Copyright 2026 Analog Devices Inc.
+ *
+ * Author: Jan Carlo Roleda <jancarlo.roleda@analog.com>
+ */
+#include <linux/bitfield.h>
+#include <linux/errno.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/leds.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#define LTC3208_SET_HIGH_BYTE_DATA(x) FIELD_PREP(GENMASK(7, 4), (x))
+
+/* Registers */
+#define LTC3208_REG_A_GRNRED 0x1 /* Green (High half-byte) and Red (Low half-byte) current DAC*/
+#define LTC3208_REG_B_AUXBLU 0x2 /* AUX (High half-byte) and Blue (Low half-byte) current DAC*/
+#define LTC3208_REG_C_MAIN 0x3 /* Main current DAC */
+#define LTC3208_REG_D_SUB 0x4 /* Sub current DAC */
+#define LTC3208_REG_E_AUX 0x5 /* AUX DAC Select */
+#define LTC3208_REG_F_CAM 0x6 /* CAM (High half-byte and Low half-byte) current DAC*/
+#define LTC3208_REG_G_OPT 0x7 /* Device Options */
+
+/* Device Options register */
+#define LTC3208_OPT_CPO_MASK GENMASK(7, 6)
+#define LTC3208_OPT_DIS_RGBDROP BIT(3)
+#define LTC3208_OPT_DIS_CAMHILO BIT(2)
+#define LTC3208_OPT_EN_RGBS BIT(1)
+
+/* Auxiliary DAC select masks */
+#define LTC3208_AUX1_MASK GENMASK(1, 0)
+#define LTC3208_AUX2_MASK GENMASK(3, 2)
+#define LTC3208_AUX3_MASK GENMASK(5, 4)
+#define LTC3208_AUX4_MASK GENMASK(7, 6)
+
+#define LTC3208_MAX_BRIGHTNESS_4BIT 0xF
+#define LTC3208_MAX_BRIGHTNESS_8BIT 0xFF
+
+#define LTC3208_NUM_LED_GRPS 8
+#define LTC3208_NUM_AUX_LEDS 4
+
+#define LTC3208_NUM_AUX_OPT 4
+#define LTC3208_MAX_CPO_OPT 3
+
+enum ltc3208_aux_channel {
+ LTC3208_AUX_CHAN_AUX = 0,
+ LTC3208_AUX_CHAN_MAIN,
+ LTC3208_AUX_CHAN_SUB,
+ LTC3208_AUX_CHAN_CAM
+};
+
+enum ltc3208_channel {
+ LTC3208_CHAN_MAIN = 0,
+ LTC3208_CHAN_SUB,
+ LTC3208_CHAN_AUX,
+ LTC3208_CHAN_CAML,
+ LTC3208_CHAN_CAMH,
+ LTC3208_CHAN_RED,
+ LTC3208_CHAN_BLUE,
+ LTC3208_CHAN_GREEN
+};
+
+static const char * const ltc3208_dt_aux_channels[] = {
+ "adi,aux1-channel", "adi,aux2-channel",
+ "adi,aux3-channel", "adi,aux4-channel"
+};
+
+static const char * const ltc3208_aux_opt[] = {
+ "aux", "main", "sub", "cam"
+};
+
+
+struct ltc3208_led {
+ struct led_classdev cdev;
+ struct i2c_client *client;
+ enum ltc3208_channel channel;
+};
+
+struct ltc3208_dev {
+ struct i2c_client *client;
+ struct regmap *map;
+ struct ltc3208_led *leds;
+};
+
+static const struct regmap_config ltc3208_regmap_cfg = {
+ .reg_bits = 8,
+ .val_bits = 8,
+};
+
+static int ltc3208_led_set_brightness(struct led_classdev *led_cdev,
+ enum led_brightness brightness)
+{
+ struct ltc3208_led *led = container_of(led_cdev,
+ struct ltc3208_led, cdev);
+ struct i2c_client *client = led->client;
+ struct ltc3208_dev *dev = i2c_get_clientdata(client);
+ struct regmap *map = dev->map;
+ u8 current_level = brightness;
+
+ /*
+ * For registers with 4-bit splits (CAM, AUX/BLUE, GREEN/RED), the other
+ * half of the byte will be retrieved from the stored DAC value before
+ * updating the register.
+ */
+ switch (led->channel) {
+ case LTC3208_CHAN_MAIN:
+ return regmap_write(map, LTC3208_REG_C_MAIN, current_level);
+ case LTC3208_CHAN_SUB:
+ return regmap_write(map, LTC3208_REG_D_SUB, current_level);
+ case LTC3208_CHAN_AUX:
+ /* combine both low and high halves of byte */
+ current_level = LTC3208_SET_HIGH_BYTE_DATA(current_level);
+ current_level |= dev->leds[LTC3208_CHAN_BLUE].cdev.brightness;
+ return regmap_write(map, LTC3208_REG_B_AUXBLU, current_level);
+ case LTC3208_CHAN_BLUE:
+ /* apply high bits stored in other led */
+ current_level |= LTC3208_SET_HIGH_BYTE_DATA(
+ dev->leds[LTC3208_CHAN_AUX].cdev.brightness);
+ return regmap_write(map, LTC3208_REG_B_AUXBLU, current_level);
+ case LTC3208_CHAN_CAMH:
+ current_level = LTC3208_SET_HIGH_BYTE_DATA(current_level);
+ current_level |= dev->leds[LTC3208_CHAN_CAML].cdev.brightness;
+ return regmap_write(map, LTC3208_REG_F_CAM, current_level);
+ case LTC3208_CHAN_CAML:
+ current_level |= LTC3208_SET_HIGH_BYTE_DATA(
+ dev->leds[LTC3208_CHAN_CAMH].cdev.brightness);
+ return regmap_write(map, LTC3208_REG_F_CAM, current_level);
+ case LTC3208_CHAN_GREEN:
+ current_level = LTC3208_SET_HIGH_BYTE_DATA(current_level);
+ current_level |= dev->leds[LTC3208_CHAN_RED].cdev.brightness;
+ return regmap_write(map, LTC3208_REG_A_GRNRED, current_level);
+ case LTC3208_CHAN_RED:
+ current_level |= LTC3208_SET_HIGH_BYTE_DATA(
+ dev->leds[LTC3208_CHAN_GREEN].cdev.brightness);
+ return regmap_write(map, LTC3208_REG_A_GRNRED, current_level);
+ default:
+ dev_err(&client->dev, "Invalid LED Channel\n");
+ return -EINVAL;
+ }
+}
+
+static int ltc3208_update_options(struct ltc3208_dev *dev,
+ bool is_sub, bool is_cam_hi, bool is_rgb_drop)
+{
+ struct regmap *map = dev->map;
+ u8 val = FIELD_PREP(LTC3208_OPT_EN_RGBS, is_sub) |
+ FIELD_PREP(LTC3208_OPT_DIS_CAMHILO, is_cam_hi) |
+ FIELD_PREP(LTC3208_OPT_DIS_RGBDROP, is_rgb_drop);
+
+ return regmap_write(map, LTC3208_REG_G_OPT, val);
+}
+
+static int ltc3208_update_aux_dac(struct ltc3208_dev *dev,
+ enum ltc3208_aux_channel aux_1, enum ltc3208_aux_channel aux_2,
+ enum ltc3208_aux_channel aux_3, enum ltc3208_aux_channel aux_4)
+{
+ struct regmap *map = dev->map;
+ u8 val = FIELD_PREP(LTC3208_AUX1_MASK, aux_1) |
+ FIELD_PREP(LTC3208_AUX2_MASK, aux_2) |
+ FIELD_PREP(LTC3208_AUX3_MASK, aux_3) |
+ FIELD_PREP(LTC3208_AUX4_MASK, aux_4);
+
+ return regmap_write(map, LTC3208_REG_E_AUX, val);
+}
+
+static int ltc3208_probe(struct i2c_client *client)
+{
+ enum ltc3208_aux_channel aux_channels[LTC3208_NUM_AUX_LEDS];
+ struct ltc3208_dev *data;
+ struct ltc3208_led *leds;
+ struct regmap *map;
+ int ret, i;
+ u32 val;
+ bool dropdis_rgb_aux4;
+ bool dis_camhl;
+ bool en_rgbs;
+
+ map = devm_regmap_init_i2c(client, <c3208_regmap_cfg);
+ if (IS_ERR(map))
+ return dev_err_probe(&client->dev, PTR_ERR(map),
+ "Failed to initialize regmap\n");
+
+ data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ leds = devm_kcalloc(&client->dev, LTC3208_NUM_LED_GRPS,
+ sizeof(struct ltc3208_led), GFP_KERNEL);
+ if (!leds)
+ return -ENOMEM;
+
+ data->client = client;
+ data->map = map;
+
+ /* initialize options from devicetree */
+ dis_camhl = device_property_read_bool(&client->dev,
+ "adi,disable-camhl-pin");
+ en_rgbs = device_property_read_bool(&client->dev,
+ "adi,cfg-enrgbs-pin");
+ dropdis_rgb_aux4 = device_property_read_bool(&client->dev,
+ "adi,disable-rgb-aux4-dropout");
+
+ ret = ltc3208_update_options(data, en_rgbs, dis_camhl,
+ dropdis_rgb_aux4);
+ if (ret)
+ return dev_err_probe(&client->dev, ret,
+ "error writing to options register\n");
+
+ /* initialize aux channel configurations from devicetree */
+ for (i = 0; i < LTC3208_NUM_AUX_LEDS; i++) {
+ ret = device_property_match_property_string(&client->dev,
+ ltc3208_dt_aux_channels[i],
+ ltc3208_aux_opt,
+ LTC3208_NUM_AUX_OPT);
+ /* use default value if absent in devicetree */
+ if (ret == -EINVAL)
+ aux_channels[i] = LTC3208_AUX_CHAN_AUX;
+ else if (ret >= 0)
+ aux_channels[i] = ret;
+ else
+ return dev_err_probe(&client->dev, ret,
+ "Failed getting aux-channel.\n");
+ }
+
+ ret = ltc3208_update_aux_dac(data, aux_channels[0], aux_channels[1],
+ aux_channels[2], aux_channels[3]);
+ if (ret)
+ return dev_err_probe(&client->dev, ret,
+ "error writing to aux %u channel register.\n", i);
+
+ i2c_set_clientdata(client, data);
+
+ device_for_each_child_node_scoped(&client->dev, child) {
+ struct ltc3208_led *led;
+ struct led_init_data init_data = {};
+
+ ret = fwnode_property_read_u32(child, "reg", &val);
+ if (ret || val >= LTC3208_NUM_LED_GRPS)
+ return dev_err_probe(&client->dev, -EINVAL,
+ "Invalid reg property for LED\n");
+
+ led = &leds[val];
+ led->client = client;
+ led->channel = val;
+ led->cdev.brightness_set_blocking = ltc3208_led_set_brightness;
+ led->cdev.max_brightness = LTC3208_MAX_BRIGHTNESS_4BIT;
+ if (val == LTC3208_CHAN_MAIN || val == LTC3208_CHAN_SUB)
+ led->cdev.max_brightness = LTC3208_MAX_BRIGHTNESS_8BIT;
+
+ init_data.fwnode = child;
+
+ ret = devm_led_classdev_register_ext(&client->dev, &led->cdev,
+ &init_data);
+ if (ret)
+ return dev_err_probe(&client->dev, ret,
+ "Failed to register LED %u\n", val);
+ }
+
+ data->leds = leds;
+
+ return 0;
+}
+
+static const struct of_device_id ltc3208_match_table[] = {
+ {.compatible = "adi,ltc3208"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, ltc3208_match_table);
+
+static const struct i2c_device_id ltc3208_idtable[] = {
+ { "ltc3208" },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, ltc3208_idtable);
+
+static struct i2c_driver ltc3208_driver = {
+ .driver = {
+ .name = "ltc3208",
+ .of_match_table = ltc3208_match_table,
+ },
+ .id_table = ltc3208_idtable,
+ .probe = ltc3208_probe,
+};
+module_i2c_driver(ltc3208_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jan Carlo Roleda <jancarlo.roleda@analog.com>");
+MODULE_DESCRIPTION("LTC3208 LED Driver");
--
2.43.0
^ permalink raw reply related
* [PATCH v3 0/2] Add support for LTC3208 multi-display driver
From: Jan Carlo Roleda @ 2026-04-06 7:17 UTC (permalink / raw)
To: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-kernel, linux-leds, devicetree, Jan Carlo Roleda
The LTC3208 is a multi-display LED driver, using a high-efficiency, low
noise charge pump to provide power to 5 channels (MAIN, SUB, RGB, CAM,
AUX). Current for each LED is controlled by the I2C serial interface.
Four AUX current sources can be independently assigned via the I2C port
to the CAM, SUB, MAIN, or AUX DAC controlled displays
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
---
Changes in v3:
- Edited device bindings descriptions
-- removed full stop in title
-- replaced quotes with double quotes for consistency
-- removed <dt-bindings/gpio/gpio.h> from example
-- removed led1-7 in example for brevity
- squashed maintainers commit to driver commit
- Link to v2: https://lore.kernel.org/r/20260326-upstream-ltc3208-v2-0-3dbc992b6098@analog.com
Changes in v2:
- Addressed DTSchema bot warnings and errors
-- removed extra blank lines
-- fixed $id to match current naming
- Addressed Kernel test warnings
-- fixed bounds for aux channel configurations
- Link to v0: https://lore.kernel.org/r/20260318-upstream-ltc3208-v1-0-015f1f1e9065@analog.com
---
Jan Carlo Roleda (2):
leds: ltc3208: add driver
dt-bindings: leds: Document LTC3208 Multidisplay LED Driver
.../devicetree/bindings/leds/adi,ltc3208.yaml | 129 +++++++++
MAINTAINERS | 8 +
drivers/leds/Kconfig | 11 +
drivers/leds/Makefile | 1 +
drivers/leds/leds-ltc3208.c | 298 +++++++++++++++++++++
5 files changed, 447 insertions(+)
---
base-commit: e68f95a51d1a8c1594b536c4d495cbea38d47561
change-id: 20260318-upstream-ltc3208-7cc8968bf69e
Best regards,
--
Jan Carlo Roleda <jancarlo.roleda@analog.com>
^ permalink raw reply
* Re: [PATCH net-next v2 4/4] net: dsa: initial support for MT7628 embedded switch
From: Joris Vaisvila @ 2026-04-06 7:13 UTC (permalink / raw)
To: Jakub Kicinski
Cc: netdev, horms, pabeni, edumazet, davem, olteanv, andrew,
devicetree, robh, krzk+dt, conor+dt
In-Reply-To: <20260402033103.911409-1-kuba@kernel.org>
Hi Jakub, thank you for the review.
On Wed, Apr 01, 2026 at 08:31:03PM -0700, Jakub Kicinski wrote:
> This is an AI-generated review of your patch. The human sending this
> email has considered the AI review valid, or at least plausible.
> ---
> net: dsa: initial support for MT7628 embedded switch
>
> Add support for the MT7628 embedded switch.
> The switch has 5 built-in 100Mbps user ports (ports 0-4) and one 1Gbps
> port that is internally attached to the SoCs CPU MAC and serves as the
> CPU port.
>
> > diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
> > --- a/drivers/net/dsa/Kconfig
> > +++ b/drivers/net/dsa/Kconfig
> > @@ -28,6 +28,14 @@ source "drivers/net/dsa/hirschmann/Kconfig"
> >
> > source "drivers/net/dsa/lantiq/Kconfig"
> >
> > +config NET_DSA_MT7628
> > + tristate "MediaTek MT7628 Embedded Ethernet switch support"
> > + select NET_DSA_TAG_MT7628
> > + select MEDIATEK_FE_SOC_PHY
>
> Does this configuration need to select NET_DSA_TAG_8021Q?
>
> The driver relies on the tag_8021q mechanism for switch port isolation. If
> the kernel is configured without NET_DSA_TAG_8021Q, dsa_tag_8021q_register()
> will return -EOPNOTSUPP, causing the switch to boot with broken port
> isolation.
>
tag_8021q.o is in DSA core, there's no option to enable or disable it.
> [ ... ]
> > +static int mt7628_mii_read(struct mii_bus *bus, int port, int regnum)
> > +{
> > + struct mt7628_esw *esw = bus->priv;
> > + int ret;
> > + u32 val;
> > +
> > + ret = regmap_read_poll_timeout(esw->regmap, MT7628_ESW_REG_PCR1, val,
> > + !(val & MT7628_ESW_PCR1_RD_DONE), 10,
> > + 5000);
>
> Will this polling logic cause an MDIO timeout?
>
> If RD_DONE is a completion status bit that remains 1 after a successful
> operation, this first poll will wait indefinitely for the bit to become 0.
>
> If RD_DONE is an active-low busy bit, the second poll below waits for the
> controller to become busy instead of waiting for it to be idle.
>
RD_DONE gets set when the read operations completes and is reset on
register read, so this will not cause a timeout.
> > + if (ret)
> > + goto out;
> > +
> > + ret = regmap_write(esw->regmap, MT7628_ESW_REG_PCR0,
> > + FIELD_PREP(MT7628_ESW_PCR0_CPU_PHY_REG,
> > + regnum) |
> > + FIELD_PREP(MT7628_ESW_PCR0_CPU_PHY_ADDR,
> > + port) | MT7628_ESW_PCR0_RD_PHY_CMD);
> > + if (ret)
> > + goto out;
> > +
> > + ret = regmap_read_poll_timeout(esw->regmap, MT7628_ESW_REG_PCR1, val,
> > + (val & MT7628_ESW_PCR1_RD_DONE), 10,
> > + 5000);
> > +out:
> > + if (ret) {
> > + dev_err(&bus->dev, "read failed. MDIO timeout?\n");
> > + return ret;
> > + }
> > + return FIELD_GET(MT7628_ESW_PCR1_RD_DATA, val);
> > +}
> > +
> > +static int mt7628_mii_write(struct mii_bus *bus, int port, int regnum, u16 dat)
> > +{
> > + struct mt7628_esw *esw = bus->priv;
> > + u32 val;
> > + int ret;
> > +
> > + ret = regmap_read_poll_timeout(esw->regmap, MT7628_ESW_REG_PCR1, val,
> > + !(val & MT7628_ESW_PCR1_WT_DONE), 10,
> > + 5000);
> > + if (ret)
> > + goto out;
> > +
> > + ret = regmap_write(esw->regmap, MT7628_ESW_REG_PCR0,
> > + FIELD_PREP(MT7628_ESW_PCR0_WT_NWAY_DATA, dat) |
> > + FIELD_PREP(MT7628_ESW_PCR0_CPU_PHY_REG,
> > + regnum) |
> > + FIELD_PREP(MT7628_ESW_PCR0_CPU_PHY_ADDR,
> > + port) | MT7628_ESW_PCR0_WT_PHY_CMD);
> > + if (ret)
> > + goto out;
> > +
> > + ret = regmap_read_poll_timeout(esw->regmap, MT7628_ESW_REG_PCR1, val,
> > + (val & MT7628_ESW_PCR1_WT_DONE), 10,
> > + 5000);
>
> Is this second poll waiting for the controller to become busy instead of
> idle, similar to the read function?
>
WT_DONE is set when the data is ready and reset on read, same as
RD_DONE.
> > +out:
> > + if (ret) {
> > + dev_err(&bus->dev, "write failed. MDIO timeout?\n");
> > + return ret;
> > + }
> > + return 0;
> > +}
> > +
> > +static int mt7628_setup_internal_mdio(struct dsa_switch *ds)
> > +{
> > + struct mt7628_esw *esw = ds->priv;
> > + struct device_node *mdio;
> > + struct mii_bus *bus;
> > + int ret = 0;
> > +
> > + mdio = of_get_available_child_by_name(ds->dev->of_node, "mdio");
> > +
> > + bus = devm_mdiobus_alloc(esw->dev);
>
> Can allocating devm_ resources in the DSA .setup callback cause a sysfs name
> collision?
>
> The .setup callback is executed whenever the DSA tree binds. Since devm_
> resources are tied to the platform device (esw->dev) rather than the DSA
> tree lifecycle, they are not released when the DSA tree unbinds. On a
> subsequent re-bind, allocating a new MDIO bus with the same ID will fail
> because the original bus was never unregistered.
>
I'm not sure how this would work. Other switches appear to be doing the
same. For example mt7530-mmio.c does `priv->dev = &pdev->dev` and later
uses priv->dev to register the mdio bus. Is this a real issue?
> [ ... ]
> > +static int mt7628_setup(struct dsa_switch *ds)
> > +{
> > + struct mt7628_esw *esw = ds->priv;
> > + int ret;
> > +
> > + reset_control_reset(esw->rst_esw);
> > + usleep_range(1000, 2000);
> > + reset_control_reset(esw->rst_ephy);
> > + usleep_range(1000, 2000);
> > + /*
> > + * all MMIO reads hang if esw is not out of reset
> > + * ephy needs extra time to get out of reset or it ends up misconfigured
> > + */
> > + mt7628_switch_init(ds);
> > + rtnl_lock();
> > + dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
>
> Is it safe to ignore the return value of dsa_tag_8021q_register()?
>
> If the registration fails, the core function frees the allocated context but
> does not clear ds->tag_8021q_ctx. The setup will continue, and the DSA core
> will later dereference the non-NULL ds->tag_8021q_ctx, leading to a
> use-after-free crash.
>
> Also, if mt7628_setup_internal_mdio() below fails, the setup returns an
> error without unregistering the tagger, which leaks the tag_8021q context.
>
No, will fix in v3.
> > + rtnl_unlock();
> > +
> > + ret = mt7628_setup_internal_mdio(ds);
> > + return ret;
> > +}
> [ ... ]
> > +static struct dsa_switch_ops mt7628_switch_ops = {
> > + .get_tag_protocol = mt7628_get_tag_proto,
> > + .setup = mt7628_setup,
>
> Does this switch ops structure need a .teardown callback?
>
> Without calling dsa_tag_8021q_unregister() in a .teardown callback, the
> tag_8021q context memory allocated during .setup will be permanently leaked
> whenever the DSA switch is unbound or the module is removed.
>
Yes, will fix in V3.
Thanks,
Joris
^ permalink raw reply
* RE: [PATCH v4 1/2] dt-bindings: iio: dac: Add ADI AD5706R
From: Torreno, Alexis Czezar @ 2026-04-06 7:04 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lars-Peter Clausen, Hennerich, Michael, Jonathan Cameron,
David Lechner, Sa, Nuno, Andy Shevchenko, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-iio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <20260402-new-venomous-groundhog-e646ee@quoll>
> > + pwms:
> > + maxItems: 1
> > + description:
> > + Optional PWM connected to the LDAC/TGP/DCK pin for hardware
> > + triggered DAC updates, toggle, or dither clock generation.
> > +
> > + reset-gpios:
> > + maxItems: 1
> > + description:
> > + GPIO connected to the active low RESET pin. If not provided,
> > + software reset is used.
> > +
> > + out-en-gpios:
>
> Isn't this just enable-gpios from gpio-consumer-common? Does the device
> have more enable-like GPIOs?
>
Ah, there's only 1 enable-like GPIO. Yeah, need to rename this to 'enable-gpios'
Regards,
Alexis
^ permalink raw reply
* RE: [PATCH v4 2/2] iio: dac: ad5706r: Add support for AD5706R DAC
From: Torreno, Alexis Czezar @ 2026-04-06 7:04 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Lars-Peter Clausen, Hennerich, Michael, Jonathan Cameron,
David Lechner, Sa, Nuno, Andy Shevchenko, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-iio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <ac0yEfGzqsbkZh86@ashevche-desk.local>
> On Wed, Apr 01, 2026 at 06:20:04PM +0800, Alexis Czezar Torreno wrote:
> > Add support for the Analog Devices AD5706R, a 4-channel 16-bit current
> > output digital-to-analog converter with SPI interface.
> >
> > Features:
> > - 4 independent DAC channels
> > - Hardware and software LDAC trigger
> > - Configurable output range
> > - PWM-based LDAC control
> > - Dither and toggle modes
> > - Dynamically configurable SPI speed
>
> ...
>
> > ---
> > Changes since v1:
> > - Removed PWM, GPIO, clock generator, debugfs, regmap, IIO_BUFFER
> > - Removed all custom ext_info sysfs attributes
> > - Simplified to basic raw read/write and read-only scale
> > - SPI read/write can handle multibyte registers
> > ---
>
> A bit confusing to have this changelog w/o having v3..v4 ones.
Will add the others
>
> ...
>
> > +config AD5706R
> > + tristate "Analog Devices AD5706R DAC driver"
> > + depends on SPI
>
> Shouldn't you select REGMAP?
Oh yeah, I should've. Will add
>
> > + help
> > + Say yes here to build support for Analog Devices AD5706R 4-channel,
> > + 16-bit current output DAC.
> > +
> > + To compile this driver as a module, choose M here: the
> > + module will be called ad5706r.
>
> ...
>
> > +#include <linux/array_size.h>
> > +#include <linux/bits.h>
>
> > +#include <linux/device.h>
>
> Not used, but dev_printk.h is missing.
>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/err.h>
>
> > +#include <linux/errno.h>
>
> No need (in most cases) when err.h is included.
>
> > +#include <linux/iio/iio.h>
> > +#include <linux/minmax.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/module.h>
> > +#include <linux/regmap.h>
> > +#include <linux/spi/spi.h>
> > +#include <linux/string.h>
> > +#include <linux/types.h>
> > +#include <linux/unaligned.h>
>
> Based on the above comments, please revisit the header block.
Will do, thanks for the suggestions above.
>
> ...
>
> > +struct ad5706r_state {
> > + struct spi_device *spi;
> > + struct regmap *regmap;
> > +
> > + u8 tx_buf[4] __aligned(ARCH_DMA_MINALIGN);
>
> Don't we have specific IIO macro for that?
Ah yeah I think it was IIO_DMA_MINALIGN, will change, will also remove the
header where ARCH_DMA_MINALIGN comes from
>
> > +static int ad5706r_regmap_write(void *context, const void *data,
> > +size_t count) {
> > + struct ad5706r_state *st = context;
> > + unsigned int num_bytes;
>
> Currently only 1 and 2 bytes are supported, right? Any updates are planned on
> this in the future?
Yes only 1 and 2 bytes, no future extension. Should I make num_bytes a 'u8'?
>
> > + u16 reg;
> > +
...
> > +
> > + cmd = AD5706R_RD_MASK | (reg & AD5706R_ADDR_MASK);
> > + put_unaligned_be16(cmd, st->tx_buf);
>
> > + memset(st->tx_buf + 2, 0, num_bytes);
>
> I would use &st->tx_buf[2] here and below for the sake of consistency with
> put_unaligned_*().
Will edit for consistnency.
>
> > + ret = spi_sync_transfer(st->spi, &xfer, 1);
> > + if (ret)
> > + return ret;
> > +
> > + /* Ignore the first two bytes (echo during command) */
> > + if (num_bytes == AD5706R_SINGLE_BYTE_LEN)
> > + put_unaligned_be16(st->rx_buf[2], val_buf);
>
> The comment wants to explain why it's required to put 2 bytes anyway.
Will add clearer comments for this
>
> > + else
> > + memcpy(val_buf, st->rx_buf + 2, num_bytes);
>
> However with the above question in mind, if it's all about 1 or 2 bytes, can't we
> simply use the same approach everywhere, like put_unaligned_*()?
For consistency, put_unaligned_*() can work.
Although since rx_buf is u8, this line:
memcpy(val_buf, &st->rx_buf[2], num_bytes);
Will look like this for 2 bytes:
x = get_unaligned_be16( &st->rx_buf[2] )
put_unaligned_be16( x, val_buf )
I suppose the mem* commands looks cleaner
>
> ...
>
> > +static int ad5706r_read_raw(struct iio_dev *indio_dev,
> > + struct iio_chan_spec const *chan, int *val,
> > + int *val2, long mask)
>
> Better to use logical split (here and elsewhere where appropriate)
>
> static int ad5706r_read_raw(struct iio_dev *indio_dev,
> struct iio_chan_spec const *chan,
> int *val, int *val2, long mask)
>
> ...
>
> > + st->regmap = devm_regmap_init(&spi->dev, &ad5706r_regmap_bus,
> > + st, &ad5706r_regmap_config);
>
> Use
>
> struct device *dev = &spi->dev;
>
> at the top of the function to make this look better.
>
> > + if (IS_ERR(st->regmap))
> > + return dev_err_probe(&spi->dev, PTR_ERR(st->regmap),
> > + "Failed to init regmap");
>
> Missing \n.
>
Will apply the three minor edits above
^ permalink raw reply
* [PATCH 3/3] arm64: tegra: Correct Tegra234 p3740 interrupt flags
From: Krzysztof Kozlowski @ 2026-04-06 6:49 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
Jonathan Hunter, devicetree, linux-tegra, linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20260406064935.27968-4-krzysztof.kozlowski@oss.qualcomm.com>
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING
Realtek RT5540 codec driver requests interrupt on rising edge, so correct
the interrupt flags, assuming the author of the code wanted the similar
logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_HIGH => IRQ_TYPE_EDGE_RISING
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
index 9ce55b4d2de8..97cede1fcb70 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
@@ -75,7 +75,7 @@ rt5640: audio-codec@1c {
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+ interrupts = <TEGRA234_MAIN_GPIO(F, 3) IRQ_TYPE_EDGE_RISING>;
clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "mclk";
--
2.51.0
^ permalink raw reply related
* [PATCH 2/3] arm64: tegra: Correct Tegra234 p3737 interrupt flags
From: Krzysztof Kozlowski @ 2026-04-06 6:49 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
Jonathan Hunter, devicetree, linux-tegra, linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20260406064935.27968-4-krzysztof.kozlowski@oss.qualcomm.com>
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING
Realtek RT5540 codec driver requests interrupt on rising edge, so correct
the interrupt flags, assuming the author of the code wanted the similar
logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_HIGH => IRQ_TYPE_EDGE_RISING
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi
index f6cad29355e6..420858a8f4a8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi
@@ -67,7 +67,7 @@ audio-codec@1c {
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH>;
+ interrupts = <TEGRA234_MAIN_GPIO(AC, 5) IRQ_TYPE_EDGE_RISING>;
clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "mclk";
realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
--
2.51.0
^ permalink raw reply related
* [PATCH 1/3] arm64: tegra: Correct Tegra194 p2972 interrupt flags
From: Krzysztof Kozlowski @ 2026-04-06 6:49 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
Jonathan Hunter, devicetree, linux-tegra, linux-kernel
Cc: Krzysztof Kozlowski
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING
Realtek RT5658 codec driver requests interrupt on both edges, so correct
the interrupt flags, assuming the author of the code wanted the similar
logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_HIGH => IRQ_TYPE_EDGE_RISING
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index ea6f397a2792..5462200f1176 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -2170,7 +2170,7 @@ rt5658: audio-codec@1a {
compatible = "realtek,rt5658";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA194_MAIN_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
+ interrupts = <TEGRA194_MAIN_GPIO(S, 5) IRQ_TYPE_EDGE_RISING>;
clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>;
clock-names = "mclk";
realtek,jd-src = <2>;
--
2.51.0
^ permalink raw reply related
* [PATCH] arm64: tegra: Enable interconnect for MC and EMC on Tegra210
From: Aaron Kling via B4 Relay @ 2026-04-06 6:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
Jonathan Hunter
Cc: Thierry Reding, devicetree, linux-tegra, linux-kernel,
Aaron Kling
From: Aaron Kling <webgeek1234@gmail.com>
These are being referenced by actmon, but are not currently enabled.
Fixes: 654427e0b9b7 ("arm64: tegra: Add OPP tables on Tegra210")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
When the opp tables were added to tegra210 [0], there was a previous
commit [1] that enabled interconnect on the mc and emc nodes. This was
later reverted [2] because some setups such as the Nvidia regression
test bench do not pass emc training data and thus the emc driver cannot
probe. Since interconnects cannot be optionally routed, the dc
interconnect routes cannot be enabled if the kernel is to support
bootloader setups that do not properly pass emc training data. Thus this
only fixes the routes enough for actmon to operate, because actmon
failing to probe is no more fatal than an emc failure.
This depends on the mc/emc driver patch to add interconnect support [3],
which should be merged first.
[0] https://lore.kernel.org/linux-tegra/20251021-t210-actmon-p4-v5-3-4a4dbc49fbc8@gmail.com/
[1] https://lore.kernel.org/linux-tegra/20251021-t210-actmon-p4-v5-2-4a4dbc49fbc8@gmail.com/
[2] https://lore.kernel.org/linux-tegra/20251217104744.184153-1-jonathanh@nvidia.com/
[3] https://lore.kernel.org/linux-tegra/20260406-t210-actmon-p2-v7-1-91adf535cf8f@gmail.com/
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 5f5e5370d70966918943232acab8992bf91ec42a..a5537a5c472c4bf5d649cc52372e531452b594f7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1028,6 +1028,7 @@ mc: memory-controller@70019000 {
#iommu-cells = <1>;
#reset-cells = <1>;
+ #interconnect-cells = <1>;
};
emc: external-memory-controller@7001b000 {
@@ -1041,6 +1042,7 @@ emc: external-memory-controller@7001b000 {
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
+ #interconnect-cells = <0>;
#cooling-cells = <2>;
};
---
base-commit: 2febe6e6ee6e34c7754eff3c4d81aa7b0dcb7979
change-id: 20260405-tegra210-actmon-dt-fixup-690c74952299
Best regards,
--
Aaron Kling <webgeek1234@gmail.com>
^ permalink raw reply related
* [PATCH 3/3] arm64: dts: imx8mp-ab2: Correct interrupt flags
From: Krzysztof Kozlowski @ 2026-04-06 6:38 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Marek Vasut,
Peng Fan, Fedor Ross, Shawn Guo, Shengjiu Wang, Viorel Suman,
devicetree, imx, linux-arm-kernel, linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20260406063810.25531-4-krzysztof.kozlowski@oss.qualcomm.com>
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING
Correct the interrupt flags, assuming the author of the code wanted the
same logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW
Fixes: bf68c18150ef ("arm64: dts: imx8mp-ab2: add support for NXP i.MX8MP audio board (version 2)")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/freescale/imx8mp-ab2.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts
index dbbc0df0e3d1..443e4fd5b9bf 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts
@@ -281,7 +281,7 @@ pca9450: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
interrupt-parent = <&gpio1>;
- interrupts = <3 GPIO_ACTIVE_LOW>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_pmic>;
regulators {
--
2.51.0
^ permalink raw reply related
* [PATCH 2/3] arm64: dts: imx8mn-vhip4-evalboard-v2: Correct interrupt flags
From: Krzysztof Kozlowski @ 2026-04-06 6:38 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Marek Vasut,
Peng Fan, Fedor Ross, Shawn Guo, Shengjiu Wang, Viorel Suman,
devicetree, imx, linux-arm-kernel, linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20260406063810.25531-4-krzysztof.kozlowski@oss.qualcomm.com>
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING
Correct the interrupt flags, assuming the author of the code wanted the
same logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW
Fixes: 5eb7405db99b ("arm64: dts: imx8mn: Add ifm VHIP4 EvalBoard v1 and v2")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts
index 4dadfb7f78de..43fd4d0041ef 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts
@@ -99,7 +99,7 @@ &i2c3 {
&ifm_pmic {
interrupt-parent = <&gpio5>;
- interrupts = <17 GPIO_ACTIVE_LOW>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
};
&iomuxc {
--
2.51.0
^ permalink raw reply related
* [PATCH 1/3] arm64: dts: imx8mn-vhip4-evalboard-v1: Correct interrupt flags
From: Krzysztof Kozlowski @ 2026-04-06 6:38 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Marek Vasut,
Peng Fan, Fedor Ross, Shawn Guo, Shengjiu Wang, Viorel Suman,
devicetree, imx, linux-arm-kernel, linux-kernel
Cc: Krzysztof Kozlowski
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING
Correct the interrupt flags, assuming the author of the code wanted the
same logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW
Fixes: 5eb7405db99b ("arm64: dts: imx8mn: Add ifm VHIP4 EvalBoard v1 and v2")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
I fixed this upstream some years ago, but people still send copy-pastes
of downstream code.
---
arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts
index 5f37065bf43f..a8f7c226a61f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts
@@ -112,7 +112,7 @@ &i2c3 {
&ifm_pmic {
interrupt-parent = <&gpio2>;
- interrupts = <0 GPIO_ACTIVE_LOW>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&iomuxc {
--
2.51.0
^ permalink raw reply related
* Re: [PATCH v6 01/13] soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC path optional
From: Mukesh Kumar Savaliya @ 2026-04-06 5:37 UTC (permalink / raw)
To: Praveen Talari, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mukesh Kumar Savaliya, Viken Dadhaniya,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, bjorn.andersson, dmitry.baryshkov,
konrad.dybcio
Cc: prasad.sodagudi, aniket.randive, chandana.chiluveru,
jyothi.seerapu, chiluka.harish
In-Reply-To: <20260227061544.1785978-2-praveen.talari@oss.qualcomm.com>
On 2/27/2026 11:45 AM, Praveen Talari wrote:
> The "qup-memory" interconnect path is optional and may not be defined
> in all device trees. Unroll the loop-based ICC path initialization to
> allow specific error handling for each path type.
>
> The "qup-core" and "qup-config" paths remain mandatory and will fail
> probe if missing, while "qup-memory" is now handled as optional and
> skipped when not present in the device tree.
>
> Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
> ---
> v1->v2:
> Bjorn:
> - Updated commit text.
> - Used local variable for more readable.
> ---
> drivers/soc/qcom/qcom-geni-se.c | 36 +++++++++++++++++----------------
> 1 file changed, 19 insertions(+), 17 deletions(-)
>
Reviewed-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>
[...]
^ permalink raw reply
* Re: [PATCH v2 2/2] hwmon:(pmbus/xdp720) Add support for efuse xdp720
From: ashish yadav @ 2026-04-06 5:22 UTC (permalink / raw)
To: Guenter Roeck
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-hwmon,
devicetree, linux-kernel, Ashish Yadav
In-Reply-To: <CAJKbuCbrqRHcy28TvhkQxh6eiLb1RpWYekx5WXPj6S=qO8CNvQ@mail.gmail.com>
Hi Guenter,
I hope you’re doing well.
I’m writing to provide an update regarding the m[PSC_POWER] issue
identified in the following
patchset: https://sashiko.dev/#/patchset/20260401104550.115715-1-Ashish.Yadav%40infineon.com.
The discrepancy was caused by an incorrect divisor in the power
calculation. Specifically:
info->m[PSC_POWER] = DIV64_U64_ROUND_CLOSEST((u64) info->m[PSC_POWER]
* rimon * gimon, 1000000000000);
The divisor should be 10^15 rather than 10^12.
With this correction, the [PSC_POWER] value scales correctly to 163.29
(previously 16329).
I will include this fix in the next version of the patch.
Apologies for any inconvenience this may have caused, and thank you
for your time and feedback.
With Best Regards,
Ashish Yadav
On Thu, Apr 2, 2026 at 7:39 PM ashish yadav <ashishyadav78@gmail.com> wrote:
>
> Hi Guenter,
>
> Thanks for your valuable feedback and time.
> Please find my response in-line.
>
> With Best Regards,
> Ashish Yadav
>
> On Wed, Apr 1, 2026 at 9:26 PM Guenter Roeck <linux@roeck-us.net> wrote:
> >
> > Hi,
> >
> > On 4/1/26 03:45, ASHISH YADAV wrote:
> > > From: Ashish Yadav <ashish.yadav@infineon.com>
> > >
> > > Add the pmbus driver for Infineon XDP720 Digital eFuse Controller.
> > >
> > > Signed-off-by: Ashish Yadav <ashish.yadav@infineon.com>
> > > ---
> > > XDP720 Digital eFuse Controller provides accurate system telemetry
> > > (V, I, P, T) and reports analog current at the IMON pin for post-processing.
> > >
> > > The Current and Power measurement depends on the RIMON and GIMON values.
> > > Please look into data sheet sections 5.4.2 and 5.4.4 for more details:
> > > https://www.infineon.com/assets/row/public/documents/24/49/infineon-xdp720-001-datasheet-en.pdf
> > >
> > > The GIMON (microA/A) depends on the 10th bit of TELEMETRY_AVG PMBUS Register.
> > > The value of RIMON (kohm) can be provided by the user through device tree using
> > > infineon,rimon-micro-ohms property.
> >
> > Please have a look at
> >
> > https://sashiko.dev/#/patchset/20260401104550.115715-1-Ashish.Yadav%40infineon.com
> >
> > Main concern is the power measurement range, but also please use 1000000000000ULL
> > as suggested.
>
> Sure, We will look into it and get back to you.
>
> > Thanks,
> > Guenter
> >
> > > ---
> > > drivers/hwmon/pmbus/Kconfig | 9 +++
> > > drivers/hwmon/pmbus/Makefile | 1 +
> > > drivers/hwmon/pmbus/xdp720.c | 123 +++++++++++++++++++++++++++++++++++
> > > 3 files changed, 133 insertions(+)
> > > create mode 100644 drivers/hwmon/pmbus/xdp720.c
> > >
> > > diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig
> > > index fc1273abe357..c419e3ecce90 100644
> > > --- a/drivers/hwmon/pmbus/Kconfig
> > > +++ b/drivers/hwmon/pmbus/Kconfig
> > > @@ -702,6 +702,15 @@ config SENSORS_XDP710
> > > This driver can also be built as a module. If so, the module will
> > > be called xdp710.
> > >
> > > +config SENSORS_XDP720
> > > + tristate "Infineon XDP720 family"
> > > + help
> > > + If you say yes here you get hardware monitoring support for Infineon
> > > + XDP720.
> > > +
> > > + This driver can also be built as a module. If so, the module will
> > > + be called xdp720.
> > > +
> > > config SENSORS_XDPE152
> > > tristate "Infineon XDPE152 family"
> > > help
> > > diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile
> > > index d6c86924f887..1cac7ccae79f 100644
> > > --- a/drivers/hwmon/pmbus/Makefile
> > > +++ b/drivers/hwmon/pmbus/Makefile
> > > @@ -68,6 +68,7 @@ obj-$(CONFIG_SENSORS_TPS546D24) += tps546d24.o
> > > obj-$(CONFIG_SENSORS_UCD9000) += ucd9000.o
> > > obj-$(CONFIG_SENSORS_UCD9200) += ucd9200.o
> > > obj-$(CONFIG_SENSORS_XDP710) += xdp710.o
> > > +obj-$(CONFIG_SENSORS_XDP720) += xdp720.o
> > > obj-$(CONFIG_SENSORS_XDPE122) += xdpe12284.o
> > > obj-$(CONFIG_SENSORS_XDPE152) += xdpe152c4.o
> > > obj-$(CONFIG_SENSORS_ZL6100) += zl6100.o
> > > diff --git a/drivers/hwmon/pmbus/xdp720.c b/drivers/hwmon/pmbus/xdp720.c
> > > new file mode 100644
> > > index 000000000000..382dc3f9ce80
> > > --- /dev/null
> > > +++ b/drivers/hwmon/pmbus/xdp720.c
> > > @@ -0,0 +1,123 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Hardware monitoring driver for Infineon XDP720 Digital eFuse Controller
> > > + *
> > > + * Copyright (c) 2026 Infineon Technologies. All rights reserved.
> > > + */
> > > +
> > > +#include <linux/i2c.h>
> > > +#include <linux/module.h>
> > > +#include <linux/init.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/of_device.h>
> > > +#include <linux/bitops.h>
> > > +#include <linux/math64.h>
> > > +#include "pmbus.h"
> > > +
> > > +/*
> > > + * The IMON resistor required to generate the system overcurrent protection.
> > > + * Arbitrary default Rimon value: 2k Ohm
> > > + */
> > > +#define XDP720_DEFAULT_RIMON 2000000000 /* 2k ohm */
> > > +#define XDP720_TELEMETRY_AVG 0xE9
> > > +
> > > +static struct pmbus_driver_info xdp720_info = {
> > > + .pages = 1,
> > > + .format[PSC_VOLTAGE_IN] = direct,
> > > + .format[PSC_VOLTAGE_OUT] = direct,
> > > + .format[PSC_CURRENT_OUT] = direct,
> > > + .format[PSC_POWER] = direct,
> > > + .format[PSC_TEMPERATURE] = direct,
> > > +
> > > + .m[PSC_VOLTAGE_IN] = 4653,
> > > + .b[PSC_VOLTAGE_IN] = 0,
> > > + .R[PSC_VOLTAGE_IN] = -2,
> > > + .m[PSC_VOLTAGE_OUT] = 4653,
> > > + .b[PSC_VOLTAGE_OUT] = 0,
> > > + .R[PSC_VOLTAGE_OUT] = -2,
> > > + /*
> > > + * Current and Power measurement depends on the RIMON (kOhm) and
> > > + * GIMON(microA/A) values.
> > > + */
> > > + .m[PSC_CURRENT_OUT] = 24668,
> > > + .b[PSC_CURRENT_OUT] = 0,
> > > + .R[PSC_CURRENT_OUT] = -4,
> > > + .m[PSC_POWER] = 4486,
> > > + .b[PSC_POWER] = 0,
> > > + .R[PSC_POWER] = -1,
> > > + .m[PSC_TEMPERATURE] = 54,
> > > + .b[PSC_TEMPERATURE] = 22521,
> > > + .R[PSC_TEMPERATURE] = -1,
> > > +
> > > + .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_PIN |
> > > + PMBUS_HAVE_TEMP | PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_INPUT |
> > > + PMBUS_HAVE_STATUS_TEMP,
> > > +};
> > > +
> > > +static int xdp720_probe(struct i2c_client *client)
> > > +{
> > > + struct pmbus_driver_info *info;
> > > + int ret;
> > > + u32 rimon;
> > > + int gimon;
> > > +
> > > + info = devm_kmemdup(&client->dev, &xdp720_info, sizeof(*info),
> > > + GFP_KERNEL);
> > > + if (!info)
> > > + return -ENOMEM;
> > > +
> > > + ret = i2c_smbus_read_word_data(client, XDP720_TELEMETRY_AVG);
> > > + if (ret < 0) {
> > > + dev_err(&client->dev, "Can't get TELEMETRY_AVG\n");
> > > + return ret;
> > > + }
> > > +
> > > + ret >>= 10; /* 10th bit of TELEMETRY_AVG REG for GIMON Value */
> > > + ret &= GENMASK(0, 0);
> > > + if (ret == 1)
> > > + gimon = 18200; /* output gain 18.2 microA/A */
> > > + else
> > > + gimon = 9100; /* output gain 9.1 microA/A */
> > > +
> > > + if (of_property_read_u32(client->dev.of_node,
> > > + "infineon,rimon-micro-ohms", &rimon))
> > > + rimon = XDP720_DEFAULT_RIMON; /* Default if not set via DT */
> > > + if (rimon == 0)
> > > + return -EINVAL;
> > > +
> > > + /* Adapt the current and power scale for each instance */
> > > + info->m[PSC_CURRENT_OUT] = DIV64_U64_ROUND_CLOSEST((u64)
> > > + info->m[PSC_CURRENT_OUT] * rimon * gimon, 1000000000000);
> > > + info->m[PSC_POWER] = DIV64_U64_ROUND_CLOSEST((u64)
> > > + info->m[PSC_POWER] * rimon * gimon, 1000000000000);
> > > +
> > > + return pmbus_do_probe(client, info);
> > > +}
> > > +
> > > +static const struct of_device_id xdp720_of_match[] = {
> > > + { .compatible = "infineon,xdp720" },
> > > + {}
> > > +};
> > > +MODULE_DEVICE_TABLE(of, xdp720_of_match);
> > > +
> > > +static const struct i2c_device_id xdp720_id[] = {
> > > + { "xdp720" },
> > > + {}
> > > +};
> > > +MODULE_DEVICE_TABLE(i2c, xdp720_id);
> > > +
> > > +static struct i2c_driver xdp720_driver = {
> > > + .driver = {
> > > + .name = "xdp720",
> > > + .of_match_table = xdp720_of_match,
> > > + },
> > > + .probe = xdp720_probe,
> > > + .id_table = xdp720_id,
> > > +};
> > > +
> > > +module_i2c_driver(xdp720_driver);
> > > +
> > > +MODULE_AUTHOR("Ashish Yadav <ashish.yadav@infineon.com>");
> > > +MODULE_DESCRIPTION("PMBus driver for Infineon XDP720 Digital eFuse Controller");
> > > +MODULE_LICENSE("GPL");
> > > +MODULE_IMPORT_NS("PMBUS");
> >
^ permalink raw reply
* [PATCH v2 4/4] ARM: dts: qcom: msm8974pro-htc-m8: add touchscreen
From: Alexandre Messier via B4 Relay @ 2026-04-06 5:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Luca Weiss, linux-arm-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, devicetree, linux-kernel,
Alexandre Messier
In-Reply-To: <20260406-m8-dts-additions-v2-0-c4c4bd50af48@me.ssier.org>
From: Alexandre Messier <alex@me.ssier.org>
Add the touchscreen device node for the HTC One (M8).
The downstream vendor kernel used an I2C frequency of 384 kHz
for this bus. Use the same value as the vendor.
Signed-off-by: Alexandre Messier <alex@me.ssier.org>
---
arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts | 36 +++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
index 2edf407db567..66ad93e7dd20 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
@@ -65,6 +65,35 @@ vreg_vph_pwr: vreg-vph-pwr {
};
};
+&blsp1_i2c2 {
+ clock-frequency = <384000>;
+
+ status = "okay";
+
+ touch@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+
+ interrupts-extended = <&tlmm 18 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&ts_int_pin>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
&blsp1_i2c3 {
clock-frequency = <384000>;
@@ -353,6 +382,13 @@ cmd-data-pins {
};
};
+ ts_int_pin: ts-int-pin-state {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
wcnss_pin_a: wcnss-pin-active-state {
bt-pins {
pins = "gpio35", "gpio43", "gpio44";
--
2.53.0
^ permalink raw reply related
* [PATCH v2 3/4] ARM: dts: qcom: msm8974pro-htc-m8: add Bluetooth pins
From: Alexandre Messier via B4 Relay @ 2026-04-06 5:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Luca Weiss, linux-arm-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, devicetree, linux-kernel,
Alexandre Messier, Konrad Dybcio
In-Reply-To: <20260406-m8-dts-additions-v2-0-c4c4bd50af48@me.ssier.org>
From: Alexandre Messier <alex@me.ssier.org>
Add the required pin configuration to enable Bluetooth.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Alexandre Messier <alex@me.ssier.org>
---
arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
index f24882dbeef3..2edf407db567 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
@@ -354,10 +354,19 @@ cmd-data-pins {
};
wcnss_pin_a: wcnss-pin-active-state {
- pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
- function = "wlan";
- drive-strength = <6>;
- bias-pull-down;
+ bt-pins {
+ pins = "gpio35", "gpio43", "gpio44";
+ function = "bt";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wlan-pins {
+ pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
+ function = "wlan";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
};
};
--
2.53.0
^ permalink raw reply related
* [PATCH v2 2/4] ARM: dts: qcom: msm8974pro-htc-m8: add NFC support
From: Alexandre Messier via B4 Relay @ 2026-04-06 5:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Luca Weiss, linux-arm-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, devicetree, linux-kernel,
Alexandre Messier
In-Reply-To: <20260406-m8-dts-additions-v2-0-c4c4bd50af48@me.ssier.org>
From: Alexandre Messier <alex@me.ssier.org>
Add the NFC chip used in the HTC One M8 to its device tree.
The downstream vendor kernel used an I2C frequency of 384 kHz
for this bus. Use the same value as the vendor.
Signed-off-by: Alexandre Messier <alex@me.ssier.org>
---
arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
index 37df271dbdeb..f24882dbeef3 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
@@ -65,6 +65,22 @@ vreg_vph_pwr: vreg-vph-pwr {
};
};
+&blsp1_i2c3 {
+ clock-frequency = <384000>;
+
+ status = "okay";
+
+ nfc@28 {
+ compatible = "nxp,pn544-i2c";
+ reg = <0x28>;
+
+ interrupts-extended = <&tlmm 144 IRQ_TYPE_LEVEL_HIGH>;
+
+ enable-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ firmware-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
&pm8941_lpg {
qcom,power-source = <1>;
--
2.53.0
^ permalink raw reply related
* [PATCH v2 0/4] Describe more hardware of the HTC One (M8)
From: Alexandre Messier via B4 Relay @ 2026-04-06 5:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Luca Weiss, linux-arm-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, devicetree, linux-kernel,
Alexandre Messier, Lee Jones, Pavel Machek, linux-leds,
Konrad Dybcio
Add hardware description for these parts of the HTC One (M8):
- Notification LEDs
- Bluetooth
- NFC
- Touchscreen
Signed-off-by: Alexandre Messier <alex@me.ssier.org>
---
Changes in v2:
- Rebased on top of 7.0-rc6
- In patch 1, change color of one LED from amber to orange.
- In patch 1, use a multicolor LED to represent the logical grouping
of the LEDs.
- In patches 2 and 4, note in the commit message the usage of same
I2C bus frequency as the downstream kernel.
- In patch 3, gather Reviewed-by tag from Konrad Dybcio.
- Link to v1: https://lore.kernel.org/r/20251007-m8-dts-additions-v1-0-53d7ab3594e7@me.ssier.org
---
Alexandre Messier (4):
ARM: dts: qcom: msm8974pro-htc-m8: add status LEDs
ARM: dts: qcom: msm8974pro-htc-m8: add NFC support
ARM: dts: qcom: msm8974pro-htc-m8: add Bluetooth pins
ARM: dts: qcom: msm8974pro-htc-m8: add touchscreen
arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts | 94 ++++++++++++++++++++++-
1 file changed, 90 insertions(+), 4 deletions(-)
---
base-commit: 7aaa8047eafd0bd628065b15757d9b48c5f9c07d
change-id: 20251007-m8-dts-additions-ac20291afa24
Best regards,
--
Alexandre Messier <alex@me.ssier.org>
^ permalink raw reply
* [PATCH v2 1/4] ARM: dts: qcom: msm8974pro-htc-m8: add status LEDs
From: Alexandre Messier via B4 Relay @ 2026-04-06 5:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Luca Weiss, linux-arm-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, devicetree, linux-kernel,
Alexandre Messier, Lee Jones, Pavel Machek, linux-leds
In-Reply-To: <20260406-m8-dts-additions-v2-0-c4c4bd50af48@me.ssier.org>
From: Alexandre Messier <alex@me.ssier.org>
Add support for the notification LEDs on the HTC One M8.
Two LEDs are available, one orange and one green. Together,
they both form a single notification source, so use a
multicolor LED node to describe this arrangement.
Cc: Lee Jones <lee@kernel.org>
Cc: Pavel Machek <pavel@kernel.org>
Cc: linux-leds@vger.kernel.org
Signed-off-by: Alexandre Messier <alex@me.ssier.org>
---
arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts | 25 +++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
index 402372834c53..37df271dbdeb 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts
@@ -3,6 +3,7 @@
#include "pm8841.dtsi"
#include "pm8941.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "HTC One (M8)";
@@ -64,6 +65,30 @@ vreg_vph_pwr: vreg-vph-pwr {
};
};
+&pm8941_lpg {
+ qcom,power-source = <1>;
+
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_MULTI>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@6 {
+ reg = <6>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@7 {
+ reg = <7>;
+ color = <LED_COLOR_ID_ORANGE>;
+ };
+ };
+};
+
&pm8941_vib {
status = "okay";
};
--
2.53.0
^ permalink raw reply related
* Re: [PATCH] dt-bindings: opp-v2: Fix example 3 CPU reg value
From: Viresh Kumar @ 2026-04-06 4:32 UTC (permalink / raw)
To: Vivian Wang
Cc: Viresh Kumar, Nishanth Menon, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-pm, devicetree,
linux-kernel
In-Reply-To: <20260403-dt-bindings-opp-v2-hex-cpu-reg-v1-1-38a4968ab515@iscas.ac.cn>
On 03-04-26, 18:34, Vivian Wang wrote:
> Example 3 is a dual-cluster example, meaning that the CPU nodes should
> have reg values 0x0, 0x1, 0x100, 0x101. The example incorrectly uses
> decimal 0, 1, 100, 101 instead, which seems unintended. Use the correct
> hexadecimal values.
>
> Even though the value doesn't change for the first two CPUs, 0 and 1 in
> example 3 are changed to 0x0 and 0x1 respectively for consistency. Other
> examples all have reg less than 10, so they have not been changed.
>
> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
> ---
> Found while trying to figure out if cpu@* unit addresses are supposed to
> be decimal or hexadecimal. This is AFAICT the only place in-tree where
> an arm/arm64 DTS uses multi-digit decimal. See also:
>
> - https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/
> - https://github.com/devicetree-org/devicetree-specification/issues/86
> ---
> Documentation/devicetree/bindings/opp/opp-v2.yaml | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/opp/opp-v2.yaml b/Documentation/devicetree/bindings/opp/opp-v2.yaml
> index 6972d76233aa..10000a758572 100644
> --- a/Documentation/devicetree/bindings/opp/opp-v2.yaml
> +++ b/Documentation/devicetree/bindings/opp/opp-v2.yaml
> @@ -172,7 +172,7 @@ examples:
> cpu@0 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> - reg = <0>;
> + reg = <0x0>;
> next-level-cache = <&L2>;
> clocks = <&clk_controller 0>;
> clock-names = "cpu";
> @@ -183,7 +183,7 @@ examples:
> cpu@1 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> - reg = <1>;
> + reg = <0x1>;
> next-level-cache = <&L2>;
> clocks = <&clk_controller 0>;
> clock-names = "cpu";
> @@ -194,7 +194,7 @@ examples:
> cpu@100 {
> compatible = "arm,cortex-a15";
> device_type = "cpu";
> - reg = <100>;
> + reg = <0x100>;
> next-level-cache = <&L2>;
> clocks = <&clk_controller 1>;
> clock-names = "cpu";
> @@ -205,7 +205,7 @@ examples:
> cpu@101 {
> compatible = "arm,cortex-a15";
> device_type = "cpu";
> - reg = <101>;
> + reg = <0x101>;
> next-level-cache = <&L2>;
> clocks = <&clk_controller 1>;
> clock-names = "cpu";
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply
* Re: [PATCH] dt-bindings: clock: qcom,kaanapali-gxclkctl: Correctly use additionalProperties
From: Taniya Das @ 2026-04-06 3:55 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, linux-clk, devicetree, linux-kernel
In-Reply-To: <20260404105436.138110-2-krzysztof.kozlowski@oss.qualcomm.com>
On 4/4/2026 4:24 PM, Krzysztof Kozlowski wrote:
> The binding does not reference any other schema, thus should use
> "additionalProperties: false" to disallow any undocumented properties.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> .../devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
--
Thanks,
Taniya Das
^ permalink raw reply
* Re: [PATCH] arm64: dts: imx{91,93}-phyboard-segin: Add peb-av-18 overlay
From: Frank Li @ 2026-04-06 2:56 UTC (permalink / raw)
To: Florijan Plohl
Cc: Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, imx, linux-arm-kernel,
devicetree, linux-kernel, upstream
In-Reply-To: <56b9e133-74b9-4e59-a40c-c7637c080fd8@norik.com>
On Fri, Apr 03, 2026 at 10:29:00AM +0200, Florijan Plohl wrote:
> Hello,
>
> On 4/2/26 15:50, Frank Li wrote:
> > On Thu, Apr 02, 2026 at 09:08:26AM +0200, Florijan Plohl wrote:
> > > Add overlay for the PEB-AV-18 adapter on phyBOARD-Segin-i.MX91/93.
> > what's means PEB-AV-18? Is it random board name?
> The PEB-AV-18 is PHYTEC designation for Audio/Video adapter modules that can
> be used to connect displays on their boards.
>
> I will improve commit message to add more such information in v2.
>
> >
> >
> > > The supported LCD is Powertip PH800480T032-ZHC19 panel (AC220).
> > >
> > > Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
> > > ---
> > > arch/arm64/boot/dts/freescale/Makefile | 4 +
> > > .../imx91-phyboard-segin-peb-av-18.dtso | 142 ++++++++++++++++++
> > > .../imx93-phyboard-segin-peb-av-18.dtso | 142 ++++++++++++++++++
> > Any difference between 91 and 93, can use one overlay file?
> >
> > Frank
>
> Can you suggest how to do so?
>
> There are imx93-pinfunc.h and imx91-pinfunc.h which are not unified
> between imx91 and imx93.
I suggest move pinmux setting to mainboard's dts files, which provide
plug adaptor header, signal should be descripted in mainboard's dts file,
which provide an unified label to overlay file.
Frank
>
> So we can only create common dtsi like so:
>
> imx91-93-phyboard-segin-peb-av-18.dtsi
>
> and still use separate dtsos:
>
> imx91-phyboard-segin-peb-av-18.dtso
> imx93-phyboard-segin-peb-av-18.dtso
>
> Is that your idea?
>
> BR,
>
> Florijan Plohl
>
> > > --
> > > 2.43.0
> > >
^ permalink raw reply
* Re: [PATCH] arm64: dts: imx8mm: imx8mp: Add DTOs for Data Modul i.MX8M Mini and Plus eDM SBC
From: Frank Li @ 2026-04-06 2:37 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, devicetree, imx, linux-kernel
In-Reply-To: <20260404201038.52093-1-marex@nabladev.com>
On Sat, Apr 04, 2026 at 10:09:08PM +0200, Marek Vasut wrote:
> 48 files changed, 3086 insertions(+), 13 deletions(-)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-cm4.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-cm7.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
The basic it is duplcated overlay file between imx8mm and imx8mp. Can you
the use the same dtso for both boards.
Addtional boards is the same, only differeence is connect signal, such gpio.
for example, you create addtional label
in main board dts.
header1_gpio: &gpio0 {
};
in addtional boards dtso
reset-gpios = <&header1_gpio>
If these addtional boards will use at imx93, imx91 ...., there will be NxM
dtso file.
Frank
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtso
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 711e36cc2c990..44385fb05c533 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -115,7 +115,81 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdps-mb-smarc-2.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
> -dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
> +
> +imx8mm-data-modul-edm-sbc-overlay-cm4-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-cm4.dtbo
> +
> +imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtbo
> +
> +imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtbo
> +
> +imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtbo
> +
> +imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo
> +
> +imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtbo
> +
> +imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtbo
> +
> +imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtbo
> +
> +imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtbo
> +
> +imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtbo
> +
> +imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtbo
> +
> +imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900-dtbs := \
> + imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtbo
> +
> +dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-cm4.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-cm4.dtbo \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtbo \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtbo \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtbo \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtbo \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtbo \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtbo \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtbo \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtbo \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtbo \
> + imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtb \
> + imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtbo
> +
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb
> @@ -237,7 +311,143 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
> DTC_FLAGS_imx8mp-cubox-m := -@
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb
> -dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
> +
> +imx8mp-data-modul-edm-sbc-overlay-cm7-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-cm7.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900-dtbs := \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902-dtbs := \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtbo
> +
> +imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902-dtbs := \
> + imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtbo
> +
> +dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-cm7.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-cm7.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtbo \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtb \
> + imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtbo
> +
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-cm4.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-cm4.dtso
> new file mode 100644
> index 0000000000000..8d681c0eff0d4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-cm4.dtso
> @@ -0,0 +1,56 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2023-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/clock/imx8mm-clock.h>
> +
> +&{/} {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + reserved-memory { /* CM4 reserved memory */
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + m_core_reserved: m_core@b7000000 {
> + reg = <0 0xb7000000 0 0x1000000>;
> + no-map;
> + };
> +
> + vdev0vring0: vdev0vring0@b8000000 {
> + reg = <0 0xb8000000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev0vring1: vdev0vring1@b8008000 {
> + reg = <0 0xb8008000 0 0x8000>;
> + no-map;
> + };
> +
> + rsc_table: rsc-table@b80ff000 {
> + reg = <0 0xb80ff000 0 0x1000>;
> + no-map;
> + };
> +
> + vdevbuffer: vdevbuffer@b8400000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0xb8400000 0 0x100000>;
> + no-map;
> + };
> + };
> +
> + imx8mm-cm4 {
> + compatible = "fsl,imx8mm-cm4";
> + clocks = <&clk IMX8MM_CLK_M4_CORE>;
> + mbox-names = "tx", "rx", "rxdb";
> + mboxes = <&mu 0 1
> + &mu 1 1
> + &mu 3 1>;
> + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;
> + syscon = <&src>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
> new file mode 100644
> index 0000000000000..a5e80383533e7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
> @@ -0,0 +1,163 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/clock/imx8mm-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "imx8mm-pinfunc.h"
> +
> +&{/} {
> + can_osc: can-osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <20000000>;
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "SGTL5000-Card";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&codec_dai>;
> + simple-audio-card,frame-master = <&codec_dai>;
> + simple-audio-card,widgets = "Headphone", "Headphone Jack";
> + simple-audio-card,routing = "Headphone Jack", "HP_OUT";
> +
> + cpu_dai: simple-audio-card,cpu {
> + sound-dai = <&sai2>;
> + };
> +
> + codec_dai: simple-audio-card,codec {
> + sound-dai = <&sgtl5000>;
> + };
> + };
> +};
> +
> +&ecspi2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + can@0 {
> + compatible = "microchip,mcp2518fd";
> + reg = <0>;
> + clocks = <&can_osc>;
> + interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
> + spi-max-frequency = <10000000>;
> + };
> +};
> +
> +&i2c4 { /* Feature connector I2C */
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + sgtl5000: codec@a {
> + #sound-dai-cells = <0>;
> + clocks = <&sai5clk 1>;
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + VDDA-supply = <&buck4_reg>;
> + VDDD-supply = <&buck5_reg>;
> + VDDIO-supply = <&buck4_reg>;
> + };
> +
> + gpio_feature: io-expander@20 {
> + compatible = "nxp,pca9554";
> + reg = <0x20>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + interrupt-parent = <&gpio5>;
> + interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
> + gpio-line-names =
> + "GPI0", "GPI1", "GPI2", "GPI3",
> + "GPO0", "GPO1", "GPO2", "GPO3";
> + };
> +
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + pagesize = <32>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_codec_mclk: codec-mclk_feature-grp {
> + fsl,pins = <
> + /* GPIO4_IO27 */
> + MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x2
> + >;
> + };
> +
> + pinctrl_sai2: sai2_feature-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x90
> + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x96
> + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x90
> + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x96
> + >;
> + };
> +};
> +
> +&pinctrl_hog_feature {
> + fsl,pins = <
> + /* GPIO5_IO03 */
> + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006
> + /* GPIO5_IO04 */
> + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006
> +
> + /* CAN_INT# */
> + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090
> + >;
> +};
> +
> +&sai2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai2>;
> + assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
> + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
> + assigned-clock-rates = <24576000>;
> + fsl,sai-asynchronous;
> + fsl,sai-bit-clock-swap;
> + fsl,sai-mclk-direction-output;
> + status = "okay";
> +};
> +
> +&spba2 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sai5clk: clock-controller@30050000 { /* SAI5 */
> + compatible = "fsl,imx8mm-sai-clock", "fsl,imx8mq-sai-clock";
> + reg = <0x30050000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
> + <&clk IMX8MM_CLK_SAI5_ROOT>;
> + clock-names = "bus", "mclk1";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_codec_mclk>;
> + assigned-clocks = <&clk IMX8MM_CLK_SAI5>,
> + <&clk IMX8MM_CLK_CLKOUT1_SEL>,
> + <&clk IMX8MM_CLK_CLKOUT2_SEL>;
> + assigned-clock-parents = <&clk IMX8MM_CLK_24M>,
> + <&clk IMX8MM_CLK_24M>,
> + <&clk IMX8MM_CLK_24M>;
> + assigned-clock-rates = <24000000>;
> + };
> +};
> +
> +&uart2 { /* RS422 J12 */
> + linux,rs485-enabled-at-boot-time;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +/* UART4 is blocked by RDC and used as CM4 console UART */
> +&uart4 { /* UART to 1-Wire J5 */
> + status = "disabled";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
> new file mode 100644
> index 0000000000000..e2eef78cfb40f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "imx8mm-pinfunc.h"
> +
> +&{/} {
> + beeper {
> + compatible = "pwm-beeper";
> + beeper-hz = <1000>;
> + pwms = <&pwm3 0 250000 0>;
> + };
> +
> + can_osc: can-osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <20000000>;
> + };
> +};
> +
> +&ecspi2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + can@0 {
> + compatible = "microchip,mcp2515";
> + reg = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_can>;
> + clocks = <&can_osc>;
> + interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
> + spi-max-frequency = <5000000>;
> + };
> +};
> +
> +&i2c4 { /* Feature connector I2C */
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio_feature: io-expander@20 {
> + compatible = "nxp,pca9554";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_expander>;
> + reg = <0x20>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + interrupt-parent = <&gpio4>;
> + interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
> + gpio-line-names =
> + "GPIO1_output", "GPIO1_input",
> + "GPIO2_output", "GPIO2_input",
> + "GPIO3_output", "GPIO3_input",
> + "PCA9511A_READY", "";
> + };
> +
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + pagesize = <32>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_can: can-feature-grp {
> + fsl,pins = <
> + /* CAN_INT# */
> + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x400000d6
> + /* CAN_RST# */
> + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x6
> + >;
> + };
> +
> + pinctrl_gpio_expander: gpio-expander-feature-grp {
> + fsl,pins = <
> + /* GPIO4_IO27 */
> + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x6
> + >;
> + };
> +
> + pinctrl_pwm3: pwm3-buzzer-feature-grp {
> + fsl,pins = <
> + /* Buzzer PWM output */
> + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x100
> + >;
> + };
> +};
> +
> +&pinctrl_hog_feature {
> + fsl,pins = <
> + /* GPIO5_IO04 */
> + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x6
> + >;
> +};
> +
> +&pwm3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm3>;
> + status = "okay";
> +};
> +
> +&uart1 { /* J500/J501 */
> + status = "okay";
> +};
> +
> +&uart2 { /* RS485 J302/J303 */
> + linux,rs485-enabled-at-boot-time;
> + uart-has-rtscts;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
> new file mode 100644
> index 0000000000000..b39532253d4dd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
> @@ -0,0 +1,102 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +&{/} {
> + hdmi-out {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con: endpoint {
> + remote-endpoint = <<9611_out>;
> + };
> + };
> + };
> +};
> +
> +&i2c3 { /* Display connector I2C */
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + lt9611_codec: hdmi-bridge@3b {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_expansion>;
> + compatible = "lontium,lt9611";
> + reg = <0x3b>;
> + interrupts-extended = <&gpio2 3 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
> + vdd-supply = <&buck5_reg>; /* X400 pin 51, +1V8_S0 */
> + vcc-supply = <&buck4_reg>; /* X400 pin 55, +3V3_S0 */
> +
> + /* Audio I2S not described */
> + #sound-dai-cells = <1>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + lt9611_a: endpoint {
> + remote-endpoint = <&mipi_dsi_bridge1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + lt9611_out: endpoint {
> + remote-endpoint = <&hdmi_con>;
> + };
> + };
> + };
> + };
> +
> + eeprom@50 {
> + compatible = "atmel,24c02";
> + reg = <0x50>;
> + pagesize = <16>;
> + };
> +};
> +
> +&iomuxc {
> + /* Free &pinctrl_panel_expansion from hog for lt9611_codec above */
> + pinctrl-0 = <&pinctrl_hog_misc>, <&pinctrl_hog_feature>,
> + <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>;
> +};
> +
> +&lcdif {
> + status = "okay";
> +};
> +
> +&mipi_dsi {
> + /* HDMI 148.5 MHz x2 (DDR) x3 (24bpp / 8) */
> + samsung,burst-clock-frequency = <891000000>;
> + samsung,esc-clock-frequency = <10000000>;
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> +
> + mipi_dsi_bridge1_out: endpoint {
> + clock-lanes = <0>;
> + data-lanes = <1 2 3 4>;
> + /* Clock and data lanes have DN/DP swapped */
> + lane-polarities = <1 1 1 1 1>;
> + remote-endpoint = <<9611_a>;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
> new file mode 100644
> index 0000000000000..4930339d0f980
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022-2026 Marek Vasut
> + */
> +
> +#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 6.3 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
> + pwm-off-delay-ms = <10>;
> + /* 3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
> + pwms = <&pwm1 0 5000000 0>;
> + status = "okay";
> +};
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <216000000>; /* RX ByteClock ~27 MHz */
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel {
> + compatible = "innolux,g070y2-l01";
> + status = "okay";
> +
> + port {
> + panel_lvds: endpoint {
> + remote-endpoint = <<9211_out_a>;
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 3.3V on this G070Y2-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 3.3V on this G070Y2-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <10000>; /* T8 */
> + off-on-delay-us = <550000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 6.3 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
> +
> + /* Always only output 3.3V on this G070Y2-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
> new file mode 100644
> index 0000000000000..a5e8db0b4557c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +
> +#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 6.3 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
> + pwm-off-delay-ms = <10>;
> + /* 3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
> + pwms = <&pwm1 0 5000000 0>;
> + status = "okay";
> +};
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <515000000>;
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel {
> + compatible = "innolux,g101ice-l01";
> + status = "okay";
> +
> + port {
> + panel_lvds: endpoint {
> + remote-endpoint = <<9211_out_a>;
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 3.3V on this G101ICE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 3.3V on this G101ICE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <10000>; /* T8 */
> + off-on-delay-us = <950000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 6.3 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
> +
> + /* Always only output 3.3V on this G101ICE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
> new file mode 100644
> index 0000000000000..46a26189f2fa0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +
> +#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 6.2 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
> + pwm-off-delay-ms = <10>;
> + /* 3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
> + pwms = <&pwm1 0 5000000 0>;
> + status = "okay";
> +};
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <470000000>;
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel {
> + compatible = "innolux,g121xce-l01";
> + status = "okay";
> +
> + port {
> + panel_lvds: endpoint {
> + remote-endpoint = <<9211_out_a>;
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 3.3V on this G121XCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 3.3V on this G121XCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <10000>; /* T8 */
> + off-on-delay-us = <1180000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 6.2 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
> +
> + /* Always only output 3.3V on this G121XCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
> new file mode 100644
> index 0000000000000..e606e9dbb098d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +
> +#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 4.6 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
> + pwm-off-delay-ms = <10>;
> + /* 4.3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
> + pwms = <&pwm1 0 5000000 0>;
> + status = "okay";
> +};
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds_a>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> +
> + lt9211_out_b: endpoint {
> + remote-endpoint = <&panel_lvds_b>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <864000000>; /* RX ByteClock ~27 MHz */
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel {
> + compatible = "innolux,g156hce-l01";
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dual-lvds-odd-pixels;
> +
> + panel_lvds_b: endpoint {
> + remote-endpoint = <<9211_out_b>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dual-lvds-even-pixels;
> +
> + panel_lvds_a: endpoint {
> + remote-endpoint = <<9211_out_a>;
> + };
> + };
> + };
> +};
> +
> +®_backlight_pwm_level { /* G156HCE-L01 can do both 3V3 and 5V IO */
> + /* Always only output 3.3V on this G156HCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level { /* G156HCE-L01 can do both 3V3 and 5V IO */
> + /* Always only output 3.3V on this G156HCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <10000>; /* T8 */
> + off-on-delay-us = <1170000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 4.6 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
> +
> + /* Always only output 3.3V on this G156HCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
> new file mode 100644
> index 0000000000000..4ed5afc4cee2c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
> @@ -0,0 +1,94 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022-2026 Marek Vasut
> + */
> +
> +#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +
> +&backlight {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_backlight>;
> + enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
> + /* 6.5 POWER ON/OFF SEQUENCE, T6 >= 10 ms */
> + post-pwm-on-delay-ms = <10>;
> + /* 6.5 POWER ON/OFF SEQUENCE, T7 >= 0 ms */
> + pwm-off-delay-ms = <10>;
> + /* 5.2 BACKLIGHT UNIT 200Hz..20kHz, value below in ns */
> + pwms = <&pwm1 0 66666 0>; /* 15 kHz = 66666ns */
> + status = "okay";
> +};
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds_a>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> +
> + lt9211_out_b: endpoint {
> + remote-endpoint = <&panel_lvds_b>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <864000000>; /* RX ByteClock ~27 MHz */
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel {
> + /* The G215HVN01 is replacement for T215HVN01, which is supported. */
> + compatible = "auo,t215hvn01";
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dual-lvds-odd-pixels;
> +
> + panel_lvds_b: endpoint {
> + remote-endpoint = <<9211_out_b>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dual-lvds-even-pixels;
> +
> + panel_lvds_a: endpoint {
> + remote-endpoint = <<9211_out_a>;
> + };
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 5V on this G215HVN01.1 panel unit. */
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 5V on this G215HVN01.1 panel unit. */
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> +};
> +
> +®_panel_vcc {
> + /* 6.5 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <40000>; /* 30.5ms <= T1 + T2 <= 60 ms */
> +
> + /* Always only output 5.0V on this G215HVN01.1 panel unit. */
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
> new file mode 100644
> index 0000000000000..a471451684295
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +
> +#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 1.5 POWER ON/OFF SEQUENCE, T4 >= 200 ms */
> + pwm-off-delay-ms = <200>;
> + /* ELECTRICAL CHARACTERISTICS, BL_ADJ Frequency 20K HZ Typ., value below in ns */
> + pwms = <&pwm1 0 50000 0>;
> + status = "okay";
> +};
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <216000000>; /* RX ByteClock ~27 MHz */
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel {
> + compatible = "multi-inno,mi0700a2t-30";
> + status = "okay";
> +
> + port {
> + panel_lvds: endpoint {
> + remote-endpoint = <<9211_out_a>;
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 3.3V on this MI0700A2T-30 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 3.3V on this MI0700A2T-30 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <200000>; /* T3 */
> + off-on-delay-us = <1450000>; /* T4 + T5 + T6 + T1 + T2 + T3 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 1.5 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <60000>; /* T1 + T2 >= 1 ms (typ. 60ms) */
> +
> + /* Always only output 3.3V on this MI0700A2T-30 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
> new file mode 100644
> index 0000000000000..830a8916bbe03
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +
> +#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 3 POWER ON/OFF SEQUENCE, T7 >= 200 ms */
> + pwm-off-delay-ms = <200>;
> + /* ELECTRICAL CHARACTERISTICS, BL_ADJ Frequency 20K HZ Typ., value below in ns */
> + pwms = <&pwm1 0 50000 0>;
> + status = "okay";
> +};
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <400000000>;
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel {
> + compatible = "multi-inno,mi1010z1t-1cp11";
> + status = "okay";
> +
> + port {
> + panel_lvds: endpoint {
> + remote-endpoint = <<9211_out_a>;
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 3.3V on this MI1010Z1T-1CP11 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 3.3V on this MI1010Z1T-1CP11 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <200000>; /* T6 */
> + off-on-delay-us = <1450000>; /* T7 + T3 + T4 + T5 + T1 + T2 + T6 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 3 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <60000>; /* T1 + T2 >= 1 ms (typ. 60ms) */
> +
> + /* Always only output 3.3V on this MI1010Z1T-1CP11 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
> new file mode 100644
> index 0000000000000..36f425234202d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
> @@ -0,0 +1,165 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +&{/} {
> + reg_backlight_en_level: regulator-backlight-en-level {
> + compatible = "regulator-gpio";
> + regulator-name = "Backlight_SEL_EN";
> + regulator-type = "voltage";
> + gpios = <&gpio_display 3 GPIO_ACTIVE_HIGH>; /* SEL_EN */
> + states = <3300000 0x0>,
> + <5000000 0x1>;
> +
> + /* Default setting: lowest supported voltage. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_backlight_pwm_level: regulator-backlight-pwm-level {
> + compatible = "regulator-gpio";
> + regulator-name = "Backlight_SEL_PWM";
> + regulator-type = "voltage";
> + gpios = <&gpio_display 2 GPIO_ACTIVE_HIGH>; /* SEL_PWM */
> + states = <3300000 0x0>,
> + <5000000 0x1>;
> +
> + /* Default setting: lowest supported voltage. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_panel_bl: regulator-panel-bl {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_backlight>;
> + regulator-name = "PANEL_BL";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio3 0 0>;
> + enable-active-high;
> + /* Used by panels which enable PWM signal before BL ON/OFF */
> + status = "disabled";
> + };
> +
> + reg_lt9211_vcc18: regulator-lt9211-vcc18 {
> + compatible = "regulator-fixed";
> + regulator-name = "LT9211_VCC18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vin-supply = <&buck5_reg>; /* X400 pin 51, +1V8_S0 */
> + };
> +};
> +
> +&i2c3 { /* Display connector I2C */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-frequency = <100000>;
> +
> + lt9211_codec: bridge@2d {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_expansion>;
> + compatible = "lontium,lt9211";
> + reg = <0x2d>;
> + interrupts-extended = <&gpio2 3 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
> + vccio-supply = <®_lt9211_vcc18>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + lt9211_a: endpoint {
> + data-lanes = <1 2 3 4>;
> + remote-endpoint = <&mipi_dsi_bridge1_out>;
> + };
> + };
> + };
> + };
> +
> + gpio_display: io-expander@41 {
> + compatible = "nxp,pca9536";
> + reg = <0x41>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-line-names = "SEL_12V", "SEL_5V", "SEL_PWM", "SEL_EN";
> + };
> +
> + eeprom@50 {
> + compatible = "atmel,24c02";
> + reg = <0x50>;
> + pagesize = <16>;
> + };
> +};
> +
> +&iomuxc {
> + /* Free &pinctrl_panel_expansion from hog for lt9211_codec above */
> + pinctrl-0 = <&pinctrl_hog_misc>, <&pinctrl_hog_feature>,
> + <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>;
> +};
> +
> +&lcdif {
> + status = "okay";
> +};
> +
> +&mipi_dsi {
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> +
> + mipi_dsi_bridge1_out: endpoint {
> + clock-lanes = <0>;
> + data-lanes = <1 2 3 4>;
> + /* Clock and data lanes have DN/DP swapped */
> + lane-polarities = <1 1 1 1 1>;
> + remote-endpoint = <<9211_a>;
> + };
> + };
> + };
> +};
> +
> +&pwm1 {
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + compatible = "regulator-gpio";
> + regulator-type = "voltage";
> + enable-gpios = <&gpio3 6 0>;
> + enable-active-high;
> + status = "okay";
> +
> + /*
> + * AP63300 voltage divider settings:
> + * R1=16k2
> + * R2=5k23 with optional series Rs=7k68 (5V) or Rt=1k5 (12V)
> + *
> + * 1 / Rx = (1 / R2) [ + (1 / Rs)][ + (1 / Rt)]
> + * Vout = 0.8 * ((R1 / Rx) + 1)
> + */
> + gpios = <&gpio_display 1 GPIO_ACTIVE_HIGH>, /* 5V */
> + <&gpio_display 0 GPIO_ACTIVE_HIGH>; /* 12V */
> + states = <3300000 0x0>,
> + <5000000 0x1>,
> + <12000000 0x2>,
> + <3900000 0x3>;
> +
> + /* Default setting: lowest supported voltage. */
> + gpios-states = <0 0>; /* Default GPIO state is LOW/LOW, so 3V3 out */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtso
> new file mode 100644
> index 0000000000000..14038215f298c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtso
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2023-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +&fec1 {
> + phy-handle = <&fec1_phy_ath>;
> +};
> +
> +&fec1_phy_ath {
> + status = "okay";
> +};
> +
> +&fec1_phy_bcm {
> + status = "disabled";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> index 472c584fb3bd2..d695ea0643e32 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> @@ -30,11 +30,8 @@ memory@40000000 {
>
> backlight: backlight {
> compatible = "pwm-backlight";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_panel_backlight>;
> brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
> default-brightness-level = <7>;
> - enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
> pwms = <&pwm1 0 5000000 0>;
> /* Disabled by default, unless display board plugged in. */
> status = "disabled";
> @@ -66,7 +63,6 @@ reg_panel_vcc: regulator-panel-vcc {
> regulator-name = "PANEL_VCC";
> regulator-min-microvolt = <5000000>;
> regulator-max-microvolt = <5000000>;
> - gpio = <&gpio3 6 0>;
> enable-active-high;
> /* Disabled by default, unless display board plugged in. */
> status = "disabled";
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-cm7.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-cm7.dtso
> new file mode 100644
> index 0000000000000..21e2a8c0bab0a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-cm7.dtso
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2023-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/clock/imx8mp-clock.h>
> +
> +&{/} {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + reserved-memory { /* CM7 reserved memory */
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + m_core_reserved: m_core@54000000 {
> + reg = <0 0x54000000 0 0x1000000>;
> + no-map;
> + };
> +
> + vdev0vring0: vdev0vring0@55000000 {
> + reg = <0 0x55000000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev0vring1: vdev0vring1@55008000 {
> + reg = <0 0x55008000 0 0x8000>;
> + no-map;
> + };
> +
> + rsc_table: rsc-table@550ff000 {
> + reg = <0 0x550ff000 0 0x1000>;
> + no-map;
> + };
> +
> + vdevbuffer: vdevbuffer@55400000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0x55400000 0 0x100000>;
> + no-map;
> + };
> + };
> +
> + imx8mp-cm7 {
> + compatible = "fsl,imx8mp-cm7-mmio";
> + clocks = <&clk IMX8MP_CLK_M7_CORE>;
> + fsl,iomuxc-gpr = <&gpr>;
> + mbox-names = "tx", "rx", "rxdb";
> + mboxes = <&mu 0 1
> + &mu 1 1
> + &mu 3 1>;
> + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;
> + syscon = <&src>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
> new file mode 100644
> index 0000000000000..0f70eb5086a03
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
> @@ -0,0 +1,151 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/clock/imx8mp-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "imx8mp-pinfunc.h"
> +
> +&{/} {
> + can_osc: can-osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <20000000>;
> + };
> +
> + sound-fio {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "SGTL5000-FIO1";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&codec_dai_fio>;
> + simple-audio-card,frame-master = <&codec_dai_fio>;
> + simple-audio-card,widgets = "Headphone", "Headphone Jack";
> + simple-audio-card,routing = "Headphone Jack", "HP_OUT";
> +
> + cpu_dai_fio: simple-audio-card,cpu {
> + sound-dai = <&sai2>;
> + };
> +
> + codec_dai_fio: simple-audio-card,codec {
> + sound-dai = <&sgtl5000_fio>;
> + };
> + };
> +};
> +
> +&ecspi2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + can@0 {
> + compatible = "microchip,mcp2518fd";
> + reg = <0>;
> + clocks = <&can_osc>;
> + interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_LOW>;
> + spi-max-frequency = <10000000>;
> + };
> +};
> +
> +&i2c2 { /* Feature connector I2C */
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + sgtl5000_fio: codec@a {
> + #sound-dai-cells = <0>;
> + clocks = <&sai5clk 1>;
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + VDDA-supply = <&buck4>;
> + VDDD-supply = <&buck5>;
> + VDDIO-supply = <&buck4>;
> + };
> +
> + gpio_feature: io-expander@20 {
> + compatible = "nxp,pca9554";
> + reg = <0x20>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + interrupt-parent = <&gpio5>;
> + interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
> + gpio-line-names =
> + "GPI0", "GPI1", "GPI2", "GPI3",
> + "GPO0", "GPO1", "GPO2", "GPO3";
> + };
> +
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + pagesize = <32>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_codec_mclk: codec-mclk_feature-grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0xd6
> + >;
> + };
> +
> + sai2-grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
> + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
> + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
> + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
> + >;
> + };
> +
> + uart1-grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x49
> + MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x49
> + MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x49
> + >;
> + };
> +};
> +
> +&sai2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai2>;
> + assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
> + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
> + assigned-clock-rates = <24576000>;
> + fsl,sai-asynchronous;
> + fsl,sai-mclk-direction-output;
> + status = "okay";
> +};
> +
> +&spba5 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sai5clk: clock-controller@30c50000 {
> + compatible = "fsl,imx8mp-sai-clock", "fsl,imx8mq-sai-clock";
> + reg = <0x30c50000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
> + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>;
> + clock-names = "bus", "mclk1";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_codec_mclk>;
> + status = "okay";
> + };
> +};
> +
> +&uart2 { /* RS422 J12 */
> + linux,rs485-enabled-at-boot-time;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +/* UART4 is blocked by RDC and used as CM4 console UART */
> +&uart4 { /* UART to 1-Wire J5 */
> + status = "disabled";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
> new file mode 100644
> index 0000000000000..0270443c667e3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
> @@ -0,0 +1,107 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "imx8mp-pinfunc.h"
> +
> +&{/} {
> + can_osc: can-osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <20000000>;
> + };
> +};
> +
> +&ecspi2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + can@0 {
> + compatible = "microchip,mcp2515";
> + reg = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_can>;
> + clocks = <&can_osc>;
> + interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_LOW>;
> + spi-max-frequency = <5000000>;
> + };
> +};
> +
> +&i2c2 { /* Feature connector I2C */
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio_feature: io-expander@20 {
> + compatible = "nxp,pca9554";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_expander>;
> + reg = <0x20>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + interrupt-parent = <&gpio4>;
> + interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
> + gpio-line-names =
> + "GPIO1_output", "GPIO1_input",
> + "GPIO2_output", "GPIO2_input",
> + "GPIO3_output", "GPIO3_input",
> + "PCA9511A_READY", "";
> + };
> +
> + eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + pagesize = <32>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_can: can-feature-grp {
> + fsl,pins = <
> + /* CAN_INT# */
> + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x400000d6
> + >;
> + };
> +
> + pinctrl_gpio_expander: gpio-expander-feature-grp {
> + fsl,pins = <
> + /* GPIO4_IO27 */
> + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6
> + >;
> + };
> +};
> +
> +&pinctrl_sai2 {
> + fsl,pins = <
> + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
> + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
> + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
> + >;
> +};
> +
> +&pinctrl_hog_feature {
> + fsl,pins = <
> + /* GPIO5_IO03 */
> + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40000006
> + /* GPIO5_IO04 */
> + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40000006
> + >;
> +};
> +
> +&uart1 { /* J500/J501 */
> + status = "okay";
> +};
> +
> +&uart2 { /* RS485 J302/J303 */
> + linux,rs485-enabled-at-boot-time;
> + uart-has-rtscts;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
> new file mode 100644
> index 0000000000000..3b5da71273c09
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
> @@ -0,0 +1,102 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +&{/} {
> + hdmi-out {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con: endpoint {
> + remote-endpoint = <<9611_out>;
> + };
> + };
> + };
> +};
> +
> +&i2c2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + lt9611_codec: hdmi-bridge@3b {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_expansion>;
> + compatible = "lontium,lt9611";
> + reg = <0x3b>;
> + interrupts-extended = <&gpio4 19 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
> + vdd-supply = <&buck5>; /* X400 pin 51, +1V8_S0 */
> + vcc-supply = <&buck4>; /* X400 pin 55, +3V3_S0 */
> +
> + /* Audio I2S not described */
> + #sound-dai-cells = <1>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + lt9611_a: endpoint {
> + remote-endpoint = <&mipi_dsi_bridge1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + lt9611_out: endpoint {
> + remote-endpoint = <&hdmi_con>;
> + };
> + };
> + };
> + };
> +
> + eeprom@50 {
> + compatible = "atmel,24c02";
> + reg = <0x50>;
> + pagesize = <16>;
> + };
> +};
> +
> +&iomuxc {
> + /* Free &pinctrl_panel_expansion from hog for lt9611_codec above */
> + pinctrl-0 = <&pinctrl_hog_misc>, <&pinctrl_hog_feature>,
> + <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>;
> +};
> +
> +&lcdif1 {
> + status = "okay";
> +};
> +
> +&mipi_dsi {
> + /* HDMI 148.5 MHz x2 (DDR) x3 (24bpp / 8) */
> + samsung,burst-clock-frequency = <891000000>;
> + samsung,esc-clock-frequency = <10000000>;
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> +
> + mipi_dsi_bridge1_out: endpoint {
> + clock-lanes = <0>;
> + data-lanes = <1 2 3 4>;
> + /* Clock and data lanes have DN/DP swapped */
> + lane-polarities = <1 1 1 1 1>;
> + remote-endpoint = <<9611_a>;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
> new file mode 100644
> index 0000000000000..78b5557e870a2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi"
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <216000000>;
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel_lvds {
> + remote-endpoint = <<9211_out_a>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
> new file mode 100644
> index 0000000000000..28e94fe0cdd63
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi"
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <515000000>;
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel_lvds {
> + remote-endpoint = <<9211_out_a>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
> new file mode 100644
> index 0000000000000..a8918b5bc8d71
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi"
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <470000000>;
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel_lvds {
> + remote-endpoint = <<9211_out_a>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
> new file mode 100644
> index 0000000000000..673a574c6f3ea
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
> @@ -0,0 +1,40 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi"
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds_a>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> +
> + lt9211_out_b: endpoint {
> + remote-endpoint = <&panel_lvds_b>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <864000000>;
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel_lvds_a {
> + remote-endpoint = <<9211_out_a>;
> +};
> +
> +&panel_lvds_b {
> + remote-endpoint = <<9211_out_b>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
> new file mode 100644
> index 0000000000000..5e3fc1ca1bf16
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
> @@ -0,0 +1,40 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi"
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds_a>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> +
> + lt9211_out_b: endpoint {
> + remote-endpoint = <&panel_lvds_b>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <864000000>;
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel_lvds_a {
> + remote-endpoint = <<9211_out_a>;
> +};
> +
> +&panel_lvds_b {
> + remote-endpoint = <<9211_out_b>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
> new file mode 100644
> index 0000000000000..443b3b3132372
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi"
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <216000000>;
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel_lvds {
> + remote-endpoint = <<9211_out_a>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
> new file mode 100644
> index 0000000000000..c979cf3a9ae65
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi"
> +
> +<9211_codec {
> + ports {
> + port@2 {
> + reg = <2>;
> +
> + lt9211_out_a: endpoint {
> + remote-endpoint = <&panel_lvds>;
> + };
> + };
> + };
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <400000000>;
> + samsung,esc-clock-frequency = <10000000>;
> +};
> +
> +&panel_lvds {
> + remote-endpoint = <<9211_out_a>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
> new file mode 100644
> index 0000000000000..4fcb553f7c669
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
> @@ -0,0 +1,172 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +&{/} {
> + reg_backlight_en_level: regulator-backlight-en-level {
> + compatible = "regulator-gpio";
> + regulator-name = "Backlight_SEL_EN";
> + regulator-type = "voltage";
> + gpios = <&gpio_display 3 GPIO_ACTIVE_HIGH>; /* SEL_EN */
> + states = <3300000 0x0>,
> + <5000000 0x1>;
> +
> + /* Default setting: lowest supported voltage. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_backlight_pwm_level: regulator-backlight-pwm-level {
> + compatible = "regulator-gpio";
> + regulator-name = "Backlight_SEL_PWM";
> + regulator-type = "voltage";
> + gpios = <&gpio_display 2 GPIO_ACTIVE_HIGH>; /* SEL_PWM */
> + states = <3300000 0x0>,
> + <5000000 0x1>;
> +
> + /* Default setting: lowest supported voltage. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_panel_bl_supply: regulator-panel-bl-supply {
> + compatible = "regulator-fixed";
> + regulator-name = "BKLT0";
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + };
> +
> + reg_panel_bl: regulator-panel-bl {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_backlight>;
> + regulator-name = "PANEL_BL";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio3 0 0>;
> + enable-active-high;
> + vin-supply = <®_panel_bl_supply>;
> + /* Used by panels which enable PWM signal before BL ON/OFF */
> + status = "disabled";
> + };
> +
> + reg_lt9211_vcc18: regulator-lt9211-vcc18 {
> + compatible = "regulator-fixed";
> + regulator-name = "LT9211_VCC18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vin-supply = <&buck5>; /* X400 pin 51, +1V8_S0 */
> + };
> +};
> +
> +&i2c2 { /* Display connector I2C */
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + lt9211_codec: bridge@2d {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_expansion>;
> + compatible = "lontium,lt9211";
> + reg = <0x2d>;
> + interrupts-extended = <&gpio4 19 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
> + vccio-supply = <®_lt9211_vcc18>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + lt9211_a: endpoint {
> + data-lanes = <1 2 3 4>;
> + remote-endpoint = <&mipi_dsi_bridge1_out>;
> + };
> + };
> + };
> + };
> +
> + gpio_display: io-expander@41 {
> + compatible = "nxp,pca9536";
> + reg = <0x41>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-line-names = "SEL_12V", "SEL_5V", "SEL_PWM", "SEL_EN";
> + };
> +
> + eeprom@50 {
> + compatible = "atmel,24c02";
> + reg = <0x50>;
> + pagesize = <16>;
> + };
> +};
> +
> +&iomuxc {
> + /* Free &pinctrl_panel_expansion from hog for lt9211_codec above */
> + pinctrl-0 = <&pinctrl_hog_misc>, <&pinctrl_hog_feature>,
> + <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>;
> +};
> +
> +&lcdif1 {
> + status = "okay";
> +};
> +
> +&mipi_dsi {
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> +
> + mipi_dsi_bridge1_out: endpoint {
> + clock-lanes = <0>;
> + data-lanes = <1 2 3 4>;
> + /* Clock and data lanes have DN/DP swapped */
> + lane-polarities = <1 1 1 1 1>;
> + remote-endpoint = <<9211_a>;
> + };
> + };
> + };
> +};
> +
> +&pwm1 {
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + compatible = "regulator-gpio";
> + regulator-type = "voltage";
> + enable-gpios = <&gpio3 6 0>;
> + enable-active-high;
> + status = "okay";
> +
> + /*
> + * AP63300 voltage divider settings:
> + * R1=16k2
> + * R2=5k23 with optional series Rs=7k68 (5V) or Rt=1k5 (12V)
> + *
> + * 1 / Rx = (1 / R2) [ + (1 / Rs)][ + (1 / Rt)]
> + * Vout = 0.8 * ((R1 / Rx) + 1)
> + */
> + gpios = <&gpio_display 1 GPIO_ACTIVE_HIGH>, /* 5V */
> + <&gpio_display 0 GPIO_ACTIVE_HIGH>; /* 12V */
> + states = <3300000 0x0>,
> + <5000000 0x1>,
> + <12000000 0x2>,
> + <3900000 0x3>;
> +
> + /* Default setting: lowest supported voltage. */
> + gpios-states = <0 0>; /* Default GPIO state is LOW/LOW, so 3V3 out */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtso
> new file mode 100644
> index 0000000000000..b6bd41f10de6b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtso
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi"
> +
> +&media_blk_ctrl {
> + /*
> + * The G070Y2-L01 panel requires 29.5 MHz LVDS clock.
> + * Set IMX8MP_VIDEO_PLL1 to 206.5 MHz , since 206.5 MHz / 7 = 29.5 MHz .
> + */
> + assigned-clock-rates = <500000000>, <200000000>,
> + <0>, <0>, <500000000>, <206500000>;
> +};
> +
> +&ldb_lvds_ch1 {
> + remote-endpoint = <&panel_lvds>;
> +};
> +
> +&panel_lvds {
> + remote-endpoint = <&ldb_lvds_ch1>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtso
> new file mode 100644
> index 0000000000000..4f80da399b7f2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtso
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi"
> +
> +&media_blk_ctrl {
> + /*
> + * The G101ICE-L01 panel requires 71.1 MHz LVDS clock.
> + * Set IMX8MP_VIDEO_PLL1 to 497.7 MHz , since 497.7 MHz / 7 = 71.1 MHz .
> + */
> + assigned-clock-rates = <500000000>, <200000000>,
> + <0>, <0>, <500000000>, <497700000>;
> +};
> +
> +&ldb_lvds_ch1 {
> + remote-endpoint = <&panel_lvds>;
> +};
> +
> +&panel_lvds {
> + remote-endpoint = <&ldb_lvds_ch1>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtso
> new file mode 100644
> index 0000000000000..7f2ad9f41882c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtso
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024 Wael Karman <wkarman@data-modul.com>
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi"
> +
> +&media_blk_ctrl {
> + /*
> + * The G121XCE-L01 panel requires 64.9 MHz LVDS clock.
> + * Set IMX8MP_VIDEO_PLL1 to 454.3 MHz , since 454.3 MHz / 7 = 64.9 MHz .
> + */
> + assigned-clock-rates = <500000000>, <200000000>,
> + <0>, <0>, <500000000>, <454300000>;
> +};
> +
> +&ldb_lvds_ch1 {
> + remote-endpoint = <&panel_lvds>;
> +};
> +
> +&panel_lvds {
> + remote-endpoint = <&ldb_lvds_ch1>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtso
> new file mode 100644
> index 0000000000000..b438bcfceda26
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtso
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi"
> +
> +&media_blk_ctrl {
> + /*
> + * The G156HCE-L01 panel requires 141.86 MHz LVDS clock.
> + * Set IMX8MP_VIDEO_PLL1 to 993.2 MHz , since 993.2 MHz / 7 = 141.86 MHz .
> + */
> + assigned-clock-rates = <500000000>, <200000000>,
> + <0>, <0>, <500000000>, <993020000>;
> +};
> +
> +&ldb_lvds_ch0 {
> + remote-endpoint = <&panel_lvds_b>;
> +};
> +
> +&ldb_lvds_ch1 {
> + remote-endpoint = <&panel_lvds_a>;
> +};
> +
> +&panel_lvds_a {
> + remote-endpoint = <&ldb_lvds_ch1>;
> +};
> +
> +&panel_lvds_b {
> + remote-endpoint = <&ldb_lvds_ch0>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtso
> new file mode 100644
> index 0000000000000..4a1dad3e75394
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtso
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi"
> +
> +&media_blk_ctrl {
> + /*
> + * The G215HVN01 panel requires 148.8 MHz LVDS clock.
> + * Set IMX8MP_VIDEO_PLL1 to 1041.6 MHz , since 1041.6 MHz / 7 = 148.8 MHz .
> + */
> + assigned-clock-rates = <500000000>, <200000000>,
> + <0>, <0>, <500000000>, <1041600000>;
> +};
> +
> +&ldb_lvds_ch0 {
> + remote-endpoint = <&panel_lvds_b>;
> +};
> +
> +&ldb_lvds_ch1 {
> + remote-endpoint = <&panel_lvds_a>;
> +};
> +
> +&panel_lvds_a {
> + remote-endpoint = <&ldb_lvds_ch1>;
> +};
> +
> +&panel_lvds_b {
> + remote-endpoint = <&ldb_lvds_ch0>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtso
> new file mode 100644
> index 0000000000000..93cecbe521188
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtso
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi"
> +
> +&media_blk_ctrl {
> + /*
> + * The MI0700A2T-30 panel requires 33 MHz LVDS clock.
> + * Set IMX8MP_VIDEO_PLL1 to 231 MHz , since 231 MHz / 7 = 33 MHz .
> + */
> + assigned-clock-rates = <500000000>, <200000000>,
> + <0>, <0>, <500000000>, <231000000>;
> +};
> +
> +&ldb_lvds_ch1 {
> + remote-endpoint = <&panel_lvds>;
> +};
> +
> +&panel_lvds {
> + remote-endpoint = <&ldb_lvds_ch1>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtso
> new file mode 100644
> index 0000000000000..65050c616155b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtso
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +
> +#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
> +#include "imx8mp-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi"
> +
> +&media_blk_ctrl {
> + /*
> + * The MI1010Z1T-1CP11 panel requires 51.2 MHz LVDS clock.
> + * Set IMX8MP_VIDEO_PLL1 to 358.4 MHz , since 358.4 MHz / 7 = 51.2 MHz .
> + */
> + assigned-clock-rates = <500000000>, <200000000>,
> + <0>, <0>, <500000000>, <358400000>;
> +};
> +
> +&ldb_lvds_ch1 {
> + remote-endpoint = <&panel_lvds>;
> +};
> +
> +&panel_lvds {
> + remote-endpoint = <&ldb_lvds_ch1>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtso
> new file mode 100644
> index 0000000000000..427585b78e45d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtso
> @@ -0,0 +1,41 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +&{/} {
> + reg_panel_vcc_raw: regulator-panel-vcc-raw {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_vcc_reg>;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-name = "PANEL_VCC";
> + };
> +};
> +
> +&panel {
> + power-supply = <®_panel_vcc_raw>;
> +};
> +
> +®_backlight_en_level {
> + status = "disabled";
> +};
> +
> +®_backlight_pwm_level {
> + status = "disabled";
> +};
> +
> +®_panel_bl_supply {
> + status = "disabled";
> +};
> +
> +®_panel_bl {
> + gpio = <&gpio3 0 0>;
> +};
> +
> +®_panel_vcc {
> + status = "disabled";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtso
> new file mode 100644
> index 0000000000000..a21fea27e0b41
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtso
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +®_panel_bl {
> + gpio = <&gpio3 0 0>;
> +};
> +
> +®_panel_vcc {
> + enable-gpios = <&gpio3 6 0>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi
> new file mode 100644
> index 0000000000000..5a184b2ca1a59
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +&{/} {
> + reg_backlight_en_level: regulator-backlight-en-level {
> + compatible = "regulator-gpio";
> + regulator-name = "Backlight_SEL_EN";
> + regulator-type = "voltage";
> + gpios = <&gpiolvds 5 GPIO_ACTIVE_HIGH>; /* SEL_EN */
> + states = <3300000 0x0>,
> + <5000000 0x1>;
> +
> + /* Default setting: lowest supported voltage. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_backlight_pwm_level: regulator-backlight-pwm-level {
> + compatible = "regulator-gpio";
> + regulator-name = "Backlight_SEL_PWM";
> + regulator-type = "voltage";
> + gpios = <&gpiolvds 4 GPIO_ACTIVE_HIGH>; /* SEL_PWM */
> + states = <3300000 0x0>,
> + <5000000 0x1>;
> +
> + /* Default setting: lowest supported voltage. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_panel_bl_supply: regulator-panel-bl-supply {
> + compatible = "regulator-gpio";
> + regulator-type = "voltage";
> + regulator-name = "PANEL_BL_SUPPLY";
> + enable-gpios = <&gpiolvds 0 0>;
> + enable-active-high;
> + status = "okay";
> +
> + /*
> + * MP2328 voltage divider settings:
> + * R1=51k1
> + * R2=5k62 with optional series Rs=2k21 (12V)
> + *
> + * 1 / Rx = (1 / R2) [ + (1 / Rs)][ + (1 / Rt)]
> + * Vout = 0.5 + ((R1 / Rx) * 0.5)
> + */
> + gpios = <&gpiolvds 1 GPIO_ACTIVE_HIGH>; /* 12V */
> + states = <5000000 0x0>,
> + <12000000 0x1>;
> +
> + /* Default setting: lowest supported voltage. */
> + gpios-states = <1>; /* Default GPIO state is HIGH, so 12V0 out */
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + };
> +
> + reg_panel_bl: regulator-panel-bl {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_backlight>;
> + regulator-name = "PANEL_BL";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpiowifi 0 0>;
> + enable-active-high;
> + vin-supply = <®_panel_bl_supply>;
> + /* Used by panels which enable PWM signal before BL ON/OFF */
> + status = "disabled";
> + };
> +};
> +
> +&lcdif2 {
> + status = "okay";
> +};
> +
> +&lvds_bridge {
> + status = "okay";
> +};
> +
> +&pwm1 {
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + compatible = "regulator-gpio";
> + regulator-type = "voltage";
> + enable-gpios = <&gpiowifi 4 0>;
> + enable-active-high;
> + status = "okay";
> +
> + /*
> + * MP2328 voltage divider settings:
> + * R1=51k1
> + * R2=9k09 with optional series Rs=5k62 (5V) or Rt=2k21 (12V)
> + *
> + * 1 / Rx = (1 / R2) [ + (1 / Rs)][ + (1 / Rt)]
> + * Vout = 0.5 + ((R1 / Rx) * 0.5)
> + */
> + gpios = <&gpiolvds 2 GPIO_ACTIVE_HIGH>, /* 5V */
> + <&gpiolvds 3 GPIO_ACTIVE_HIGH>; /* 12V */
> + states = <3300000 0x0>,
> + <5000000 0x1>,
> + <12000000 0x2>,
> + <14000000 0x3>;
> +
> + /* Default setting: lowest supported voltage. */
> + gpios-states = <0 0>; /* Default GPIO state is LOW/LOW, so 3V3 out */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtso
> new file mode 100644
> index 0000000000000..ec861aa64541e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtso
> @@ -0,0 +1,97 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2023-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include "imx8mp-pinfunc.h"
> +
> +&eeprom900 {
> + status = "okay";
> +};
> +
> +&eeprom902 {
> + status = "disabled";
> +};
> +
> +&eqos { /* First ethernet */
> + phy-handle = <&phy_eqos_ath>;
> +};
> +
> +&fec { /* Second ethernet */
> + /* pinctrl_wifi is ENET2_INT# */
> + pinctrl-0 = <&pinctrl_fec &pinctrl_wifi>;
> + phy-handle = <&phy_fec_ath>;
> +};
> +
> +&gpiolvds {
> + status = "disabled";
> +};
> +
> +/*
> + * External pull ups on R242 and R243 on I2C2_SCL_3V3 and I2C2_SDA_3V3
> + * are not populated on this early board revision, activate in-SoC pull
> + * up resistors instead to work around the missing external pull ups.
> + */
> +&pinctrl_i2c2 {
> + fsl,pins = <
> + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c4
> + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c4
> + >;
> +};
> +
> +&pinctrl_i2c2_gpio {
> + fsl,pins = <
> + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c4
> + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c4
> + >;
> +};
> +
> +&pcie_phy {
> + status = "disabled";
> +};
> +
> +&pcie {
> + status = "disabled";
> +};
> +
> +&phy_eqos_ath {
> + /*
> + * The software support for combination of EEE capable PHY and EEE
> + * capable MAC is so far missing from the Linux kernel. By default,
> + * the AR8035 PHY does enable EEE functionality on the PHY side,
> + * while the EQoS/DWMAC MAC expects to handle the EEE functionality
> + * on the MAC side. Because the Linux kernel is currently unable to
> + * align EEE configuration of the PHY and MAC, enabling EEE leads
> + * to unreliable link. Disable EEE until the kernel support is in
> + * place.
> + */
> + eee-broken-100tx;
> + eee-broken-1000t;
> + status = "okay";
> +};
> +
> +&phy_eqos_bcm {
> + status = "disabled";
> +};
> +
> +&phy_fec_ath {
> + status = "okay";
> +};
> +
> +&phy_fec_bcm {
> + status = "disabled";
> +};
> +
> +®_pcie0 {
> + status = "disabled";
> +};
> +
> +&tpm {
> + status = "disabled";
> +};
> +
> +&uart4 {
> + status = "disabled";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtso
> new file mode 100644
> index 0000000000000..0141b5d77c6bd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtso
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2024-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include "imx8mp-pinfunc.h"
> +
> +&pinctrl_hog_misc {
> + fsl,pins = <
> + /* ENET_WOL# -- shared by both PHYs */
> + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000090
> +
> + /* PG_V_IN_VAR# */
> + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000
> + /* CSI2_PD_1V8 */
> + MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0
> + /* CSI2_RESET_1V8# */
> + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0
> +
> + /* DIS_USB_DN1 */
> + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0
> + /* DIS_USB_DN2 */
> + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0
> +
> + /* EEPROM_WP_1V8# */
> + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x100
> + /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
> + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0
> + /* GRAPHICS_PRSNT_1V8# */
> + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000
> +
> + /* CLK_CCM_CLKO1_3V3 */
> + MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10
> + >;
> +};
> +
> +&pinctrl_pcie0 {
> + fsl,pins = <
> + /* M2_PCIE_RST# */
> + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
> + /* M2_W_DISABLE1_1V8# */
> + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2
> + /* M2_W_DISABLE2_1V8# */
> + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2
> + /* CLK_M2_32K768 */
> + MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14
> + /* M2_PCIE_WAKE# */
> + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140
> + /* M2_PCIE_CLKREQ# */
> + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61
> + >;
> +};
> +
> +&pinctrl_uart4 {
> + fsl,pins = <
> + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
> + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
> + >;
> +};
> +
> +&gpiowifi {
> + status = "disabled";
> +};
> +
> +&uart4 {
> + status = "disabled";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi
> new file mode 100644
> index 0000000000000..d7df9454c39a4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 6.3 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
> + pwm-off-delay-ms = <10>;
> + /* 3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
> + pwms = <&pwm1 0 5000000 0>;
> + status = "okay";
> +};
> +
> +&panel {
> + compatible = "innolux,g070y2-l01";
> + status = "okay";
> +
> + port {
> + panel_lvds: endpoint {
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 3.3V on this G070Y2-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 3.3V on this G070Y2-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <10000>; /* T8 */
> + off-on-delay-us = <550000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 6.3 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
> +
> + /* Always only output 3.3V on this G070Y2-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi
> new file mode 100644
> index 0000000000000..673cb77caaf2c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 6.3 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
> + pwm-off-delay-ms = <10>;
> + /* 3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
> + pwms = <&pwm1 0 5000000 0>;
> + status = "okay";
> +};
> +
> +&panel {
> + compatible = "innolux,g101ice-l01";
> + status = "okay";
> +
> + port {
> + panel_lvds: endpoint {
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 3.3V on this G101ICE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 3.3V on this G101ICE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <10000>; /* T8 */
> + off-on-delay-us = <950000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 6.3 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
> +
> + /* Always only output 3.3V on this G101ICE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi
> new file mode 100644
> index 0000000000000..2be8b35b5c185
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024 Wael Karman <wkarman@data-modul.com>
> + */
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 6.2 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
> + pwm-off-delay-ms = <10>;
> + /* 3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
> + pwms = <&pwm1 0 5000000 0>;
> + status = "okay";
> +};
> +
> +&panel {
> + compatible = "innolux,g121xce-l01";
> + status = "okay";
> +
> + port {
> + panel_lvds: endpoint {
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 3.3V on this G121XCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 3.3V on this G121XCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <10000>; /* T8 */
> + off-on-delay-us = <1180000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 6.2 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
> +
> + /* Always only output 3.3V on this G121XCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi
> new file mode 100644
> index 0000000000000..bff5f5f99321a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi
> @@ -0,0 +1,66 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2023-2026 Marek Vasut
> + */
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 4.6 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
> + pwm-off-delay-ms = <10>;
> + /* 4.3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
> + pwms = <&pwm1 0 5000000 0>;
> + status = "okay";
> +};
> +
> +&panel {
> + compatible = "innolux,g156hce-l01";
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dual-lvds-odd-pixels;
> +
> + panel_lvds_b: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dual-lvds-even-pixels;
> +
> + panel_lvds_a: endpoint {
> + };
> + };
> + };
> +};
> +
> +®_backlight_pwm_level { /* G156HCE-L01 can do both 3V3 and 5V IO */
> + /* Always only output 3.3V on this G156HCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level { /* G156HCE-L01 can do both 3V3 and 5V IO */
> + /* Always only output 3.3V on this G156HCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <10000>; /* T8 */
> + off-on-delay-us = <1170000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 4.6 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
> +
> + /* Always only output 3.3V on this G156HCE-L01 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi
> new file mode 100644
> index 0000000000000..8b48bae448f30
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi
> @@ -0,0 +1,66 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022-2026 Marek Vasut
> + */
> +
> +&backlight {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_backlight>;
> + enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
> + power-supply = <®_panel_bl_supply>;
> + /* 6.5 POWER ON/OFF SEQUENCE, T6 >= 10 ms */
> + post-pwm-on-delay-ms = <10>;
> + /* 6.5 POWER ON/OFF SEQUENCE, T7 >= 0 ms */
> + pwm-off-delay-ms = <10>;
> + /* 5.2 BACKLIGHT UNIT 200Hz..20kHz, value below in ns */
> + pwms = <&pwm1 0 66666 0>; /* 15 kHz = 66666ns */
> + status = "okay";
> +};
> +
> +&panel {
> + /* The G215HVN01 is replacement for T215HVN01, which is supported. */
> + compatible = "auo,t215hvn01";
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dual-lvds-odd-pixels;
> +
> + panel_lvds_b: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dual-lvds-even-pixels;
> +
> + panel_lvds_a: endpoint {
> + };
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 5V on this G215HVN01.1 panel unit. */
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 5V on this G215HVN01.1 panel unit. */
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> +};
> +
> +®_panel_vcc {
> + /* 6.5 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <40000>; /* 30.5ms <= T1 + T2 <= 60 ms */
> +
> + /* Always only output 5.0V on this G215HVN01.1 panel unit. */
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi
> new file mode 100644
> index 0000000000000..bc77dc4021f6c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 1.5 POWER ON/OFF SEQUENCE, T4 >= 200 ms */
> + pwm-off-delay-ms = <200>;
> + /* ELECTRICAL CHARACTERISTICS, BL_ADJ Frequency 20K HZ Typ., value below in ns */
> + pwms = <&pwm1 0 50000 0>;
> + status = "okay";
> +};
> +
> +&panel {
> + compatible = "multi-inno,mi0700a2t-30";
> + status = "okay";
> +
> + port {
> + panel_lvds: endpoint {
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 3.3V on this MI0700A2T-30 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 3.3V on this MI0700A2T-30 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <200000>; /* T3 */
> + off-on-delay-us = <1450000>; /* T4 + T5 + T6 + T1 + T2 + T3 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 1.5 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <60000>; /* T1 + T2 >= 1 ms (typ. 60ms) */
> +
> + /* Always only output 3.3V on this MI0700A2T-30 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi
> new file mode 100644
> index 0000000000000..f7d06002dcd5c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +
> +&backlight {
> + power-supply = <®_panel_bl>;
> + /* 3 POWER ON/OFF SEQUENCE, T7 >= 200 ms */
> + pwm-off-delay-ms = <200>;
> + /* ELECTRICAL CHARACTERISTICS, BL_ADJ Frequency 20K HZ Typ., value below in ns */
> + pwms = <&pwm1 0 50000 0>;
> + status = "okay";
> +};
> +
> +&panel {
> + compatible = "multi-inno,mi1010z1t-1cp11";
> + status = "okay";
> +
> + port {
> + panel_lvds: endpoint {
> + };
> + };
> +};
> +
> +®_backlight_pwm_level {
> + /* Always only output 3.3V on this MI1010Z1T-1CP11 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_backlight_en_level {
> + /* Always only output 3.3V on this MI1010Z1T-1CP11 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> +
> +®_panel_bl {
> + startup-delay-us = <200000>; /* T6 */
> + off-on-delay-us = <1450000>; /* T7 + T3 + T4 + T5 + T1 + T2 + T6 */
> + status = "okay";
> +};
> +
> +®_panel_vcc {
> + /* 3 POWER ON/OFF SEQUENCE */
> + startup-delay-us = <60000>; /* T1 + T2 >= 1 ms (typ. 60ms) */
> +
> + /* Always only output 3.3V on this MI1010Z1T-1CP11 panel unit. */
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
> index cb28cf1cdd23f..67d4343a8b59f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
> @@ -30,11 +30,8 @@ memory@40000000 {
>
> backlight: backlight {
> compatible = "pwm-backlight";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_panel_backlight>;
> brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
> default-brightness-level = <7>;
> - enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
> pwms = <&pwm1 0 5000000 0>;
> /* Disabled by default, unless display board plugged in. */
> status = "disabled";
> @@ -86,9 +83,6 @@ reg_panel_vcc: regulator-panel-vcc {
> regulator-min-microvolt = <5000000>;
> regulator-max-microvolt = <5000000>;
> regulator-name = "PANEL_VCC";
> - /* GPIO flags are ignored, enable-active-high applies. */
> - gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>;
> - enable-active-high;
> /* Disabled by default, unless display board plugged in. */
> status = "disabled";
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 90d7bb8f5619e..42a3216daed44 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1437,7 +1437,7 @@ aips5: bus@30df0000 {
> #access-controller-cells = <3>;
> ranges = <0x30c00000 0x30c00000 0x400000>;
>
> - spba-bus@30c00000 {
> + spba5: spba-bus@30c00000 {
> compatible = "fsl,spba-bus", "simple-bus";
> reg = <0x30c00000 0x100000>;
> #address-cells = <1>;
> --
> 2.53.0
>
^ permalink raw reply
* [PATCH 2/2] arm64: dts: qcom: milos: Add QCrypto nodes
From: Alexander Koskovich @ 2026-04-06 2:10 UTC (permalink / raw)
To: Thara Gopinath, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-crypto, linux-arm-msm, devicetree, linux-kernel,
Alexander Koskovich
In-Reply-To: <20260405-milos-qce-v1-0-6996fb0b8a9c@pm.me>
Add the QCE and Crypto BAM DMA nodes.
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
arch/arm64/boot/dts/qcom/milos.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index e1a51d43943f..61418657c4e9 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -1151,6 +1151,38 @@ aggre2_noc: interconnect@1700000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0x0 0x01dc4000 0x0 0x28000>;
+
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ #dma-cells = <1>;
+
+ iommus = <&apps_smmu 0x480 0>,
+ <&apps_smmu 0x481 0>;
+
+ qcom,ee = <0>;
+ qcom,num-ees = <4>;
+ num-channels = <20>;
+ qcom,controlled-remotely;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,milos-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0x0 0x01dfa000 0x0 0x6000>;
+
+ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "memory";
+
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+
+ iommus = <&apps_smmu 0x480 0>,
+ <&apps_smmu 0x481 0>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
--
2.53.0
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: crypto: qcom-qce: Document the Milos crypto engine
From: Alexander Koskovich @ 2026-04-06 2:10 UTC (permalink / raw)
To: Thara Gopinath, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-crypto, linux-arm-msm, devicetree, linux-kernel,
Alexander Koskovich
In-Reply-To: <20260405-milos-qce-v1-0-6996fb0b8a9c@pm.me>
Document the crypto engine on the Milos platform.
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 79d5be2548bc..74a121d8b2a5 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -46,6 +46,7 @@ properties:
- items:
- enum:
- qcom,kaanapali-qce
+ - qcom,milos-qce
- qcom,qcs615-qce
- qcom,qcs8300-qce
- qcom,sa8775p-qce
--
2.53.0
^ permalink raw reply related
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