* Re: [PATCH v1 03/13] clk: starfive: Add system-0 domain PLL clock driver
From: Changhuang Liang @ 2026-04-07 1:17 UTC (permalink / raw)
To: Brian Masney
Cc: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Chen Wang,
Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer, Keguang Zhang,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Leyfoon Tan
In-Reply-To: <ac_mdhEl9VtpTuw8@redhat.com>
Hi, Brian
Thanks for the review.
> Hi Changhuang,
>
> On Thu, Apr 02, 2026 at 10:49:35PM -0700, Changhuang Liang wrote:
> > Add system-0 domain PLL clock driver for StarFive JHB100 SoC.
> >
> > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> > ---
> > drivers/clk/starfive/Kconfig | 8 +
> > drivers/clk/starfive/Makefile | 1 +
> > .../clk/starfive/clk-starfive-jhb100-pll.c | 498 ++++++++++++++++++
> > 3 files changed, 507 insertions(+)
> > create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.c
> >
> > diff --git a/drivers/clk/starfive/Kconfig
> > b/drivers/clk/starfive/Kconfig index c612f1ede7d7..cc712da68bd0 100644
> > --- a/drivers/clk/starfive/Kconfig
> > +++ b/drivers/clk/starfive/Kconfig
> > @@ -105,6 +105,14 @@ config CLK_STARFIVE_JHB100_PER3
> > Say yes here to support the peripheral-3 clock controller
> > on the StarFive JHB100 SoC.
> >
> > +config CLK_STARFIVE_JHB100_PLL
> > + bool "StarFive JHB100 PLL clock support"
> > + depends on ARCH_STARFIVE || COMPILE_TEST
> > + default ARCH_STARFIVE
> > + help
> > + Say yes here to support the PLL clock controller on the
> > + StarFive JHB100 SoC.
> > +
> > config CLK_STARFIVE_JHB100_SYS0
> > bool "StarFive JHB100 system-0 clock support"
> > depends on ARCH_STARFIVE || COMPILE_TEST diff --git
> > a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index
> > f00690f0cdad..547a8c170728 100644
> > --- a/drivers/clk/starfive/Makefile
> > +++ b/drivers/clk/starfive/Makefile
> > @@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0)
> += clk-starfive-jhb100-per0.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) +=
> clk-starfive-jhb100-per1.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) +=
> clk-starfive-jhb100-per2.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_PER3) +=
> clk-starfive-jhb100-per3.o
> > +obj-$(CONFIG_CLK_STARFIVE_JHB100_PLL) +=
> clk-starfive-jhb100-pll.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) +=
> clk-starfive-jhb100-sys0.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) +=
> clk-starfive-jhb100-sys1.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) +=
> clk-starfive-jhb100-sys2.o
> > diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c
> > b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
> > new file mode 100644
> > index 000000000000..1751a734ee83
> > --- /dev/null
> > +++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
> > @@ -0,0 +1,498 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * StarFive JHB100 PLL Clock Generator Driver
> > + *
> > + * Copyright (C) 2024 StarFive Technology Co., Ltd.
> > + *
> > + * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
> > + */
> > +
> > +#include <linux/bits.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/debugfs.h>
> > +#include <linux/device.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +
> > +#include <dt-bindings/clock/starfive,jhb100-crg.h>
> > +
> > +/* this driver expects a 25MHz input frequency from the oscillator */
> > +#define JHB100_PLL_OSC_RATE 25000000UL
>
> You could include linux/units.h and then use: 25 * HZ_PER_MHZ
>
> > +
> > +/* System-0 domain PLL */
> > +#define JHB100_PLL2_OFFSET 0x00
> > +#define JHB100_PLL3_OFFSET 0x0c
> > +#define JHB100_PLL4_OFFSET 0x18
> > +#define JHB100_PLL5_OFFSET 0x24
> > +
> > +#define JHB100_PLL_CFG0_OFFSET 0x0
> > +#define JHB100_PLL_CFG1_OFFSET 0x4
> > +#define JHB100_PLL_CFG2_OFFSET 0x8
> > +
> > +#define JHB100_PLLX_CFG0(offset) ((offset) + JHB100_PLL_CFG0_OFFSET)
> > +/* fbdiv value should be 16 to 4095 */
> > +#define JHB100_PLL_FBDIV GENMASK(13, 2)
> > +#define JHB100_PLL_FBDIV_SHIFT 2
> > +#define JHB100_PLL_FOUTPOSTDIV_EN BIT(14)
> > +#define JHB100_PLL_FOUTPOSTDIV_EN_SHIFT 14
> > +#define JHB100_PLL_FOUTVCOP_EN BIT(16)
> > +#define JHB100_PLL_FOUTVCOP_EN_SHIFT 16
> > +
> > +#define JHB100_PLLX_CFG1(offset) ((offset) + JHB100_PLL_CFG1_OFFSET)
> > +/* frac value should be decimals multiplied by 2^24 */
> > +#define JHB100_PLL_FRAC GENMASK(23, 0)
> > +#define JHB100_PLL_FRAC_SHIFT 0
> > +#define JHB100_PLL_LOCK BIT(24)
> > +#define JHB100_PLL_LOCK_SHIFT 24
> > +
> > +#define JHB100_PLLX_CFG2(offset) ((offset) + JHB100_PLL_CFG2_OFFSET)
> > +#define JHB100_PLL_PD BIT(13)
> > +#define JHB100_PLL_PD_SHIFT 13
> > +#define JHB100_PLL_POSTDIV GENMASK(15, 14)
> > +#define JHB100_PLL_POSTDIV_SHIFT 14
> > +#define JHB100_PLL_REFDIV GENMASK(23, 18)
> > +#define JHB100_PLL_REFDIV_SHIFT 18
> > +
> > +#define JHB100_PLL_TIMEOUT_US 1000
> > +#define JHB100_PLL_INTERVAL_US 100
> > +
> > +struct jhb100_pll_preset {
> > + unsigned long freq;
> > + u32 frac; /* frac value should be decimals multiplied by 2^24
> */
> > + unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */
> > + unsigned refdiv : 6;
> > + unsigned postdiv : 2;
> > + unsigned foutpostdiv_en : 1;
> > + unsigned foutvcop_en : 1;
> > +};
> > +
> > +struct jhb100_pll_info {
> > + char *name;
> > + const struct jhb100_pll_preset *presets;
> > + unsigned int npresets;
> > + unsigned long flag;
> > + u8 offset;
> > + bool continuous;
> > +};
> > +
> > +#define _JHB100_PLL(_idx, _name, _presets, _npresets, _offset, _flag,
> _cont) \
> > + [_idx] = { \
> > + .name = _name, \
> > + .offset = _offset, \
> > + .presets = _presets, \
> > + .npresets = _npresets, \
> > + .flag = _flag, \
> > + .continuous = _cont, \
> > + }
> > +
> > +#define JHB100_PLL(idx, name, presets, npresets, offset, cont)
> \
> > + _JHB100_PLL(idx, name, presets, npresets, offset, 0, cont)
> > +
> > +struct jhb100_pll_match_data {
> > + const struct jhb100_pll_info *pll_info;
> > + int num_pll;
> > +};
> > +
> > +struct jhb100_pll_data {
> > + struct clk_hw hw;
> > + unsigned int idx;
> > +};
> > +
> > +struct jhb100_pll_priv {
> > + struct device *dev;
> > + struct regmap *regmap;
> > + const struct jhb100_pll_match_data *match_data;
> > + struct jhb100_pll_data pll[];
> > +};
> > +
> > +struct jhb100_pll_regvals {
> > + u32 fbdiv;
> > + u32 frac;
> > + u32 postdiv;
> > + u32 refdiv;
> > + bool foutpostdiv_en;
> > + bool foutvcop_en;
> > +};
> > +
> > +static struct jhb100_pll_data *jhb100_pll_data_from(struct clk_hw
> > +*hw) {
> > + return container_of(hw, struct jhb100_pll_data, hw); }
> > +
> > +static struct jhb100_pll_priv *jhb100_pll_priv_from(struct
> > +jhb100_pll_data *pll) {
> > + return container_of(pll, struct jhb100_pll_priv, pll[pll->idx]); }
> > +
> > +static int jhb100_pll_enable(struct clk_hw *hw) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> > +&priv->match_data->pll_info[pll->idx];
> > +
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
> > + JHB100_PLL_PD, 0);
>
> Should the return value be checked here? Or just:
>
> return regumap_update_bits(...);
>
> > +
> > + return 0;
> > +}
> > +
> > +static void jhb100_pll_disable(struct clk_hw *hw) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> > +&priv->match_data->pll_info[pll->idx];
> > +
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
> > + JHB100_PLL_PD, BIT(JHB100_PLL_PD_SHIFT)); }
> > +
> > +static int jhb100_pll_is_enabled(struct clk_hw *hw) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> &priv->match_data->pll_info[pll->idx];
> > + u32 val;
> > +
> > + regmap_read(priv->regmap, JHB100_PLLX_CFG2(info->offset), &val);
>
> Should the return value be checked?
>
> > +
> > + return !(val & JHB100_PLL_PD);
>
> If regmap_read() returns an error, then is val uninitialized?
>
> > +}
> > +
> > +static void jhb100_pll_regvals_get(struct regmap *regmap,
> > + const struct jhb100_pll_info *info,
> > + struct jhb100_pll_regvals *ret) {
> > + u32 val;
> > +
> > + regmap_read(regmap, JHB100_PLLX_CFG0(info->offset), &val);
> > + ret->fbdiv = (val & JHB100_PLL_FBDIV) >> JHB100_PLL_FBDIV_SHIFT;
> > + ret->foutpostdiv_en = !!((val & JHB100_PLL_FOUTPOSTDIV_EN) >>
> > + JHB100_PLL_FOUTPOSTDIV_EN_SHIFT);
> > + ret->foutvcop_en = !!((val & JHB100_PLL_FOUTVCOP_EN) >>
> > + JHB100_PLL_FOUTVCOP_EN_SHIFT);
> > +
> > + regmap_read(regmap, JHB100_PLLX_CFG1(info->offset), &val);
> > + ret->frac = (val & JHB100_PLL_FRAC) >> JHB100_PLL_FRAC_SHIFT;
> > +
> > + regmap_read(regmap, JHB100_PLLX_CFG2(info->offset), &val);
> > + ret->postdiv = (val & JHB100_PLL_POSTDIV) >>
> JHB100_PLL_POSTDIV_SHIFT;
> > + ret->refdiv = (val & JHB100_PLL_REFDIV) >> JHB100_PLL_REFDIV_SHIFT;
>
> Should these regmap return values be checked, and the error code returned?
>
> > +}
> > +
> > +static unsigned long jhb100_pll_recalc_rate(struct clk_hw *hw,
> > +unsigned long parent_rate) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + struct jhb100_pll_regvals val;
> > + unsigned long rate;
> > + u32 power = 0;
> > +
> > + jhb100_pll_regvals_get(priv->regmap,
> > +&priv->match_data->pll_info[pll->idx], &val);
> > +
> > + /*
> > + *
> > + * if (foutvcop_en)
> > + * rate = parent * (fbdiv + frac / 2^24) / refdiv
> > + *
> > + * if (foutpostdiv_en)
> > + * rate = parent * (fbdiv + frac / 2^24) / refdiv / 2^(postdiv + 1)
> > + *
> > + * parent * (fbdiv + frac / 2^24) = parent * fbdiv + parent * frac / 2^24
> > + */
> > +
> > + if (!!val.foutvcop_en == !!val.foutpostdiv_en)
> > + return 0;
> > +
> > + rate = (parent_rate * val.frac) >> 24;
> > +
> > + if (val.foutpostdiv_en)
> > + power = val.postdiv + 1;
> > +
> > + rate += parent_rate * val.fbdiv;
> > + rate /= val.refdiv << power;
>
> Could val.refdiv ever be zero?
Will check it at next version.
> > +
> > + return rate;
> > +}
> > +
> > +static int jhb100_pll_determine_rate(struct clk_hw *hw, struct
> > +clk_rate_request *req) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> &priv->match_data->pll_info[pll->idx];
> > + const struct jhb100_pll_preset *selected = &info->presets[0];
> > + unsigned int idx;
> > +
> > + /* if the parent rate doesn't match our expectations the presets won't
> work */
> > + if (req->best_parent_rate != JHB100_PLL_OSC_RATE) {
> > + req->rate = jhb100_pll_recalc_rate(hw, req->best_parent_rate);
> > + return 0;
> > + }
> > +
> > + /* continuous means support any rate */
> > + if (info->continuous)
> > + return 0;
> > +
> > + /* find highest rate lower or equal to the requested rate */
> > + for (idx = 1; idx < info->npresets; idx++) {
> > + const struct jhb100_pll_preset *val = &info->presets[idx];
> > +
> > + if (req->rate < val->freq)
> > + break;
> > +
> > + selected = val;
> > + }
> > +
> > + req->rate = selected->freq;
> > +
> > + return 0;
> > +}
> > +
> > +static int jhb100_pll_set_preset(struct clk_hw *hw, struct
> > +jhb100_pll_preset *val) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> &priv->match_data->pll_info[pll->idx];
> > + unsigned int value;
> > +
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG0(info->offset),
> JHB100_PLL_FBDIV,
> > + (u32)val->fbdiv << JHB100_PLL_FBDIV_SHIFT);
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG0(info->offset),
> JHB100_PLL_FOUTPOSTDIV_EN,
> > + (u32)val->foutpostdiv_en <<
> JHB100_PLL_FOUTPOSTDIV_EN_SHIFT);
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG0(info->offset),
> JHB100_PLL_FOUTVCOP_EN,
> > + (u32)val->foutvcop_en <<
> JHB100_PLL_FOUTVCOP_EN_SHIFT);
>
> These are writing to the same register. Should the values be combined into
> one, and written once to the register?
>
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG1(info->offset),
> JHB100_PLL_FRAC,
> > + val->frac << JHB100_PLL_FRAC_SHIFT);
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
> JHB100_PLL_REFDIV,
> > + (u32)val->refdiv << JHB100_PLL_REFDIV_SHIFT);
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
> JHB100_PLL_POSTDIV,
> > + (u32)val->postdiv << JHB100_PLL_POSTDIV_SHIFT);
>
> The last two calls to JHB100_PLLX_CFG2 also write to the same register.
> Should the two writes be combined into one?
>
> Should the return values from regmap_update_bits() be checked?
>
> > +
> > + /* waiting for PLL to lock */
> > + return regmap_read_poll_timeout_atomic(priv->regmap,
> JHB100_PLLX_CFG1(info->offset),
> > + value, value & JHB100_PLL_LOCK,
> > + JHB100_PLL_INTERVAL_US,
> > + JHB100_PLL_TIMEOUT_US);
> > +}
> > +
> > +static int jhb100_pll_rate_to_preset(struct clk_hw *hw, unsigned long rate,
> > + unsigned long parent_rate)
> > +{
> > + struct jhb100_pll_preset val = {
> > + .refdiv = 1,
> > + .postdiv = 3,
> > + .foutpostdiv_en = 1,
> > + .foutvcop_en = 0,
> > + };
> > + unsigned int power = 0;
> > + unsigned long fbdiv_24, t;
> > +
> > + if (val.foutpostdiv_en)
> > + power = val.postdiv + 1;
> > +
> > + t = val.refdiv << power;
> > + t *= rate;
> > +
> > + val.fbdiv = t / parent_rate;
>
> Should a check for parent_rate == 0 be added?
parent_rate is checked in jhb100_pll_set_rate, and it only supports 25M.
> > +
> > + fbdiv_24 = (t << 24) / parent_rate;
> > + val.frac = fbdiv_24 - (val.fbdiv << 24);
> > +
> > + return jhb100_pll_set_preset(hw, &val); }
> > +
> > +static int jhb100_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long parent_rate)
> > +{
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> &priv->match_data->pll_info[pll->idx];
> > + const struct jhb100_pll_preset *val;
> > + unsigned int idx;
> > +
> > + /* if the parent rate doesn't match our expectations the presets won't
> work */
> > + if (parent_rate != JHB100_PLL_OSC_RATE)
> > + return -EINVAL;
> > +
> > + if (info->continuous)
> > + return jhb100_pll_rate_to_preset(hw, rate, parent_rate);
> > +
> > + for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) {
> > + if (val->freq == rate)
> > + return jhb100_pll_set_preset(hw, (struct jhb100_pll_preset
> *)val);
>
> The cast looks to be here because of the const in jhb100_pll_set_preset(). Can
> const be added to the declaration of jhb100_pll_set_preset()?
Will try it.
Best Regards,
Changhuang
^ permalink raw reply
* Re: [PATCH v1 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT
From: Changhuang Liang @ 2026-04-07 0:52 UTC (permalink / raw)
To: Conor Dooley
Cc: Emil Renner Berthing, Joel Stanley, Drew Fustini,
Darshan Prajapati, linux-riscv@lists.infradead.org, Rob Herring,
Alexandre Ghiti, Anup Patel, Hal Feng, Guodong Xu, Yixun Lan,
Heinrich Schuchardt, devicetree@vger.kernel.org, Conor Dooley,
Albert Ou, E Shattow, Leyfoon Tan, Junhui Liu, Daniel Lezcano,
Michal Simek, Paul Walmsley, linux-kernel@vger.kernel.org,
Samuel Holland, Michael Zhu, Palmer Dabbelt, Thomas Gleixner,
JiSheng Teoh, Krzysztof Kozlowski
In-Reply-To: <20260403-pristine-slam-71d8e0093b6f@spud>
Hi, Conor
Thanks for the review.
> On Fri, Apr 03, 2026 at 03:06:23AM +0000, Changhuang Liang wrote:
> > Hi, Conor
> >
> > > On Thu, Apr 02, 2026 at 01:40:19AM -0700, Changhuang Liang wrote:
> > > > From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > > >
> > > > Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT,
> > > > PLIC, PMU, UART and 1GB DDR.
> > > >
> > > > Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > > > Signed-off-by: Changhuang Liang
> > > > <changhuang.liang@starfivetech.com>
> > > > ---
> > > > MAINTAINERS | 6 +
> > > > arch/riscv/boot/dts/starfive/Makefile | 2 +
> > > > .../boot/dts/starfive/jhb100-evb1-eth.dts | 6 +
> > > > arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi | 32 ++
> > > > arch/riscv/boot/dts/starfive/jhb100.dtsi | 326
> > > ++++++++++++++++++
> > > > 5 files changed, 372 insertions(+) create mode 100644
> > > > arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > > create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> > > > create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
> > > >
> > > > diff --git a/MAINTAINERS b/MAINTAINERS index
> > > > 7d10988cbc62..b1892a480c31 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -25306,6 +25306,12 @@ S: Supported
> > > > F:
> > >
> > > Documentation/devicetree/bindings/interrupt-controller/starfive,jh81
> > > 00
> > > -intc.yaml
> > > > F: drivers/irqchip/irq-starfive-jh8100-intc.c
> > > >
> > > > +STARFIVE JHB100 DEVICETREES
> > > > +M: Changhuang Liang <changhuang.liang@starfivetech.com>
> > > > +L: linux-riscv@lists.infradead.org
> > > > +S: Maintained
> > >
> > > Supported, no?
> > >
> > > > +F: arch/riscv/boot/dts/starfive/jhb100*
> > > > +
> > > > STATIC BRANCH/CALL
> > > > M: Peter Zijlstra <peterz@infradead.org>
> > > > M: Josh Poimboeuf <jpoimboe@kernel.org>
> > > > diff --git a/arch/riscv/boot/dts/starfive/Makefile
> > > > b/arch/riscv/boot/dts/starfive/Makefile
> > > > index 3dd1f05283f7..7cdb75788053 100644
> > > > --- a/arch/riscv/boot/dts/starfive/Makefile
> > > > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > > > @@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > > jh7110-starfive-visionfive-2-lite.dtb
> > > > dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > > jh7110-starfive-visionfive-2-lite-emmc.dtb
> > > > dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > > jh7110-starfive-visionfive-2-v1.2a.dtb
> > > > dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > > jh7110-starfive-visionfive-2-v1.3b.dtb
> > > > +
> > > > +dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1-eth.dtb
> > > > diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > > b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > > new file mode 100644
> > > > index 000000000000..62cd046e1224
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > > @@ -0,0 +1,6 @@
> > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > > +/*
> > > > + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> > > > + */
> > > > +
> > > > +#include "jhb100-evb1.dtsi"
> > >
> > > What is the point of this file? Is this the base-board?
> > > Shouldn't it have a specific compatible?
> > >
> > > Can the SoM be used without a base board? I've got no info about
> > > this board appearing on google, do you even have pictures of it or any
> documentation?
> > > I see this
> > >
> https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=22
> > > and
> > >
> https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=23
> > > but the former doesn't look like it needs a base-board and the
> > > latter is called "evb3", so is not what's here?
> >
> > The former is the base board of the EVB1. Currently, we are only
> > carrying out upstream work based on the EVB1. The EVB1 base board has
> > reserved slots
>
> Except when I look at the first link, the picture doesn't show something that is
> a SoM + base-board, it's just a regular board. If that's the case, the breakdown
> of files doesn't make sense, with jhb100-evb1.dtsi sounding like it should be a
> dts. Usually we talk about base-boards in relation to a SoM, like what the
> mars-cm needs to function.
>
>
>
> > that can accommodate expansion boards to verify more advanced features.
> > At present, the jhb100-evb1.dtsi file corresponds to the configuration
> > of the
> > EVB1 base board. In the future, we will add dtsi files for the expansion
> boards.
> > The jhb100-evb1-eth.dts file will then be used to combine these dtsi
> > files to generate the final version of the device tree source.
>
> Sounds like here the evb1 is a complete board and jhb100-evb1-eth.dts
> represents some kind of expansion card added to that board?
> I think this not correct, since the base-board needs to be usable in isolation.
> Take a look at what rockchip do for rk3588-rock-5b-pcie-ep in
> arch/arm64/boot/dts/rockchip/Makefile/, where these expansion type things
> are dealt with using overlays.
This means a lot to me. Will change it to jhb100-evb.dts
Best Regards,
Changhuang
^ permalink raw reply
* Re: [PATCh v3 06/14] ASoC: rsnd: Add RZ/G3E DMA address calculation support
From: Kuninori Morimoto @ 2026-04-07 0:44 UTC (permalink / raw)
To: John Madieu
Cc: Mark Brown, Liam Girdwood, Geert Uytterhoeven, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
Magnus Damm, Philipp Zabel, Claudiu Beznea, Biju Das, john.madieu,
linux-sound, linux-renesas-soc, devicetree, linux-kernel
In-Reply-To: <20260402162436.12059-7-john.madieu.xa@bp.renesas.com>
Hi John, again
> RZ/G3E has different DMA register base addresses and offset
> calculations compared to R-Car platforms.
>
> Add dedicated rsnd_rzg3e_dma_addr() function with dispatch from
> rsnd_dma_addr(), following the existing per-generation pattern.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
(snip)
> +struct rsnd_dma_addr {
> + dma_addr_t out_addr;
> + dma_addr_t in_addr;
> +};
> +
> static dma_addr_t
> -rsnd_gen2_dma_addr(struct rsnd_dai_stream *io,
> - struct rsnd_mod *mod,
> - int is_play, int is_from)
> +rsnd_dma_addr_lookup(struct rsnd_dai_stream *io,
> + struct rsnd_mod *mod,
> + const struct rsnd_dma_addr tbl[3][2][3],
> + int is_play, int is_from)
Here, it is using raw [3][2][3] array as param.
I think it is good timing to create new struct for it, and use its pointer ?
Something like...
struct rsnd_dma_addr {
dma_addr_t out_addr;
dma_addr_t in_addr;
};
struct rsnd_dma_addr_dir {
struct rsnd_dma_addr capture[3];
struct rsnd_dma_addr platback[3];
};
struct rsnd_dma_addr_map {
struct rsnd_dma_addr_dir src;
struct rsnd_dma_addr_dri ssi;
struct rsnd_dma_addr_dir ssui;
};
> - } dma_addrs[3][2][3] = {
> + const struct rsnd_dma_addr tbl[3][2][3] = {
> + /* SRC */
> + /* Capture */
> + {{{ 0, 0, },
> + { RDMA_SRC_O_N_G3E(src, id), RDMA_SRC_I_P_G3E(src, id) },
> + { RDMA_CMD_O_N_G3E(src, id), RDMA_SRC_I_P_G3E(src, id) } },
> + /* Playback */
> + {{ 0, 0 },
> + { RDMA_SRC_O_P_G3E(src, id), RDMA_SRC_I_N_G3E(src, id) },
> + { RDMA_CMD_O_P_G3E(src, id), RDMA_SRC_I_N_G3E(src, id) } }
> + },
> + /* SSI */
> + /* Capture */
> + {{{ RDMA_SSI_O_N_G3E(ssi, id), 0 },
> + { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 },
> + { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 } },
> + /* Playback */
> + {{ 0, RDMA_SSI_I_N_G3E(ssi, id) },
> + { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) },
> + { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) } }
> + },
> + /* SSIU */
> + /* Capture */
> + {{{ RDMA_SSIU_O_N_G3E(ssi, id, busif), 0 },
> + { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 },
> + { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 } },
> + /* Playback */
> + {{ 0, RDMA_SSIU_I_N_G3E(ssi, id, busif) },
> + { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) },
> + { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) } } },
> + };
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* Re: [PATCH] dt-bindings: display/msm: move DSI PHY bindings to phy/ subdir
From: Dmitry Baryshkov @ 2026-04-06 23:42 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong,
Krishna Manikandan, Jonathan Marek, Dmitry Baryshkov
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-phy
In-Reply-To: <20260305-msm-dsi-phy-v1-1-0a99ac665995@oss.qualcomm.com>
On Thu, 05 Mar 2026 01:47:12 +0200, Dmitry Baryshkov wrote:
> Historically DSI PHY bindings landed to the display/msm subdir, however
> they describe PHYs and as such they should be in the phy/ subdir.
> Follow the example of other Qualcomm display-related PHYs (HDMI, eDP)
> and move bindings for the Qualcomm DSI PHYs to the correct subdir.
Applied to msm-next, thanks!
[1/1] dt-bindings: display/msm: move DSI PHY bindings to phy/ subdir
https://gitlab.freedesktop.org/lumag/msm/-/commit/f94aa7e9cf68
Best regards,
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 3/3] ASoC: renesas: fsi: Fix hang by enabling SPU clock
From: Kuninori Morimoto @ 2026-04-06 23:31 UTC (permalink / raw)
To: Bui Duc Phuc
Cc: broonie, lgirdwood, robh, krzk+dt, conor+dt, geert+renesas,
magnus.damm, perex, tiwai, linux-sound, linux-renesas-soc,
devicetree, linux-kernel
In-Reply-To: <CAABR9nGUyTkDmB0SgKAuM1Pp75L=m1q4bLSfhobm98TswDnt8w@mail.gmail.com>
Hi Bui
> Yes, enabling this clock is essential as it functions as a bus bridge clock.
> Currently, the SPU clock is still enabled by the bootloader. In legacy
> kernels (v4.2 and earlier) using the Armadillo board-file/defconfig, this
> clock remained active after boot, allowing the FSI to function correctly.
> However, after migrating to a full Device Tree (DTS) implementation,
> the kernel's unused clock cleanup mechanism disables the SPU clock
> because it isn't explicitly claimed. This leads to a system hang every
> time aplay is executed, as the FSI registers become inaccessible
> without this clock.
Thank you for clarify the situation.
I didn't notice about this.
> I previously attempted to manage the clock within fsi_hw_startup/
> shutdown, but the system would hang when stopping aplay
> (e.g., via Ctrl+C). This happens because certain cleanup operations,
> such as fsi_irq_disable(), are performed after fsi_hw_shutdown()
> finishes. These operations require register access, which triggers a
> system hang if the SPU clock has already been disabled. Therefore,
> I moved the clock management to fsi_dai_startup/shutdown to ensure
> the clock remains active throughout the entire lifecycle of the stream.
Hmm ?
fsi_irq_disable() is called after fsi_hw_shutdown() ??
Ah... is it because PIO transfer ?
I have 100% forgotten, but FSI doesn't support RX DMA...
Hmm... fsi_dai_trigger() seems strange.
It seems (A) stops clock, and (B) sets register after that.
Is this the reason why you get error ? I think (A) and (B) should be
reversed. The balance between SNDRV_PCM_TRIGGER_START, and with
__fsi_suspend() are also not good.
If so, can you use hw_start/stop() ?
static int fsi_dai_trigger(...)
{
...
switch (cmd) {
...
case SNDRV_PCM_TRIGGER_STOP:
if (!ret)
(A) ret = fsi_hw_shutdown(fsi, dev);
(B) fsi_stream_stop(fsi, io);
(C) fsi_stream_quit(fsi, io);
break;
}
...
}
> Furthermore, my testing shows that using dai_startup/shutdown
> eliminates the need for explicit Suspend/Resume handling for this clock.
> Since the ALSA framework typically invokes the hw_ callbacks during
> power management transitions rather than the dai_ ones, the SPU clock
> state remains stable, preventing any illegal register access during
> these transitions.
Basically, concept of this driver is that power/clock is enabled/disabled
when trigger() was called (except suspend/resume).
While your testing may be correct from an ALSA point of view, but setting
configuring it in multiple places will lead to confusion.
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* [PATCH 2/2] riscv: dts: sophgo: sg2042: use hex for CPU unit address
From: Inochi Amaoto @ 2026-04-06 23:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Han Gao, Nutty Liu, Guodong Xu, Guo Ren,
Xiaoguang Xing
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
In-Reply-To: <20260406232655.144043-1-inochiama@gmail.com>
Previous the CPU unit address cpu of sg2042 use decimal, it is
not following the general convention for unit addresses of the
OF. Convent the unit address to hex to resolve this problem.
The introduces a small ABI break for the CPU id, but it should
affect nothing since there is no direct full-path reference to
these CPU nodes.
Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/
---
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++----------
1 file changed, 118 insertions(+), 118 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index 509488eee432..fd8906b313d2 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -263,7 +263,7 @@ cpu0: cpu@0 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <0>;
+ reg = <0x0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -291,7 +291,7 @@ cpu1: cpu@1 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <1>;
+ reg = <0x1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -319,7 +319,7 @@ cpu2: cpu@2 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <2>;
+ reg = <0x2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -347,7 +347,7 @@ cpu3: cpu@3 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <3>;
+ reg = <0x3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -375,7 +375,7 @@ cpu4: cpu@4 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <4>;
+ reg = <0x4>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -403,7 +403,7 @@ cpu5: cpu@5 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <5>;
+ reg = <0x5>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -431,7 +431,7 @@ cpu6: cpu@6 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <6>;
+ reg = <0x6>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -459,7 +459,7 @@ cpu7: cpu@7 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <7>;
+ reg = <0x7>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -487,7 +487,7 @@ cpu8: cpu@8 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <8>;
+ reg = <0x8>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -515,7 +515,7 @@ cpu9: cpu@9 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <9>;
+ reg = <0x9>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller {
};
};
- cpu10: cpu@10 {
+ cpu10: cpu@a {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -543,7 +543,7 @@ cpu10: cpu@10 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <10>;
+ reg = <0xa>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller {
};
};
- cpu11: cpu@11 {
+ cpu11: cpu@b {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -571,7 +571,7 @@ cpu11: cpu@11 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <11>;
+ reg = <0xb>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller {
};
};
- cpu12: cpu@12 {
+ cpu12: cpu@c {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -599,7 +599,7 @@ cpu12: cpu@12 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <12>;
+ reg = <0xc>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller {
};
};
- cpu13: cpu@13 {
+ cpu13: cpu@d {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -627,7 +627,7 @@ cpu13: cpu@13 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <13>;
+ reg = <0xd>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller {
};
};
- cpu14: cpu@14 {
+ cpu14: cpu@e {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -655,7 +655,7 @@ cpu14: cpu@14 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <14>;
+ reg = <0xe>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller {
};
};
- cpu15: cpu@15 {
+ cpu15: cpu@f {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -683,7 +683,7 @@ cpu15: cpu@15 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <15>;
+ reg = <0xf>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller {
};
};
- cpu16: cpu@16 {
+ cpu16: cpu@10 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -711,7 +711,7 @@ cpu16: cpu@16 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <16>;
+ reg = <0x10>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller {
};
};
- cpu17: cpu@17 {
+ cpu17: cpu@11 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -739,7 +739,7 @@ cpu17: cpu@17 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <17>;
+ reg = <0x11>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller {
};
};
- cpu18: cpu@18 {
+ cpu18: cpu@12 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -767,7 +767,7 @@ cpu18: cpu@18 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <18>;
+ reg = <0x12>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller {
};
};
- cpu19: cpu@19 {
+ cpu19: cpu@13 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -795,7 +795,7 @@ cpu19: cpu@19 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <19>;
+ reg = <0x13>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller {
};
};
- cpu20: cpu@20 {
+ cpu20: cpu@14 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -823,7 +823,7 @@ cpu20: cpu@20 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <20>;
+ reg = <0x14>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller {
};
};
- cpu21: cpu@21 {
+ cpu21: cpu@15 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -851,7 +851,7 @@ cpu21: cpu@21 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <21>;
+ reg = <0x15>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller {
};
};
- cpu22: cpu@22 {
+ cpu22: cpu@16 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -879,7 +879,7 @@ cpu22: cpu@22 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <22>;
+ reg = <0x16>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller {
};
};
- cpu23: cpu@23 {
+ cpu23: cpu@17 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -907,7 +907,7 @@ cpu23: cpu@23 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <23>;
+ reg = <0x17>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller {
};
};
- cpu24: cpu@24 {
+ cpu24: cpu@18 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -935,7 +935,7 @@ cpu24: cpu@24 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <24>;
+ reg = <0x18>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller {
};
};
- cpu25: cpu@25 {
+ cpu25: cpu@19 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -963,7 +963,7 @@ cpu25: cpu@25 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <25>;
+ reg = <0x19>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller {
};
};
- cpu26: cpu@26 {
+ cpu26: cpu@1a {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -991,7 +991,7 @@ cpu26: cpu@26 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <26>;
+ reg = <0x1a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller {
};
};
- cpu27: cpu@27 {
+ cpu27: cpu@1b {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1019,7 +1019,7 @@ cpu27: cpu@27 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <27>;
+ reg = <0x1b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller {
};
};
- cpu28: cpu@28 {
+ cpu28: cpu@1c {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1047,7 +1047,7 @@ cpu28: cpu@28 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <28>;
+ reg = <0x1c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller {
};
};
- cpu29: cpu@29 {
+ cpu29: cpu@1d {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1075,7 +1075,7 @@ cpu29: cpu@29 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <29>;
+ reg = <0x1d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller {
};
};
- cpu30: cpu@30 {
+ cpu30: cpu@1e {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1103,7 +1103,7 @@ cpu30: cpu@30 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <30>;
+ reg = <0x1e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller {
};
};
- cpu31: cpu@31 {
+ cpu31: cpu@1f {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1131,7 +1131,7 @@ cpu31: cpu@31 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <31>;
+ reg = <0x1f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller {
};
};
- cpu32: cpu@32 {
+ cpu32: cpu@20 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1159,7 +1159,7 @@ cpu32: cpu@32 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <32>;
+ reg = <0x20>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller {
};
};
- cpu33: cpu@33 {
+ cpu33: cpu@21 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1187,7 +1187,7 @@ cpu33: cpu@33 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <33>;
+ reg = <0x21>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller {
};
};
- cpu34: cpu@34 {
+ cpu34: cpu@22 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1215,7 +1215,7 @@ cpu34: cpu@34 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <34>;
+ reg = <0x22>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller {
};
};
- cpu35: cpu@35 {
+ cpu35: cpu@23 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1243,7 +1243,7 @@ cpu35: cpu@35 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <35>;
+ reg = <0x23>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller {
};
};
- cpu36: cpu@36 {
+ cpu36: cpu@24 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1271,7 +1271,7 @@ cpu36: cpu@36 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <36>;
+ reg = <0x24>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller {
};
};
- cpu37: cpu@37 {
+ cpu37: cpu@25 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1299,7 +1299,7 @@ cpu37: cpu@37 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <37>;
+ reg = <0x25>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller {
};
};
- cpu38: cpu@38 {
+ cpu38: cpu@26 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1327,7 +1327,7 @@ cpu38: cpu@38 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <38>;
+ reg = <0x26>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller {
};
};
- cpu39: cpu@39 {
+ cpu39: cpu@27 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1355,7 +1355,7 @@ cpu39: cpu@39 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <39>;
+ reg = <0x27>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller {
};
};
- cpu40: cpu@40 {
+ cpu40: cpu@28 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1383,7 +1383,7 @@ cpu40: cpu@40 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <40>;
+ reg = <0x28>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller {
};
};
- cpu41: cpu@41 {
+ cpu41: cpu@29 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1411,7 +1411,7 @@ cpu41: cpu@41 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <41>;
+ reg = <0x29>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller {
};
};
- cpu42: cpu@42 {
+ cpu42: cpu@2a {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1439,7 +1439,7 @@ cpu42: cpu@42 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <42>;
+ reg = <0x2a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller {
};
};
- cpu43: cpu@43 {
+ cpu43: cpu@2b {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1467,7 +1467,7 @@ cpu43: cpu@43 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <43>;
+ reg = <0x2b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller {
};
};
- cpu44: cpu@44 {
+ cpu44: cpu@2c {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1495,7 +1495,7 @@ cpu44: cpu@44 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <44>;
+ reg = <0x2c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller {
};
};
- cpu45: cpu@45 {
+ cpu45: cpu@2d {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1523,7 +1523,7 @@ cpu45: cpu@45 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <45>;
+ reg = <0x2d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller {
};
};
- cpu46: cpu@46 {
+ cpu46: cpu@2e {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1551,7 +1551,7 @@ cpu46: cpu@46 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <46>;
+ reg = <0x2e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller {
};
};
- cpu47: cpu@47 {
+ cpu47: cpu@2f {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1579,7 +1579,7 @@ cpu47: cpu@47 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <47>;
+ reg = <0x2f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller {
};
};
- cpu48: cpu@48 {
+ cpu48: cpu@30 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1607,7 +1607,7 @@ cpu48: cpu@48 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <48>;
+ reg = <0x30>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller {
};
};
- cpu49: cpu@49 {
+ cpu49: cpu@31 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1635,7 +1635,7 @@ cpu49: cpu@49 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <49>;
+ reg = <0x31>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller {
};
};
- cpu50: cpu@50 {
+ cpu50: cpu@32 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1663,7 +1663,7 @@ cpu50: cpu@50 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <50>;
+ reg = <0x32>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller {
};
};
- cpu51: cpu@51 {
+ cpu51: cpu@33 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1691,7 +1691,7 @@ cpu51: cpu@51 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <51>;
+ reg = <0x33>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller {
};
};
- cpu52: cpu@52 {
+ cpu52: cpu@34 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1719,7 +1719,7 @@ cpu52: cpu@52 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <52>;
+ reg = <0x34>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller {
};
};
- cpu53: cpu@53 {
+ cpu53: cpu@35 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1747,7 +1747,7 @@ cpu53: cpu@53 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <53>;
+ reg = <0x35>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller {
};
};
- cpu54: cpu@54 {
+ cpu54: cpu@36 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1775,7 +1775,7 @@ cpu54: cpu@54 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <54>;
+ reg = <0x36>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller {
};
};
- cpu55: cpu@55 {
+ cpu55: cpu@37 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1803,7 +1803,7 @@ cpu55: cpu@55 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <55>;
+ reg = <0x37>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller {
};
};
- cpu56: cpu@56 {
+ cpu56: cpu@38 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1831,7 +1831,7 @@ cpu56: cpu@56 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <56>;
+ reg = <0x38>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller {
};
};
- cpu57: cpu@57 {
+ cpu57: cpu@39 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1859,7 +1859,7 @@ cpu57: cpu@57 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <57>;
+ reg = <0x39>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller {
};
};
- cpu58: cpu@58 {
+ cpu58: cpu@3a {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1887,7 +1887,7 @@ cpu58: cpu@58 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <58>;
+ reg = <0x3a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller {
};
};
- cpu59: cpu@59 {
+ cpu59: cpu@3b {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1915,7 +1915,7 @@ cpu59: cpu@59 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <59>;
+ reg = <0x3b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller {
};
};
- cpu60: cpu@60 {
+ cpu60: cpu@3c {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1943,7 +1943,7 @@ cpu60: cpu@60 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <60>;
+ reg = <0x3c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller {
};
};
- cpu61: cpu@61 {
+ cpu61: cpu@3d {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1971,7 +1971,7 @@ cpu61: cpu@61 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <61>;
+ reg = <0x3d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller {
};
};
- cpu62: cpu@62 {
+ cpu62: cpu@3e {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1999,7 +1999,7 @@ cpu62: cpu@62 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <62>;
+ reg = <0x3e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller {
};
};
- cpu63: cpu@63 {
+ cpu63: cpu@3f {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -2027,7 +2027,7 @@ cpu63: cpu@63 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <63>;
+ reg = <0x3f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
--
2.53.0
^ permalink raw reply related
* [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address
From: Inochi Amaoto @ 2026-04-06 23:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Han Gao, Nutty Liu, Guodong Xu, Guo Ren,
Xiaoguang Xing
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
In-Reply-To: <20260406232655.144043-1-inochiama@gmail.com>
Previous the CPU unit address cpu of sg2044 use decimal, it is
not following the general convention for unit addresses of the
OF. Convent the unit address to hex to resolve this problem.
The introduces a small ABI break for the CPU id, but it should
affect nothing since there is no direct full-path reference to
these CPU nodes.
Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/
---
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++----------
1 file changed, 118 insertions(+), 118 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
index 3135409c2149..f66a382c95bd 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
@@ -14,7 +14,7 @@ cpus {
cpu0: cpu@0 {
compatible = "thead,c920", "riscv";
- reg = <0>;
+ reg = <0x0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller {
cpu1: cpu@1 {
compatible = "thead,c920", "riscv";
- reg = <1>;
+ reg = <0x1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller {
cpu2: cpu@2 {
compatible = "thead,c920", "riscv";
- reg = <2>;
+ reg = <0x2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller {
cpu3: cpu@3 {
compatible = "thead,c920", "riscv";
- reg = <3>;
+ reg = <0x3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller {
cpu4: cpu@4 {
compatible = "thead,c920", "riscv";
- reg = <4>;
+ reg = <0x4>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller {
cpu5: cpu@5 {
compatible = "thead,c920", "riscv";
- reg = <5>;
+ reg = <0x5>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller {
cpu6: cpu@6 {
compatible = "thead,c920", "riscv";
- reg = <6>;
+ reg = <0x6>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller {
cpu7: cpu@7 {
compatible = "thead,c920", "riscv";
- reg = <7>;
+ reg = <0x7>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller {
cpu8: cpu@8 {
compatible = "thead,c920", "riscv";
- reg = <8>;
+ reg = <0x8>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller {
cpu9: cpu@9 {
compatible = "thead,c920", "riscv";
- reg = <9>;
+ reg = <0x9>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller {
};
};
- cpu10: cpu@10 {
+ cpu10: cpu@a {
compatible = "thead,c920", "riscv";
- reg = <10>;
+ reg = <0xa>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller {
};
};
- cpu11: cpu@11 {
+ cpu11: cpu@b {
compatible = "thead,c920", "riscv";
- reg = <11>;
+ reg = <0xb>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller {
};
};
- cpu12: cpu@12 {
+ cpu12: cpu@c {
compatible = "thead,c920", "riscv";
- reg = <12>;
+ reg = <0xc>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller {
};
};
- cpu13: cpu@13 {
+ cpu13: cpu@d {
compatible = "thead,c920", "riscv";
- reg = <13>;
+ reg = <0xd>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller {
};
};
- cpu14: cpu@14 {
+ cpu14: cpu@e {
compatible = "thead,c920", "riscv";
- reg = <14>;
+ reg = <0xe>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller {
};
};
- cpu15: cpu@15 {
+ cpu15: cpu@f {
compatible = "thead,c920", "riscv";
- reg = <15>;
+ reg = <0xf>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller {
};
};
- cpu16: cpu@16 {
+ cpu16: cpu@10 {
compatible = "thead,c920", "riscv";
- reg = <16>;
+ reg = <0x10>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller {
};
};
- cpu17: cpu@17 {
+ cpu17: cpu@11 {
compatible = "thead,c920", "riscv";
- reg = <17>;
+ reg = <0x11>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller {
};
};
- cpu18: cpu@18 {
+ cpu18: cpu@12 {
compatible = "thead,c920", "riscv";
- reg = <18>;
+ reg = <0x12>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller {
};
};
- cpu19: cpu@19 {
+ cpu19: cpu@13 {
compatible = "thead,c920", "riscv";
- reg = <19>;
+ reg = <0x13>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller {
};
};
- cpu20: cpu@20 {
+ cpu20: cpu@14 {
compatible = "thead,c920", "riscv";
- reg = <20>;
+ reg = <0x14>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller {
};
};
- cpu21: cpu@21 {
+ cpu21: cpu@15 {
compatible = "thead,c920", "riscv";
- reg = <21>;
+ reg = <0x15>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller {
};
};
- cpu22: cpu@22 {
+ cpu22: cpu@16 {
compatible = "thead,c920", "riscv";
- reg = <22>;
+ reg = <0x16>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller {
};
};
- cpu23: cpu@23 {
+ cpu23: cpu@17 {
compatible = "thead,c920", "riscv";
- reg = <23>;
+ reg = <0x17>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller {
};
};
- cpu24: cpu@24 {
+ cpu24: cpu@18 {
compatible = "thead,c920", "riscv";
- reg = <24>;
+ reg = <0x18>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller {
};
};
- cpu25: cpu@25 {
+ cpu25: cpu@19 {
compatible = "thead,c920", "riscv";
- reg = <25>;
+ reg = <0x19>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller {
};
};
- cpu26: cpu@26 {
+ cpu26: cpu@1a {
compatible = "thead,c920", "riscv";
- reg = <26>;
+ reg = <0x1a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller {
};
};
- cpu27: cpu@27 {
+ cpu27: cpu@1b {
compatible = "thead,c920", "riscv";
- reg = <27>;
+ reg = <0x1b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller {
};
};
- cpu28: cpu@28 {
+ cpu28: cpu@1c {
compatible = "thead,c920", "riscv";
- reg = <28>;
+ reg = <0x1c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller {
};
};
- cpu29: cpu@29 {
+ cpu29: cpu@1d {
compatible = "thead,c920", "riscv";
- reg = <29>;
+ reg = <0x1d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller {
};
};
- cpu30: cpu@30 {
+ cpu30: cpu@1e {
compatible = "thead,c920", "riscv";
- reg = <30>;
+ reg = <0x1e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller {
};
};
- cpu31: cpu@31 {
+ cpu31: cpu@1f {
compatible = "thead,c920", "riscv";
- reg = <31>;
+ reg = <0x1f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller {
};
};
- cpu32: cpu@32 {
+ cpu32: cpu@20 {
compatible = "thead,c920", "riscv";
- reg = <32>;
+ reg = <0x20>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller {
};
};
- cpu33: cpu@33 {
+ cpu33: cpu@21 {
compatible = "thead,c920", "riscv";
- reg = <33>;
+ reg = <0x21>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller {
};
};
- cpu34: cpu@34 {
+ cpu34: cpu@22 {
compatible = "thead,c920", "riscv";
- reg = <34>;
+ reg = <0x22>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller {
};
};
- cpu35: cpu@35 {
+ cpu35: cpu@23 {
compatible = "thead,c920", "riscv";
- reg = <35>;
+ reg = <0x23>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller {
};
};
- cpu36: cpu@36 {
+ cpu36: cpu@24 {
compatible = "thead,c920", "riscv";
- reg = <36>;
+ reg = <0x24>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller {
};
};
- cpu37: cpu@37 {
+ cpu37: cpu@25 {
compatible = "thead,c920", "riscv";
- reg = <37>;
+ reg = <0x25>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller {
};
};
- cpu38: cpu@38 {
+ cpu38: cpu@26 {
compatible = "thead,c920", "riscv";
- reg = <38>;
+ reg = <0x26>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller {
};
};
- cpu39: cpu@39 {
+ cpu39: cpu@27 {
compatible = "thead,c920", "riscv";
- reg = <39>;
+ reg = <0x27>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller {
};
};
- cpu40: cpu@40 {
+ cpu40: cpu@28 {
compatible = "thead,c920", "riscv";
- reg = <40>;
+ reg = <0x28>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller {
};
};
- cpu41: cpu@41 {
+ cpu41: cpu@29 {
compatible = "thead,c920", "riscv";
- reg = <41>;
+ reg = <0x29>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller {
};
};
- cpu42: cpu@42 {
+ cpu42: cpu@2a {
compatible = "thead,c920", "riscv";
- reg = <42>;
+ reg = <0x2a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller {
};
};
- cpu43: cpu@43 {
+ cpu43: cpu@2b {
compatible = "thead,c920", "riscv";
- reg = <43>;
+ reg = <0x2b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller {
};
};
- cpu44: cpu@44 {
+ cpu44: cpu@2c {
compatible = "thead,c920", "riscv";
- reg = <44>;
+ reg = <0x2c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller {
};
};
- cpu45: cpu@45 {
+ cpu45: cpu@2d {
compatible = "thead,c920", "riscv";
- reg = <45>;
+ reg = <0x2d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller {
};
};
- cpu46: cpu@46 {
+ cpu46: cpu@2e {
compatible = "thead,c920", "riscv";
- reg = <46>;
+ reg = <0x2e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller {
};
};
- cpu47: cpu@47 {
+ cpu47: cpu@2f {
compatible = "thead,c920", "riscv";
- reg = <47>;
+ reg = <0x2f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller {
};
};
- cpu48: cpu@48 {
+ cpu48: cpu@30 {
compatible = "thead,c920", "riscv";
- reg = <48>;
+ reg = <0x30>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller {
};
};
- cpu49: cpu@49 {
+ cpu49: cpu@31 {
compatible = "thead,c920", "riscv";
- reg = <49>;
+ reg = <0x31>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller {
};
};
- cpu50: cpu@50 {
+ cpu50: cpu@32 {
compatible = "thead,c920", "riscv";
- reg = <50>;
+ reg = <0x32>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller {
};
};
- cpu51: cpu@51 {
+ cpu51: cpu@33 {
compatible = "thead,c920", "riscv";
- reg = <51>;
+ reg = <0x33>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller {
};
};
- cpu52: cpu@52 {
+ cpu52: cpu@34 {
compatible = "thead,c920", "riscv";
- reg = <52>;
+ reg = <0x34>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller {
};
};
- cpu53: cpu@53 {
+ cpu53: cpu@35 {
compatible = "thead,c920", "riscv";
- reg = <53>;
+ reg = <0x35>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller {
};
};
- cpu54: cpu@54 {
+ cpu54: cpu@36 {
compatible = "thead,c920", "riscv";
- reg = <54>;
+ reg = <0x36>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller {
};
};
- cpu55: cpu@55 {
+ cpu55: cpu@37 {
compatible = "thead,c920", "riscv";
- reg = <55>;
+ reg = <0x37>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller {
};
};
- cpu56: cpu@56 {
+ cpu56: cpu@38 {
compatible = "thead,c920", "riscv";
- reg = <56>;
+ reg = <0x38>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller {
};
};
- cpu57: cpu@57 {
+ cpu57: cpu@39 {
compatible = "thead,c920", "riscv";
- reg = <57>;
+ reg = <0x39>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller {
};
};
- cpu58: cpu@58 {
+ cpu58: cpu@3a {
compatible = "thead,c920", "riscv";
- reg = <58>;
+ reg = <0x3a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller {
};
};
- cpu59: cpu@59 {
+ cpu59: cpu@3b {
compatible = "thead,c920", "riscv";
- reg = <59>;
+ reg = <0x3b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller {
};
};
- cpu60: cpu@60 {
+ cpu60: cpu@3c {
compatible = "thead,c920", "riscv";
- reg = <60>;
+ reg = <0x3c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller {
};
};
- cpu61: cpu@61 {
+ cpu61: cpu@3d {
compatible = "thead,c920", "riscv";
- reg = <61>;
+ reg = <0x3d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller {
};
};
- cpu62: cpu@62 {
+ cpu62: cpu@3e {
compatible = "thead,c920", "riscv";
- reg = <62>;
+ reg = <0x3e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller {
};
};
- cpu63: cpu@63 {
+ cpu63: cpu@3f {
compatible = "thead,c920", "riscv";
- reg = <63>;
+ reg = <0x3f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
--
2.53.0
^ permalink raw reply related
* [PATCH 0/2] riscv: dts: sophgo: Fix CPU unit address for SG2042/SG2044
From: Inochi Amaoto @ 2026-04-06 23:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Han Gao, Nutty Liu, Guodong Xu, Guo Ren,
Xiaoguang Xing
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
The CPU unit addres for SG2042/SG2044 misused the decimal number for the
unit address, Refer to this discussion in the Link, it should be in the
hex format.
Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/
Inochi Amaoto (2):
riscv: dts: sophgo: sg2044: use hex for CPU unit address
riscv: dts: sophgo: sg2042: use hex for CPU unit address
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++----------
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++----------
2 files changed, 236 insertions(+), 236 deletions(-)
--
2.53.0
^ permalink raw reply
* [PATCH v5 8/9] driver core: Replace dev->of_node_reused with dev_of_node_reused()
From: Douglas Anderson @ 2026-04-06 23:23 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rafael J . Wysocki, Danilo Krummrich,
Alan Stern
Cc: Alexey Kardashevskiy, Johan Hovold, Eric Dumazet, Leon Romanovsky,
Christoph Hellwig, Robin Murphy, maz, Alexander Lobakin,
Saravana Kannan, Douglas Anderson, Mark Brown, alexander.stein,
andrew, andrew, andriy.shevchenko, astewart, bhelgaas, brgl,
davem, devicetree, driver-core, hkallweit1, jirislaby, joel, kees,
kuba, lgirdwood, linux-arm-kernel, linux-aspeed, linux-kernel,
linux-pci, linux-serial, linux-usb, linux, mani, netdev, pabeni,
robh
In-Reply-To: <20260406232444.3117516-1-dianders@chromium.org>
In C, bitfields are not necessarily safe to modify from multiple
threads without locking. Switch "of_node_reused" over to the "flags"
field so modifications are safe.
Cc: Johan Hovold <johan@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Rafael J. Wysocki (Intel) <rafael@kernel.org>
Reviewed-by: Danilo Krummrich <dakr@kernel.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
Not fixing any known bugs; problem is theoretical and found by code
inspection. Change is done somewhat manually and only lightly tested
(mostly compile-time tested).
(no changes since v4)
Changes in v4:
- Use accessor functions for flags
Changes in v3:
- New
drivers/base/core.c | 2 +-
drivers/base/pinctrl.c | 2 +-
drivers/base/platform.c | 2 +-
drivers/net/pcs/pcs-xpcs-plat.c | 2 +-
drivers/of/device.c | 6 +++---
drivers/pci/of.c | 2 +-
drivers/pci/pwrctrl/core.c | 2 +-
drivers/regulator/bq257xx-regulator.c | 2 +-
drivers/regulator/rk808-regulator.c | 2 +-
drivers/tty/serial/serial_base_bus.c | 2 +-
drivers/usb/gadget/udc/aspeed-vhub/dev.c | 2 +-
include/linux/device.h | 7 ++++---
12 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 8a83d7c93361..30825bf83234 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -5283,7 +5283,7 @@ void device_set_of_node_from_dev(struct device *dev, const struct device *dev2)
{
of_node_put(dev->of_node);
dev->of_node = of_node_get(dev2->of_node);
- dev->of_node_reused = true;
+ dev_set_of_node_reused(dev);
}
EXPORT_SYMBOL_GPL(device_set_of_node_from_dev);
diff --git a/drivers/base/pinctrl.c b/drivers/base/pinctrl.c
index 6e250272c843..0bbc83231234 100644
--- a/drivers/base/pinctrl.c
+++ b/drivers/base/pinctrl.c
@@ -24,7 +24,7 @@ int pinctrl_bind_pins(struct device *dev)
{
int ret;
- if (dev->of_node_reused)
+ if (dev_of_node_reused(dev))
return 0;
dev->pins = devm_kzalloc(dev, sizeof(*(dev->pins)), GFP_KERNEL);
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index d44591d52e36..199e6fb25770 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -856,7 +856,7 @@ struct platform_device *platform_device_register_full(
pdev->dev.parent = pdevinfo->parent;
pdev->dev.fwnode = pdevinfo->fwnode;
pdev->dev.of_node = of_node_get(to_of_node(pdev->dev.fwnode));
- pdev->dev.of_node_reused = pdevinfo->of_node_reused;
+ dev_assign_of_node_reused(&pdev->dev, pdevinfo->of_node_reused);
if (pdevinfo->dma_mask) {
pdev->platform_dma_mask = pdevinfo->dma_mask;
diff --git a/drivers/net/pcs/pcs-xpcs-plat.c b/drivers/net/pcs/pcs-xpcs-plat.c
index b8c48f9effbf..f4b1b8246ce9 100644
--- a/drivers/net/pcs/pcs-xpcs-plat.c
+++ b/drivers/net/pcs/pcs-xpcs-plat.c
@@ -349,7 +349,7 @@ static int xpcs_plat_init_dev(struct dw_xpcs_plat *pxpcs)
* up later. Make sure DD-core is aware of the OF-node being re-used.
*/
device_set_node(&mdiodev->dev, fwnode_handle_get(dev_fwnode(dev)));
- mdiodev->dev.of_node_reused = true;
+ dev_set_of_node_reused(&mdiodev->dev);
/* Pass the data further so the DW XPCS driver core could use it */
mdiodev->dev.platform_data = (void *)device_get_match_data(dev);
diff --git a/drivers/of/device.c b/drivers/of/device.c
index f7e75e527667..be4e1584e0af 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -26,7 +26,7 @@
const struct of_device_id *of_match_device(const struct of_device_id *matches,
const struct device *dev)
{
- if (!matches || !dev->of_node || dev->of_node_reused)
+ if (!matches || !dev->of_node || dev_of_node_reused(dev))
return NULL;
return of_match_node(matches, dev->of_node);
}
@@ -192,7 +192,7 @@ ssize_t of_device_modalias(struct device *dev, char *str, ssize_t len)
{
ssize_t sl;
- if (!dev || !dev->of_node || dev->of_node_reused)
+ if (!dev || !dev->of_node || dev_of_node_reused(dev))
return -ENODEV;
sl = of_modalias(dev->of_node, str, len - 2);
@@ -254,7 +254,7 @@ int of_device_uevent_modalias(const struct device *dev, struct kobj_uevent_env *
{
int sl;
- if ((!dev) || (!dev->of_node) || dev->of_node_reused)
+ if ((!dev) || (!dev->of_node) || dev_of_node_reused(dev))
return -ENODEV;
/* Devicetree modalias is tricky, we add it in 2 steps */
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index 9f8eb5df279e..1f9b669abdb0 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -38,7 +38,7 @@ int pci_set_of_node(struct pci_dev *dev)
struct device *pdev __free(put_device) =
bus_find_device_by_of_node(&platform_bus_type, node);
if (pdev)
- dev->bus->dev.of_node_reused = true;
+ dev_set_of_node_reused(&dev->bus->dev);
device_set_node(&dev->dev, of_fwnode_handle(no_free_ptr(node)));
return 0;
diff --git a/drivers/pci/pwrctrl/core.c b/drivers/pci/pwrctrl/core.c
index 7754baed67f2..72963a92362a 100644
--- a/drivers/pci/pwrctrl/core.c
+++ b/drivers/pci/pwrctrl/core.c
@@ -39,7 +39,7 @@ static int pci_pwrctrl_notify(struct notifier_block *nb, unsigned long action,
* If we got here then the PCI device is the second after the
* power control platform device. Mark its OF node as reused.
*/
- dev->of_node_reused = true;
+ dev_set_of_node_reused(dev);
break;
}
diff --git a/drivers/regulator/bq257xx-regulator.c b/drivers/regulator/bq257xx-regulator.c
index dab8f1ab4450..40e0f1a7ae81 100644
--- a/drivers/regulator/bq257xx-regulator.c
+++ b/drivers/regulator/bq257xx-regulator.c
@@ -143,7 +143,7 @@ static int bq257xx_regulator_probe(struct platform_device *pdev)
struct regulator_config cfg = {};
pdev->dev.of_node = pdev->dev.parent->of_node;
- pdev->dev.of_node_reused = true;
+ dev_set_of_node_reused(&pdev->dev);
pdata = devm_kzalloc(&pdev->dev, sizeof(struct bq257xx_reg_data), GFP_KERNEL);
if (!pdata)
diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c
index e66408f23bb6..8297d31cde9f 100644
--- a/drivers/regulator/rk808-regulator.c
+++ b/drivers/regulator/rk808-regulator.c
@@ -2115,7 +2115,7 @@ static int rk808_regulator_probe(struct platform_device *pdev)
int ret, i, nregulators;
pdev->dev.of_node = pdev->dev.parent->of_node;
- pdev->dev.of_node_reused = true;
+ dev_set_of_node_reused(&pdev->dev);
regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!regmap)
diff --git a/drivers/tty/serial/serial_base_bus.c b/drivers/tty/serial/serial_base_bus.c
index a12935f6b992..5f23284a8778 100644
--- a/drivers/tty/serial/serial_base_bus.c
+++ b/drivers/tty/serial/serial_base_bus.c
@@ -74,7 +74,7 @@ static int serial_base_device_init(struct uart_port *port,
dev->parent = parent_dev;
dev->bus = &serial_base_bus_type;
dev->release = release;
- dev->of_node_reused = true;
+ dev_set_of_node_reused(dev);
device_set_node(dev, fwnode_handle_get(dev_fwnode(parent_dev)));
diff --git a/drivers/usb/gadget/udc/aspeed-vhub/dev.c b/drivers/usb/gadget/udc/aspeed-vhub/dev.c
index 2ecd049dacc2..8b9449d16324 100644
--- a/drivers/usb/gadget/udc/aspeed-vhub/dev.c
+++ b/drivers/usb/gadget/udc/aspeed-vhub/dev.c
@@ -593,7 +593,7 @@ int ast_vhub_init_dev(struct ast_vhub *vhub, unsigned int idx)
d->gadget.max_speed = USB_SPEED_HIGH;
d->gadget.speed = USB_SPEED_UNKNOWN;
d->gadget.dev.of_node = vhub->pdev->dev.of_node;
- d->gadget.dev.of_node_reused = true;
+ dev_set_of_node_reused(&d->gadget.dev);
rc = usb_add_gadget_udc(d->port_dev, &d->gadget);
if (rc != 0)
diff --git a/include/linux/device.h b/include/linux/device.h
index 5b0fb6ad4c72..a79865a212e9 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -483,6 +483,8 @@ struct device_physical_location {
* driver/bus sync_state() callback.
* @DEV_FLAG_DMA_COHERENT: This particular device is dma coherent, even if the
* architecture supports non-coherent devices.
+ * @DEV_FLAG_OF_NODE_REUSED: Set if the device-tree node is shared with an
+ * ancestor device.
*/
enum struct_device_flags {
DEV_FLAG_READY_TO_PROBE = 0,
@@ -492,6 +494,7 @@ enum struct_device_flags {
DEV_FLAG_DMA_OPS_BYPASS = 4,
DEV_FLAG_STATE_SYNCED = 5,
DEV_FLAG_DMA_COHERENT = 6,
+ DEV_FLAG_OF_NODE_REUSED = 7,
DEV_FLAG_COUNT
};
@@ -573,8 +576,6 @@ enum struct_device_flags {
*
* @offline_disabled: If set, the device is permanently online.
* @offline: Set after successful invocation of bus type's .offline().
- * @of_node_reused: Set if the device-tree node is shared with an ancestor
- * device.
* @flags: DEV_FLAG_XXX flags. Use atomic bitfield operations to modify.
*
* At the lowest level, every device in a Linux system is represented by an
@@ -681,7 +682,6 @@ struct device {
bool offline_disabled:1;
bool offline:1;
- bool of_node_reused:1;
DECLARE_BITMAP(flags, DEV_FLAG_COUNT);
};
@@ -715,6 +715,7 @@ __create_dev_flag_accessors(dma_skip_sync, DEV_FLAG_DMA_SKIP_SYNC);
__create_dev_flag_accessors(dma_ops_bypass, DEV_FLAG_DMA_OPS_BYPASS);
__create_dev_flag_accessors(state_synced, DEV_FLAG_STATE_SYNCED);
__create_dev_flag_accessors(dma_coherent, DEV_FLAG_DMA_COHERENT);
+__create_dev_flag_accessors(of_node_reused, DEV_FLAG_OF_NODE_REUSED);
#undef __create_dev_flag_accessors
--
2.53.0.1213.gd9a14994de-goog
^ permalink raw reply related
* [PATCH v5 0/9] driver core: Fix some race conditions
From: Douglas Anderson @ 2026-04-06 23:22 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rafael J . Wysocki, Danilo Krummrich,
Alan Stern
Cc: Alexey Kardashevskiy, Johan Hovold, Eric Dumazet, Leon Romanovsky,
Christoph Hellwig, Robin Murphy, maz, Alexander Lobakin,
Saravana Kannan, Douglas Anderson, Andrew Morton, Frank.Li,
Jason Gunthorpe, alex, alexander.stein, andre.przywara, andrew,
andrew, andriy.shevchenko, aou, ardb, astewart, bhelgaas, brgl,
broonie, catalin.marinas, chleroy, davem, david, devicetree,
dmaengine, driver-core, gbatra, gregory.clement, hkallweit1,
iommu, jirislaby, joel, joro, kees, kevin.brodsky, kuba, lenb,
lgirdwood, linux-acpi, linux-arm-kernel, linux-aspeed, linux-cxl,
linux-kernel, linux-mips, linux-mm, linux-pci, linux-riscv,
linux-serial, linux-snps-arc, linux-usb, linux, linuxppc-dev,
m.szyprowski, maddy, mani, miko.lenczewski, mpe, netdev, npiggin,
osalvador, oupton, pabeni, palmer, peter.ujfalusi, peterz, pjw,
robh, sebastian.hesselbarth, tglx, tsbogend, vgupta, vkoul, will,
willy, yangyicong, yeoreum.yun
The main goal of this series is to fix the observed bug talked about
in the first patch ("driver core: Don't let a device probe until it's
ready"). That patch fixes a problem that has been observed in the real
world and could land even if the rest of the patches are found
unacceptable or need to be spun.
That said, during patch review Danilo correctly pointed out that many
of the bitfield accesses in "struct device" are unsafe. I added a
bunch of patches in the series to address each one.
Danilo said he's most worried about "can_match", so I put that one
first. After that, I tried to transition bitfields to flags in reverse
order to when the bitfield was added.
Even if transitioning from bitfields to flags isn't truly needed for
correctness, it seems silly (and wasteful of space in struct device)
to have some in bitfields and some as flags. Thus I didn't spend time
for each bitfield showing that it's truly needed for correctness.
Transition was done semi manually. Presumably someone skilled at
coccinelle could do a better job, but I just used sed in a heavy-
handed manner and then reviewed/fixed the results, undoing anything my
script got wrong. My terrible/ugly script was:
var=can_match
caps="${var^^}"
for f in $(git grep -l "[>\.]${var}[^1-9_a-zA-Z\[]"); do
echo $f
sed -i~ -e "s/\([a-zA-Z_0-9\.>()-][a-zA-Z_0-9\.>()-]*\)->${var} = true/set_bit(DEV_FLAG_${caps}, \&\\1->flags)/" "$f"
sed -i~ -e "s/\([a-zA-Z_0-9\.>()-][a-zA-Z_0-9\.>()-]*\)\.${var} = true/dev_set_${caps}(\&\\1)/" "$f"
sed -i~ -e "s/\([a-zA-Z_0-9\.>()-][a-zA-Z_0-9\.>()-]*\)->${var} = false/clear_bit(DEV_FLAG_${caps}, \&\\1->flags)/" "$f"
sed -i~ -e "s/\([a-zA-Z_0-9\.>()-][a-zA-Z_0-9\.>()-]*\)\.${var} = false/dev_clear_${caps}(\&\\1)/" "$f"
sed -i~ -e "s/\([a-zA-Z_0-9\.>()-][a-zA-Z_0-9\.>()-]*\)->${var} = \([^;]*\)/assign_bit(DEV_FLAG_${caps}, \&\\1->flags, \\2)/" "$f"
sed -i~ -e "s/\([a-zA-Z_0-9\.>()-][a-zA-Z_0-9\.>()-]*\)\.${var} = \([^;]*\)/dev_assign_${caps}(\&\\1, \\2)/" "$f"
sed -i~ -e "s/\([a-zA-Z_0-9\.>()-][a-zA-Z_0-9\.>()-]*\)->${var}\([^1-9_a-zA-Z\[]\)/test_bit(DEV_FLAG_${caps}, \&\\1->flags)\\2/" "$f"
sed -i~ -e "s/\([a-zA-Z_0-9\.>()-][a-zA-Z_0-9\.>()-]*\)\.${var}\([^1-9_a-zA-Z\[]\)/dev_${caps}(\&\\1)\\2/" "$f"
done
From v3 to v4, I transitioned to accessor functions with another ugly
sed script. I had git format the old patches, then transformed them
with:
for f in *.patch; do
echo $f
sed -i~ -e "s/test_and_set_bit(DEV_FLAG_\([^,]*\), \&\(.*\)->flags)/dev_test_and_set_\\L\\1(\\2)/" "$f"
sed -i~ -e "s/test_and_set_bit(DEV_FLAG_\([^,]*\), \(.*\)\.flags)/dev_test_and_set_\\L\\1(\\2)/" "$f"
sed -i~ -e "s/test_bit(DEV_FLAG_\([^,]*\), \&\(.*\)->flags)/dev_\\L\\1(\\2)/" "$f"
sed -i~ -e "s/test_bit(DEV_FLAG_\([^,]*\), \(.*\)\.flags)/dev_\\L\\1(\\2)/" "$f"
sed -i~ -e "s/set_bit(DEV_FLAG_\([^,]*\), \&\(.*\)->flags)/dev_set_\\L\\1(\\2)/" "$f"
sed -i~ -e "s/set_bit(DEV_FLAG_\([^,]*\), \(.*\)\.flags)/dev_set_\\L\\1(\\2)/" "$f"
sed -i~ -e "s/clear_bit(DEV_FLAG_\([^,]*\), \&\(.*\)->flags)/dev_clear_\\L\\1(\\2)/" "$f"
sed -i~ -e "s/clear_bit(DEV_FLAG_\([^,]*\), \(.*\)\.flags)/dev_clear_\\L\\1(\\2)/" "$f"
sed -i~ -e "s/assign_bit(DEV_FLAG_\([^,]*\), \&\(.*\)->flags, \(.*\))/dev_assign_\\L\\1(\\2, \\3)/" "$f"
sed -i~ -e "s/assign_bit(DEV_FLAG_\([^,]*\), \(.*\)\.flags, \(.*\))/dev_assign_\\L\\1(\\2, \\3)/" "$f"
done
...and then did a few manual touchups for spacing.
I only marked the first patch as a "Fix" since it is the only one
fixing observed problems. Other patches could be considered fixes too
if folks want.
I tested the first patch in the series backported to kernel 6.6 on the
Pixel phone that was experiencing the race. I added extra printouts to
make sure that the problem was hitting / addressed. The rest of the
patches are tested with allmodconfig with arm32, arm64, ppc, and
x86. I boot tested on an arm64 Chromebook running mainline.
Changes in v5:
- ready_to_prove => ready_to_probe typo
- device_lock() while calling dev_set_ready_to_probe()
- Add comment before "can_match = true" from Danilo.
- undef __create_dev_flag_accessors
Changes in v4:
- Use accessor functions for flags
Changes in v3:
- Use a new "flags" bitfield
- Add missing \n in probe error message
Changes in v2:
- Instead of adjusting the ordering, use "ready_to_probe" flag
Douglas Anderson (9):
driver core: Don't let a device probe until it's ready
driver core: Replace dev->can_match with dev_can_match()
driver core: Replace dev->dma_iommu with dev_dma_iommu()
driver core: Replace dev->dma_skip_sync with dev_dma_skip_sync()
driver core: Replace dev->dma_ops_bypass with dev_dma_ops_bypass()
driver core: Replace dev->state_synced with dev_state_synced()
driver core: Replace dev->dma_coherent with dev_dma_coherent()
driver core: Replace dev->of_node_reused with dev_of_node_reused()
driver core: Replace dev->offline + ->offline_disabled with accessors
arch/arc/mm/dma.c | 4 +-
arch/arm/mach-highbank/highbank.c | 2 +-
arch/arm/mach-mvebu/coherency.c | 2 +-
arch/arm/mm/dma-mapping-nommu.c | 4 +-
arch/arm/mm/dma-mapping.c | 28 ++--
arch/arm64/kernel/cpufeature.c | 2 +-
arch/arm64/mm/dma-mapping.c | 2 +-
arch/mips/mm/dma-noncoherent.c | 2 +-
arch/powerpc/kernel/dma-iommu.c | 8 +-
.../platforms/pseries/hotplug-memory.c | 4 +-
arch/riscv/mm/dma-noncoherent.c | 2 +-
drivers/acpi/scan.c | 2 +-
drivers/base/core.c | 55 +++++---
drivers/base/cpu.c | 4 +-
drivers/base/dd.c | 36 ++++--
drivers/base/memory.c | 2 +-
drivers/base/pinctrl.c | 2 +-
drivers/base/platform.c | 2 +-
drivers/dma/ti/k3-udma-glue.c | 6 +-
drivers/dma/ti/k3-udma.c | 6 +-
drivers/iommu/dma-iommu.c | 9 +-
drivers/iommu/iommu.c | 5 +-
drivers/net/pcs/pcs-xpcs-plat.c | 2 +-
drivers/of/device.c | 6 +-
drivers/pci/of.c | 2 +-
drivers/pci/pwrctrl/core.c | 2 +-
drivers/regulator/bq257xx-regulator.c | 2 +-
drivers/regulator/rk808-regulator.c | 2 +-
drivers/tty/serial/serial_base_bus.c | 2 +-
drivers/usb/gadget/udc/aspeed-vhub/dev.c | 2 +-
include/linux/device.h | 122 ++++++++++++------
include/linux/dma-map-ops.h | 6 +-
include/linux/dma-mapping.h | 2 +-
include/linux/iommu-dma.h | 3 +-
kernel/cpu.c | 4 +-
kernel/dma/mapping.c | 12 +-
mm/hmm.c | 2 +-
37 files changed, 218 insertions(+), 142 deletions(-)
--
2.53.0.1213.gd9a14994de-goog
^ permalink raw reply
* [PATCH v2 2/2] interconnect: qcom: add Hawi interconnect provider driver
From: Vivek Aknurwar @ 2026-04-06 23:04 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, Mike Tipton,
Vivek Aknurwar, Krzysztof Kozlowski
In-Reply-To: <20260406-icc-hawi-v2-0-6cfee87a1d25@oss.qualcomm.com>
Add driver for the Qualcomm interconnect buses found in Hawi
based platforms. The topology consists of several NoCs that are
controlled by a remote processor that collects the aggregated
bandwidth for each master-slave pair.
Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
drivers/interconnect/qcom/Kconfig | 9 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/hawi.c | 2021 ++++++++++++++++++++++++++++++++++++
3 files changed, 2032 insertions(+)
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index bb1cb8a640c1..896b07589386 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -17,6 +17,15 @@ config INTERCONNECT_QCOM_GLYMUR
This is a driver for the Qualcomm Network-on-Chip on glymur-based
platforms.
+config INTERCONNECT_QCOM_HAWI
+ tristate "Qualcomm HAWI interconnect driver"
+ depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
+ select INTERCONNECT_QCOM_RPMH
+ select INTERCONNECT_QCOM_BCM_VOTER
+ help
+ This is a driver for the Qualcomm Network-on-Chip on hawi-based
+ platforms.
+
config INTERCONNECT_QCOM_KAANAPALI
tristate "Qualcomm KAANAPALI interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index 6eedff043b41..750ff9fd5b46 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM) += interconnect_qcom.o
interconnect_qcom-y := icc-common.o
icc-bcm-voter-objs := bcm-voter.o
qnoc-glymur-objs := glymur.o
+qnoc-hawi-objs := hawi.o
qnoc-kaanapali-objs := kaanapali.o
qnoc-milos-objs := milos.o
qnoc-msm8909-objs := msm8909.o
@@ -49,6 +50,7 @@ icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) += qnoc-glymur.o
+obj-$(CONFIG_INTERCONNECT_QCOM_HAWI) += qnoc-hawi.o
obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) += qnoc-kaanapali.o
obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) += qnoc-milos.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o
diff --git a/drivers/interconnect/qcom/hawi.c b/drivers/interconnect/qcom/hawi.c
new file mode 100644
index 000000000000..ef01ed5624d2
--- /dev/null
+++ b/drivers/interconnect/qcom/hawi.c
@@ -0,0 +1,2021 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
+
+#include "bcm-voter.h"
+#include "icc-rpmh.h"
+
+static struct qcom_icc_node ddr_eff_veto_slave = {
+ .name = "ddr_eff_veto_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup0_core_slave = {
+ .name = "qup0_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup1_core_slave = {
+ .name = "qup1_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup2_core_slave = {
+ .name = "qup2_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup3_core_slave = {
+ .name = "qup3_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup4_core_slave = {
+ .name = "qup4_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_aoss = {
+ .name = "qhs_aoss",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipa = {
+ .name = "qhs_ipa",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipc_router_fence = {
+ .name = "qhs_ipc_router_fence",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_soccp = {
+ .name = "qhs_soccp",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_tme_cfg = {
+ .name = "qhs_tme_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_ddrss_cfg = {
+ .name = "qss_ddrss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qxs_imem = {
+ .name = "qxs_imem",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node xs_pcie = {
+ .name = "xs_pcie",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qhs_lpi_cc = {
+ .name = "qhs_lpi_cc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_lb = {
+ .name = "qns_lb",
+ .channels = 4,
+ .buswidth = 32,
+};
+
+static struct qcom_icc_node srvc_llclpi_noc = {
+ .name = "srvc_llclpi_noc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_llclpi_noc_chipcx = {
+ .name = "srvc_llclpi_noc_chipcx",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node ebi = {
+ .name = "ebi",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node ddr_rt_slave = {
+ .name = "ddr_rt_slave",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_pcie_aggre_noc = {
+ .name = "srvc_pcie_aggre_noc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ahb2phy0 = {
+ .name = "qhs_ahb2phy0",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_boot_rom = {
+ .name = "qhs_boot_rom",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_camera_cfg = {
+ .name = "qhs_camera_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_clk_ctl = {
+ .name = "qhs_clk_ctl",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_crypto_cfg = {
+ .name = "qhs_crypto_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_display_cfg = {
+ .name = "qhs_display_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_eva_cfg = {
+ .name = "qhs_eva_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_gpuss_cfg = {
+ .name = "qhs_gpuss_cfg",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qhs_i2c = {
+ .name = "qhs_i2c",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_imem_cfg = {
+ .name = "qhs_imem_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipc_router = {
+ .name = "qhs_ipc_router",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_iris_cfg = {
+ .name = "qhs_iris_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_mss_cfg = {
+ .name = "qhs_mss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie_cfg = {
+ .name = "qhs_pcie_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie_g4x1_cfg = {
+ .name = "qhs_pcie_g4x1_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_prng = {
+ .name = "qhs_prng",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qspi = {
+ .name = "qhs_qspi",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup1 = {
+ .name = "qhs_qup1",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup2 = {
+ .name = "qhs_qup2",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup3 = {
+ .name = "qhs_qup3",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup4 = {
+ .name = "qhs_qup4",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_sdc2 = {
+ .name = "qhs_sdc2",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_sdc4 = {
+ .name = "qhs_sdc4",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_tlmm = {
+ .name = "qhs_tlmm",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ufs_mem_cfg = {
+ .name = "qhs_ufs_mem_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_usb3 = {
+ .name = "qhs_usb3",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
+ .name = "qhs_vsense_ctrl_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_qdss_cfg = {
+ .name = "qss_qdss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_qdss_stm = {
+ .name = "qss_qdss_stm",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_tcsr = {
+ .name = "qss_tcsr",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node xs_sys_tcu_cfg = {
+ .name = "xs_sys_tcu_cfg",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node ddr_eff_veto_master = {
+ .name = "ddr_eff_veto_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ddr_eff_veto_slave },
+};
+
+static struct qcom_icc_node qup0_core_master = {
+ .name = "qup0_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup0_core_slave },
+};
+
+static struct qcom_icc_node qup1_core_master = {
+ .name = "qup1_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup1_core_slave },
+};
+
+static struct qcom_icc_node qup2_core_master = {
+ .name = "qup2_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup2_core_slave },
+};
+
+static struct qcom_icc_node qup3_core_master = {
+ .name = "qup3_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup3_core_slave },
+};
+
+static struct qcom_icc_node qup4_core_master = {
+ .name = "qup4_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup4_core_slave },
+};
+
+static struct qcom_icc_node qnm_gemnoc_pcie = {
+ .name = "qnm_gemnoc_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .link_nodes = { &xs_pcie },
+};
+
+static struct qcom_icc_node qnm_lpiaon_noc_llclpi_noc = {
+ .name = "qnm_lpiaon_noc_llclpi_noc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 4,
+ .link_nodes = { &qhs_lpi_cc, &qns_lb,
+ &srvc_llclpi_noc, &srvc_llclpi_noc_chipcx },
+};
+
+static struct qcom_icc_node llcc_mc = {
+ .name = "llcc_mc",
+ .channels = 4,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ebi },
+};
+
+static struct qcom_icc_node ddr_rt_mc = {
+ .name = "ddr_rt_mc",
+ .channels = 4,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ddr_rt_slave },
+};
+
+static struct qcom_icc_node qsm_pcie_anoc_cfg = {
+ .name = "qsm_pcie_anoc_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &srvc_pcie_aggre_noc },
+};
+
+static struct qcom_icc_node qsm_cfg_east = {
+ .name = "qsm_cfg_east",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 4,
+ .link_nodes = { &qhs_crypto_cfg, &qhs_gpuss_cfg,
+ &qhs_qup2, &qhs_vsense_ctrl_cfg },
+};
+
+static struct qcom_icc_node qsm_cfg_mm = {
+ .name = "qsm_cfg_mm",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 5,
+ .link_nodes = { &qhs_boot_rom, &qhs_camera_cfg,
+ &qhs_display_cfg, &qhs_eva_cfg,
+ &qhs_iris_cfg },
+};
+
+static struct qcom_icc_node qsm_cfg_north = {
+ .name = "qsm_cfg_north",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 5,
+ .link_nodes = { &qhs_pcie_cfg, &qhs_pcie_g4x1_cfg,
+ &qhs_qup3, &qhs_qup4,
+ &qhs_sdc2 },
+};
+
+static struct qcom_icc_node qsm_cfg_south = {
+ .name = "qsm_cfg_south",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 6,
+ .link_nodes = { &qhs_ahb2phy0, &qhs_qspi,
+ &qhs_qup1, &qhs_sdc4,
+ &qhs_ufs_mem_cfg, &qhs_usb3 },
+};
+
+static struct qcom_icc_node qsm_cfg_southwest = {
+ .name = "qsm_cfg_southwest",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 2,
+ .link_nodes = { &qhs_ipc_router, &qhs_mss_cfg },
+};
+
+static struct qcom_icc_node qns_llcc = {
+ .name = "qns_llcc",
+ .channels = 4,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &llcc_mc },
+};
+
+static struct qcom_icc_node qns_pcie = {
+ .name = "qns_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .link_nodes = { &qnm_gemnoc_pcie },
+};
+
+static struct qcom_icc_node qns_llc_lpinoc = {
+ .name = "qns_llc_lpinoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpiaon_noc_llclpi_noc },
+};
+
+static struct qcom_icc_node qss_pcie_anoc_cfg = {
+ .name = "qss_pcie_anoc_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_pcie_anoc_cfg },
+};
+
+static struct qcom_icc_node qss_stdst_east_cfg = {
+ .name = "qss_stdst_east_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_east },
+};
+
+static struct qcom_icc_node qss_stdst_mm_cfg = {
+ .name = "qss_stdst_mm_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_mm },
+};
+
+static struct qcom_icc_node qss_stdst_north_cfg = {
+ .name = "qss_stdst_north_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_north },
+};
+
+static struct qcom_icc_node qss_stdst_south_cfg = {
+ .name = "qss_stdst_south_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_south },
+};
+
+static struct qcom_icc_node qss_stdst_southwest_cfg = {
+ .name = "qss_stdst_southwest_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_southwest },
+};
+
+static struct qcom_icc_node alm_gic = {
+ .name = "alm_gic",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14d000 },
+ .prio = 4,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_node qnm_qpace = {
+ .name = "qnm_qpace",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x153000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_node qsm_cfg_center = {
+ .name = "qsm_cfg_center",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 10,
+ .link_nodes = { &qhs_clk_ctl, &qhs_i2c,
+ &qhs_imem_cfg, &qhs_prng,
+ &qhs_tlmm, &qss_pcie_anoc_cfg,
+ &qss_qdss_cfg, &qss_qdss_stm,
+ &qss_tcsr, &xs_sys_tcu_cfg },
+};
+
+static struct qcom_icc_node qss_stdst_center_cfg = {
+ .name = "qss_stdst_center_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_center },
+};
+
+static struct qcom_icc_node qsm_cnoc_main = {
+ .name = "qsm_cnoc_main",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 6,
+ .link_nodes = { &qss_stdst_center_cfg, &qss_stdst_east_cfg,
+ &qss_stdst_mm_cfg, &qss_stdst_north_cfg,
+ &qss_stdst_south_cfg, &qss_stdst_southwest_cfg },
+};
+
+static struct qcom_icc_node qss_cfg = {
+ .name = "qss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cnoc_main },
+};
+
+static struct qcom_icc_node qnm_gemnoc_cnoc = {
+ .name = "qnm_gemnoc_cnoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 8,
+ .link_nodes = { &qhs_aoss, &qhs_ipa,
+ &qhs_ipc_router_fence, &qhs_soccp,
+ &qhs_tme_cfg, &qss_cfg,
+ &qss_ddrss_cfg, &qxs_imem },
+};
+
+static struct qcom_icc_node qns_gem_noc_cnoc = {
+ .name = "qns_gem_noc_cnoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &qnm_gemnoc_cnoc },
+};
+
+static struct qcom_icc_node alm_gpu_tcu = {
+ .name = "alm_gpu_tcu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x145000 },
+ .prio = 1,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node alm_sys_tcu = {
+ .name = "alm_sys_tcu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x147000 },
+ .prio = 6,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node chm_apps = {
+ .name = "chm_apps",
+ .channels = 4,
+ .buswidth = 32,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_gpu = {
+ .name = "qnm_gpu",
+ .channels = 4,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 4,
+ .port_offsets = { 0x51000, 0x53000, 0xd1000, 0xd3000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_lpass_gemnoc = {
+ .name = "qnm_lpass_gemnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x149000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mdsp = {
+ .name = "qnm_mdsp",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mnoc_hf = {
+ .name = "qnm_mnoc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x55000, 0xd5000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mnoc_sf = {
+ .name = "qnm_mnoc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x57000, 0xd7000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_nsp_gemnoc = {
+ .name = "qnm_nsp_gemnoc",
+ .channels = 4,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 4,
+ .port_offsets = { 0x59000, 0x5b000, 0xd9000, 0xdb000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_pcie = {
+ .name = "qnm_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14b000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node qnm_snoc_sf = {
+ .name = "qnm_snoc_sf",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14f000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_wlan_q6 = {
+ .name = "qnm_wlan_q6",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
+ .name = "qns_lpass_ag_noc_gemnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpass_gemnoc },
+};
+
+static struct qcom_icc_node qns_mem_noc_hf = {
+ .name = "qns_mem_noc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_mnoc_hf },
+};
+
+static struct qcom_icc_node qns_mem_noc_sf = {
+ .name = "qns_mem_noc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_mnoc_sf },
+};
+
+static struct qcom_icc_node qns_nsp_gemnoc = {
+ .name = "qns_nsp_gemnoc",
+ .channels = 4,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_nsp_gemnoc },
+};
+
+static struct qcom_icc_node qns_pcie_gemnoc = {
+ .name = "qns_pcie_gemnoc",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .link_nodes = { &qnm_pcie },
+};
+
+static struct qcom_icc_node qns_gemnoc_sf = {
+ .name = "qns_gemnoc_sf",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_snoc_sf },
+};
+
+static struct qcom_icc_node qnm_lpiaon_noc = {
+ .name = "qnm_lpiaon_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_lpass_ag_noc_gemnoc },
+};
+
+static struct qcom_icc_node qnm_camnoc_hf = {
+ .name = "qnm_camnoc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x2a000, 0x2b000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = {
+ .name = "qnm_camnoc_nrt_icp_sf",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x2c000 },
+ .prio = 4,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = {
+ .name = "qnm_camnoc_rt_cdm_sf",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x38000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_camnoc_sf = {
+ .name = "qnm_camnoc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x2d000, 0x2e000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_mdp = {
+ .name = "qnm_mdp",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x2f000, 0x30000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_node qnm_mdss_dcp = {
+ .name = "qnm_mdss_dcp",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x39000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_vapss_hcp = {
+ .name = "qnm_vapss_hcp",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_cv_cpu = {
+ .name = "qnm_video_cv_cpu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x34000 },
+ .prio = 4,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_eva = {
+ .name = "qnm_video_eva",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x35000, 0x36000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_mvp = {
+ .name = "qnm_video_mvp",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x32000, 0x33000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_v_cpu = {
+ .name = "qnm_video_v_cpu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x37000 },
+ .prio = 4,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_nsp = {
+ .name = "qnm_nsp",
+ .channels = 4,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_nsp_gemnoc },
+};
+
+static struct qcom_icc_node xm_pcie = {
+ .name = "xm_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xc000 },
+ .prio = 3,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_node xm_pcie_g4x1 = {
+ .name = "xm_pcie_g4x1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xd000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_node qnm_aggre_noc = {
+ .name = "qnm_aggre_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x20000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qnm_apss_noc = {
+ .name = "qnm_apss_noc",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x1e000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qnm_cnoc_data = {
+ .name = "qnm_cnoc_data",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x1f000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qns_a1noc_snoc = {
+ .name = "qns_a1noc_snoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_aggre_noc },
+};
+
+static struct qcom_icc_node qns_lpass_aggnoc = {
+ .name = "qns_lpass_aggnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpiaon_noc },
+};
+
+static struct qcom_icc_node qhm_qspi = {
+ .name = "qhm_qspi",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x49000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup2 = {
+ .name = "qhm_qup2",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x48000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup3 = {
+ .name = "qhm_qup3",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x46000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup4 = {
+ .name = "qhm_qup4",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x47000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_crypto = {
+ .name = "qxm_crypto",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x40000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_ipa = {
+ .name = "qxm_ipa",
+ .channels = 1,
+ .buswidth = 16,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x41000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_qup1 = {
+ .name = "qxm_qup1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4d000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_soccp = {
+ .name = "qxm_soccp",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x45000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_qdss_etr_0 = {
+ .name = "xm_qdss_etr_0",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x42000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_qdss_etr_1 = {
+ .name = "xm_qdss_etr_1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x43000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_sdc2 = {
+ .name = "xm_sdc2",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x44000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_sdc4 = {
+ .name = "xm_sdc4",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4a000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_ufs_mem = {
+ .name = "xm_ufs_mem",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4b000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_usb3 = {
+ .name = "xm_usb3",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4c000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qnm_lpass_lpinoc = {
+ .name = "qnm_lpass_lpinoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 2,
+ .link_nodes = { &qns_llc_lpinoc, &qns_lpass_aggnoc },
+};
+
+static struct qcom_icc_node qns_lpi_aon_noc = {
+ .name = "qns_lpi_aon_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpass_lpinoc },
+};
+
+static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = {
+ .name = "qnm_lpinoc_dsp_qns4m",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_lpi_aon_noc },
+};
+
+static struct qcom_icc_bcm bcm_acv = {
+ .name = "ACV",
+ .enable_mask = BIT(3),
+ .num_nodes = 1,
+ .nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_ce0 = {
+ .name = "CE0",
+ .num_nodes = 1,
+ .nodes = { &qxm_crypto },
+};
+
+static struct qcom_icc_bcm bcm_cn0 = {
+ .name = "CN0",
+ .enable_mask = BIT(0),
+ .keepalive = true,
+ .num_nodes = 23,
+ .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
+ &qhs_aoss, &qhs_ipa,
+ &qhs_ipc_router_fence, &qhs_soccp,
+ &qhs_tme_cfg, &qss_cfg,
+ &qss_ddrss_cfg, &qxs_imem,
+ &xs_pcie, &qsm_cfg_center,
+ &qsm_cfg_east, &qsm_cfg_mm,
+ &qsm_cfg_north, &qsm_cfg_south,
+ &qsm_cfg_southwest, &qhs_ahb2phy0,
+ &qhs_boot_rom, &qhs_camera_cfg,
+ &qhs_clk_ctl, &qhs_crypto_cfg,
+ &qhs_eva_cfg },
+};
+
+static struct qcom_icc_bcm bcm_cn1 = {
+ .name = "CN1",
+ .num_nodes = 1,
+ .nodes = { &qhs_display_cfg },
+};
+
+static struct qcom_icc_bcm bcm_co0 = {
+ .name = "CO0",
+ .enable_mask = BIT(0),
+ .num_nodes = 2,
+ .nodes = { &qnm_nsp, &qns_nsp_gemnoc },
+};
+
+static struct qcom_icc_bcm bcm_de0 = {
+ .name = "DE0",
+ .enable_mask = BIT(0),
+ .num_nodes = 1,
+ .nodes = { &ddr_eff_veto_slave },
+};
+
+static struct qcom_icc_bcm bcm_lp0 = {
+ .name = "LP0",
+ .num_nodes = 5,
+ .nodes = { &qnm_lpiaon_noc_llclpi_noc, &qns_lb,
+ &qnm_lpass_lpinoc, &qns_llc_lpinoc,
+ &qns_lpass_aggnoc },
+};
+
+static struct qcom_icc_bcm bcm_mc0 = {
+ .name = "MC0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_mc5 = {
+ .name = "MC5",
+ .num_nodes = 1,
+ .nodes = { &ddr_rt_slave },
+};
+
+static struct qcom_icc_bcm bcm_mm0 = {
+ .name = "MM0",
+ .num_nodes = 1,
+ .nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_bcm bcm_mm1 = {
+ .name = "MM1",
+ .enable_mask = BIT(0),
+ .num_nodes = 9,
+ .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf,
+ &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf,
+ &qnm_vapss_hcp, &qnm_video_cv_cpu,
+ &qnm_video_mvp, &qnm_video_v_cpu,
+ &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_bcm bcm_qpc0 = {
+ .name = "QPC0",
+ .num_nodes = 1,
+ .nodes = { &qnm_qpace },
+};
+
+static struct qcom_icc_bcm bcm_qup0 = {
+ .name = "QUP0",
+ .keepalive = true,
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup0_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup1 = {
+ .name = "QUP1",
+ .keepalive = true,
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup1_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup2 = {
+ .name = "QUP2",
+ .keepalive = true,
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup2_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup3 = {
+ .name = "QUP3",
+ .keepalive = true,
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup3_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup4 = {
+ .name = "QUP4",
+ .keepalive = true,
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup4_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_sh0 = {
+ .name = "SH0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_bcm bcm_sh1 = {
+ .name = "SH1",
+ .enable_mask = BIT(0),
+ .num_nodes = 15,
+ .nodes = { &alm_gic, &alm_gpu_tcu,
+ &alm_sys_tcu, &chm_apps,
+ &qnm_gpu, &qnm_lpass_gemnoc,
+ &qnm_mdsp, &qnm_mnoc_hf,
+ &qnm_mnoc_sf, &qnm_nsp_gemnoc,
+ &qnm_pcie, &qnm_snoc_sf,
+ &qnm_wlan_q6, &qns_gem_noc_cnoc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_bcm bcm_sn0 = {
+ .name = "SN0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_bcm bcm_sn2 = {
+ .name = "SN2",
+ .num_nodes = 1,
+ .nodes = { &qnm_aggre_noc },
+};
+
+static struct qcom_icc_bcm bcm_sn3 = {
+ .name = "SN3",
+ .num_nodes = 1,
+ .nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
+ &bcm_ce0,
+};
+
+static struct qcom_icc_node * const aggre1_noc_nodes[] = {
+ [MASTER_QSPI_0] = &qhm_qspi,
+ [MASTER_QUP_2] = &qhm_qup2,
+ [MASTER_QUP_3] = &qhm_qup3,
+ [MASTER_QUP_4] = &qhm_qup4,
+ [MASTER_CRYPTO] = &qxm_crypto,
+ [MASTER_IPA] = &qxm_ipa,
+ [MASTER_QUP_1] = &qxm_qup1,
+ [MASTER_SOCCP_PROC] = &qxm_soccp,
+ [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
+ [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
+ [MASTER_SDCC_2] = &xm_sdc2,
+ [MASTER_SDCC_4] = &xm_sdc4,
+ [MASTER_UFS_MEM] = &xm_ufs_mem,
+ [MASTER_USB3] = &xm_usb3,
+ [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
+};
+
+static const struct regmap_config hawi_aggre1_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x54400,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_aggre1_noc = {
+ .config = &hawi_aggre1_noc_regmap_config,
+ .nodes = aggre1_noc_nodes,
+ .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
+ .bcms = aggre1_noc_bcms,
+ .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+ .qos_requires_clocks = true,
+};
+
+static struct qcom_icc_bcm * const clk_virt_bcms[] = {
+ &bcm_de0,
+ &bcm_qup0,
+ &bcm_qup1,
+ &bcm_qup2,
+ &bcm_qup3,
+ &bcm_qup4,
+};
+
+static struct qcom_icc_node * const clk_virt_nodes[] = {
+ [MASTER_DDR_EFF_VETO] = &ddr_eff_veto_master,
+ [MASTER_QUP_CORE_0] = &qup0_core_master,
+ [MASTER_QUP_CORE_1] = &qup1_core_master,
+ [MASTER_QUP_CORE_2] = &qup2_core_master,
+ [MASTER_QUP_CORE_3] = &qup3_core_master,
+ [MASTER_QUP_CORE_4] = &qup4_core_master,
+ [SLAVE_DDR_EFF_VETO] = &ddr_eff_veto_slave,
+ [SLAVE_QUP_CORE_0] = &qup0_core_slave,
+ [SLAVE_QUP_CORE_1] = &qup1_core_slave,
+ [SLAVE_QUP_CORE_2] = &qup2_core_slave,
+ [SLAVE_QUP_CORE_3] = &qup3_core_slave,
+ [SLAVE_QUP_CORE_4] = &qup4_core_slave,
+};
+
+static const struct qcom_icc_desc hawi_clk_virt = {
+ .nodes = clk_virt_nodes,
+ .num_nodes = ARRAY_SIZE(clk_virt_nodes),
+ .bcms = clk_virt_bcms,
+ .num_bcms = ARRAY_SIZE(clk_virt_bcms),
+};
+
+static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
+ &bcm_cn0,
+};
+
+static struct qcom_icc_node * const cnoc_main_nodes[] = {
+ [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
+ [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
+ [SLAVE_AOSS] = &qhs_aoss,
+ [SLAVE_IPA_CFG] = &qhs_ipa,
+ [SLAVE_IPC_ROUTER_FENCE] = &qhs_ipc_router_fence,
+ [SLAVE_SOCCP] = &qhs_soccp,
+ [SLAVE_TME_CFG] = &qhs_tme_cfg,
+ [SLAVE_CNOC_CFG] = &qss_cfg,
+ [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
+ [SLAVE_IMEM] = &qxs_imem,
+ [SLAVE_PCIE_0] = &xs_pcie,
+};
+
+static const struct regmap_config hawi_cnoc_main_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_cnoc_main = {
+ .config = &hawi_cnoc_main_regmap_config,
+ .nodes = cnoc_main_nodes,
+ .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
+ .bcms = cnoc_main_bcms,
+ .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
+};
+
+static struct qcom_icc_bcm * const gem_noc_bcms[] = {
+ &bcm_qpc0,
+ &bcm_sh0,
+ &bcm_sh1,
+};
+
+static struct qcom_icc_node * const gem_noc_nodes[] = {
+ [MASTER_GIC] = &alm_gic,
+ [MASTER_GPU_TCU] = &alm_gpu_tcu,
+ [MASTER_SYS_TCU] = &alm_sys_tcu,
+ [MASTER_APPSS_PROC] = &chm_apps,
+ [MASTER_GFX3D] = &qnm_gpu,
+ [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
+ [MASTER_MSS_PROC] = &qnm_mdsp,
+ [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
+ [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
+ [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
+ [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
+ [MASTER_QPACE] = &qnm_qpace,
+ [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
+ [MASTER_WLAN_Q6] = &qnm_wlan_q6,
+ [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
+ [SLAVE_LLCC] = &qns_llcc,
+ [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
+};
+
+static const struct regmap_config hawi_gem_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x160200,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_gem_noc = {
+ .config = &hawi_gem_noc_regmap_config,
+ .nodes = gem_noc_nodes,
+ .num_nodes = ARRAY_SIZE(gem_noc_nodes),
+ .bcms = gem_noc_bcms,
+ .num_bcms = ARRAY_SIZE(gem_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const llclpi_noc_bcms[] = {
+ &bcm_lp0,
+};
+
+static struct qcom_icc_node * const llclpi_noc_nodes[] = {
+ [MASTER_LPIAON_NOC_LLCLPI_NOC] = &qnm_lpiaon_noc_llclpi_noc,
+ [SLAVE_LPASS_LPI_CC] = &qhs_lpi_cc,
+ [SLAVE_LLCC_ISLAND] = &qns_lb,
+ [SLAVE_SERVICE_LLCLPI_NOC] = &srvc_llclpi_noc,
+ [SLAVE_SERVICE_LLCLPI_NOC_CHIPCX] = &srvc_llclpi_noc_chipcx,
+};
+
+static const struct regmap_config hawi_llclpi_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x17200,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_llclpi_noc = {
+ .config = &hawi_llclpi_noc_regmap_config,
+ .nodes = llclpi_noc_nodes,
+ .num_nodes = ARRAY_SIZE(llclpi_noc_nodes),
+ .bcms = llclpi_noc_bcms,
+ .num_bcms = ARRAY_SIZE(llclpi_noc_bcms),
+};
+
+static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
+ [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
+ [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
+};
+
+static const struct regmap_config hawi_lpass_ag_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xc080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_lpass_ag_noc = {
+ .config = &hawi_lpass_ag_noc_regmap_config,
+ .nodes = lpass_ag_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
+};
+
+static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
+ &bcm_lp0,
+};
+
+static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
+ [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
+ [SLAVE_LPIAON_NOC_LLCLPI_NOC] = &qns_llc_lpinoc,
+ [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
+};
+
+static const struct regmap_config hawi_lpass_lpiaon_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x19080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_lpass_lpiaon_noc = {
+ .config = &hawi_lpass_lpiaon_noc_regmap_config,
+ .nodes = lpass_lpiaon_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
+ .bcms = lpass_lpiaon_noc_bcms,
+ .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
+};
+
+static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
+ [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m,
+ [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
+};
+
+static const struct regmap_config hawi_lpass_lpicx_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x46080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_lpass_lpicx_noc = {
+ .config = &hawi_lpass_lpicx_noc_regmap_config,
+ .nodes = lpass_lpicx_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
+};
+
+static struct qcom_icc_bcm * const mc_virt_bcms[] = {
+ &bcm_acv,
+ &bcm_mc0,
+ &bcm_mc5,
+};
+
+static struct qcom_icc_node * const mc_virt_nodes[] = {
+ [MASTER_LLCC] = &llcc_mc,
+ [MASTER_DDR_RT] = &ddr_rt_mc,
+ [SLAVE_EBI1] = &ebi,
+ [SLAVE_DDR_RT] = &ddr_rt_slave,
+};
+
+static const struct qcom_icc_desc hawi_mc_virt = {
+ .nodes = mc_virt_nodes,
+ .num_nodes = ARRAY_SIZE(mc_virt_nodes),
+ .bcms = mc_virt_bcms,
+ .num_bcms = ARRAY_SIZE(mc_virt_bcms),
+};
+
+static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
+ &bcm_mm0,
+ &bcm_mm1,
+};
+
+static struct qcom_icc_node * const mmss_noc_nodes[] = {
+ [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
+ [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf,
+ [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf,
+ [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
+ [MASTER_MDP] = &qnm_mdp,
+ [MASTER_MDSS_DCP] = &qnm_mdss_dcp,
+ [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
+ [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
+ [MASTER_VIDEO_EVA] = &qnm_video_eva,
+ [MASTER_VIDEO_MVP] = &qnm_video_mvp,
+ [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
+ [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
+ [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
+};
+
+static const struct regmap_config hawi_mmss_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x5f800,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_mmss_noc = {
+ .config = &hawi_mmss_noc_regmap_config,
+ .nodes = mmss_noc_nodes,
+ .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
+ .bcms = mmss_noc_bcms,
+ .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
+ &bcm_co0,
+};
+
+static struct qcom_icc_node * const nsp_noc_nodes[] = {
+ [MASTER_CDSP_PROC] = &qnm_nsp,
+ [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
+};
+
+static const struct regmap_config hawi_nsp_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x21280,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_nsp_noc = {
+ .config = &hawi_nsp_noc_regmap_config,
+ .nodes = nsp_noc_nodes,
+ .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
+ .bcms = nsp_noc_bcms,
+ .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
+ &bcm_sn3,
+};
+
+static struct qcom_icc_node * const pcie_anoc_nodes[] = {
+ [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
+ [MASTER_PCIE_0] = &xm_pcie,
+ [MASTER_PCIE_1] = &xm_pcie_g4x1,
+ [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
+ [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
+};
+
+static const struct regmap_config hawi_pcie_anoc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x12400,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_pcie_anoc = {
+ .config = &hawi_pcie_anoc_regmap_config,
+ .nodes = pcie_anoc_nodes,
+ .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
+ .bcms = pcie_anoc_bcms,
+ .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
+ .qos_requires_clocks = true,
+};
+
+static struct qcom_icc_bcm * const stdst_cfg_bcms[] = {
+ &bcm_cn0,
+ &bcm_cn1,
+};
+
+static struct qcom_icc_node * const stdst_cfg_nodes[] = {
+ [MASTER_CFG_CENTER] = &qsm_cfg_center,
+ [MASTER_CFG_EAST] = &qsm_cfg_east,
+ [MASTER_CFG_MM] = &qsm_cfg_mm,
+ [MASTER_CFG_NORTH] = &qsm_cfg_north,
+ [MASTER_CFG_SOUTH] = &qsm_cfg_south,
+ [MASTER_CFG_SOUTHWEST] = &qsm_cfg_southwest,
+ [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
+ [SLAVE_BOOT_ROM] = &qhs_boot_rom,
+ [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
+ [SLAVE_CLK_CTL] = &qhs_clk_ctl,
+ [SLAVE_CRYPTO_CFG] = &qhs_crypto_cfg,
+ [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
+ [SLAVE_EVA_CFG] = &qhs_eva_cfg,
+ [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
+ [SLAVE_I2C] = &qhs_i2c,
+ [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
+ [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
+ [SLAVE_IRIS_CFG] = &qhs_iris_cfg,
+ [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
+ [SLAVE_PCIE_0_CFG] = &qhs_pcie_cfg,
+ [SLAVE_PCIE_1_CFG] = &qhs_pcie_g4x1_cfg,
+ [SLAVE_PRNG] = &qhs_prng,
+ [SLAVE_QSPI_0] = &qhs_qspi,
+ [SLAVE_QUP_1] = &qhs_qup1,
+ [SLAVE_QUP_2] = &qhs_qup2,
+ [SLAVE_QUP_3] = &qhs_qup3,
+ [SLAVE_QUP_4] = &qhs_qup4,
+ [SLAVE_SDCC_2] = &qhs_sdc2,
+ [SLAVE_SDCC_4] = &qhs_sdc4,
+ [SLAVE_TLMM] = &qhs_tlmm,
+ [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
+ [SLAVE_USB3] = &qhs_usb3,
+ [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
+ [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
+ [SLAVE_QDSS_CFG] = &qss_qdss_cfg,
+ [SLAVE_QDSS_STM] = &qss_qdss_stm,
+ [SLAVE_TCSR] = &qss_tcsr,
+ [SLAVE_TCU] = &xs_sys_tcu_cfg,
+};
+
+static const struct regmap_config hawi_stdst_cfg_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xb1000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_stdst_cfg = {
+ .config = &hawi_stdst_cfg_regmap_config,
+ .nodes = stdst_cfg_nodes,
+ .num_nodes = ARRAY_SIZE(stdst_cfg_nodes),
+ .bcms = stdst_cfg_bcms,
+ .num_bcms = ARRAY_SIZE(stdst_cfg_bcms),
+};
+
+static struct qcom_icc_node * const stdst_main_nodes[] = {
+ [MASTER_CNOC_STARDUST] = &qsm_cnoc_main,
+ [SLAVE_STARDUST_CENTER_CFG] = &qss_stdst_center_cfg,
+ [SLAVE_STARDUST_EAST_CFG] = &qss_stdst_east_cfg,
+ [SLAVE_STARDUST_MM_CFG] = &qss_stdst_mm_cfg,
+ [SLAVE_STARDUST_NORTH_CFG] = &qss_stdst_north_cfg,
+ [SLAVE_STARDUST_SOUTH_CFG] = &qss_stdst_south_cfg,
+ [SLAVE_STARDUST_SOUTHWEST_CFG] = &qss_stdst_southwest_cfg,
+};
+
+static const struct regmap_config hawi_stdst_main_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x10000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_stdst_main = {
+ .config = &hawi_stdst_main_regmap_config,
+ .nodes = stdst_main_nodes,
+ .num_nodes = ARRAY_SIZE(stdst_main_nodes),
+};
+
+static struct qcom_icc_bcm * const system_noc_bcms[] = {
+ &bcm_sn0,
+ &bcm_sn2,
+};
+
+static struct qcom_icc_node * const system_noc_nodes[] = {
+ [MASTER_A1NOC_SNOC] = &qnm_aggre_noc,
+ [MASTER_APSS_NOC] = &qnm_apss_noc,
+ [MASTER_CNOC_SNOC] = &qnm_cnoc_data,
+ [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
+};
+
+static const struct regmap_config hawi_system_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_system_noc = {
+ .config = &hawi_system_noc_regmap_config,
+ .nodes = system_noc_nodes,
+ .num_nodes = ARRAY_SIZE(system_noc_nodes),
+ .bcms = system_noc_bcms,
+ .num_bcms = ARRAY_SIZE(system_noc_bcms),
+};
+
+static const struct of_device_id qnoc_of_match[] = {
+ { .compatible = "qcom,hawi-aggre1-noc", .data = &hawi_aggre1_noc },
+ { .compatible = "qcom,hawi-clk-virt", .data = &hawi_clk_virt },
+ { .compatible = "qcom,hawi-cnoc-main", .data = &hawi_cnoc_main },
+ { .compatible = "qcom,hawi-gem-noc", .data = &hawi_gem_noc },
+ { .compatible = "qcom,hawi-llclpi-noc", .data = &hawi_llclpi_noc },
+ { .compatible = "qcom,hawi-lpass-ag-noc", .data = &hawi_lpass_ag_noc },
+ { .compatible = "qcom,hawi-lpass-lpiaon-noc", .data = &hawi_lpass_lpiaon_noc },
+ { .compatible = "qcom,hawi-lpass-lpicx-noc", .data = &hawi_lpass_lpicx_noc },
+ { .compatible = "qcom,hawi-mc-virt", .data = &hawi_mc_virt },
+ { .compatible = "qcom,hawi-mmss-noc", .data = &hawi_mmss_noc },
+ { .compatible = "qcom,hawi-nsp-noc", .data = &hawi_nsp_noc },
+ { .compatible = "qcom,hawi-pcie-anoc", .data = &hawi_pcie_anoc },
+ { .compatible = "qcom,hawi-stdst-cfg", .data = &hawi_stdst_cfg },
+ { .compatible = "qcom,hawi-stdst-main", .data = &hawi_stdst_main },
+ { .compatible = "qcom,hawi-system-noc", .data = &hawi_system_noc },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qnoc_of_match);
+
+static struct platform_driver qnoc_driver = {
+ .probe = qcom_icc_rpmh_probe,
+ .remove = qcom_icc_rpmh_remove,
+ .driver = {
+ .name = "qnoc-hawi",
+ .of_match_table = qnoc_of_match,
+ .sync_state = icc_sync_state,
+ },
+};
+
+static int __init qnoc_driver_init(void)
+{
+ return platform_driver_register(&qnoc_driver);
+}
+core_initcall(qnoc_driver_init);
+
+static void __exit qnoc_driver_exit(void)
+{
+ platform_driver_unregister(&qnoc_driver);
+}
+module_exit(qnoc_driver_exit);
+
+MODULE_DESCRIPTION("Qualcomm Hawi NoC driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Hawi SoC
From: Vivek Aknurwar @ 2026-04-06 23:04 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, Mike Tipton,
Vivek Aknurwar
In-Reply-To: <20260406-icc-hawi-v2-0-6cfee87a1d25@oss.qualcomm.com>
Document the RPMh Network-On-Chip Interconnect of the Hawi platform.
Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
---
.../bindings/interconnect/qcom,hawi-rpmh.yaml | 131 ++++++++++++++++
include/dt-bindings/interconnect/qcom,hawi-rpmh.h | 164 +++++++++++++++++++++
2 files changed, 295 insertions(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml
new file mode 100644
index 000000000000..49a2dca5db62
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,hawi-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on Hawi
+
+maintainers:
+ - Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
+
+description: |
+ RPMh interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+ able to communicate with the BCM through the Resource State Coordinator (RSC)
+ associated with each execution environment. Provider nodes must point to at
+ least one RPMh device child node pertaining to their RSC and each provider
+ can map to multiple RPMh resources.
+
+ See also: include/dt-bindings/interconnect/qcom,hawi-rpmh.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,hawi-aggre1-noc
+ - qcom,hawi-clk-virt
+ - qcom,hawi-cnoc-main
+ - qcom,hawi-gem-noc
+ - qcom,hawi-llclpi-noc
+ - qcom,hawi-lpass-ag-noc
+ - qcom,hawi-lpass-lpiaon-noc
+ - qcom,hawi-lpass-lpicx-noc
+ - qcom,hawi-mc-virt
+ - qcom,hawi-mmss-noc
+ - qcom,hawi-nsp-noc
+ - qcom,hawi-pcie-anoc
+ - qcom,hawi-stdst-cfg
+ - qcom,hawi-stdst-main
+ - qcom,hawi-system-noc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+required:
+ - compatible
+
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,hawi-clk-virt
+ - qcom,hawi-mc-virt
+ then:
+ properties:
+ reg: false
+ else:
+ required:
+ - reg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,hawi-pcie-anoc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre-NOC PCIe AXI clock
+ - description: cfg-NOC PCIe a-NOC AHB clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,hawi-aggre1-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre UFS PHY AXI clock
+ - description: aggre USB3 PRIM AXI clock
+ - description: RPMH CC IPA clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,hawi-aggre1-noc
+ - qcom,hawi-pcie-anoc
+ then:
+ required:
+ - clocks
+ else:
+ properties:
+ clocks: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,hawi-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre_noc: interconnect@f00000 {
+ compatible = "qcom,hawi-aggre1-noc";
+ reg = <0x0 0xf00000 0x0 0x54400>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc_aggre_ufs_phy_axi_clk>,
+ <&gcc_aggre_usb3_prim_axi_clk>,
+ <&rpmhcc_ipa_clk>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+ };
diff --git a/include/dt-bindings/interconnect/qcom,hawi-rpmh.h b/include/dt-bindings/interconnect/qcom,hawi-rpmh.h
new file mode 100644
index 000000000000..75312cbbb80e
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,hawi-rpmh.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_HAWI_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_HAWI_H
+
+#define MASTER_QSPI_0 0
+#define MASTER_QUP_2 1
+#define MASTER_QUP_3 2
+#define MASTER_QUP_4 3
+#define MASTER_CRYPTO 4
+#define MASTER_IPA 5
+#define MASTER_QUP_1 6
+#define MASTER_SOCCP_PROC 7
+#define MASTER_QDSS_ETR 8
+#define MASTER_QDSS_ETR_1 9
+#define MASTER_SDCC_2 10
+#define MASTER_SDCC_4 11
+#define MASTER_UFS_MEM 12
+#define MASTER_USB3 13
+#define SLAVE_A1NOC_SNOC 14
+
+#define MASTER_DDR_EFF_VETO 0
+#define MASTER_QUP_CORE_0 1
+#define MASTER_QUP_CORE_1 2
+#define MASTER_QUP_CORE_2 3
+#define MASTER_QUP_CORE_3 4
+#define MASTER_QUP_CORE_4 5
+#define SLAVE_DDR_EFF_VETO 6
+#define SLAVE_QUP_CORE_0 7
+#define SLAVE_QUP_CORE_1 8
+#define SLAVE_QUP_CORE_2 9
+#define SLAVE_QUP_CORE_3 10
+#define SLAVE_QUP_CORE_4 11
+
+#define MASTER_GEM_NOC_CNOC 0
+#define MASTER_GEM_NOC_PCIE_SNOC 1
+#define SLAVE_AOSS 2
+#define SLAVE_IPA_CFG 3
+#define SLAVE_IPC_ROUTER_FENCE 4
+#define SLAVE_SOCCP 5
+#define SLAVE_TME_CFG 6
+#define SLAVE_CNOC_CFG 7
+#define SLAVE_DDRSS_CFG 8
+#define SLAVE_IMEM 9
+#define SLAVE_PCIE_0 10
+
+#define MASTER_GIC 0
+#define MASTER_GPU_TCU 1
+#define MASTER_SYS_TCU 2
+#define MASTER_APPSS_PROC 3
+#define MASTER_GFX3D 4
+#define MASTER_LPASS_GEM_NOC 5
+#define MASTER_MSS_PROC 6
+#define MASTER_MNOC_HF_MEM_NOC 7
+#define MASTER_MNOC_SF_MEM_NOC 8
+#define MASTER_COMPUTE_NOC 9
+#define MASTER_ANOC_PCIE_GEM_NOC 10
+#define MASTER_QPACE 11
+#define MASTER_SNOC_SF_MEM_NOC 12
+#define MASTER_WLAN_Q6 13
+#define SLAVE_GEM_NOC_CNOC 14
+#define SLAVE_LLCC 15
+#define SLAVE_MEM_NOC_PCIE_SNOC 16
+
+#define MASTER_LPIAON_NOC_LLCLPI_NOC 0
+#define SLAVE_LPASS_LPI_CC 1
+#define SLAVE_LLCC_ISLAND 2
+#define SLAVE_SERVICE_LLCLPI_NOC 3
+#define SLAVE_SERVICE_LLCLPI_NOC_CHIPCX 4
+
+#define MASTER_LPIAON_NOC 0
+#define SLAVE_LPASS_GEM_NOC 1
+
+#define MASTER_LPASS_LPINOC 0
+#define SLAVE_LPIAON_NOC_LLCLPI_NOC 1
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 2
+
+#define MASTER_LPASS_PROC 0
+#define SLAVE_LPICX_NOC_LPIAON_NOC 1
+
+#define MASTER_LLCC 0
+#define MASTER_DDR_RT 1
+#define SLAVE_EBI1 2
+#define SLAVE_DDR_RT 3
+
+#define MASTER_CAMNOC_HF 0
+#define MASTER_CAMNOC_NRT_ICP_SF 1
+#define MASTER_CAMNOC_RT_CDM_SF 2
+#define MASTER_CAMNOC_SF 3
+#define MASTER_MDP 4
+#define MASTER_MDSS_DCP 5
+#define MASTER_CDSP_HCP 6
+#define MASTER_VIDEO_CV_PROC 7
+#define MASTER_VIDEO_EVA 8
+#define MASTER_VIDEO_MVP 9
+#define MASTER_VIDEO_V_PROC 10
+#define SLAVE_MNOC_HF_MEM_NOC 11
+#define SLAVE_MNOC_SF_MEM_NOC 12
+
+#define MASTER_CDSP_PROC 0
+#define SLAVE_CDSP_MEM_NOC 1
+
+#define MASTER_PCIE_ANOC_CFG 0
+#define MASTER_PCIE_0 1
+#define MASTER_PCIE_1 2
+#define SLAVE_ANOC_PCIE_GEM_NOC 3
+#define SLAVE_SERVICE_PCIE_ANOC 4
+
+#define MASTER_CFG_CENTER 0
+#define MASTER_CFG_EAST 1
+#define MASTER_CFG_MM 2
+#define MASTER_CFG_NORTH 3
+#define MASTER_CFG_SOUTH 4
+#define MASTER_CFG_SOUTHWEST 5
+#define SLAVE_AHB2PHY_SOUTH 6
+#define SLAVE_BOOT_ROM 7
+#define SLAVE_CAMERA_CFG 8
+#define SLAVE_CLK_CTL 9
+#define SLAVE_CRYPTO_CFG 10
+#define SLAVE_DISPLAY_CFG 11
+#define SLAVE_EVA_CFG 12
+#define SLAVE_GFX3D_CFG 13
+#define SLAVE_I2C 14
+#define SLAVE_IMEM_CFG 15
+#define SLAVE_IPC_ROUTER_CFG 16
+#define SLAVE_IRIS_CFG 17
+#define SLAVE_CNOC_MSS 18
+#define SLAVE_PCIE_0_CFG 19
+#define SLAVE_PCIE_1_CFG 20
+#define SLAVE_PRNG 21
+#define SLAVE_QSPI_0 22
+#define SLAVE_QUP_1 23
+#define SLAVE_QUP_2 24
+#define SLAVE_QUP_3 25
+#define SLAVE_QUP_4 26
+#define SLAVE_SDCC_2 27
+#define SLAVE_SDCC_4 28
+#define SLAVE_TLMM 29
+#define SLAVE_UFS_MEM_CFG 30
+#define SLAVE_USB3 31
+#define SLAVE_VSENSE_CTRL_CFG 32
+#define SLAVE_PCIE_ANOC_CFG 33
+#define SLAVE_QDSS_CFG 34
+#define SLAVE_QDSS_STM 35
+#define SLAVE_TCSR 36
+#define SLAVE_TCU 37
+
+#define MASTER_CNOC_STARDUST 0
+#define SLAVE_STARDUST_CENTER_CFG 1
+#define SLAVE_STARDUST_EAST_CFG 2
+#define SLAVE_STARDUST_MM_CFG 3
+#define SLAVE_STARDUST_NORTH_CFG 4
+#define SLAVE_STARDUST_SOUTH_CFG 5
+#define SLAVE_STARDUST_SOUTHWEST_CFG 6
+
+#define MASTER_A1NOC_SNOC 0
+#define MASTER_APSS_NOC 1
+#define MASTER_CNOC_SNOC 2
+#define SLAVE_SNOC_GEM_NOC_SF 3
+
+#endif
--
2.34.1
^ permalink raw reply related
* [PATCH v2 0/2] interconnect: qcom: Add support for upcoming Hawi SoC
From: Vivek Aknurwar @ 2026-04-06 23:04 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, Mike Tipton,
Vivek Aknurwar, Krzysztof Kozlowski
Add interconnect bindings and RPMh-based interconnect
driver support for the upcoming Qualcomm Hawi SoC.
Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
---
Changes in v2:
- Fix warning reported by dt_binding_check.
- Collected Acked-bys
- Link to v1: https://lore.kernel.org/r/20260330-icc-hawi-v1-0-4b54a9e7d38c@oss.qualcomm.com
---
Vivek Aknurwar (2):
dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Hawi SoC
interconnect: qcom: add Hawi interconnect provider driver
.../bindings/interconnect/qcom,hawi-rpmh.yaml | 131 ++
drivers/interconnect/qcom/Kconfig | 9 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/hawi.c | 2021 ++++++++++++++++++++
include/dt-bindings/interconnect/qcom,hawi-rpmh.h | 164 ++
5 files changed, 2327 insertions(+)
---
base-commit: e3b32dcb9f23e3c3927ef3eec6a5842a988fb574
change-id: 20260311-icc-hawi-d6dc165f8935
Best regards,
--
Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v1 1/2] dt-bindings: chrome: Add cros-ec-ucsi compatibility to typec binding
From: Rob Herring (Arm) @ 2026-04-06 22:49 UTC (permalink / raw)
To: Jameson Thies
Cc: abhishekpandit, akuchynski, devicetree, chrome-platform, bleung,
conor+dt, linux-kernel, heikki.krogerus, linux-usb, krzk+dt,
gregkh
In-Reply-To: <20260403223357.1896403-2-jthies@google.com>
On Fri, 03 Apr 2026 22:33:26 +0000, Jameson Thies wrote:
> Chrome OS devices with discrete power delivery controllers (PDCs) allow
> the host to read port status and control port behavior through a USB
> Type-C Connector System Software (UCSI) interface with the embedded
> controller (EC). This uses a separate interface driver than other
> Chrome OS devices with a Type-C port manager in the EC FW. Those use
> a host command interface supported by cros-ec-typec. Add a cros-ec-ucsi
> compatibility string to the existing cros-ec-typec binding.
>
> Additionally, update maintainer list to reflect cros-ec-ucsi and
> cros-ec-typec driver maintainers.
>
> Signed-off-by: Jameson Thies <jthies@google.com>
> ---
> .../bindings/chrome/google,cros-ec-typec.yaml | 19 +++++++++++++++----
> 1 file changed, 15 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH] dt-bindings: opp-v2: Fix example 3 CPU reg value
From: Rob Herring (Arm) @ 2026-04-06 22:44 UTC (permalink / raw)
To: Vivian Wang
Cc: Krzysztof Kozlowski, Viresh Kumar, linux-kernel, linux-pm,
Viresh Kumar, devicetree, Nishanth Menon, Conor Dooley,
Stephen Boyd
In-Reply-To: <20260403-dt-bindings-opp-v2-hex-cpu-reg-v1-1-38a4968ab515@iscas.ac.cn>
On Fri, 03 Apr 2026 18:34:29 +0800, Vivian Wang wrote:
> Example 3 is a dual-cluster example, meaning that the CPU nodes should
> have reg values 0x0, 0x1, 0x100, 0x101. The example incorrectly uses
> decimal 0, 1, 100, 101 instead, which seems unintended. Use the correct
> hexadecimal values.
>
> Even though the value doesn't change for the first two CPUs, 0 and 1 in
> example 3 are changed to 0x0 and 0x1 respectively for consistency. Other
> examples all have reg less than 10, so they have not been changed.
>
> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
> ---
> Found while trying to figure out if cpu@* unit addresses are supposed to
> be decimal or hexadecimal. This is AFAICT the only place in-tree where
> an arm/arm64 DTS uses multi-digit decimal. See also:
>
> - https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/
> - https://github.com/devicetree-org/devicetree-specification/issues/86
> ---
> Documentation/devicetree/bindings/opp/opp-v2.yaml | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCh v3 11/14] ASoC: rsnd: src: Add SRC reset and clock support for RZ/G3E
From: Kuninori Morimoto @ 2026-04-06 22:34 UTC (permalink / raw)
To: John Madieu
Cc: Mark Brown, Liam Girdwood, Geert Uytterhoeven, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
magnus.damm, Philipp Zabel, Claudiu.Beznea, Biju Das,
john.madieu@gmail.com, linux-sound@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <87se99t04m.wl-kuninori.morimoto.gx@renesas.com>
Hi John, again
> > Agreed. However, since rsnd_src is a per-SRC instance structure,
> > I'll rather have these variables static in src.c, as the clocks
> > are shared across all SRC instances but used only in that file.
> > I hope this is fine for you ?
>
> Ah, OK.
> So how about to create new struct rsnd_src_clk or something,
> and has above clocks, instead of using file-static, like below.
>
> struct rsnd_priv {
> ...
> + void *src_clk; // I'm not sure the name ;)
> void *src;
> int src_nr;
> ...
> };
>
> + struct rsnd_src_clk { // I'm not sure the name :)
> + struct clk *scu;
> + struct clk *scu_x2;
> + struct clk *scu_supply;
> + };
> + #define rsnd_priv_to_src_clk(priv) ((struct rsnd_src_clk *)(priv)->src_clk)
About the naming, maybe rsnd_src_base / rsnd_src_master or something is
better ? It has SRC overall items.
Maybe same comment for SSIU.
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* [PATCH] ARM: dts: BCM5301X: EA6500v2: fix USB3
From: Rosen Penev @ 2026-04-06 22:06 UTC (permalink / raw)
To: devicetree
Cc: Florian Fainelli, Hauke Mehrtens, Rafał Miłecki,
Broadcom internal kernel review list, Rob Herring,
Krzysztof Kozlowski, Conor Dooley,
moderated list:BROADCOM BCM5301X ARM ARCHITECTURE, open list
USB3 needs to have a GPIO pulled HIGH in order to function. Add vcc-gpio
to do so.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts
index 0454423fe166..ad246f9a734a 100644
--- a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts
+++ b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts
@@ -43,3 +43,7 @@ button-restart {
&usb3_phy {
status = "okay";
};
+
+&usb3 {
+ vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
+};
--
2.53.0
^ permalink raw reply related
* [PATCH] ARM: dts: BCM5301X: EA6500v2: fix USB3
From: Rosen Penev @ 2026-04-06 22:05 UTC (permalink / raw)
To: devicetree
Cc: Florian Fainelli, Hauke Mehrtens, Rafał Miłecki,
Broadcom internal kernel review list, Rob Herring,
Krzysztof Kozlowski, Conor Dooley,
moderated list:BROADCOM BCM5301X ARM ARCHITECTURE, open list
USB3 needs to have a GPIO pulled HIGH in order to function. Add vcc-gpio
to do so.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts
index 0454423fe166..ad246f9a734a 100644
--- a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts
+++ b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts
@@ -43,3 +43,7 @@ button-restart {
&usb3_phy {
status = "okay";
};
+
+&usb3 {
+ vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
+};
--
2.53.0
^ permalink raw reply related
* [PATCH] ARM: dts: BCM5301X: R6300v2: fix USB3
From: Rosen Penev @ 2026-04-06 22:04 UTC (permalink / raw)
To: devicetree
Cc: Florian Fainelli, Hauke Mehrtens, Rafał Miłecki,
Broadcom internal kernel review list, Rob Herring,
Krzysztof Kozlowski, Conor Dooley,
moderated list:BROADCOM BCM5301X ARM ARCHITECTURE, open list
USB3 needs GPIO to be pulled HIGH in order to function. Add vcc-gpio to
do so.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts
index 77396730bdd3..55f0d9e90d5f 100644
--- a/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts
+++ b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts
@@ -86,3 +86,7 @@ &spi_nor {
&usb3_phy {
status = "okay";
};
+
+&usb3 {
+ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
+};
--
2.53.0
^ permalink raw reply related
* [PATCH v2] arm64: dts: imx8mm: imx8mp: Add DTOs for Data Modul i.MX8M Mini and Plus eDM SBC
From: Marek Vasut @ 2026-04-06 21:58 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Conor Dooley, Fabio Estevam, Frank Li,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, devicetree, imx, linux-kernel
Add DT overlay for feature connector expansion module eDM-MOD-iMX8Mm-FIO1
providing additional UARTs, CAN, PWM Beeper, I2C, SPI and GPIO breakout.
This adapter can be optionally populated onto the eDM SBC.
Add DT overlay for the DSI-to-HDMI adapter eDM-MOD-iMX8Mm-HDMI populated
with Lontium LT9611 bridge. This adapter can be optionally populated onto
the eDM SBC.
Add DT overlay for the DSI-to-LVDS adapter eDM-MOD-iMX8Mm-LVDS populated
with Lontium LT9211 bridge. This adapter can be optionally populated onto
the eDM SBC. This adapter can be extended with multiple panels, currently
supported are the following:
- AUO G215HVN011
- Innolux G070Y2-L01
- Innolux G101ICE-L01
- Innolux G121XCE-L01
- Innolux G156HCE-L01
- Multi-Inno Technology MI0700A2T-30
- Multi-Inno Technology MI1010Z1T-1CP11
Note that in case of the i.MX8M Plus eDM SBC, the adapter name containing
iMX8Mm is not a typo, this is the adapter model string. The adapter was
originally developed for the iMX8Mm eDM SBC.
Add DT overlay which adds CM4/CM7 extras so that CM4/CM7 firmware could
be used with remoteproc and rpmsg, but without imposing the overhead
on every user of the platform. The CM4 variant applies to i.MX8M Mini,
while the CM7 variant applies to i.MX8M Plus .
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
DEPENDS:
- https://patchwork.kernel.org/project/devicetree/patch/20260404033709.340026-1-marex@nabladev.com/
- https://patchwork.kernel.org/project/devicetree/patch/20260404034123.340818-1-marex@nabladev.com/
- https://patchwork.kernel.org/project/devicetree/patch/20260404034321.341210-1-marex@nabladev.com/
https://patchwork.kernel.org/project/devicetree/patch/20260404034321.341210-2-marex@nabladev.com/
- https://patchwork.kernel.org/project/linux-clk/patch/20260406215150.176599-1-marex@nabladev.com/
https://patchwork.kernel.org/project/linux-clk/patch/20260406215150.176599-2-marex@nabladev.com/
https://patchwork.kernel.org/project/linux-clk/patch/20260406215150.176599-3-marex@nabladev.com/
https://patchwork.kernel.org/project/linux-clk/patch/20260406215150.176599-4-marex@nabladev.com/
https://patchwork.kernel.org/project/linux-clk/patch/20260406215150.176599-5-marex@nabladev.com/
https://patchwork.kernel.org/project/linux-clk/patch/20260406215150.176599-6-marex@nabladev.com/
- https://patchwork.kernel.org/project/devicetree/patch/20260404183547.46509-1-marex@nabladev.com/
https://patchwork.kernel.org/project/devicetree/patch/20260404183547.46509-2-marex@nabladev.com/
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Frank Li <Frank.Li@nxp.com>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: devicetree@vger.kernel.org
Cc: imx@lists.linux.dev
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
V2: Deduplicate the DTOs further
---
arch/arm64/boot/dts/freescale/Makefile | 214 +++++++++++++++++-
...imx8mm-data-modul-edm-sbc-overlay-cm4.dtso | 56 +++++
...edm-sbc-overlay-edm-mod-imx8mm-common.dtsi | 59 +++++
...sbc-overlay-edm-mod-imx8mm-fio1-audio.dtsi | 98 ++++++++
...sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso | 80 +++++++
...l-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtsi | 69 ++++++
...l-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso | 59 +++++
...l-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtsi | 92 ++++++++
...l-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso | 19 ++
...bc-overlay-edm-mod-imx8mm-lvds-common.dtsi | 117 ++++++++++
...-sbc-overlay-edm-mod-imx8mm-lvds-dual.dtsi | 32 +++
...verlay-edm-mod-imx8mm-lvds-g070y2-l01.dtsi | 12 +
...verlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso | 7 +
...erlay-edm-mod-imx8mm-lvds-g101ice-l01.dtsi | 12 +
...erlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso | 7 +
...erlay-edm-mod-imx8mm-lvds-g121xce-l01.dtsi | 12 +
...erlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso | 7 +
...erlay-edm-mod-imx8mm-lvds-g151hce-l01.dtsi | 12 +
...erlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso | 7 +
...verlay-edm-mod-imx8mm-lvds-g215hvn011.dtsi | 12 +
...verlay-edm-mod-imx8mm-lvds-g215hvn011.dtso | 7 +
...rlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtsi | 12 +
...rlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso | 7 +
...y-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtsi | 12 +
...y-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso | 7 +
...bc-overlay-edm-mod-imx8mm-lvds-single.dtsi | 20 ++
...l-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi | 26 +++
...edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtso | 18 ++
...m-data-modul-edm-sbc-overlay-lvds-3v3.dtsi | 19 ++
...m-data-modul-edm-sbc-overlay-lvds-5v0.dtsi | 19 ++
...-data-modul-edm-sbc-overlay-lvds-dual.dtsi | 29 +++
...modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi | 31 +++
...odul-edm-sbc-overlay-lvds-g101ice-l01.dtsi | 31 +++
...odul-edm-sbc-overlay-lvds-g121xce-l01.dtsi | 31 +++
...odul-edm-sbc-overlay-lvds-g156hce-l01.dtsi | 31 +++
...modul-edm-sbc-overlay-lvds-g215hvn011.dtsi | 30 +++
...dul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi | 31 +++
...-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi | 31 +++
...ata-modul-edm-sbc-overlay-lvds-single.dtsi | 13 ++
.../freescale/imx8mm-data-modul-edm-sbc.dts | 8 +-
...imx8mp-data-modul-edm-sbc-overlay-cm7.dtso | 57 +++++
...sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso | 68 ++++++
...l-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso | 46 ++++
...l-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso | 19 ++
...verlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso | 7 +
...erlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso | 7 +
...erlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso | 7 +
...erlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso | 7 +
...verlay-edm-mod-imx8mm-lvds-g215hvn011.dtso | 11 +
...rlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso | 7 +
...y-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso | 7 +
...l-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi | 39 ++++
...verlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtso | 24 ++
...erlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtso | 24 ++
...erlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtso | 24 ++
...erlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtso | 32 +++
...verlay-edm-sbc-imx8mp-lvds-g215hvn011.dtso | 36 +++
...rlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtso | 24 ++
...y-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtso | 24 ++
...bc-overlay-edm-sbc-imx8mp-lvds-rev900.dtso | 41 ++++
...bc-overlay-edm-sbc-imx8mp-lvds-rev902.dtso | 14 ++
...l-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi | 79 +++++++
...edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtso | 97 ++++++++
...edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtso | 69 ++++++
.../freescale/imx8mp-data-modul-edm-sbc.dts | 10 +-
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +-
66 files changed, 2162 insertions(+), 16 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-cm4.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-common.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-common.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-dual.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g151hce-l01.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-single.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-3v3.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-5v0.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-dual.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-single.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-cm7.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtso
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 711e36cc2c990..44385fb05c533 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -115,7 +115,81 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdps-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
-dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
+
+imx8mm-data-modul-edm-sbc-overlay-cm4-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-cm4.dtbo
+
+imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtbo
+
+imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtbo
+
+imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtbo
+
+imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo
+
+imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtbo
+
+imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtbo
+
+imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtbo
+
+imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtbo
+
+imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtbo
+
+imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtbo
+
+imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900-dtbs := \
+ imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtbo
+
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-cm4.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-cm4.dtbo \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtbo \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtbo \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtbo \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtbo \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtbo \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtbo \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtbo \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtbo \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtbo \
+ imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtb \
+ imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtbo
+
dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb
@@ -237,7 +311,143 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
DTC_FLAGS_imx8mp-cubox-m := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb
-dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
+
+imx8mp-data-modul-edm-sbc-overlay-cm7-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-cm7.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900-dtbs := \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902-dtbs := \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtbo
+
+imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902-dtbs := \
+ imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtbo
+
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-cm7.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-cm7.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtbo \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtb \
+ imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtbo
+
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-cm4.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-cm4.dtso
new file mode 100644
index 0000000000000..8d681c0eff0d4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-cm4.dtso
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mm-clock.h>
+
+&{/} {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory { /* CM4 reserved memory */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ m_core_reserved: m_core@b7000000 {
+ reg = <0 0xb7000000 0 0x1000000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@b8000000 {
+ reg = <0 0xb8000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@b8008000 {
+ reg = <0 0xb8008000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table: rsc-table@b80ff000 {
+ reg = <0 0xb80ff000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@b8400000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xb8400000 0 0x100000>;
+ no-map;
+ };
+ };
+
+ imx8mm-cm4 {
+ compatible = "fsl,imx8mm-cm4";
+ clocks = <&clk IMX8MM_CLK_M4_CORE>;
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu 0 1
+ &mu 1 1
+ &mu 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;
+ syscon = <&src>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-common.dtsi
new file mode 100644
index 0000000000000..8a95dc05b1fcf
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-common.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&{/} {
+ reg_backlight_en_level: regulator-backlight-en-level {
+ compatible = "regulator-gpio";
+ regulator-name = "Backlight_SEL_EN";
+ regulator-type = "voltage";
+ states = <3300000 0x0>,
+ <5000000 0x1>;
+
+ /* Default setting: lowest supported voltage. */
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_backlight_pwm_level: regulator-backlight-pwm-level {
+ compatible = "regulator-gpio";
+ regulator-name = "Backlight_SEL_PWM";
+ regulator-type = "voltage";
+ gpios = <&gpio_display 2 GPIO_ACTIVE_HIGH>; /* SEL_PWM */
+ states = <3300000 0x0>,
+ <5000000 0x1>;
+
+ /* Default setting: lowest supported voltage. */
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_panel_bl: regulator-panel-bl {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel_backlight>;
+ regulator-name = "PANEL_BL";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 0 0>;
+ enable-active-high;
+ /* Used by panels which enable PWM signal before BL ON/OFF */
+ status = "disabled";
+ };
+};
+
+®_panel_vcc {
+ compatible = "regulator-gpio";
+ regulator-type = "voltage";
+ enable-active-high;
+ status = "okay";
+
+ /* Default setting: lowest supported voltage. */
+ gpios-states = <0 0>; /* Default GPIO state is LOW/LOW, so 3V3 out */
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtsi
new file mode 100644
index 0000000000000..a4d503d1d3b63
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtsi
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&{/} {
+ can_osc: can-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
+
+ sound-fio {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SGTL5000-FIO1";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&codec_dai_fio>;
+ simple-audio-card,frame-master = <&codec_dai_fio>;
+ simple-audio-card,widgets = "Headphone", "Headphone Jack";
+ simple-audio-card,routing = "Headphone Jack", "HP_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+
+ codec_dai_fio: simple-audio-card,codec {
+ sound-dai = <&sgtl5000_fio>;
+ };
+ };
+};
+
+&ecspi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ can_fio: can@0 {
+ compatible = "microchip,mcp2518fd";
+ reg = <0>;
+ clocks = <&can_osc>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&i2c_feature { /* Feature connector I2C */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgtl5000_fio: codec@a {
+ #sound-dai-cells = <0>;
+ clocks = <&sai5clk 1>;
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ };
+
+ gpio_feature: io-expander@20 {
+ compatible = "nxp,pca9554";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio5>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "GPI0", "GPI1", "GPI2", "GPI3",
+ "GPO0", "GPO1", "GPO2", "GPO3";
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
+
+&sai2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clock-rates = <24576000>;
+ fsl,sai-asynchronous;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&uart2 { /* RS422 J12 */
+ linux,rs485-enabled-at-boot-time;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* UART4 is blocked by RDC and used as CM4 console UART */
+&uart4 { /* UART to 1-Wire J5 */
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
new file mode 100644
index 0000000000000..f446938b74006
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mm-clock.h>
+
+#include "imx8mm-pinfunc.h"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtsi"
+
+&can_fio {
+ interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&iomuxc {
+ pinctrl_codec_mclk: codec-mclk_feature-grp {
+ fsl,pins = <
+ /* GPIO4_IO27 */
+ MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x2
+ >;
+ };
+
+ pinctrl_sai2: sai2_feature-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x90
+ MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x96
+ MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x90
+ MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x96
+ >;
+ };
+};
+
+&pinctrl_hog_feature {
+ fsl,pins = <
+ /* GPIO5_IO03 */
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006
+ /* GPIO5_IO04 */
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006
+
+ /* CAN_INT# */
+ MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090
+ >;
+};
+
+&sai2 {
+ assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ fsl,sai-bit-clock-swap;
+};
+
+&sgtl5000_fio {
+ VDDA-supply = <&buck4_reg>;
+ VDDD-supply = <&buck5_reg>;
+ VDDIO-supply = <&buck4_reg>;
+};
+
+&spba2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sai5clk: clock-controller@30050000 { /* SAI5 */
+ compatible = "fsl,imx8mm-sai-clock", "fsl,imx8mq-sai-clock";
+ reg = <0x30050000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
+ <&clk IMX8MM_CLK_SAI5_ROOT>;
+ clock-names = "bus", "mclk1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_codec_mclk>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI5>,
+ <&clk IMX8MM_CLK_CLKOUT1_SEL>,
+ <&clk IMX8MM_CLK_CLKOUT2_SEL>;
+ assigned-clock-parents = <&clk IMX8MM_CLK_24M>,
+ <&clk IMX8MM_CLK_24M>,
+ <&clk IMX8MM_CLK_24M>;
+ assigned-clock-rates = <24000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtsi
new file mode 100644
index 0000000000000..7851ca73ccd8e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&{/} {
+ can_osc: can-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
+};
+
+&ecspi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ can_fio: can@0 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can>;
+ clocks = <&can_osc>;
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&i2c_feature { /* Feature connector I2C */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio_feature: io-expander@20 {
+ compatible = "nxp,pca9554";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_expander>;
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio4>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "GPIO1_output", "GPIO1_input",
+ "GPIO2_output", "GPIO2_input",
+ "GPIO3_output", "GPIO3_input",
+ "PCA9511A_READY", "";
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
+
+&uart1 { /* J500/J501 */
+ status = "okay";
+};
+
+&uart2 { /* RS485 J302/J303 */
+ linux,rs485-enabled-at-boot-time;
+ uart-has-rtscts;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
new file mode 100644
index 0000000000000..ad410db5f5b76
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mm-pinfunc.h"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtsi"
+
+&{/} {
+ beeper {
+ compatible = "pwm-beeper";
+ beeper-hz = <1000>;
+ pwms = <&pwm3 0 250000 0>;
+ };
+};
+
+&can_fio {
+ interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&iomuxc {
+ pinctrl_can: can-feature-grp {
+ fsl,pins = <
+ /* CAN_INT# */
+ MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x400000d6
+ /* CAN_RST# */
+ MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x6
+ >;
+ };
+
+ pinctrl_gpio_expander: gpio-expander-feature-grp {
+ fsl,pins = <
+ /* GPIO4_IO27 */
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x6
+ >;
+ };
+
+ pinctrl_pwm3: pwm3-buzzer-feature-grp {
+ fsl,pins = <
+ /* Buzzer PWM output */
+ MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x100
+ >;
+ };
+};
+
+&pinctrl_hog_feature {
+ fsl,pins = <
+ /* GPIO5_IO04 */
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x6
+ >;
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtsi
new file mode 100644
index 0000000000000..c91b7a2781d27
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&{/} {
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+};
+
+&i2c_display { /* Display connector I2C */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lt9611_codec: hdmi-bridge@3b {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel_expansion>;
+ compatible = "lontium,lt9611";
+ reg = <0x3b>;
+
+ /* Audio I2S not described */
+ #sound-dai-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mipi_dsi_bridge1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&iomuxc {
+ /* Free &pinctrl_panel_expansion from hog for lt9611_codec above */
+ pinctrl-0 = <&pinctrl_hog_misc>, <&pinctrl_hog_feature>,
+ <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>;
+};
+
+&mipi_dsi {
+ /* HDMI 148.5 MHz x2 (DDR) x3 (24bpp / 8) */
+ samsung,burst-clock-frequency = <891000000>;
+ samsung,esc-clock-frequency = <10000000>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ mipi_dsi_bridge1_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ /* Clock and data lanes have DN/DP swapped */
+ lane-polarities = <1 1 1 1 1>;
+ remote-endpoint = <<9611_a>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
new file mode 100644
index 0000000000000..49f9d3073748c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtsi"
+
+<9611_codec {
+ interrupts-extended = <&gpio2 3 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ vdd-supply = <&buck5_reg>; /* X400 pin 51, +1V8_S0 */
+ vcc-supply = <&buck4_reg>; /* X400 pin 55, +3V3_S0 */
+};
+
+&lcdif {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-common.dtsi
new file mode 100644
index 0000000000000..971468e4edc80
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-common.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+&{/} {
+ reg_lt9211_vcc18: regulator-lt9211-vcc18 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9211_VCC18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&i2c_display { /* Display connector I2C */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+
+ lt9211_codec: bridge@2d {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel_expansion>;
+ compatible = "lontium,lt9211";
+ reg = <0x2d>;
+ interrupts-extended = <&gpio2 3 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ vccio-supply = <®_lt9211_vcc18>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9211_a: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&mipi_dsi_bridge1_out>;
+ };
+ };
+ };
+ };
+
+ gpio_display: io-expander@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "SEL_12V", "SEL_5V", "SEL_PWM", "SEL_EN";
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+®_backlight_en_level {
+ gpios = <&gpio_display 3 GPIO_ACTIVE_HIGH>; /* SEL_EN */
+};
+
+®_backlight_pwm_level {
+ gpios = <&gpio_display 2 GPIO_ACTIVE_HIGH>; /* SEL_PWM */
+};
+
+®_panel_bl {
+ gpio = <&gpio3 0 0>;
+};
+
+&iomuxc {
+ /* Free &pinctrl_panel_expansion from hog for lt9211_codec above */
+ pinctrl-0 = <&pinctrl_hog_misc>, <&pinctrl_hog_feature>,
+ <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>;
+};
+
+&mipi_dsi {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ mipi_dsi_bridge1_out: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ /* Clock and data lanes have DN/DP swapped */
+ lane-polarities = <1 1 1 1 1>;
+ remote-endpoint = <<9211_a>;
+ };
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+®_panel_vcc {
+ /*
+ * AP63300 voltage divider settings:
+ * R1=16k2
+ * R2=5k23 with optional series Rs=7k68 (5V) or Rt=1k5 (12V)
+ *
+ * 1 / Rx = (1 / R2) [ + (1 / Rs)][ + (1 / Rt)]
+ * Vout = 0.8 * ((R1 / Rx) + 1)
+ */
+ gpios = <&gpio_display 1 GPIO_ACTIVE_HIGH>, /* 5V */
+ <&gpio_display 0 GPIO_ACTIVE_HIGH>; /* 12V */
+ states = <3300000 0x0>,
+ <5000000 0x1>,
+ <12000000 0x2>,
+ <3900000 0x3>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-dual.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-dual.dtsi
new file mode 100644
index 0000000000000..abe50eb8b4b61
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-dual.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+<9211_codec {
+ ports {
+ port@2 {
+ reg = <2>;
+
+ lt9211_out_a: endpoint {
+ remote-endpoint = <&panel_lvds_a>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ lt9211_out_b: endpoint {
+ remote-endpoint = <&panel_lvds_b>;
+ };
+ };
+ };
+};
+
+&panel_lvds_a {
+ remote-endpoint = <<9211_out_a>;
+};
+
+&panel_lvds_b {
+ remote-endpoint = <<9211_out_b>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtsi
new file mode 100644
index 0000000000000..cca52464a695e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-single.dtsi"
+
+&mipi_dsi {
+ samsung,burst-clock-frequency = <216000000>; /* RX ByteClock ~27 MHz */
+ samsung,esc-clock-frequency = <10000000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
new file mode 100644
index 0000000000000..5d1ea31f33de3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtsi
new file mode 100644
index 0000000000000..52d216fbba432
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-single.dtsi"
+
+&mipi_dsi {
+ samsung,burst-clock-frequency = <515000000>;
+ samsung,esc-clock-frequency = <10000000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
new file mode 100644
index 0000000000000..2d1bbdd065227
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtsi
new file mode 100644
index 0000000000000..aba3c9a1a3e8a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-single.dtsi"
+
+&mipi_dsi {
+ samsung,burst-clock-frequency = <470000000>;
+ samsung,esc-clock-frequency = <10000000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
new file mode 100644
index 0000000000000..bc2f6fef6256e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g151hce-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g151hce-l01.dtsi
new file mode 100644
index 0000000000000..f478f4e557cce
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g151hce-l01.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-dual.dtsi"
+
+&mipi_dsi {
+ samsung,burst-clock-frequency = <864000000>;
+ samsung,esc-clock-frequency = <10000000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
new file mode 100644
index 0000000000000..5f77946e042e3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g151hce-l01.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtsi
new file mode 100644
index 0000000000000..21bec8a01287e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-dual.dtsi"
+
+&mipi_dsi {
+ samsung,burst-clock-frequency = <864000000>; /* RX ByteClock ~27 MHz */
+ samsung,esc-clock-frequency = <10000000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
new file mode 100644
index 0000000000000..75ae12dfd7fc6
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtsi
new file mode 100644
index 0000000000000..38a3a9a4c75b3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-single.dtsi"
+
+&mipi_dsi {
+ samsung,burst-clock-frequency = <216000000>; /* RX ByteClock ~27 MHz */
+ samsung,esc-clock-frequency = <10000000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
new file mode 100644
index 0000000000000..ee2c79664e355
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtsi
new file mode 100644
index 0000000000000..98b5c5883cfd0
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-single.dtsi"
+
+&mipi_dsi {
+ samsung,burst-clock-frequency = <400000000>;
+ samsung,esc-clock-frequency = <10000000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
new file mode 100644
index 0000000000000..d05f0dcc3137c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-single.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-single.dtsi
new file mode 100644
index 0000000000000..9e70c1481c1eb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-single.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+<9211_codec {
+ ports {
+ port@2 {
+ reg = <2>;
+
+ lt9211_out_a: endpoint {
+ remote-endpoint = <&panel_lvds>;
+ };
+ };
+ };
+};
+
+&panel_lvds {
+ remote-endpoint = <<9211_out_a>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
new file mode 100644
index 0000000000000..200bc8be0353b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-common.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-common.dtsi"
+
+<9211_codec {
+ interrupts-extended = <&gpio2 3 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+};
+
+®_lt9211_vcc18 {
+ vin-supply = <&buck5_reg>; /* X400 pin 51, +1V8_S0 */
+};
+
+&lcdif {
+ status = "okay";
+};
+
+®_panel_vcc {
+ enable-gpios = <&gpio3 6 0>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtso
new file mode 100644
index 0000000000000..14038215f298c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-sbc-imx8mm-rev900.dtso
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&fec1 {
+ phy-handle = <&fec1_phy_ath>;
+};
+
+&fec1_phy_ath {
+ status = "okay";
+};
+
+&fec1_phy_bcm {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-3v3.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-3v3.dtsi
new file mode 100644
index 0000000000000..0955764c0ebff
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-3v3.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+®_backlight_pwm_level {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+};
+
+®_backlight_en_level {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+};
+
+®_panel_vcc {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-5v0.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-5v0.dtsi
new file mode 100644
index 0000000000000..70ad6bb9b80ac
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-5v0.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+®_backlight_pwm_level {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+};
+
+®_backlight_en_level {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+};
+
+®_panel_vcc {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-dual.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-dual.dtsi
new file mode 100644
index 0000000000000..65f9ad81cfbc7
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-dual.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+&panel {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dual-lvds-odd-pixels;
+
+ panel_lvds_b: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dual-lvds-even-pixels;
+
+ panel_lvds_a: endpoint {
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi
new file mode 100644
index 0000000000000..80f7b74f1ea08
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-3v3.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-single.dtsi"
+
+&backlight {
+ power-supply = <®_panel_bl>;
+ /* 6.3 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
+ pwm-off-delay-ms = <10>;
+ /* 3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
+ pwms = <&pwm1 0 5000000 0>;
+ status = "okay";
+};
+
+&panel {
+ compatible = "innolux,g070y2-l01";
+};
+
+®_panel_bl {
+ startup-delay-us = <10000>; /* T8 */
+ off-on-delay-us = <550000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
+ status = "okay";
+};
+
+®_panel_vcc {
+ /* 6.3 POWER ON/OFF SEQUENCE */
+ startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi
new file mode 100644
index 0000000000000..1a2bd204c30b1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-3v3.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-single.dtsi"
+
+&backlight {
+ power-supply = <®_panel_bl>;
+ /* 6.3 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
+ pwm-off-delay-ms = <10>;
+ /* 3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
+ pwms = <&pwm1 0 5000000 0>;
+ status = "okay";
+};
+
+&panel {
+ compatible = "innolux,g101ice-l01";
+};
+
+®_panel_bl {
+ startup-delay-us = <10000>; /* T8 */
+ off-on-delay-us = <950000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
+ status = "okay";
+};
+
+®_panel_vcc {
+ /* 6.3 POWER ON/OFF SEQUENCE */
+ startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi
new file mode 100644
index 0000000000000..f87e8c821dacb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 Wael Karman <wkarman@data-modul.com>
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-3v3.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-single.dtsi"
+
+&backlight {
+ power-supply = <®_panel_bl>;
+ /* 6.2 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
+ pwm-off-delay-ms = <10>;
+ /* 3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
+ pwms = <&pwm1 0 5000000 0>;
+ status = "okay";
+};
+
+&panel {
+ compatible = "innolux,g121xce-l01";
+};
+
+®_panel_bl {
+ startup-delay-us = <10000>; /* T8 */
+ off-on-delay-us = <1180000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
+ status = "okay";
+};
+
+®_panel_vcc {
+ /* 6.2 POWER ON/OFF SEQUENCE */
+ startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi
new file mode 100644
index 0000000000000..46c8bc7021a4f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-3v3.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-dual.dtsi"
+
+&backlight {
+ power-supply = <®_panel_bl>;
+ /* 4.6 POWER ON/OFF SEQUENCE, T9 >= 10 ms */
+ pwm-off-delay-ms = <10>;
+ /* 4.3.2 BACKLIGHT UNIT fPWM=200 Hz (Typ.), value below in ns */
+ pwms = <&pwm1 0 5000000 0>;
+ status = "okay";
+};
+
+&panel {
+ compatible = "innolux,g156hce-l01";
+};
+
+®_panel_bl {
+ startup-delay-us = <10000>; /* T8 */
+ off-on-delay-us = <1170000>; /* T9 + T6 + T3 + T7 + T4 + T1 + T2 + T5 */
+ status = "okay";
+};
+
+®_panel_vcc {
+ /* 4.6 POWER ON/OFF SEQUENCE */
+ startup-delay-us = <1000>; /* 0.5ms <= T1 + T2 <= 60 ms */
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi
new file mode 100644
index 0000000000000..3585170bd59dd
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-5v0.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-dual.dtsi"
+
+&backlight {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel_backlight>;
+ enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
+ /* 6.5 POWER ON/OFF SEQUENCE, T6 >= 10 ms */
+ post-pwm-on-delay-ms = <10>;
+ /* 6.5 POWER ON/OFF SEQUENCE, T7 >= 0 ms */
+ pwm-off-delay-ms = <10>;
+ /* 5.2 BACKLIGHT UNIT 200Hz..20kHz, value below in ns */
+ pwms = <&pwm1 0 66666 0>; /* 15 kHz = 66666ns */
+ status = "okay";
+};
+
+&panel {
+ /* The G215HVN01 is replacement for T215HVN01, which is supported. */
+ compatible = "auo,t215hvn01";
+};
+
+®_panel_vcc {
+ /* 6.5 POWER ON/OFF SEQUENCE */
+ startup-delay-us = <40000>; /* 30.5ms <= T1 + T2 <= 60 ms */
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi
new file mode 100644
index 0000000000000..4a077e6e6b8af
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-3v3.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-single.dtsi"
+
+&backlight {
+ power-supply = <®_panel_bl>;
+ /* 1.5 POWER ON/OFF SEQUENCE, T4 >= 200 ms */
+ pwm-off-delay-ms = <200>;
+ /* ELECTRICAL CHARACTERISTICS, BL_ADJ Frequency 20K HZ Typ., value below in ns */
+ pwms = <&pwm1 0 50000 0>;
+ status = "okay";
+};
+
+&panel {
+ compatible = "multi-inno,mi0700a2t-30";
+};
+
+®_panel_bl {
+ startup-delay-us = <200000>; /* T3 */
+ off-on-delay-us = <1450000>; /* T4 + T5 + T6 + T1 + T2 + T3 */
+ status = "okay";
+};
+
+®_panel_vcc {
+ /* 1.5 POWER ON/OFF SEQUENCE */
+ startup-delay-us = <60000>; /* T1 + T2 >= 1 ms (typ. 60ms) */
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi
new file mode 100644
index 0000000000000..e8d8cd85d04ae
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-3v3.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-single.dtsi"
+
+&backlight {
+ power-supply = <®_panel_bl>;
+ /* 3 POWER ON/OFF SEQUENCE, T7 >= 200 ms */
+ pwm-off-delay-ms = <200>;
+ /* ELECTRICAL CHARACTERISTICS, BL_ADJ Frequency 20K HZ Typ., value below in ns */
+ pwms = <&pwm1 0 50000 0>;
+ status = "okay";
+};
+
+&panel {
+ compatible = "multi-inno,mi1010z1t-1cp11";
+};
+
+®_panel_bl {
+ startup-delay-us = <200000>; /* T6 */
+ off-on-delay-us = <1450000>; /* T7 + T3 + T4 + T5 + T1 + T2 + T6 */
+ status = "okay";
+};
+
+®_panel_vcc {
+ /* 3 POWER ON/OFF SEQUENCE */
+ startup-delay-us = <60000>; /* T1 + T2 >= 1 ms (typ. 60ms) */
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-single.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-single.dtsi
new file mode 100644
index 0000000000000..68c20692241a1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-lvds-single.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Marek Vasut
+ */
+
+&panel {
+ status = "okay";
+
+ port {
+ panel_lvds: endpoint {
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
index 472c584fb3bd2..df857de0375cf 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
@@ -30,11 +30,8 @@ memory@40000000 {
backlight: backlight {
compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_panel_backlight>;
brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
default-brightness-level = <7>;
- enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
pwms = <&pwm1 0 5000000 0>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
@@ -66,7 +63,6 @@ reg_panel_vcc: regulator-panel-vcc {
regulator-name = "PANEL_VCC";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 6 0>;
enable-active-high;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
@@ -454,7 +450,7 @@ pcieclk: clk@6a {
};
};
-&i2c3 { /* Display connector I2C */
+i2c_display: &i2c3 { /* Display connector I2C */
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <320000>;
pinctrl-names = "default", "gpio";
@@ -465,7 +461,7 @@ &i2c3 { /* Display connector I2C */
status = "okay";
};
-&i2c4 { /* Feature connector I2C */
+i2c_feature: &i2c4 { /* Feature connector I2C */
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <320000>;
pinctrl-names = "default", "gpio";
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-cm7.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-cm7.dtso
new file mode 100644
index 0000000000000..21e2a8c0bab0a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-cm7.dtso
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+&{/} {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory { /* CM7 reserved memory */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ m_core_reserved: m_core@54000000 {
+ reg = <0 0x54000000 0 0x1000000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@55000000 {
+ reg = <0 0x55000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@55008000 {
+ reg = <0 0x55008000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table: rsc-table@550ff000 {
+ reg = <0 0x550ff000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@55400000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x55400000 0 0x100000>;
+ no-map;
+ };
+ };
+
+ imx8mp-cm7 {
+ compatible = "fsl,imx8mp-cm7-mmio";
+ clocks = <&clk IMX8MP_CLK_M7_CORE>;
+ fsl,iomuxc-gpr = <&gpr>;
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu 0 1
+ &mu 1 1
+ &mu 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;
+ syscon = <&src>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
new file mode 100644
index 0000000000000..8df1a860348d5
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+#include "imx8mp-pinfunc.h"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtsi"
+
+&can_fio {
+ interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&iomuxc {
+ pinctrl_codec_mclk: codec-mclk_feature-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0xd6
+ >;
+ };
+
+ sai2-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
+ MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
+ MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
+ >;
+ };
+
+ uart1-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x49
+ MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x49
+ MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x49
+ >;
+ };
+};
+
+&sai2 {
+ assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
+};
+
+&sgtl5000_fio {
+ VDDA-supply = <&buck4>;
+ VDDD-supply = <&buck5>;
+ VDDIO-supply = <&buck4>;
+};
+
+&spba5 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sai5clk: clock-controller@30c50000 {
+ compatible = "fsl,imx8mp-sai-clock", "fsl,imx8mq-sai-clock";
+ reg = <0x30c50000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>;
+ clock-names = "bus", "mclk1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_codec_mclk>;
+ status = "okay";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
new file mode 100644
index 0000000000000..0eccb7f7c0a8c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtso
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-pinfunc.h"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1.dtsi"
+
+&can_fio {
+ interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&iomuxc {
+ pinctrl_can: can-feature-grp {
+ fsl,pins = <
+ /* CAN_INT# */
+ MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x400000d6
+ >;
+ };
+
+ pinctrl_gpio_expander: gpio-expander-feature-grp {
+ fsl,pins = <
+ /* GPIO4_IO27 */
+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6
+ >;
+ };
+};
+
+&pinctrl_sai2 {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
+ MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
+ >;
+};
+
+&pinctrl_hog_feature {
+ fsl,pins = <
+ /* GPIO5_IO03 */
+ MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40000006
+ /* GPIO5_IO04 */
+ MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40000006
+ >;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
new file mode 100644
index 0000000000000..22ded48fc8ccf
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtso
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-hdmi.dtsi"
+
+<9611_codec {
+ interrupts-extended = <&gpio4 19 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ vdd-supply = <&buck5>; /* X400 pin 51, +1V8_S0 */
+ vcc-supply = <&buck4>; /* X400 pin 55, +3V3_S0 */
+};
+
+&lcdif1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
new file mode 100644
index 0000000000000..6b6b160c0f3a1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g070y2-l01.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
new file mode 100644
index 0000000000000..549ea2ab8819a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g101ice-l01.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
new file mode 100644
index 0000000000000..c8c4328218152
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g121xce-l01.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
new file mode 100644
index 0000000000000..033eb210917cd
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g156hce-l01.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g151hce-l01.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
new file mode 100644
index 0000000000000..faf2c06fc50c3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtso
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-g215hvn011.dtsi"
+
+&backlight {
+ power-supply = <®_panel_bl_supply>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
new file mode 100644
index 0000000000000..359a8b1521b01
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi0700a2t-30.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
new file mode 100644
index 0000000000000..525cedb64a776
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtso
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-mi1010z1t-1cp11.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
new file mode 100644
index 0000000000000..86aa8d5e822d3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-common.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-lvds-common.dtsi"
+
+&{/} {
+ reg_panel_bl_supply: regulator-panel-bl-supply {
+ compatible = "regulator-fixed";
+ regulator-name = "BKLT0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+};
+
+&lcdif1 {
+ status = "okay";
+};
+
+<9211_codec {
+ interrupts-extended = <&gpio4 19 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+};
+
+®_lt9211_vcc18 {
+ vin-supply = <&buck5>; /* X400 pin 51, +1V8_S0 */
+};
+
+®_panel_bl {
+ vin-supply = <®_panel_bl_supply>;
+};
+
+®_panel_vcc {
+ enable-gpios = <&gpio3 6 0>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtso
new file mode 100644
index 0000000000000..7a4126214a4f6
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g070y2-l01.dtso
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-g070y2-l01.dtsi"
+
+&media_blk_ctrl {
+ /*
+ * The G070Y2-L01 panel requires 29.5 MHz LVDS clock.
+ * Set IMX8MP_VIDEO_PLL1 to 206.5 MHz , since 206.5 MHz / 7 = 29.5 MHz .
+ */
+ assigned-clock-rates = <500000000>, <200000000>,
+ <0>, <0>, <500000000>, <206500000>;
+};
+
+&ldb_lvds_ch1 {
+ remote-endpoint = <&panel_lvds>;
+};
+
+&panel_lvds {
+ remote-endpoint = <&ldb_lvds_ch1>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtso
new file mode 100644
index 0000000000000..817d4ec62d0e8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g101ice-l01.dtso
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-g101ice-l01.dtsi"
+
+&media_blk_ctrl {
+ /*
+ * The G101ICE-L01 panel requires 71.1 MHz LVDS clock.
+ * Set IMX8MP_VIDEO_PLL1 to 497.7 MHz , since 497.7 MHz / 7 = 71.1 MHz .
+ */
+ assigned-clock-rates = <500000000>, <200000000>,
+ <0>, <0>, <500000000>, <497700000>;
+};
+
+&ldb_lvds_ch1 {
+ remote-endpoint = <&panel_lvds>;
+};
+
+&panel_lvds {
+ remote-endpoint = <&ldb_lvds_ch1>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtso
new file mode 100644
index 0000000000000..729f477038b17
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g121xce-l01.dtso
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 Wael Karman <wkarman@data-modul.com>
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-g121xce-l01.dtsi"
+
+&media_blk_ctrl {
+ /*
+ * The G121XCE-L01 panel requires 64.9 MHz LVDS clock.
+ * Set IMX8MP_VIDEO_PLL1 to 454.3 MHz , since 454.3 MHz / 7 = 64.9 MHz .
+ */
+ assigned-clock-rates = <500000000>, <200000000>,
+ <0>, <0>, <500000000>, <454300000>;
+};
+
+&ldb_lvds_ch1 {
+ remote-endpoint = <&panel_lvds>;
+};
+
+&panel_lvds {
+ remote-endpoint = <&ldb_lvds_ch1>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtso
new file mode 100644
index 0000000000000..86163d6ddd5c6
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g156hce-l01.dtso
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-g156hce-l01.dtsi"
+
+&media_blk_ctrl {
+ /*
+ * The G156HCE-L01 panel requires 141.86 MHz LVDS clock.
+ * Set IMX8MP_VIDEO_PLL1 to 993.2 MHz , since 993.2 MHz / 7 = 141.86 MHz .
+ */
+ assigned-clock-rates = <500000000>, <200000000>,
+ <0>, <0>, <500000000>, <993020000>;
+};
+
+&ldb_lvds_ch0 {
+ remote-endpoint = <&panel_lvds_b>;
+};
+
+&ldb_lvds_ch1 {
+ remote-endpoint = <&panel_lvds_a>;
+};
+
+&panel_lvds_a {
+ remote-endpoint = <&ldb_lvds_ch1>;
+};
+
+&panel_lvds_b {
+ remote-endpoint = <&ldb_lvds_ch0>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtso
new file mode 100644
index 0000000000000..a6d13c3609796
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-g215hvn011.dtso
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-g215hvn011.dtsi"
+
+&backlight {
+ power-supply = <®_panel_bl_supply>;
+};
+
+&media_blk_ctrl {
+ /*
+ * The G215HVN01 panel requires 148.8 MHz LVDS clock.
+ * Set IMX8MP_VIDEO_PLL1 to 1041.6 MHz , since 1041.6 MHz / 7 = 148.8 MHz .
+ */
+ assigned-clock-rates = <500000000>, <200000000>,
+ <0>, <0>, <500000000>, <1041600000>;
+};
+
+&ldb_lvds_ch0 {
+ remote-endpoint = <&panel_lvds_b>;
+};
+
+&ldb_lvds_ch1 {
+ remote-endpoint = <&panel_lvds_a>;
+};
+
+&panel_lvds_a {
+ remote-endpoint = <&ldb_lvds_ch1>;
+};
+
+&panel_lvds_b {
+ remote-endpoint = <&ldb_lvds_ch0>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtso
new file mode 100644
index 0000000000000..76bfbd307ba2d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi0700a2t-30.dtso
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-mi0700a2t-30.dtsi"
+
+&media_blk_ctrl {
+ /*
+ * The MI0700A2T-30 panel requires 33 MHz LVDS clock.
+ * Set IMX8MP_VIDEO_PLL1 to 231 MHz , since 231 MHz / 7 = 33 MHz .
+ */
+ assigned-clock-rates = <500000000>, <200000000>,
+ <0>, <0>, <500000000>, <231000000>;
+};
+
+&ldb_lvds_ch1 {
+ remote-endpoint = <&panel_lvds>;
+};
+
+&panel_lvds {
+ remote-endpoint = <&ldb_lvds_ch1>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtso
new file mode 100644
index 0000000000000..4066bac28f3df
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-mi1010z1t-1cp11.dtso
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024-2026 Marek Vasut
+ */
+
+#include "imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi"
+#include "imx8mm-data-modul-edm-sbc-overlay-lvds-mi1010z1t-1cp11.dtsi"
+
+&media_blk_ctrl {
+ /*
+ * The MI1010Z1T-1CP11 panel requires 51.2 MHz LVDS clock.
+ * Set IMX8MP_VIDEO_PLL1 to 358.4 MHz , since 358.4 MHz / 7 = 51.2 MHz .
+ */
+ assigned-clock-rates = <500000000>, <200000000>,
+ <0>, <0>, <500000000>, <358400000>;
+};
+
+&ldb_lvds_ch1 {
+ remote-endpoint = <&panel_lvds>;
+};
+
+&panel_lvds {
+ remote-endpoint = <&ldb_lvds_ch1>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtso
new file mode 100644
index 0000000000000..427585b78e45d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev900.dtso
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ reg_panel_vcc_raw: regulator-panel-vcc-raw {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel_vcc_reg>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "PANEL_VCC";
+ };
+};
+
+&panel {
+ power-supply = <®_panel_vcc_raw>;
+};
+
+®_backlight_en_level {
+ status = "disabled";
+};
+
+®_backlight_pwm_level {
+ status = "disabled";
+};
+
+®_panel_bl_supply {
+ status = "disabled";
+};
+
+®_panel_bl {
+ gpio = <&gpio3 0 0>;
+};
+
+®_panel_vcc {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtso
new file mode 100644
index 0000000000000..a21fea27e0b41
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds-rev902.dtso
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+®_panel_bl {
+ gpio = <&gpio3 0 0>;
+};
+
+®_panel_vcc {
+ enable-gpios = <&gpio3 6 0>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi
new file mode 100644
index 0000000000000..b06af369a9245
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-lvds.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-common.dtsi"
+
+&{/} {
+ reg_panel_bl_supply: regulator-panel-bl-supply {
+ compatible = "regulator-gpio";
+ regulator-type = "voltage";
+ regulator-name = "PANEL_BL_SUPPLY";
+ enable-gpios = <&gpiolvds 0 0>;
+ enable-active-high;
+ status = "okay";
+
+ /*
+ * MP2328 voltage divider settings:
+ * R1=51k1
+ * R2=5k62 with optional series Rs=2k21 (12V)
+ *
+ * 1 / Rx = (1 / R2) [ + (1 / Rs)][ + (1 / Rt)]
+ * Vout = 0.5 + ((R1 / Rx) * 0.5)
+ */
+ gpios = <&gpiolvds 1 GPIO_ACTIVE_HIGH>; /* 12V */
+ states = <5000000 0x0>,
+ <12000000 0x1>;
+
+ /* Default setting: lowest supported voltage. */
+ gpios-states = <1>; /* Default GPIO state is HIGH, so 12V0 out */
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+};
+
+&lcdif2 {
+ status = "okay";
+};
+
+&lvds_bridge {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+®_backlight_en_level {
+ gpios = <&gpiolvds 5 GPIO_ACTIVE_HIGH>; /* SEL_EN */
+};
+
+®_backlight_pwm_level {
+ gpios = <&gpiolvds 4 GPIO_ACTIVE_HIGH>; /* SEL_PWM */
+};
+
+®_panel_bl {
+ gpio = <&gpiowifi 0 0>;
+ vin-supply = <®_panel_bl_supply>;
+};
+
+®_panel_vcc {
+ enable-gpios = <&gpiowifi 4 0>;
+ /*
+ * MP2328 voltage divider settings:
+ * R1=51k1
+ * R2=9k09 with optional series Rs=5k62 (5V) or Rt=2k21 (12V)
+ *
+ * 1 / Rx = (1 / R2) [ + (1 / Rs)][ + (1 / Rt)]
+ * Vout = 0.5 + ((R1 / Rx) * 0.5)
+ */
+ gpios = <&gpiolvds 2 GPIO_ACTIVE_HIGH>, /* 5V */
+ <&gpiolvds 3 GPIO_ACTIVE_HIGH>; /* 12V */
+ states = <3300000 0x0>,
+ <5000000 0x1>,
+ <12000000 0x2>,
+ <14000000 0x3>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtso
new file mode 100644
index 0000000000000..ec861aa64541e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev900.dtso
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-pinfunc.h"
+
+&eeprom900 {
+ status = "okay";
+};
+
+&eeprom902 {
+ status = "disabled";
+};
+
+&eqos { /* First ethernet */
+ phy-handle = <&phy_eqos_ath>;
+};
+
+&fec { /* Second ethernet */
+ /* pinctrl_wifi is ENET2_INT# */
+ pinctrl-0 = <&pinctrl_fec &pinctrl_wifi>;
+ phy-handle = <&phy_fec_ath>;
+};
+
+&gpiolvds {
+ status = "disabled";
+};
+
+/*
+ * External pull ups on R242 and R243 on I2C2_SCL_3V3 and I2C2_SDA_3V3
+ * are not populated on this early board revision, activate in-SoC pull
+ * up resistors instead to work around the missing external pull ups.
+ */
+&pinctrl_i2c2 {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c4
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c4
+ >;
+};
+
+&pinctrl_i2c2_gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c4
+ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c4
+ >;
+};
+
+&pcie_phy {
+ status = "disabled";
+};
+
+&pcie {
+ status = "disabled";
+};
+
+&phy_eqos_ath {
+ /*
+ * The software support for combination of EEE capable PHY and EEE
+ * capable MAC is so far missing from the Linux kernel. By default,
+ * the AR8035 PHY does enable EEE functionality on the PHY side,
+ * while the EQoS/DWMAC MAC expects to handle the EEE functionality
+ * on the MAC side. Because the Linux kernel is currently unable to
+ * align EEE configuration of the PHY and MAC, enabling EEE leads
+ * to unreliable link. Disable EEE until the kernel support is in
+ * place.
+ */
+ eee-broken-100tx;
+ eee-broken-1000t;
+ status = "okay";
+};
+
+&phy_eqos_bcm {
+ status = "disabled";
+};
+
+&phy_fec_ath {
+ status = "okay";
+};
+
+&phy_fec_bcm {
+ status = "disabled";
+};
+
+®_pcie0 {
+ status = "disabled";
+};
+
+&tpm {
+ status = "disabled";
+};
+
+&uart4 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtso b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtso
new file mode 100644
index 0000000000000..0141b5d77c6bd
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc-overlay-edm-sbc-imx8mp-rev902.dtso
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-pinfunc.h"
+
+&pinctrl_hog_misc {
+ fsl,pins = <
+ /* ENET_WOL# -- shared by both PHYs */
+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000090
+
+ /* PG_V_IN_VAR# */
+ MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000
+ /* CSI2_PD_1V8 */
+ MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0
+ /* CSI2_RESET_1V8# */
+ MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0
+
+ /* DIS_USB_DN1 */
+ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0
+ /* DIS_USB_DN2 */
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0
+
+ /* EEPROM_WP_1V8# */
+ MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x100
+ /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0
+ /* GRAPHICS_PRSNT_1V8# */
+ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000
+
+ /* CLK_CCM_CLKO1_3V3 */
+ MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10
+ >;
+};
+
+&pinctrl_pcie0 {
+ fsl,pins = <
+ /* M2_PCIE_RST# */
+ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
+ /* M2_W_DISABLE1_1V8# */
+ MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2
+ /* M2_W_DISABLE2_1V8# */
+ MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2
+ /* CLK_M2_32K768 */
+ MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14
+ /* M2_PCIE_WAKE# */
+ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140
+ /* M2_PCIE_CLKREQ# */
+ MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61
+ >;
+};
+
+&pinctrl_uart4 {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
+ >;
+};
+
+&gpiowifi {
+ status = "disabled";
+};
+
+&uart4 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
index cb28cf1cdd23f..a229670992a48 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
@@ -30,11 +30,8 @@ memory@40000000 {
backlight: backlight {
compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_panel_backlight>;
brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
default-brightness-level = <7>;
- enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
pwms = <&pwm1 0 5000000 0>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
@@ -86,9 +83,6 @@ reg_panel_vcc: regulator-panel-vcc {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "PANEL_VCC";
- /* GPIO flags are ignored, enable-active-high applies. */
- gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
@@ -454,7 +448,9 @@ pcieclk: clk@6a {
};
};
-&i2c2 {
+i2c_display: &i2c2 { };
+
+i2c_feature: &i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 90d7bb8f5619e..42a3216daed44 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1437,7 +1437,7 @@ aips5: bus@30df0000 {
#access-controller-cells = <3>;
ranges = <0x30c00000 0x30c00000 0x400000>;
- spba-bus@30c00000 {
+ spba5: spba-bus@30c00000 {
compatible = "fsl,spba-bus", "simple-bus";
reg = <0x30c00000 0x100000>;
#address-cells = <1>;
--
2.53.0
^ permalink raw reply related
* [PATCH v4 6/6] clk: fsl-sai: Add MCLK generation support
From: Marek Vasut @ 2026-04-06 21:49 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Michael Walle, Brian Masney, Conor Dooley,
Krzysztof Kozlowski, Michael Turquette, Michael Walle,
Rob Herring, Stephen Boyd, devicetree, linux-kernel
In-Reply-To: <20260406215150.176599-1-marex@nabladev.com>
The driver currently supports generating BCLK. There are systems which
require generation of MCLK instead. Register new MCLK clock and handle
clock-cells = <1> to differentiate between BCLK and MCLK. In case of a
legacy system with clock-cells = <0>, the driver behaves as before, i.e.
always returns BCLK.
Note that it is not possible re-use the current SAI audio driver to
generate MCLK and correctly enable and disable the MCLK.
If SAI (audio driver) is used to control the MCLK enablement, then MCLK
clock is not always enabled, and it is not necessarily enabled when the
codec may need the clock to be enabled. There is also no way for the
codec node to specify phandle to clock provider in DT, because the SAI
(audio driver) is not clock provider.
If SAI (clock driver) is used to control the MCLK enablement, then MCLK
clock is enabled when the codec needs the clock enabled, because the
codec is the clock consumer and the SAI (clock driver) is the clock
provider, and the codec driver can request the clock to be enabled when
needed. There is also the usual phandle to clock provider in DT, because
the SAI (clock driver) is clock provider.
Acked-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Brian Masney <bmasney@redhat.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
V2: No change
V3: - Rebase on current next, update mail address
- Update commit message according to clarify the difference between
SAI audio and SAI clock driver
- Pick ancient AB from Michael, although this may be outdated
https://patchwork.kernel.org/project/alsa-devel/patch/20241226162234.40141-4-marex@denx.de/
V4: Use the fsl_sai_clk_register() helper.
---
drivers/clk/clk-fsl-sai.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index 7ec9a4f22735c..386ee5f77a986 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -6,6 +6,7 @@
*/
#include <linux/clk-provider.h>
+#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -15,22 +16,37 @@
#define I2S_CSR 0x00
#define I2S_CR2 0x08
+#define I2S_MCR 0x100
#define CSR_BCE_BIT 28
+#define CSR_TE_BIT 31
#define CR2_BCD BIT(24)
#define CR2_DIV_SHIFT 0
#define CR2_DIV_WIDTH 8
+#define MCR_MOE BIT(30)
struct fsl_sai_clk {
struct clk_divider bclk_div;
+ struct clk_divider mclk_div;
struct clk_gate bclk_gate;
+ struct clk_gate mclk_gate;
struct clk_hw *bclk_hw;
+ struct clk_hw *mclk_hw;
spinlock_t lock;
};
struct fsl_sai_data {
unsigned int offset; /* Register offset */
+ bool have_mclk; /* Have MCLK control */
};
+static struct clk_hw *
+fsl_sai_of_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct fsl_sai_clk *sai_clk = data;
+
+ return clkspec->args[0] ? sai_clk->mclk_hw : sai_clk->bclk_hw;
+}
+
static int fsl_sai_clk_register(struct device *dev, void __iomem *base,
spinlock_t *lock, struct clk_divider *div,
struct clk_gate *gate, struct clk_hw **hw,
@@ -104,15 +120,28 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
if (ret)
return ret;
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
+ if (data->have_mclk) {
+ ret = fsl_sai_clk_register(dev, base, &sai_clk->lock,
+ &sai_clk->mclk_div,
+ &sai_clk->mclk_gate,
+ &sai_clk->mclk_hw,
+ CSR_TE_BIT, MCR_MOE, I2S_MCR,
+ "MCLK");
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(dev, fsl_sai_of_clk_get, sai_clk);
}
static const struct fsl_sai_data fsl_sai_vf610_data = {
.offset = 0,
+ .have_mclk = false,
};
static const struct fsl_sai_data fsl_sai_imx8mq_data = {
.offset = 8,
+ .have_mclk = true,
};
static const struct of_device_id of_fsl_sai_clk_ids[] = {
--
2.53.0
^ permalink raw reply related
* [PATCH v4 5/6] clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
From: Marek Vasut @ 2026-04-06 21:49 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Brian Masney, Conor Dooley, Krzysztof Kozlowski,
Michael Turquette, Michael Walle, Rob Herring, Stephen Boyd,
devicetree, linux-kernel
In-Reply-To: <20260406215150.176599-1-marex@nabladev.com>
Create helper function fsl_sai_clk_register() to set up and register
SAI clock. Rename BCLK specific struct fsl_sai_clk members with bclk_
prefix. Use of_node_full_name(dev->of_node) and clock name to register
uniquely named clock. This is done in preparation for the follow up
patch, which adds MCLK support.
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Brian Masney <bmasney@redhat.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
V4: New patch
---
drivers/clk/clk-fsl-sai.c | 78 ++++++++++++++++++++++++++-------------
1 file changed, 53 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index 2a68e32c3167b..7ec9a4f22735c 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -21,8 +21,9 @@
#define CR2_DIV_WIDTH 8
struct fsl_sai_clk {
- struct clk_divider div;
- struct clk_gate gate;
+ struct clk_divider bclk_div;
+ struct clk_gate bclk_gate;
+ struct clk_hw *bclk_hw;
spinlock_t lock;
};
@@ -30,15 +31,57 @@ struct fsl_sai_data {
unsigned int offset; /* Register offset */
};
+static int fsl_sai_clk_register(struct device *dev, void __iomem *base,
+ spinlock_t *lock, struct clk_divider *div,
+ struct clk_gate *gate, struct clk_hw **hw,
+ const int gate_bit, const int dir_bit,
+ const int div_reg, char *name)
+{
+ const struct fsl_sai_data *data = device_get_match_data(dev);
+ struct clk_parent_data pdata = { .index = 0 };
+ struct clk_hw *chw;
+ char *cname;
+
+ gate->reg = base + data->offset + I2S_CSR;
+ gate->bit_idx = gate_bit;
+ gate->lock = lock;
+
+ div->reg = base + div_reg;
+ div->shift = CR2_DIV_SHIFT;
+ div->width = CR2_DIV_WIDTH;
+ div->lock = lock;
+
+ cname = devm_kasprintf(dev, GFP_KERNEL, "%s.%s",
+ of_node_full_name(dev->of_node), name);
+ if (!cname)
+ return -ENOMEM;
+
+ chw = devm_clk_hw_register_composite_pdata(dev, cname,
+ &pdata, 1, NULL, NULL,
+ &div->hw,
+ &clk_divider_ops,
+ &gate->hw,
+ &clk_gate_ops,
+ CLK_SET_RATE_GATE);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ *hw = chw;
+
+ /* Set clock direction */
+ writel(dir_bit, base + div_reg);
+
+ return 0;
+}
+
static int fsl_sai_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct fsl_sai_data *data = device_get_match_data(dev);
struct fsl_sai_clk *sai_clk;
- struct clk_parent_data pdata = { .index = 0 };
struct clk *clk_bus;
void __iomem *base;
- struct clk_hw *hw;
+ int ret;
sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
if (!sai_clk)
@@ -54,27 +97,12 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
spin_lock_init(&sai_clk->lock);
- sai_clk->gate.reg = base + data->offset + I2S_CSR;
- sai_clk->gate.bit_idx = CSR_BCE_BIT;
- sai_clk->gate.lock = &sai_clk->lock;
-
- sai_clk->div.reg = base + data->offset + I2S_CR2;
- sai_clk->div.shift = CR2_DIV_SHIFT;
- sai_clk->div.width = CR2_DIV_WIDTH;
- sai_clk->div.lock = &sai_clk->lock;
-
- /* set clock direction, we are the BCLK master */
- writel(CR2_BCD, base + data->offset + I2S_CR2);
-
- hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
- &pdata, 1, NULL, NULL,
- &sai_clk->div.hw,
- &clk_divider_ops,
- &sai_clk->gate.hw,
- &clk_gate_ops,
- CLK_SET_RATE_GATE);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
+ ret = fsl_sai_clk_register(dev, base, &sai_clk->lock,
+ &sai_clk->bclk_div, &sai_clk->bclk_gate,
+ &sai_clk->bclk_hw, CSR_BCE_BIT, CR2_BCD,
+ data->offset + I2S_CR2, "BCLK");
+ if (ret)
+ return ret;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}
--
2.53.0
^ permalink raw reply related
* [PATCH v4 4/6] clk: fsl-sai: Sort the headers
From: Marek Vasut @ 2026-04-06 21:49 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Brian Masney, Conor Dooley, Krzysztof Kozlowski,
Michael Turquette, Michael Walle, Rob Herring, Stephen Boyd,
devicetree, linux-kernel
In-Reply-To: <20260406215150.176599-1-marex@nabladev.com>
Sort the headers. No functional change.
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Brian Masney <bmasney@redhat.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
V4: New patch
---
drivers/clk/clk-fsl-sai.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index 336aa8477d0ea..2a68e32c3167b 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -5,12 +5,12 @@
* Copyright 2020 Michael Walle <michael@walle.cc>
*/
-#include <linux/module.h>
-#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/platform_device.h>
#include <linux/slab.h>
#define I2S_CSR 0x00
--
2.53.0
^ permalink raw reply related
* [PATCH v4 3/6] dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
From: Marek Vasut @ 2026-04-06 21:49 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Conor Dooley, Brian Masney, Conor Dooley,
Krzysztof Kozlowski, Michael Turquette, Michael Walle,
Rob Herring, Stephen Boyd, devicetree, linux-kernel
In-Reply-To: <20260406215150.176599-1-marex@nabladev.com>
The driver now supports generation of both BCLK and MCLK, document
support for #clock-cells = <0> for legacy case and #clock-cells = <1>
for the new case which can differentiate between BCLK and MCLK.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Brian Masney <bmasney@redhat.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
V2: Update commit message, align it with the bindings one
V3: - Rebase on current next, update mail address
- Pick ancient AB from Conor, although this may be outdated
https://patchwork.kernel.org/project/alsa-devel/patch/20241226162234.40141-3-marex@denx.de/
V4: No change
---
Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
index 90799b3b505ee..041a63fa2d2b0 100644
--- a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
@@ -10,7 +10,7 @@ maintainers:
- Michael Walle <michael@walle.cc>
description: |
- It is possible to use the BCLK pin of a SAI module as a generic
+ It is possible to use the BCLK or MCLK pin of a SAI module as a generic
clock output. Some SoC are very constrained in their pin multiplexer
configuration. E.g. pins can only be changed in groups. For example, on
the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
@@ -47,7 +47,7 @@ properties:
- const: mclk1
'#clock-cells':
- const: 0
+ maximum: 1
allOf:
- if:
--
2.53.0
^ permalink raw reply related
* [PATCH v4 2/6] clk: fsl-sai: Add i.MX8M support with 8 byte register offset
From: Marek Vasut @ 2026-04-06 21:49 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Brian Masney, Peng Fan, Conor Dooley,
Krzysztof Kozlowski, Michael Turquette, Michael Walle,
Rob Herring, Stephen Boyd, devicetree, linux-kernel
In-Reply-To: <20260406215150.176599-1-marex@nabladev.com>
The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers
shifted by +8 bytes and requires additional bus clock. Add support for
the i.MX8M variant of the IP with this register shift and additional
clock.
Reviewed-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Brian Masney <bmasney@redhat.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
V2: Update commit message, align it with the bindings one
V3: - Rebase on current next, update mail address
- Pick ancient RB from Peng, although this may be outdated
https://patchwork.kernel.org/project/alsa-devel/patch/20241226162234.40141-2-marex@denx.de/
- Optionally enable "bus" clock, which are needed on MX8M to operate
register file
V4: Add RB from Brian
---
drivers/clk/Kconfig | 2 +-
drivers/clk/clk-fsl-sai.c | 27 +++++++++++++++++++++++----
2 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index cc8743b11bb1f..9f7f391a5615a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -255,7 +255,7 @@ config COMMON_CLK_FSL_FLEXSPI
config COMMON_CLK_FSL_SAI
bool "Clock driver for BCLK of Freescale SAI cores"
- depends on ARCH_LAYERSCAPE || COMPILE_TEST
+ depends on ARCH_LAYERSCAPE || ARCH_MXC || COMPILE_TEST
help
This driver supports the Freescale SAI (Synchronous Audio Interface)
to be used as a generic clock output. Some SoCs have restrictions
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index cba45e07562da..336aa8477d0ea 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -26,11 +26,17 @@ struct fsl_sai_clk {
spinlock_t lock;
};
+struct fsl_sai_data {
+ unsigned int offset; /* Register offset */
+};
+
static int fsl_sai_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ const struct fsl_sai_data *data = device_get_match_data(dev);
struct fsl_sai_clk *sai_clk;
struct clk_parent_data pdata = { .index = 0 };
+ struct clk *clk_bus;
void __iomem *base;
struct clk_hw *hw;
@@ -42,19 +48,23 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
+ clk_bus = devm_clk_get_optional_enabled(dev, "bus");
+ if (IS_ERR(clk_bus))
+ return PTR_ERR(clk_bus);
+
spin_lock_init(&sai_clk->lock);
- sai_clk->gate.reg = base + I2S_CSR;
+ sai_clk->gate.reg = base + data->offset + I2S_CSR;
sai_clk->gate.bit_idx = CSR_BCE_BIT;
sai_clk->gate.lock = &sai_clk->lock;
- sai_clk->div.reg = base + I2S_CR2;
+ sai_clk->div.reg = base + data->offset + I2S_CR2;
sai_clk->div.shift = CR2_DIV_SHIFT;
sai_clk->div.width = CR2_DIV_WIDTH;
sai_clk->div.lock = &sai_clk->lock;
/* set clock direction, we are the BCLK master */
- writel(CR2_BCD, base + I2S_CR2);
+ writel(CR2_BCD, base + data->offset + I2S_CR2);
hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
&pdata, 1, NULL, NULL,
@@ -69,8 +79,17 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}
+static const struct fsl_sai_data fsl_sai_vf610_data = {
+ .offset = 0,
+};
+
+static const struct fsl_sai_data fsl_sai_imx8mq_data = {
+ .offset = 8,
+};
+
static const struct of_device_id of_fsl_sai_clk_ids[] = {
- { .compatible = "fsl,vf610-sai-clock" },
+ { .compatible = "fsl,vf610-sai-clock", .data = &fsl_sai_vf610_data },
+ { .compatible = "fsl,imx8mq-sai-clock", .data = &fsl_sai_imx8mq_data },
{ }
};
MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);
--
2.53.0
^ permalink raw reply related
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