* [PATCH v5 0/4] AST2700-A2 interrupt controller hierarchy and route support
From: Ryan Chen @ 2026-04-07 3:08 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Thomas Gleixner, Thomas Gleixner
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-aspeed,
linux-riscv, Ryan Chen
The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2)
prior to mass production.
A0 laid the ground-work with a split controller design (INTC0 and
INTC1) used for early development and bring-up. The interrupt
architecture was substantially reworked in the A1 to introduce an
explicit routing model and clearer hierarchy, though the split
controllers remained. The A1 interrupt architecture is unchanged in A2.
A2 is the production design. A0 and A1 are pre-production silicon and
are no longer intended for deployment outside of ASPEED.
The existing binding and driver were written against A0 prior to the A1
rework. The A0 design directly wired INTC1 instances to INTC0, and
INTC0 to the GIC of the Primary Service Processor (PSP, a Cortex-A35).
The A0 binding and driver therefore do not account for the alternative
destinations of the Secondary and Tertiary Service Processors (SSP,
TSP) and BootMCU, or the necessary route selection logic present in the
production design.
With the above context, this series replaces the existing binding and
driver.
It is not necessary for projects to maintain support for A0 due to its
pre-production nature, and between Linux, U-Boot and Zephyr there are
no upstream devicetree users of the current binding.
The new binding uses localised interrupt numbers and models the
hardware connectivity between interrupt controllers using the
aspeed,interrupt-ranges property. It is introduced in a new file before
the existing binding is removed in order to keep the diff readable.
The INTC0 driver creates a hierarchical irqdomain under the selected
upstream interrupt controller and implements route resolution logic.
INTC1 driver instances defer route selection to INTC0 and expose a
linear interrupt namespace to their parent.
A brief history of related submissions
--------------------------------------
Some modifications to the existing binding were sent to the lists in
the past. Due to process choices the revisions were difficult to track.
They are listed below.
The approaches took several forms but ended in the minor adjustment in
v6 being applied. This enabled use of the A1 design but requires
assumptions about platform route configuration defined in firmware.
These assumptions are removed by this current series.
* [PATCH] dt-bindings: interrupt-controller: aspeed: Refine AST2700 binding description and example
https://lore.kernel.org/all/20250714071753.2653620-1-ryan_chen@aspeedtech.com/
* [PATCH v2] dt-bindings: interrupt-controller: aspeed: Add parent node compatibles and refine documentation
https://lore.kernel.org/all/20250715024258.2304665-1-ryan_chen@aspeedtech.com/
* [PATCH v3 0/2] irqchip: aspeed: Add AST2700 INTC debugfs support and yaml update
https://lore.kernel.org/all/20250722095156.1672873-1-ryan_chen@aspeedtech.com/
* [PATCH v4 0/2] irqchip/ast2700-intc: Add AST2700 INTC debugfs support and yaml update
https://lore.kernel.org/all/20250812100830.145578-1-ryan_chen@aspeedtech.com/
* [PATCH v5 0/3] AST2700 interrupt controller hierarchy support
https://lore.kernel.org/all/20251022065507.1152071-1-ryan_chen@aspeedtech.com/
* [PATCH v6 0/1] Update correct AST2700 interrupt controller binding
https://lore.kernel.org/all/20251030060155.2342604-1-ryan_chen@aspeedtech.com/
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
Changes in v5:
- 2/4 reduce unnecessary line breaks.
- 2/4, 3/4 fix enable CONFIG_PROVE_LOCKING irq lock inversion dependency
detected.
- Link to v4: https://lore.kernel.org/r/20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com
Changes in v4:
- 3/4 fix warning: the frame size of 1296 bytes is larger than 1280 bytes
- Link to v3: https://lore.kernel.org/r/20260326-irqchip-v3-0-366739f57acf@aspeedtech.com
Changes in v3:
- 1/4 Squash patch 5/5 and 1/5.
- 1/4 modify wrap lines at 80 char.
- 1/4 modify maintainers name and email.
- 1/4 modify typo Sevice-> Service
- Link to v2: https://lore.kernel.org/r/20260306-irqchip-v2-0-f8512c09be63@aspeedtech.com
Changes in v2:
- Change suject to "AST2700-A2 interrupt controller hierarchy and route
support".
- Describe timeline for (pre-)production design evolution and
binding development to support the break in compatibility.
- fix "make dt_binding_check" compatible string consistance with
example.
- Split KUnit coverage out of the main driver patch.
- Link to v1: https://lore.kernel.org/r/20260205-irqchip-v1-0-b0310e06c087@aspeedtech.com
---
Ryan Chen (4):
dt-bindings: interrupt-controller: Describe AST2700-A2 hardware instead of A0
irqchip/ast2700-intc: Add AST2700-A2 support
irqchip/ast2700-intc: Add KUnit tests for route resolution
irqchip/aspeed-intc: Remove AST2700-A0 support
.../interrupt-controller/aspeed,ast2700-intc.yaml | 90 ----
.../aspeed,ast2700-interrupt.yaml | 188 +++++++
drivers/irqchip/.kunitconfig | 5 +
drivers/irqchip/Kconfig | 23 +
drivers/irqchip/Makefile | 3 +-
drivers/irqchip/irq-aspeed-intc.c | 139 -----
drivers/irqchip/irq-ast2700-intc0-test.c | 473 +++++++++++++++++
drivers/irqchip/irq-ast2700-intc0.c | 582 +++++++++++++++++++++
drivers/irqchip/irq-ast2700-intc1.c | 280 ++++++++++
drivers/irqchip/irq-ast2700.c | 107 ++++
drivers/irqchip/irq-ast2700.h | 48 ++
11 files changed, 1708 insertions(+), 230 deletions(-)
---
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
change-id: 20260205-irqchip-7eaef3674de9
Best regards,
--
Ryan Chen <ryan_chen@aspeedtech.com>
^ permalink raw reply
* [PATCH v3] arm64: dts: imx952: Describe Mali G310 GPU
From: Guangliu Ding @ 2026-04-07 3:15 UTC (permalink / raw)
To: Daniel Almeida, Alice Ryhl, Boris Brezillon, Steven Price,
Liviu Dudau, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
Guangliu Ding
Support Mali G310 GPU on i.MX952 board. Describe this GPU in the DT.
Include dummy GPU voltage regulator and OPP tables.
A hardware GPU auto clock‑gating mechanism has been introduced,
enabling GPUMIX to automatically manage the GPU clock. This improves
overall response time.
Signed-off-by: Guangliu Ding <guangliu.ding@nxp.com>
---
This series enable Mali G310 GPU support on i.MX952 boards, the same GPU
IP as the instance on i.MX95 boards.
---
Changes in v3:
- Follow the order of interrupts/interrupt-names in arm,mali-valhall-csf.yaml.
- Drop dt-bindings change in arm,mali-valhall-csf.yaml.
- Replace "nxp,imx952-mali" with "nxp,imx95-mali" in compatible.
- Link to v2: https://patch.msgid.link/20260401-master-v2-0-20d3fbcd19d6@nxp.com
Changes in v2:
- Improve patch description, adding more GPU information.
- Remove Reviewed-by tag.
- Link to v1: https://patch.msgid.link/20260331-master-v1-0-65c8e318d462@nxp.com
---
arch/arm64/boot/dts/freescale/imx952.dtsi | 36 +++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi
index 91fe4916ac04..ced09e7a1dc5 100644
--- a/arch/arm64/boot/dts/freescale/imx952.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx952.dtsi
@@ -318,6 +318,28 @@ usbphynop2: usbphynop2 {
clock-names = "main_clk";
};
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-hz-real = /bits/ 64 <500000000>;
+ opp-microvolt = <920000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-hz-real = /bits/ 64 <800000000>;
+ opp-microvolt = <920000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-hz-real = /bits/ 64 <1000000000>;
+ opp-microvolt = <920000>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -1262,5 +1284,19 @@ usbmisc2: usbmisc@4c200200 {
reg = <0x0 0x4c200200 0x0 0x200>,
<0x0 0x4c010014 0x0 0x4>;
};
+
+ gpu: gpu@4d900000 {
+ compatible = "nxp,imx95-mali", "arm,mali-valhall-csf";
+ reg = <0 0x4d900000 0 0x480000>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = <&scmi_clk IMX952_CLK_GPU>;
+ clock-names = "core";
+ power-domains = <&scmi_devpd IMX952_PD_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
+ dynamic-power-coefficient = <1013>;
+ };
};
};
---
base-commit: 0138af2472dfdef0d56fc4697416eaa0ff2589bd
change-id: 20260331-master-7ec7ff0fe1b2
Best regards,
--
Guangliu Ding <guangliu.ding@nxp.com>
^ permalink raw reply related
* Re: [PATCH 2/2] drm/panel: simple: Add EDT ETML1010G0DKA panel
From: Frank Li @ 2026-04-07 2:50 UTC (permalink / raw)
To: Dominik Haller, Neil Armstrong
Cc: robh+dt@kernel.org, sam@ravnborg.org, thierry.reding@gmail.com,
krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org, upstream@phytec.de
In-Reply-To: <ba13246c-3838-4993-12ef-420d82730b28@phytec.de>
On Mon, Feb 06, 2023 at 02:20:31PM +0000, Dominik Haller wrote:
> Hello,
Neil Armstrong:
It is quite old. Any reason why not pick this patch?
Frank
>
> ping here, this one got forgotten.
> It still applies on drm-misc-next and v6.2-rc7
>
>
> On 18.08.22 14:45, Dominik Haller wrote:
> > Add support for the EDT ETML1010G0DKA 10.1" 1280x800 LVDS panel.
> >
> > Signed-off-by: Dominik Haller <d.haller@phytec.de>
> > ---
> > drivers/gpu/drm/panel/panel-simple.c | 29 ++++++++++++++++++++++++++++
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > index f9e1f85daef7..9314db24ab51 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -1779,6 +1779,32 @@ static const struct panel_desc edt_etml0700y5dha = {
> > .connector_type = DRM_MODE_CONNECTOR_LVDS,
> > };
> >
> > +static const struct drm_display_mode edt_etml1010g0dka_mode = {
> > + .clock = 70000,
> > + .hdisplay = 1280,
> > + .hsync_start = 1280 + 100,
> > + .hsync_end = 1280 + 100 + 19,
> > + .htotal = 1280 + 100 + 19 + 41,
> > + .vdisplay = 800,
> > + .vsync_start = 800 + 4,
> > + .vsync_end = 800 + 4 + 4,
> > + .vtotal = 800 + 4 + 4 + 15,
> > + .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
> > +};
> > +
> > +static const struct panel_desc edt_etml1010g0dka = {
> > + .modes = &edt_etml1010g0dka_mode,
> > + .num_modes = 1,
> > + .bpc = 8,
> > + .size = {
> > + .width = 216,
> > + .height = 135,
> > + },
> > + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
> > + .bus_flags = DRM_BUS_FLAG_DE_HIGH,
> > + .connector_type = DRM_MODE_CONNECTOR_LVDS,
> > +};
> > +
> > static const struct drm_display_mode edt_etmv570g2dhu_mode = {
> > .clock = 25175,
> > .hdisplay = 640,
> > @@ -4057,6 +4083,9 @@ static const struct of_device_id platform_of_match[] = {
> > }, {
> > .compatible = "edt,etml0700y5dha",
> > .data = &edt_etml0700y5dha,
> > + }, {
> > + .compatible = "edt,etml1010g0dka",
> > + .data = &edt_etml1010g0dka,
> > }, {
> > .compatible = "edt,etmv570g2dhu",
> > .data = &edt_etmv570g2dhu,
>
>
> --
> PHYTEC Messtechnik GmbH | Barcelona-Allee 1 | 55129 Mainz, Germany
>
> Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber |
> Handelsregister Mainz HRB 4656 | Finanzamt Mainz-Mitte | St.Nr.
> 266500608, DE 149059855
>
^ permalink raw reply
* Re: [PATCH v4 6/7] remoteproc: qcom: pas: Add late attach support for subsystems
From: Jingyi Wang @ 2026-04-07 2:44 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Mathieu Poirier, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Luca Weiss, Bartosz Golaszewski,
Konrad Dybcio, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Gokul Krishna Krishnakumar
In-Reply-To: <adPI2w5tVGCdo_x3@baldur>
On 4/6/2026 10:59 PM, Bjorn Andersson wrote:
> On Tue, Mar 10, 2026 at 03:03:22AM -0700, Jingyi Wang wrote:
>> From: Gokul Krishna Krishnakumar <gokul.krishnakumar@oss.qualcomm.com>
>>
>> Subsystems can be brought out of reset by entities such as bootloaders.
>> As the irq enablement could be later than subsystem bring up, the state
>> of subsystem should be checked by reading SMP2P bits and performing ping
>> test.
>>
>> A new qcom_pas_attach() function is introduced. if a crash state is
>> detected for the subsystem, rproc_report_crash() is called. If the
>> subsystem is ready either at the first check or within a 5-second timeout
>> and the ping is successful, it will be marked as "attached". The ready
>> state could be set by either ready interrupt or handover interrupt.
>>
>
> The whole use case of early booting SoCCP is to get the charger and USB
> Type-C running early - so that charging and USB Type-C works in UEFI.
>
> If SMP2P indicates that it was booted, but it's still not there...then
> there's no reason to wait another 5 seconds - it's not there.
>
>> If "early_boot" is set by kernel but "subsys_booted" is not completed
>> within the timeout, It could be the early boot feature is not supported
>> by other entities. In this case, the state will be marked as RPROC_OFFLINE
>> so that the PAS driver can load the firmware and start the remoteproc. As
>> the running state is set once attach function is called, the watchdog or
>> fatal interrupt received can be handled correctly.
>>
>> Signed-off-by: Gokul Krishna Krishnakumar <gokul.krishnakumar@oss.qualcomm.com>
>> Co-developed-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> [..]
>> diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
> [..]
>> +static int qcom_pas_attach(struct rproc *rproc)
> [..]
>> + if (!ret)
>> + ret = irq_get_irqchip_state(pas->q6v5.ready_irq,
>> + IRQCHIP_STATE_LINE_LEVEL, &ready_state);
>> +
>> + /*
>> + * smp2p allocate irq entry can be delayed, irq_get_irqchip_state will get -ENODEV,
>
> This on the other hand, sounds like a bug in the smp2p driver. If we can
> acquire the interrupt without getting EPROBE_DEFER, then we should not
> get -ENODEV when reading the irq state.
>
>> + * the 5 seconds timeout is set to wait for this, after the entry is allocated, smp2p
>> + * will call the qcom_smp2p_intr and complete the timeout in the ISR.
>
> If this indeed is the problem you're working around with the 5 second
> delay - then stop. Fix the issue instead!
>
> Also, this comment conflicts with the reasoning for the ping and the 5
> second thing in the commit message.
>
> Regards,
> Bjorn
>
It is a design in downstream code to avoid the irq is not received when
we check the irq state, but indeed it seems like a redundant design and
I didn't see the delay in the test for the soccp attach. So we will remove
this 5 seconds wait in next series.
Thanks,
Jingyi
>> + */
>> + if (unlikely(ret == -ENODEV) || unlikely(!ready_state)) {
>> + ret = wait_for_completion_timeout(&pas->q6v5.subsys_booted,
>> + msecs_to_jiffies(EARLY_ATTACH_TIMEOUT_MS));
>> +
>> + /*
>> + * The bootloader may not support early boot, mark the state as
>> + * RPROC_OFFLINE so that the PAS driver can load the firmware and
>> + * start the remoteproc.
>> + */
>> + if (!ret) {
>> + dev_err(pas->dev, "Timeout on waiting for subsystem interrupt\n");
>> + pas->rproc->state = RPROC_OFFLINE;
>> + ret = -ETIMEDOUT;
>> + goto disable_running;
>> + }
>> +
>> + /* Only ping the subsystem if ready_state is set */
>> + ret = irq_get_irqchip_state(pas->q6v5.ready_irq,
>> + IRQCHIP_STATE_LINE_LEVEL, &ready_state);
>> +
>> + if (ret)
>> + goto disable_running;
>> +
>> + if (!ready_state) {
>> + ret = -EINVAL;
>> + goto disable_running;
>> + }
>> + }
>> +
>> + ret = qcom_q6v5_ping_subsystem(&pas->q6v5);
>> +
>> + if (ret) {
>> + dev_err(pas->dev, "Failed to ping subsystem, assuming device crashed\n");
>> + rproc_report_crash(rproc, RPROC_FATAL_ERROR);
>> + goto disable_running;
>> + }
>> +
>> + pas->q6v5.handover_issued = true;
>> +
>> + return 0;
>> +
>> +disable_running:
>> + pas->q6v5.running = false;
>> +
>> + return ret;
>> +}
>> +
>> static const struct rproc_ops qcom_pas_ops = {
>> .unprepare = qcom_pas_unprepare,
>> .start = qcom_pas_start,
>> @@ -518,6 +603,7 @@ static const struct rproc_ops qcom_pas_ops = {
>> .parse_fw = qcom_pas_parse_firmware,
>> .load = qcom_pas_load,
>> .panic = qcom_pas_panic,
>> + .attach = qcom_pas_attach,
>> };
>>
>> static const struct rproc_ops qcom_pas_minidump_ops = {
>> @@ -823,7 +909,7 @@ static int qcom_pas_probe(struct platform_device *pdev)
>> pas->proxy_pd_count = ret;
>>
>> ret = qcom_q6v5_init(&pas->q6v5, pdev, rproc, desc->crash_reason_smem,
>> - desc->load_state, qcom_pas_handover);
>> + desc->load_state, desc->early_boot, qcom_pas_handover);
>> if (ret)
>> goto detach_proxy_pds;
>>
>> @@ -855,6 +941,15 @@ static int qcom_pas_probe(struct platform_device *pdev)
>>
>> pas->pas_ctx->use_tzmem = rproc->has_iommu;
>> pas->dtb_pas_ctx->use_tzmem = rproc->has_iommu;
>> +
>> + if (pas->q6v5.early_boot) {
>> + ret = qcom_q6v5_ping_subsystem_init(&pas->q6v5, pdev);
>> + if (ret)
>> + dev_warn(&pdev->dev, "Falling back to firmware load\n");
>> + else
>> + pas->rproc->state = RPROC_DETACHED;
>> + }
>> +
>> ret = rproc_add(rproc);
>> if (ret)
>> goto remove_ssr_sysmon;
>> diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
>> index c27200159a88..859141589ed7 100644
>> --- a/drivers/remoteproc/qcom_q6v5_wcss.c
>> +++ b/drivers/remoteproc/qcom_q6v5_wcss.c
>> @@ -1011,7 +1011,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
>> if (ret)
>> return ret;
>>
>> - ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, NULL);
>> + ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, false, NULL);
>> if (ret)
>> return ret;
>>
>>
>> --
>> 2.25.1
>>
^ permalink raw reply
* [PATCH v2 0/4] riscv: Add PCIe support for UltraRISC DP1000 SoC
From: Jia Wang @ 2026-04-07 2:40 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han,
Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley
Cc: linux-riscv, linux-kernel, linux-pci, devicetree, Jia Wang
This patch series adds PCIe controller support for the UltraRISC DP1000 SoC.
The DP1000 is an 8-core 64-bit RISC-V SoC based on UltraRISC CP100 cores,
supporting RV64GCBHX ISA with Hardware Virtualization and RISC-V H(v1.0)
Extension.
The PCIe controller is based on Synopsys DesignWare PCIe IP.
This series adds:
- Patch 1 adds the basic SoC family Kconfig support for UltraRISC platforms.
- Patch 2 adds the MAINTAINERS entry for the new driver.
- Patch 3 adds the device tree bindings documentation for the PCIe controller.
- Patch 4 introduces the PCIe host controller driver.
The patches have been tested on UltraRISC DP1000 development board with
various PCIe devices including NVMe SSDs and network cards, verifying
link establishment, enumeration, and basic data transfer.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
Changes in v2:
- Rebased onto v7.0-rc7.
- Patch 1:
* Removed unnecessary 'depends' line.
* Fixed help text indentation.
- Patch 2:
* No changes.
- Patch 3:
* Updated $ref to use 'snps,dw-pcie.yaml' as the base schema.
* Add interrupts/interrupt-names (MSI + INTx).
* Drop properties covered by generic DWC/PCI host bindings;
update example accordingly.
* Verified the schema passes 'make dt_binding_check' and 'yamllint'.
- Patch 4:
* Update commit message.
* Kconfig: switch PCIE_ULTRARISC to tristate; simplify help text.
* Convert suspend/resume to dev_pm_ops and called
`dw_pcie_suspend_noirq()` / `dw_pcie_resume_noirq()`.
* Use FIELD_MODIFY(); adjust DWC header macros/comments.
* Added empty `.pme_turn_off()` callback for DP1000 limitation.
* Renamed link callback to `start_link`.
* Switched to `module_platform_driver()`.
* Formatting cleanups (headers order, spacing, variable naming,
function names)
- Link to v1: https://patch.msgid.link/20260316-ultrarisc-pcie-v1-0-ef2946ede698@ultrarisc.com
---
Jia Wang (3):
riscv: add UltraRISC SoC family Kconfig support
MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding
dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller
Xincheng Zhang (1):
PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver
.../bindings/pci/ultrarisc,dp1000-pcie.yaml | 103 +++++++++++
MAINTAINERS | 8 +
arch/riscv/Kconfig.socs | 9 +
drivers/pci/controller/dwc/Kconfig | 12 ++
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-designware.h | 22 +++
drivers/pci/controller/dwc/pcie-ultrarisc.c | 188 +++++++++++++++++++++
7 files changed, 343 insertions(+)
---
base-commit: bfe62a454542cfad3379f6ef5680b125f41e20f4
change-id: 20260310-ultrarisc-pcie-494998763399
Best regards,
--
Jia Wang <wangjia@ultrarisc.com>
^ permalink raw reply
* [PATCH v2 2/4] MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding
From: Jia Wang @ 2026-04-07 2:40 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han,
Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley
Cc: linux-riscv, linux-kernel, linux-pci, devicetree, Jia Wang
In-Reply-To: <20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>
Add a MAINTAINERS entry for the UltraRISC DP1000 PCIe host driver and its
DT binding.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c3fe46d7c4bc..c8159670a14d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20582,6 +20582,14 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
F: drivers/pci/controller/plda/pcie-starfive.c
+PCIE DRIVER FOR ULTRARISC DP1000
+M: Xincheng Zhang <zhangxincheng@ultrarisc.com>
+M: Jia Wang <wangjia@ultrarisc.com>
+L: linux-pci@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
+F: drivers/pci/controller/dwc/pcie-ultrarisc.c
+
PCIE ENDPOINT DRIVER FOR QUALCOMM
M: Manivannan Sadhasivam <mani@kernel.org>
L: linux-pci@vger.kernel.org
--
2.34.1
^ permalink raw reply related
* [PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller
From: Jia Wang @ 2026-04-07 2:40 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han,
Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley
Cc: linux-riscv, linux-kernel, linux-pci, devicetree, Jia Wang
In-Reply-To: <20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>
Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
.../bindings/pci/ultrarisc,dp1000-pcie.yaml | 103 +++++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
new file mode 100644
index 000000000000..d0517130e127
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UltraRISC DP1000 PCIe Host Controller
+
+description: |
+ UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
+ This binding describes the UltraRISC specific extensions to the base
+ DesignWare PCIe binding.
+
+maintainers:
+ - Xincheng Zhang <zhangxincheng@ultrarisc.com>
+ - Jia Wang <wangjia@ultrarisc.com>
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+properties:
+ compatible:
+ const: ultrarisc,dp1000-pcie
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers.
+ - description: PCIe configuration space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: config
+
+ num-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [4, 16]
+ description: Number of lanes to use.
+
+ max-link-speed:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ const: 4
+ description: Maximum PCIe link speed supported.
+
+ interrupts:
+ description: List of interrupt specifiers used by the controller
+ items:
+ - description: MSI interrupt
+ - description: Legacy INTA interrupt
+ - description: Legacy INTB interrupt
+ - description: Legacy INTC interrupt
+ - description: Legacy INTD interrupt
+
+ interrupt-names:
+ items:
+ - const: msi
+ - const: inta
+ - const: intb
+ - const: intc
+ - const: intd
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie_x16: pcie@21000000 {
+ compatible = "ultrarisc,dp1000-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ reg = <0x0 0x21000000 0x0 0x01000000>,
+ <0x0 0x4fff0000 0x0 0x00010000>;
+ reg-names = "dbi", "config";
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ num-lanes = <16>;
+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>,
+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>,
+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>;
+
+ max-link-speed = <4>;
+ interrupt-parent = <&plic>;
+ interrupts = <43>, <44>, <45>, <46>, <47>;
+ interrupt-names = "msi", "inta", "intb", "intc", "intd";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,
+ <0x0 0x0 0x0 0x2 &plic 45>,
+ <0x0 0x0 0x0 0x3 &plic 46>,
+ <0x0 0x0 0x0 0x4 &plic 47>;
+ };
+ };
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support
From: Jia Wang @ 2026-04-07 2:40 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han,
Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley
Cc: linux-riscv, linux-kernel, linux-pci, devicetree, Jia Wang
In-Reply-To: <20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>
The first SoC in the UltraRISC series is UR-DP1000, containing octa
UltraRISC C100 cores.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
arch/riscv/Kconfig.socs | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index d621b85dd63b..98708569ec6a 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -84,6 +84,15 @@ config ARCH_THEAD
help
This enables support for the RISC-V based T-HEAD SoCs.
+config ARCH_ULTRARISC
+ bool "UltraRISC RISC-V SoCs"
+ help
+ This enables support for UltraRISC SoC platform hardware,
+ including boards based on the UR-DP1000.
+ UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
+ the RV64GCBHX ISA. It supports Hardware Virtualization
+ and RISC-V RV64 ISA H(v1.0) Extension.
+
config ARCH_VIRT
bool "QEMU Virt Machine"
select POWER_RESET
--
2.34.1
^ permalink raw reply related
* [PATCH v2 4/4] PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver
From: Jia Wang @ 2026-04-07 2:40 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han,
Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley
Cc: linux-riscv, linux-kernel, linux-pci, devicetree, Jia Wang
In-Reply-To: <20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>
From: Xincheng Zhang <zhangxincheng@ultrarisc.com>
Add DP1000 SoC PCIe Root Complex driver.
Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
drivers/pci/controller/dwc/Kconfig | 12 ++
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-designware.h | 22 ++++
drivers/pci/controller/dwc/pcie-ultrarisc.c | 188 +++++++++++++++++++++++++++
4 files changed, 223 insertions(+)
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index d0aa031397fa..06f7d98259cd 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -548,4 +548,16 @@ config PCIE_VISCONTI_HOST
Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
This driver supports TMPV7708 SoC.
+config PCIE_ULTRARISC
+ tristate "UltraRISC PCIe host controller"
+ depends on ARCH_ULTRARISC || COMPILE_TEST
+ select PCIE_DW_HOST
+ select PCI_MSI
+ default y if ARCH_ULTRARISC
+ help
+ Enables support for the PCIe controller in the UltraRISC SoC.
+ This driver supports UR-DP1000 SoC.
+ By default, this symbol is enabled when ARCH_ULTRARISC is active,
+ requiring no further configuration on that platform.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 67ba59c02038..884c46b78e01 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
+obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ae6389dd9caa..88dcb0e7943a 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -69,6 +69,8 @@
/* Synopsys-specific PCIe configuration registers */
#define PCIE_PORT_FORCE 0x708
+/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */
+#define PORT_LINK_NUM_MASK GENMASK(7, 0)
#define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23)
#define PCIE_PORT_AFR 0x70C
@@ -96,6 +98,26 @@
#define PCIE_PORT_LANE_SKEW 0x714
#define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0)
+/*
+ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number
+ * Register.
+ * This register holds the ack frequency, latency, replay, fast link
+ * scaling timers, and max function number values.
+ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor.
+ * 0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us).
+ * When the LTSSM is in Config or L12 Entry State, 1ms
+ * timer is 2us, 2ms timer is 4us and 3ms timer is 6us.
+ * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us)
+ * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)
+ * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)
+ */
+#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718
+#define PORT_FLT_SF_MASK GENMASK(30, 29)
+#define PORT_FLT_SF_VAL_1024 0x0
+#define PORT_FLT_SF_VAL_256 0x1
+#define PORT_FLT_SF_VAL_64 0x2
+#define PORT_FLT_SF_VAL_16 0x3
+
#define PCIE_PORT_DEBUG0 0x728
#define PORT_LOGIC_LTSSM_STATE_MASK 0x3f
#define PORT_LOGIC_LTSSM_STATE_L0 0x11
diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
new file mode 100644
index 000000000000..0da37efa8680
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DWC PCIe RC driver for UltraRISC DP1000 SoC
+ *
+ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#include "pcie-designware.h"
+
+#define PCIE_CUS_CORE 0x400000
+
+#define LTSSM_ENABLE BIT(7)
+#define FAST_LINK_MODE BIT(12)
+#define HOLD_PHY_RST BIT(14)
+#define L1SUB_DISABLE BIT(15)
+
+struct ultrarisc_pcie {
+ struct dw_pcie *pci;
+ u32 irq_mask[MAX_MSI_CTRLS];
+};
+
+static struct pci_ops ultrarisc_pci_ops = {
+ .map_bus = dw_pcie_own_conf_map_bus,
+ .read = pci_generic_config_read32,
+ .write = pci_generic_config_write32,
+};
+
+static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)
+{
+ struct pci_host_bridge *bridge = pp->bridge;
+
+ bridge->ops = &ultrarisc_pci_ops;
+
+ return 0;
+}
+
+static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp)
+{
+ /*
+ * DP1000 does not support sending PME_Turn_Off from the RC.
+ * Keep this callback empty to skip the generic MSG TLP path.
+ */
+}
+
+static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = {
+ .init = ultrarisc_pcie_host_init,
+ .pme_turn_off = ultrarisc_pcie_pme_turn_off,
+};
+
+static int ultrarisc_pcie_start_link(struct dw_pcie *pci)
+{
+ u32 val;
+ u8 cap_exp;
+
+ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
+ val &= ~FAST_LINK_MODE;
+ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
+
+ val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);
+ FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64);
+ dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);
+
+ cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);
+ FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT);
+ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);
+
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
+ FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0);
+ dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
+
+ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);
+ FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val, 0x6);
+ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val);
+
+ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
+ val &= ~(HOLD_PHY_RST | L1SUB_DISABLE);
+ val |= LTSSM_ENABLE;
+ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
+
+ return 0;
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+ .start_link = ultrarisc_pcie_start_link,
+};
+
+static int ultrarisc_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ultrarisc_pcie *pcie;
+ struct dw_pcie *pci;
+ struct dw_pcie_rp *pp;
+ int ret;
+
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci)
+ return -ENOMEM;
+
+ pci->dev = dev;
+ pci->ops = &dw_pcie_ops;
+
+ /* Set a default value suitable for at most 16 in and 16 out windows */
+ pci->atu_size = SZ_8K;
+
+ pcie->pci = pci;
+
+ pp = &pci->pp;
+
+ platform_set_drvdata(pdev, pcie);
+
+ pp->irq = platform_get_irq(pdev, 1);
+ if (pp->irq < 0)
+ return pp->irq;
+
+ pp->num_vectors = MAX_MSI_IRQS;
+ /* No L2/L3 Ready indication is available on this platform. */
+ pp->skip_l23_ready = true;
+ pp->ops = &ultrarisc_pcie_host_ops;
+
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(dev, "Failed to initialize host\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ultrarisc_pcie_suspend_noirq(struct device *dev)
+{
+ struct ultrarisc_pcie *pcie = dev_get_drvdata(dev);
+ struct dw_pcie *pci = pcie->pci;
+
+ return dw_pcie_suspend_noirq(pci);
+}
+
+static int ultrarisc_pcie_resume_noirq(struct device *dev)
+{
+ struct ultrarisc_pcie *pcie = dev_get_drvdata(dev);
+ struct dw_pcie *pci = pcie->pci;
+
+ return dw_pcie_resume_noirq(pci);
+}
+
+static const struct dev_pm_ops ultrarisc_pcie_pm_ops = {
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq,
+ ultrarisc_pcie_resume_noirq)
+};
+
+static const struct of_device_id ultrarisc_pcie_of_match[] = {
+ {
+ .compatible = "ultrarisc,dp1000-pcie",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match);
+
+static struct platform_driver ultrarisc_pcie_driver = {
+ .driver = {
+ .name = "ultrarisc-pcie",
+ .of_match_table = ultrarisc_pcie_of_match,
+ .suppress_bind_attrs = true,
+ .pm = &ultrarisc_pcie_pm_ops,
+ },
+ .probe = ultrarisc_pcie_probe,
+};
+module_platform_driver(ultrarisc_pcie_driver);
+
+MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v4 5/7] remoteproc: core: set recovery_disabled when doing rproc_add()
From: Jingyi Wang @ 2026-04-07 2:40 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Dmitry Baryshkov, Bartosz Golaszewski, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, linux-arm-msm, linux-remoteproc,
devicetree, linux-kernel, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Luca Weiss, Konrad Dybcio
In-Reply-To: <adPLDWz6_QmBa8w1@baldur>
On 4/6/2026 11:04 PM, Bjorn Andersson wrote:
> On Thu, Mar 19, 2026 at 01:44:48PM +0800, Jingyi Wang wrote:
>>
>>
>> On 3/19/2026 1:23 PM, Dmitry Baryshkov wrote:
>>> On Thu, Mar 19, 2026 at 12:36:15PM +0800, Jingyi Wang wrote:
>>>>
>>>>
>>>> On 3/13/2026 10:37 AM, Dmitry Baryshkov wrote:
>>>>> On Wed, Mar 11, 2026 at 01:39:50AM -0700, Bartosz Golaszewski wrote:
>>>>>> On Wed, 11 Mar 2026 03:11:42 +0100, Dmitry Baryshkov
>>>>>> <dmitry.baryshkov@oss.qualcomm.com> said:
>>>>>>> On Tue, Mar 10, 2026 at 06:50:30AM -0700, Bartosz Golaszewski wrote:
>>>>>>>>
>>>>>>>> Ideally things like this would be passed to the rproc core in some kind of a
>>>>>>>> config structure and only set when registration succeeds. This looks to me
>>>>>>>> like papering over the real issue and I think it's still racy as there's no
>>>>>>>> true synchronization.
>>>>>>>>
>>>>>>>> Wouldn't it be better to take rproc->lock for the entire duration of
>>>>>>>> rproc_add()? It's already initialized in rproc_alloc().
>>>>>>>
>>>>>>> It would still be racy as rproc_trigger_recovery() is called outside of
>>>>>>> the lock. Instead the error cleanup path (and BTW, rproc_del() path too)
>>>>>>> must explicitly call cancel_work_sync() on the crash_handler work (and
>>>>>>> any other work items that can be scheduled).
>>>>>>>
>>>>>>
>>>>>> This looks weird TBH. For example: rproc_crash_handler_work() takes the lock,
>>>>>> but releases it right before calling inspecting rproc->recovery_disabled and
>>>>>> calling rproc_trigger_recovery(). It looks wrong, I think it should keep the
>>>>>> lock and rptoc_trigger_recovery() should enforce it being taken before the
>>>>>> call.
>>>>>
>>>>> Yes. Nevertheless the driver should cancel the work too.
>>>>>
>>>>
>>>> Hi Dmitry & Bartosz,
>>>>
>>>> rproc_crash_handler_work() may call rproc_trigger_recovery() and
>>>> rproc_add() may call rproc_boot(), both the function have already
>>>> hold the lock. And the lock cannot protect resources like glink_subdev
>>>> in the patch.
>>>>
>>>> And there is a possible case for cancel_work, rproc_add tear down call
>>>> cancel work and wait for the work finished, the reboot run successfully,
>>>> and the tear down continued and the resources all released, including sysfs
>>>> and glink_subdev.
>>>>
>>>> Indeed recovery_disabled is kind of hacky.
>>>> The root cause for this issue is that for remoteproc with RPROC_OFFLINE
>>>> state, the rproc_start will be called asynchronously, but for the remoteproc
>>>> with RPROC_DETACHED, the attach function is called directly, the failure
>>>> in this path will cause the rproc_add() fail and the resource release.
>>>> I think the current patch can be dropped, we are thinking about make rproc_attach
>>>> called asynchronously to avoid this race.
>>>
>>> Isn't this patch necessary for SoCCP bringup? If not, why did you
>>> include it into the series?
>>>
>> yes, will squash to soccp patch in next versoin.
>
> I'm sorry, but that doesn't make sense to me.
>
> The SoCCP patch adds support for attaching SoCCP. This change tries to
> address a generic problem shared across all remoteproc drivers (that
> does attach?).
>
> I think you should interpret Dmitry's comment as "why is this part of
> this series, please fix this problem in a separate series".
>
> Regards,
> Bjorn
Sorry I might misunderstand this comment, this patch only address problem for
remoteproc that does attach, I will send a separate series to make rproc_attach
called asynchronously
Thanks,
Jingyi
^ permalink raw reply
* Re: [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address
From: Inochi Amaoto @ 2026-04-07 2:36 UTC (permalink / raw)
To: Guo Ren, Inochi Amaoto
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Han Gao,
Nutty Liu, Guodong Xu, Xiaoguang Xing, devicetree, linux-riscv,
sophgo, linux-kernel, Yixun Lan, Longbin Li
In-Reply-To: <CAJF2gTTPt7UvFDRcA2EHfib1Yd0V8jjwAtqV8D2RCCGTn=RQ_g@mail.gmail.com>
On Tue, Apr 07, 2026 at 09:26:11AM +0800, Guo Ren wrote:
> On Tue, Apr 7, 2026 at 7:27 AM Inochi Amaoto <inochiama@gmail.com> wrote:
> >
> > Previous the CPU unit address cpu of sg2044 use decimal, it is
> > not following the general convention for unit addresses of the
> > OF. Convent the unit address to hex to resolve this problem.
> >
> > The introduces a small ABI break for the CPU id, but it should
> > affect nothing since there is no direct full-path reference to
> > these CPU nodes.
> >
> > Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/
>
> Remove the Link tag, and add:
>
> Reviewed-by: Guo Ren <guoren@kernel.org>
>
This link provides the motivation for this patch, I think it will be
fine for other to know why this patch is needed.
Regards,
Inochi
> > ---
> > arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++----------
> > 1 file changed, 118 insertions(+), 118 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
> > index 3135409c2149..f66a382c95bd 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
> > @@ -14,7 +14,7 @@ cpus {
> >
> > cpu0: cpu@0 {
> > compatible = "thead,c920", "riscv";
> > - reg = <0>;
> > + reg = <0x0>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller {
> >
> > cpu1: cpu@1 {
> > compatible = "thead,c920", "riscv";
> > - reg = <1>;
> > + reg = <0x1>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller {
> >
> > cpu2: cpu@2 {
> > compatible = "thead,c920", "riscv";
> > - reg = <2>;
> > + reg = <0x2>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller {
> >
> > cpu3: cpu@3 {
> > compatible = "thead,c920", "riscv";
> > - reg = <3>;
> > + reg = <0x3>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller {
> >
> > cpu4: cpu@4 {
> > compatible = "thead,c920", "riscv";
> > - reg = <4>;
> > + reg = <0x4>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller {
> >
> > cpu5: cpu@5 {
> > compatible = "thead,c920", "riscv";
> > - reg = <5>;
> > + reg = <0x5>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller {
> >
> > cpu6: cpu@6 {
> > compatible = "thead,c920", "riscv";
> > - reg = <6>;
> > + reg = <0x6>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller {
> >
> > cpu7: cpu@7 {
> > compatible = "thead,c920", "riscv";
> > - reg = <7>;
> > + reg = <0x7>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller {
> >
> > cpu8: cpu@8 {
> > compatible = "thead,c920", "riscv";
> > - reg = <8>;
> > + reg = <0x8>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller {
> >
> > cpu9: cpu@9 {
> > compatible = "thead,c920", "riscv";
> > - reg = <9>;
> > + reg = <0x9>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu10: cpu@10 {
> > + cpu10: cpu@a {
> > compatible = "thead,c920", "riscv";
> > - reg = <10>;
> > + reg = <0xa>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu11: cpu@11 {
> > + cpu11: cpu@b {
> > compatible = "thead,c920", "riscv";
> > - reg = <11>;
> > + reg = <0xb>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu12: cpu@12 {
> > + cpu12: cpu@c {
> > compatible = "thead,c920", "riscv";
> > - reg = <12>;
> > + reg = <0xc>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu13: cpu@13 {
> > + cpu13: cpu@d {
> > compatible = "thead,c920", "riscv";
> > - reg = <13>;
> > + reg = <0xd>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu14: cpu@14 {
> > + cpu14: cpu@e {
> > compatible = "thead,c920", "riscv";
> > - reg = <14>;
> > + reg = <0xe>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu15: cpu@15 {
> > + cpu15: cpu@f {
> > compatible = "thead,c920", "riscv";
> > - reg = <15>;
> > + reg = <0xf>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu16: cpu@16 {
> > + cpu16: cpu@10 {
> > compatible = "thead,c920", "riscv";
> > - reg = <16>;
> > + reg = <0x10>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu17: cpu@17 {
> > + cpu17: cpu@11 {
> > compatible = "thead,c920", "riscv";
> > - reg = <17>;
> > + reg = <0x11>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu18: cpu@18 {
> > + cpu18: cpu@12 {
> > compatible = "thead,c920", "riscv";
> > - reg = <18>;
> > + reg = <0x12>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu19: cpu@19 {
> > + cpu19: cpu@13 {
> > compatible = "thead,c920", "riscv";
> > - reg = <19>;
> > + reg = <0x13>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu20: cpu@20 {
> > + cpu20: cpu@14 {
> > compatible = "thead,c920", "riscv";
> > - reg = <20>;
> > + reg = <0x14>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu21: cpu@21 {
> > + cpu21: cpu@15 {
> > compatible = "thead,c920", "riscv";
> > - reg = <21>;
> > + reg = <0x15>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu22: cpu@22 {
> > + cpu22: cpu@16 {
> > compatible = "thead,c920", "riscv";
> > - reg = <22>;
> > + reg = <0x16>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu23: cpu@23 {
> > + cpu23: cpu@17 {
> > compatible = "thead,c920", "riscv";
> > - reg = <23>;
> > + reg = <0x17>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu24: cpu@24 {
> > + cpu24: cpu@18 {
> > compatible = "thead,c920", "riscv";
> > - reg = <24>;
> > + reg = <0x18>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu25: cpu@25 {
> > + cpu25: cpu@19 {
> > compatible = "thead,c920", "riscv";
> > - reg = <25>;
> > + reg = <0x19>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu26: cpu@26 {
> > + cpu26: cpu@1a {
> > compatible = "thead,c920", "riscv";
> > - reg = <26>;
> > + reg = <0x1a>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu27: cpu@27 {
> > + cpu27: cpu@1b {
> > compatible = "thead,c920", "riscv";
> > - reg = <27>;
> > + reg = <0x1b>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu28: cpu@28 {
> > + cpu28: cpu@1c {
> > compatible = "thead,c920", "riscv";
> > - reg = <28>;
> > + reg = <0x1c>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu29: cpu@29 {
> > + cpu29: cpu@1d {
> > compatible = "thead,c920", "riscv";
> > - reg = <29>;
> > + reg = <0x1d>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu30: cpu@30 {
> > + cpu30: cpu@1e {
> > compatible = "thead,c920", "riscv";
> > - reg = <30>;
> > + reg = <0x1e>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu31: cpu@31 {
> > + cpu31: cpu@1f {
> > compatible = "thead,c920", "riscv";
> > - reg = <31>;
> > + reg = <0x1f>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu32: cpu@32 {
> > + cpu32: cpu@20 {
> > compatible = "thead,c920", "riscv";
> > - reg = <32>;
> > + reg = <0x20>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu33: cpu@33 {
> > + cpu33: cpu@21 {
> > compatible = "thead,c920", "riscv";
> > - reg = <33>;
> > + reg = <0x21>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu34: cpu@34 {
> > + cpu34: cpu@22 {
> > compatible = "thead,c920", "riscv";
> > - reg = <34>;
> > + reg = <0x22>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu35: cpu@35 {
> > + cpu35: cpu@23 {
> > compatible = "thead,c920", "riscv";
> > - reg = <35>;
> > + reg = <0x23>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu36: cpu@36 {
> > + cpu36: cpu@24 {
> > compatible = "thead,c920", "riscv";
> > - reg = <36>;
> > + reg = <0x24>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu37: cpu@37 {
> > + cpu37: cpu@25 {
> > compatible = "thead,c920", "riscv";
> > - reg = <37>;
> > + reg = <0x25>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu38: cpu@38 {
> > + cpu38: cpu@26 {
> > compatible = "thead,c920", "riscv";
> > - reg = <38>;
> > + reg = <0x26>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu39: cpu@39 {
> > + cpu39: cpu@27 {
> > compatible = "thead,c920", "riscv";
> > - reg = <39>;
> > + reg = <0x27>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu40: cpu@40 {
> > + cpu40: cpu@28 {
> > compatible = "thead,c920", "riscv";
> > - reg = <40>;
> > + reg = <0x28>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu41: cpu@41 {
> > + cpu41: cpu@29 {
> > compatible = "thead,c920", "riscv";
> > - reg = <41>;
> > + reg = <0x29>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu42: cpu@42 {
> > + cpu42: cpu@2a {
> > compatible = "thead,c920", "riscv";
> > - reg = <42>;
> > + reg = <0x2a>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu43: cpu@43 {
> > + cpu43: cpu@2b {
> > compatible = "thead,c920", "riscv";
> > - reg = <43>;
> > + reg = <0x2b>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu44: cpu@44 {
> > + cpu44: cpu@2c {
> > compatible = "thead,c920", "riscv";
> > - reg = <44>;
> > + reg = <0x2c>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu45: cpu@45 {
> > + cpu45: cpu@2d {
> > compatible = "thead,c920", "riscv";
> > - reg = <45>;
> > + reg = <0x2d>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu46: cpu@46 {
> > + cpu46: cpu@2e {
> > compatible = "thead,c920", "riscv";
> > - reg = <46>;
> > + reg = <0x2e>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu47: cpu@47 {
> > + cpu47: cpu@2f {
> > compatible = "thead,c920", "riscv";
> > - reg = <47>;
> > + reg = <0x2f>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu48: cpu@48 {
> > + cpu48: cpu@30 {
> > compatible = "thead,c920", "riscv";
> > - reg = <48>;
> > + reg = <0x30>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu49: cpu@49 {
> > + cpu49: cpu@31 {
> > compatible = "thead,c920", "riscv";
> > - reg = <49>;
> > + reg = <0x31>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu50: cpu@50 {
> > + cpu50: cpu@32 {
> > compatible = "thead,c920", "riscv";
> > - reg = <50>;
> > + reg = <0x32>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu51: cpu@51 {
> > + cpu51: cpu@33 {
> > compatible = "thead,c920", "riscv";
> > - reg = <51>;
> > + reg = <0x33>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu52: cpu@52 {
> > + cpu52: cpu@34 {
> > compatible = "thead,c920", "riscv";
> > - reg = <52>;
> > + reg = <0x34>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu53: cpu@53 {
> > + cpu53: cpu@35 {
> > compatible = "thead,c920", "riscv";
> > - reg = <53>;
> > + reg = <0x35>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu54: cpu@54 {
> > + cpu54: cpu@36 {
> > compatible = "thead,c920", "riscv";
> > - reg = <54>;
> > + reg = <0x36>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu55: cpu@55 {
> > + cpu55: cpu@37 {
> > compatible = "thead,c920", "riscv";
> > - reg = <55>;
> > + reg = <0x37>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu56: cpu@56 {
> > + cpu56: cpu@38 {
> > compatible = "thead,c920", "riscv";
> > - reg = <56>;
> > + reg = <0x38>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu57: cpu@57 {
> > + cpu57: cpu@39 {
> > compatible = "thead,c920", "riscv";
> > - reg = <57>;
> > + reg = <0x39>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu58: cpu@58 {
> > + cpu58: cpu@3a {
> > compatible = "thead,c920", "riscv";
> > - reg = <58>;
> > + reg = <0x3a>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu59: cpu@59 {
> > + cpu59: cpu@3b {
> > compatible = "thead,c920", "riscv";
> > - reg = <59>;
> > + reg = <0x3b>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu60: cpu@60 {
> > + cpu60: cpu@3c {
> > compatible = "thead,c920", "riscv";
> > - reg = <60>;
> > + reg = <0x3c>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu61: cpu@61 {
> > + cpu61: cpu@3d {
> > compatible = "thead,c920", "riscv";
> > - reg = <61>;
> > + reg = <0x3d>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu62: cpu@62 {
> > + cpu62: cpu@3e {
> > compatible = "thead,c920", "riscv";
> > - reg = <62>;
> > + reg = <0x3e>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > @@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller {
> > };
> > };
> >
> > - cpu63: cpu@63 {
> > + cpu63: cpu@3f {
> > compatible = "thead,c920", "riscv";
> > - reg = <63>;
> > + reg = <0x3f>;
> > i-cache-block-size = <64>;
> > i-cache-size = <65536>;
> > i-cache-sets = <512>;
> > --
> > 2.53.0
> >
>
>
> --
> Best Regards
> Guo Ren
^ permalink raw reply
* Re: [PATCH ath-next v4 0/6] wifi: ath12k: Enable IPQ5424 AHB WiFi device
From: Baochen Qiang @ 2026-04-07 2:23 UTC (permalink / raw)
To: Krzysztof Kozlowski, Raj Kumar Bhagat, Johannes Berg, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jeff Johnson
Cc: linux-wireless, devicetree, linux-kernel, ath12k,
Saravanakumar Duraisamy, Sowmiya Sree Elavalagan
In-Reply-To: <95face24-deaf-47c4-935d-0b48b5141371@kernel.org>
On 4/4/2026 1:23 PM, Krzysztof Kozlowski wrote:
> On 03/04/2026 11:13, Baochen Qiang wrote:
>>>
>>> .../bindings/net/wireless/qcom,ipq5332-wifi.yaml | 1 +
>>> drivers/net/wireless/ath/ath12k/ahb.c | 36 +++++----
>>> drivers/net/wireless/ath/ath12k/ahb.h | 1 +
>>> drivers/net/wireless/ath/ath12k/ce.h | 13 ++-
>>> drivers/net/wireless/ath/ath12k/core.h | 1 +
>>> drivers/net/wireless/ath/ath12k/wifi7/ahb.c | 8 ++
>>> drivers/net/wireless/ath/ath12k/wifi7/hal.c | 7 ++
>>> drivers/net/wireless/ath/ath12k/wifi7/hal.h | 3 +
>>> .../net/wireless/ath/ath12k/wifi7/hal_qcn9274.c | 88 ++++++++++++++++++++
>>> .../net/wireless/ath/ath12k/wifi7/hal_qcn9274.h | 1 +
>>> drivers/net/wireless/ath/ath12k/wifi7/hw.c | 93 +++++++++++++++++++++-
>>> 11 files changed, 231 insertions(+), 21 deletions(-)
>>> ---
>>> base-commit: 15551ababf6d4e857f2101366a0c3eaa86dd822c
>>> change-id: 20260331-ath12k-ipq5424-cddb63a46a97
>>>
>>
>> only nit in patch 2/6, so for patches 2-6/6:
>>
>> Reviewed-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com>
>
> It does not work like this. Replying to cover letter causes that all
> patches will get it. Provide detailed review and response to each email
> in such case.
Got it, thank you!
>
> Best regards,
> Krzysztof
^ permalink raw reply
* Re: [PATCH v3 0/5] NFC support for five Qualcomm SDM845 phones
From: patchwork-bot+netdevbpf @ 2026-04-07 2:10 UTC (permalink / raw)
To: David Heidelberg
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, amartinz,
andrew+netdev, davem, edumazet, kuba, pabeni, casey.connolly,
amartinz, petr.hodina, l.j.beemster, netdev, linux-arm-msm,
oe-linux-nfc, devicetree, linux-kernel, phone-devel, krzk
In-Reply-To: <20260403-oneplus-nfc-v3-0-fbdce57d63c1@ixit.cz>
Hello:
This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Fri, 03 Apr 2026 15:58:45 +0200 you wrote:
> - OnePlus 6 / 6T
> - Pixel 3 / 3 XL
> - SHIFT 6MQ
>
> Verified with NFC card using neard:
>
> systemctl enable --now neard
> nfctool --device nfc0 -1
> nfctool -d nfc0 -p
> gdbus introspect --system --dest org.neard --object-path /org/neard/nfc0/tag0/record0
>
> [...]
Here is the summary with links:
- [v3,1/5] dt-bindings: nfc: nxp,nci: Document PN557 compatible
https://git.kernel.org/netdev/net-next/c/e72058a4bed0
- [v3,2/5] arm64: dts: qcom: sdm845-oneplus: Enable NFC
(no matching commit)
- [v3,3/5] arm64: dts: qcom: sdm845-shift-axolotl: Correct touchscreen sleep state
(no matching commit)
- [v3,4/5] arm64: dts: qcom: sdm845-shift-axolotl: Enable NFC
(no matching commit)
- [v3,5/5] arm64: dts: qcom: sdm845-google-common: Enable NFC
(no matching commit)
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: imx8mm: imx8mp: Add DTOs for Data Modul i.MX8M Mini and Plus eDM SBC
From: Frank Li @ 2026-04-07 1:58 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, devicetree, imx, linux-kernel
In-Reply-To: <20260406215959.184061-1-marex@nabladev.com>
On Mon, Apr 06, 2026 at 11:58:45PM +0200, Marek Vasut wrote:
> Add DT overlay for feature connector expansion module eDM-MOD-iMX8Mm-FIO1
> providing additional UARTs, CAN, PWM Beeper, I2C, SPI and GPIO breakout.
> This adapter can be optionally populated onto the eDM SBC.
>
> Add DT overlay for the DSI-to-HDMI adapter eDM-MOD-iMX8Mm-HDMI populated
> with Lontium LT9611 bridge. This adapter can be optionally populated onto
> the eDM SBC.
>
> Add DT overlay for the DSI-to-LVDS adapter eDM-MOD-iMX8Mm-LVDS populated
> with Lontium LT9211 bridge. This adapter can be optionally populated onto
> the eDM SBC. This adapter can be extended with multiple panels, currently
> supported are the following:
At least you can split to 3 patches to add these.
...
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
> new file mode 100644
> index 0000000000000..f446938b74006
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtso
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024-2026 Marek Vasut
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/clock/imx8mm-clock.h>
> +
> +#include "imx8mm-pinfunc.h"
> +#include "imx8mm-data-modul-edm-sbc-overlay-edm-mod-imx8mm-fio1-audio.dtsi"
> +
> +&can_fio {
> + interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
Now, I have not good ways to unify this information for difference boards
yet. It is quite common user case, let me think more.
> +};
> +
> +&iomuxc {
> + pinctrl_codec_mclk: codec-mclk_feature-grp {
> + fsl,pins = <
> + /* GPIO4_IO27 */
> + MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x2
> + >;
> + };
> +
> + pinctrl_sai2: sai2_feature-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x90
> + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x96
> + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x90
> + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x96
> + >;
> + };
I think this part should be in main boards's dts file, there should have
hardware plug header, which include these signals.
If there are other added on boards, add-on dtso can resuse the label,
pinctrl_sai2 and pinctrl_codec_mclk.
> +};
> +
> +&pinctrl_hog_feature {
> + fsl,pins = <
> + /* GPIO5_IO03 */
> + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006
> + /* GPIO5_IO04 */
> + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006
> +
> + /* CAN_INT# */
> + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090
> + >;
> +};
> +
> +&sai2 {
> + assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
> + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
> + fsl,sai-bit-clock-swap;
> +};
> +
> +&sgtl5000_fio {
> + VDDA-supply = <&buck4_reg>;
> + VDDD-supply = <&buck5_reg>;
> + VDDIO-supply = <&buck4_reg>;
buck4_reg can provide addtional label, such as porta_vdd ..., so needn't
this sections.
> +};
> +
> +&spba2 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sai5clk: clock-controller@30050000 { /* SAI5 */
> + compatible = "fsl,imx8mm-sai-clock", "fsl,imx8mq-sai-clock";
> + reg = <0x30050000 0x10000>;
> + #clock-cells = <1>;
Not sure why need overwrite these informaiton here, suppose it should be
the same for Soc.
Frank
^ permalink raw reply
* Re: [PATCH v2 4/5] phy: qcom: qmp-pcie: Add Gen5 8-lanes mode for Glymur
From: Qiang Yu @ 2026-04-07 1:49 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Dmitry Baryshkov, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <ac0ubhTTsUNKHD__@baldur>
On Wed, Apr 01, 2026 at 09:41:03AM -0500, Bjorn Andersson wrote:
> On Tue, Mar 31, 2026 at 02:59:12AM -0700, Qiang Yu wrote:
> > On Tue, Mar 24, 2026 at 11:23:19PM +0200, Dmitry Baryshkov wrote:
> > > On Mon, Mar 23, 2026 at 12:15:31AM -0700, Qiang Yu wrote:
> > > > The third PCIe controller on Glymur SoC supports 8-lane operation via
> > > > bifurcation of two PHYs (each requires separate power domian, resets and
> > > > aux clk).
> > > >
> > > > Add dedicated reset/no_csr reset list ("phy_b", "phy_b_nocsr") and
> > > > clock ("phy_b_aux") required for 8-lane operation. Introduce new
> > > > glymur_qmp_gen5x8_pciephy_cfg configuration to enable PCIe Gen5 x8 mode.
> > > >
> > > > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > > > ---
> > > > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 30 +++++++++++++++++++++++++++++-
> > > > 1 file changed, 29 insertions(+), 1 deletion(-)
> > > >
> > > > @@ -4705,6 +4713,23 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = {
> > > > .phy_status = PHYSTATUS_4_20,
> > > > };
> > > >
> > > > +static const struct qmp_phy_cfg glymur_qmp_gen5x8_pciephy_cfg = {
> > > > + .lanes = 8,
> > > > +
> > > > + .offsets = &qmp_pcie_offsets_v8_50,
> > > > +
> > > > + .reset_list = glymur_pciephy_reset_l,
> > > > + .num_resets = ARRAY_SIZE(glymur_pciephy_reset_l),
> > > > + .nocsr_reset_list = glymur_pciephy_nocsr_reset_l,
> > > > + .num_nocsr_resets = ARRAY_SIZE(glymur_pciephy_nocsr_reset_l),
> > >
> > > Just for my understanding. If it was not the NOCSR case and had to
> > > program the registers, would we have needed to program anything in the
> > > PCIe3B space?
> >
> > The PCIe3B PHY registers need to be programmed.
>
> Why?
Because PCIe3A and PCIe3B are independent PHYs, each has its own SWI
interface. Per the PHY HPG, all SWI interfaces must be configured, so in a
non-NOCSR flow we also need to program PCIe3B PHY registers. This is
required by the hardware design.
- Qiang Yu
>
> Regards,
> Bjorn
>
> > But we don't need to do it explicitly because there are also broadcast
> > registers: writing to these registers will automatically write the same
> > offset and value to both PHY ports simultaneously.
> >
> > - Qiang Yu
> > >
> > > > + .vreg_list = qmp_phy_vreg_l,
> > > > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> > > > +
> > > > + .regs = pciephy_v8_50_regs_layout,
> > > > +
> > > > + .phy_status = PHYSTATUS_4_20,
> > > > +};
> > > > +
> > > > static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
> > > > {
> > > > const struct qmp_phy_cfg *cfg = qmp->cfg;
> > > > @@ -5483,6 +5508,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
> > > > }, {
> > > > .compatible = "qcom,glymur-qmp-gen5x4-pcie-phy",
> > > > .data = &glymur_qmp_gen5x4_pciephy_cfg,
> > > > + }, {
> > > > + .compatible = "qcom,glymur-qmp-gen5x8-pcie-phy",
> > > > + .data = &glymur_qmp_gen5x8_pciephy_cfg,
> > > > }, {
> > > > .compatible = "qcom,ipq6018-qmp-pcie-phy",
> > > > .data = &ipq6018_pciephy_cfg,
> > > >
> > > > --
> > > > 2.34.1
> > > >
> > >
> > > --
> > > With best wishes
> > > Dmitry
^ permalink raw reply
* Re: [PATCH v1 17/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator
From: Changhuang Liang @ 2026-04-07 1:37 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-hardening@vger.kernel.org,
netdev@vger.kernel.org, JeeHeng Sia, Hal Feng, Leyfoon Tan
In-Reply-To: <20260404-valiant-auburn-raven-c24be6@quoll>
Hi, Krzysztof
Thanks for the review.
> On Thu, Apr 02, 2026 at 03:55:18AM -0700, Changhuang Liang wrote:
> > + clocks:
> > + items:
> > + - description: Peripheral-2 600MHz
> > + - description: Peripheral-2 400MHz
> > + - description: Peripheral-2 125MHz
> > + - description: Peripheral-2 GMAC2 RGMII RX
> > + - description: Peripheral-2 GMAC2 RMII Reference
> > + - description: Peripheral-2 GMAC3 SGMII TX
> > + - description: Peripheral-2 GMAC3 SGMII RX
> > + - description: Main Oscillator (25 MHz)
> > +
> > + clock-names:
> > + items:
> > + - const: per2_600
>
> Does not have any meaningful name in datasheet / clock hierarchy?
Yes, some clocks are named directly by frequency.
I will try to find if there are other meaningful naming options.
Best Regards,
Changhuang
^ permalink raw reply
* Re: [PATCH 2/2] riscv: dts: sophgo: sg2042: use hex for CPU unit address
From: Guo Ren @ 2026-04-07 1:26 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Han Gao,
Nutty Liu, Guodong Xu, Xiaoguang Xing, devicetree, linux-riscv,
sophgo, linux-kernel, Yixun Lan, Longbin Li
In-Reply-To: <20260406232655.144043-3-inochiama@gmail.com>
On Tue, Apr 7, 2026 at 7:27 AM Inochi Amaoto <inochiama@gmail.com> wrote:
>
> Previous the CPU unit address cpu of sg2042 use decimal, it is
> not following the general convention for unit addresses of the
> OF. Convent the unit address to hex to resolve this problem.
>
> The introduces a small ABI break for the CPU id, but it should
> affect nothing since there is no direct full-path reference to
> these CPU nodes.
>
> Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10")
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/
I don't think this tag is necessary. For others:
Reviewed-by: Guo Ren <guoren@kernel.org>
> ---
> arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++----------
> 1 file changed, 118 insertions(+), 118 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> index 509488eee432..fd8906b313d2 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> @@ -263,7 +263,7 @@ cpu0: cpu@0 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <0>;
> + reg = <0x0>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -291,7 +291,7 @@ cpu1: cpu@1 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <1>;
> + reg = <0x1>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -319,7 +319,7 @@ cpu2: cpu@2 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <2>;
> + reg = <0x2>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -347,7 +347,7 @@ cpu3: cpu@3 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <3>;
> + reg = <0x3>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -375,7 +375,7 @@ cpu4: cpu@4 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <4>;
> + reg = <0x4>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -403,7 +403,7 @@ cpu5: cpu@5 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <5>;
> + reg = <0x5>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -431,7 +431,7 @@ cpu6: cpu@6 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <6>;
> + reg = <0x6>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -459,7 +459,7 @@ cpu7: cpu@7 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <7>;
> + reg = <0x7>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -487,7 +487,7 @@ cpu8: cpu@8 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <8>;
> + reg = <0x8>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -515,7 +515,7 @@ cpu9: cpu@9 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <9>;
> + reg = <0x9>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller {
> };
> };
>
> - cpu10: cpu@10 {
> + cpu10: cpu@a {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -543,7 +543,7 @@ cpu10: cpu@10 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <10>;
> + reg = <0xa>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller {
> };
> };
>
> - cpu11: cpu@11 {
> + cpu11: cpu@b {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -571,7 +571,7 @@ cpu11: cpu@11 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <11>;
> + reg = <0xb>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller {
> };
> };
>
> - cpu12: cpu@12 {
> + cpu12: cpu@c {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -599,7 +599,7 @@ cpu12: cpu@12 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <12>;
> + reg = <0xc>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller {
> };
> };
>
> - cpu13: cpu@13 {
> + cpu13: cpu@d {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -627,7 +627,7 @@ cpu13: cpu@13 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <13>;
> + reg = <0xd>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller {
> };
> };
>
> - cpu14: cpu@14 {
> + cpu14: cpu@e {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -655,7 +655,7 @@ cpu14: cpu@14 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <14>;
> + reg = <0xe>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller {
> };
> };
>
> - cpu15: cpu@15 {
> + cpu15: cpu@f {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -683,7 +683,7 @@ cpu15: cpu@15 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <15>;
> + reg = <0xf>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller {
> };
> };
>
> - cpu16: cpu@16 {
> + cpu16: cpu@10 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -711,7 +711,7 @@ cpu16: cpu@16 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <16>;
> + reg = <0x10>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller {
> };
> };
>
> - cpu17: cpu@17 {
> + cpu17: cpu@11 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -739,7 +739,7 @@ cpu17: cpu@17 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <17>;
> + reg = <0x11>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller {
> };
> };
>
> - cpu18: cpu@18 {
> + cpu18: cpu@12 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -767,7 +767,7 @@ cpu18: cpu@18 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <18>;
> + reg = <0x12>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller {
> };
> };
>
> - cpu19: cpu@19 {
> + cpu19: cpu@13 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -795,7 +795,7 @@ cpu19: cpu@19 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <19>;
> + reg = <0x13>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller {
> };
> };
>
> - cpu20: cpu@20 {
> + cpu20: cpu@14 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -823,7 +823,7 @@ cpu20: cpu@20 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <20>;
> + reg = <0x14>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller {
> };
> };
>
> - cpu21: cpu@21 {
> + cpu21: cpu@15 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -851,7 +851,7 @@ cpu21: cpu@21 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <21>;
> + reg = <0x15>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller {
> };
> };
>
> - cpu22: cpu@22 {
> + cpu22: cpu@16 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -879,7 +879,7 @@ cpu22: cpu@22 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <22>;
> + reg = <0x16>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller {
> };
> };
>
> - cpu23: cpu@23 {
> + cpu23: cpu@17 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -907,7 +907,7 @@ cpu23: cpu@23 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <23>;
> + reg = <0x17>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller {
> };
> };
>
> - cpu24: cpu@24 {
> + cpu24: cpu@18 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -935,7 +935,7 @@ cpu24: cpu@24 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <24>;
> + reg = <0x18>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller {
> };
> };
>
> - cpu25: cpu@25 {
> + cpu25: cpu@19 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -963,7 +963,7 @@ cpu25: cpu@25 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <25>;
> + reg = <0x19>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller {
> };
> };
>
> - cpu26: cpu@26 {
> + cpu26: cpu@1a {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -991,7 +991,7 @@ cpu26: cpu@26 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <26>;
> + reg = <0x1a>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller {
> };
> };
>
> - cpu27: cpu@27 {
> + cpu27: cpu@1b {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1019,7 +1019,7 @@ cpu27: cpu@27 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <27>;
> + reg = <0x1b>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller {
> };
> };
>
> - cpu28: cpu@28 {
> + cpu28: cpu@1c {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1047,7 +1047,7 @@ cpu28: cpu@28 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <28>;
> + reg = <0x1c>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller {
> };
> };
>
> - cpu29: cpu@29 {
> + cpu29: cpu@1d {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1075,7 +1075,7 @@ cpu29: cpu@29 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <29>;
> + reg = <0x1d>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller {
> };
> };
>
> - cpu30: cpu@30 {
> + cpu30: cpu@1e {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1103,7 +1103,7 @@ cpu30: cpu@30 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <30>;
> + reg = <0x1e>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller {
> };
> };
>
> - cpu31: cpu@31 {
> + cpu31: cpu@1f {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1131,7 +1131,7 @@ cpu31: cpu@31 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <31>;
> + reg = <0x1f>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller {
> };
> };
>
> - cpu32: cpu@32 {
> + cpu32: cpu@20 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1159,7 +1159,7 @@ cpu32: cpu@32 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <32>;
> + reg = <0x20>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller {
> };
> };
>
> - cpu33: cpu@33 {
> + cpu33: cpu@21 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1187,7 +1187,7 @@ cpu33: cpu@33 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <33>;
> + reg = <0x21>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller {
> };
> };
>
> - cpu34: cpu@34 {
> + cpu34: cpu@22 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1215,7 +1215,7 @@ cpu34: cpu@34 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <34>;
> + reg = <0x22>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller {
> };
> };
>
> - cpu35: cpu@35 {
> + cpu35: cpu@23 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1243,7 +1243,7 @@ cpu35: cpu@35 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <35>;
> + reg = <0x23>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller {
> };
> };
>
> - cpu36: cpu@36 {
> + cpu36: cpu@24 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1271,7 +1271,7 @@ cpu36: cpu@36 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <36>;
> + reg = <0x24>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller {
> };
> };
>
> - cpu37: cpu@37 {
> + cpu37: cpu@25 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1299,7 +1299,7 @@ cpu37: cpu@37 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <37>;
> + reg = <0x25>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller {
> };
> };
>
> - cpu38: cpu@38 {
> + cpu38: cpu@26 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1327,7 +1327,7 @@ cpu38: cpu@38 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <38>;
> + reg = <0x26>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller {
> };
> };
>
> - cpu39: cpu@39 {
> + cpu39: cpu@27 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1355,7 +1355,7 @@ cpu39: cpu@39 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <39>;
> + reg = <0x27>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller {
> };
> };
>
> - cpu40: cpu@40 {
> + cpu40: cpu@28 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1383,7 +1383,7 @@ cpu40: cpu@40 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <40>;
> + reg = <0x28>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller {
> };
> };
>
> - cpu41: cpu@41 {
> + cpu41: cpu@29 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1411,7 +1411,7 @@ cpu41: cpu@41 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <41>;
> + reg = <0x29>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller {
> };
> };
>
> - cpu42: cpu@42 {
> + cpu42: cpu@2a {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1439,7 +1439,7 @@ cpu42: cpu@42 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <42>;
> + reg = <0x2a>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller {
> };
> };
>
> - cpu43: cpu@43 {
> + cpu43: cpu@2b {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1467,7 +1467,7 @@ cpu43: cpu@43 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <43>;
> + reg = <0x2b>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller {
> };
> };
>
> - cpu44: cpu@44 {
> + cpu44: cpu@2c {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1495,7 +1495,7 @@ cpu44: cpu@44 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <44>;
> + reg = <0x2c>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller {
> };
> };
>
> - cpu45: cpu@45 {
> + cpu45: cpu@2d {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1523,7 +1523,7 @@ cpu45: cpu@45 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <45>;
> + reg = <0x2d>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller {
> };
> };
>
> - cpu46: cpu@46 {
> + cpu46: cpu@2e {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1551,7 +1551,7 @@ cpu46: cpu@46 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <46>;
> + reg = <0x2e>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller {
> };
> };
>
> - cpu47: cpu@47 {
> + cpu47: cpu@2f {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1579,7 +1579,7 @@ cpu47: cpu@47 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <47>;
> + reg = <0x2f>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller {
> };
> };
>
> - cpu48: cpu@48 {
> + cpu48: cpu@30 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1607,7 +1607,7 @@ cpu48: cpu@48 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <48>;
> + reg = <0x30>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller {
> };
> };
>
> - cpu49: cpu@49 {
> + cpu49: cpu@31 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1635,7 +1635,7 @@ cpu49: cpu@49 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <49>;
> + reg = <0x31>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller {
> };
> };
>
> - cpu50: cpu@50 {
> + cpu50: cpu@32 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1663,7 +1663,7 @@ cpu50: cpu@50 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <50>;
> + reg = <0x32>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller {
> };
> };
>
> - cpu51: cpu@51 {
> + cpu51: cpu@33 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1691,7 +1691,7 @@ cpu51: cpu@51 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <51>;
> + reg = <0x33>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller {
> };
> };
>
> - cpu52: cpu@52 {
> + cpu52: cpu@34 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1719,7 +1719,7 @@ cpu52: cpu@52 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <52>;
> + reg = <0x34>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller {
> };
> };
>
> - cpu53: cpu@53 {
> + cpu53: cpu@35 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1747,7 +1747,7 @@ cpu53: cpu@53 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <53>;
> + reg = <0x35>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller {
> };
> };
>
> - cpu54: cpu@54 {
> + cpu54: cpu@36 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1775,7 +1775,7 @@ cpu54: cpu@54 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <54>;
> + reg = <0x36>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller {
> };
> };
>
> - cpu55: cpu@55 {
> + cpu55: cpu@37 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1803,7 +1803,7 @@ cpu55: cpu@55 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <55>;
> + reg = <0x37>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller {
> };
> };
>
> - cpu56: cpu@56 {
> + cpu56: cpu@38 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1831,7 +1831,7 @@ cpu56: cpu@56 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <56>;
> + reg = <0x38>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller {
> };
> };
>
> - cpu57: cpu@57 {
> + cpu57: cpu@39 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1859,7 +1859,7 @@ cpu57: cpu@57 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <57>;
> + reg = <0x39>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller {
> };
> };
>
> - cpu58: cpu@58 {
> + cpu58: cpu@3a {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1887,7 +1887,7 @@ cpu58: cpu@58 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <58>;
> + reg = <0x3a>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller {
> };
> };
>
> - cpu59: cpu@59 {
> + cpu59: cpu@3b {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1915,7 +1915,7 @@ cpu59: cpu@59 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <59>;
> + reg = <0x3b>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller {
> };
> };
>
> - cpu60: cpu@60 {
> + cpu60: cpu@3c {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1943,7 +1943,7 @@ cpu60: cpu@60 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <60>;
> + reg = <0x3c>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller {
> };
> };
>
> - cpu61: cpu@61 {
> + cpu61: cpu@3d {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1971,7 +1971,7 @@ cpu61: cpu@61 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <61>;
> + reg = <0x3d>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller {
> };
> };
>
> - cpu62: cpu@62 {
> + cpu62: cpu@3e {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -1999,7 +1999,7 @@ cpu62: cpu@62 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <62>;
> + reg = <0x3e>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller {
> };
> };
>
> - cpu63: cpu@63 {
> + cpu63: cpu@3f {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> @@ -2027,7 +2027,7 @@ cpu63: cpu@63 {
> "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> - reg = <63>;
> + reg = <0x3f>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> --
> 2.53.0
>
--
Best Regards
Guo Ren
^ permalink raw reply
* Re: [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address
From: Guo Ren @ 2026-04-07 1:26 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Han Gao,
Nutty Liu, Guodong Xu, Xiaoguang Xing, devicetree, linux-riscv,
sophgo, linux-kernel, Yixun Lan, Longbin Li
In-Reply-To: <20260406232655.144043-2-inochiama@gmail.com>
On Tue, Apr 7, 2026 at 7:27 AM Inochi Amaoto <inochiama@gmail.com> wrote:
>
> Previous the CPU unit address cpu of sg2044 use decimal, it is
> not following the general convention for unit addresses of the
> OF. Convent the unit address to hex to resolve this problem.
>
> The introduces a small ABI break for the CPU id, but it should
> affect nothing since there is no direct full-path reference to
> these CPU nodes.
>
> Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/
Remove the Link tag, and add:
Reviewed-by: Guo Ren <guoren@kernel.org>
> ---
> arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++----------
> 1 file changed, 118 insertions(+), 118 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
> index 3135409c2149..f66a382c95bd 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
> @@ -14,7 +14,7 @@ cpus {
>
> cpu0: cpu@0 {
> compatible = "thead,c920", "riscv";
> - reg = <0>;
> + reg = <0x0>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller {
>
> cpu1: cpu@1 {
> compatible = "thead,c920", "riscv";
> - reg = <1>;
> + reg = <0x1>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller {
>
> cpu2: cpu@2 {
> compatible = "thead,c920", "riscv";
> - reg = <2>;
> + reg = <0x2>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller {
>
> cpu3: cpu@3 {
> compatible = "thead,c920", "riscv";
> - reg = <3>;
> + reg = <0x3>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller {
>
> cpu4: cpu@4 {
> compatible = "thead,c920", "riscv";
> - reg = <4>;
> + reg = <0x4>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller {
>
> cpu5: cpu@5 {
> compatible = "thead,c920", "riscv";
> - reg = <5>;
> + reg = <0x5>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller {
>
> cpu6: cpu@6 {
> compatible = "thead,c920", "riscv";
> - reg = <6>;
> + reg = <0x6>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller {
>
> cpu7: cpu@7 {
> compatible = "thead,c920", "riscv";
> - reg = <7>;
> + reg = <0x7>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller {
>
> cpu8: cpu@8 {
> compatible = "thead,c920", "riscv";
> - reg = <8>;
> + reg = <0x8>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller {
>
> cpu9: cpu@9 {
> compatible = "thead,c920", "riscv";
> - reg = <9>;
> + reg = <0x9>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller {
> };
> };
>
> - cpu10: cpu@10 {
> + cpu10: cpu@a {
> compatible = "thead,c920", "riscv";
> - reg = <10>;
> + reg = <0xa>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller {
> };
> };
>
> - cpu11: cpu@11 {
> + cpu11: cpu@b {
> compatible = "thead,c920", "riscv";
> - reg = <11>;
> + reg = <0xb>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller {
> };
> };
>
> - cpu12: cpu@12 {
> + cpu12: cpu@c {
> compatible = "thead,c920", "riscv";
> - reg = <12>;
> + reg = <0xc>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller {
> };
> };
>
> - cpu13: cpu@13 {
> + cpu13: cpu@d {
> compatible = "thead,c920", "riscv";
> - reg = <13>;
> + reg = <0xd>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller {
> };
> };
>
> - cpu14: cpu@14 {
> + cpu14: cpu@e {
> compatible = "thead,c920", "riscv";
> - reg = <14>;
> + reg = <0xe>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller {
> };
> };
>
> - cpu15: cpu@15 {
> + cpu15: cpu@f {
> compatible = "thead,c920", "riscv";
> - reg = <15>;
> + reg = <0xf>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller {
> };
> };
>
> - cpu16: cpu@16 {
> + cpu16: cpu@10 {
> compatible = "thead,c920", "riscv";
> - reg = <16>;
> + reg = <0x10>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller {
> };
> };
>
> - cpu17: cpu@17 {
> + cpu17: cpu@11 {
> compatible = "thead,c920", "riscv";
> - reg = <17>;
> + reg = <0x11>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller {
> };
> };
>
> - cpu18: cpu@18 {
> + cpu18: cpu@12 {
> compatible = "thead,c920", "riscv";
> - reg = <18>;
> + reg = <0x12>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller {
> };
> };
>
> - cpu19: cpu@19 {
> + cpu19: cpu@13 {
> compatible = "thead,c920", "riscv";
> - reg = <19>;
> + reg = <0x13>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller {
> };
> };
>
> - cpu20: cpu@20 {
> + cpu20: cpu@14 {
> compatible = "thead,c920", "riscv";
> - reg = <20>;
> + reg = <0x14>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller {
> };
> };
>
> - cpu21: cpu@21 {
> + cpu21: cpu@15 {
> compatible = "thead,c920", "riscv";
> - reg = <21>;
> + reg = <0x15>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller {
> };
> };
>
> - cpu22: cpu@22 {
> + cpu22: cpu@16 {
> compatible = "thead,c920", "riscv";
> - reg = <22>;
> + reg = <0x16>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller {
> };
> };
>
> - cpu23: cpu@23 {
> + cpu23: cpu@17 {
> compatible = "thead,c920", "riscv";
> - reg = <23>;
> + reg = <0x17>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller {
> };
> };
>
> - cpu24: cpu@24 {
> + cpu24: cpu@18 {
> compatible = "thead,c920", "riscv";
> - reg = <24>;
> + reg = <0x18>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller {
> };
> };
>
> - cpu25: cpu@25 {
> + cpu25: cpu@19 {
> compatible = "thead,c920", "riscv";
> - reg = <25>;
> + reg = <0x19>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller {
> };
> };
>
> - cpu26: cpu@26 {
> + cpu26: cpu@1a {
> compatible = "thead,c920", "riscv";
> - reg = <26>;
> + reg = <0x1a>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller {
> };
> };
>
> - cpu27: cpu@27 {
> + cpu27: cpu@1b {
> compatible = "thead,c920", "riscv";
> - reg = <27>;
> + reg = <0x1b>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller {
> };
> };
>
> - cpu28: cpu@28 {
> + cpu28: cpu@1c {
> compatible = "thead,c920", "riscv";
> - reg = <28>;
> + reg = <0x1c>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller {
> };
> };
>
> - cpu29: cpu@29 {
> + cpu29: cpu@1d {
> compatible = "thead,c920", "riscv";
> - reg = <29>;
> + reg = <0x1d>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller {
> };
> };
>
> - cpu30: cpu@30 {
> + cpu30: cpu@1e {
> compatible = "thead,c920", "riscv";
> - reg = <30>;
> + reg = <0x1e>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller {
> };
> };
>
> - cpu31: cpu@31 {
> + cpu31: cpu@1f {
> compatible = "thead,c920", "riscv";
> - reg = <31>;
> + reg = <0x1f>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller {
> };
> };
>
> - cpu32: cpu@32 {
> + cpu32: cpu@20 {
> compatible = "thead,c920", "riscv";
> - reg = <32>;
> + reg = <0x20>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller {
> };
> };
>
> - cpu33: cpu@33 {
> + cpu33: cpu@21 {
> compatible = "thead,c920", "riscv";
> - reg = <33>;
> + reg = <0x21>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller {
> };
> };
>
> - cpu34: cpu@34 {
> + cpu34: cpu@22 {
> compatible = "thead,c920", "riscv";
> - reg = <34>;
> + reg = <0x22>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller {
> };
> };
>
> - cpu35: cpu@35 {
> + cpu35: cpu@23 {
> compatible = "thead,c920", "riscv";
> - reg = <35>;
> + reg = <0x23>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller {
> };
> };
>
> - cpu36: cpu@36 {
> + cpu36: cpu@24 {
> compatible = "thead,c920", "riscv";
> - reg = <36>;
> + reg = <0x24>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller {
> };
> };
>
> - cpu37: cpu@37 {
> + cpu37: cpu@25 {
> compatible = "thead,c920", "riscv";
> - reg = <37>;
> + reg = <0x25>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller {
> };
> };
>
> - cpu38: cpu@38 {
> + cpu38: cpu@26 {
> compatible = "thead,c920", "riscv";
> - reg = <38>;
> + reg = <0x26>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller {
> };
> };
>
> - cpu39: cpu@39 {
> + cpu39: cpu@27 {
> compatible = "thead,c920", "riscv";
> - reg = <39>;
> + reg = <0x27>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller {
> };
> };
>
> - cpu40: cpu@40 {
> + cpu40: cpu@28 {
> compatible = "thead,c920", "riscv";
> - reg = <40>;
> + reg = <0x28>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller {
> };
> };
>
> - cpu41: cpu@41 {
> + cpu41: cpu@29 {
> compatible = "thead,c920", "riscv";
> - reg = <41>;
> + reg = <0x29>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller {
> };
> };
>
> - cpu42: cpu@42 {
> + cpu42: cpu@2a {
> compatible = "thead,c920", "riscv";
> - reg = <42>;
> + reg = <0x2a>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller {
> };
> };
>
> - cpu43: cpu@43 {
> + cpu43: cpu@2b {
> compatible = "thead,c920", "riscv";
> - reg = <43>;
> + reg = <0x2b>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller {
> };
> };
>
> - cpu44: cpu@44 {
> + cpu44: cpu@2c {
> compatible = "thead,c920", "riscv";
> - reg = <44>;
> + reg = <0x2c>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller {
> };
> };
>
> - cpu45: cpu@45 {
> + cpu45: cpu@2d {
> compatible = "thead,c920", "riscv";
> - reg = <45>;
> + reg = <0x2d>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller {
> };
> };
>
> - cpu46: cpu@46 {
> + cpu46: cpu@2e {
> compatible = "thead,c920", "riscv";
> - reg = <46>;
> + reg = <0x2e>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller {
> };
> };
>
> - cpu47: cpu@47 {
> + cpu47: cpu@2f {
> compatible = "thead,c920", "riscv";
> - reg = <47>;
> + reg = <0x2f>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller {
> };
> };
>
> - cpu48: cpu@48 {
> + cpu48: cpu@30 {
> compatible = "thead,c920", "riscv";
> - reg = <48>;
> + reg = <0x30>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller {
> };
> };
>
> - cpu49: cpu@49 {
> + cpu49: cpu@31 {
> compatible = "thead,c920", "riscv";
> - reg = <49>;
> + reg = <0x31>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller {
> };
> };
>
> - cpu50: cpu@50 {
> + cpu50: cpu@32 {
> compatible = "thead,c920", "riscv";
> - reg = <50>;
> + reg = <0x32>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller {
> };
> };
>
> - cpu51: cpu@51 {
> + cpu51: cpu@33 {
> compatible = "thead,c920", "riscv";
> - reg = <51>;
> + reg = <0x33>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller {
> };
> };
>
> - cpu52: cpu@52 {
> + cpu52: cpu@34 {
> compatible = "thead,c920", "riscv";
> - reg = <52>;
> + reg = <0x34>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller {
> };
> };
>
> - cpu53: cpu@53 {
> + cpu53: cpu@35 {
> compatible = "thead,c920", "riscv";
> - reg = <53>;
> + reg = <0x35>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller {
> };
> };
>
> - cpu54: cpu@54 {
> + cpu54: cpu@36 {
> compatible = "thead,c920", "riscv";
> - reg = <54>;
> + reg = <0x36>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller {
> };
> };
>
> - cpu55: cpu@55 {
> + cpu55: cpu@37 {
> compatible = "thead,c920", "riscv";
> - reg = <55>;
> + reg = <0x37>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller {
> };
> };
>
> - cpu56: cpu@56 {
> + cpu56: cpu@38 {
> compatible = "thead,c920", "riscv";
> - reg = <56>;
> + reg = <0x38>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller {
> };
> };
>
> - cpu57: cpu@57 {
> + cpu57: cpu@39 {
> compatible = "thead,c920", "riscv";
> - reg = <57>;
> + reg = <0x39>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller {
> };
> };
>
> - cpu58: cpu@58 {
> + cpu58: cpu@3a {
> compatible = "thead,c920", "riscv";
> - reg = <58>;
> + reg = <0x3a>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller {
> };
> };
>
> - cpu59: cpu@59 {
> + cpu59: cpu@3b {
> compatible = "thead,c920", "riscv";
> - reg = <59>;
> + reg = <0x3b>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller {
> };
> };
>
> - cpu60: cpu@60 {
> + cpu60: cpu@3c {
> compatible = "thead,c920", "riscv";
> - reg = <60>;
> + reg = <0x3c>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller {
> };
> };
>
> - cpu61: cpu@61 {
> + cpu61: cpu@3d {
> compatible = "thead,c920", "riscv";
> - reg = <61>;
> + reg = <0x3d>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller {
> };
> };
>
> - cpu62: cpu@62 {
> + cpu62: cpu@3e {
> compatible = "thead,c920", "riscv";
> - reg = <62>;
> + reg = <0x3e>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> @@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller {
> };
> };
>
> - cpu63: cpu@63 {
> + cpu63: cpu@3f {
> compatible = "thead,c920", "riscv";
> - reg = <63>;
> + reg = <0x3f>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> i-cache-sets = <512>;
> --
> 2.53.0
>
--
Best Regards
Guo Ren
^ permalink raw reply
* Re: [PATCH v1 03/13] clk: starfive: Add system-0 domain PLL clock driver
From: Changhuang Liang @ 2026-04-07 1:17 UTC (permalink / raw)
To: Brian Masney
Cc: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Chen Wang,
Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer, Keguang Zhang,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Leyfoon Tan
In-Reply-To: <ac_mdhEl9VtpTuw8@redhat.com>
Hi, Brian
Thanks for the review.
> Hi Changhuang,
>
> On Thu, Apr 02, 2026 at 10:49:35PM -0700, Changhuang Liang wrote:
> > Add system-0 domain PLL clock driver for StarFive JHB100 SoC.
> >
> > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> > ---
> > drivers/clk/starfive/Kconfig | 8 +
> > drivers/clk/starfive/Makefile | 1 +
> > .../clk/starfive/clk-starfive-jhb100-pll.c | 498 ++++++++++++++++++
> > 3 files changed, 507 insertions(+)
> > create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.c
> >
> > diff --git a/drivers/clk/starfive/Kconfig
> > b/drivers/clk/starfive/Kconfig index c612f1ede7d7..cc712da68bd0 100644
> > --- a/drivers/clk/starfive/Kconfig
> > +++ b/drivers/clk/starfive/Kconfig
> > @@ -105,6 +105,14 @@ config CLK_STARFIVE_JHB100_PER3
> > Say yes here to support the peripheral-3 clock controller
> > on the StarFive JHB100 SoC.
> >
> > +config CLK_STARFIVE_JHB100_PLL
> > + bool "StarFive JHB100 PLL clock support"
> > + depends on ARCH_STARFIVE || COMPILE_TEST
> > + default ARCH_STARFIVE
> > + help
> > + Say yes here to support the PLL clock controller on the
> > + StarFive JHB100 SoC.
> > +
> > config CLK_STARFIVE_JHB100_SYS0
> > bool "StarFive JHB100 system-0 clock support"
> > depends on ARCH_STARFIVE || COMPILE_TEST diff --git
> > a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index
> > f00690f0cdad..547a8c170728 100644
> > --- a/drivers/clk/starfive/Makefile
> > +++ b/drivers/clk/starfive/Makefile
> > @@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0)
> += clk-starfive-jhb100-per0.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) +=
> clk-starfive-jhb100-per1.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) +=
> clk-starfive-jhb100-per2.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_PER3) +=
> clk-starfive-jhb100-per3.o
> > +obj-$(CONFIG_CLK_STARFIVE_JHB100_PLL) +=
> clk-starfive-jhb100-pll.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) +=
> clk-starfive-jhb100-sys0.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) +=
> clk-starfive-jhb100-sys1.o
> > obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) +=
> clk-starfive-jhb100-sys2.o
> > diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c
> > b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
> > new file mode 100644
> > index 000000000000..1751a734ee83
> > --- /dev/null
> > +++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
> > @@ -0,0 +1,498 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * StarFive JHB100 PLL Clock Generator Driver
> > + *
> > + * Copyright (C) 2024 StarFive Technology Co., Ltd.
> > + *
> > + * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
> > + */
> > +
> > +#include <linux/bits.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/debugfs.h>
> > +#include <linux/device.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +
> > +#include <dt-bindings/clock/starfive,jhb100-crg.h>
> > +
> > +/* this driver expects a 25MHz input frequency from the oscillator */
> > +#define JHB100_PLL_OSC_RATE 25000000UL
>
> You could include linux/units.h and then use: 25 * HZ_PER_MHZ
>
> > +
> > +/* System-0 domain PLL */
> > +#define JHB100_PLL2_OFFSET 0x00
> > +#define JHB100_PLL3_OFFSET 0x0c
> > +#define JHB100_PLL4_OFFSET 0x18
> > +#define JHB100_PLL5_OFFSET 0x24
> > +
> > +#define JHB100_PLL_CFG0_OFFSET 0x0
> > +#define JHB100_PLL_CFG1_OFFSET 0x4
> > +#define JHB100_PLL_CFG2_OFFSET 0x8
> > +
> > +#define JHB100_PLLX_CFG0(offset) ((offset) + JHB100_PLL_CFG0_OFFSET)
> > +/* fbdiv value should be 16 to 4095 */
> > +#define JHB100_PLL_FBDIV GENMASK(13, 2)
> > +#define JHB100_PLL_FBDIV_SHIFT 2
> > +#define JHB100_PLL_FOUTPOSTDIV_EN BIT(14)
> > +#define JHB100_PLL_FOUTPOSTDIV_EN_SHIFT 14
> > +#define JHB100_PLL_FOUTVCOP_EN BIT(16)
> > +#define JHB100_PLL_FOUTVCOP_EN_SHIFT 16
> > +
> > +#define JHB100_PLLX_CFG1(offset) ((offset) + JHB100_PLL_CFG1_OFFSET)
> > +/* frac value should be decimals multiplied by 2^24 */
> > +#define JHB100_PLL_FRAC GENMASK(23, 0)
> > +#define JHB100_PLL_FRAC_SHIFT 0
> > +#define JHB100_PLL_LOCK BIT(24)
> > +#define JHB100_PLL_LOCK_SHIFT 24
> > +
> > +#define JHB100_PLLX_CFG2(offset) ((offset) + JHB100_PLL_CFG2_OFFSET)
> > +#define JHB100_PLL_PD BIT(13)
> > +#define JHB100_PLL_PD_SHIFT 13
> > +#define JHB100_PLL_POSTDIV GENMASK(15, 14)
> > +#define JHB100_PLL_POSTDIV_SHIFT 14
> > +#define JHB100_PLL_REFDIV GENMASK(23, 18)
> > +#define JHB100_PLL_REFDIV_SHIFT 18
> > +
> > +#define JHB100_PLL_TIMEOUT_US 1000
> > +#define JHB100_PLL_INTERVAL_US 100
> > +
> > +struct jhb100_pll_preset {
> > + unsigned long freq;
> > + u32 frac; /* frac value should be decimals multiplied by 2^24
> */
> > + unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */
> > + unsigned refdiv : 6;
> > + unsigned postdiv : 2;
> > + unsigned foutpostdiv_en : 1;
> > + unsigned foutvcop_en : 1;
> > +};
> > +
> > +struct jhb100_pll_info {
> > + char *name;
> > + const struct jhb100_pll_preset *presets;
> > + unsigned int npresets;
> > + unsigned long flag;
> > + u8 offset;
> > + bool continuous;
> > +};
> > +
> > +#define _JHB100_PLL(_idx, _name, _presets, _npresets, _offset, _flag,
> _cont) \
> > + [_idx] = { \
> > + .name = _name, \
> > + .offset = _offset, \
> > + .presets = _presets, \
> > + .npresets = _npresets, \
> > + .flag = _flag, \
> > + .continuous = _cont, \
> > + }
> > +
> > +#define JHB100_PLL(idx, name, presets, npresets, offset, cont)
> \
> > + _JHB100_PLL(idx, name, presets, npresets, offset, 0, cont)
> > +
> > +struct jhb100_pll_match_data {
> > + const struct jhb100_pll_info *pll_info;
> > + int num_pll;
> > +};
> > +
> > +struct jhb100_pll_data {
> > + struct clk_hw hw;
> > + unsigned int idx;
> > +};
> > +
> > +struct jhb100_pll_priv {
> > + struct device *dev;
> > + struct regmap *regmap;
> > + const struct jhb100_pll_match_data *match_data;
> > + struct jhb100_pll_data pll[];
> > +};
> > +
> > +struct jhb100_pll_regvals {
> > + u32 fbdiv;
> > + u32 frac;
> > + u32 postdiv;
> > + u32 refdiv;
> > + bool foutpostdiv_en;
> > + bool foutvcop_en;
> > +};
> > +
> > +static struct jhb100_pll_data *jhb100_pll_data_from(struct clk_hw
> > +*hw) {
> > + return container_of(hw, struct jhb100_pll_data, hw); }
> > +
> > +static struct jhb100_pll_priv *jhb100_pll_priv_from(struct
> > +jhb100_pll_data *pll) {
> > + return container_of(pll, struct jhb100_pll_priv, pll[pll->idx]); }
> > +
> > +static int jhb100_pll_enable(struct clk_hw *hw) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> > +&priv->match_data->pll_info[pll->idx];
> > +
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
> > + JHB100_PLL_PD, 0);
>
> Should the return value be checked here? Or just:
>
> return regumap_update_bits(...);
>
> > +
> > + return 0;
> > +}
> > +
> > +static void jhb100_pll_disable(struct clk_hw *hw) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> > +&priv->match_data->pll_info[pll->idx];
> > +
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
> > + JHB100_PLL_PD, BIT(JHB100_PLL_PD_SHIFT)); }
> > +
> > +static int jhb100_pll_is_enabled(struct clk_hw *hw) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> &priv->match_data->pll_info[pll->idx];
> > + u32 val;
> > +
> > + regmap_read(priv->regmap, JHB100_PLLX_CFG2(info->offset), &val);
>
> Should the return value be checked?
>
> > +
> > + return !(val & JHB100_PLL_PD);
>
> If regmap_read() returns an error, then is val uninitialized?
>
> > +}
> > +
> > +static void jhb100_pll_regvals_get(struct regmap *regmap,
> > + const struct jhb100_pll_info *info,
> > + struct jhb100_pll_regvals *ret) {
> > + u32 val;
> > +
> > + regmap_read(regmap, JHB100_PLLX_CFG0(info->offset), &val);
> > + ret->fbdiv = (val & JHB100_PLL_FBDIV) >> JHB100_PLL_FBDIV_SHIFT;
> > + ret->foutpostdiv_en = !!((val & JHB100_PLL_FOUTPOSTDIV_EN) >>
> > + JHB100_PLL_FOUTPOSTDIV_EN_SHIFT);
> > + ret->foutvcop_en = !!((val & JHB100_PLL_FOUTVCOP_EN) >>
> > + JHB100_PLL_FOUTVCOP_EN_SHIFT);
> > +
> > + regmap_read(regmap, JHB100_PLLX_CFG1(info->offset), &val);
> > + ret->frac = (val & JHB100_PLL_FRAC) >> JHB100_PLL_FRAC_SHIFT;
> > +
> > + regmap_read(regmap, JHB100_PLLX_CFG2(info->offset), &val);
> > + ret->postdiv = (val & JHB100_PLL_POSTDIV) >>
> JHB100_PLL_POSTDIV_SHIFT;
> > + ret->refdiv = (val & JHB100_PLL_REFDIV) >> JHB100_PLL_REFDIV_SHIFT;
>
> Should these regmap return values be checked, and the error code returned?
>
> > +}
> > +
> > +static unsigned long jhb100_pll_recalc_rate(struct clk_hw *hw,
> > +unsigned long parent_rate) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + struct jhb100_pll_regvals val;
> > + unsigned long rate;
> > + u32 power = 0;
> > +
> > + jhb100_pll_regvals_get(priv->regmap,
> > +&priv->match_data->pll_info[pll->idx], &val);
> > +
> > + /*
> > + *
> > + * if (foutvcop_en)
> > + * rate = parent * (fbdiv + frac / 2^24) / refdiv
> > + *
> > + * if (foutpostdiv_en)
> > + * rate = parent * (fbdiv + frac / 2^24) / refdiv / 2^(postdiv + 1)
> > + *
> > + * parent * (fbdiv + frac / 2^24) = parent * fbdiv + parent * frac / 2^24
> > + */
> > +
> > + if (!!val.foutvcop_en == !!val.foutpostdiv_en)
> > + return 0;
> > +
> > + rate = (parent_rate * val.frac) >> 24;
> > +
> > + if (val.foutpostdiv_en)
> > + power = val.postdiv + 1;
> > +
> > + rate += parent_rate * val.fbdiv;
> > + rate /= val.refdiv << power;
>
> Could val.refdiv ever be zero?
Will check it at next version.
> > +
> > + return rate;
> > +}
> > +
> > +static int jhb100_pll_determine_rate(struct clk_hw *hw, struct
> > +clk_rate_request *req) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> &priv->match_data->pll_info[pll->idx];
> > + const struct jhb100_pll_preset *selected = &info->presets[0];
> > + unsigned int idx;
> > +
> > + /* if the parent rate doesn't match our expectations the presets won't
> work */
> > + if (req->best_parent_rate != JHB100_PLL_OSC_RATE) {
> > + req->rate = jhb100_pll_recalc_rate(hw, req->best_parent_rate);
> > + return 0;
> > + }
> > +
> > + /* continuous means support any rate */
> > + if (info->continuous)
> > + return 0;
> > +
> > + /* find highest rate lower or equal to the requested rate */
> > + for (idx = 1; idx < info->npresets; idx++) {
> > + const struct jhb100_pll_preset *val = &info->presets[idx];
> > +
> > + if (req->rate < val->freq)
> > + break;
> > +
> > + selected = val;
> > + }
> > +
> > + req->rate = selected->freq;
> > +
> > + return 0;
> > +}
> > +
> > +static int jhb100_pll_set_preset(struct clk_hw *hw, struct
> > +jhb100_pll_preset *val) {
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> &priv->match_data->pll_info[pll->idx];
> > + unsigned int value;
> > +
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG0(info->offset),
> JHB100_PLL_FBDIV,
> > + (u32)val->fbdiv << JHB100_PLL_FBDIV_SHIFT);
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG0(info->offset),
> JHB100_PLL_FOUTPOSTDIV_EN,
> > + (u32)val->foutpostdiv_en <<
> JHB100_PLL_FOUTPOSTDIV_EN_SHIFT);
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG0(info->offset),
> JHB100_PLL_FOUTVCOP_EN,
> > + (u32)val->foutvcop_en <<
> JHB100_PLL_FOUTVCOP_EN_SHIFT);
>
> These are writing to the same register. Should the values be combined into
> one, and written once to the register?
>
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG1(info->offset),
> JHB100_PLL_FRAC,
> > + val->frac << JHB100_PLL_FRAC_SHIFT);
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
> JHB100_PLL_REFDIV,
> > + (u32)val->refdiv << JHB100_PLL_REFDIV_SHIFT);
> > + regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
> JHB100_PLL_POSTDIV,
> > + (u32)val->postdiv << JHB100_PLL_POSTDIV_SHIFT);
>
> The last two calls to JHB100_PLLX_CFG2 also write to the same register.
> Should the two writes be combined into one?
>
> Should the return values from regmap_update_bits() be checked?
>
> > +
> > + /* waiting for PLL to lock */
> > + return regmap_read_poll_timeout_atomic(priv->regmap,
> JHB100_PLLX_CFG1(info->offset),
> > + value, value & JHB100_PLL_LOCK,
> > + JHB100_PLL_INTERVAL_US,
> > + JHB100_PLL_TIMEOUT_US);
> > +}
> > +
> > +static int jhb100_pll_rate_to_preset(struct clk_hw *hw, unsigned long rate,
> > + unsigned long parent_rate)
> > +{
> > + struct jhb100_pll_preset val = {
> > + .refdiv = 1,
> > + .postdiv = 3,
> > + .foutpostdiv_en = 1,
> > + .foutvcop_en = 0,
> > + };
> > + unsigned int power = 0;
> > + unsigned long fbdiv_24, t;
> > +
> > + if (val.foutpostdiv_en)
> > + power = val.postdiv + 1;
> > +
> > + t = val.refdiv << power;
> > + t *= rate;
> > +
> > + val.fbdiv = t / parent_rate;
>
> Should a check for parent_rate == 0 be added?
parent_rate is checked in jhb100_pll_set_rate, and it only supports 25M.
> > +
> > + fbdiv_24 = (t << 24) / parent_rate;
> > + val.frac = fbdiv_24 - (val.fbdiv << 24);
> > +
> > + return jhb100_pll_set_preset(hw, &val); }
> > +
> > +static int jhb100_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long parent_rate)
> > +{
> > + struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
> > + struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
> > + const struct jhb100_pll_info *info =
> &priv->match_data->pll_info[pll->idx];
> > + const struct jhb100_pll_preset *val;
> > + unsigned int idx;
> > +
> > + /* if the parent rate doesn't match our expectations the presets won't
> work */
> > + if (parent_rate != JHB100_PLL_OSC_RATE)
> > + return -EINVAL;
> > +
> > + if (info->continuous)
> > + return jhb100_pll_rate_to_preset(hw, rate, parent_rate);
> > +
> > + for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) {
> > + if (val->freq == rate)
> > + return jhb100_pll_set_preset(hw, (struct jhb100_pll_preset
> *)val);
>
> The cast looks to be here because of the const in jhb100_pll_set_preset(). Can
> const be added to the declaration of jhb100_pll_set_preset()?
Will try it.
Best Regards,
Changhuang
^ permalink raw reply
* Re: [PATCH v1 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT
From: Changhuang Liang @ 2026-04-07 0:52 UTC (permalink / raw)
To: Conor Dooley
Cc: Emil Renner Berthing, Joel Stanley, Drew Fustini,
Darshan Prajapati, linux-riscv@lists.infradead.org, Rob Herring,
Alexandre Ghiti, Anup Patel, Hal Feng, Guodong Xu, Yixun Lan,
Heinrich Schuchardt, devicetree@vger.kernel.org, Conor Dooley,
Albert Ou, E Shattow, Leyfoon Tan, Junhui Liu, Daniel Lezcano,
Michal Simek, Paul Walmsley, linux-kernel@vger.kernel.org,
Samuel Holland, Michael Zhu, Palmer Dabbelt, Thomas Gleixner,
JiSheng Teoh, Krzysztof Kozlowski
In-Reply-To: <20260403-pristine-slam-71d8e0093b6f@spud>
Hi, Conor
Thanks for the review.
> On Fri, Apr 03, 2026 at 03:06:23AM +0000, Changhuang Liang wrote:
> > Hi, Conor
> >
> > > On Thu, Apr 02, 2026 at 01:40:19AM -0700, Changhuang Liang wrote:
> > > > From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > > >
> > > > Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT,
> > > > PLIC, PMU, UART and 1GB DDR.
> > > >
> > > > Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > > > Signed-off-by: Changhuang Liang
> > > > <changhuang.liang@starfivetech.com>
> > > > ---
> > > > MAINTAINERS | 6 +
> > > > arch/riscv/boot/dts/starfive/Makefile | 2 +
> > > > .../boot/dts/starfive/jhb100-evb1-eth.dts | 6 +
> > > > arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi | 32 ++
> > > > arch/riscv/boot/dts/starfive/jhb100.dtsi | 326
> > > ++++++++++++++++++
> > > > 5 files changed, 372 insertions(+) create mode 100644
> > > > arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > > create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> > > > create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
> > > >
> > > > diff --git a/MAINTAINERS b/MAINTAINERS index
> > > > 7d10988cbc62..b1892a480c31 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -25306,6 +25306,12 @@ S: Supported
> > > > F:
> > >
> > > Documentation/devicetree/bindings/interrupt-controller/starfive,jh81
> > > 00
> > > -intc.yaml
> > > > F: drivers/irqchip/irq-starfive-jh8100-intc.c
> > > >
> > > > +STARFIVE JHB100 DEVICETREES
> > > > +M: Changhuang Liang <changhuang.liang@starfivetech.com>
> > > > +L: linux-riscv@lists.infradead.org
> > > > +S: Maintained
> > >
> > > Supported, no?
> > >
> > > > +F: arch/riscv/boot/dts/starfive/jhb100*
> > > > +
> > > > STATIC BRANCH/CALL
> > > > M: Peter Zijlstra <peterz@infradead.org>
> > > > M: Josh Poimboeuf <jpoimboe@kernel.org>
> > > > diff --git a/arch/riscv/boot/dts/starfive/Makefile
> > > > b/arch/riscv/boot/dts/starfive/Makefile
> > > > index 3dd1f05283f7..7cdb75788053 100644
> > > > --- a/arch/riscv/boot/dts/starfive/Makefile
> > > > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > > > @@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > > jh7110-starfive-visionfive-2-lite.dtb
> > > > dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > > jh7110-starfive-visionfive-2-lite-emmc.dtb
> > > > dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > > jh7110-starfive-visionfive-2-v1.2a.dtb
> > > > dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > > jh7110-starfive-visionfive-2-v1.3b.dtb
> > > > +
> > > > +dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1-eth.dtb
> > > > diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > > b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > > new file mode 100644
> > > > index 000000000000..62cd046e1224
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > > @@ -0,0 +1,6 @@
> > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > > +/*
> > > > + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> > > > + */
> > > > +
> > > > +#include "jhb100-evb1.dtsi"
> > >
> > > What is the point of this file? Is this the base-board?
> > > Shouldn't it have a specific compatible?
> > >
> > > Can the SoM be used without a base board? I've got no info about
> > > this board appearing on google, do you even have pictures of it or any
> documentation?
> > > I see this
> > >
> https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=22
> > > and
> > >
> https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=23
> > > but the former doesn't look like it needs a base-board and the
> > > latter is called "evb3", so is not what's here?
> >
> > The former is the base board of the EVB1. Currently, we are only
> > carrying out upstream work based on the EVB1. The EVB1 base board has
> > reserved slots
>
> Except when I look at the first link, the picture doesn't show something that is
> a SoM + base-board, it's just a regular board. If that's the case, the breakdown
> of files doesn't make sense, with jhb100-evb1.dtsi sounding like it should be a
> dts. Usually we talk about base-boards in relation to a SoM, like what the
> mars-cm needs to function.
>
>
>
> > that can accommodate expansion boards to verify more advanced features.
> > At present, the jhb100-evb1.dtsi file corresponds to the configuration
> > of the
> > EVB1 base board. In the future, we will add dtsi files for the expansion
> boards.
> > The jhb100-evb1-eth.dts file will then be used to combine these dtsi
> > files to generate the final version of the device tree source.
>
> Sounds like here the evb1 is a complete board and jhb100-evb1-eth.dts
> represents some kind of expansion card added to that board?
> I think this not correct, since the base-board needs to be usable in isolation.
> Take a look at what rockchip do for rk3588-rock-5b-pcie-ep in
> arch/arm64/boot/dts/rockchip/Makefile/, where these expansion type things
> are dealt with using overlays.
This means a lot to me. Will change it to jhb100-evb.dts
Best Regards,
Changhuang
^ permalink raw reply
* Re: [PATCh v3 06/14] ASoC: rsnd: Add RZ/G3E DMA address calculation support
From: Kuninori Morimoto @ 2026-04-07 0:44 UTC (permalink / raw)
To: John Madieu
Cc: Mark Brown, Liam Girdwood, Geert Uytterhoeven, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
Magnus Damm, Philipp Zabel, Claudiu Beznea, Biju Das, john.madieu,
linux-sound, linux-renesas-soc, devicetree, linux-kernel
In-Reply-To: <20260402162436.12059-7-john.madieu.xa@bp.renesas.com>
Hi John, again
> RZ/G3E has different DMA register base addresses and offset
> calculations compared to R-Car platforms.
>
> Add dedicated rsnd_rzg3e_dma_addr() function with dispatch from
> rsnd_dma_addr(), following the existing per-generation pattern.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
(snip)
> +struct rsnd_dma_addr {
> + dma_addr_t out_addr;
> + dma_addr_t in_addr;
> +};
> +
> static dma_addr_t
> -rsnd_gen2_dma_addr(struct rsnd_dai_stream *io,
> - struct rsnd_mod *mod,
> - int is_play, int is_from)
> +rsnd_dma_addr_lookup(struct rsnd_dai_stream *io,
> + struct rsnd_mod *mod,
> + const struct rsnd_dma_addr tbl[3][2][3],
> + int is_play, int is_from)
Here, it is using raw [3][2][3] array as param.
I think it is good timing to create new struct for it, and use its pointer ?
Something like...
struct rsnd_dma_addr {
dma_addr_t out_addr;
dma_addr_t in_addr;
};
struct rsnd_dma_addr_dir {
struct rsnd_dma_addr capture[3];
struct rsnd_dma_addr platback[3];
};
struct rsnd_dma_addr_map {
struct rsnd_dma_addr_dir src;
struct rsnd_dma_addr_dri ssi;
struct rsnd_dma_addr_dir ssui;
};
> - } dma_addrs[3][2][3] = {
> + const struct rsnd_dma_addr tbl[3][2][3] = {
> + /* SRC */
> + /* Capture */
> + {{{ 0, 0, },
> + { RDMA_SRC_O_N_G3E(src, id), RDMA_SRC_I_P_G3E(src, id) },
> + { RDMA_CMD_O_N_G3E(src, id), RDMA_SRC_I_P_G3E(src, id) } },
> + /* Playback */
> + {{ 0, 0 },
> + { RDMA_SRC_O_P_G3E(src, id), RDMA_SRC_I_N_G3E(src, id) },
> + { RDMA_CMD_O_P_G3E(src, id), RDMA_SRC_I_N_G3E(src, id) } }
> + },
> + /* SSI */
> + /* Capture */
> + {{{ RDMA_SSI_O_N_G3E(ssi, id), 0 },
> + { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 },
> + { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 } },
> + /* Playback */
> + {{ 0, RDMA_SSI_I_N_G3E(ssi, id) },
> + { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) },
> + { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) } }
> + },
> + /* SSIU */
> + /* Capture */
> + {{{ RDMA_SSIU_O_N_G3E(ssi, id, busif), 0 },
> + { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 },
> + { RDMA_SSIU_O_P_G3E(ssi, id, busif), 0 } },
> + /* Playback */
> + {{ 0, RDMA_SSIU_I_N_G3E(ssi, id, busif) },
> + { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) },
> + { 0, RDMA_SSIU_I_P_G3E(ssi, id, busif) } } },
> + };
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* Re: [PATCH] dt-bindings: display/msm: move DSI PHY bindings to phy/ subdir
From: Dmitry Baryshkov @ 2026-04-06 23:42 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong,
Krishna Manikandan, Jonathan Marek, Dmitry Baryshkov
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-phy
In-Reply-To: <20260305-msm-dsi-phy-v1-1-0a99ac665995@oss.qualcomm.com>
On Thu, 05 Mar 2026 01:47:12 +0200, Dmitry Baryshkov wrote:
> Historically DSI PHY bindings landed to the display/msm subdir, however
> they describe PHYs and as such they should be in the phy/ subdir.
> Follow the example of other Qualcomm display-related PHYs (HDMI, eDP)
> and move bindings for the Qualcomm DSI PHYs to the correct subdir.
Applied to msm-next, thanks!
[1/1] dt-bindings: display/msm: move DSI PHY bindings to phy/ subdir
https://gitlab.freedesktop.org/lumag/msm/-/commit/f94aa7e9cf68
Best regards,
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 3/3] ASoC: renesas: fsi: Fix hang by enabling SPU clock
From: Kuninori Morimoto @ 2026-04-06 23:31 UTC (permalink / raw)
To: Bui Duc Phuc
Cc: broonie, lgirdwood, robh, krzk+dt, conor+dt, geert+renesas,
magnus.damm, perex, tiwai, linux-sound, linux-renesas-soc,
devicetree, linux-kernel
In-Reply-To: <CAABR9nGUyTkDmB0SgKAuM1Pp75L=m1q4bLSfhobm98TswDnt8w@mail.gmail.com>
Hi Bui
> Yes, enabling this clock is essential as it functions as a bus bridge clock.
> Currently, the SPU clock is still enabled by the bootloader. In legacy
> kernels (v4.2 and earlier) using the Armadillo board-file/defconfig, this
> clock remained active after boot, allowing the FSI to function correctly.
> However, after migrating to a full Device Tree (DTS) implementation,
> the kernel's unused clock cleanup mechanism disables the SPU clock
> because it isn't explicitly claimed. This leads to a system hang every
> time aplay is executed, as the FSI registers become inaccessible
> without this clock.
Thank you for clarify the situation.
I didn't notice about this.
> I previously attempted to manage the clock within fsi_hw_startup/
> shutdown, but the system would hang when stopping aplay
> (e.g., via Ctrl+C). This happens because certain cleanup operations,
> such as fsi_irq_disable(), are performed after fsi_hw_shutdown()
> finishes. These operations require register access, which triggers a
> system hang if the SPU clock has already been disabled. Therefore,
> I moved the clock management to fsi_dai_startup/shutdown to ensure
> the clock remains active throughout the entire lifecycle of the stream.
Hmm ?
fsi_irq_disable() is called after fsi_hw_shutdown() ??
Ah... is it because PIO transfer ?
I have 100% forgotten, but FSI doesn't support RX DMA...
Hmm... fsi_dai_trigger() seems strange.
It seems (A) stops clock, and (B) sets register after that.
Is this the reason why you get error ? I think (A) and (B) should be
reversed. The balance between SNDRV_PCM_TRIGGER_START, and with
__fsi_suspend() are also not good.
If so, can you use hw_start/stop() ?
static int fsi_dai_trigger(...)
{
...
switch (cmd) {
...
case SNDRV_PCM_TRIGGER_STOP:
if (!ret)
(A) ret = fsi_hw_shutdown(fsi, dev);
(B) fsi_stream_stop(fsi, io);
(C) fsi_stream_quit(fsi, io);
break;
}
...
}
> Furthermore, my testing shows that using dai_startup/shutdown
> eliminates the need for explicit Suspend/Resume handling for this clock.
> Since the ALSA framework typically invokes the hw_ callbacks during
> power management transitions rather than the dai_ ones, the SPU clock
> state remains stable, preventing any illegal register access during
> these transitions.
Basically, concept of this driver is that power/clock is enabled/disabled
when trigger() was called (except suspend/resume).
While your testing may be correct from an ALSA point of view, but setting
configuring it in multiple places will lead to confusion.
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* [PATCH 2/2] riscv: dts: sophgo: sg2042: use hex for CPU unit address
From: Inochi Amaoto @ 2026-04-06 23:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Han Gao, Nutty Liu, Guodong Xu, Guo Ren,
Xiaoguang Xing
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
In-Reply-To: <20260406232655.144043-1-inochiama@gmail.com>
Previous the CPU unit address cpu of sg2042 use decimal, it is
not following the general convention for unit addresses of the
OF. Convent the unit address to hex to resolve this problem.
The introduces a small ABI break for the CPU id, but it should
affect nothing since there is no direct full-path reference to
these CPU nodes.
Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/
---
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++----------
1 file changed, 118 insertions(+), 118 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index 509488eee432..fd8906b313d2 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -263,7 +263,7 @@ cpu0: cpu@0 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <0>;
+ reg = <0x0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -291,7 +291,7 @@ cpu1: cpu@1 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <1>;
+ reg = <0x1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -319,7 +319,7 @@ cpu2: cpu@2 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <2>;
+ reg = <0x2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -347,7 +347,7 @@ cpu3: cpu@3 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <3>;
+ reg = <0x3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -375,7 +375,7 @@ cpu4: cpu@4 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <4>;
+ reg = <0x4>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -403,7 +403,7 @@ cpu5: cpu@5 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <5>;
+ reg = <0x5>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -431,7 +431,7 @@ cpu6: cpu@6 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <6>;
+ reg = <0x6>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -459,7 +459,7 @@ cpu7: cpu@7 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <7>;
+ reg = <0x7>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -487,7 +487,7 @@ cpu8: cpu@8 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <8>;
+ reg = <0x8>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -515,7 +515,7 @@ cpu9: cpu@9 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <9>;
+ reg = <0x9>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller {
};
};
- cpu10: cpu@10 {
+ cpu10: cpu@a {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -543,7 +543,7 @@ cpu10: cpu@10 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <10>;
+ reg = <0xa>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller {
};
};
- cpu11: cpu@11 {
+ cpu11: cpu@b {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -571,7 +571,7 @@ cpu11: cpu@11 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <11>;
+ reg = <0xb>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller {
};
};
- cpu12: cpu@12 {
+ cpu12: cpu@c {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -599,7 +599,7 @@ cpu12: cpu@12 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <12>;
+ reg = <0xc>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller {
};
};
- cpu13: cpu@13 {
+ cpu13: cpu@d {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -627,7 +627,7 @@ cpu13: cpu@13 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <13>;
+ reg = <0xd>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller {
};
};
- cpu14: cpu@14 {
+ cpu14: cpu@e {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -655,7 +655,7 @@ cpu14: cpu@14 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <14>;
+ reg = <0xe>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller {
};
};
- cpu15: cpu@15 {
+ cpu15: cpu@f {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -683,7 +683,7 @@ cpu15: cpu@15 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <15>;
+ reg = <0xf>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller {
};
};
- cpu16: cpu@16 {
+ cpu16: cpu@10 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -711,7 +711,7 @@ cpu16: cpu@16 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <16>;
+ reg = <0x10>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller {
};
};
- cpu17: cpu@17 {
+ cpu17: cpu@11 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -739,7 +739,7 @@ cpu17: cpu@17 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <17>;
+ reg = <0x11>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller {
};
};
- cpu18: cpu@18 {
+ cpu18: cpu@12 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -767,7 +767,7 @@ cpu18: cpu@18 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <18>;
+ reg = <0x12>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller {
};
};
- cpu19: cpu@19 {
+ cpu19: cpu@13 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -795,7 +795,7 @@ cpu19: cpu@19 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <19>;
+ reg = <0x13>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller {
};
};
- cpu20: cpu@20 {
+ cpu20: cpu@14 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -823,7 +823,7 @@ cpu20: cpu@20 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <20>;
+ reg = <0x14>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller {
};
};
- cpu21: cpu@21 {
+ cpu21: cpu@15 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -851,7 +851,7 @@ cpu21: cpu@21 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <21>;
+ reg = <0x15>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller {
};
};
- cpu22: cpu@22 {
+ cpu22: cpu@16 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -879,7 +879,7 @@ cpu22: cpu@22 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <22>;
+ reg = <0x16>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller {
};
};
- cpu23: cpu@23 {
+ cpu23: cpu@17 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -907,7 +907,7 @@ cpu23: cpu@23 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <23>;
+ reg = <0x17>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller {
};
};
- cpu24: cpu@24 {
+ cpu24: cpu@18 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -935,7 +935,7 @@ cpu24: cpu@24 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <24>;
+ reg = <0x18>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller {
};
};
- cpu25: cpu@25 {
+ cpu25: cpu@19 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -963,7 +963,7 @@ cpu25: cpu@25 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <25>;
+ reg = <0x19>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller {
};
};
- cpu26: cpu@26 {
+ cpu26: cpu@1a {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -991,7 +991,7 @@ cpu26: cpu@26 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <26>;
+ reg = <0x1a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller {
};
};
- cpu27: cpu@27 {
+ cpu27: cpu@1b {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1019,7 +1019,7 @@ cpu27: cpu@27 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <27>;
+ reg = <0x1b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller {
};
};
- cpu28: cpu@28 {
+ cpu28: cpu@1c {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1047,7 +1047,7 @@ cpu28: cpu@28 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <28>;
+ reg = <0x1c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller {
};
};
- cpu29: cpu@29 {
+ cpu29: cpu@1d {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1075,7 +1075,7 @@ cpu29: cpu@29 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <29>;
+ reg = <0x1d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller {
};
};
- cpu30: cpu@30 {
+ cpu30: cpu@1e {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1103,7 +1103,7 @@ cpu30: cpu@30 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <30>;
+ reg = <0x1e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller {
};
};
- cpu31: cpu@31 {
+ cpu31: cpu@1f {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1131,7 +1131,7 @@ cpu31: cpu@31 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <31>;
+ reg = <0x1f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller {
};
};
- cpu32: cpu@32 {
+ cpu32: cpu@20 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1159,7 +1159,7 @@ cpu32: cpu@32 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <32>;
+ reg = <0x20>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller {
};
};
- cpu33: cpu@33 {
+ cpu33: cpu@21 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1187,7 +1187,7 @@ cpu33: cpu@33 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <33>;
+ reg = <0x21>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller {
};
};
- cpu34: cpu@34 {
+ cpu34: cpu@22 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1215,7 +1215,7 @@ cpu34: cpu@34 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <34>;
+ reg = <0x22>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller {
};
};
- cpu35: cpu@35 {
+ cpu35: cpu@23 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1243,7 +1243,7 @@ cpu35: cpu@35 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <35>;
+ reg = <0x23>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller {
};
};
- cpu36: cpu@36 {
+ cpu36: cpu@24 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1271,7 +1271,7 @@ cpu36: cpu@36 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <36>;
+ reg = <0x24>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller {
};
};
- cpu37: cpu@37 {
+ cpu37: cpu@25 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1299,7 +1299,7 @@ cpu37: cpu@37 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <37>;
+ reg = <0x25>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller {
};
};
- cpu38: cpu@38 {
+ cpu38: cpu@26 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1327,7 +1327,7 @@ cpu38: cpu@38 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <38>;
+ reg = <0x26>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller {
};
};
- cpu39: cpu@39 {
+ cpu39: cpu@27 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1355,7 +1355,7 @@ cpu39: cpu@39 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <39>;
+ reg = <0x27>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller {
};
};
- cpu40: cpu@40 {
+ cpu40: cpu@28 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1383,7 +1383,7 @@ cpu40: cpu@40 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <40>;
+ reg = <0x28>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller {
};
};
- cpu41: cpu@41 {
+ cpu41: cpu@29 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1411,7 +1411,7 @@ cpu41: cpu@41 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <41>;
+ reg = <0x29>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller {
};
};
- cpu42: cpu@42 {
+ cpu42: cpu@2a {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1439,7 +1439,7 @@ cpu42: cpu@42 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <42>;
+ reg = <0x2a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller {
};
};
- cpu43: cpu@43 {
+ cpu43: cpu@2b {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1467,7 +1467,7 @@ cpu43: cpu@43 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <43>;
+ reg = <0x2b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller {
};
};
- cpu44: cpu@44 {
+ cpu44: cpu@2c {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1495,7 +1495,7 @@ cpu44: cpu@44 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <44>;
+ reg = <0x2c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller {
};
};
- cpu45: cpu@45 {
+ cpu45: cpu@2d {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1523,7 +1523,7 @@ cpu45: cpu@45 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <45>;
+ reg = <0x2d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller {
};
};
- cpu46: cpu@46 {
+ cpu46: cpu@2e {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1551,7 +1551,7 @@ cpu46: cpu@46 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <46>;
+ reg = <0x2e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller {
};
};
- cpu47: cpu@47 {
+ cpu47: cpu@2f {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1579,7 +1579,7 @@ cpu47: cpu@47 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <47>;
+ reg = <0x2f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller {
};
};
- cpu48: cpu@48 {
+ cpu48: cpu@30 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1607,7 +1607,7 @@ cpu48: cpu@48 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <48>;
+ reg = <0x30>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller {
};
};
- cpu49: cpu@49 {
+ cpu49: cpu@31 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1635,7 +1635,7 @@ cpu49: cpu@49 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <49>;
+ reg = <0x31>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller {
};
};
- cpu50: cpu@50 {
+ cpu50: cpu@32 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1663,7 +1663,7 @@ cpu50: cpu@50 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <50>;
+ reg = <0x32>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller {
};
};
- cpu51: cpu@51 {
+ cpu51: cpu@33 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1691,7 +1691,7 @@ cpu51: cpu@51 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <51>;
+ reg = <0x33>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller {
};
};
- cpu52: cpu@52 {
+ cpu52: cpu@34 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1719,7 +1719,7 @@ cpu52: cpu@52 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <52>;
+ reg = <0x34>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller {
};
};
- cpu53: cpu@53 {
+ cpu53: cpu@35 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1747,7 +1747,7 @@ cpu53: cpu@53 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <53>;
+ reg = <0x35>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller {
};
};
- cpu54: cpu@54 {
+ cpu54: cpu@36 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1775,7 +1775,7 @@ cpu54: cpu@54 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <54>;
+ reg = <0x36>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller {
};
};
- cpu55: cpu@55 {
+ cpu55: cpu@37 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1803,7 +1803,7 @@ cpu55: cpu@55 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <55>;
+ reg = <0x37>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller {
};
};
- cpu56: cpu@56 {
+ cpu56: cpu@38 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1831,7 +1831,7 @@ cpu56: cpu@56 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <56>;
+ reg = <0x38>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller {
};
};
- cpu57: cpu@57 {
+ cpu57: cpu@39 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1859,7 +1859,7 @@ cpu57: cpu@57 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <57>;
+ reg = <0x39>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller {
};
};
- cpu58: cpu@58 {
+ cpu58: cpu@3a {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1887,7 +1887,7 @@ cpu58: cpu@58 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <58>;
+ reg = <0x3a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller {
};
};
- cpu59: cpu@59 {
+ cpu59: cpu@3b {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1915,7 +1915,7 @@ cpu59: cpu@59 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <59>;
+ reg = <0x3b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller {
};
};
- cpu60: cpu@60 {
+ cpu60: cpu@3c {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1943,7 +1943,7 @@ cpu60: cpu@60 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <60>;
+ reg = <0x3c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller {
};
};
- cpu61: cpu@61 {
+ cpu61: cpu@3d {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1971,7 +1971,7 @@ cpu61: cpu@61 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <61>;
+ reg = <0x3d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller {
};
};
- cpu62: cpu@62 {
+ cpu62: cpu@3e {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -1999,7 +1999,7 @@ cpu62: cpu@62 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <62>;
+ reg = <0x3e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller {
};
};
- cpu63: cpu@63 {
+ cpu63: cpu@3f {
compatible = "thead,c920", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
@@ -2027,7 +2027,7 @@ cpu63: cpu@63 {
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
- reg = <63>;
+ reg = <0x3f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
--
2.53.0
^ permalink raw reply related
* [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address
From: Inochi Amaoto @ 2026-04-06 23:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Han Gao, Nutty Liu, Guodong Xu, Guo Ren,
Xiaoguang Xing
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
In-Reply-To: <20260406232655.144043-1-inochiama@gmail.com>
Previous the CPU unit address cpu of sg2044 use decimal, it is
not following the general convention for unit addresses of the
OF. Convent the unit address to hex to resolve this problem.
The introduces a small ABI break for the CPU id, but it should
affect nothing since there is no direct full-path reference to
these CPU nodes.
Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/
---
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++----------
1 file changed, 118 insertions(+), 118 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
index 3135409c2149..f66a382c95bd 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
@@ -14,7 +14,7 @@ cpus {
cpu0: cpu@0 {
compatible = "thead,c920", "riscv";
- reg = <0>;
+ reg = <0x0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller {
cpu1: cpu@1 {
compatible = "thead,c920", "riscv";
- reg = <1>;
+ reg = <0x1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller {
cpu2: cpu@2 {
compatible = "thead,c920", "riscv";
- reg = <2>;
+ reg = <0x2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller {
cpu3: cpu@3 {
compatible = "thead,c920", "riscv";
- reg = <3>;
+ reg = <0x3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller {
cpu4: cpu@4 {
compatible = "thead,c920", "riscv";
- reg = <4>;
+ reg = <0x4>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller {
cpu5: cpu@5 {
compatible = "thead,c920", "riscv";
- reg = <5>;
+ reg = <0x5>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller {
cpu6: cpu@6 {
compatible = "thead,c920", "riscv";
- reg = <6>;
+ reg = <0x6>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller {
cpu7: cpu@7 {
compatible = "thead,c920", "riscv";
- reg = <7>;
+ reg = <0x7>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller {
cpu8: cpu@8 {
compatible = "thead,c920", "riscv";
- reg = <8>;
+ reg = <0x8>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller {
cpu9: cpu@9 {
compatible = "thead,c920", "riscv";
- reg = <9>;
+ reg = <0x9>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller {
};
};
- cpu10: cpu@10 {
+ cpu10: cpu@a {
compatible = "thead,c920", "riscv";
- reg = <10>;
+ reg = <0xa>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller {
};
};
- cpu11: cpu@11 {
+ cpu11: cpu@b {
compatible = "thead,c920", "riscv";
- reg = <11>;
+ reg = <0xb>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller {
};
};
- cpu12: cpu@12 {
+ cpu12: cpu@c {
compatible = "thead,c920", "riscv";
- reg = <12>;
+ reg = <0xc>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller {
};
};
- cpu13: cpu@13 {
+ cpu13: cpu@d {
compatible = "thead,c920", "riscv";
- reg = <13>;
+ reg = <0xd>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller {
};
};
- cpu14: cpu@14 {
+ cpu14: cpu@e {
compatible = "thead,c920", "riscv";
- reg = <14>;
+ reg = <0xe>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller {
};
};
- cpu15: cpu@15 {
+ cpu15: cpu@f {
compatible = "thead,c920", "riscv";
- reg = <15>;
+ reg = <0xf>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller {
};
};
- cpu16: cpu@16 {
+ cpu16: cpu@10 {
compatible = "thead,c920", "riscv";
- reg = <16>;
+ reg = <0x10>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller {
};
};
- cpu17: cpu@17 {
+ cpu17: cpu@11 {
compatible = "thead,c920", "riscv";
- reg = <17>;
+ reg = <0x11>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller {
};
};
- cpu18: cpu@18 {
+ cpu18: cpu@12 {
compatible = "thead,c920", "riscv";
- reg = <18>;
+ reg = <0x12>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller {
};
};
- cpu19: cpu@19 {
+ cpu19: cpu@13 {
compatible = "thead,c920", "riscv";
- reg = <19>;
+ reg = <0x13>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller {
};
};
- cpu20: cpu@20 {
+ cpu20: cpu@14 {
compatible = "thead,c920", "riscv";
- reg = <20>;
+ reg = <0x14>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller {
};
};
- cpu21: cpu@21 {
+ cpu21: cpu@15 {
compatible = "thead,c920", "riscv";
- reg = <21>;
+ reg = <0x15>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller {
};
};
- cpu22: cpu@22 {
+ cpu22: cpu@16 {
compatible = "thead,c920", "riscv";
- reg = <22>;
+ reg = <0x16>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller {
};
};
- cpu23: cpu@23 {
+ cpu23: cpu@17 {
compatible = "thead,c920", "riscv";
- reg = <23>;
+ reg = <0x17>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller {
};
};
- cpu24: cpu@24 {
+ cpu24: cpu@18 {
compatible = "thead,c920", "riscv";
- reg = <24>;
+ reg = <0x18>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller {
};
};
- cpu25: cpu@25 {
+ cpu25: cpu@19 {
compatible = "thead,c920", "riscv";
- reg = <25>;
+ reg = <0x19>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller {
};
};
- cpu26: cpu@26 {
+ cpu26: cpu@1a {
compatible = "thead,c920", "riscv";
- reg = <26>;
+ reg = <0x1a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller {
};
};
- cpu27: cpu@27 {
+ cpu27: cpu@1b {
compatible = "thead,c920", "riscv";
- reg = <27>;
+ reg = <0x1b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller {
};
};
- cpu28: cpu@28 {
+ cpu28: cpu@1c {
compatible = "thead,c920", "riscv";
- reg = <28>;
+ reg = <0x1c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller {
};
};
- cpu29: cpu@29 {
+ cpu29: cpu@1d {
compatible = "thead,c920", "riscv";
- reg = <29>;
+ reg = <0x1d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller {
};
};
- cpu30: cpu@30 {
+ cpu30: cpu@1e {
compatible = "thead,c920", "riscv";
- reg = <30>;
+ reg = <0x1e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller {
};
};
- cpu31: cpu@31 {
+ cpu31: cpu@1f {
compatible = "thead,c920", "riscv";
- reg = <31>;
+ reg = <0x1f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller {
};
};
- cpu32: cpu@32 {
+ cpu32: cpu@20 {
compatible = "thead,c920", "riscv";
- reg = <32>;
+ reg = <0x20>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller {
};
};
- cpu33: cpu@33 {
+ cpu33: cpu@21 {
compatible = "thead,c920", "riscv";
- reg = <33>;
+ reg = <0x21>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller {
};
};
- cpu34: cpu@34 {
+ cpu34: cpu@22 {
compatible = "thead,c920", "riscv";
- reg = <34>;
+ reg = <0x22>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller {
};
};
- cpu35: cpu@35 {
+ cpu35: cpu@23 {
compatible = "thead,c920", "riscv";
- reg = <35>;
+ reg = <0x23>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller {
};
};
- cpu36: cpu@36 {
+ cpu36: cpu@24 {
compatible = "thead,c920", "riscv";
- reg = <36>;
+ reg = <0x24>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller {
};
};
- cpu37: cpu@37 {
+ cpu37: cpu@25 {
compatible = "thead,c920", "riscv";
- reg = <37>;
+ reg = <0x25>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller {
};
};
- cpu38: cpu@38 {
+ cpu38: cpu@26 {
compatible = "thead,c920", "riscv";
- reg = <38>;
+ reg = <0x26>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller {
};
};
- cpu39: cpu@39 {
+ cpu39: cpu@27 {
compatible = "thead,c920", "riscv";
- reg = <39>;
+ reg = <0x27>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller {
};
};
- cpu40: cpu@40 {
+ cpu40: cpu@28 {
compatible = "thead,c920", "riscv";
- reg = <40>;
+ reg = <0x28>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller {
};
};
- cpu41: cpu@41 {
+ cpu41: cpu@29 {
compatible = "thead,c920", "riscv";
- reg = <41>;
+ reg = <0x29>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller {
};
};
- cpu42: cpu@42 {
+ cpu42: cpu@2a {
compatible = "thead,c920", "riscv";
- reg = <42>;
+ reg = <0x2a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller {
};
};
- cpu43: cpu@43 {
+ cpu43: cpu@2b {
compatible = "thead,c920", "riscv";
- reg = <43>;
+ reg = <0x2b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller {
};
};
- cpu44: cpu@44 {
+ cpu44: cpu@2c {
compatible = "thead,c920", "riscv";
- reg = <44>;
+ reg = <0x2c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller {
};
};
- cpu45: cpu@45 {
+ cpu45: cpu@2d {
compatible = "thead,c920", "riscv";
- reg = <45>;
+ reg = <0x2d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller {
};
};
- cpu46: cpu@46 {
+ cpu46: cpu@2e {
compatible = "thead,c920", "riscv";
- reg = <46>;
+ reg = <0x2e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller {
};
};
- cpu47: cpu@47 {
+ cpu47: cpu@2f {
compatible = "thead,c920", "riscv";
- reg = <47>;
+ reg = <0x2f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller {
};
};
- cpu48: cpu@48 {
+ cpu48: cpu@30 {
compatible = "thead,c920", "riscv";
- reg = <48>;
+ reg = <0x30>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller {
};
};
- cpu49: cpu@49 {
+ cpu49: cpu@31 {
compatible = "thead,c920", "riscv";
- reg = <49>;
+ reg = <0x31>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller {
};
};
- cpu50: cpu@50 {
+ cpu50: cpu@32 {
compatible = "thead,c920", "riscv";
- reg = <50>;
+ reg = <0x32>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller {
};
};
- cpu51: cpu@51 {
+ cpu51: cpu@33 {
compatible = "thead,c920", "riscv";
- reg = <51>;
+ reg = <0x33>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller {
};
};
- cpu52: cpu@52 {
+ cpu52: cpu@34 {
compatible = "thead,c920", "riscv";
- reg = <52>;
+ reg = <0x34>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller {
};
};
- cpu53: cpu@53 {
+ cpu53: cpu@35 {
compatible = "thead,c920", "riscv";
- reg = <53>;
+ reg = <0x35>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller {
};
};
- cpu54: cpu@54 {
+ cpu54: cpu@36 {
compatible = "thead,c920", "riscv";
- reg = <54>;
+ reg = <0x36>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller {
};
};
- cpu55: cpu@55 {
+ cpu55: cpu@37 {
compatible = "thead,c920", "riscv";
- reg = <55>;
+ reg = <0x37>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller {
};
};
- cpu56: cpu@56 {
+ cpu56: cpu@38 {
compatible = "thead,c920", "riscv";
- reg = <56>;
+ reg = <0x38>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller {
};
};
- cpu57: cpu@57 {
+ cpu57: cpu@39 {
compatible = "thead,c920", "riscv";
- reg = <57>;
+ reg = <0x39>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller {
};
};
- cpu58: cpu@58 {
+ cpu58: cpu@3a {
compatible = "thead,c920", "riscv";
- reg = <58>;
+ reg = <0x3a>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller {
};
};
- cpu59: cpu@59 {
+ cpu59: cpu@3b {
compatible = "thead,c920", "riscv";
- reg = <59>;
+ reg = <0x3b>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller {
};
};
- cpu60: cpu@60 {
+ cpu60: cpu@3c {
compatible = "thead,c920", "riscv";
- reg = <60>;
+ reg = <0x3c>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller {
};
};
- cpu61: cpu@61 {
+ cpu61: cpu@3d {
compatible = "thead,c920", "riscv";
- reg = <61>;
+ reg = <0x3d>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller {
};
};
- cpu62: cpu@62 {
+ cpu62: cpu@3e {
compatible = "thead,c920", "riscv";
- reg = <62>;
+ reg = <0x3e>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller {
};
};
- cpu63: cpu@63 {
+ cpu63: cpu@3f {
compatible = "thead,c920", "riscv";
- reg = <63>;
+ reg = <0x3f>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
--
2.53.0
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