* [PATCH 11/12] ASoC: dt-bindings: google,sc7280-herobrine: Add Radxa Dragon Q6A sound card
From: Xilin Wu @ 2026-04-07 15:20 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
The Radxa Dragon Q6A can boot in EL2, allowing the kernel to access the
LPASS hardware directly. Add the compatible for it to the bindings.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../devicetree/bindings/sound/google,sc7280-herobrine.yaml | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml b/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
index cdcd7c6f21eb..cd87dfe20618 100644
--- a/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
+++ b/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
@@ -17,8 +17,13 @@ allOf:
properties:
compatible:
- enum:
- - google,sc7280-herobrine
+ oneOf:
+ - enum:
+ - google,sc7280-herobrine
+ - items:
+ - enum:
+ - radxa,dragon-q6a-sndcard
+ - const: google,sc7280-herobrine
"#address-cells":
const: 1
--
2.53.0
^ permalink raw reply related
* [PATCH 12/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: add LPASS CPU audio variant
From: Xilin Wu @ 2026-04-07 15:20 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
Add a qcs6490-radxa-dragon-q6a-lpass-cpu.dts variant for debugging and
bring-up of the host-controlled LPASS audio path on the Radxa Dragon
Q6A.
This variant enables the LPASS blocks and codec macros needed by the
lpass-cpu driver, wires WCD9380 playback/capture and DisplayPort audio
to the LPASS CDC DMA and DP interfaces, and disables remoteproc_adsp so
that the audio hardware is owned directly by Linux.
This DTB is an optional configuration for systems booted with the kernel
running at EL2, where direct CPU access to the LPASS hardware is
available. It is useful for users who need low-latency and fully
controllable audio.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts | 131 +++++++++++++++++++++
2 files changed, 132 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4ba8e7306419..2f84ef7109b5 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -169,6 +169,7 @@ qcs615-ride-el2-dtbs := qcs615-ride.dtb talos-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a-lpass-cpu.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts
new file mode 100644
index 000000000000..e7ee57372d7e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025-2026 Radxa Computer (Shenzhen) Co., Ltd.
+ *
+ * Direct CPU access to the LPASS hardware block on this platform is
+ * restricted by default. Booting the Linux kernel in EL2 will allow the
+ * kernel to access the LPASS hardware directly.
+ *
+ * You can achieve this by setting the Hypervisor Override BIOS setting to
+ * "Enabled" if you are using the official UEFI firmware.
+ */
+
+/dts-v1/;
+
+#include "qcs6490-radxa-dragon-q6a.dtsi"
+
+&gcc {
+ protected-clocks = <GCC_MSS_CFG_AHB_CLK>,
+ <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
+ <GCC_MSS_OFFLINE_AXI_CLK>,
+ <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+ <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+ <GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_SEC_CTRL_CLK_SRC>,
+ <GCC_WPSS_AHB_BDG_MST_CLK>,
+ <GCC_WPSS_AHB_CLK>,
+ <GCC_WPSS_RSCP_CLK>;
+};
+
+&lpass_aon {
+ status = "okay";
+};
+
+&lpass_core {
+ status = "okay";
+};
+
+&lpass_cpu {
+ status = "okay";
+
+ dai-link@5 {
+ reg = <LPASS_DP_RX>;
+ };
+
+ dai-link@6 {
+ reg = <LPASS_CDC_DMA_RX0>;
+ };
+
+ dai-link@19 {
+ reg = <LPASS_CDC_DMA_TX3>;
+ };
+};
+
+&lpass_hm {
+ status = "okay";
+};
+
+&lpass_rx_macro {
+ status = "okay";
+};
+
+&lpass_tx_macro {
+ status = "okay";
+};
+
+&lpass_va_macro {
+ status = "okay";
+};
+
+&lpasscc {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ status = "disabled";
+};
+
+&sound {
+ compatible = "radxa,dragon-q6a-sndcard", "google,sc7280-herobrine";
+ model = "qcs6490-wcd938x-dp";
+
+ audio-routing = "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "TX SWR_ADC1", "ADC2_OUTPUT";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dai-link@0 {
+ link-name = "WCD9380 Playback";
+ reg = <0>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr0 0>, <&lpass_rx_macro 0>;
+ };
+ };
+
+ dai-link@1 {
+ link-name = "DisplayPort";
+ reg = <1>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_DP_RX>;
+ };
+
+ codec {
+ sound-dai = <&mdss_dp>;
+ };
+ };
+
+ dai-link@2 {
+ link-name = "WCD9380 Capture";
+ reg = <2>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr1 0>, <&lpass_tx_macro 0>;
+ };
+ };
+};
--
2.53.0
^ permalink raw reply related
* [PATCH 10/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: factor out common board dtsi
From: Xilin Wu @ 2026-04-07 15:20 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
Move the common Radxa Dragon Q6A board description from
qcs6490-radxa-dragon-q6a.dts to a new qcs6490-radxa-dragon-q6a.dtsi so
it can be shared by multiple board variants.
Keep the existing Audioreach-based qcs6490-radxa-dragon-q6a.dts as the
default configuration by including the new common .dtsi and
qcs6490-audioreach.dtsi.
No functional change intended.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 1135 +------------------
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi | 1137 ++++++++++++++++++++
2 files changed, 1139 insertions(+), 1133 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 5679f38de5b3..f52328fbaef9 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -1,568 +1,13 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
- * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd.
+ * Copyright (c) 2025-2026 Radxa Computer (Shenzhen) Co., Ltd.
*/
/dts-v1/;
-/* PM7250B is configured to use SID8/9 */
-#define PM7250B_SID 8
-#define PM7250B_SID1 9
-
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
-#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include "kodiak.dtsi"
-#include "pm7250b.dtsi"
-#include "pm7325.dtsi"
-#include "pm8350c.dtsi" /* PM7350C */
-#include "pmk8350.dtsi" /* PMK7325 */
+#include "qcs6490-radxa-dragon-q6a.dtsi"
#include "qcs6490-audioreach.dtsi"
-/delete-node/ &adsp_mem;
-/delete-node/ &adsp_rpc_remote_heap_mem;
-/delete-node/ &cdsp_mem;
-/delete-node/ &gpu_zap_mem;
-/delete-node/ &ipa_fw_mem;
-/delete-node/ &mpss_mem;
-/delete-node/ &remoteproc_mpss;
-/delete-node/ &remoteproc_wpss;
-/delete-node/ &rmtfs_mem;
-/delete-node/ &video_mem;
-/delete-node/ &wifi;
-/delete-node/ &wlan_ce_mem;
-/delete-node/ &wlan_fw_mem;
-/delete-node/ &wpss_mem;
-
-/ {
- model = "Radxa Dragon Q6A";
- compatible = "radxa,dragon-q6a", "qcom,qcm6490";
- chassis-type = "embedded";
-
- aliases {
- mmc0 = &sdhc_1;
- mmc1 = &sdhc_2;
- serial0 = &uart5;
- };
-
- wcd938x: audio-codec {
- compatible = "qcom,wcd9380-codec";
-
- pinctrl-0 = <&wcd_default>;
- pinctrl-names = "default";
-
- reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
-
- vdd-rxtx-supply = <&vreg_l18b_1p8>;
- vdd-io-supply = <&vreg_l18b_1p8>;
- vdd-buck-supply = <&vreg_l17b_1p8>;
- vdd-mic-bias-supply = <&vreg_bob_3p296>;
-
- qcom,micbias1-microvolt = <1800000>;
- qcom,micbias2-microvolt = <1800000>;
- qcom,micbias3-microvolt = <1800000>;
- qcom,micbias4-microvolt = <1800000>;
- qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
- qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
- qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
- qcom,rx-device = <&wcd_rx>;
- qcom,tx-device = <&wcd_tx>;
-
- qcom,hphl-jack-type-normally-closed;
-
- #sound-dai-cells = <1>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- usb2_1_con: connector-0 {
- compatible = "usb-a-connector";
- vbus-supply = <&vcc_5v_peri>;
-
- port {
- usb2_1_connector: endpoint {
- remote-endpoint = <&usb_hub_2_1>;
- };
- };
- };
-
- usb2_2_con: connector-1 {
- compatible = "usb-a-connector";
- vbus-supply = <&vcc_5v_peri>;
-
- port {
- usb2_2_connector: endpoint {
- remote-endpoint = <&usb_hub_2_2>;
- };
- };
- };
-
- usb2_3_con: connector-2 {
- compatible = "usb-a-connector";
- vbus-supply = <&vcc_5v_peri>;
-
- port {
- usb2_3_connector: endpoint {
- remote-endpoint = <&usb_hub_2_3>;
- };
- };
- };
-
- usb3_con: connector {
- compatible = "usb-a-connector";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- usb3_con_hs_in: endpoint {
- remote-endpoint = <&usb_1_dwc3_hs>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- usb3_con_ss_in: endpoint {
- remote-endpoint = <&usb_1_qmpphy_out_usb>;
- };
- };
- };
- };
-
- hdmi-bridge {
- compatible = "radxa,ra620";
-
- pinctrl-0 = <&dp_hot_plug_det>;
- pinctrl-names = "default";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- hdmi_bridge_in: endpoint {
- remote-endpoint = <&usb_1_qmpphy_out_dp>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- hdmi_bridge_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- label = "hdmi";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_bridge_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-0 = <&user_led>;
- pinctrl-names = "default";
-
- user-led {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_INDICATOR;
- gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
- default-state = "off";
- panic-indicator;
- };
- };
-
- reserved-memory {
- lpass_ml_mem: lpass-ml@81800000 {
- reg = <0x0 0x81800000 0x0 0xf00000>;
- no-map;
- };
-
- cdsp_secure_heap_mem: cdsp-secure-heap@82700000 {
- reg = <0x0 0x82700000 0x0 0x10000>;
- no-map;
- };
-
- adsp_mem: adsp@8b800000 {
- reg = <0x0 0x8b800000 0x0 0x2800000>;
- no-map;
- };
-
- cdsp_mem: cdsp@8e000000 {
- reg = <0x0 0x8e000000 0x0 0x1e00000>;
- no-map;
- };
-
- video_mem: video@8fe00000 {
- reg = <0x0 0x8fe00000 0x0 0x500000>;
- no-map;
- };
-
- gpu_zap_mem: zap@90300000 {
- reg = <0x0 0x90300000 0x0 0x5000>;
- no-map;
- };
-
- tz_stat_mem: tz-stat@c0000000 {
- reg = <0x0 0xc0000000 0x0 0x100000>;
- no-map;
- };
-
- tags_mem: tags@c0100000 {
- reg = <0x0 0xc0100000 0x0 0x1200000>;
- no-map;
- };
-
- qtee_mem: qtee@c1300000 {
- reg = <0x0 0xc1300000 0x0 0x500000>;
- no-map;
- };
-
- trusted_apps_mem: trusted-apps@c1800000 {
- reg = <0x0 0xc1800000 0x0 0x2200000>;
- no-map;
- };
-
- adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@c6500000 {
- reg = <0x0 0xc6500000 0x0 0x800000>;
- no-map;
- };
- };
-
- thermal-zones {
- msm-skin-thermal {
- polling-delay-passive = <0>;
- thermal-sensors = <&pmk8350_adc_tm 2>;
- };
-
- quiet-thermal {
- polling-delay-passive = <0>;
- thermal-sensors = <&pmk8350_adc_tm 1>;
- };
-
- ufs-thermal {
- polling-delay-passive = <0>;
- thermal-sensors = <&pmk8350_adc_tm 3>;
- };
-
- xo-thermal {
- polling-delay-passive = <0>;
- thermal-sensors = <&pmk8350_adc_tm 0>;
- };
- };
-
- vcc_1v8: regulator-vcc-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_5v_peri>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_5v_peri>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_5v_peri: regulator-vcc-5v-peri {
- compatible = "regulator-fixed";
- regulator-name = "vcc_5v_peri";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vph_pwr>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vph_pwr: regulator-vph-pwr {
- compatible = "regulator-fixed";
- regulator-name = "vph_pwr";
- regulator-min-microvolt = <3700000>;
- regulator-max-microvolt = <3700000>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&apps_rsc {
- regulators-0 {
- compatible = "qcom,pm7325-rpmh-regulators";
- qcom,pmic-id = "b";
-
- vdd-s1-supply = <&vph_pwr>;
- vdd-s2-supply = <&vph_pwr>;
- vdd-s3-supply = <&vph_pwr>;
- vdd-s4-supply = <&vph_pwr>;
- vdd-s5-supply = <&vph_pwr>;
- vdd-s6-supply = <&vph_pwr>;
- vdd-s7-supply = <&vph_pwr>;
- vdd-s8-supply = <&vph_pwr>;
- vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p536>;
- vdd-l2-l7-supply = <&vreg_bob_3p296>;
- vdd-l6-l9-l10-supply = <&vreg_s8b_1p2>;
- vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p84>;
-
- vreg_s1b_1p84: smps1 {
- regulator-name = "vreg_s1b_1p84";
- regulator-min-microvolt = <1840000>;
- regulator-max-microvolt = <2040000>;
- };
-
- vreg_s7b_0p536: smps7 {
- regulator-name = "vreg_s7b_0p536";
- regulator-min-microvolt = <536000>;
- regulator-max-microvolt = <1120000>;
- };
-
- vreg_s8b_1p2: smps8 {
- regulator-name = "vreg_s8b_1p2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1496000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
- };
-
- vreg_l1b_0p912: ldo1 {
- regulator-name = "vreg_l1b_0p912";
- regulator-min-microvolt = <832000>;
- regulator-max-microvolt = <920000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l2b_3p072: ldo2 {
- regulator-name = "vreg_l2b_3p072";
- regulator-min-microvolt = <2704000>;
- regulator-max-microvolt = <3544000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l6b_1p2: ldo6 {
- regulator-name = "vreg_l6b_1p2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1256000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l7b_2p96: ldo7 {
- regulator-name = "vreg_l7b_2p96";
- regulator-min-microvolt = <2960000>;
- regulator-max-microvolt = <2960000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l9b_1p2: ldo9 {
- regulator-name = "vreg_l9b_1p2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1304000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l17b_1p8: ldo17 {
- regulator-name = "vreg_l17b_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1896000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l18b_1p8: ldo18 {
- regulator-name = "vreg_l18b_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2000000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-always-on;
- };
-
- vreg_l19b_1p8: ldo19 {
- regulator-name = "vreg_l19b_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2000000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
- };
-
- regulators-1 {
- compatible = "qcom,pm8350c-rpmh-regulators";
- qcom,pmic-id = "c";
-
- vdd-s1-supply = <&vph_pwr>;
- vdd-s2-supply = <&vph_pwr>;
- vdd-s3-supply = <&vph_pwr>;
- vdd-s4-supply = <&vph_pwr>;
- vdd-s5-supply = <&vph_pwr>;
- vdd-s6-supply = <&vph_pwr>;
- vdd-s7-supply = <&vph_pwr>;
- vdd-s8-supply = <&vph_pwr>;
- vdd-s9-supply = <&vph_pwr>;
- vdd-s10-supply = <&vph_pwr>;
- vdd-l1-l12-supply = <&vreg_s1b_1p84>;
- vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
- vdd-l10-supply = <&vreg_s7b_0p536>;
- vdd-bob-supply = <&vph_pwr>;
-
- vreg_l1c_1p8: ldo1 {
- regulator-name = "vreg_l1c_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1976000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l6c_2p96: ldo6 {
- regulator-name = "vreg_l6c_2p96";
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <3544000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l9c_2p96: ldo9 {
- regulator-name = "vreg_l9c_2p96";
- regulator-min-microvolt = <2704000>;
- regulator-max-microvolt = <3544000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l10c_0p88: ldo10 {
- regulator-name = "vreg_l10c_0p88";
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <1048000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_bob_3p296: bob {
- regulator-name = "vreg_bob_3p296";
- regulator-min-microvolt = <3032000>;
- regulator-max-microvolt = <3960000>;
- };
- };
-};
-
-&gcc {
- protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
- <GCC_MSS_CFG_AHB_CLK>,
- <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
- <GCC_MSS_OFFLINE_AXI_CLK>,
- <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
- <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
- <GCC_MSS_SNOC_AXI_CLK>,
- <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
- <GCC_QSPI_CORE_CLK>,
- <GCC_QSPI_CORE_CLK_SRC>,
- <GCC_SEC_CTRL_CLK_SRC>,
- <GCC_WPSS_AHB_BDG_MST_CLK>,
- <GCC_WPSS_AHB_CLK>,
- <GCC_WPSS_RSCP_CLK>;
-};
-
-&gpi_dma0 {
- status = "okay";
-};
-
-&gpi_dma1 {
- status = "okay";
-};
-
-&gpu {
- status = "okay";
-};
-
-&gpu_zap_shader {
- firmware-name = "qcom/qcs6490/a660_zap.mbn";
-};
-
-/* Pin 13, 15 in GPIO header */
-&i2c0 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-/* Pin 27, 28 in GPIO header */
-&i2c2 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-/* Pin 3, 5 in GPIO header */
-&i2c6 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-&i2c10 {
- qcom,enable-gsi-dma;
- status = "okay";
-
- rtc: rtc@68 {
- compatible = "st,m41t11";
- reg = <0x68>;
- };
-};
-
-/* External touchscreen */
-&i2c13 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
&lpass_audiocc {
compatible = "qcom,qcm6490-lpassaudiocc";
/delete-property/ power-domains;
@@ -580,207 +25,6 @@ &lpass_va_macro {
status = "okay";
};
-&mdss {
- status = "okay";
-};
-
-&mdss_dp {
- sound-name-prefix = "Display Port0";
-
- status = "okay";
-};
-
-&mdss_dp_out {
- data-lanes = <0 1>;
- remote-endpoint = <&usb_dp_qmpphy_dp_in>;
-};
-
-&pcie0 {
- perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
-
- pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&pcie0_phy {
- vdda-phy-supply = <&vreg_l10c_0p88>;
- vdda-pll-supply = <&vreg_l6b_1p2>;
-
- status = "okay";
-};
-
-&pcie1 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-
- pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
- pinctrl-names = "default";
-
- /* Support for QPS615 PCIe switch */
- iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
- <0x100 &apps_smmu 0x1c81 0x1>,
- <0x208 &apps_smmu 0x1c84 0x1>,
- <0x210 &apps_smmu 0x1c85 0x1>,
- <0x218 &apps_smmu 0x1c86 0x1>,
- <0x300 &apps_smmu 0x1c87 0x1>,
- <0x400 &apps_smmu 0x1c88 0x1>,
- <0x500 &apps_smmu 0x1c89 0x1>,
- <0x501 &apps_smmu 0x1c90 0x1>;
-
- status = "okay";
-};
-
-&pcie1_phy {
- vdda-phy-supply = <&vreg_l10c_0p88>;
- vdda-pll-supply = <&vreg_l6b_1p2>;
-
- status = "okay";
-};
-
-&pm7325_gpios {
- pm7325_adc_default: adc-default-state {
- pins = "gpio2";
- function = PMIC_GPIO_FUNC_NORMAL;
- bias-high-impedance;
- };
-};
-
-&pm7325_temp_alarm {
- io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>;
- io-channel-names = "thermal";
-};
-
-&pmk8350_adc_tm {
- status = "okay";
-
- xo-therm@0 {
- reg = <0>;
- io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
- };
-
- quiet-therm@1 {
- reg = <1>;
- io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
- };
-
- msm-skin-therm@2 {
- reg = <2>;
- io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
- };
-
- ufs-therm@3 {
- reg = <3>;
- io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
- };
-};
-
-&pmk8350_vadc {
- pinctrl-0 = <&pm7325_adc_default>;
- pinctrl-names = "default";
-
- channel@3 {
- reg = <PMK8350_ADC7_DIE_TEMP>;
- label = "pmk7325_die_temp";
- qcom,pre-scaling = <1 1>;
- };
-
- channel@44 {
- reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
- label = "xo_therm";
- qcom,hw-settle-time = <200>;
- qcom,pre-scaling = <1 1>;
- qcom,ratiometric;
- };
-
- channel@103 {
- reg = <PM7325_ADC7_DIE_TEMP>;
- label = "pm7325_die_temp";
- qcom,pre-scaling = <1 1>;
- };
-
- channel@144 {
- reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time = <200>;
- qcom,pre-scaling = <1 1>;
- label = "quiet_therm";
- };
-
- channel@146 {
- reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time = <200>;
- qcom,pre-scaling = <1 1>;
- label = "msm_skin_therm";
- };
-
- channel@14a {
- /* According to datasheet, 0x4a = AMUX1_GPIO = GPIO_02 */
- reg = <PM7325_ADC7_GPIO1_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time = <200>;
- qcom,pre-scaling = <1 1>;
- label = "ufs_therm";
- };
-};
-
-&pon_pwrkey {
- status = "okay";
-};
-
-&qupv3_id_0 {
- firmware-name = "qcom/qcm6490/qupv3fw.elf";
- status = "okay";
-};
-
-&qupv3_id_1 {
- firmware-name = "qcom/qcm6490/qupv3fw.elf";
- status = "okay";
-};
-
-&remoteproc_adsp {
- firmware-name = "qcom/qcs6490/radxa/dragon-q6a/adsp.mbn";
- status = "okay";
-};
-
-&remoteproc_cdsp {
- firmware-name = "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn";
- status = "okay";
-};
-
-&sdhc_1 {
- non-removable;
- no-sd;
- no-sdio;
-
- vmmc-supply = <&vreg_l7b_2p96>;
- vqmmc-supply = <&vreg_l19b_1p8>;
-
- status = "okay";
-};
-
-&sdhc_2 {
- pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>;
- pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>;
-
- vmmc-supply = <&vreg_l9c_2p96>;
- vqmmc-supply = <&vreg_l6c_2p96>;
-
- cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
&sound {
compatible = "qcom,qcs6490-rb3gen2-sndcard";
model = "QCS6490-Radxa-Dragon-Q6A";
@@ -838,378 +82,3 @@ platform {
};
};
};
-
-/* Pin 11, 29, 31, 32 in GPIO header */
-&spi7 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-/* Pin 19, 21, 23, 24, 26 in GPIO header */
-&spi12 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-/* Pin 22, 33, 36, 37 in GPIO header */
-&spi14 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-&swr0 {
- status = "okay";
-
- wcd_rx: codec@0,4 {
- compatible = "sdw20217010d00";
- reg = <0 4>;
- qcom,rx-port-mapping = <1 2 3 4 5>;
- };
-};
-
-&swr1 {
- status = "okay";
-
- wcd_tx: codec@0,3 {
- compatible = "sdw20217010d00";
- reg = <0 3>;
- qcom,tx-port-mapping = <1 1 2 3>;
- };
-};
-
-&tlmm {
- /*
- * 12-17: reserved for QSPI flash
- */
- gpio-reserved-ranges = <12 6>;
- gpio-line-names =
- /* GPIO_0 ~ GPIO_3 */
- "PIN_13", "PIN_15", "", "",
- /* GPIO_4 ~ GPIO_7 */
- "", "", "", "",
- /* GPIO_8 ~ GPIO_11 */
- "PIN_27", "PIN_28", "", "",
- /* GPIO_12 ~ GPIO_15 */
- "", "", "", "",
- /* GPIO_16 ~ GPIO_19 */
- "", "", "", "",
- /* GPIO_20 ~ GPIO_23 */
- "", "", "PIN_8", "PIN_10",
- /* GPIO_24 ~ GPIO_27 */
- "PIN_3", "PIN_5", "PIN_16", "PIN_18",
- /* GPIO_28 ~ GPIO_31 */
- "PIN_31", "PIN_11", "PIN_32", "PIN_29",
- /* GPIO_32 ~ GPIO_35 */
- "", "", "", "",
- /* GPIO_36 ~ GPIO_39 */
- "", "", "", "",
- /* GPIO_40 ~ GPIO_43 */
- "", "", "", "",
- /* GPIO_44 ~ GPIO_47 */
- "", "", "", "",
- /* GPIO_48 ~ GPIO_51 */
- "PIN_21", "PIN_19", "PIN_23", "PIN_24",
- /* GPIO_52 ~ GPIO_55 */
- "", "", "", "PIN_26",
- /* GPIO_56 ~ GPIO_59 */
- "PIN_33", "PIN_22", "PIN_37", "PIN_36",
- /* GPIO_60 ~ GPIO_63 */
- "", "", "", "",
- /* GPIO_64 ~ GPIO_67 */
- "", "", "", "",
- /* GPIO_68 ~ GPIO_71 */
- "", "", "", "",
- /* GPIO_72 ~ GPIO_75 */
- "", "", "", "",
- /* GPIO_76 ~ GPIO_79 */
- "", "", "", "",
- /* GPIO_80 ~ GPIO_83 */
- "", "", "", "",
- /* GPIO_84 ~ GPIO_87 */
- "", "", "", "",
- /* GPIO_88 ~ GPIO_91 */
- "", "", "", "",
- /* GPIO_92 ~ GPIO_95 */
- "", "", "", "",
- /* GPIO_96 ~ GPIO_99 */
- "PIN_7", "PIN_12", "PIN_38", "PIN_40",
- /* GPIO_100 ~ GPIO_103 */
- "PIN_35", "", "", "",
- /* GPIO_104 ~ GPIO_107 */
- "", "", "", "",
- /* GPIO_108 ~ GPIO_111 */
- "", "", "", "",
- /* GPIO_112 ~ GPIO_115 */
- "", "", "", "",
- /* GPIO_116 ~ GPIO_119 */
- "", "", "", "",
- /* GPIO_120 ~ GPIO_123 */
- "", "", "", "",
- /* GPIO_124 ~ GPIO_127 */
- "", "", "", "",
- /* GPIO_128 ~ GPIO_131 */
- "", "", "", "",
- /* GPIO_132 ~ GPIO_135 */
- "", "", "", "",
- /* GPIO_136 ~ GPIO_139 */
- "", "", "", "",
- /* GPIO_140 ~ GPIO_143 */
- "", "", "", "",
- /* GPIO_144 ~ GPIO_147 */
- "", "", "", "",
- /* GPIO_148 ~ GPIO_151 */
- "", "", "", "",
- /* GPIO_152 ~ GPIO_155 */
- "", "", "", "",
- /* GPIO_156 ~ GPIO_159 */
- "", "", "", "",
- /* GPIO_160 ~ GPIO_163 */
- "", "", "", "",
- /* GPIO_164 ~ GPIO_167 */
- "", "", "", "",
- /* GPIO_168 ~ GPIO_171 */
- "", "", "", "",
- /* GPIO_172 ~ GPIO_174 */
- "", "", "";
-
- pcie0_reset_n: pcie0-reset-n-state {
- pins = "gpio87";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- pcie0_wake_n: pcie0-wake-n-state {
- pins = "gpio89";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- pcie1_reset_n: pcie1-reset-n-state {
- pins = "gpio2";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- pcie1_wake_n: pcie1-wake-n-state {
- pins = "gpio3";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- sd_cd: sd-cd-state {
- pins = "gpio91";
- function = "gpio";
- bias-pull-up;
- };
-
- user_led: user-led-state {
- pins = "gpio42";
- function = "gpio";
- bias-pull-up;
- };
-
- wcd_default: wcd-reset-n-active-state {
- pins = "gpio83";
- function = "gpio";
- drive-strength = <16>;
- bias-disable;
- output-low;
- };
-};
-
-&uart5 {
- status = "okay";
-};
-
-&ufs_mem_hc {
- reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
- vcc-supply = <&vreg_l7b_2p96>;
- vcc-max-microamp = <800000>;
- vccq-supply = <&vreg_l9b_1p2>;
- vccq-max-microamp = <900000>;
- vccq2-supply = <&vreg_l9b_1p2>;
- vccq2-max-microamp = <1300000>;
-
- /* Gear-4 Rate-B is unstable due to board */
- /* and UFS module design limitations */
- limit-gear-rate = "rate-a";
-
- status = "okay";
-};
-
-&ufs_mem_phy {
- vdda-phy-supply = <&vreg_l10c_0p88>;
- vdda-pll-supply = <&vreg_l6b_1p2>;
-
- status = "okay";
-};
-
-&usb_1 {
- dr_mode = "host";
-
- status = "okay";
-};
-
-&usb_1_dwc3_hs {
- remote-endpoint = <&usb3_con_hs_in>;
-};
-
-&usb_1_hsphy {
- vdda-pll-supply = <&vreg_l10c_0p88>;
- vdda33-supply = <&vreg_l2b_3p072>;
- vdda18-supply = <&vreg_l1c_1p8>;
-
- status = "okay";
-};
-
-&usb_1_qmpphy {
- vdda-phy-supply = <&vreg_l6b_1p2>;
- vdda-pll-supply = <&vreg_l1b_0p912>;
-
- /delete-property/ orientation-switch;
-
- status = "okay";
-
- ports {
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /delete-node/ endpoint;
-
- /* RX0/TX0 is statically connected to RA620 bridge */
- usb_1_qmpphy_out_dp: endpoint@0 {
- reg = <0>;
-
- data-lanes = <0 1>;
- remote-endpoint = <&hdmi_bridge_in>;
- };
-
- /* RX1/TX1 is statically connected to USB-A port */
- usb_1_qmpphy_out_usb: endpoint@1 {
- reg = <1>;
-
- data-lanes = <2 3>;
- remote-endpoint = <&usb3_con_ss_in>;
- };
- };
- };
-};
-
-&usb_2 {
- dr_mode = "host";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "okay";
-
- /* Onboard USB 2.0 hub */
- usb_hub_2_x: hub@1 {
- compatible = "usb1a40,0101";
- reg = <1>;
- vdd-supply = <&vcc_5v_peri>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
-
- usb_hub_2_1: endpoint {
- remote-endpoint = <&usb2_1_connector>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- usb_hub_2_2: endpoint {
- remote-endpoint = <&usb2_2_connector>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- usb_hub_2_3: endpoint {
- remote-endpoint = <&usb2_3_connector>;
- };
- };
- };
-
- /* FCU760K Wi-Fi & Bluetooth module */
- wifi@4 {
- compatible = "usba69c,8d80";
- reg = <4>;
- };
- };
-};
-
-&usb_2_hsphy {
- vdda-pll-supply = <&vreg_l10c_0p88>;
- vdda33-supply = <&vreg_l2b_3p072>;
- vdda18-supply = <&vreg_l1c_1p8>;
-
- status = "okay";
-};
-
-&venus {
- status = "okay";
-};
-
-/* PINCTRL - additions to nodes defined in sc7280.dtsi */
-&dp_hot_plug_det {
- bias-disable;
-};
-
-&pcie0_clkreq_n {
- bias-pull-up;
- drive-strength = <2>;
-};
-
-&pcie1_clkreq_n {
- bias-pull-up;
- drive-strength = <2>;
-};
-
-&sdc1_clk {
- bias-disable;
- drive-strength = <16>;
-};
-
-&sdc1_cmd {
- bias-pull-up;
- drive-strength = <10>;
-};
-
-&sdc1_data {
- bias-pull-up;
- drive-strength = <10>;
-};
-
-&sdc1_rclk {
- bias-pull-down;
-};
-
-&sdc2_clk {
- bias-disable;
- drive-strength = <16>;
-};
-
-&sdc2_cmd {
- bias-pull-up;
- drive-strength = <10>;
-};
-
-&sdc2_data {
- bias-pull-up;
- drive-strength = <10>;
-};
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi
new file mode 100644
index 000000000000..52c2f053c820
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi
@@ -0,0 +1,1137 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025-2026 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+/* PM7250B is configured to use SID8/9 */
+#define PM7250B_SID 8
+#define PM7250B_SID1 9
+
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "kodiak.dtsi"
+#include "pm7250b.dtsi"
+#include "pm7325.dtsi"
+#include "pm8350c.dtsi" /* PM7350C */
+#include "pmk8350.dtsi" /* PMK7325 */
+
+/delete-node/ &adsp_mem;
+/delete-node/ &adsp_rpc_remote_heap_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &gpu_zap_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &remoteproc_mpss;
+/delete-node/ &remoteproc_wpss;
+/delete-node/ &rmtfs_mem;
+/delete-node/ &video_mem;
+/delete-node/ &wifi;
+/delete-node/ &wlan_ce_mem;
+/delete-node/ &wlan_fw_mem;
+/delete-node/ &wpss_mem;
+
+/ {
+ model = "Radxa Dragon Q6A";
+ compatible = "radxa,dragon-q6a", "qcom,qcm6490";
+ chassis-type = "embedded";
+
+ aliases {
+ mmc0 = &sdhc_1;
+ mmc1 = &sdhc_2;
+ serial0 = &uart5;
+ };
+
+ wcd938x: audio-codec {
+ compatible = "qcom,wcd9380-codec";
+
+ pinctrl-0 = <&wcd_default>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
+
+ vdd-rxtx-supply = <&vreg_l18b_1p8>;
+ vdd-io-supply = <&vreg_l18b_1p8>;
+ vdd-buck-supply = <&vreg_l17b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob_3p296>;
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ qcom,hphl-jack-type-normally-closed;
+
+ #sound-dai-cells = <1>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb2_1_con: connector-0 {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vcc_5v_peri>;
+
+ port {
+ usb2_1_connector: endpoint {
+ remote-endpoint = <&usb_hub_2_1>;
+ };
+ };
+ };
+
+ usb2_2_con: connector-1 {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vcc_5v_peri>;
+
+ port {
+ usb2_2_connector: endpoint {
+ remote-endpoint = <&usb_hub_2_2>;
+ };
+ };
+ };
+
+ usb2_3_con: connector-2 {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vcc_5v_peri>;
+
+ port {
+ usb2_3_connector: endpoint {
+ remote-endpoint = <&usb_hub_2_3>;
+ };
+ };
+ };
+
+ usb3_con: connector {
+ compatible = "usb-a-connector";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb3_con_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb3_con_ss_in: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_out_usb>;
+ };
+ };
+ };
+ };
+
+ hdmi-bridge {
+ compatible = "radxa,ra620";
+
+ pinctrl-0 = <&dp_hot_plug_det>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_bridge_in: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_out_dp>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_bridge_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_bridge_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-0 = <&user_led>;
+ pinctrl-names = "default";
+
+ user-led {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ panic-indicator;
+ };
+ };
+
+ reserved-memory {
+ lpass_ml_mem: lpass-ml@81800000 {
+ reg = <0x0 0x81800000 0x0 0xf00000>;
+ no-map;
+ };
+
+ cdsp_secure_heap_mem: cdsp-secure-heap@82700000 {
+ reg = <0x0 0x82700000 0x0 0x10000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0x2800000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@8e000000 {
+ reg = <0x0 0x8e000000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ video_mem: video@8fe00000 {
+ reg = <0x0 0x8fe00000 0x0 0x500000>;
+ no-map;
+ };
+
+ gpu_zap_mem: zap@90300000 {
+ reg = <0x0 0x90300000 0x0 0x5000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat@c0000000 {
+ reg = <0x0 0xc0000000 0x0 0x100000>;
+ no-map;
+ };
+
+ tags_mem: tags@c0100000 {
+ reg = <0x0 0xc0100000 0x0 0x1200000>;
+ no-map;
+ };
+
+ qtee_mem: qtee@c1300000 {
+ reg = <0x0 0xc1300000 0x0 0x500000>;
+ no-map;
+ };
+
+ trusted_apps_mem: trusted-apps@c1800000 {
+ reg = <0x0 0xc1800000 0x0 0x2200000>;
+ no-map;
+ };
+
+ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@c6500000 {
+ reg = <0x0 0xc6500000 0x0 0x800000>;
+ no-map;
+ };
+ };
+
+ thermal-zones {
+ msm-skin-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 2>;
+ };
+
+ quiet-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 1>;
+ };
+
+ ufs-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 3>;
+ };
+
+ xo-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 0>;
+ };
+ };
+
+ vcc_1v8: regulator-vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_5v_peri>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v_peri>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_5v_peri: regulator-vcc-5v-peri {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v_peri";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vph_pwr>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7325-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p536>;
+ vdd-l2-l7-supply = <&vreg_bob_3p296>;
+ vdd-l6-l9-l10-supply = <&vreg_s8b_1p2>;
+ vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p84>;
+
+ vreg_s1b_1p84: smps1 {
+ regulator-name = "vreg_s1b_1p84";
+ regulator-min-microvolt = <1840000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s7b_0p536: smps7 {
+ regulator-name = "vreg_s7b_0p536";
+ regulator-min-microvolt = <536000>;
+ regulator-max-microvolt = <1120000>;
+ };
+
+ vreg_s8b_1p2: smps8 {
+ regulator-name = "vreg_s8b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1496000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_l1b_0p912: ldo1 {
+ regulator-name = "vreg_l1b_0p912";
+ regulator-min-microvolt = <832000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p072: ldo2 {
+ regulator-name = "vreg_l2b_3p072";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p2: ldo6 {
+ regulator-name = "vreg_l6b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p96: ldo7 {
+ regulator-name = "vreg_l7b_2p96";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_1p2: ldo9 {
+ regulator-name = "vreg_l9b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_1p8: ldo17 {
+ regulator-name = "vreg_l17b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1896000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p8: ldo18 {
+ regulator-name = "vreg_l18b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l19b_1p8: ldo19 {
+ regulator-name = "vreg_l19b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-l1-l12-supply = <&vreg_s1b_1p84>;
+ vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
+ vdd-l10-supply = <&vreg_s7b_0p536>;
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-name = "vreg_l1c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1976000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p96: ldo6 {
+ regulator-name = "vreg_l6c_2p96";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p96: ldo9 {
+ regulator-name = "vreg_l9c_2p96";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10c_0p88: ldo10 {
+ regulator-name = "vreg_l10c_0p88";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1048000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob_3p296: bob {
+ regulator-name = "vreg_bob_3p296";
+ regulator-min-microvolt = <3032000>;
+ regulator-max-microvolt = <3960000>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
+ <GCC_MSS_CFG_AHB_CLK>,
+ <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
+ <GCC_MSS_OFFLINE_AXI_CLK>,
+ <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+ <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+ <GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_SEC_CTRL_CLK_SRC>,
+ <GCC_WPSS_AHB_BDG_MST_CLK>,
+ <GCC_WPSS_AHB_CLK>,
+ <GCC_WPSS_RSCP_CLK>;
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/qcs6490/a660_zap.mbn";
+};
+
+/* Pin 13, 15 in GPIO header */
+&i2c0 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+/* Pin 27, 28 in GPIO header */
+&i2c2 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+/* Pin 3, 5 in GPIO header */
+&i2c6 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+&i2c10 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+
+ rtc: rtc@68 {
+ compatible = "st,m41t11";
+ reg = <0x68>;
+ };
+};
+
+/* External touchscreen */
+&i2c13 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp {
+ sound-name-prefix = "Display Port0";
+
+ status = "okay";
+};
+
+&mdss_dp_out {
+ data-lanes = <0 1>;
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+};
+
+&pcie0 {
+ perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&pcie1 {
+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
+ pinctrl-names = "default";
+
+ /* Support for QPS615 PCIe switch */
+ iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+ <0x100 &apps_smmu 0x1c81 0x1>,
+ <0x208 &apps_smmu 0x1c84 0x1>,
+ <0x210 &apps_smmu 0x1c85 0x1>,
+ <0x218 &apps_smmu 0x1c86 0x1>,
+ <0x300 &apps_smmu 0x1c87 0x1>,
+ <0x400 &apps_smmu 0x1c88 0x1>,
+ <0x500 &apps_smmu 0x1c89 0x1>,
+ <0x501 &apps_smmu 0x1c90 0x1>;
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&pm7325_gpios {
+ pm7325_adc_default: adc-default-state {
+ pins = "gpio2";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-high-impedance;
+ };
+};
+
+&pm7325_temp_alarm {
+ io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>;
+ io-channel-names = "thermal";
+};
+
+&pmk8350_adc_tm {
+ status = "okay";
+
+ xo-therm@0 {
+ reg = <0>;
+ io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ quiet-therm@1 {
+ reg = <1>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ msm-skin-therm@2 {
+ reg = <2>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ ufs-therm@3 {
+ reg = <3>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pmk8350_vadc {
+ pinctrl-0 = <&pm7325_adc_default>;
+ pinctrl-names = "default";
+
+ channel@3 {
+ reg = <PMK8350_ADC7_DIE_TEMP>;
+ label = "pmk7325_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@44 {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ label = "xo_therm";
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ };
+
+ channel@103 {
+ reg = <PM7325_ADC7_DIE_TEMP>;
+ label = "pm7325_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@144 {
+ reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "quiet_therm";
+ };
+
+ channel@146 {
+ reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "msm_skin_therm";
+ };
+
+ channel@14a {
+ /* According to datasheet, 0x4a = AMUX1_GPIO = GPIO_02 */
+ reg = <PM7325_ADC7_GPIO1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "ufs_therm";
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ firmware-name = "qcom/qcm6490/qupv3fw.elf";
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ firmware-name = "qcom/qcm6490/qupv3fw.elf";
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcs6490/radxa/dragon-q6a/adsp.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn";
+ status = "okay";
+};
+
+&sdhc_1 {
+ non-removable;
+ no-sd;
+ no-sdio;
+
+ vmmc-supply = <&vreg_l7b_2p96>;
+ vqmmc-supply = <&vreg_l19b_1p8>;
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>;
+ pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>;
+
+ vmmc-supply = <&vreg_l9c_2p96>;
+ vqmmc-supply = <&vreg_l6c_2p96>;
+
+ cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* Pin 11, 29, 31, 32 in GPIO header */
+&spi7 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+/* Pin 19, 21, 23, 24, 26 in GPIO header */
+&spi12 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+/* Pin 22, 33, 36, 37 in GPIO header */
+&spi14 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+&swr0 {
+ status = "okay";
+
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <1 1 2 3>;
+ };
+};
+
+&tlmm {
+ /*
+ * 12-17: reserved for QSPI flash
+ */
+ gpio-reserved-ranges = <12 6>;
+ gpio-line-names =
+ /* GPIO_0 ~ GPIO_3 */
+ "PIN_13", "PIN_15", "", "",
+ /* GPIO_4 ~ GPIO_7 */
+ "", "", "", "",
+ /* GPIO_8 ~ GPIO_11 */
+ "PIN_27", "PIN_28", "", "",
+ /* GPIO_12 ~ GPIO_15 */
+ "", "", "", "",
+ /* GPIO_16 ~ GPIO_19 */
+ "", "", "", "",
+ /* GPIO_20 ~ GPIO_23 */
+ "", "", "PIN_8", "PIN_10",
+ /* GPIO_24 ~ GPIO_27 */
+ "PIN_3", "PIN_5", "PIN_16", "PIN_18",
+ /* GPIO_28 ~ GPIO_31 */
+ "PIN_31", "PIN_11", "PIN_32", "PIN_29",
+ /* GPIO_32 ~ GPIO_35 */
+ "", "", "", "",
+ /* GPIO_36 ~ GPIO_39 */
+ "", "", "", "",
+ /* GPIO_40 ~ GPIO_43 */
+ "", "", "", "",
+ /* GPIO_44 ~ GPIO_47 */
+ "", "", "", "",
+ /* GPIO_48 ~ GPIO_51 */
+ "PIN_21", "PIN_19", "PIN_23", "PIN_24",
+ /* GPIO_52 ~ GPIO_55 */
+ "", "", "", "PIN_26",
+ /* GPIO_56 ~ GPIO_59 */
+ "PIN_33", "PIN_22", "PIN_37", "PIN_36",
+ /* GPIO_60 ~ GPIO_63 */
+ "", "", "", "",
+ /* GPIO_64 ~ GPIO_67 */
+ "", "", "", "",
+ /* GPIO_68 ~ GPIO_71 */
+ "", "", "", "",
+ /* GPIO_72 ~ GPIO_75 */
+ "", "", "", "",
+ /* GPIO_76 ~ GPIO_79 */
+ "", "", "", "",
+ /* GPIO_80 ~ GPIO_83 */
+ "", "", "", "",
+ /* GPIO_84 ~ GPIO_87 */
+ "", "", "", "",
+ /* GPIO_88 ~ GPIO_91 */
+ "", "", "", "",
+ /* GPIO_92 ~ GPIO_95 */
+ "", "", "", "",
+ /* GPIO_96 ~ GPIO_99 */
+ "PIN_7", "PIN_12", "PIN_38", "PIN_40",
+ /* GPIO_100 ~ GPIO_103 */
+ "PIN_35", "", "", "",
+ /* GPIO_104 ~ GPIO_107 */
+ "", "", "", "",
+ /* GPIO_108 ~ GPIO_111 */
+ "", "", "", "",
+ /* GPIO_112 ~ GPIO_115 */
+ "", "", "", "",
+ /* GPIO_116 ~ GPIO_119 */
+ "", "", "", "",
+ /* GPIO_120 ~ GPIO_123 */
+ "", "", "", "",
+ /* GPIO_124 ~ GPIO_127 */
+ "", "", "", "",
+ /* GPIO_128 ~ GPIO_131 */
+ "", "", "", "",
+ /* GPIO_132 ~ GPIO_135 */
+ "", "", "", "",
+ /* GPIO_136 ~ GPIO_139 */
+ "", "", "", "",
+ /* GPIO_140 ~ GPIO_143 */
+ "", "", "", "",
+ /* GPIO_144 ~ GPIO_147 */
+ "", "", "", "",
+ /* GPIO_148 ~ GPIO_151 */
+ "", "", "", "",
+ /* GPIO_152 ~ GPIO_155 */
+ "", "", "", "",
+ /* GPIO_156 ~ GPIO_159 */
+ "", "", "", "",
+ /* GPIO_160 ~ GPIO_163 */
+ "", "", "", "",
+ /* GPIO_164 ~ GPIO_167 */
+ "", "", "", "",
+ /* GPIO_168 ~ GPIO_171 */
+ "", "", "", "",
+ /* GPIO_172 ~ GPIO_174 */
+ "", "", "";
+
+ pcie0_reset_n: pcie0-reset-n-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie0_wake_n: pcie0-wake-n-state {
+ pins = "gpio89";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcie1_reset_n: pcie1-reset-n-state {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie1_wake_n: pcie1-wake-n-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sd_cd: sd-cd-state {
+ pins = "gpio91";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ user_led: user-led-state {
+ pins = "gpio42";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l7b_2p96>;
+ vcc-max-microamp = <800000>;
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <900000>;
+ vccq2-supply = <&vreg_l9b_1p2>;
+ vccq2-max-microamp = <1300000>;
+
+ /* Gear-4 Rate-B is unstable due to board */
+ /* and UFS module design limitations */
+ limit-gear-rate = "rate-a";
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ dr_mode = "host";
+
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&usb3_con_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l10c_0p88>;
+ vdda33-supply = <&vreg_l2b_3p072>;
+ vdda18-supply = <&vreg_l1c_1p8>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l6b_1p2>;
+ vdda-pll-supply = <&vreg_l1b_0p912>;
+
+ /delete-property/ orientation-switch;
+
+ status = "okay";
+
+ ports {
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /delete-node/ endpoint;
+
+ /* RX0/TX0 is statically connected to RA620 bridge */
+ usb_1_qmpphy_out_dp: endpoint@0 {
+ reg = <0>;
+
+ data-lanes = <0 1>;
+ remote-endpoint = <&hdmi_bridge_in>;
+ };
+
+ /* RX1/TX1 is statically connected to USB-A port */
+ usb_1_qmpphy_out_usb: endpoint@1 {
+ reg = <1>;
+
+ data-lanes = <2 3>;
+ remote-endpoint = <&usb3_con_ss_in>;
+ };
+ };
+ };
+};
+
+&usb_2 {
+ dr_mode = "host";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ /* Onboard USB 2.0 hub */
+ usb_hub_2_x: hub@1 {
+ compatible = "usb1a40,0101";
+ reg = <1>;
+ vdd-supply = <&vcc_5v_peri>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ usb_hub_2_1: endpoint {
+ remote-endpoint = <&usb2_1_connector>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_hub_2_2: endpoint {
+ remote-endpoint = <&usb2_2_connector>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ usb_hub_2_3: endpoint {
+ remote-endpoint = <&usb2_3_connector>;
+ };
+ };
+ };
+
+ /* FCU760K Wi-Fi & Bluetooth module */
+ wifi@4 {
+ compatible = "usba69c,8d80";
+ reg = <4>;
+ };
+ };
+};
+
+&usb_2_hsphy {
+ vdda-pll-supply = <&vreg_l10c_0p88>;
+ vdda33-supply = <&vreg_l2b_3p072>;
+ vdda18-supply = <&vreg_l1c_1p8>;
+
+ status = "okay";
+};
+
+&venus {
+ status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in sc7280.dtsi */
+&dp_hot_plug_det {
+ bias-disable;
+};
+
+&pcie0_clkreq_n {
+ bias-pull-up;
+ drive-strength = <2>;
+};
+
+&pcie1_clkreq_n {
+ bias-pull-up;
+ drive-strength = <2>;
+};
+
+&sdc1_clk {
+ bias-disable;
+ drive-strength = <16>;
+};
+
+&sdc1_cmd {
+ bias-pull-up;
+ drive-strength = <10>;
+};
+
+&sdc1_data {
+ bias-pull-up;
+ drive-strength = <10>;
+};
+
+&sdc1_rclk {
+ bias-pull-down;
+};
+
+&sdc2_clk {
+ bias-disable;
+ drive-strength = <16>;
+};
+
+&sdc2_cmd {
+ bias-pull-up;
+ drive-strength = <10>;
+};
+
+&sdc2_data {
+ bias-pull-up;
+ drive-strength = <10>;
+};
--
2.53.0
^ permalink raw reply related
* [PATCH 09/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Align reserved-memory with latest firmware map
From: Xilin Wu @ 2026-04-07 15:20 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
The current board DTS no longer matches the reserved-memory carveouts
used by the latest official Dragon Q6A firmware. Update the memory map
to keep the DTS in sync with firmware expectations.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 43 +++++++++-------------
1 file changed, 17 insertions(+), 26 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index fe3f60f8ed5a..5679f38de5b3 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -22,7 +22,9 @@
#include "qcs6490-audioreach.dtsi"
/delete-node/ &adsp_mem;
+/delete-node/ &adsp_rpc_remote_heap_mem;
/delete-node/ &cdsp_mem;
+/delete-node/ &gpu_zap_mem;
/delete-node/ &ipa_fw_mem;
/delete-node/ &mpss_mem;
/delete-node/ &remoteproc_mpss;
@@ -33,7 +35,6 @@
/delete-node/ &wlan_ce_mem;
/delete-node/ &wlan_fw_mem;
/delete-node/ &wpss_mem;
-/delete-node/ &xbl_mem;
/ {
model = "Radxa Dragon Q6A";
@@ -193,43 +194,33 @@ user-led {
};
reserved-memory {
- xbl_mem: xbl@80700000 {
- reg = <0x0 0x80700000 0x0 0x100000>;
+ lpass_ml_mem: lpass-ml@81800000 {
+ reg = <0x0 0x81800000 0x0 0xf00000>;
no-map;
};
- cdsp_secure_heap_mem: cdsp-secure-heap@81800000 {
- reg = <0x0 0x81800000 0x0 0x1e00000>;
+ cdsp_secure_heap_mem: cdsp-secure-heap@82700000 {
+ reg = <0x0 0x82700000 0x0 0x10000>;
no-map;
};
- camera_mem: camera@84300000 {
- reg = <0x0 0x84300000 0x0 0x500000>;
+ adsp_mem: adsp@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0x2800000>;
no-map;
};
- adsp_mem: adsp@84800000 {
- reg = <0x0 0x84800000 0x0 0x2800000>;
+ cdsp_mem: cdsp@8e000000 {
+ reg = <0x0 0x8e000000 0x0 0x1e00000>;
no-map;
};
- cdsp_mem: cdsp@87000000 {
- reg = <0x0 0x87000000 0x0 0x1e00000>;
+ video_mem: video@8fe00000 {
+ reg = <0x0 0x8fe00000 0x0 0x500000>;
no-map;
};
- video_mem: video@88e00000 {
- reg = <0x0 0x88e00000 0x0 0x700000>;
- no-map;
- };
-
- cvp_mem: cvp@89500000 {
- reg = <0x0 0x89500000 0x0 0x500000>;
- no-map;
- };
-
- gpu_microcode_mem: gpu-microcode@89a00000 {
- reg = <0x0 0x89a00000 0x0 0x2000>;
+ gpu_zap_mem: zap@90300000 {
+ reg = <0x0 0x90300000 0x0 0x5000>;
no-map;
};
@@ -249,12 +240,12 @@ qtee_mem: qtee@c1300000 {
};
trusted_apps_mem: trusted-apps@c1800000 {
- reg = <0x0 0xc1800000 0x0 0x1c00000>;
+ reg = <0x0 0xc1800000 0x0 0x2200000>;
no-map;
};
- debug_vm_mem: debug-vm@d0600000 {
- reg = <0x0 0xd0600000 0x0 0x100000>;
+ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@c6500000 {
+ reg = <0x0 0xc6500000 0x0 0x800000>;
no-map;
};
};
--
2.53.0
^ permalink raw reply related
* [PATCH 08/12] arm64: dts: qcom: kodiak: Mark secondary USB controller as wakeup source
From: Xilin Wu @ 2026-04-07 15:20 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu, Stephen Chen
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
From: Stephen Chen <stephen@radxa.com>
Mark the secondary USB controller (usb_2) as a wakeup source so that it
can be used to wake the system from suspend.
Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 3a30126af3d4..940ec799e905 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -4404,6 +4404,7 @@ usb_2: usb@8c00000 {
phy-names = "usb2-phy";
maximum-speed = "high-speed";
usb-role-switch;
+ wakeup-source;
port {
usb2_role_switch: endpoint {
--
2.53.0
^ permalink raw reply related
* [PATCH 07/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Correct GPIO_27 label
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu, Stephen Chen
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
From: Stephen Chen <stephen@radxa.com>
The label of GPIO_27 is wrong. Fix it.
Fixes: ef254b12ec60 ("arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A")
Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 8d6bb4b0724b..fe3f60f8ed5a 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -905,7 +905,7 @@ &tlmm {
/* GPIO_20 ~ GPIO_23 */
"", "", "PIN_8", "PIN_10",
/* GPIO_24 ~ GPIO_27 */
- "PIN_3", "PIN_5", "PIN_16", "PIN_27",
+ "PIN_3", "PIN_5", "PIN_16", "PIN_18",
/* GPIO_28 ~ GPIO_31 */
"PIN_31", "PIN_11", "PIN_32", "PIN_29",
/* GPIO_32 ~ GPIO_35 */
--
2.53.0
^ permalink raw reply related
* [PATCH 04/12] arm64: dts: qcom: kodiak: Add I2C aliases for CCI
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu, Stephen Chen
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
From: Stephen Chen <stephen@radxa.com>
Add I2C bus aliases (i2c16-i2c19) for the CCI (Camera Control Interface)
I2C buses, allowing a stable numbering of these buses independent of
probe order.
Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 988ca5f7c8a0..3a30126af3d4 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -57,6 +57,10 @@ aliases {
i2c13 = &i2c13;
i2c14 = &i2c14;
i2c15 = &i2c15;
+ i2c16 = &cci0_i2c0;
+ i2c17 = &cci0_i2c1;
+ i2c18 = &cci1_i2c0;
+ i2c19 = &cci1_i2c1;
mmc1 = &sdhc_1;
mmc2 = &sdhc_2;
spi0 = &spi0;
--
2.53.0
^ permalink raw reply related
* [PATCH 06/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Drop QSPI node and reserve its pins
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
The latest official boot firmware configures TrustZone to restrict
direct access to the QSPI controller. Any attempt to access it from
the non-secure world causes an immediate board reset.
Remove the QSPI flash node and its associated pinctrl states, mark
GPIOs 12-17 as reserved, and protect the QSPI clocks in the GCC
node to prevent the kernel from touching this hardware.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 60 +++-------------------
1 file changed, 7 insertions(+), 53 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 91f1b4f57915..8d6bb4b0724b 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -513,6 +513,9 @@ &gcc {
<GCC_MSS_Q6SS_BOOT_CLK_SRC>,
<GCC_MSS_Q6_MEMNOC_AXI_CLK>,
<GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
<GCC_SEC_CTRL_CLK_SRC>,
<GCC_WPSS_AHB_BDG_MST_CLK>,
<GCC_WPSS_AHB_CLK>,
@@ -745,28 +748,6 @@ &pon_pwrkey {
status = "okay";
};
-&qspi {
- /* It's not possible to use QSPI with iommu */
- /* due to an error in qcom_smmu_write_s2cr */
- /delete-property/ iommus;
-
- pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>,
- <&qspi_data1>, <&qspi_data23>;
- pinctrl-1 = <&qspi_sleep>;
- pinctrl-names = "default", "sleep";
-
- status = "okay";
-
- spi_flash: flash@0 {
- compatible = "winbond,w25q256", "jedec,spi-nor";
- reg = <0>;
-
- spi-max-frequency = <104000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- };
-};
-
&qupv3_id_0 {
firmware-name = "qcom/qcm6490/qupv3fw.elf";
status = "okay";
@@ -906,6 +887,10 @@ wcd_tx: codec@0,3 {
};
&tlmm {
+ /*
+ * 12-17: reserved for QSPI flash
+ */
+ gpio-reserved-ranges = <12 6>;
gpio-line-names =
/* GPIO_0 ~ GPIO_3 */
"PIN_13", "PIN_15", "", "",
@@ -1024,12 +1009,6 @@ pcie1_wake_n: pcie1-wake-n-state {
bias-pull-up;
};
- qspi_sleep: qspi-sleep-state {
- pins = "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17";
- function = "gpio";
- output-disable;
- };
-
sd_cd: sd-cd-state {
pins = "gpio91";
function = "gpio";
@@ -1210,31 +1189,6 @@ &pcie1_clkreq_n {
drive-strength = <2>;
};
-&qspi_clk {
- bias-disable;
- drive-strength = <16>;
-};
-
-&qspi_cs0 {
- bias-disable;
- drive-strength = <8>;
-};
-
-&qspi_data0 {
- bias-disable;
- drive-strength = <8>;
-};
-
-&qspi_data1 {
- bias-disable;
- drive-strength = <8>;
-};
-
-&qspi_data23 {
- bias-disable;
- drive-strength = <8>;
-};
-
&sdc1_clk {
bias-disable;
drive-strength = <16>;
--
2.53.0
^ permalink raw reply related
* [PATCH 05/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Use board-specific CDSP firmware
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
The official boot firmware for Dragon Q6A has been switched to the
Qualcomm WP (Windows) boot firmware. Use the matching board-specific
CDSP firmware instead of the generic one so that the DSP firmware stack
remains compatible with the new boot firmware.
The corresponding custom DSP firmware has already been added to
linux-firmware:
https://gitlab.com/kernel-firmware/linux-firmware/-/merge_requests/882
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 8d649b3a1cfa..91f1b4f57915 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -783,7 +783,7 @@ &remoteproc_adsp {
};
&remoteproc_cdsp {
- firmware-name = "qcom/qcs6490/cdsp.mbn";
+ firmware-name = "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn";
status = "okay";
};
--
2.53.0
^ permalink raw reply related
* [PATCH 01/12] firmware: qcom: scm: Allow QSEECOM for Radxa Dragon Q6A
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
add "radxa,dragon-q6a" as compatible device for QSEECOM
This is required to get access to efivars and uefi boot loader support.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
drivers/firmware/qcom/qcom_scm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index 9b06a69d3a6d..55b18463560a 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -2319,6 +2319,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = {
{ .compatible = "qcom,x1e80100-crd" },
{ .compatible = "qcom,x1e80100-qcp" },
{ .compatible = "qcom,x1p42100-crd" },
+ { .compatible = "radxa,dragon-q6a" },
{ }
};
--
2.53.0
^ permalink raw reply related
* [PATCH 02/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
Add and enable UFS related nodes for this board.
Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design
limitations. UFS on this board is stable when working at Gear-4 Rate-A.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index bb5a42b038f1..c961d3ec625f 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -959,6 +959,29 @@ &uart5 {
status = "okay";
};
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l7b_2p96>;
+ vcc-max-microamp = <800000>;
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <900000>;
+ vccq2-supply = <&vreg_l9b_1p2>;
+ vccq2-max-microamp = <1300000>;
+
+ /* Gear-4 Rate-B is unstable due to board */
+ /* and UFS module design limitations */
+ limit-gear-rate = "rate-a";
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
&usb_2 {
dr_mode = "host";
--
2.53.0
^ permalink raw reply related
* [PATCH 03/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
This board doesn't feature a regular Type-C port. The usb_1_qmpphy's
RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0
pair is connected to the RA620 DP-to-HDMI bridge.
Add and enable the nodes for the features to work.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 152 +++++++++++++++++++++
1 file changed, 152 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index c961d3ec625f..8d649b3a1cfa 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -111,6 +111,71 @@ usb2_3_connector: endpoint {
};
};
+ usb3_con: connector {
+ compatible = "usb-a-connector";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb3_con_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb3_con_ss_in: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_out_usb>;
+ };
+ };
+ };
+ };
+
+ hdmi-bridge {
+ compatible = "radxa,ra620";
+
+ pinctrl-0 = <&dp_hot_plug_det>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_bridge_in: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_out_dp>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_bridge_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_bridge_out>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -521,6 +586,21 @@ &lpass_va_macro {
status = "okay";
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp {
+ sound-name-prefix = "Display Port0";
+
+ status = "okay";
+};
+
+&mdss_dp_out {
+ data-lanes = <0 1>;
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+};
+
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
@@ -738,6 +818,22 @@ &sound {
"AMIC2", "MIC BIAS2",
"TX SWR_ADC1", "ADC2_OUTPUT";
+ dp0-dai-link {
+ link-name = "DP0 Playback";
+
+ codec {
+ sound-dai = <&mdss_dp>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
wcd-playback-dai-link {
link-name = "WCD Playback";
@@ -982,6 +1078,58 @@ &ufs_mem_phy {
status = "okay";
};
+&usb_1 {
+ dr_mode = "host";
+
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&usb3_con_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l10c_0p88>;
+ vdda33-supply = <&vreg_l2b_3p072>;
+ vdda18-supply = <&vreg_l1c_1p8>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l6b_1p2>;
+ vdda-pll-supply = <&vreg_l1b_0p912>;
+
+ /delete-property/ orientation-switch;
+
+ status = "okay";
+
+ ports {
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /delete-node/ endpoint;
+
+ /* RX0/TX0 is statically connected to RA620 bridge */
+ usb_1_qmpphy_out_dp: endpoint@0 {
+ reg = <0>;
+
+ data-lanes = <0 1>;
+ remote-endpoint = <&hdmi_bridge_in>;
+ };
+
+ /* RX1/TX1 is statically connected to USB-A port */
+ usb_1_qmpphy_out_usb: endpoint@1 {
+ reg = <1>;
+
+ data-lanes = <2 3>;
+ remote-endpoint = <&usb3_con_ss_in>;
+ };
+ };
+ };
+};
+
&usb_2 {
dr_mode = "host";
@@ -1048,6 +1196,10 @@ &venus {
};
/* PINCTRL - additions to nodes defined in sc7280.dtsi */
+&dp_hot_plug_det {
+ bias-disable;
+};
+
&pcie0_clkreq_n {
bias-pull-up;
drive-strength = <2>;
--
2.53.0
^ permalink raw reply related
* [PATCH 00/12] arm64: dts: qcom: qcs6490: Radxa Dragon Q6A feature enablement and fixes
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu, Stephen Chen
This series brings the Radxa Dragon Q6A (QCS6490) board support up to
date with the latest official firmware and enables additional hardware.
Fixes and alignment with latest firmware:
- Allow QSEECOM for UEFI/efivars support
- Align reserved-memory with the latest firmware memory map
- Drop QSPI node now restricted by TrustZone
- Switch to board-specific CDSP firmware matching new WP boot firmware
- Correct GPIO_27 label
Hardware enablement:
- Enable UFS controller (Gear-4 Rate-A)
- Enable USB 3.0 and HDMI (via DP-to-HDMI bridge)
- Mark secondary USB controller as wakeup source
- Add I2C aliases for CCI buses
Variant for LPASS CPU audio:
- Factor out common board dtsi for sharing between variants
- Add dt-bindings for Dragon Q6A sound card
- Add LPASS CPU audio variant for EL2 direct hardware access
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
Stephen Chen (3):
arm64: dts: qcom: kodiak: Add I2C aliases for CCI
arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Correct GPIO_27 label
arm64: dts: qcom: kodiak: Mark secondary USB controller as wakeup source
Xilin Wu (9):
firmware: qcom: scm: Allow QSEECOM for Radxa Dragon Q6A
arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller
arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports
arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Use board-specific CDSP firmware
arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Drop QSPI node and reserve its pins
arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Align reserved-memory with latest firmware map
arm64: dts: qcom: qcs6490-radxa-dragon-q6a: factor out common board dtsi
ASoC: dt-bindings: google,sc7280-herobrine: Add Radxa Dragon Q6A sound card
arm64: dts: qcom: qcs6490-radxa-dragon-q6a: add LPASS CPU audio variant
.../bindings/sound/google,sc7280-herobrine.yaml | 9 +-
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/kodiak.dtsi | 5 +
.../qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts | 131 +++
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 1047 +-----------------
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi | 1137 ++++++++++++++++++++
drivers/firmware/qcom/qcom_scm.c | 1 +
7 files changed, 1300 insertions(+), 1031 deletions(-)
---
base-commit: 816f193dd0d95246f208590924dd962b192def78
change-id: 20260407-dragon-q6a-feat-fixes-6a30f6ba8b18
Best regards,
--
Xilin Wu <sophon@radxa.com>
^ permalink raw reply
* Re: [PATCH v2 2/3] remoteproc: imx_rproc: Pass bootaddr to SM CPU/LMM reset vector
From: Mathieu Poirier @ 2026-04-07 15:19 UTC (permalink / raw)
To: Peng Fan
Cc: Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Daniel Baluta, linux-remoteproc, devicetree, imx,
linux-arm-kernel, linux-kernel, Peng Fan
In-Reply-To: <acs2PAZq2k3zjmDW@shlinux89>
On Tue, Mar 31, 2026 at 10:49:32AM +0800, Peng Fan wrote:
> On Mon, Mar 30, 2026 at 10:22:35AM -0600, Mathieu Poirier wrote:
> >On Fri, Mar 27, 2026 at 10:42:03AM +0800, Peng Fan (OSS) wrote:
> >> From: Peng Fan <peng.fan@nxp.com>
> >>
> >> Cortex-M[7,33] processors use a fixed reset vector table format:
> >>
> >> 0x00 Initial SP value
> >> 0x04 Reset vector
> >> 0x08 NMI
> >> 0x0C ...
> >> ...
> >> IRQ[n]
> >>
> >> In ELF images, the corresponding layout is:
> >>
> >> reset_vectors: --> hardware reset address
> >> .word __stack_end__
> >> .word Reset_Handler
> >> .word NMI_Handler
> >> .word HardFault_Handler
> >> ...
> >> .word UART_IRQHandler
> >> .word SPI_IRQHandler
> >> ...
> >>
> >> Reset_Handler: --> ELF entry point address
> >> ...
> >>
> >> The hardware fetches the first two words from reset_vectors and populates
> >> SP with __stack_end__ and PC with Reset_Handler. Execution proceeds from
> >> Reset_Handler.
> >>
> >> However, the ELF entry point does not always match the hardware reset
> >> address. For example, on i.MX94 CM33S:
> >>
> >> ELF entry point: 0x0ffc211d
> >> hardware reset base: 0x0ffc0000 (default reset value, sw programmable)
> >>
> >
> >But why? Why can't the ELF image be set to the right reset base?
>
> Per zephyr general link script[1]:
> ENTRY(CONFIG_KERNEL_ENTRY)
>
> CONFIG_KERNEL_ENTRY(_start) is the first instruction that Cortex-M starts to
> execute.
>
> config KERNEL_ENTRY
> string "Kernel entry symbol"
> default "__start"
> help
> Code entry symbol, to be set at linking phase.
>
> The hardware reset base is different: it is the address where the hardware
> fetches the initial MSP and PC values from the vector table. Hardware uses
> this base to initialize the stack pointer and program counter, and only then
> does the Cortex‑M begin execution at the reset handler.
That part is clear.
>
> Aligning the ELF entry point with the hardware reset base on Cortex‑M systems
> is possible, but it comes with several risks.
I'm not asking to align the ELF entry point with the hardware reset base. All I
want is to have the correct start address embedded in the ELF file to avoid
having to use a mask.
> 1, Semantic mismatch (ELF vs. hardware behavior)
> 2, Debuggers may attempt to set breakpoints or start execution at the entry symbol
>
> [1] https://elixir.bootlin.com/zephyr/v4.4.0-rc1/source/include/zephyr/arch/arm/cortex_m/scripts/linker.ld#L103
>
> Regards
> Peng.
> >
^ permalink raw reply
* [PATCH v2 2/2] arm64: dts: qcom: milos: Add IMEM node
From: Luca Weiss @ 2026-04-07 15:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss
In-Reply-To: <20260407-milos-imem-v2-0-5084a490340c@fairphone.com>
Add a node for the IMEM found on Milos, which contains pil-reloc-info
and the modem tables for IPA, among others.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Not happy about the names of the subnodes. pil-reloc-sram is not allowed
it seems. Glymur calls it "pil-sram@94c", not sure this is wanted?
Please advice.
---
arch/arm64/boot/dts/qcom/milos.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 4a64a98a434b..0c69d5810f5e 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -2289,6 +2289,26 @@ scl-pins {
};
};
+ sram@14680000 {
+ compatible = "qcom,milos-imem", "mmio-sram";
+ reg = <0x0 0x14680000 0x0 0x2c000>;
+ ranges = <0 0 0x14680000 0x2c000>;
+
+ no-memory-wc;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pilreloc-sram@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+
+ ipa_modem_tables: modemtables-sram@3000 {
+ reg = <0x3000 0x2000>;
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x15000000 0x0 0x100000>;
--
2.53.0
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: sram: Document qcom,milos-imem
From: Luca Weiss @ 2026-04-07 15:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss
In-Reply-To: <20260407-milos-imem-v2-0-5084a490340c@fairphone.com>
Add compatible for Milos SoC IMEM.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/sram/sram.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml
index c451140962c8..cb2e11c73d98 100644
--- a/Documentation/devicetree/bindings/sram/sram.yaml
+++ b/Documentation/devicetree/bindings/sram/sram.yaml
@@ -35,6 +35,7 @@ properties:
- nvidia,tegra194-sysram
- nvidia,tegra234-sysram
- qcom,kaanapali-imem
+ - qcom,milos-imem
- qcom,rpm-msg-ram
- rockchip,rk3288-pmu-sram
--
2.53.0
^ permalink raw reply related
* [PATCH v2 0/2] Describe IMEM on Milos
From: Luca Weiss @ 2026-04-07 15:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss
Add a compatible and describe the IMEM for the Milos SoC.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes in v2:
- Use mmio-sram for describing IMEM
- Link to v1: https://patch.msgid.link/20260403-milos-imem-v1-0-4244ebb47017@fairphone.com
---
Luca Weiss (2):
dt-bindings: sram: Document qcom,milos-imem
arm64: dts: qcom: milos: Add IMEM node
Documentation/devicetree/bindings/sram/sram.yaml | 1 +
arch/arm64/boot/dts/qcom/milos.dtsi | 20 ++++++++++++++++++++
2 files changed, 21 insertions(+)
---
base-commit: 83acad05dee54a5cff0c98dd7962e55d4c6b145a
change-id: 20260403-milos-imem-3a034224946a
Best regards,
--
Luca Weiss <luca.weiss@fairphone.com>
^ permalink raw reply
* Re: [PATCH] dt-bindings: display: bridge: lt9211: Require data-lanes on DSI input ports
From: Marek Vasut @ 2026-04-07 14:51 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: devicetree, Andrzej Hajda, Conor Dooley, David Airlie,
Jernej Skrabec, Jonas Karlman, Krzysztof Kozlowski,
Laurent Pinchart, Maarten Lankhorst, Maxime Ripard,
Neil Armstrong, Rob Herring, Robert Foss, Simona Vetter,
Thomas Zimmermann, dri-devel, linux-kernel
In-Reply-To: <20260407-invaluable-pretty-leopard-1e8dfc@quoll>
On 4/7/26 10:00 AM, Krzysztof Kozlowski wrote:
>> NOTE: For example Linux kernel driver does already use that information
>> and fails to probe if it is missing. There are currently no intree
>
> The first sentence must be part of the commit msg. That is important
> reason why you are doing this... but I don't see how you achieve any of
> this. Look:
>
>
>> users for this binding, so no new warnings will be generated once
>> this is applied, but a new user is about to be added.
>
> What warnings? How?
There are no in-tree users of this binding, so no DT checker warnings
will be produced on existing in-tree DTs. I am in the process of adding
a DTO which uses this binding now in arm64: dts: imx8mm: imx8mp: Add
DTOs for Data Modul i.MX8M Mini and Plus eDM SBC
>> ---
>> .../display/bridge/lontium,lt9211.yaml | 37 ++++++++++++++++++-
>> 1 file changed, 35 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml
>> index 9a6e9b25d14a9..5264fb2b68b78 100644
>> --- a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml
>> +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml
>> @@ -36,18 +36,50 @@ properties:
>>
>> properties:
>> port@0:
>> - $ref: /schemas/graph.yaml#/properties/port
>> + $ref: /schemas/graph.yaml#/$defs/port-base
>
> OK, that's correct.
>
>> + unevaluatedProperties: false
>> description:
>> Primary MIPI DSI port-1 for MIPI input or
>> LVDS port-1 for LVDS input or DPI input.
>>
>> + properties:
>> + endpoint:
>> + $ref: /schemas/media/video-interfaces.yaml#
>> + unevaluatedProperties: false
>
> That's correct.
>
>> +
>> + properties:
>> + data-lanes:
>> + description: array of physical DSI data lane indexes.
>> + minItems: 1
>> + items:
>> + - const: 1
>> + - const: 2
>> + - const: 3
>> + - const: 4
>
> That's almost redundant in this context - it was already there - and the
> point is that it solves noting in the problem you had. Binding still
> does not validate the ABI and does not match it, still.
>
> Since commit foo bar, driver needs data-lanes, so what you need to do is
> allow them and to require them. You can also specify their constraints
> if device can be configured multiple ways, up to 4 lanes.
Please pardon my ignorance, what exactly do you propose I change in this
patch ?
^ permalink raw reply
* [PATCH] of: fdt: skip KHO when booting as crash kernel
From: Evangelos Petrongonas @ 2026-04-07 15:06 UTC (permalink / raw)
To: Rob Herring, Saravana Kannan
Cc: Evangelos Petrongonas, Mike Rapoport (Microsoft), Changyuan Lyu,
Alexander Graf, Pasha Tatashin, Pratyush Yadav, Andrew Morton,
devicetree, kexec, linux-kernel, nh-open-source
KHO preserves state across kexec by passing a KHO-specific FDT pointer
and scratch memory region to the incoming kernel. These point to
physical addresses in the outgoing kernel's memory that the incoming
kernel is expected to access and restore from. This falls apart when
the incoming kernel is a crash kernel as the crash kernel can run in a
small reserved memory region. The scratch regions can sit outside this
reservation, so the end result is quite unpleasant.
kho_add_chosen() unconditionally propagates KHO properties into
the device tree for all kexec image types, including crash images. The
crash kernel then discovers these properties during
early_init_dt_check_kho(), records the stale physical addresses via
kho_populate(), and later faults in kho_memory_init() when it tries
phys_to_virt() on the KHO FDT address:
Unable to handle kernel paging request at virtual address xxxxxxxx
...
fdt_offset_ptr+...
fdt_check_node_offset_+...
fdt_first_property_offset+...
fdt_get_property_namelen_+...
fdt_getprop+...
kho_memory_init+...
mm_core_init+...
start_kernel+...
kho_locate_mem_hole() already skips KHO logic for KEXEC_TYPE_CRASH
images, but the DT property propagation and the consumer side were both
missing the same guard.
Fix this at both ends. Have kho_add_chosen() skip writing KHO properties
for crash images so the stale pointers never reach the crash kernel's
device tree. Also have early_init_dt_check_kho() bail out when
is_kdump_kernel() is true. This way even if KHO properties end up in
the DT through some other path, the crash kernel will not act on them.
Fixes: 274cdcb1c004 ("arm64: add KHO support")
Signed-off-by: Evangelos Petrongonas <epetron@amazon.de>
---
I think we should backport the fix on KHO compatible versions (6.16+),
hence the "Fixes:" tag. Tested on an arm64 system.
drivers/of/fdt.c | 3 +++
drivers/of/kexec.c | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index 43a0944ca462..77018ec99fc8 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -926,6 +926,9 @@ static void __init early_init_dt_check_kho(void)
if (!IS_ENABLED(CONFIG_KEXEC_HANDOVER) || (long)node < 0)
return;
+ if (is_kdump_kernel())
+ return;
+
if (!of_flat_dt_get_addr_size(node, "linux,kho-fdt",
&fdt_start, &fdt_size))
return;
diff --git a/drivers/of/kexec.c b/drivers/of/kexec.c
index c4cf3552c018..b95f0b386684 100644
--- a/drivers/of/kexec.c
+++ b/drivers/of/kexec.c
@@ -271,7 +271,8 @@ static int kho_add_chosen(const struct kimage *image, void *fdt, int chosen_node
if (ret && ret != -FDT_ERR_NOTFOUND)
return ret;
- if (!image->kho.fdt || !image->kho.scratch)
+ if (!image->kho.fdt || !image->kho.scratch ||
+ image->type == KEXEC_TYPE_CRASH)
return 0;
fdt_mem = image->kho.fdt;
--
2.43.0
Amazon Web Services Development Center Germany GmbH
Tamara-Danz-Str. 13
10243 Berlin
Geschaeftsfuehrung: Christof Hellmis, Andreas Stieger
Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B
Sitz: Berlin
Ust-ID: DE 365 538 597
^ permalink raw reply related
* Re: [PATCH 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
From: Dmitry Baryshkov @ 2026-04-07 15:01 UTC (permalink / raw)
To: Joe Sandom
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260407113925.4imd3lxkcrq47pu3@linaro>
On Tue, Apr 07, 2026 at 12:39:25PM +0100, Joe Sandom wrote:
> On Sun, Apr 05, 2026 at 12:20:23AM +0300, Dmitry Baryshkov wrote:
> > On Sat, Apr 04, 2026 at 10:50:58AM +0100, Joe Sandom via B4 Relay wrote:
> > > +
> > > + wcn7850-pmu {
> > > + compatible = "qcom,wcn7850-pmu";
> > > +
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>;
> >
> > swctrl?
> Bundled into bt_default since it's tied to BT
It's not. It's either WiFi or BT.
> >
> > > +
> > > + wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
> > > + bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
> >
[...]
> > > + iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
> > > + <0x100 &apps_smmu 0x1401 0x1>,
> > > + <0x208 &apps_smmu 0x1402 0x1>,
> > > + <0x210 &apps_smmu 0x1403 0x1>,
> > > + <0x218 &apps_smmu 0x1404 0x1>,
> > > + <0x300 &apps_smmu 0x1407 0x1>,
> > > + <0x400 &apps_smmu 0x1408 0x1>,
> > > + <0x500 &apps_smmu 0x140c 0x1>,
> > > + <0x501 &apps_smmu 0x140e 0x1>;
> > > +
> > > + /delete-property/ msi-map;
> >
> > Why?
> I tried extending the msi-map to cover the RIDs from the QPS615
> PCIe switch (matching the iommu-map entries), but this caused
> ITS MAPD command timeouts. From what I could gather, deleting
> msi-map forces the PCIe controller to fall back to the internal
> iMSI-RX module, where this worked properly.
>
> For reference, I checked the RB3gen2 since it also uses a QPS615
> and there doesn't seem to be any msi-map defined (in kodiak.dtsi).
>
> Any recommendations to resolve this properly?
Maybe Mani knows. Please mention this in the commit message at least.
> >
> > > +
> > > + status = "okay";
> > > +};
> > > +
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC
From: Biju @ 2026-04-07 14:57 UTC (permalink / raw)
To: Fabrizio Castro, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-spi, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
In-Reply-To: <20260407145753.101840-1-biju.das.jz@bp.renesas.com>
From: Biju Das <biju.das.jz@bp.renesas.com>
Document RSPI IP found on the RZ/G3L SoC. The RSPI IP is compatible with
the RZ/V2H RSPI IP, but has 2 clocks compared to 3 on RZ/V2H.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
* Added ordered DMA names for the dma-names property.
* Dropped the tag
v1->v2:
* Collected tag
---
.../bindings/spi/renesas,rzv2h-rspi.yaml | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
index 2c9045fd51de..6f4bb83a549f 100644
--- a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
+++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
@@ -13,6 +13,7 @@ properties:
compatible:
oneOf:
- enum:
+ - renesas,r9a08g046-rspi # RZ/G3L
- renesas,r9a09g057-rspi # RZ/V2H(P)
- renesas,r9a09g077-rspi # RZ/T2H
- items:
@@ -90,6 +91,33 @@ required:
allOf:
- $ref: spi-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a08g046-rspi
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: tclk
+ dmas:
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+ required:
+ - resets
+ - reset-names
+
- if:
properties:
compatible:
--
2.43.0
^ permalink raw reply related
* [PATCH v3 0/2] Add Renesas RZ/G3L RSPI support
From: Biju @ 2026-04-07 14:57 UTC (permalink / raw)
To: Fabrizio Castro, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-spi, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
This patch series adds binding and driver support for RSPI IP found on the
RZ/G3L SoC. The RSPI is compatible with RZ/V2H RSPI, but has 2 clocks
compared to 3 on RZ/V2H.
v2->v3:
* Added ordered DMA names for the dma-names property.
* Dropped the tag from bindings as there is a change related to dma-names
property.
v1->v2:
* Rebased to next
* Collected tags
Biju Das (2):
dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC
spi: rzv2h-rspi: Add support for RZ/G3L (R9A08G046)
.../bindings/spi/renesas,rzv2h-rspi.yaml | 28 +++++++++++++++++++
drivers/spi/spi-rzv2h-rspi.c | 8 ++++++
2 files changed, 36 insertions(+)
--
2.43.0
^ permalink raw reply
* Re: [PATCH v5 2/2] iio: dac: ad5706r: Add support for AD5706R DAC
From: Andy Shevchenko @ 2026-04-07 14:46 UTC (permalink / raw)
To: Alexis Czezar Torreno
Cc: Lars-Peter Clausen, Michael Hennerich, Jonathan Cameron,
David Lechner, Nuno Sá, Andy Shevchenko, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-iio, devicetree,
linux-kernel
In-Reply-To: <20260407-dev_ad5706r-v5-2-a4c7737b6ae9@analog.com>
On Tue, Apr 07, 2026 at 11:39:45AM +0800, Alexis Czezar Torreno wrote:
> Add support for the Analog Devices AD5706R, a 4-channel 16-bit
> current output digital-to-analog converter with SPI interface.
>
> Features:
> - 4 independent DAC channels
> - Hardware and software LDAC trigger
> - Configurable output range
> - PWM-based LDAC control
> - Dither and toggle modes
> - Dynamically configurable SPI speed
Mostly okay, see minor comments below, the main one is about treating void * as
__be16/__be32 * without any validation.
...
> +static int ad5706r_regmap_write(void *context, const void *data, size_t count)
> +{
> + struct ad5706r_state *st = context;
> + unsigned int num_bytes, val;
> + u16 reg;
> +
> + reg = get_unaligned_be16(data);
> + num_bytes = ad5706r_reg_len(reg);
> +
> + struct spi_transfer xfer = {
> + .tx_buf = st->tx_buf,
> + .len = num_bytes + 2,
> + };
> + val = get_unaligned_be32(data);
Is it safe? The data is void *, no size of it is counted here...
> + put_unaligned_be32(val, st->tx_buf);
> +
> + /* For single byte, copy the data to the correct position */
> + if (num_bytes == AD5706R_SINGLE_BYTE_LEN)
> + st->tx_buf[2] = st->tx_buf[3];
> +
> + return spi_sync_transfer(st->spi, &xfer, 1);
> +}
> +static int ad5706r_regmap_read(void *context, const void *reg_buf,
> + size_t reg_size, void *val_buf, size_t val_size)
> +{
> + struct ad5706r_state *st = context;
> + unsigned int num_bytes;
> + u16 reg, cmd, val;
> + int ret;
> +
> + reg = get_unaligned_be16(reg_buf);
> + num_bytes = ad5706r_reg_len(reg);
> +
> + /* Full duplex, device responds immediately after command */
> + struct spi_transfer xfer = {
> + .tx_buf = st->tx_buf,
> + .rx_buf = st->rx_buf,
> + .len = 2 + num_bytes,
> + };
> +
> + cmd = AD5706R_RD_MASK | (reg & AD5706R_ADDR_MASK);
> + put_unaligned_be16(cmd, st->tx_buf);
For the consistency's sake use &st->tx_buf[0].
> + put_unaligned_be16(0, &st->tx_buf[2]);
> +
> + ret = spi_sync_transfer(st->spi, &xfer, 1);
> + if (ret)
> + return ret;
> +
> + /* Extract value from response (skip 2-byte command echo) */
> + if (num_bytes == AD5706R_SINGLE_BYTE_LEN)
> + val = st->rx_buf[2];
> + else if (num_bytes == AD5706R_DOUBLE_BYTE_LEN)
> + val = get_unaligned_be16(&st->rx_buf[2]);
> + else
> + return -EINVAL;
> +
> + put_unaligned_be16(val, val_buf);
> +
> + return 0;
> +}
...
> +#define AD5706R_CHAN(_channel) { \
> + .type = IIO_CURRENT, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_SCALE), \
Missing indentation at the end with tabs.
> + .output = 1, \
> + .indexed = 1, \
> + .channel = _channel, \
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* [PATCH v8 4/4] arm64: dts: freescale: moduline-display-av123z7m-n17: add backlight
From: Maud Spierings via B4 Relay @ 2026-04-07 14:41 UTC (permalink / raw)
To: Lee Jones, Daniel Thompson, Jingoo Han, Pavel Machek, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Helge Deller, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Liam Girdwood, Mark Brown, Frank Li
Cc: dri-devel, linux-leds, devicetree, linux-kernel, linux-fbdev, imx,
linux-arm-kernel, Maud Spierings
In-Reply-To: <20260407-max25014-v8-0-14eac7ed673a@gocontroll.com>
From: Maud Spierings <maudspierings@gocontroll.com>
Add the missing backlight.
Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
---
...p-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso
index 3eb665ce9d5d2..0b969c8c04db1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso
@@ -16,6 +16,7 @@
panel {
compatible = "boe,av123z7m-n17";
+ backlight = <&backlight>;
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinctrl_panel>;
pinctrl-names = "default";
@@ -91,10 +92,26 @@ lvds1_out: endpoint {
};
};
- /* max25014 @ 0x6f */
+ backlight: backlight@6f {
+ compatible = "maxim,max25014";
+ reg = <0x6f>;
+ default-brightness = <50>;
+ enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ maxim,iset = <7>;
+ maxim,strings = <1 1 1 1>;
+ };
};
&iomuxc {
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04
+ (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
+ >;
+ };
+
pinctrl_lvds_bridge: lvdsbridgegrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14
--
2.53.0
^ permalink raw reply related
* [PATCH v8 2/4] backlight: add max25014atg backlight
From: Maud Spierings via B4 Relay @ 2026-04-07 14:41 UTC (permalink / raw)
To: Lee Jones, Daniel Thompson, Jingoo Han, Pavel Machek, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Helge Deller, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Liam Girdwood, Mark Brown, Frank Li
Cc: dri-devel, linux-leds, devicetree, linux-kernel, linux-fbdev, imx,
linux-arm-kernel, Maud Spierings
In-Reply-To: <20260407-max25014-v8-0-14eac7ed673a@gocontroll.com>
From: Maud Spierings <maudspierings@gocontroll.com>
The Maxim MAX25014 is a 4-channel automotive grade backlight driver IC
with integrated boost controller.
Reviewed-by: Daniel Thompson (RISCstar) <danielt@kernel.org>
Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
---
MAINTAINERS | 1 +
drivers/video/backlight/Kconfig | 7 +
drivers/video/backlight/Makefile | 1 +
drivers/video/backlight/max25014.c | 377 +++++++++++++++++++++++++++++++++++++
4 files changed, 386 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7e3ad236537fe..1f1a5326a6aab 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15692,6 +15692,7 @@ MAX25014 BACKLIGHT DRIVER
M: Maud Spierings <maudspierings@gocontroll.com>
S: Maintained
F: Documentation/devicetree/bindings/leds/backlight/maxim,max25014.yaml
+F: drivers/video/backlight/max25014.c
MAX31335 RTC DRIVER
M: Antoniu Miclaus <antoniu.miclaus@analog.com>
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index a7a3fbaf7c29e..f4e99542ffe8f 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -282,6 +282,13 @@ config BACKLIGHT_DA9052
help
Enable the Backlight Driver for DA9052-BC and DA9053-AA/Bx PMICs.
+config BACKLIGHT_MAX25014
+ tristate "Backlight driver for Maxim MAX25014"
+ depends on I2C
+ select REGMAP_I2C
+ help
+ If you are using a MAX25014 chip as a backlight driver say Y to enable it.
+
config BACKLIGHT_MAX8925
tristate "Backlight driver for MAX8925"
depends on MFD_MAX8925
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index 794820a98ed49..21c8313cfb121 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
obj-$(CONFIG_BACKLIGHT_LP855X) += lp855x_bl.o
obj-$(CONFIG_BACKLIGHT_LP8788) += lp8788_bl.o
obj-$(CONFIG_BACKLIGHT_LV5207LP) += lv5207lp.o
+obj-$(CONFIG_BACKLIGHT_MAX25014) += max25014.o
obj-$(CONFIG_BACKLIGHT_MAX8925) += max8925_bl.o
obj-$(CONFIG_BACKLIGHT_MP3309C) += mp3309c.o
obj-$(CONFIG_BACKLIGHT_MT6370) += mt6370-backlight.o
diff --git a/drivers/video/backlight/max25014.c b/drivers/video/backlight/max25014.c
new file mode 100644
index 0000000000000..3ee45617261f3
--- /dev/null
+++ b/drivers/video/backlight/max25014.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Backlight driver for Maxim MAX25014
+ *
+ * Copyright (C) 2025 GOcontroll B.V.
+ * Author: Maud Spierings <maudspierings@gocontroll.com>
+ */
+
+#include <linux/backlight.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#define MAX25014_ISET_DEFAULT_100 11
+#define MAX_BRIGHTNESS 100
+#define MIN_BRIGHTNESS 0
+#define TON_MAX 130720 /* @153Hz */
+#define TON_STEP 1307 /* @153Hz */
+#define TON_MIN 0
+
+#define MAX25014_DEV_ID 0x00
+#define MAX25014_REV_ID 0x01
+#define MAX25014_ISET 0x02
+#define MAX25014_IMODE 0x03
+#define MAX25014_TON1H 0x04
+#define MAX25014_TON1L 0x05
+#define MAX25014_TON2H 0x06
+#define MAX25014_TON2L 0x07
+#define MAX25014_TON3H 0x08
+#define MAX25014_TON3L 0x09
+#define MAX25014_TON4H 0x0A
+#define MAX25014_TON4L 0x0B
+#define MAX25014_TON_1_4_LSB 0x0C
+#define MAX25014_SETTING 0x12
+#define MAX25014_DISABLE 0x13
+#define MAX25014_BSTMON 0x14
+#define MAX25014_IOUT1 0x15
+#define MAX25014_IOUT2 0x16
+#define MAX25014_IOUT3 0x17
+#define MAX25014_IOUT4 0x18
+#define MAX25014_OPEN 0x1B
+#define MAX25014_SHORTGND 0x1C
+#define MAX25014_SHORTED_LED 0x1D
+#define MAX25014_MASK 0x1E
+#define MAX25014_DIAG 0x1F
+
+#define MAX25014_ISET_ENA BIT(5)
+#define MAX25014_ISET_PSEN BIT(4)
+#define MAX25014_IMODE_HDIM BIT(2)
+#define MAX25014_SETTING_FPWM GENMASK(6, 4)
+#define MAX25014_DISABLE_DIS_MASK GENMASK(3, 0)
+#define MAX25014_DIAG_OT BIT(0)
+#define MAX25014_DIAG_OTW BIT(1)
+#define MAX25014_DIAG_HW_RST BIT(2)
+#define MAX25014_DIAG_BSTOV BIT(3)
+#define MAX25014_DIAG_BSTUV BIT(4)
+#define MAX25014_DIAG_IREFOOR BIT(5)
+
+struct max25014 {
+ struct i2c_client *client;
+ struct backlight_device *bl;
+ struct regmap *regmap;
+ struct gpio_desc *enable;
+ uint32_t iset;
+ uint8_t strings_mask;
+};
+
+static const struct regmap_config max25014_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = MAX25014_DIAG,
+};
+
+static int max25014_initial_power_state(struct max25014 *maxim)
+{
+ uint32_t val;
+ int ret;
+
+ ret = regmap_read(maxim->regmap, MAX25014_ISET, &val);
+ if (ret)
+ return ret;
+
+ return val & MAX25014_ISET_ENA ? BACKLIGHT_POWER_ON : BACKLIGHT_POWER_OFF;
+}
+
+static int max25014_check_errors(struct max25014 *maxim)
+{
+ uint32_t val;
+ uint8_t i;
+ int ret;
+
+ ret = regmap_read(maxim->regmap, MAX25014_OPEN, &val);
+ if (ret)
+ return ret;
+ if (val) {
+ dev_err(&maxim->client->dev, "Open led strings detected on:\n");
+ for (i = 0; i < 4; i++) {
+ if (val & 1 << i)
+ dev_err(&maxim->client->dev, "string %d\n", i + 1);
+ }
+ return -EIO;
+ }
+
+ ret = regmap_read(maxim->regmap, MAX25014_SHORTGND, &val);
+ if (ret)
+ return ret;
+ if (val) {
+ dev_err(&maxim->client->dev, "Short to ground detected on:\n");
+ for (i = 0; i < 4; i++) {
+ if (val & 1 << i)
+ dev_err(&maxim->client->dev, "string %d\n", i + 1);
+ }
+ return -EIO;
+ }
+
+ ret = regmap_read(maxim->regmap, MAX25014_SHORTED_LED, &val);
+ if (ret)
+ return ret;
+ if (val) {
+ dev_err(&maxim->client->dev, "Shorted led detected on:\n");
+ for (i = 0; i < 4; i++) {
+ if (val & 1 << i)
+ dev_err(&maxim->client->dev, "string %d\n", i + 1);
+ }
+ return -EIO;
+ }
+
+ ret = regmap_read(maxim->regmap, MAX25014_DIAG, &val);
+ if (ret)
+ return ret;
+ /*
+ * The HW_RST bit always starts at 1 after power up.
+ * It is reset on first read, does not indicate an error.
+ */
+ if (val && val != MAX25014_DIAG_HW_RST) {
+ if (val & MAX25014_DIAG_OT)
+ dev_err(&maxim->client->dev,
+ "Overtemperature shutdown\n");
+ if (val & MAX25014_DIAG_OTW)
+ dev_err(&maxim->client->dev,
+ "Chip is getting too hot (>125C)\n");
+ if (val & MAX25014_DIAG_BSTOV)
+ dev_err(&maxim->client->dev,
+ "Boost converter overvoltage\n");
+ if (val & MAX25014_DIAG_BSTUV)
+ dev_err(&maxim->client->dev,
+ "Boost converter undervoltage\n");
+ if (val & MAX25014_DIAG_IREFOOR)
+ dev_err(&maxim->client->dev, "IREF out of range\n");
+ return -EIO;
+ }
+ return 0;
+}
+
+/*
+ * 1. disable unused strings
+ * 2. set dim mode
+ * 3. set setting register
+ * 4. enable the backlight
+ */
+static int max25014_configure(struct max25014 *maxim, int initial_state)
+{
+ uint32_t val;
+ int ret;
+
+ ret = regmap_read(maxim->regmap, MAX25014_DISABLE, &val);
+ if (ret)
+ return ret;
+
+ /*
+ * Strings can only be disabled when MAX25014_ISET_ENA == 0, check if
+ * it needs to be changed at all to prevent the backlight flashing when
+ * it is configured correctly by the bootloader
+ */
+ if (!((val & MAX25014_DISABLE_DIS_MASK) == maxim->strings_mask)) {
+ if (initial_state == BACKLIGHT_POWER_ON) {
+ ret = regmap_write(maxim->regmap, MAX25014_ISET, 0);
+ if (ret)
+ return ret;
+ }
+ ret = regmap_write(maxim->regmap, MAX25014_DISABLE, maxim->strings_mask);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_write(maxim->regmap, MAX25014_IMODE, MAX25014_IMODE_HDIM);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(maxim->regmap, MAX25014_SETTING, &val);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(maxim->regmap, MAX25014_SETTING,
+ val & ~MAX25014_SETTING_FPWM);
+ if (ret)
+ return ret;
+
+ return regmap_write(maxim->regmap, MAX25014_ISET,
+ maxim->iset | MAX25014_ISET_ENA |
+ MAX25014_ISET_PSEN);
+}
+
+static int max25014_update_status(struct backlight_device *bl_dev)
+{
+ struct max25014 *maxim = bl_get_data(bl_dev);
+ uint32_t reg;
+ int ret;
+
+ reg = TON_STEP * backlight_get_brightness(bl_dev);
+
+ /*
+ * 18 bit number lowest, 2 bits in first register,
+ * next lowest 8 in the L register, next 8 in the H register
+ * Seemingly setting the strength of only one string controls all of
+ * them, individual settings don't affect the outcome.
+ */
+ ret = regmap_write(maxim->regmap, MAX25014_TON_1_4_LSB, reg & 0b00000011);
+ if (ret != 0)
+ return ret;
+ ret = regmap_write(maxim->regmap, MAX25014_TON1L, (reg >> 2) & 0b11111111);
+ if (ret != 0)
+ return ret;
+ return regmap_write(maxim->regmap, MAX25014_TON1H, (reg >> 10) & 0b11111111);
+}
+
+static const struct backlight_ops max25014_bl_ops = {
+ .options = BL_CORE_SUSPENDRESUME,
+ .update_status = max25014_update_status,
+};
+
+static int max25014_parse_dt(struct max25014 *maxim,
+ uint32_t *initial_brightness)
+{
+ struct device *dev = &maxim->client->dev;
+ struct device_node *node = dev->of_node;
+ uint32_t strings[4];
+ int res, i;
+
+ res = of_property_count_u32_elems(node, "maxim,strings");
+ if (res == 4) {
+ of_property_read_u32_array(node, "maxim,strings", strings, 4);
+ for (i = 0; i < 4; i++) {
+ if (strings[i] == 0)
+ maxim->strings_mask |= 1 << i;
+ }
+ } else {
+ maxim->strings_mask = 0;
+ }
+
+ *initial_brightness = 50U;
+ of_property_read_u32(node, "default-brightness", initial_brightness);
+
+ maxim->iset = MAX25014_ISET_DEFAULT_100;
+ of_property_read_u32(node, "maxim,iset", &maxim->iset);
+
+ if (maxim->iset > 15)
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid iset, should be a value from 0-15, entered was %d\n",
+ maxim->iset);
+
+ if (*initial_brightness > 100)
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid initial brightness, should be a value from 0-100, entered was %d\n",
+ *initial_brightness);
+
+ return 0;
+}
+
+static int max25014_probe(struct i2c_client *cl)
+{
+ const struct i2c_device_id *id = i2c_client_get_device_id(cl);
+ struct backlight_properties props;
+ uint32_t initial_brightness = 50;
+ struct backlight_device *bl;
+ struct max25014 *maxim;
+ int ret;
+
+ maxim = devm_kzalloc(&cl->dev, sizeof(struct max25014), GFP_KERNEL);
+ if (!maxim)
+ return -ENOMEM;
+
+ maxim->client = cl;
+
+ ret = max25014_parse_dt(maxim, &initial_brightness);
+ if (ret)
+ return ret;
+
+ ret = devm_regulator_get_enable(&maxim->client->dev, "power");
+ if (ret)
+ return dev_err_probe(&maxim->client->dev, ret,
+ "failed to get power-supply");
+
+ maxim->enable = devm_gpiod_get_optional(&maxim->client->dev, "enable",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(maxim->enable))
+ return dev_err_probe(&maxim->client->dev, PTR_ERR(maxim->enable),
+ "failed to get enable gpio\n");
+
+ /* Datasheet Electrical Characteristics tSTARTUP 2ms */
+ fsleep(2000);
+
+ maxim->regmap = devm_regmap_init_i2c(cl, &max25014_regmap_config);
+ if (IS_ERR(maxim->regmap))
+ return dev_err_probe(&maxim->client->dev, PTR_ERR(maxim->regmap),
+ "failed to initialize the i2c regmap\n");
+
+ i2c_set_clientdata(cl, maxim);
+
+ ret = max25014_check_errors(maxim);
+ if (ret) /* error is already reported in the above function */
+ return ret;
+
+ ret = max25014_initial_power_state(maxim);
+ if (ret < 0)
+ return dev_err_probe(&maxim->client->dev, ret, "Could not get enabled state\n");
+
+ memset(&props, 0, sizeof(struct backlight_properties));
+ props.type = BACKLIGHT_PLATFORM;
+ props.max_brightness = MAX_BRIGHTNESS;
+ props.brightness = initial_brightness;
+ props.scale = BACKLIGHT_SCALE_LINEAR;
+ props.power = ret;
+
+ ret = max25014_configure(maxim, ret);
+ if (ret)
+ return dev_err_probe(&maxim->client->dev, ret, "device config error");
+
+ bl = devm_backlight_device_register(&maxim->client->dev, id->name,
+ &maxim->client->dev, maxim,
+ &max25014_bl_ops, &props);
+ if (IS_ERR(bl))
+ return dev_err_probe(&maxim->client->dev, PTR_ERR(bl),
+ "failed to register backlight\n");
+
+ maxim->bl = bl;
+
+ backlight_update_status(maxim->bl);
+
+ return 0;
+}
+
+static void max25014_remove(struct i2c_client *cl)
+{
+ struct max25014 *maxim = i2c_get_clientdata(cl);
+
+ backlight_device_set_brightness(maxim->bl, 0);
+ gpiod_set_value_cansleep(maxim->enable, 0);
+}
+
+static const struct of_device_id max25014_dt_ids[] = {
+ { .compatible = "maxim,max25014", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, max25014_dt_ids);
+
+static const struct i2c_device_id max25014_ids[] = {
+ { "max25014" },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, max25014_ids);
+
+static struct i2c_driver max25014_driver = {
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = of_match_ptr(max25014_dt_ids),
+ },
+ .probe = max25014_probe,
+ .remove = max25014_remove,
+ .id_table = max25014_ids,
+};
+module_i2c_driver(max25014_driver);
+
+MODULE_DESCRIPTION("Maxim MAX25014 backlight driver");
+MODULE_AUTHOR("Maud Spierings <maudspierings@gocontroll.com>");
+MODULE_LICENSE("GPL");
--
2.53.0
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