* [PATCH 3/3] riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically
From: Conor Dooley @ 2026-04-07 15:36 UTC (permalink / raw)
To: linux-riscv
Cc: conor, Conor Dooley, Daire McNamara, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, devicetree, linux-kernel
In-Reply-To: <20260407-rely-speculate-dae3a81ea1fc@spud>
From: Conor Dooley <conor.dooley@microchip.com>
The i2c nodes are out of place, sort them where they should be.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../boot/dts/microchip/pic64gx-curiosity-kit.dts | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
index ed3ff03f3b11b..ef5bff3093fc3 100644
--- a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
+++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
@@ -89,6 +89,14 @@ &gpio2 {
"DIP4", "USR_IO11", "", "", "SWITCH1", "", "", "";
};
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
&irqmux {
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
@@ -134,14 +142,6 @@ &mbox {
status = "okay";
};
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-};
-
&mmc {
bus-width = <4>;
disable-wp;
--
2.53.0
^ permalink raw reply related
* [PATCH 2/3] riscv: dts: microchip: update pic64gx gpio interrupts to better match the SoC
From: Conor Dooley @ 2026-04-07 15:36 UTC (permalink / raw)
To: linux-riscv
Cc: conor, Conor Dooley, Daire McNamara, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, devicetree, linux-kernel
In-Reply-To: <20260407-rely-speculate-dae3a81ea1fc@spud>
From: Conor Dooley <conor.dooley@microchip.com>
Just like PolarFire SoC, the same issues with GPIO interrupts exist in
the pic64gx, due to their similarity. Yoinking from the commit message
for the same change for PolarFire SoC:
There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPIO controller 2 has 32 GPIOs
All GPIOs are capable of generating interrupts, for a total of 70.
There are only 41 IRQs available however, so a configurable mux is used
to ensure all GPIOs can be used for interrupt generation.
38 of the 41 interrupts are in what the documentation calls "direct
mode", as they provide an exclusive connection from a GPIO to the PLIC.
The 3 remaining interrupts are used to mux the interrupts which do not
have a exclusive connection, one for each GPIO controller.
The mux was overlooked when the bindings and driver were originally
written for the GPIO controllers on Polarfire SoC, and the interrupts
property in the GPIO nodes used to try and convey what the mapping was.
Instead, the mux should be a device in its own right, and the GPIO
controllers should be connected to it, rather than to the PLIC.
Now that a binding exists for that mux, fix the inaccurate description
of the interrupt controller hierarchy.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../dts/microchip/pic64gx-curiosity-kit.dts | 47 ++++++++++++-------
arch/riscv/boot/dts/microchip/pic64gx.dtsi | 32 +++++++++++--
2 files changed, 58 insertions(+), 21 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
index 2f2ccd77af30a..ed3ff03f3b11b 100644
--- a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
+++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
@@ -63,10 +63,6 @@ hss: hss-buffer@bfc00000 {
};
&gpio0 {
- interrupts = <13>, <14>, <15>, <16>,
- <17>, <18>, <19>, <20>,
- <21>, <22>, <23>, <24>,
- <25>, <26>;
status ="okay";
gpio-line-names =
"", "", "", "", "", "", "", "",
@@ -74,12 +70,6 @@ &gpio0 {
};
&gpio1 {
- interrupts = <27>, <28>, <29>, <30>,
- <31>, <32>, <33>, <34>,
- <35>, <36>, <37>, <38>,
- <39>, <40>, <41>, <42>,
- <43>, <44>, <45>, <46>,
- <47>, <48>, <49>, <50>;
status ="okay";
gpio-line-names =
"", "", "LED1", "LED2", "LED3", "LED4", "LED5", "LED6",
@@ -88,14 +78,6 @@ &gpio1 {
};
&gpio2 {
- interrupts = <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>;
pinctrl-names = "default";
pinctrl-0 = <&mdio1_gpio>, <&spi0_gpio>, <&can0_gpio>, <&pcie_gpio>,
<&qspi_gpio>, <&uart3_gpio>, <&uart4_gpio>, <&can1_gpio>;
@@ -107,6 +89,35 @@ &gpio2 {
"DIP4", "USR_IO11", "", "", "SWITCH1", "", "", "";
};
+&irqmux {
+ interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
+ <3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
+ <6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
+ <9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
+ <12 &plic 25>, <13 &plic 26>,
+
+ <32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
+ <35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
+ <38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
+ <41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
+ <44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
+ <47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
+ <50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
+ <53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
+
+ <64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
+ <67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
+ <70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
+ <73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
+ <76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
+ <79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
+ <82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
+ <85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
+ <88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
+ <91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
+ <94 &plic 53>, <95 &plic 53>;
+};
+
&mac0 {
status = "okay";
phy-mode = "sgmii";
diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi
index e9ec376b1776b..5cf3e3de0e067 100644
--- a/arch/riscv/boot/dts/microchip/pic64gx.dtsi
+++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi
@@ -295,6 +295,14 @@ mss_top_sysreg: syscon@20002000 {
#size-cells = <1>;
#reset-cells = <1>;
+ irqmux: interrupt-controller@54 {
+ compatible = "microchip,pic64gx-irqmux", "microchip,mpfs-irqmux";
+ reg = <0x54 0x4>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x7f>;
+ };
+
iomux0: pinctrl@200 {
compatible = "microchip,pic64gx-pinctrl-iomux0",
"microchip,mpfs-pinctrl-iomux0";
@@ -484,9 +492,13 @@ mac1: ethernet@20112000 {
gpio0: gpio@20120000 {
compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
reg = <0x0 0x20120000 0x0 0x1000>;
- interrupt-parent = <&plic>;
+ interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <1>;
+ interrupts = <0>, <1>, <2>, <3>,
+ <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>,
+ <12>, <13>;
clocks = <&clkcfg CLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
@@ -497,9 +509,15 @@ gpio0: gpio@20120000 {
gpio1: gpio@20121000 {
compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
reg = <0x0 0x20121000 0x0 0x1000>;
- interrupt-parent = <&plic>;
+ interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <1>;
+ interrupts = <32>, <33>, <34>, <35>,
+ <36>, <37>, <38>, <39>,
+ <40>, <41>, <42>, <43>,
+ <44>, <45>, <46>, <47>,
+ <48>, <49>, <50>, <51>,
+ <52>, <53>, <54>, <55>;
clocks = <&clkcfg CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
@@ -510,9 +528,17 @@ gpio1: gpio@20121000 {
gpio2: gpio@20122000 {
compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
reg = <0x0 0x20122000 0x0 0x1000>;
- interrupt-parent = <&plic>;
+ interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <1>;
+ interrupts = <64>, <65>, <66>, <67>,
+ <68>, <69>, <70>, <71>,
+ <72>, <73>, <74>, <75>,
+ <76>, <77>, <78>, <79>,
+ <80>, <81>, <82>, <83>,
+ <84>, <85>, <86>, <87>,
+ <88>, <89>, <90>, <91>,
+ <92>, <93>, <94>, <95>;
clocks = <&clkcfg CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
--
2.53.0
^ permalink raw reply related
* [PATCH 1/3] riscv: dts: microchip: add tsu clock to macb on pic64gx
From: Conor Dooley @ 2026-04-07 15:36 UTC (permalink / raw)
To: linux-riscv
Cc: conor, Conor Dooley, Daire McNamara, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, devicetree, linux-kernel
In-Reply-To: <20260407-rely-speculate-dae3a81ea1fc@spud>
From: Conor Dooley <conor.dooley@microchip.com>
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is required for
correct rate selection.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/pic64gx.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi
index c164d7bc270a2..e9ec376b1776b 100644
--- a/arch/riscv/boot/dts/microchip/pic64gx.dtsi
+++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi
@@ -459,8 +459,8 @@ mac0: ethernet@20110000 {
interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
/* Filled in by a bootloader */
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
- clock-names = "pclk", "hclk";
+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>;
+ clock-names = "pclk", "hclk", "tsu_clk";
resets = <&mss_top_sysreg CLK_MAC0>;
status = "disabled";
};
@@ -475,8 +475,8 @@ mac1: ethernet@20112000 {
interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
/* Filled in by a bootloader */
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
- clock-names = "pclk", "hclk";
+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>;
+ clock-names = "pclk", "hclk", "tsu_clk";
resets = <&mss_top_sysreg CLK_MAC1>;
status = "disabled";
};
--
2.53.0
^ permalink raw reply related
* [PATCH 0/3] pic64gx semantic conflict "fixes"
From: Conor Dooley @ 2026-04-07 15:36 UTC (permalink / raw)
To: linux-riscv
Cc: conor, Conor Dooley, Daire McNamara, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, devicetree, linux-kernel
From: Conor Dooley <conor.dooley@microchip.com>
CC: Conor Dooley <conor.dooley@microchip.com>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: Paul Walmsley <pjw@kernel.org>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Albert Ou <aou@eecs.berkeley.edu>
CC: Alexandre Ghiti <alex@ghiti.fr>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
Conor Dooley (3):
riscv: dts: microchip: add tsu clock to macb on pic64gx
riscv: dts: microchip: update pic64gx gpio interrupts to better match
the SoC
riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically
.../dts/microchip/pic64gx-curiosity-kit.dts | 63 +++++++++++--------
arch/riscv/boot/dts/microchip/pic64gx.dtsi | 40 +++++++++---
2 files changed, 70 insertions(+), 33 deletions(-)
--
2.53.0
^ permalink raw reply
* [PATCH 2/2] arm64: dts: renesas: r9a09g056: Add #mux-state-cells to usb20phyrst
From: Tommaso Merciai @ 2026-04-07 15:34 UTC (permalink / raw)
To: tomm.merciai, peda, p.zabel
Cc: linux-renesas-soc, biju.das.jz, Tommaso Merciai,
Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, linux-kernel
In-Reply-To: <cover.1775575276.git.tommaso.merciai.xr@bp.renesas.com>
The renesas,rzv2h-usb2phy-reset binding schema defines #mux-state-cells
as a required property. Add it to the usb20phyrst node to fix the
following warnings:
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-emmc.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-sd.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
Fixes: 6a1b6f7e56dc ("dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property")
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index 40525470194e..7ccddd6a4a9a 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -1327,6 +1327,7 @@ usb20phyrst: usb20phy-reset@15830000 {
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
+ #mux-state-cells = <1>;
status = "disabled";
};
--
2.43.0
^ permalink raw reply related
* [PATCH 1/2] arm64: dts: renesas: r9a09g057: Add #mux-state-cells to usb2{0,1}phyrst
From: Tommaso Merciai @ 2026-04-07 15:34 UTC (permalink / raw)
To: tomm.merciai, peda, p.zabel
Cc: linux-renesas-soc, biju.das.jz, Tommaso Merciai,
Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, linux-kernel
In-Reply-To: <cover.1775575276.git.tommaso.merciai.xr@bp.renesas.com>
The renesas,rzv2h-usb2phy-reset binding schema defines #mux-state-cells
as a required property. Add it to the usb20phyrst and usb21phyrst nodes
to fix the following warnings:
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-emmc.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-emmc.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-sd.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-sd.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
Fixes: 6a1b6f7e56dc ("dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property")
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 9581af58024e..6f6fe5f36bef 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -1345,6 +1345,7 @@ usb20phyrst: usb20phy-reset@15830000 {
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
+ #mux-state-cells = <1>;
status = "disabled";
};
@@ -1355,6 +1356,7 @@ usb21phyrst: usb21phy-reset@15840000 {
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
+ #mux-state-cells = <1>;
status = "disabled";
};
--
2.43.0
^ permalink raw reply related
* [PATCH 0/2] arm64: dts: renesas: Add missing #mux-state-cells to usb2phy-reset nodes
From: Tommaso Merciai @ 2026-04-07 15:34 UTC (permalink / raw)
To: tomm.merciai, peda, p.zabel
Cc: linux-renesas-soc, biju.das.jz, Tommaso Merciai,
Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, linux-kernel
Dear All,
The renesas,rzv2h-usb2phy-reset binding schema defines #mux-state-cells as a
required property. Add it to the USB2 PHY reset nodes in the RZ/V2H and RZ/V2N
device trees to fix dtbs_check warnings.
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-emmc.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-sd.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-emmc.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-emmc.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-sd.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-sd.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
Kind Regards,
Tommaso
Tommaso Merciai (2):
arm64: dts: renesas: r9a09g057: Add #mux-state-cells to
usb2{0,1}phyrst
arm64: dts: renesas: r9a09g056: Add #mux-state-cells to usb20phyrst
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 2 ++
2 files changed, 3 insertions(+)
--
2.43.0
^ permalink raw reply
* [PATCH v1] dt-bindings: soc: microchip: document irqmux on pic64gx
From: Conor Dooley @ 2026-04-07 15:29 UTC (permalink / raw)
To: linux-riscv
Cc: conor, Conor Dooley, Daire McNamara, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
From: Conor Dooley <conor.dooley@microchip.com>
Being practically identical to PolarFire SoC, pic64gx has a irqmux
that's entirely compatible with that on mpfs.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Conor Dooley <conor.dooley@microchip.com>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
---
.../bindings/soc/microchip/microchip,mpfs-irqmux.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml
index 51164772724f5..419b32e2df936 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml
@@ -26,7 +26,11 @@ description: |
properties:
compatible:
- const: microchip,mpfs-irqmux
+ oneOf:
+ - items:
+ - const: microchip,pic64gx-irqmux
+ - const: microchip,mpfs-irqmux
+ - const: microchip,mpfs-irqmux
reg:
maxItems: 1
--
2.53.0
^ permalink raw reply related
* [PATCH v10 2/3] riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2
From: Han Gao @ 2026-04-07 15:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao,
Vincent Legoll
In-Reply-To: <cover.1775575436.git.gaohan@iscas.ac.cn>
Define the DC power input and the 4v power as fixed regulator supplies.
Define the SpacemiT P1 PMIC voltage regulators and their constraints.
Co-developed-by: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Tested-by: Vincent Legoll <legoll@online.fr> # OrangePi-RV2
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 131 ++++++++++++++++++
1 file changed, 131 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index 57ec1cc32b03..f7a1dadaa95f 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -23,6 +23,25 @@ chosen {
stdout-path = "serial0";
};
+ vcc_5v0: regulator-vcc-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc4v0: regulator-vcc4v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc4v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ vin-supply = <&vcc_5v0>;
+ };
+
leds {
compatible = "gpio-leds";
@@ -91,6 +110,118 @@ &i2c8 {
pinctrl-names = "default";
pinctrl-0 = <&i2c8_cfg>;
status = "okay";
+
+ pmic@41 {
+ compatible = "spacemit,p1";
+ reg = <0x41>;
+ interrupts = <64>;
+ vin1-supply = <&vcc4v0>;
+ vin2-supply = <&vcc4v0>;
+ vin3-supply = <&vcc4v0>;
+ vin4-supply = <&vcc4v0>;
+ vin5-supply = <&vcc4v0>;
+ vin6-supply = <&vcc4v0>;
+ aldoin-supply = <&vcc4v0>;
+ dldoin1-supply = <&buck5>;
+ dldoin2-supply = <&buck5>;
+
+ regulators {
+ buck1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck3_1v8: buck3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck4_3v3: buck4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck5: buck5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ aldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ aldo2 {
+ /* not connected */
+ };
+
+ aldo3 {
+ /* not connected */
+ };
+
+ aldo4 {
+ /* not connected */
+ };
+
+ dldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ dldo2 {
+ /* not connected */
+ };
+
+ dldo3 {
+ /* not connected */
+ };
+
+ dldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo7 {
+ /* not connected */
+ };
+ };
+ };
};
&uart0 {
--
2.47.3
^ permalink raw reply related
* [PATCH v10 3/3] riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
From: Han Gao @ 2026-04-07 15:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao,
Vincent Legoll
In-Reply-To: <cover.1775575436.git.gaohan@iscas.ac.cn>
Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the
OrangePi RV2 board.
The board utilizes a Genesys Logic GL3523 USB3.0 hub.
Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and
PHY-related Device Tree nodes for the OrangePi RV2.
Co-developed-by: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Tested-by: Vincent Legoll <legoll@online.fr> # OrangePi-RV2
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index f7a1dadaa95f..3a829e3c9cbc 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -23,6 +23,16 @@ chosen {
stdout-path = "serial0";
};
+ pcie_vcc3v3: regulator-pcie-vcc3v3 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>;
+ regulator-name = "pcie_vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v0>;
+ };
+
vcc_5v0: regulator-vcc-5v0 {
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
@@ -42,6 +52,16 @@ vcc4v0: regulator-vcc4v0 {
vin-supply = <&vcc_5v0>;
};
+ vcc5v0_usb30: regulator-vcc5v0-usb30 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc5v0_usb30";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v0>;
+ };
+
leds {
compatible = "gpio-leds";
@@ -54,6 +74,10 @@ led1 {
};
};
+&combo_phy {
+ status = "okay";
+};
+
ð0 {
phy-handle = <&rgmii0>;
phy-mode = "rgmii-id";
@@ -224,8 +248,64 @@ dldo7 {
};
};
+&pcie1_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_3_cfg>;
+ status = "okay";
+};
+
+&pcie1_port {
+ phys = <&pcie1_phy>;
+ vpcie3v3-supply = <&pcie_vcc3v3>;
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_4_cfg>;
+ status = "okay";
+};
+
+&pcie2_port {
+ phys = <&pcie2_phy>;
+ vpcie3v3-supply = <&pcie_vcc3v3>;
+};
+
+&pcie2 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vbus-supply = <&vcc5v0_usb30>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb5e3,610";
+ reg = <0x1>;
+ peer-hub = <&hub_3_0>;
+ vdd-supply = <&vcc_5v0>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb5e3,620";
+ reg = <0x2>;
+ peer-hub = <&hub_2_0>;
+ vdd-supply = <&vcc_5v0>;
+ };
+};
--
2.47.3
^ permalink raw reply related
* [PATCH v10 1/3] riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2
From: Han Gao @ 2026-04-07 15:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao,
Vincent Legoll
In-Reply-To: <cover.1775575436.git.gaohan@iscas.ac.cn>
The adapter is used to access the SpacemiT P1 PMIC present in this board.
Tested-by: Vincent Legoll <legoll@online.fr> # OrangePi-RV2
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index 7b7331cb3c72..57ec1cc32b03 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -87,6 +87,12 @@ &pdma {
status = "okay";
};
+&i2c8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8_cfg>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
--
2.47.3
^ permalink raw reply related
* [PATCH v10 0/3] riscv: dts: spacemit: Add PMIC regulators usb pcie
From: Han Gao @ 2026-04-07 15:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao
Changes in v10:
- patch 3:
add vin-supply in pcie_vcc3v3
reorder vcc5v0_usb30
remove vpcie3v3-supply form pcie1
- Link to v9: https://lore.kernel.org/linux-riscv/cover.1775417019.git.gaohan@iscas.ac.cn
Han Gao (3):
riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2
riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2
riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 217 ++++++++++++++++++
1 file changed, 217 insertions(+)
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
prerequisite-patch-id: ef6e9c7b5854d0c08066b72f9a7868db8c2140eb
prerequisite-patch-id: cfe3800f8c791ec4c63e070af9628e88e0fc31b9
prerequisite-patch-id: b76493e625ae257c8adcd67874178458420e4d47
prerequisite-patch-id: 88e01dc92c83bd88ddeb78891d3088209fed8d6b
prerequisite-patch-id: 60336d10ab8322c70596d0f046b6b5c54bb24b54
prerequisite-patch-id: 68c4d869548687dc115dd91e2ffb8f4c11482d86
prerequisite-patch-id: fdadcf964c2cb3406160edb579d99a8d5695f8e6
prerequisite-patch-id: 73b9e745338b0499b849fa4f7f9508987ab39a59
prerequisite-patch-id: cd26770c2160c3c31a406bd8a6b01ab666180ae0
prerequisite-patch-id: e5dfddc32cefae195692da8b80e19adf086e4ad7
prerequisite-patch-id: 7fd53cbe4977598f26148a4bb1cf692bbdb79a09
prerequisite-patch-id: 96ebac57bb29619b97fe95422206a685825618e9
prerequisite-patch-id: 00fac16b52f60383db3140e2885f3f7f8d14dd1a
prerequisite-patch-id: 3b7a60047b922c48e93599f621cb738856f42354
prerequisite-patch-id: 275c030b963be05dd1041451f539a130ce614277
prerequisite-patch-id: 93963424b0871e64276af0e0b2199b52e29b4603
prerequisite-patch-id: 8383188b1c01ed6280629faaa29c37d699ade241
prerequisite-patch-id: 5f8126b912b924d63d4a1e0c5eb42d212eb0d369
prerequisite-patch-id: e80af628a2e0b5f2eeb3cb1b5e7133d08bdd2c4e
prerequisite-patch-id: 0234a6dca15eb91f98a45a46604ce5b4935048a5
--
2.47.3
^ permalink raw reply
* Re: [PATCH v3] arm64: dts: imx8mp: Add DT overlays for DH i.MX8M Plus DHCOM SoM and boards
From: Marek Vasut @ 2026-04-07 15:26 UTC (permalink / raw)
To: linux-arm-kernel, Frank Li
Cc: Christoph Niedermaier, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, devicetree, imx, kernel, linux-kernel
In-Reply-To: <20260326044411.222907-1-marex@nabladev.com>
On 3/26/26 5:43 AM, Marek Vasut wrote:
> Add DT overlays to support DH i.MX8M Plus DHCOM SoM variants and carrier
> board expansion modules. The following DT overlays are implemented:
> - SoM:
> - DH 660-x00 SoM with 1xRMII PHY
> - DH 660-x00 SoM with 2xRMII PHY
> - PDK2:
> - DH 505-200 Display board in edge connector X12 via direct LVDS
> - DH 531-100 SPI/I2C board in header X21
> - DH 531-200 SPI/I2C board in header X22
> - DH 560-200 Display board in edge connector X12
> - PDK3:
> - DH 505-200 Display board in edge connector X36 via direct LVDS
> - DH 531-100 SPI/I2C board in header X40
> - DH 531-200 SPI/I2C board in header X41
> - DH 560-300 Display board in edge connector X36
> - EA muRata 2AE M.2 A/E-Key card in connector X20
> - NXP SPF-29853-C1 MINISASTOCSI with OV5640 sensor in connector X31
> - NXP SPF-29853-C1 MINISASTOCSI with OV5640 sensor in connector X29
> - PicoITX:
> - DH 626-100 Display board in edge connector X2
Hello Frank,
I know I was sending quite a few DTOs recently. Is this set still on
your review list, or was this one missed ?
Thank you for reviewing the DTOs so actively, it really helps a lot !
^ permalink raw reply
* Re: [PATCH RFC 0/2] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A
From: Xilin Wu @ 2026-04-07 15:22 UTC (permalink / raw)
To: Andriy Sharandakov, Konrad Dybcio, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong,
Viken Dadhaniya, Ram Kumar Dwivedi
In-Reply-To: <9f04ae8e-e15a-414f-a436-987d02d31cdd@gmail.com>
On 4/7/2026 6:16 PM, Andriy Sharandakov wrote:
> On 12.09.2025 11:15, Konrad Dybcio wrote:
>> On 9/12/25 11:04 AM, Xilin Wu wrote:
>>> On 2025/9/12 16:56:04, Konrad Dybcio wrote:
>>>> On 9/12/25 10:03 AM, Xilin Wu wrote:
>>>>> Radxa Dragon Q6A (https://docs.radxa.com/en/dragon/q6a) is a single
>>>>> board
>>>>> computer, based on the Qualcomm QCS6490 platform.
>>>>>
>>>>> The board ships with a modified version of the Qualcomm Linux boot
>>>>> firmware, which is stored on the onboard SPI NOR flash. This allows
>>>>> booting standard EFI-based bootloaders from SD/eMMC/USB/UFS/NVMe. It
>>>>> supports replaceable UFS 3.1/eMMC modules for easy user upgrades.
>>>>>
>>>>> The board schematic is available at [1].
>>>>>
>>>>> Features enabled and working:
>>>>>
>>>>> - USB-A 3.0 port (depends on [2])
>>>>> - Three USB-A 2.0 ports
>>>>> - RTL8111K Ethernet connected to PCIe0
>>>>> - UFS 3.1 module (depends on [3])
>>>>> - eMMC module
>>>>> - SD card
>>>>> - M.2 M-Key 2230 PCIe 3.0 x2
>>>>> - HDMI 2.0 port including audio (depends on [2])
>>>>> - Configurable I2C/SPI/UART from 40-Pin GPIO (depends on [4])
>>>>> - Headphone jack
>>>>> - Onboard thermal sensors
>>>>> - QSPI controller for updating boot firmware
>>>>> - ADSP remoteproc (Type-C and charging features disabled in firmware)
>>>>> - CDSP remoteproc (for AI applications using QNN)
>>>>> - Venus video encode and decode accelerator
>>>>
>>>> You have a number of features that depend on several other series, and
>>>> as Krzysztof pointed out this is difficult to merge/review.. Could you
>>>> please create a "linux-next/master-ready" version of this series and
>>>> separate the changes for which the dependencies are unmet, putting them
>>>> at the end? This way we can take at least some of your diff.
>>>>
>>>> If you still want review on them, you can also send them as [PATCH DNM]
>>>> or so
>>>>
>>>> Konrad
>>>>
>>>
>>> Thanks for the suggestion. I think I can separate the changes that
>>> have unmet dependencies, and mark them as DNM. Can I send the new
>>> series now, or am I supposed to wait for a few days?
>>
>> Since we can't do much with this one, please apply Krzysztof's review
>> comments and tags and feel free to resend
>>
>> Konrad
>
> Xilin,
>
> The prerequisite for the "USB-A 3.0 port (depends on [2])" feature has
> been added - https://github.com/torvalds/linux/commit/
> f842daf740114a8783be566219db34c6a0f1d02c
>
> Could you please check and resend the USB 3.0 port feature?
>
> Thanks.
>
> Best regards,
> Andriy
>
>
Hi Andriy,
Thanks for reminding me. A new series has been sent just now.
--
Best regards,
Xilin Wu <sophon@radxa.com>
^ permalink raw reply
* [PATCH 11/12] ASoC: dt-bindings: google,sc7280-herobrine: Add Radxa Dragon Q6A sound card
From: Xilin Wu @ 2026-04-07 15:20 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
The Radxa Dragon Q6A can boot in EL2, allowing the kernel to access the
LPASS hardware directly. Add the compatible for it to the bindings.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../devicetree/bindings/sound/google,sc7280-herobrine.yaml | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml b/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
index cdcd7c6f21eb..cd87dfe20618 100644
--- a/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
+++ b/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
@@ -17,8 +17,13 @@ allOf:
properties:
compatible:
- enum:
- - google,sc7280-herobrine
+ oneOf:
+ - enum:
+ - google,sc7280-herobrine
+ - items:
+ - enum:
+ - radxa,dragon-q6a-sndcard
+ - const: google,sc7280-herobrine
"#address-cells":
const: 1
--
2.53.0
^ permalink raw reply related
* [PATCH 12/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: add LPASS CPU audio variant
From: Xilin Wu @ 2026-04-07 15:20 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
Add a qcs6490-radxa-dragon-q6a-lpass-cpu.dts variant for debugging and
bring-up of the host-controlled LPASS audio path on the Radxa Dragon
Q6A.
This variant enables the LPASS blocks and codec macros needed by the
lpass-cpu driver, wires WCD9380 playback/capture and DisplayPort audio
to the LPASS CDC DMA and DP interfaces, and disables remoteproc_adsp so
that the audio hardware is owned directly by Linux.
This DTB is an optional configuration for systems booted with the kernel
running at EL2, where direct CPU access to the LPASS hardware is
available. It is useful for users who need low-latency and fully
controllable audio.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts | 131 +++++++++++++++++++++
2 files changed, 132 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4ba8e7306419..2f84ef7109b5 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -169,6 +169,7 @@ qcs615-ride-el2-dtbs := qcs615-ride.dtb talos-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a-lpass-cpu.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts
new file mode 100644
index 000000000000..e7ee57372d7e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025-2026 Radxa Computer (Shenzhen) Co., Ltd.
+ *
+ * Direct CPU access to the LPASS hardware block on this platform is
+ * restricted by default. Booting the Linux kernel in EL2 will allow the
+ * kernel to access the LPASS hardware directly.
+ *
+ * You can achieve this by setting the Hypervisor Override BIOS setting to
+ * "Enabled" if you are using the official UEFI firmware.
+ */
+
+/dts-v1/;
+
+#include "qcs6490-radxa-dragon-q6a.dtsi"
+
+&gcc {
+ protected-clocks = <GCC_MSS_CFG_AHB_CLK>,
+ <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
+ <GCC_MSS_OFFLINE_AXI_CLK>,
+ <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+ <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+ <GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_SEC_CTRL_CLK_SRC>,
+ <GCC_WPSS_AHB_BDG_MST_CLK>,
+ <GCC_WPSS_AHB_CLK>,
+ <GCC_WPSS_RSCP_CLK>;
+};
+
+&lpass_aon {
+ status = "okay";
+};
+
+&lpass_core {
+ status = "okay";
+};
+
+&lpass_cpu {
+ status = "okay";
+
+ dai-link@5 {
+ reg = <LPASS_DP_RX>;
+ };
+
+ dai-link@6 {
+ reg = <LPASS_CDC_DMA_RX0>;
+ };
+
+ dai-link@19 {
+ reg = <LPASS_CDC_DMA_TX3>;
+ };
+};
+
+&lpass_hm {
+ status = "okay";
+};
+
+&lpass_rx_macro {
+ status = "okay";
+};
+
+&lpass_tx_macro {
+ status = "okay";
+};
+
+&lpass_va_macro {
+ status = "okay";
+};
+
+&lpasscc {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ status = "disabled";
+};
+
+&sound {
+ compatible = "radxa,dragon-q6a-sndcard", "google,sc7280-herobrine";
+ model = "qcs6490-wcd938x-dp";
+
+ audio-routing = "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "TX SWR_ADC1", "ADC2_OUTPUT";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dai-link@0 {
+ link-name = "WCD9380 Playback";
+ reg = <0>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr0 0>, <&lpass_rx_macro 0>;
+ };
+ };
+
+ dai-link@1 {
+ link-name = "DisplayPort";
+ reg = <1>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_DP_RX>;
+ };
+
+ codec {
+ sound-dai = <&mdss_dp>;
+ };
+ };
+
+ dai-link@2 {
+ link-name = "WCD9380 Capture";
+ reg = <2>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr1 0>, <&lpass_tx_macro 0>;
+ };
+ };
+};
--
2.53.0
^ permalink raw reply related
* [PATCH 10/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: factor out common board dtsi
From: Xilin Wu @ 2026-04-07 15:20 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
Move the common Radxa Dragon Q6A board description from
qcs6490-radxa-dragon-q6a.dts to a new qcs6490-radxa-dragon-q6a.dtsi so
it can be shared by multiple board variants.
Keep the existing Audioreach-based qcs6490-radxa-dragon-q6a.dts as the
default configuration by including the new common .dtsi and
qcs6490-audioreach.dtsi.
No functional change intended.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 1135 +------------------
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi | 1137 ++++++++++++++++++++
2 files changed, 1139 insertions(+), 1133 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 5679f38de5b3..f52328fbaef9 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -1,568 +1,13 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
- * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd.
+ * Copyright (c) 2025-2026 Radxa Computer (Shenzhen) Co., Ltd.
*/
/dts-v1/;
-/* PM7250B is configured to use SID8/9 */
-#define PM7250B_SID 8
-#define PM7250B_SID1 9
-
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
-#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include "kodiak.dtsi"
-#include "pm7250b.dtsi"
-#include "pm7325.dtsi"
-#include "pm8350c.dtsi" /* PM7350C */
-#include "pmk8350.dtsi" /* PMK7325 */
+#include "qcs6490-radxa-dragon-q6a.dtsi"
#include "qcs6490-audioreach.dtsi"
-/delete-node/ &adsp_mem;
-/delete-node/ &adsp_rpc_remote_heap_mem;
-/delete-node/ &cdsp_mem;
-/delete-node/ &gpu_zap_mem;
-/delete-node/ &ipa_fw_mem;
-/delete-node/ &mpss_mem;
-/delete-node/ &remoteproc_mpss;
-/delete-node/ &remoteproc_wpss;
-/delete-node/ &rmtfs_mem;
-/delete-node/ &video_mem;
-/delete-node/ &wifi;
-/delete-node/ &wlan_ce_mem;
-/delete-node/ &wlan_fw_mem;
-/delete-node/ &wpss_mem;
-
-/ {
- model = "Radxa Dragon Q6A";
- compatible = "radxa,dragon-q6a", "qcom,qcm6490";
- chassis-type = "embedded";
-
- aliases {
- mmc0 = &sdhc_1;
- mmc1 = &sdhc_2;
- serial0 = &uart5;
- };
-
- wcd938x: audio-codec {
- compatible = "qcom,wcd9380-codec";
-
- pinctrl-0 = <&wcd_default>;
- pinctrl-names = "default";
-
- reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
-
- vdd-rxtx-supply = <&vreg_l18b_1p8>;
- vdd-io-supply = <&vreg_l18b_1p8>;
- vdd-buck-supply = <&vreg_l17b_1p8>;
- vdd-mic-bias-supply = <&vreg_bob_3p296>;
-
- qcom,micbias1-microvolt = <1800000>;
- qcom,micbias2-microvolt = <1800000>;
- qcom,micbias3-microvolt = <1800000>;
- qcom,micbias4-microvolt = <1800000>;
- qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
- qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
- qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
- qcom,rx-device = <&wcd_rx>;
- qcom,tx-device = <&wcd_tx>;
-
- qcom,hphl-jack-type-normally-closed;
-
- #sound-dai-cells = <1>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- usb2_1_con: connector-0 {
- compatible = "usb-a-connector";
- vbus-supply = <&vcc_5v_peri>;
-
- port {
- usb2_1_connector: endpoint {
- remote-endpoint = <&usb_hub_2_1>;
- };
- };
- };
-
- usb2_2_con: connector-1 {
- compatible = "usb-a-connector";
- vbus-supply = <&vcc_5v_peri>;
-
- port {
- usb2_2_connector: endpoint {
- remote-endpoint = <&usb_hub_2_2>;
- };
- };
- };
-
- usb2_3_con: connector-2 {
- compatible = "usb-a-connector";
- vbus-supply = <&vcc_5v_peri>;
-
- port {
- usb2_3_connector: endpoint {
- remote-endpoint = <&usb_hub_2_3>;
- };
- };
- };
-
- usb3_con: connector {
- compatible = "usb-a-connector";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- usb3_con_hs_in: endpoint {
- remote-endpoint = <&usb_1_dwc3_hs>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- usb3_con_ss_in: endpoint {
- remote-endpoint = <&usb_1_qmpphy_out_usb>;
- };
- };
- };
- };
-
- hdmi-bridge {
- compatible = "radxa,ra620";
-
- pinctrl-0 = <&dp_hot_plug_det>;
- pinctrl-names = "default";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- hdmi_bridge_in: endpoint {
- remote-endpoint = <&usb_1_qmpphy_out_dp>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- hdmi_bridge_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- label = "hdmi";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_bridge_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-0 = <&user_led>;
- pinctrl-names = "default";
-
- user-led {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_INDICATOR;
- gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
- default-state = "off";
- panic-indicator;
- };
- };
-
- reserved-memory {
- lpass_ml_mem: lpass-ml@81800000 {
- reg = <0x0 0x81800000 0x0 0xf00000>;
- no-map;
- };
-
- cdsp_secure_heap_mem: cdsp-secure-heap@82700000 {
- reg = <0x0 0x82700000 0x0 0x10000>;
- no-map;
- };
-
- adsp_mem: adsp@8b800000 {
- reg = <0x0 0x8b800000 0x0 0x2800000>;
- no-map;
- };
-
- cdsp_mem: cdsp@8e000000 {
- reg = <0x0 0x8e000000 0x0 0x1e00000>;
- no-map;
- };
-
- video_mem: video@8fe00000 {
- reg = <0x0 0x8fe00000 0x0 0x500000>;
- no-map;
- };
-
- gpu_zap_mem: zap@90300000 {
- reg = <0x0 0x90300000 0x0 0x5000>;
- no-map;
- };
-
- tz_stat_mem: tz-stat@c0000000 {
- reg = <0x0 0xc0000000 0x0 0x100000>;
- no-map;
- };
-
- tags_mem: tags@c0100000 {
- reg = <0x0 0xc0100000 0x0 0x1200000>;
- no-map;
- };
-
- qtee_mem: qtee@c1300000 {
- reg = <0x0 0xc1300000 0x0 0x500000>;
- no-map;
- };
-
- trusted_apps_mem: trusted-apps@c1800000 {
- reg = <0x0 0xc1800000 0x0 0x2200000>;
- no-map;
- };
-
- adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@c6500000 {
- reg = <0x0 0xc6500000 0x0 0x800000>;
- no-map;
- };
- };
-
- thermal-zones {
- msm-skin-thermal {
- polling-delay-passive = <0>;
- thermal-sensors = <&pmk8350_adc_tm 2>;
- };
-
- quiet-thermal {
- polling-delay-passive = <0>;
- thermal-sensors = <&pmk8350_adc_tm 1>;
- };
-
- ufs-thermal {
- polling-delay-passive = <0>;
- thermal-sensors = <&pmk8350_adc_tm 3>;
- };
-
- xo-thermal {
- polling-delay-passive = <0>;
- thermal-sensors = <&pmk8350_adc_tm 0>;
- };
- };
-
- vcc_1v8: regulator-vcc-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_5v_peri>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_5v_peri>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_5v_peri: regulator-vcc-5v-peri {
- compatible = "regulator-fixed";
- regulator-name = "vcc_5v_peri";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vph_pwr>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vph_pwr: regulator-vph-pwr {
- compatible = "regulator-fixed";
- regulator-name = "vph_pwr";
- regulator-min-microvolt = <3700000>;
- regulator-max-microvolt = <3700000>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&apps_rsc {
- regulators-0 {
- compatible = "qcom,pm7325-rpmh-regulators";
- qcom,pmic-id = "b";
-
- vdd-s1-supply = <&vph_pwr>;
- vdd-s2-supply = <&vph_pwr>;
- vdd-s3-supply = <&vph_pwr>;
- vdd-s4-supply = <&vph_pwr>;
- vdd-s5-supply = <&vph_pwr>;
- vdd-s6-supply = <&vph_pwr>;
- vdd-s7-supply = <&vph_pwr>;
- vdd-s8-supply = <&vph_pwr>;
- vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p536>;
- vdd-l2-l7-supply = <&vreg_bob_3p296>;
- vdd-l6-l9-l10-supply = <&vreg_s8b_1p2>;
- vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p84>;
-
- vreg_s1b_1p84: smps1 {
- regulator-name = "vreg_s1b_1p84";
- regulator-min-microvolt = <1840000>;
- regulator-max-microvolt = <2040000>;
- };
-
- vreg_s7b_0p536: smps7 {
- regulator-name = "vreg_s7b_0p536";
- regulator-min-microvolt = <536000>;
- regulator-max-microvolt = <1120000>;
- };
-
- vreg_s8b_1p2: smps8 {
- regulator-name = "vreg_s8b_1p2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1496000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
- };
-
- vreg_l1b_0p912: ldo1 {
- regulator-name = "vreg_l1b_0p912";
- regulator-min-microvolt = <832000>;
- regulator-max-microvolt = <920000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l2b_3p072: ldo2 {
- regulator-name = "vreg_l2b_3p072";
- regulator-min-microvolt = <2704000>;
- regulator-max-microvolt = <3544000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l6b_1p2: ldo6 {
- regulator-name = "vreg_l6b_1p2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1256000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l7b_2p96: ldo7 {
- regulator-name = "vreg_l7b_2p96";
- regulator-min-microvolt = <2960000>;
- regulator-max-microvolt = <2960000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l9b_1p2: ldo9 {
- regulator-name = "vreg_l9b_1p2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1304000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l17b_1p8: ldo17 {
- regulator-name = "vreg_l17b_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1896000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l18b_1p8: ldo18 {
- regulator-name = "vreg_l18b_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2000000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-always-on;
- };
-
- vreg_l19b_1p8: ldo19 {
- regulator-name = "vreg_l19b_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2000000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
- };
-
- regulators-1 {
- compatible = "qcom,pm8350c-rpmh-regulators";
- qcom,pmic-id = "c";
-
- vdd-s1-supply = <&vph_pwr>;
- vdd-s2-supply = <&vph_pwr>;
- vdd-s3-supply = <&vph_pwr>;
- vdd-s4-supply = <&vph_pwr>;
- vdd-s5-supply = <&vph_pwr>;
- vdd-s6-supply = <&vph_pwr>;
- vdd-s7-supply = <&vph_pwr>;
- vdd-s8-supply = <&vph_pwr>;
- vdd-s9-supply = <&vph_pwr>;
- vdd-s10-supply = <&vph_pwr>;
- vdd-l1-l12-supply = <&vreg_s1b_1p84>;
- vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
- vdd-l10-supply = <&vreg_s7b_0p536>;
- vdd-bob-supply = <&vph_pwr>;
-
- vreg_l1c_1p8: ldo1 {
- regulator-name = "vreg_l1c_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1976000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l6c_2p96: ldo6 {
- regulator-name = "vreg_l6c_2p96";
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <3544000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l9c_2p96: ldo9 {
- regulator-name = "vreg_l9c_2p96";
- regulator-min-microvolt = <2704000>;
- regulator-max-microvolt = <3544000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l10c_0p88: ldo10 {
- regulator-name = "vreg_l10c_0p88";
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <1048000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_bob_3p296: bob {
- regulator-name = "vreg_bob_3p296";
- regulator-min-microvolt = <3032000>;
- regulator-max-microvolt = <3960000>;
- };
- };
-};
-
-&gcc {
- protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
- <GCC_MSS_CFG_AHB_CLK>,
- <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
- <GCC_MSS_OFFLINE_AXI_CLK>,
- <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
- <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
- <GCC_MSS_SNOC_AXI_CLK>,
- <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
- <GCC_QSPI_CORE_CLK>,
- <GCC_QSPI_CORE_CLK_SRC>,
- <GCC_SEC_CTRL_CLK_SRC>,
- <GCC_WPSS_AHB_BDG_MST_CLK>,
- <GCC_WPSS_AHB_CLK>,
- <GCC_WPSS_RSCP_CLK>;
-};
-
-&gpi_dma0 {
- status = "okay";
-};
-
-&gpi_dma1 {
- status = "okay";
-};
-
-&gpu {
- status = "okay";
-};
-
-&gpu_zap_shader {
- firmware-name = "qcom/qcs6490/a660_zap.mbn";
-};
-
-/* Pin 13, 15 in GPIO header */
-&i2c0 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-/* Pin 27, 28 in GPIO header */
-&i2c2 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-/* Pin 3, 5 in GPIO header */
-&i2c6 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-&i2c10 {
- qcom,enable-gsi-dma;
- status = "okay";
-
- rtc: rtc@68 {
- compatible = "st,m41t11";
- reg = <0x68>;
- };
-};
-
-/* External touchscreen */
-&i2c13 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
&lpass_audiocc {
compatible = "qcom,qcm6490-lpassaudiocc";
/delete-property/ power-domains;
@@ -580,207 +25,6 @@ &lpass_va_macro {
status = "okay";
};
-&mdss {
- status = "okay";
-};
-
-&mdss_dp {
- sound-name-prefix = "Display Port0";
-
- status = "okay";
-};
-
-&mdss_dp_out {
- data-lanes = <0 1>;
- remote-endpoint = <&usb_dp_qmpphy_dp_in>;
-};
-
-&pcie0 {
- perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
-
- pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&pcie0_phy {
- vdda-phy-supply = <&vreg_l10c_0p88>;
- vdda-pll-supply = <&vreg_l6b_1p2>;
-
- status = "okay";
-};
-
-&pcie1 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-
- pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
- pinctrl-names = "default";
-
- /* Support for QPS615 PCIe switch */
- iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
- <0x100 &apps_smmu 0x1c81 0x1>,
- <0x208 &apps_smmu 0x1c84 0x1>,
- <0x210 &apps_smmu 0x1c85 0x1>,
- <0x218 &apps_smmu 0x1c86 0x1>,
- <0x300 &apps_smmu 0x1c87 0x1>,
- <0x400 &apps_smmu 0x1c88 0x1>,
- <0x500 &apps_smmu 0x1c89 0x1>,
- <0x501 &apps_smmu 0x1c90 0x1>;
-
- status = "okay";
-};
-
-&pcie1_phy {
- vdda-phy-supply = <&vreg_l10c_0p88>;
- vdda-pll-supply = <&vreg_l6b_1p2>;
-
- status = "okay";
-};
-
-&pm7325_gpios {
- pm7325_adc_default: adc-default-state {
- pins = "gpio2";
- function = PMIC_GPIO_FUNC_NORMAL;
- bias-high-impedance;
- };
-};
-
-&pm7325_temp_alarm {
- io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>;
- io-channel-names = "thermal";
-};
-
-&pmk8350_adc_tm {
- status = "okay";
-
- xo-therm@0 {
- reg = <0>;
- io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
- };
-
- quiet-therm@1 {
- reg = <1>;
- io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
- };
-
- msm-skin-therm@2 {
- reg = <2>;
- io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
- };
-
- ufs-therm@3 {
- reg = <3>;
- io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
- };
-};
-
-&pmk8350_vadc {
- pinctrl-0 = <&pm7325_adc_default>;
- pinctrl-names = "default";
-
- channel@3 {
- reg = <PMK8350_ADC7_DIE_TEMP>;
- label = "pmk7325_die_temp";
- qcom,pre-scaling = <1 1>;
- };
-
- channel@44 {
- reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
- label = "xo_therm";
- qcom,hw-settle-time = <200>;
- qcom,pre-scaling = <1 1>;
- qcom,ratiometric;
- };
-
- channel@103 {
- reg = <PM7325_ADC7_DIE_TEMP>;
- label = "pm7325_die_temp";
- qcom,pre-scaling = <1 1>;
- };
-
- channel@144 {
- reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time = <200>;
- qcom,pre-scaling = <1 1>;
- label = "quiet_therm";
- };
-
- channel@146 {
- reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time = <200>;
- qcom,pre-scaling = <1 1>;
- label = "msm_skin_therm";
- };
-
- channel@14a {
- /* According to datasheet, 0x4a = AMUX1_GPIO = GPIO_02 */
- reg = <PM7325_ADC7_GPIO1_100K_PU>;
- qcom,ratiometric;
- qcom,hw-settle-time = <200>;
- qcom,pre-scaling = <1 1>;
- label = "ufs_therm";
- };
-};
-
-&pon_pwrkey {
- status = "okay";
-};
-
-&qupv3_id_0 {
- firmware-name = "qcom/qcm6490/qupv3fw.elf";
- status = "okay";
-};
-
-&qupv3_id_1 {
- firmware-name = "qcom/qcm6490/qupv3fw.elf";
- status = "okay";
-};
-
-&remoteproc_adsp {
- firmware-name = "qcom/qcs6490/radxa/dragon-q6a/adsp.mbn";
- status = "okay";
-};
-
-&remoteproc_cdsp {
- firmware-name = "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn";
- status = "okay";
-};
-
-&sdhc_1 {
- non-removable;
- no-sd;
- no-sdio;
-
- vmmc-supply = <&vreg_l7b_2p96>;
- vqmmc-supply = <&vreg_l19b_1p8>;
-
- status = "okay";
-};
-
-&sdhc_2 {
- pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>;
- pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>;
-
- vmmc-supply = <&vreg_l9c_2p96>;
- vqmmc-supply = <&vreg_l6c_2p96>;
-
- cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
&sound {
compatible = "qcom,qcs6490-rb3gen2-sndcard";
model = "QCS6490-Radxa-Dragon-Q6A";
@@ -838,378 +82,3 @@ platform {
};
};
};
-
-/* Pin 11, 29, 31, 32 in GPIO header */
-&spi7 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-/* Pin 19, 21, 23, 24, 26 in GPIO header */
-&spi12 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-/* Pin 22, 33, 36, 37 in GPIO header */
-&spi14 {
- qcom,enable-gsi-dma;
- status = "okay";
-};
-
-&swr0 {
- status = "okay";
-
- wcd_rx: codec@0,4 {
- compatible = "sdw20217010d00";
- reg = <0 4>;
- qcom,rx-port-mapping = <1 2 3 4 5>;
- };
-};
-
-&swr1 {
- status = "okay";
-
- wcd_tx: codec@0,3 {
- compatible = "sdw20217010d00";
- reg = <0 3>;
- qcom,tx-port-mapping = <1 1 2 3>;
- };
-};
-
-&tlmm {
- /*
- * 12-17: reserved for QSPI flash
- */
- gpio-reserved-ranges = <12 6>;
- gpio-line-names =
- /* GPIO_0 ~ GPIO_3 */
- "PIN_13", "PIN_15", "", "",
- /* GPIO_4 ~ GPIO_7 */
- "", "", "", "",
- /* GPIO_8 ~ GPIO_11 */
- "PIN_27", "PIN_28", "", "",
- /* GPIO_12 ~ GPIO_15 */
- "", "", "", "",
- /* GPIO_16 ~ GPIO_19 */
- "", "", "", "",
- /* GPIO_20 ~ GPIO_23 */
- "", "", "PIN_8", "PIN_10",
- /* GPIO_24 ~ GPIO_27 */
- "PIN_3", "PIN_5", "PIN_16", "PIN_18",
- /* GPIO_28 ~ GPIO_31 */
- "PIN_31", "PIN_11", "PIN_32", "PIN_29",
- /* GPIO_32 ~ GPIO_35 */
- "", "", "", "",
- /* GPIO_36 ~ GPIO_39 */
- "", "", "", "",
- /* GPIO_40 ~ GPIO_43 */
- "", "", "", "",
- /* GPIO_44 ~ GPIO_47 */
- "", "", "", "",
- /* GPIO_48 ~ GPIO_51 */
- "PIN_21", "PIN_19", "PIN_23", "PIN_24",
- /* GPIO_52 ~ GPIO_55 */
- "", "", "", "PIN_26",
- /* GPIO_56 ~ GPIO_59 */
- "PIN_33", "PIN_22", "PIN_37", "PIN_36",
- /* GPIO_60 ~ GPIO_63 */
- "", "", "", "",
- /* GPIO_64 ~ GPIO_67 */
- "", "", "", "",
- /* GPIO_68 ~ GPIO_71 */
- "", "", "", "",
- /* GPIO_72 ~ GPIO_75 */
- "", "", "", "",
- /* GPIO_76 ~ GPIO_79 */
- "", "", "", "",
- /* GPIO_80 ~ GPIO_83 */
- "", "", "", "",
- /* GPIO_84 ~ GPIO_87 */
- "", "", "", "",
- /* GPIO_88 ~ GPIO_91 */
- "", "", "", "",
- /* GPIO_92 ~ GPIO_95 */
- "", "", "", "",
- /* GPIO_96 ~ GPIO_99 */
- "PIN_7", "PIN_12", "PIN_38", "PIN_40",
- /* GPIO_100 ~ GPIO_103 */
- "PIN_35", "", "", "",
- /* GPIO_104 ~ GPIO_107 */
- "", "", "", "",
- /* GPIO_108 ~ GPIO_111 */
- "", "", "", "",
- /* GPIO_112 ~ GPIO_115 */
- "", "", "", "",
- /* GPIO_116 ~ GPIO_119 */
- "", "", "", "",
- /* GPIO_120 ~ GPIO_123 */
- "", "", "", "",
- /* GPIO_124 ~ GPIO_127 */
- "", "", "", "",
- /* GPIO_128 ~ GPIO_131 */
- "", "", "", "",
- /* GPIO_132 ~ GPIO_135 */
- "", "", "", "",
- /* GPIO_136 ~ GPIO_139 */
- "", "", "", "",
- /* GPIO_140 ~ GPIO_143 */
- "", "", "", "",
- /* GPIO_144 ~ GPIO_147 */
- "", "", "", "",
- /* GPIO_148 ~ GPIO_151 */
- "", "", "", "",
- /* GPIO_152 ~ GPIO_155 */
- "", "", "", "",
- /* GPIO_156 ~ GPIO_159 */
- "", "", "", "",
- /* GPIO_160 ~ GPIO_163 */
- "", "", "", "",
- /* GPIO_164 ~ GPIO_167 */
- "", "", "", "",
- /* GPIO_168 ~ GPIO_171 */
- "", "", "", "",
- /* GPIO_172 ~ GPIO_174 */
- "", "", "";
-
- pcie0_reset_n: pcie0-reset-n-state {
- pins = "gpio87";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- pcie0_wake_n: pcie0-wake-n-state {
- pins = "gpio89";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- pcie1_reset_n: pcie1-reset-n-state {
- pins = "gpio2";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- pcie1_wake_n: pcie1-wake-n-state {
- pins = "gpio3";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- sd_cd: sd-cd-state {
- pins = "gpio91";
- function = "gpio";
- bias-pull-up;
- };
-
- user_led: user-led-state {
- pins = "gpio42";
- function = "gpio";
- bias-pull-up;
- };
-
- wcd_default: wcd-reset-n-active-state {
- pins = "gpio83";
- function = "gpio";
- drive-strength = <16>;
- bias-disable;
- output-low;
- };
-};
-
-&uart5 {
- status = "okay";
-};
-
-&ufs_mem_hc {
- reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
- vcc-supply = <&vreg_l7b_2p96>;
- vcc-max-microamp = <800000>;
- vccq-supply = <&vreg_l9b_1p2>;
- vccq-max-microamp = <900000>;
- vccq2-supply = <&vreg_l9b_1p2>;
- vccq2-max-microamp = <1300000>;
-
- /* Gear-4 Rate-B is unstable due to board */
- /* and UFS module design limitations */
- limit-gear-rate = "rate-a";
-
- status = "okay";
-};
-
-&ufs_mem_phy {
- vdda-phy-supply = <&vreg_l10c_0p88>;
- vdda-pll-supply = <&vreg_l6b_1p2>;
-
- status = "okay";
-};
-
-&usb_1 {
- dr_mode = "host";
-
- status = "okay";
-};
-
-&usb_1_dwc3_hs {
- remote-endpoint = <&usb3_con_hs_in>;
-};
-
-&usb_1_hsphy {
- vdda-pll-supply = <&vreg_l10c_0p88>;
- vdda33-supply = <&vreg_l2b_3p072>;
- vdda18-supply = <&vreg_l1c_1p8>;
-
- status = "okay";
-};
-
-&usb_1_qmpphy {
- vdda-phy-supply = <&vreg_l6b_1p2>;
- vdda-pll-supply = <&vreg_l1b_0p912>;
-
- /delete-property/ orientation-switch;
-
- status = "okay";
-
- ports {
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /delete-node/ endpoint;
-
- /* RX0/TX0 is statically connected to RA620 bridge */
- usb_1_qmpphy_out_dp: endpoint@0 {
- reg = <0>;
-
- data-lanes = <0 1>;
- remote-endpoint = <&hdmi_bridge_in>;
- };
-
- /* RX1/TX1 is statically connected to USB-A port */
- usb_1_qmpphy_out_usb: endpoint@1 {
- reg = <1>;
-
- data-lanes = <2 3>;
- remote-endpoint = <&usb3_con_ss_in>;
- };
- };
- };
-};
-
-&usb_2 {
- dr_mode = "host";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "okay";
-
- /* Onboard USB 2.0 hub */
- usb_hub_2_x: hub@1 {
- compatible = "usb1a40,0101";
- reg = <1>;
- vdd-supply = <&vcc_5v_peri>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
-
- usb_hub_2_1: endpoint {
- remote-endpoint = <&usb2_1_connector>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- usb_hub_2_2: endpoint {
- remote-endpoint = <&usb2_2_connector>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- usb_hub_2_3: endpoint {
- remote-endpoint = <&usb2_3_connector>;
- };
- };
- };
-
- /* FCU760K Wi-Fi & Bluetooth module */
- wifi@4 {
- compatible = "usba69c,8d80";
- reg = <4>;
- };
- };
-};
-
-&usb_2_hsphy {
- vdda-pll-supply = <&vreg_l10c_0p88>;
- vdda33-supply = <&vreg_l2b_3p072>;
- vdda18-supply = <&vreg_l1c_1p8>;
-
- status = "okay";
-};
-
-&venus {
- status = "okay";
-};
-
-/* PINCTRL - additions to nodes defined in sc7280.dtsi */
-&dp_hot_plug_det {
- bias-disable;
-};
-
-&pcie0_clkreq_n {
- bias-pull-up;
- drive-strength = <2>;
-};
-
-&pcie1_clkreq_n {
- bias-pull-up;
- drive-strength = <2>;
-};
-
-&sdc1_clk {
- bias-disable;
- drive-strength = <16>;
-};
-
-&sdc1_cmd {
- bias-pull-up;
- drive-strength = <10>;
-};
-
-&sdc1_data {
- bias-pull-up;
- drive-strength = <10>;
-};
-
-&sdc1_rclk {
- bias-pull-down;
-};
-
-&sdc2_clk {
- bias-disable;
- drive-strength = <16>;
-};
-
-&sdc2_cmd {
- bias-pull-up;
- drive-strength = <10>;
-};
-
-&sdc2_data {
- bias-pull-up;
- drive-strength = <10>;
-};
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi
new file mode 100644
index 000000000000..52c2f053c820
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi
@@ -0,0 +1,1137 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025-2026 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+/* PM7250B is configured to use SID8/9 */
+#define PM7250B_SID 8
+#define PM7250B_SID1 9
+
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "kodiak.dtsi"
+#include "pm7250b.dtsi"
+#include "pm7325.dtsi"
+#include "pm8350c.dtsi" /* PM7350C */
+#include "pmk8350.dtsi" /* PMK7325 */
+
+/delete-node/ &adsp_mem;
+/delete-node/ &adsp_rpc_remote_heap_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &gpu_zap_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &remoteproc_mpss;
+/delete-node/ &remoteproc_wpss;
+/delete-node/ &rmtfs_mem;
+/delete-node/ &video_mem;
+/delete-node/ &wifi;
+/delete-node/ &wlan_ce_mem;
+/delete-node/ &wlan_fw_mem;
+/delete-node/ &wpss_mem;
+
+/ {
+ model = "Radxa Dragon Q6A";
+ compatible = "radxa,dragon-q6a", "qcom,qcm6490";
+ chassis-type = "embedded";
+
+ aliases {
+ mmc0 = &sdhc_1;
+ mmc1 = &sdhc_2;
+ serial0 = &uart5;
+ };
+
+ wcd938x: audio-codec {
+ compatible = "qcom,wcd9380-codec";
+
+ pinctrl-0 = <&wcd_default>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
+
+ vdd-rxtx-supply = <&vreg_l18b_1p8>;
+ vdd-io-supply = <&vreg_l18b_1p8>;
+ vdd-buck-supply = <&vreg_l17b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob_3p296>;
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ qcom,hphl-jack-type-normally-closed;
+
+ #sound-dai-cells = <1>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb2_1_con: connector-0 {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vcc_5v_peri>;
+
+ port {
+ usb2_1_connector: endpoint {
+ remote-endpoint = <&usb_hub_2_1>;
+ };
+ };
+ };
+
+ usb2_2_con: connector-1 {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vcc_5v_peri>;
+
+ port {
+ usb2_2_connector: endpoint {
+ remote-endpoint = <&usb_hub_2_2>;
+ };
+ };
+ };
+
+ usb2_3_con: connector-2 {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vcc_5v_peri>;
+
+ port {
+ usb2_3_connector: endpoint {
+ remote-endpoint = <&usb_hub_2_3>;
+ };
+ };
+ };
+
+ usb3_con: connector {
+ compatible = "usb-a-connector";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb3_con_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb3_con_ss_in: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_out_usb>;
+ };
+ };
+ };
+ };
+
+ hdmi-bridge {
+ compatible = "radxa,ra620";
+
+ pinctrl-0 = <&dp_hot_plug_det>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_bridge_in: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_out_dp>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_bridge_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_bridge_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-0 = <&user_led>;
+ pinctrl-names = "default";
+
+ user-led {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ panic-indicator;
+ };
+ };
+
+ reserved-memory {
+ lpass_ml_mem: lpass-ml@81800000 {
+ reg = <0x0 0x81800000 0x0 0xf00000>;
+ no-map;
+ };
+
+ cdsp_secure_heap_mem: cdsp-secure-heap@82700000 {
+ reg = <0x0 0x82700000 0x0 0x10000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0x2800000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@8e000000 {
+ reg = <0x0 0x8e000000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ video_mem: video@8fe00000 {
+ reg = <0x0 0x8fe00000 0x0 0x500000>;
+ no-map;
+ };
+
+ gpu_zap_mem: zap@90300000 {
+ reg = <0x0 0x90300000 0x0 0x5000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat@c0000000 {
+ reg = <0x0 0xc0000000 0x0 0x100000>;
+ no-map;
+ };
+
+ tags_mem: tags@c0100000 {
+ reg = <0x0 0xc0100000 0x0 0x1200000>;
+ no-map;
+ };
+
+ qtee_mem: qtee@c1300000 {
+ reg = <0x0 0xc1300000 0x0 0x500000>;
+ no-map;
+ };
+
+ trusted_apps_mem: trusted-apps@c1800000 {
+ reg = <0x0 0xc1800000 0x0 0x2200000>;
+ no-map;
+ };
+
+ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@c6500000 {
+ reg = <0x0 0xc6500000 0x0 0x800000>;
+ no-map;
+ };
+ };
+
+ thermal-zones {
+ msm-skin-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 2>;
+ };
+
+ quiet-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 1>;
+ };
+
+ ufs-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 3>;
+ };
+
+ xo-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 0>;
+ };
+ };
+
+ vcc_1v8: regulator-vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_5v_peri>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v_peri>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_5v_peri: regulator-vcc-5v-peri {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v_peri";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vph_pwr>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7325-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p536>;
+ vdd-l2-l7-supply = <&vreg_bob_3p296>;
+ vdd-l6-l9-l10-supply = <&vreg_s8b_1p2>;
+ vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p84>;
+
+ vreg_s1b_1p84: smps1 {
+ regulator-name = "vreg_s1b_1p84";
+ regulator-min-microvolt = <1840000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s7b_0p536: smps7 {
+ regulator-name = "vreg_s7b_0p536";
+ regulator-min-microvolt = <536000>;
+ regulator-max-microvolt = <1120000>;
+ };
+
+ vreg_s8b_1p2: smps8 {
+ regulator-name = "vreg_s8b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1496000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_l1b_0p912: ldo1 {
+ regulator-name = "vreg_l1b_0p912";
+ regulator-min-microvolt = <832000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p072: ldo2 {
+ regulator-name = "vreg_l2b_3p072";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p2: ldo6 {
+ regulator-name = "vreg_l6b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p96: ldo7 {
+ regulator-name = "vreg_l7b_2p96";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_1p2: ldo9 {
+ regulator-name = "vreg_l9b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_1p8: ldo17 {
+ regulator-name = "vreg_l17b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1896000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p8: ldo18 {
+ regulator-name = "vreg_l18b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l19b_1p8: ldo19 {
+ regulator-name = "vreg_l19b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-l1-l12-supply = <&vreg_s1b_1p84>;
+ vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
+ vdd-l10-supply = <&vreg_s7b_0p536>;
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-name = "vreg_l1c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1976000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p96: ldo6 {
+ regulator-name = "vreg_l6c_2p96";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p96: ldo9 {
+ regulator-name = "vreg_l9c_2p96";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10c_0p88: ldo10 {
+ regulator-name = "vreg_l10c_0p88";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1048000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob_3p296: bob {
+ regulator-name = "vreg_bob_3p296";
+ regulator-min-microvolt = <3032000>;
+ regulator-max-microvolt = <3960000>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
+ <GCC_MSS_CFG_AHB_CLK>,
+ <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
+ <GCC_MSS_OFFLINE_AXI_CLK>,
+ <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+ <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+ <GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_SEC_CTRL_CLK_SRC>,
+ <GCC_WPSS_AHB_BDG_MST_CLK>,
+ <GCC_WPSS_AHB_CLK>,
+ <GCC_WPSS_RSCP_CLK>;
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/qcs6490/a660_zap.mbn";
+};
+
+/* Pin 13, 15 in GPIO header */
+&i2c0 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+/* Pin 27, 28 in GPIO header */
+&i2c2 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+/* Pin 3, 5 in GPIO header */
+&i2c6 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+&i2c10 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+
+ rtc: rtc@68 {
+ compatible = "st,m41t11";
+ reg = <0x68>;
+ };
+};
+
+/* External touchscreen */
+&i2c13 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp {
+ sound-name-prefix = "Display Port0";
+
+ status = "okay";
+};
+
+&mdss_dp_out {
+ data-lanes = <0 1>;
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+};
+
+&pcie0 {
+ perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&pcie1 {
+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
+ pinctrl-names = "default";
+
+ /* Support for QPS615 PCIe switch */
+ iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+ <0x100 &apps_smmu 0x1c81 0x1>,
+ <0x208 &apps_smmu 0x1c84 0x1>,
+ <0x210 &apps_smmu 0x1c85 0x1>,
+ <0x218 &apps_smmu 0x1c86 0x1>,
+ <0x300 &apps_smmu 0x1c87 0x1>,
+ <0x400 &apps_smmu 0x1c88 0x1>,
+ <0x500 &apps_smmu 0x1c89 0x1>,
+ <0x501 &apps_smmu 0x1c90 0x1>;
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&pm7325_gpios {
+ pm7325_adc_default: adc-default-state {
+ pins = "gpio2";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-high-impedance;
+ };
+};
+
+&pm7325_temp_alarm {
+ io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>;
+ io-channel-names = "thermal";
+};
+
+&pmk8350_adc_tm {
+ status = "okay";
+
+ xo-therm@0 {
+ reg = <0>;
+ io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ quiet-therm@1 {
+ reg = <1>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ msm-skin-therm@2 {
+ reg = <2>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ ufs-therm@3 {
+ reg = <3>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pmk8350_vadc {
+ pinctrl-0 = <&pm7325_adc_default>;
+ pinctrl-names = "default";
+
+ channel@3 {
+ reg = <PMK8350_ADC7_DIE_TEMP>;
+ label = "pmk7325_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@44 {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ label = "xo_therm";
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ };
+
+ channel@103 {
+ reg = <PM7325_ADC7_DIE_TEMP>;
+ label = "pm7325_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@144 {
+ reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "quiet_therm";
+ };
+
+ channel@146 {
+ reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "msm_skin_therm";
+ };
+
+ channel@14a {
+ /* According to datasheet, 0x4a = AMUX1_GPIO = GPIO_02 */
+ reg = <PM7325_ADC7_GPIO1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "ufs_therm";
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ firmware-name = "qcom/qcm6490/qupv3fw.elf";
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ firmware-name = "qcom/qcm6490/qupv3fw.elf";
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcs6490/radxa/dragon-q6a/adsp.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn";
+ status = "okay";
+};
+
+&sdhc_1 {
+ non-removable;
+ no-sd;
+ no-sdio;
+
+ vmmc-supply = <&vreg_l7b_2p96>;
+ vqmmc-supply = <&vreg_l19b_1p8>;
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>;
+ pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>;
+
+ vmmc-supply = <&vreg_l9c_2p96>;
+ vqmmc-supply = <&vreg_l6c_2p96>;
+
+ cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* Pin 11, 29, 31, 32 in GPIO header */
+&spi7 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+/* Pin 19, 21, 23, 24, 26 in GPIO header */
+&spi12 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+/* Pin 22, 33, 36, 37 in GPIO header */
+&spi14 {
+ qcom,enable-gsi-dma;
+ status = "okay";
+};
+
+&swr0 {
+ status = "okay";
+
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <1 1 2 3>;
+ };
+};
+
+&tlmm {
+ /*
+ * 12-17: reserved for QSPI flash
+ */
+ gpio-reserved-ranges = <12 6>;
+ gpio-line-names =
+ /* GPIO_0 ~ GPIO_3 */
+ "PIN_13", "PIN_15", "", "",
+ /* GPIO_4 ~ GPIO_7 */
+ "", "", "", "",
+ /* GPIO_8 ~ GPIO_11 */
+ "PIN_27", "PIN_28", "", "",
+ /* GPIO_12 ~ GPIO_15 */
+ "", "", "", "",
+ /* GPIO_16 ~ GPIO_19 */
+ "", "", "", "",
+ /* GPIO_20 ~ GPIO_23 */
+ "", "", "PIN_8", "PIN_10",
+ /* GPIO_24 ~ GPIO_27 */
+ "PIN_3", "PIN_5", "PIN_16", "PIN_18",
+ /* GPIO_28 ~ GPIO_31 */
+ "PIN_31", "PIN_11", "PIN_32", "PIN_29",
+ /* GPIO_32 ~ GPIO_35 */
+ "", "", "", "",
+ /* GPIO_36 ~ GPIO_39 */
+ "", "", "", "",
+ /* GPIO_40 ~ GPIO_43 */
+ "", "", "", "",
+ /* GPIO_44 ~ GPIO_47 */
+ "", "", "", "",
+ /* GPIO_48 ~ GPIO_51 */
+ "PIN_21", "PIN_19", "PIN_23", "PIN_24",
+ /* GPIO_52 ~ GPIO_55 */
+ "", "", "", "PIN_26",
+ /* GPIO_56 ~ GPIO_59 */
+ "PIN_33", "PIN_22", "PIN_37", "PIN_36",
+ /* GPIO_60 ~ GPIO_63 */
+ "", "", "", "",
+ /* GPIO_64 ~ GPIO_67 */
+ "", "", "", "",
+ /* GPIO_68 ~ GPIO_71 */
+ "", "", "", "",
+ /* GPIO_72 ~ GPIO_75 */
+ "", "", "", "",
+ /* GPIO_76 ~ GPIO_79 */
+ "", "", "", "",
+ /* GPIO_80 ~ GPIO_83 */
+ "", "", "", "",
+ /* GPIO_84 ~ GPIO_87 */
+ "", "", "", "",
+ /* GPIO_88 ~ GPIO_91 */
+ "", "", "", "",
+ /* GPIO_92 ~ GPIO_95 */
+ "", "", "", "",
+ /* GPIO_96 ~ GPIO_99 */
+ "PIN_7", "PIN_12", "PIN_38", "PIN_40",
+ /* GPIO_100 ~ GPIO_103 */
+ "PIN_35", "", "", "",
+ /* GPIO_104 ~ GPIO_107 */
+ "", "", "", "",
+ /* GPIO_108 ~ GPIO_111 */
+ "", "", "", "",
+ /* GPIO_112 ~ GPIO_115 */
+ "", "", "", "",
+ /* GPIO_116 ~ GPIO_119 */
+ "", "", "", "",
+ /* GPIO_120 ~ GPIO_123 */
+ "", "", "", "",
+ /* GPIO_124 ~ GPIO_127 */
+ "", "", "", "",
+ /* GPIO_128 ~ GPIO_131 */
+ "", "", "", "",
+ /* GPIO_132 ~ GPIO_135 */
+ "", "", "", "",
+ /* GPIO_136 ~ GPIO_139 */
+ "", "", "", "",
+ /* GPIO_140 ~ GPIO_143 */
+ "", "", "", "",
+ /* GPIO_144 ~ GPIO_147 */
+ "", "", "", "",
+ /* GPIO_148 ~ GPIO_151 */
+ "", "", "", "",
+ /* GPIO_152 ~ GPIO_155 */
+ "", "", "", "",
+ /* GPIO_156 ~ GPIO_159 */
+ "", "", "", "",
+ /* GPIO_160 ~ GPIO_163 */
+ "", "", "", "",
+ /* GPIO_164 ~ GPIO_167 */
+ "", "", "", "",
+ /* GPIO_168 ~ GPIO_171 */
+ "", "", "", "",
+ /* GPIO_172 ~ GPIO_174 */
+ "", "", "";
+
+ pcie0_reset_n: pcie0-reset-n-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie0_wake_n: pcie0-wake-n-state {
+ pins = "gpio89";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcie1_reset_n: pcie1-reset-n-state {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie1_wake_n: pcie1-wake-n-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sd_cd: sd-cd-state {
+ pins = "gpio91";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ user_led: user-led-state {
+ pins = "gpio42";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l7b_2p96>;
+ vcc-max-microamp = <800000>;
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <900000>;
+ vccq2-supply = <&vreg_l9b_1p2>;
+ vccq2-max-microamp = <1300000>;
+
+ /* Gear-4 Rate-B is unstable due to board */
+ /* and UFS module design limitations */
+ limit-gear-rate = "rate-a";
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ dr_mode = "host";
+
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&usb3_con_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l10c_0p88>;
+ vdda33-supply = <&vreg_l2b_3p072>;
+ vdda18-supply = <&vreg_l1c_1p8>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l6b_1p2>;
+ vdda-pll-supply = <&vreg_l1b_0p912>;
+
+ /delete-property/ orientation-switch;
+
+ status = "okay";
+
+ ports {
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /delete-node/ endpoint;
+
+ /* RX0/TX0 is statically connected to RA620 bridge */
+ usb_1_qmpphy_out_dp: endpoint@0 {
+ reg = <0>;
+
+ data-lanes = <0 1>;
+ remote-endpoint = <&hdmi_bridge_in>;
+ };
+
+ /* RX1/TX1 is statically connected to USB-A port */
+ usb_1_qmpphy_out_usb: endpoint@1 {
+ reg = <1>;
+
+ data-lanes = <2 3>;
+ remote-endpoint = <&usb3_con_ss_in>;
+ };
+ };
+ };
+};
+
+&usb_2 {
+ dr_mode = "host";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ /* Onboard USB 2.0 hub */
+ usb_hub_2_x: hub@1 {
+ compatible = "usb1a40,0101";
+ reg = <1>;
+ vdd-supply = <&vcc_5v_peri>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ usb_hub_2_1: endpoint {
+ remote-endpoint = <&usb2_1_connector>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_hub_2_2: endpoint {
+ remote-endpoint = <&usb2_2_connector>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ usb_hub_2_3: endpoint {
+ remote-endpoint = <&usb2_3_connector>;
+ };
+ };
+ };
+
+ /* FCU760K Wi-Fi & Bluetooth module */
+ wifi@4 {
+ compatible = "usba69c,8d80";
+ reg = <4>;
+ };
+ };
+};
+
+&usb_2_hsphy {
+ vdda-pll-supply = <&vreg_l10c_0p88>;
+ vdda33-supply = <&vreg_l2b_3p072>;
+ vdda18-supply = <&vreg_l1c_1p8>;
+
+ status = "okay";
+};
+
+&venus {
+ status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in sc7280.dtsi */
+&dp_hot_plug_det {
+ bias-disable;
+};
+
+&pcie0_clkreq_n {
+ bias-pull-up;
+ drive-strength = <2>;
+};
+
+&pcie1_clkreq_n {
+ bias-pull-up;
+ drive-strength = <2>;
+};
+
+&sdc1_clk {
+ bias-disable;
+ drive-strength = <16>;
+};
+
+&sdc1_cmd {
+ bias-pull-up;
+ drive-strength = <10>;
+};
+
+&sdc1_data {
+ bias-pull-up;
+ drive-strength = <10>;
+};
+
+&sdc1_rclk {
+ bias-pull-down;
+};
+
+&sdc2_clk {
+ bias-disable;
+ drive-strength = <16>;
+};
+
+&sdc2_cmd {
+ bias-pull-up;
+ drive-strength = <10>;
+};
+
+&sdc2_data {
+ bias-pull-up;
+ drive-strength = <10>;
+};
--
2.53.0
^ permalink raw reply related
* [PATCH 09/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Align reserved-memory with latest firmware map
From: Xilin Wu @ 2026-04-07 15:20 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
The current board DTS no longer matches the reserved-memory carveouts
used by the latest official Dragon Q6A firmware. Update the memory map
to keep the DTS in sync with firmware expectations.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 43 +++++++++-------------
1 file changed, 17 insertions(+), 26 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index fe3f60f8ed5a..5679f38de5b3 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -22,7 +22,9 @@
#include "qcs6490-audioreach.dtsi"
/delete-node/ &adsp_mem;
+/delete-node/ &adsp_rpc_remote_heap_mem;
/delete-node/ &cdsp_mem;
+/delete-node/ &gpu_zap_mem;
/delete-node/ &ipa_fw_mem;
/delete-node/ &mpss_mem;
/delete-node/ &remoteproc_mpss;
@@ -33,7 +35,6 @@
/delete-node/ &wlan_ce_mem;
/delete-node/ &wlan_fw_mem;
/delete-node/ &wpss_mem;
-/delete-node/ &xbl_mem;
/ {
model = "Radxa Dragon Q6A";
@@ -193,43 +194,33 @@ user-led {
};
reserved-memory {
- xbl_mem: xbl@80700000 {
- reg = <0x0 0x80700000 0x0 0x100000>;
+ lpass_ml_mem: lpass-ml@81800000 {
+ reg = <0x0 0x81800000 0x0 0xf00000>;
no-map;
};
- cdsp_secure_heap_mem: cdsp-secure-heap@81800000 {
- reg = <0x0 0x81800000 0x0 0x1e00000>;
+ cdsp_secure_heap_mem: cdsp-secure-heap@82700000 {
+ reg = <0x0 0x82700000 0x0 0x10000>;
no-map;
};
- camera_mem: camera@84300000 {
- reg = <0x0 0x84300000 0x0 0x500000>;
+ adsp_mem: adsp@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0x2800000>;
no-map;
};
- adsp_mem: adsp@84800000 {
- reg = <0x0 0x84800000 0x0 0x2800000>;
+ cdsp_mem: cdsp@8e000000 {
+ reg = <0x0 0x8e000000 0x0 0x1e00000>;
no-map;
};
- cdsp_mem: cdsp@87000000 {
- reg = <0x0 0x87000000 0x0 0x1e00000>;
+ video_mem: video@8fe00000 {
+ reg = <0x0 0x8fe00000 0x0 0x500000>;
no-map;
};
- video_mem: video@88e00000 {
- reg = <0x0 0x88e00000 0x0 0x700000>;
- no-map;
- };
-
- cvp_mem: cvp@89500000 {
- reg = <0x0 0x89500000 0x0 0x500000>;
- no-map;
- };
-
- gpu_microcode_mem: gpu-microcode@89a00000 {
- reg = <0x0 0x89a00000 0x0 0x2000>;
+ gpu_zap_mem: zap@90300000 {
+ reg = <0x0 0x90300000 0x0 0x5000>;
no-map;
};
@@ -249,12 +240,12 @@ qtee_mem: qtee@c1300000 {
};
trusted_apps_mem: trusted-apps@c1800000 {
- reg = <0x0 0xc1800000 0x0 0x1c00000>;
+ reg = <0x0 0xc1800000 0x0 0x2200000>;
no-map;
};
- debug_vm_mem: debug-vm@d0600000 {
- reg = <0x0 0xd0600000 0x0 0x100000>;
+ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@c6500000 {
+ reg = <0x0 0xc6500000 0x0 0x800000>;
no-map;
};
};
--
2.53.0
^ permalink raw reply related
* [PATCH 08/12] arm64: dts: qcom: kodiak: Mark secondary USB controller as wakeup source
From: Xilin Wu @ 2026-04-07 15:20 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu, Stephen Chen
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
From: Stephen Chen <stephen@radxa.com>
Mark the secondary USB controller (usb_2) as a wakeup source so that it
can be used to wake the system from suspend.
Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 3a30126af3d4..940ec799e905 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -4404,6 +4404,7 @@ usb_2: usb@8c00000 {
phy-names = "usb2-phy";
maximum-speed = "high-speed";
usb-role-switch;
+ wakeup-source;
port {
usb2_role_switch: endpoint {
--
2.53.0
^ permalink raw reply related
* [PATCH 07/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Correct GPIO_27 label
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu, Stephen Chen
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
From: Stephen Chen <stephen@radxa.com>
The label of GPIO_27 is wrong. Fix it.
Fixes: ef254b12ec60 ("arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A")
Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 8d6bb4b0724b..fe3f60f8ed5a 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -905,7 +905,7 @@ &tlmm {
/* GPIO_20 ~ GPIO_23 */
"", "", "PIN_8", "PIN_10",
/* GPIO_24 ~ GPIO_27 */
- "PIN_3", "PIN_5", "PIN_16", "PIN_27",
+ "PIN_3", "PIN_5", "PIN_16", "PIN_18",
/* GPIO_28 ~ GPIO_31 */
"PIN_31", "PIN_11", "PIN_32", "PIN_29",
/* GPIO_32 ~ GPIO_35 */
--
2.53.0
^ permalink raw reply related
* [PATCH 04/12] arm64: dts: qcom: kodiak: Add I2C aliases for CCI
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu, Stephen Chen
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
From: Stephen Chen <stephen@radxa.com>
Add I2C bus aliases (i2c16-i2c19) for the CCI (Camera Control Interface)
I2C buses, allowing a stable numbering of these buses independent of
probe order.
Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 988ca5f7c8a0..3a30126af3d4 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -57,6 +57,10 @@ aliases {
i2c13 = &i2c13;
i2c14 = &i2c14;
i2c15 = &i2c15;
+ i2c16 = &cci0_i2c0;
+ i2c17 = &cci0_i2c1;
+ i2c18 = &cci1_i2c0;
+ i2c19 = &cci1_i2c1;
mmc1 = &sdhc_1;
mmc2 = &sdhc_2;
spi0 = &spi0;
--
2.53.0
^ permalink raw reply related
* [PATCH 06/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Drop QSPI node and reserve its pins
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
The latest official boot firmware configures TrustZone to restrict
direct access to the QSPI controller. Any attempt to access it from
the non-secure world causes an immediate board reset.
Remove the QSPI flash node and its associated pinctrl states, mark
GPIOs 12-17 as reserved, and protect the QSPI clocks in the GCC
node to prevent the kernel from touching this hardware.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 60 +++-------------------
1 file changed, 7 insertions(+), 53 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 91f1b4f57915..8d6bb4b0724b 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -513,6 +513,9 @@ &gcc {
<GCC_MSS_Q6SS_BOOT_CLK_SRC>,
<GCC_MSS_Q6_MEMNOC_AXI_CLK>,
<GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
<GCC_SEC_CTRL_CLK_SRC>,
<GCC_WPSS_AHB_BDG_MST_CLK>,
<GCC_WPSS_AHB_CLK>,
@@ -745,28 +748,6 @@ &pon_pwrkey {
status = "okay";
};
-&qspi {
- /* It's not possible to use QSPI with iommu */
- /* due to an error in qcom_smmu_write_s2cr */
- /delete-property/ iommus;
-
- pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>,
- <&qspi_data1>, <&qspi_data23>;
- pinctrl-1 = <&qspi_sleep>;
- pinctrl-names = "default", "sleep";
-
- status = "okay";
-
- spi_flash: flash@0 {
- compatible = "winbond,w25q256", "jedec,spi-nor";
- reg = <0>;
-
- spi-max-frequency = <104000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- };
-};
-
&qupv3_id_0 {
firmware-name = "qcom/qcm6490/qupv3fw.elf";
status = "okay";
@@ -906,6 +887,10 @@ wcd_tx: codec@0,3 {
};
&tlmm {
+ /*
+ * 12-17: reserved for QSPI flash
+ */
+ gpio-reserved-ranges = <12 6>;
gpio-line-names =
/* GPIO_0 ~ GPIO_3 */
"PIN_13", "PIN_15", "", "",
@@ -1024,12 +1009,6 @@ pcie1_wake_n: pcie1-wake-n-state {
bias-pull-up;
};
- qspi_sleep: qspi-sleep-state {
- pins = "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17";
- function = "gpio";
- output-disable;
- };
-
sd_cd: sd-cd-state {
pins = "gpio91";
function = "gpio";
@@ -1210,31 +1189,6 @@ &pcie1_clkreq_n {
drive-strength = <2>;
};
-&qspi_clk {
- bias-disable;
- drive-strength = <16>;
-};
-
-&qspi_cs0 {
- bias-disable;
- drive-strength = <8>;
-};
-
-&qspi_data0 {
- bias-disable;
- drive-strength = <8>;
-};
-
-&qspi_data1 {
- bias-disable;
- drive-strength = <8>;
-};
-
-&qspi_data23 {
- bias-disable;
- drive-strength = <8>;
-};
-
&sdc1_clk {
bias-disable;
drive-strength = <16>;
--
2.53.0
^ permalink raw reply related
* [PATCH 05/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Use board-specific CDSP firmware
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
The official boot firmware for Dragon Q6A has been switched to the
Qualcomm WP (Windows) boot firmware. Use the matching board-specific
CDSP firmware instead of the generic one so that the DSP firmware stack
remains compatible with the new boot firmware.
The corresponding custom DSP firmware has already been added to
linux-firmware:
https://gitlab.com/kernel-firmware/linux-firmware/-/merge_requests/882
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 8d649b3a1cfa..91f1b4f57915 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -783,7 +783,7 @@ &remoteproc_adsp {
};
&remoteproc_cdsp {
- firmware-name = "qcom/qcs6490/cdsp.mbn";
+ firmware-name = "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn";
status = "okay";
};
--
2.53.0
^ permalink raw reply related
* [PATCH 01/12] firmware: qcom: scm: Allow QSEECOM for Radxa Dragon Q6A
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
add "radxa,dragon-q6a" as compatible device for QSEECOM
This is required to get access to efivars and uefi boot loader support.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
drivers/firmware/qcom/qcom_scm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index 9b06a69d3a6d..55b18463560a 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -2319,6 +2319,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = {
{ .compatible = "qcom,x1e80100-crd" },
{ .compatible = "qcom,x1e80100-qcp" },
{ .compatible = "qcom,x1p42100-crd" },
+ { .compatible = "radxa,dragon-q6a" },
{ }
};
--
2.53.0
^ permalink raw reply related
* [PATCH 02/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller
From: Xilin Wu @ 2026-04-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
Add and enable UFS related nodes for this board.
Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design
limitations. UFS on this board is stable when working at Gear-4 Rate-A.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index bb5a42b038f1..c961d3ec625f 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -959,6 +959,29 @@ &uart5 {
status = "okay";
};
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l7b_2p96>;
+ vcc-max-microamp = <800000>;
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <900000>;
+ vccq2-supply = <&vreg_l9b_1p2>;
+ vccq2-max-microamp = <1300000>;
+
+ /* Gear-4 Rate-B is unstable due to board */
+ /* and UFS module design limitations */
+ limit-gear-rate = "rate-a";
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
&usb_2 {
dr_mode = "host";
--
2.53.0
^ permalink raw reply related
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