* Re: [PATCH RFC v2 0/6] Add support for Adreno 810 GPU
From: Akhil P Oommen @ 2026-04-07 19:26 UTC (permalink / raw)
To: Alexander Koskovich
Cc: Luca Weiss, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Konrad Dybcio, Rob Clark, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Sean Paul, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Konrad Dybcio, Bjorn Andersson
In-Reply-To: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me>
On 4/3/2026 4:38 AM, Alexander Koskovich wrote:
> Adreno 810 is present in the Milos SoC and is the first GPU to be released in
> the A8x family.
>
> Note that the OPP table is limited to 1050MHz to start with as the only Milos
> device I have is limited to that speed in GPU_CC_FREQ_LIMIT_VAL.
>
> This series is marked as RFC because it depends on a couple other in review
> series, batch 2 for A8x [1] and the GXCLKCTL block for Milos [2].
>
> There is also currently an issue on Milos with gx_clkctl_gx_gdsc being stuck on
> during runtime PM [3]. The proper fix is to only toggle the GX GDSC during GMU
> recovery, as the firmware manages it in all other cases. This is the same issue
> seen on SM8750 and is being worked on by Qualcomm. Right now I am just working
> around this locally by not collapsing the GX GDSC during runtime suspend.
This fix is posted here:
https://lore.kernel.org/lkml/20260407-gfx-clk-fixes-v1-0-4bb5583a5054@oss.qualcomm.com/
Please mark you series as dependent on this.
-Akhil
>
> [1]: https://lore.kernel.org/linux-arm-msm/20260327-a8xx-gpu-batch2-v2-0-2b53c38d2101@oss.qualcomm.com
> [2]: https://lore.kernel.org/linux-arm-msm/20260306-milos-gxclkctl-v1-0-00b09ee159a7@fairphone.com
> [3]: https://lore.kernel.org/linux-arm-msm/5409e13e-280c-47b6-a29f-351cb609bc6f@oss.qualcomm.com
>
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
> Changes in v2:
> - Mark as RFC due to dependency on in-review changes
> - Explain in DTS commit why qcom,kaanapali-gxclkctl.h and not qcom,milos-gxclkctl.h
> - cx_mmio -> cx_misc_mmio
> - Sync a810_nonctxt_regs with GRAPHICS.LA.14.0.r5-03100-lanai.0
> - Link to v1: https://lore.kernel.org/r/20260331-adreno-810-v1-0-725801dbb12b@pm.me
>
> ---
> Alexander Koskovich (6):
> dt-bindings: display/msm/gmu: Document Adreno 810 GMU
> drm/msm/adreno: rename llc_mmio to cx_misc_mmio
> drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC
> drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature
> drm/msm/adreno: add Adreno 810 GPU support
> arm64: dts: qcom: milos: Add Adreno 810 GPU and GMU nodes
>
> .../devicetree/bindings/display/msm/gmu.yaml | 32 +++
> arch/arm64/boot/dts/qcom/milos.dtsi | 148 +++++++++++
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 271 +++++++++++++++++++++
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 +-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 44 ++--
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 14 +-
> drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 11 +-
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +
> 8 files changed, 493 insertions(+), 40 deletions(-)
> ---
> base-commit: 128d2eccd20bd74fd104b412d949d869aa48f108
> change-id: 20260330-adreno-810-5a47525522cd
>
> Best regards,
^ permalink raw reply
* Re: [PATCH 08/11] dt-bindings: timer: renesas,rz-mtu3: document RZ/{T2H,N2H}
From: Rob Herring @ 2026-04-07 19:24 UTC (permalink / raw)
To: Cosmin Tanislav
Cc: Biju Das, Daniel Lezcano, Thomas Gleixner, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Michael Turquette,
Stephen Boyd, Lee Jones, Philipp Zabel, linux-iio,
linux-renesas-soc, linux-kernel, devicetree, linux-clk
In-Reply-To: <20260327192425.438263-9-cosmin-gabriel.tanislav.xa@renesas.com>
On Fri, Mar 27, 2026 at 09:24:22PM +0200, Cosmin Tanislav wrote:
> Compared to the previously supported SoCs, the Renesas RZ/T2H and RZ/N2H
> SoCs do not have a reset line.
>
> Add a new conditional only matching RZ/T2H and RZ/N2H which disables the
> resets property.
>
> Document RZ/T2H and RZ/N2H, and use the generic compatible as a
> fallback, as functionality is the same.
>
> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> ---
> .../devicetree/bindings/timer/renesas,rz-mtu3.yaml | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
> index 4623f6cddaf0..410951ca53f8 100644
> --- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
> +++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
> @@ -112,6 +112,8 @@ properties:
> - renesas,r9a07g043-mtu3 # RZ/{G2UL,Five}
> - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
> - renesas,r9a07g054-mtu3 # RZ/V2L
> + - renesas,r9a09g077-mtu3 # RZ/T2H
> + - renesas,r9a09g087-mtu3 # RZ/N2H
> - const: renesas,rz-mtu3
>
> reg:
> @@ -245,6 +247,17 @@ allOf:
> required:
> - resets
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,r9a09g077-mtu3
> + - renesas,r9a09g087-mtu3
This can just be an 'else' on the prior if/then schema. Really, these 2
patches can be combined as the motivation for the 1st patch is the 2nd
patch.
> + then:
> + properties:
> + resets: false
> +
> additionalProperties: false
>
> examples:
> --
> 2.53.0
>
^ permalink raw reply
* Re: [PATCH RFC 0/4] Devicetree support for Glymur GPU
From: Akhil P Oommen @ 2026-04-07 19:22 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann
Cc: linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
Rajendra Nayak, Rajendra Nayak
In-Reply-To: <20260405-glymur-gpu-dt-v1-0-2135eb11c562@oss.qualcomm.com>
On 4/5/2026 2:33 AM, Akhil P Oommen wrote:
> This series adds the necessary Device Tree bits to enable GPU support
> on the Glymur-based CRD devices. The Adreno X2-85 GPU present in Glymur
> chipsets is based on the new Adreno A8x family of GPUs. It features a new
> slice architecture with 4 slices, significantly higher bandwidth
> throughput compared to mobile counterparts, raytracing support, and the
> highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among other
> improvements.
>
> This series includes patches that add GPU SMMU, GPU/GMU support, and a
> patch to enable the GPU/GMU nodes on the CRD. Keen-eyed readers may
> notice that the secure firmware property is missing. This is
> intentional: The Glymur-based laptop platforms generally allow booting
> Linux at EL2 (yay!), which means the zap firmware not required here.
>
> The series is marked as RFC because an update is required in the
> gxclkctl/drm drivers to properly support the IFPC feature across all A8x
> GPUs. We plan to post a separate series shortly to address this. I prefer
> to merge the DT series after that series is acked, so that we retain the
> flexibility adjust the DT bindings if needed.
Taniya has posted it here:
https://lore.kernel.org/lkml/20260407-gfx-clk-fixes-v1-0-4bb5583a5054@oss.qualcomm.com/
-Akhil
>
> This series is only compile tested on linux-next. But I have cherry-picked
> and verified the functionality on a downstream tree which is pretty close
> to upstream. Also, there is a dtb-check error for the adreno smmu node. I
> will fix that in the next revision.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> Akhil P Oommen (3):
> dt-bindings: display/msm: gpu: Document Adreno X2-185
> arm64: dts: qcom: Add GPU support for Glymur
> arm64: dts: qcom: Enable GPU & GMU on Glymur CRD
>
> Rajendra Nayak (1):
> arm64: dts: qcom: glymur: Add GPU smmu node
>
> .../devicetree/bindings/display/msm/gpu.yaml | 1 +
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 8 +
> arch/arm64/boot/dts/qcom/glymur.dtsi | 234 +++++++++++++++++++++
> 3 files changed, 243 insertions(+)
> ---
> base-commit: 83acad05dee54a5cff0c98dd7962e55d4c6b145a
> change-id: 20260226-glymur-gpu-dt-339e5092606b
> prerequisite-message-id: <20260303-glymur_mmcc_dt_config_v2-v2-0-da9ded08c26f@oss.qualcomm.com>
> prerequisite-patch-id: a1fb5b7ee94995a24f6e96d1d2524e710d3a7e60
> prerequisite-patch-id: 56c830b7718129323b006e492aed9822d7c30079
>
> Best regards,
^ permalink raw reply
* Re: [PATCH 07/11] dt-bindings: timer: renesas,rz-mtu3: move required resets to conditional
From: Rob Herring (Arm) @ 2026-04-07 19:22 UTC (permalink / raw)
To: Cosmin Tanislav
Cc: Biju Das, linux-iio, Lee Jones, Magnus Damm, Daniel Lezcano,
Stephen Boyd, devicetree, Michael Turquette, Geert Uytterhoeven,
Philipp Zabel, linux-renesas-soc, Thomas Gleixner, linux-clk,
linux-kernel, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <20260327192425.438263-8-cosmin-gabriel.tanislav.xa@renesas.com>
On Fri, 27 Mar 2026 21:24:21 +0200, Cosmin Tanislav wrote:
> The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs do not have a
> reset line for the MTU3 block.
>
> Prepare for adding support for them by moving the required reset into a
> conditional matching all compatibles except the fallback one.
>
> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> ---
> .../devicetree/bindings/timer/renesas,rz-mtu3.yaml | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 06/11] dt-bindings: timer: renesas,rz-mtu3: remove TCIU8 interrupt
From: Rob Herring (Arm) @ 2026-04-07 19:21 UTC (permalink / raw)
To: Cosmin Tanislav
Cc: Stephen Boyd, Philipp Zabel, linux-iio, Krzysztof Kozlowski,
Biju Das, linux-clk, Conor Dooley, Magnus Damm, Thomas Gleixner,
linux-renesas-soc, linux-kernel, Geert Uytterhoeven, Lee Jones,
Michael Turquette, devicetree, Daniel Lezcano
In-Reply-To: <20260327192425.438263-7-cosmin-gabriel.tanislav.xa@renesas.com>
On Fri, 27 Mar 2026 21:24:20 +0200, Cosmin Tanislav wrote:
> Based on the following pages in the User Manuals, the MTU3 block does
> not have a TCIU8 interrupt, only a TCIV8 interrupt, as the row where
> TCIU8 should have been is marked as reserved, and the GIC SPI numbers
> stop at 212.
>
> * Page 486, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2UL
> Rev.1.40 User Manual
> * Page 363, Table 8.2 Interrupt Mapping (6/13) in the Renesas RZ/Five
> Rev.1.30 User Manual
> * Page 528, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2L
> and RZ/G2LC Rev.1.50 User Manual
> * Page 540, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/V2L
> Rev.1.50 User Manual
>
> Remove the TCIU8 interrupt.
>
> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> ---
> .../devicetree/bindings/timer/renesas,rz-mtu3.yaml | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH RFC 4/4] arm64: dts: qcom: Enable GPU & GMU on Glymur CRD
From: Akhil P Oommen @ 2026-04-07 19:21 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, linux-arm-msm, devicetree, linux-kernel,
dri-devel, freedreno
In-Reply-To: <ui4r3krzvd3i6kjdozhmmueejdqpbnbo5wfa6pwzjolcse3eeg@3u7bdphqv4iz>
On 4/5/2026 3:14 AM, Dmitry Baryshkov wrote:
> On Sun, Apr 05, 2026 at 02:33:17AM +0530, Akhil P Oommen wrote:
>> Enable the necessary DT nodes to add support for GPU on the Glymur CRD.
>> The Glymur CRD boots Linux at EL2, which means it doesn't require the
>> secure GPU firmware (zap fw).
>
> Is this going to be a default mode for other laptops too? Otherwise it
> might be better to keep ZAP node enabled by default and disable it here.
I believe so. Anyway the laptops are hitting the market right now. If
anyone reports that the EL2 is locked down, we can revisit this.
-Akhil.
>
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/glymur-crd.dts | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
>> index 51ea23a49b9e..a579df902323 100644
>> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
>> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
>> @@ -110,6 +110,14 @@ vreg_misc_3p3: regulator-misc-3p3 {
>> };
>> };
>>
>> +&gpu {
>> + status = "okay";
>> +};
>> +
>> +&gmu {
>> + status = "okay";
>> +};
>> +
>> &i2c0 {
>> clock-frequency = <400000>;
>>
>>
>> --
>> 2.51.0
>>
>
^ permalink raw reply
* Re: [PATCH v4 5/5] dt-bindings: usb: atmel,at91sam9rl-udc: convert to DT schema
From: Rob Herring (Arm) @ 2026-04-07 19:11 UTC (permalink / raw)
To: Charan Pedumuru
Cc: Greg Kroah-Hartman, Conor Dooley, Krzysztof Kozlowski,
linux-arm-kernel, Claudiu Beznea, Nicolas Ferre, Herve Codina,
devicetree, linux-kernel, linux-usb, Alexandre Belloni
In-Reply-To: <20260327-atmel-usb-v4-5-eb8b6e49b29d@gmail.com>
On Fri, 27 Mar 2026 16:47:46 +0000, Charan Pedumuru wrote:
> Convert Atmel High-Speed USB Device Controller (USBA) binding to DT schema.
> Changes during conversion:
> - Make the "clock-names" property flexible enough to accept the items
> in any order as the existing in tree DTS nodes doesn't follow an order.
>
> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> ---
> .../bindings/usb/atmel,at91sam9rl-udc.yaml | 74 ++++++++++++++++++++++
> .../devicetree/bindings/usb/atmel-usb.txt | 46 --------------
> 2 files changed, 74 insertions(+), 46 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v4 2/5] dt-bindings: usb: generic-ohci: add AT91RM9200 OHCI binding support
From: Rob Herring (Arm) @ 2026-04-07 19:08 UTC (permalink / raw)
To: Charan Pedumuru
Cc: linux-arm-kernel, Conor Dooley, linux-usb, Claudiu Beznea,
Herve Codina, Krzysztof Kozlowski, Greg Kroah-Hartman,
linux-kernel, Alexandre Belloni, Nicolas Ferre, devicetree
In-Reply-To: <20260327-atmel-usb-v4-2-eb8b6e49b29d@gmail.com>
On Fri, 27 Mar 2026 16:47:43 +0000, Charan Pedumuru wrote:
> Convert the Atmel AT91RM9200 OHCI USB host controller binding to DT schema
> by defining it in the existing generic OHCI schema.
>
> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> ---
> .../devicetree/bindings/usb/atmel-usb.txt | 27 --------------
> .../devicetree/bindings/usb/generic-ohci.yaml | 41 ++++++++++++++++++++++
> 2 files changed, 41 insertions(+), 27 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 3/9] dt-bindings: display: msm: document the Milos DPU
From: Rob Herring (Arm) @ 2026-04-07 19:07 UTC (permalink / raw)
To: Luca Weiss
Cc: Thomas Zimmermann, Sean Paul, Marijn Suijten, Alexander Koskovich,
Maarten Lankhorst, David Airlie, devicetree, Krzysztof Kozlowski,
Krishna Manikandan, Konrad Dybcio, ~postmarketos/upstreaming,
Rob Clark, linux-kernel, Neil Armstrong, Bjorn Andersson,
Abhinav Kumar, Dmitry Baryshkov, Conor Dooley, Jonathan Marek,
phone-devel, Jessica Zhang, freedreno, Simona Vetter, dri-devel,
Maxime Ripard, linux-arm-msm
In-Reply-To: <20260327-milos-mdss-v2-3-bc586683f5ca@fairphone.com>
On Fri, 27 Mar 2026 17:12:22 +0100, Luca Weiss wrote:
> Document the DPU Display Controller on the Milos Platform.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 2/9] dt-bindings: display: msm-dsi-controller-main: document the Milos DSI Controller
From: Rob Herring (Arm) @ 2026-04-07 19:06 UTC (permalink / raw)
To: Luca Weiss
Cc: Maxime Ripard, Thomas Zimmermann, Rob Clark, Jessica Zhang,
linux-arm-msm, devicetree, dri-devel, freedreno,
Maarten Lankhorst, phone-devel, Simona Vetter, David Airlie,
Neil Armstrong, ~postmarketos/upstreaming, Conor Dooley,
Marijn Suijten, Sean Paul, Konrad Dybcio, Bjorn Andersson,
Krzysztof Kozlowski, linux-kernel, Jonathan Marek,
Krishna Manikandan, Abhinav Kumar, Dmitry Baryshkov,
Alexander Koskovich
In-Reply-To: <20260327-milos-mdss-v2-2-bc586683f5ca@fairphone.com>
On Fri, 27 Mar 2026 17:12:21 +0100, Luca Weiss wrote:
> Document the DSI Controller on the Milos Platform.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 1/9] dt-bindings: display: msm-dsi-phy-7nm: document the Milos DSI PHY
From: Rob Herring (Arm) @ 2026-04-07 19:06 UTC (permalink / raw)
To: Luca Weiss
Cc: freedreno, Alexander Koskovich, Conor Dooley, Maxime Ripard,
Maarten Lankhorst, linux-kernel, Sean Paul, Abhinav Kumar,
David Airlie, Jessica Zhang, Thomas Zimmermann, Rob Clark,
phone-devel, Dmitry Baryshkov, Marijn Suijten, dri-devel,
~postmarketos/upstreaming, devicetree, Jonathan Marek,
Neil Armstrong, Krzysztof Kozlowski, Bjorn Andersson,
linux-arm-msm, Simona Vetter, Krishna Manikandan, Konrad Dybcio
In-Reply-To: <20260327-milos-mdss-v2-1-bc586683f5ca@fairphone.com>
On Fri, 27 Mar 2026 17:12:20 +0100, Luca Weiss wrote:
> Document the DSI PHY on the Milos Platform.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v4 5/6] clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
From: Brian Masney @ 2026-04-07 19:03 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-clk, Conor Dooley, Krzysztof Kozlowski, Michael Turquette,
Michael Walle, Rob Herring, Stephen Boyd, devicetree,
linux-kernel
In-Reply-To: <20260406215150.176599-5-marex@nabladev.com>
Hi Marek,
On Mon, Apr 06, 2026 at 11:49:45PM +0200, Marek Vasut wrote:
> Create helper function fsl_sai_clk_register() to set up and register
> SAI clock. Rename BCLK specific struct fsl_sai_clk members with bclk_
> prefix. Use of_node_full_name(dev->of_node) and clock name to register
> uniquely named clock. This is done in preparation for the follow up
> patch, which adds MCLK support.
>
> Signed-off-by: Marek Vasut <marex@nabladev.com>
> ---
> Cc: Brian Masney <bmasney@redhat.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Michael Walle <michael@walle.cc>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
> V4: New patch
> ---
> drivers/clk/clk-fsl-sai.c | 78 ++++++++++++++++++++++++++-------------
> 1 file changed, 53 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
> index 2a68e32c3167b..7ec9a4f22735c 100644
> --- a/drivers/clk/clk-fsl-sai.c
> +++ b/drivers/clk/clk-fsl-sai.c
> @@ -21,8 +21,9 @@
> #define CR2_DIV_WIDTH 8
>
> struct fsl_sai_clk {
> - struct clk_divider div;
> - struct clk_gate gate;
> + struct clk_divider bclk_div;
> + struct clk_gate bclk_gate;
> + struct clk_hw *bclk_hw;
> spinlock_t lock;
> };
>
> @@ -30,15 +31,57 @@ struct fsl_sai_data {
> unsigned int offset; /* Register offset */
> };
>
> +static int fsl_sai_clk_register(struct device *dev, void __iomem *base,
> + spinlock_t *lock, struct clk_divider *div,
> + struct clk_gate *gate, struct clk_hw **hw,
> + const int gate_bit, const int dir_bit,
> + const int div_reg, char *name)
> +{
> + const struct fsl_sai_data *data = device_get_match_data(dev);
> + struct clk_parent_data pdata = { .index = 0 };
> + struct clk_hw *chw;
> + char *cname;
> +
> + gate->reg = base + data->offset + I2S_CSR;
> + gate->bit_idx = gate_bit;
> + gate->lock = lock;
> +
> + div->reg = base + div_reg;
> + div->shift = CR2_DIV_SHIFT;
> + div->width = CR2_DIV_WIDTH;
> + div->lock = lock;
> +
> + cname = devm_kasprintf(dev, GFP_KERNEL, "%s.%s",
> + of_node_full_name(dev->of_node), name);
> + if (!cname)
> + return -ENOMEM;
> +
> + chw = devm_clk_hw_register_composite_pdata(dev, cname,
> + &pdata, 1, NULL, NULL,
> + &div->hw,
> + &clk_divider_ops,
> + &gate->hw,
> + &clk_gate_ops,
> + CLK_SET_RATE_GATE);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
s/hw/chw/ on the two lines above.
> +
> + *hw = chw;
> +
> + /* Set clock direction */
> + writel(dir_bit, base + div_reg);
The previous behavior of the code was to call writel() and then register
the clk. This flips it. Just to be sure no regressions are introduced,
should we keep the old behavior?
> +
> + return 0;
> +}
> +
> static int fsl_sai_clk_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> const struct fsl_sai_data *data = device_get_match_data(dev);
> struct fsl_sai_clk *sai_clk;
> - struct clk_parent_data pdata = { .index = 0 };
> struct clk *clk_bus;
> void __iomem *base;
> - struct clk_hw *hw;
> + int ret;
>
> sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
> if (!sai_clk)
> @@ -54,27 +97,12 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
>
> spin_lock_init(&sai_clk->lock);
>
> - sai_clk->gate.reg = base + data->offset + I2S_CSR;
> - sai_clk->gate.bit_idx = CSR_BCE_BIT;
> - sai_clk->gate.lock = &sai_clk->lock;
> -
> - sai_clk->div.reg = base + data->offset + I2S_CR2;
> - sai_clk->div.shift = CR2_DIV_SHIFT;
> - sai_clk->div.width = CR2_DIV_WIDTH;
> - sai_clk->div.lock = &sai_clk->lock;
> -
> - /* set clock direction, we are the BCLK master */
> - writel(CR2_BCD, base + data->offset + I2S_CR2);
> -
> - hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
> - &pdata, 1, NULL, NULL,
> - &sai_clk->div.hw,
> - &clk_divider_ops,
> - &sai_clk->gate.hw,
> - &clk_gate_ops,
> - CLK_SET_RATE_GATE);
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> + ret = fsl_sai_clk_register(dev, base, &sai_clk->lock,
> + &sai_clk->bclk_div, &sai_clk->bclk_gate,
> + &sai_clk->bclk_hw, CSR_BCE_BIT, CR2_BCD,
> + data->offset + I2S_CR2, "BCLK");
> + if (ret)
> + return ret;
>
> return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
^^^
hw is removed above, and it's still here in this patch. It's removed in
the last patch. This will break git bisect.
Brian
^ permalink raw reply
* Re: [PATCH] dt-bindings: phy: qcom,snps-eusb2: Document the Eliza Synopsys eUSB2 PHY
From: Rob Herring (Arm) @ 2026-04-07 18:51 UTC (permalink / raw)
To: Abel Vesa
Cc: linux-arm-msm, linux-phy, Vinod Koul, linux-kernel, devicetree,
Conor Dooley, Neil Armstrong, Abel Vesa, Krzysztof Kozlowski
In-Reply-To: <20260327-eliza-bindings-phy-eusb2-v1-1-1f8a9ad6a033@oss.qualcomm.com>
On Fri, 27 Mar 2026 16:14:27 +0200, Abel Vesa wrote:
> The Synopsys eUSB2 PHY found on the Eliza SoC is fully compatible with the
> one found the SM8550.
>
> So document it by adding the compatible to the list that has the SM8550
> one as fallback.
>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH] dt-bindings: soc: qcom: qcom,pmic-glink: Document Eliza compatible
From: Rob Herring (Arm) @ 2026-04-07 18:50 UTC (permalink / raw)
To: Abel Vesa
Cc: Bjorn Andersson, linux-arm-msm, Conor Dooley, Krzysztof Kozlowski,
devicetree, linux-kernel, Konrad Dybcio
In-Reply-To: <20260327-eliza-bindings-pmic-glink-v1-1-f9a65495f599@oss.qualcomm.com>
On Fri, 27 Mar 2026 15:44:13 +0200, Abel Vesa wrote:
> Document the compatible for the PMIC GLINK interface found on the
> Qualcomm Eliza SoC.
>
> It is fully compatible with the one found on SM8550, so use that as
> fallback.
>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH] dt-bindings: soc: qcom,aoss-qmp: Document the Eliza Always-On Subsystem side channel
From: Rob Herring (Arm) @ 2026-04-07 18:50 UTC (permalink / raw)
To: Abel Vesa
Cc: Bjorn Andersson, Konrad Dybcio, devicetree, Conor Dooley,
linux-kernel, linux-arm-msm, Krzysztof Kozlowski
In-Reply-To: <20260327-eliza-bindings-aoss-v1-1-70df76adc69b@oss.qualcomm.com>
On Fri, 27 Mar 2026 14:46:53 +0200, Abel Vesa wrote:
> Document the Always-On Subsystem (AOSS) side channel found on the Qualcomm
> Eliza SoC. It is used for communication with other clients, like
> remoteprocs.
>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v6 2/3] dt-bindings: fpga: Add Efinix SPI programming bindings
From: Rob Herring (Arm) @ 2026-04-07 18:49 UTC (permalink / raw)
To: iansdannapel
Cc: linux-fpga, devicetree, conor+dt, prabhakar.mahadev-lad.rj, heiko,
krzk+dt, marex, dev, linux-kernel, neil.armstrong, yilun.xu, mdf,
trix
In-Reply-To: <20260327114842.1300284-3-iansdannapel@gmail.com>
On Fri, 27 Mar 2026 12:48:40 +0100, iansdannapel@gmail.com wrote:
> From: Ian Dannapel <iansdannapel@gmail.com>
>
> Add device tree bindings documentation for configuring Efinix FPGA
> using serial SPI passive programming mode.
>
> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> ---
> .../bindings/fpga/efinix,trion-config.yaml | 96 +++++++++++++++++++
> 1 file changed, 96 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v4 4/6] clk: fsl-sai: Sort the headers
From: Brian Masney @ 2026-04-07 18:48 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-clk, Conor Dooley, Krzysztof Kozlowski, Michael Turquette,
Michael Walle, Rob Herring, Stephen Boyd, devicetree,
linux-kernel
In-Reply-To: <20260406215150.176599-4-marex@nabladev.com>
On Mon, Apr 06, 2026 at 11:49:44PM +0200, Marek Vasut wrote:
> Sort the headers. No functional change.
>
> Signed-off-by: Marek Vasut <marex@nabladev.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: crypto: qcom-qce: Add Qualcomm Eliza QCE
From: Kuldeep Singh @ 2026-04-07 18:47 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thara Gopinath, Herbert Xu, David S. Miller,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, linux-crypto, devicetree, linux-kernel
In-Reply-To: <20260407-crypto-qcom-eliza-v1-1-40f61a1454a2@oss.qualcomm.com>
On 4/7/2026 7:21 PM, Krzysztof Kozlowski wrote:
> Document the QCE crypto engine on Qualcomm Eliza SoC, fully compatible
> with earlier generations.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
--
Regards
Kuldeep
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: arm: marvell: Convert armada-380-mpcore-soc-ctrl to DT Schema
From: Rob Herring @ 2026-04-07 18:44 UTC (permalink / raw)
To: Padmashree S S
Cc: andrew, gregory.clement, sebastian.hesselbarth, krzk+dt, conor+dt,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260327114653.593582-1-padmashreess2006@gmail.com>
On Fri, Mar 27, 2026 at 05:16:53PM +0530, Padmashree S S wrote:
> Convert armada-380-mpcore-soc-ctrl to DT schema
>
> Signed-off-by: Padmashree S S <padmashreess2006@gmail.com>
> ---
> .../marvell/armada-380-mpcore-soc-ctrl.txt | 14 --------
> .../marvell/armada-380-mpcore-soc-ctrl.yaml | 32 +++++++++++++++++++
> 2 files changed, 32 insertions(+), 14 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.yaml
Please move this to
bindings/soc/marvell/marvell,armada-380-mpcore-soc-ctrl.yaml
Don't forget to update the '$id' value.
Rob
^ permalink raw reply
* Re: [PATCH v2 2/3] dt-bindings: pinctrl: sun55i-a523: increase IRQ banks number
From: Rob Herring (Arm) @ 2026-04-07 18:40 UTC (permalink / raw)
To: Andre Przywara
Cc: Jernej Skrabec, Samuel Holland, linux-gpio, linux-sunxi,
devicetree, linux-arm-kernel, Krzysztof Kozlowski, linux-kernel,
Conor Dooley, Chen-Yu Tsai
In-Reply-To: <20260327113006.3135663-3-andre.przywara@arm.com>
On Fri, 27 Mar 2026 11:30:05 +0000, Andre Przywara wrote:
> The Allwinner A523 SoC implements 10 GPIO banks in the first pinctrl
> instance, but it skips the first bank (PortA), so their index goes from
> 1 to 10. The same is actually true for the IRQ banks: there are registers
> for 11 banks, though the first bank is not implemented (RAZ/WI).
> In contrast to previous SoCs, the count of the IRQ banks starts with this
> first unimplemented bank, so we need to provide an interrupt for it.
> And indeed the A523 user manual lists an interrupt number for PortA, so we
> need to increase the maximum number of interrupts per pin controller to 11,
> to be able to assign the correct interrupt number for each bank.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v3] ASoC: dt-bindings: hisilicon: Convert hi6210 I2S to dt-schema
From: Rob Herring @ 2026-04-07 18:38 UTC (permalink / raw)
To: Chaitanya Sabnis
Cc: lgirdwood, broonie, krzk+dt, conor+dt, john.stultz, linux-sound,
devicetree, linux-kernel
In-Reply-To: <20260327092106.4233-1-chaitanya.msabnis@gmail.com>
On Fri, Mar 27, 2026 at 02:51:06PM +0530, Chaitanya Sabnis wrote:
> Convert the Hisilicon hi6210 I2S controller hardware binding from
> legacy plain text to modern YAML dt-schema format.
>
> During the conversion, the order of the dma-names properties in the
> example was corrected to "tx", "rx" to match the official property
> description, resolving a contradiction in the original text binding.
>
> Signed-off-by: Chaitanya Sabnis <chaitanya.msabnis@gmail.com>
> ---
> .../bindings/sound/hisilicon,hi6210-i2s.txt | 42 ----------
> .../bindings/sound/hisilicon,hi6210-i2s.yaml | 80 +++++++++++++++++++
> 2 files changed, 80 insertions(+), 42 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.txt
> create mode 100644 Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.yaml
>
> diff --git a/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.txt b/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.txt
> deleted file mode 100644
> index 7a296784eb37..000000000000
> --- a/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.txt
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -* Hisilicon 6210 i2s controller
> -
> -Required properties:
> -
> -- compatible: should be one of the following:
> - - "hisilicon,hi6210-i2s"
> -- reg: physical base address of the i2s controller unit and length of
> - memory mapped region.
> -- interrupts: should contain the i2s interrupt.
> -- clocks: a list of phandle + clock-specifier pairs, one for each entry
> - in clock-names.
> -- clock-names: should contain following:
> - - "dacodec"
> - - "i2s-base"
> -- dmas: DMA specifiers for tx dma. See the DMA client binding,
> - Documentation/devicetree/bindings/dma/dma.txt
> -- dma-names: should be "tx" and "rx"
> -- hisilicon,sysctrl-syscon: phandle to sysctrl syscon
> -- #sound-dai-cells: Should be set to 1 (for multi-dai)
> - - The dai cell indexes reference the following interfaces:
> - 0: S2 interface
> - (Currently that is the only one available, but more may be
> - supported in the future)
> -
> -Example for the hi6210 i2s controller:
> -
> -i2s0: i2s@f7118000{
> - compatible = "hisilicon,hi6210-i2s";
> - reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
> - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
> - clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
> - <&sys_ctrl HI6220_BBPPLL0_DIV>;
> - clock-names = "dacodec", "i2s-base";
> - dmas = <&dma0 15 &dma0 14>;
> - dma-names = "rx", "tx";
> - hisilicon,sysctrl-syscon = <&sys_ctrl>;
> - #sound-dai-cells = <1>;
> -};
> -
> -Then when referencing the i2s controller:
> - sound-dai = <&i2s0 0>; /* index 0 => S2 interface */
> -
> diff --git a/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.yaml b/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.yaml
> new file mode 100644
> index 000000000000..5171f984630b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/hisilicon,hi6210-i2s.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: HiSilicon hi6210 I2S controller
> +
> +maintainers:
> + - John Stultz <john.stultz@linaro.org>
That email hasn't worked for years. I would suggest putting the
HiSilicon maintainer down for anything HiSilicon related.
With that,
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: qcom: eliza: Add QCE crypto
From: Harshal Dev @ 2026-04-07 18:35 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thara Gopinath, Herbert Xu, David S. Miller,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, linux-crypto, devicetree, linux-kernel
In-Reply-To: <20260407-crypto-qcom-eliza-v1-2-40f61a1454a2@oss.qualcomm.com>
On 4/7/2026 7:21 PM, Krzysztof Kozlowski wrote:
> Add nodes for the BAM DAM and QCE crypto engine.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/eliza.dtsi | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Regards,
Harshal
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: crypto: qcom-qce: Add Qualcomm Eliza QCE
From: Harshal Dev @ 2026-04-07 18:34 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thara Gopinath, Herbert Xu, David S. Miller,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, linux-crypto, devicetree, linux-kernel
In-Reply-To: <20260407-crypto-qcom-eliza-v1-1-40f61a1454a2@oss.qualcomm.com>
On 4/7/2026 7:21 PM, Krzysztof Kozlowski wrote:
> Document the QCE crypto engine on Qualcomm Eliza SoC, fully compatible
> with earlier generations.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Regards,
Harshal
^ permalink raw reply
* Re: [PATCH v4 01/27] media: dt-bindings: media: rockchip-rga: add rockchip,rk3588-rga3
From: Rob Herring (Arm) @ 2026-04-07 18:10 UTC (permalink / raw)
To: Sven Püschel
Cc: Jacob Chen, devicetree, sebastian.reichel, Ezequiel Garcia,
Krzysztof Kozlowski, Mauro Carvalho Chehab, Heiko Stuebner,
linux-rockchip, linux-kernel, Conor Dooley, linux-arm-kernel,
kernel, nicolas, linux-media
In-Reply-To: <20260325-spu-rga3-v4-1-e90ec1c61354@pengutronix.de>
On Wed, 25 Mar 2026 15:50:32 +0100, Sven Püschel wrote:
> Add a new compatible for the RGA3 (Raster Graphic Acceleration 3)
> peripheral found on the RK3588 SoC. Also specify an iommu property,
> as the RGA3 contains the generic rockchip iommu. While other versions
> also have an iommu, it's usually specific to them.
>
> The RK3588 contains one RGA2-Enhance core (also contained on the RK3399)
> and two RGA3 cores. Both feature a similar functionality of scaling,
> cropping and rotating of up to two input images into one output image.
> Key differences of the RGA3 are:
>
> - supports 10bit YUV output formats
> - supports 8x8 tiles and FBCD as inputs and outputs
> - supports BT2020 color space conversion
> - max output resolution of (8192-64)x(8192-64)
> - MMU can map up to 32G DDR RAM
> - fully planar formats (3 planes) are not supported
> - max scale up/down factor of 8 (RGA2 allows up to 16)
>
> Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
>
> ---
>
> Changed in v3/v4:
> - Dropped Acked-by: Krzysztof Kozlowski due to the added iommus property
> and description adjustments.
> ---
> Documentation/devicetree/bindings/media/rockchip-rga.yaml | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v6 17/27] of: property: Allow fw_devlink device-tree on x86
From: Rob Herring (Arm) @ 2026-04-07 18:09 UTC (permalink / raw)
To: Herve Codina
Cc: Arnd Bergmann, linux-acpi, Daniel Scally, Charles Keepax,
Richard Fitzgerald, Andy Shevchenko, Jonathan Cameron,
Fabio Estevam, Dave Jiang, Thomas Petazzoni, Andi Shyti,
Ulf Hansson, Saravana Kannan, Ira Weiny, Dan Williams,
Steen Hegelund, Linus Walleij, imx, linux-gpio, patches,
Sakari Ailus, Andrew Lunn, devicetree, Geert Uytterhoeven,
linux-arm-kernel, Rafael J. Wysocki, Stephen Boyd,
Greg Kroah-Hartman, David Rhodes, Bjorn Helgaas, Conor Dooley,
linux-kernel, Luca Ceresoli, Shawn Guo, Vishal Verma, Mark Brown,
Davidlohr Bueso, linux-pm, Allan Nielsen, Pengutronix Kernel Team,
Wolfram Sang, Len Brown, Sascha Hauer, Danilo Krummrich,
Michael Turquette, Frank Li, Krzysztof Kozlowski, driver-core,
linux-i2c, linux-sound, Horatiu Vultur, Heikki Krogerus,
Kalle Niemi, linux-cxl, Alison Schofield, linux-clk, linux-pci,
Matti Vaittinen, Wolfram Sang, linux-spi, Peter Rosin
In-Reply-To: <20260325143555.451852-18-herve.codina@bootlin.com>
On Wed, 25 Mar 2026 15:35:44 +0100, Herve Codina wrote:
> PCI drivers can use a device-tree overlay to describe the hardware
> available on the PCI board. This is the case, for instance, of the
> LAN966x PCI device driver.
>
> Adding some more nodes in the device-tree overlay adds some more
> consumer/supplier relationship between devices instantiated from this
> overlay.
>
> Those fw_node consumer/supplier relationships are handled by fw_devlink
> and are created based on the device-tree parsing done by the
> of_fwnode_add_links() function.
>
> Those consumer/supplier links are needed in order to ensure a correct PM
> runtime management and a correct removal order between devices.
>
> For instance, without those links a supplier can be removed before its
> consumers is removed leading to all kind of issue if this consumer still
> want the use the already removed supplier.
>
> The support for the usage of an overlay from a PCI driver has been added
> on x86 systems in commit 1f340724419ed ("PCI: of: Create device tree PCI
> host bridge node").
>
> In the past, support for fw_devlink on x86 had been tried but this
> support has been removed in commit 4a48b66b3f52 ("of: property: Disable
> fw_devlink DT support for X86"). Indeed, this support was breaking some
> x86 systems such as OLPC system and the regression was reported in [0].
>
> Instead of disabling this support for all x86 system, use a finer grain
> and disable this support only for the possible problematic subset of x86
> systems (at least OLPC and CE4100).
>
> Those systems use a device-tree to describe their hardware. Identify
> those systems using key properties in the device-tree.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> Link: https://lore.kernel.org/lkml/3c1f2473-92ad-bfc4-258e-a5a08ad73dd0@web.de/ [0]
> ---
> drivers/of/property.c | 26 +++++++++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
Applied, thanks!
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox