* Re: [PATCH] arm64: dts: qcom: Use GIC_SPI macro for interrupt-map
From: Konrad Dybcio @ 2026-04-08 10:21 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <20260407201839.25759-2-krzysztof.kozlowski@oss.qualcomm.com>
On 4/7/26 10:18 PM, Krzysztof Kozlowski wrote:
> Make the complicated interrupt-map property (with multiple '0' entries)
> a bit more readable by using known define for GIC_SPI.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* [PATCH v2 1/2] dt-bindings: pwm: clk-pwm: add optional GPIO and pinctrl properties
From: Xilin Wu @ 2026-04-08 10:07 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nikita Travkin
Cc: linux-pwm, devicetree, linux-kernel, linux-arm-msm, Xilin Wu
In-Reply-To: <20260408-clk-pwm-gpio-v2-0-d22f1f3498a0@radxa.com>
The clk-pwm driver cannot produce constant output levels (0% or 100%
duty cycle, or disabled state) through the clock hardware alone - the
actual pin level when the clock is off is undefined and
hardware-dependent.
Document optional gpios, pinctrl-names, pinctrl-0, and pinctrl-1
properties that allow the driver to switch the pin between clock
function mux (for normal PWM output) and GPIO mode (to drive a
deterministic constant level).
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
Documentation/devicetree/bindings/pwm/clk-pwm.yaml | 36 +++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml
index ec1768291503..2a0e3e02d27b 100644
--- a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml
@@ -15,6 +15,11 @@ description: |
It's often possible to control duty-cycle of such clocks which makes them
suitable for generating PWM signal.
+ Optionally, a GPIO and pinctrl states can be provided. When a constant
+ output level is needed (0%, 100%, or disabled), the pin is switched to
+ GPIO mode to drive the level directly. For normal PWM output the pin is
+ switched back to its clock function mux.
+
allOf:
- $ref: pwm.yaml#
@@ -29,6 +34,26 @@ properties:
"#pwm-cells":
const: 2
+ gpios:
+ description:
+ Optional GPIO used to drive a constant level when the PWM output is
+ disabled or set to 0% / 100% duty cycle. When provided, pinctrl states
+ "default" (clock mux) and "gpio" must also be defined.
+ maxItems: 1
+
+ pinctrl-names: true
+
+ pinctrl-0:
+ description: Pin configuration for clock function mux (normal PWM).
+ maxItems: 1
+
+ pinctrl-1:
+ description: Pin configuration for GPIO mode (constant level output).
+ maxItems: 1
+
+dependencies:
+ gpios: [ pinctrl-0, pinctrl-1 ]
+
unevaluatedProperties: false
required:
@@ -41,6 +66,15 @@ examples:
compatible = "clk-pwm";
#pwm-cells = <2>;
clocks = <&gcc 0>;
- pinctrl-names = "default";
+ };
+
+ - |
+ pwm {
+ compatible = "clk-pwm";
+ #pwm-cells = <2>;
+ clocks = <&gcc 0>;
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pwm_clk_flash_default>;
+ pinctrl-1 = <&pwm_clk_flash_gpio>;
+ gpios = <&tlmm 32 0>;
};
--
2.53.0
^ permalink raw reply related
* [PATCH v2 2/2] pwm: clk-pwm: add GPIO and pinctrl support for constant output levels
From: Xilin Wu @ 2026-04-08 10:07 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nikita Travkin
Cc: linux-pwm, devicetree, linux-kernel, linux-arm-msm, Xilin Wu
In-Reply-To: <20260408-clk-pwm-gpio-v2-0-d22f1f3498a0@radxa.com>
The clk-pwm driver cannot guarantee a defined output level when the
PWM is disabled or when 0%/100% duty cycle is requested, because the
pin state when the clock is stopped is hardware-dependent.
Add optional GPIO and pinctrl support: when a GPIO descriptor and
pinctrl states ("default" for clock mux, "gpio" for GPIO mode) are
provided in the device tree, the driver switches the pin to GPIO mode
and drives the appropriate level for disabled/0%/100% states. For
normal PWM output, the pin is switched back to its clock function mux.
If no GPIO is provided, the driver falls back to the original
clock-only behavior.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
drivers/pwm/pwm-clk.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 80 insertions(+), 4 deletions(-)
diff --git a/drivers/pwm/pwm-clk.c b/drivers/pwm/pwm-clk.c
index f8f5af57acba..d7d8d2c2dd0f 100644
--- a/drivers/pwm/pwm-clk.c
+++ b/drivers/pwm/pwm-clk.c
@@ -11,11 +11,20 @@
* - Due to the fact that exact behavior depends on the underlying
* clock driver, various limitations are possible.
* - Underlying clock may not be able to give 0% or 100% duty cycle
- * (constant off or on), exact behavior will depend on the clock.
+ * (constant off or on), exact behavior will depend on the clock,
+ * unless a gpio pinctrl state is supplied.
* - When the PWM is disabled, the clock will be disabled as well,
- * line state will depend on the clock.
+ * line state will depend on the clock, unless a gpio pinctrl
+ * state is supplied.
* - The clk API doesn't expose the necessary calls to implement
* .get_state().
+ *
+ * Optionally, a GPIO descriptor and pinctrl states ("default" and
+ * "gpio") can be provided. When a constant output level is needed
+ * (0% duty, 100% duty, or disabled), the driver switches the pin to
+ * GPIO mode and drives the appropriate level. For normal PWM output
+ * the pin is switched back to its clock function mux. If no GPIO is
+ * provided, the driver falls back to the original clock-only behavior.
*/
#include <linux/kernel.h>
@@ -25,11 +34,17 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
+#include <linux/gpio/consumer.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/pwm.h>
struct pwm_clk_chip {
struct clk *clk;
bool clk_enabled;
+ struct pinctrl *pinctrl;
+ struct pinctrl_state *pins_default; /* clock function mux */
+ struct pinctrl_state *pins_gpio; /* GPIO mode */
+ struct gpio_desc *gpiod;
};
static inline struct pwm_clk_chip *to_pwm_clk_chip(struct pwm_chip *chip)
@@ -45,14 +60,36 @@ static int pwm_clk_apply(struct pwm_chip *chip, struct pwm_device *pwm,
u32 rate;
u64 period = state->period;
u64 duty_cycle = state->duty_cycle;
+ bool constant_level = false;
+ int gpio_value = 0;
if (!state->enabled) {
- if (pwm->state.enabled) {
+ constant_level = true;
+ gpio_value = 0;
+ } else if (state->duty_cycle == 0) {
+ constant_level = true;
+ gpio_value = (state->polarity == PWM_POLARITY_INVERSED) ? 1 : 0;
+ } else if (state->duty_cycle >= state->period) {
+ constant_level = true;
+ gpio_value = (state->polarity == PWM_POLARITY_INVERSED) ? 0 : 1;
+ }
+
+ if (constant_level) {
+ if (pcchip->gpiod) {
+ gpiod_direction_output(pcchip->gpiod, gpio_value);
+ pinctrl_select_state(pcchip->pinctrl, pcchip->pins_gpio);
+ }
+ if (pcchip->clk_enabled) {
clk_disable(pcchip->clk);
pcchip->clk_enabled = false;
}
return 0;
- } else if (!pwm->state.enabled) {
+ }
+
+ if (pcchip->gpiod)
+ pinctrl_select_state(pcchip->pinctrl, pcchip->pins_default);
+
+ if (!pcchip->clk_enabled) {
ret = clk_enable(pcchip->clk);
if (ret)
return ret;
@@ -97,6 +134,45 @@ static int pwm_clk_probe(struct platform_device *pdev)
return dev_err_probe(&pdev->dev, PTR_ERR(pcchip->clk),
"Failed to get clock\n");
+ pcchip->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (IS_ERR(pcchip->pinctrl)) {
+ ret = PTR_ERR(pcchip->pinctrl);
+ pcchip->pinctrl = NULL;
+ if (ret == -EPROBE_DEFER)
+ return ret;
+ } else {
+ pcchip->pins_default = pinctrl_lookup_state(pcchip->pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ pcchip->pins_gpio = pinctrl_lookup_state(pcchip->pinctrl,
+ "gpio");
+ if (IS_ERR(pcchip->pins_default) || IS_ERR(pcchip->pins_gpio))
+ pcchip->pinctrl = NULL;
+ }
+
+ /*
+ * Switch to GPIO pinctrl state before requesting the GPIO.
+ * The driver core has already applied the "default" state, which
+ * muxes the pin to the clock function and claims it. We must
+ * release that claim first so that gpiolib can request the pin.
+ */
+ if (pcchip->pinctrl)
+ pinctrl_select_state(pcchip->pinctrl, pcchip->pins_gpio);
+
+ pcchip->gpiod = devm_gpiod_get_optional(&pdev->dev, NULL, GPIOD_ASIS);
+ if (IS_ERR(pcchip->gpiod))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pcchip->gpiod),
+ "Failed to get gpio\n");
+
+ /*
+ * If pinctrl states were found but no GPIO was provided, the pin is
+ * stuck in GPIO mode from the switch above. Restore the default
+ * (clock-function) mux and fall back to clock-only operation.
+ */
+ if (pcchip->pinctrl && !pcchip->gpiod) {
+ pinctrl_select_state(pcchip->pinctrl, pcchip->pins_default);
+ pcchip->pinctrl = NULL;
+ }
+
chip->ops = &pwm_clk_ops;
ret = pwmchip_add(chip);
--
2.53.0
^ permalink raw reply related
* [PATCH v2 0/2] pwm: clk-pwm: Add GPIO support for constant output levels
From: Xilin Wu @ 2026-04-08 10:07 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nikita Travkin
Cc: linux-pwm, devicetree, linux-kernel, linux-arm-msm, Xilin Wu
The clk-pwm driver uses a clock with duty cycle control to generate
PWM output. However, when the PWM is disabled or a 0%/100% duty cycle
is requested, the clock must be stopped, and the resulting pin level
is undefined and hardware-dependent.
This series adds optional GPIO and pinctrl support to the clk-pwm
driver. When a GPIO and pinctrl states ("default" for clock mux,
"gpio" for GPIO mode) are provided in the device tree, the driver
switches the pin to GPIO mode and drives a deterministic output level
for disabled/0%/100% states. For normal PWM output the pin is switched
back to its clock function mux. If no GPIO is provided, the driver
falls back to the original clock-only behavior.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
Changes in v2:
- Restore the original limitation comments
- Swap the order of pinctrl_select_state and gpiod_direction_output
- Handle a situation where pinctrl states were found but no GPIO was provided
- Link to v1: https://patch.msgid.link/20260406-clk-pwm-gpio-v1-0-40d2f3a20aff@radxa.com
---
Xilin Wu (2):
dt-bindings: pwm: clk-pwm: add optional GPIO and pinctrl properties
pwm: clk-pwm: add GPIO and pinctrl support for constant output levels
Documentation/devicetree/bindings/pwm/clk-pwm.yaml | 36 +++++++++-
drivers/pwm/pwm-clk.c | 84 ++++++++++++++++++++--
2 files changed, 115 insertions(+), 5 deletions(-)
---
base-commit: 2febe6e6ee6e34c7754eff3c4d81aa7b0dcb7979
change-id: 20260406-clk-pwm-gpio-7f63b38908a5
Best regards,
--
Xilin Wu <sophon@radxa.com>
^ permalink raw reply
* Re: [PATCH v12 2/2] arm: dts: aspeed: ventura: add Meta Ventura BMC
From: P.K. Lee @ 2026-04-08 10:06 UTC (permalink / raw)
To: Andrew Lunn
Cc: robh+dt, krzysztof.kozlowski+dt, conor+dt, joel, andrew,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
Jason-Hsu, p.k.lee
In-Reply-To: <435616b8-8d4c-4814-8f21-d667755473f1@lunn.ch>
> > > > +&mac3 {
> > > > + status = "okay";
> > > > + phy-mode = "rmii";
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&pinctrl_rmii4_default>;
> > > > + fixed-link {
> > > > + speed = <100>;
> > > > + full-duplex;
> > > > + };
> > >
> > > What is on the other end of this fixed link?
> >
> > The other end of this fixed link is the CPU port of a Marvell 88E6393X
> > switch. We are using this switch in unmanaged mode rather than using
> > the DSA subsystem. Therefore, we use a fixed-link to force the mac3 to
> > 100Mbps full-duplex RMII to match the CPU port configuration.
>
> You are mixing up terms. The 88E6393X does not have a dedicated port
> for connecting to the host CPU. Any port can be connected to the host,
> using DSA tags. And all the ports are 1G or faster, so it seems odd to
> limit it to 100Mbps. There is something consider a CPU port, but that
> connects the internal Z80 CPU to the switch fabric.
>
I apologize for the confusing terminology. I meant the port 0 of the
88E6393X is connected to the AST2600 mac3. Regarding the 100Mbps RMII
limitation, this is a strict hardware design constraint on our
specific board.
> > > > +};
> > > > +
> > > > +&mdio0 {
> > > > + status = "okay";
> > > > +};
> > >
> > > If there are no devices on the bus, why enable it?
> >
> > We intentionally enable it so user-space tools can access the switch
> > registers. I have added a comment in v13 to clarify this.
>
> Why would user space want to access the switch registers for an
> unmanaged switch? It sounds like you are using Marvells SDK in
> userspace to manage the switch, rather than using DSA.
>
We do have a custom user-space daemon that configures the switch
registers for our specific use case. Should I remove the &mdio0 node
if it is only enabled and has no other configuration in the upstream
device tree?
P.K. Lee
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: qcom: milos: Add QCrypto nodes
From: Konrad Dybcio @ 2026-04-08 10:05 UTC (permalink / raw)
To: Alexander Koskovich, Thara Gopinath, Herbert Xu, David S. Miller,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: linux-crypto, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260405-milos-qce-v1-2-6996fb0b8a9c@pm.me>
On 4/6/26 4:10 AM, Alexander Koskovich wrote:
> Add the QCE and Crypto BAM DMA nodes.
>
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* [PATCH v13 3/3] of: Respect #{iommu,msi}-cells in maps
From: Vijayanand Jitta @ 2026-04-08 10:03 UTC (permalink / raw)
To: Nipun Gupta, Nikhil Agarwal, Joerg Roedel, Will Deacon,
Robin Murphy, Marc Zyngier, Lorenzo Pieralisi, Thomas Gleixner,
Saravana Kannan, Richard Zhu, Lucas Stach,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Juergen Gross, Stefano Stabellini, Oleksandr Tyshchenko,
Dmitry Baryshkov, Konrad Dybcio, Bjorn Andersson, Rob Herring,
Conor Dooley, Krzysztof Kozlowski, Prakash Gupta, Vikash Garodia
Cc: linux-kernel, iommu, linux-arm-kernel, devicetree, linux-pci, imx,
xen-devel, linux-arm-msm, Vijayanand Jitta, Charan Teja Kalla
In-Reply-To: <20260408-parse_iommu_cells-v13-0-fa921e92661b@oss.qualcomm.com>
From: Robin Murphy <robin.murphy@arm.com>
So far our parsing of {iommu,msi}-map properties has always blindly
assumed that the output specifiers will always have exactly 1 cell.
This typically does happen to be the case, but is not actually enforced
(and the PCI msi-map binding even explicitly states support for 0 or 1
cells) - as a result we've now ended up with dodgy DTs out in the field
which depend on this behaviour to map a 1-cell specifier for a 2-cell
provider, despite that being bogus per the bindings themselves.
Since there is some potential use in being able to map at least single
input IDs to multi-cell output specifiers (and properly support 0-cell
outputs as well), add support for properly parsing and using the target
nodes' #cells values, albeit with the unfortunate complication of still
having to work around expectations of the old behaviour too.
Since there are multi-cell output specifiers, the callers of of_map_id()
may need to get the exact cell output value for further processing.
Update of_map_id() to set args_count in the output to reflect the actual
number of output specifier cells.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Charan Teja Kalla <charan.kalla@oss.qualcomm.com>
Signed-off-by: Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com>
---
drivers/of/base.c | 157 +++++++++++++++++++++++++++++++++++++++++------------
include/linux/of.h | 6 +-
2 files changed, 125 insertions(+), 38 deletions(-)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index b3d002015192..2554e4f1a181 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -2096,18 +2096,48 @@ int of_find_last_cache_level(unsigned int cpu)
return cache_level;
}
+/*
+ * Some DTs have an iommu-map targeting a 2-cell IOMMU node while
+ * specifying only 1 cell. Fortunately they all consist of value '1'
+ * as the 2nd cell entry with the same target, so check for that pattern.
+ *
+ * Example:
+ * IOMMU node:
+ * #iommu-cells = <2>;
+ *
+ * Device node:
+ * iommu-map = <0x0000 &smmu 0x0000 0x1>,
+ * <0x0100 &smmu 0x0100 0x1>;
+ */
+static bool of_check_bad_map(const __be32 *map, int len)
+{
+ __be32 phandle = map[1];
+
+ if (len % 4)
+ return false;
+ for (int i = 0; i < len; i += 4) {
+ if (map[i + 1] != phandle || map[i + 3] != cpu_to_be32(1))
+ return false;
+ }
+ return true;
+}
+
/**
* of_map_id - Translate an ID through a downstream mapping.
* @np: root complex device node.
* @id: device ID to map.
* @map_name: property name of the map to use.
+ * @cells_name: property name of target specifier cells.
* @map_mask_name: optional property name of the mask to use.
* @filter_np: optional device node to filter matches by, or NULL to match any.
* If non-NULL, only map entries targeting this node will be matched.
* @arg: pointer to a &struct of_phandle_args for the result. On success,
- * @arg->args[0] will contain the translated ID. If a map entry was
- * matched, @arg->np will be set to the target node with a reference
- * held that the caller must release with of_node_put().
+ * @arg->args_count will be set to the number of output specifier cells
+ * as defined by @cells_name in the target node, and
+ * @arg->args[0..args_count-1] will contain the translated output
+ * specifier values. If a map entry was matched, @arg->np will be set
+ * to the target node with a reference held that the caller must release
+ * with of_node_put().
*
* Given a device ID, look up the appropriate implementation-defined
* platform ID and/or the target device which receives transactions on that
@@ -2116,17 +2146,19 @@ int of_find_last_cache_level(unsigned int cpu)
* Return: 0 on success or a standard error code on failure.
*/
int of_map_id(const struct device_node *np, u32 id,
- const char *map_name, const char *map_mask_name,
+ const char *map_name, const char *cells_name,
+ const char *map_mask_name,
const struct device_node *filter_np, struct of_phandle_args *arg)
{
u32 map_mask, masked_id;
- int map_len;
+ int map_bytes, map_len, offset = 0;
+ bool bad_map = false;
const __be32 *map = NULL;
if (!np || !map_name || !arg)
return -EINVAL;
- map = of_get_property(np, map_name, &map_len);
+ map = of_get_property(np, map_name, &map_bytes);
if (!map) {
if (filter_np)
return -ENODEV;
@@ -2136,11 +2168,9 @@ int of_map_id(const struct device_node *np, u32 id,
return 0;
}
- if (!map_len || map_len % (4 * sizeof(*map))) {
- pr_err("%pOF: Error: Bad %s length: %d\n", np,
- map_name, map_len);
- return -EINVAL;
- }
+ if (map_bytes % sizeof(*map))
+ goto err_map_len;
+ map_len = map_bytes / sizeof(*map);
/* The default is to select all bits. */
map_mask = 0xffffffff;
@@ -2153,39 +2183,84 @@ int of_map_id(const struct device_node *np, u32 id,
of_property_read_u32(np, map_mask_name, &map_mask);
masked_id = map_mask & id;
- for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) {
+
+ while (offset < map_len) {
struct device_node *phandle_node;
- u32 id_base = be32_to_cpup(map + 0);
- u32 phandle = be32_to_cpup(map + 1);
- u32 out_base = be32_to_cpup(map + 2);
- u32 id_len = be32_to_cpup(map + 3);
+ u32 id_base, phandle, id_len, id_off, cells = 0;
+ const __be32 *out_base;
+
+ if (map_len - offset < 2)
+ goto err_map_len;
+
+ id_base = be32_to_cpup(map + offset);
if (id_base & ~map_mask) {
- pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores id-base (0x%x)\n",
- np, map_name, map_name,
- map_mask, id_base);
+ pr_err("%pOF: Invalid %s translation - %s (0x%x) ignores id-base (0x%x)\n",
+ np, map_name, map_mask_name, map_mask, id_base);
return -EFAULT;
}
- if (masked_id < id_base || masked_id >= id_base + id_len)
- continue;
-
+ phandle = be32_to_cpup(map + offset + 1);
phandle_node = of_find_node_by_phandle(phandle);
if (!phandle_node)
return -ENODEV;
+ if (bad_map) {
+ cells = 1;
+ } else if (of_property_read_u32(phandle_node, cells_name, &cells)) {
+ pr_err("%pOF: missing %s property\n", phandle_node, cells_name);
+ of_node_put(phandle_node);
+ return -EINVAL;
+ }
+
+ if (map_len - offset < 3 + cells) {
+ of_node_put(phandle_node);
+ goto err_map_len;
+ }
+
+ if (offset == 0 && cells == 2) {
+ bad_map = of_check_bad_map(map, map_len);
+ if (bad_map) {
+ pr_warn_once("%pOF: %s mismatches target %s, assuming extra cell of 0\n",
+ np, map_name, cells_name);
+ cells = 1;
+ }
+ }
+
+ out_base = map + offset + 2;
+ offset += 3 + cells;
+
+ id_len = be32_to_cpup(map + offset - 1);
+ if (id_len > 1 && cells > 1) {
+ /*
+ * With 1 output cell we reasonably assume its value
+ * has a linear relationship to the input; with more,
+ * we'd need help from the provider to know what to do.
+ */
+ pr_err("%pOF: Unsupported %s - cannot handle %d-ID range with %d-cell output specifier\n",
+ np, map_name, id_len, cells);
+ of_node_put(phandle_node);
+ return -EINVAL;
+ }
+ id_off = masked_id - id_base;
+ if (masked_id < id_base || id_off >= id_len) {
+ of_node_put(phandle_node);
+ continue;
+ }
+
if (filter_np && filter_np != phandle_node) {
of_node_put(phandle_node);
continue;
}
arg->np = phandle_node;
- arg->args[0] = masked_id - id_base + out_base;
- arg->args_count = 1;
+ for (int i = 0; i < cells; i++)
+ arg->args[i] = id_off + be32_to_cpu(out_base[i]);
+ arg->args_count = cells;
pr_debug("%pOF: %s, using mask %08x, id-base: %08x, out-base: %08x, length: %08x, id: %08x -> %08x\n",
- np, map_name, map_mask, id_base, out_base,
- id_len, id, masked_id - id_base + out_base);
+ np, map_name, map_mask, id_base, be32_to_cpup(out_base),
+ id_len, id, id_off + be32_to_cpup(out_base));
return 0;
}
@@ -2196,6 +2271,10 @@ int of_map_id(const struct device_node *np, u32 id,
arg->args[0] = id;
arg->args_count = 1;
return 0;
+
+err_map_len:
+ pr_err("%pOF: Error: Bad %s length: %d\n", np, map_name, map_bytes);
+ return -EINVAL;
}
EXPORT_SYMBOL_GPL(of_map_id);
@@ -2205,18 +2284,21 @@ EXPORT_SYMBOL_GPL(of_map_id);
* @id: Requester ID of the device (e.g. PCI RID/BDF or a platform
* stream/device ID) used as the lookup key in the iommu-map table.
* @arg: pointer to a &struct of_phandle_args for the result. On success,
- * @arg->args[0] contains the translated ID. If a map entry was matched,
- * @arg->np holds a reference to the target node that the caller must
- * release with of_node_put().
+ * @arg->args_count will be set to the number of output specifier cells
+ * and @arg->args[0..args_count-1] will contain the translated output
+ * specifier values. If a map entry was matched, @arg->np holds a
+ * reference to the target node that the caller must release with
+ * of_node_put().
*
- * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask".
+ * Convenience wrapper around of_map_id() using "iommu-map", "#iommu-cells",
+ * and "iommu-map-mask".
*
* Return: 0 on success or a standard error code on failure.
*/
int of_map_iommu_id(const struct device_node *np, u32 id,
struct of_phandle_args *arg)
{
- return of_map_id(np, id, "iommu-map", "iommu-map-mask", NULL, arg);
+ return of_map_id(np, id, "iommu-map", "#iommu-cells", "iommu-map-mask", NULL, arg);
}
EXPORT_SYMBOL_GPL(of_map_iommu_id);
@@ -2229,17 +2311,20 @@ EXPORT_SYMBOL_GPL(of_map_iommu_id);
* to match any. If non-NULL, only map entries targeting this node will
* be matched.
* @arg: pointer to a &struct of_phandle_args for the result. On success,
- * @arg->args[0] contains the translated ID. If a map entry was matched,
- * @arg->np holds a reference to the target node that the caller must
- * release with of_node_put().
+ * @arg->args_count will be set to the number of output specifier cells
+ * and @arg->args[0..args_count-1] will contain the translated output
+ * specifier values. If a map entry was matched, @arg->np holds a
+ * reference to the target node that the caller must release with
+ * of_node_put().
*
- * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask".
+ * Convenience wrapper around of_map_id() using "msi-map", "#msi-cells",
+ * and "msi-map-mask".
*
* Return: 0 on success or a standard error code on failure.
*/
int of_map_msi_id(const struct device_node *np, u32 id,
const struct device_node *filter_np, struct of_phandle_args *arg)
{
- return of_map_id(np, id, "msi-map", "msi-map-mask", filter_np, arg);
+ return of_map_id(np, id, "msi-map", "#msi-cells", "msi-map-mask", filter_np, arg);
}
EXPORT_SYMBOL_GPL(of_map_msi_id);
diff --git a/include/linux/of.h b/include/linux/of.h
index 8548cd9eb4f1..51ac8539f2c3 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -462,7 +462,8 @@ const char *of_prop_next_string(const struct property *prop, const char *cur);
bool of_console_check(const struct device_node *dn, char *name, int index);
int of_map_id(const struct device_node *np, u32 id,
- const char *map_name, const char *map_mask_name,
+ const char *map_name, const char *cells_name,
+ const char *map_mask_name,
const struct device_node *filter_np, struct of_phandle_args *arg);
int of_map_iommu_id(const struct device_node *np, u32 id,
@@ -934,7 +935,8 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag
}
static inline int of_map_id(const struct device_node *np, u32 id,
- const char *map_name, const char *map_mask_name,
+ const char *map_name, const char *cells_name,
+ const char *map_mask_name,
const struct device_node *filter_np,
struct of_phandle_args *arg)
{
--
2.34.1
^ permalink raw reply related
* [PATCH v13 2/3] of: Factor arguments passed to of_map_id() into a struct
From: Vijayanand Jitta @ 2026-04-08 10:03 UTC (permalink / raw)
To: Nipun Gupta, Nikhil Agarwal, Joerg Roedel, Will Deacon,
Robin Murphy, Marc Zyngier, Lorenzo Pieralisi, Thomas Gleixner,
Saravana Kannan, Richard Zhu, Lucas Stach,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Juergen Gross, Stefano Stabellini, Oleksandr Tyshchenko,
Dmitry Baryshkov, Konrad Dybcio, Bjorn Andersson, Rob Herring,
Conor Dooley, Krzysztof Kozlowski, Prakash Gupta, Vikash Garodia
Cc: linux-kernel, iommu, linux-arm-kernel, devicetree, linux-pci, imx,
xen-devel, linux-arm-msm, Vijayanand Jitta, Charan Teja Kalla
In-Reply-To: <20260408-parse_iommu_cells-v13-0-fa921e92661b@oss.qualcomm.com>
From: Charan Teja Kalla <charan.kalla@oss.qualcomm.com>
Change of_map_id() to take a pointer to struct of_phandle_args
instead of passing target device node and translated IDs separately.
Update all callers accordingly.
Add an explicit filter_np parameter to of_map_id() and of_map_msi_id()
to separate the filter input from the output. Previously, the target
parameter served dual purpose: as an input filter (if non-NULL, only
match entries targeting that node) and as an output (receiving the
matched node with a reference held). Now filter_np is the explicit
input filter and arg->np is the pure output.
Previously, of_map_id() would call of_node_put() on the matched node
when a filter was provided, making reference ownership inconsistent.
Remove this internal of_node_put() call so that of_map_id() now always
transfers ownership of the matched node reference to the caller via
arg->np. Callers are now consistently responsible for releasing this
reference with of_node_put(arg->np) when done.
Acked-by: Frank Li <Frank.Li@nxp.com>
Suggested-by: Rob Herring (Arm) <robh@kernel.org>
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Charan Teja Kalla <charan.kalla@oss.qualcomm.com>
Signed-off-by: Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com>
---
drivers/cdx/cdx_msi.c | 7 ++--
drivers/iommu/of_iommu.c | 4 +-
drivers/irqchip/irq-gic-its-msi-parent.c | 11 ++++--
drivers/of/base.c | 68 +++++++++++++++++---------------
drivers/of/irq.c | 10 ++++-
drivers/pci/controller/dwc/pci-imx6.c | 32 +++++++--------
drivers/pci/controller/pcie-apple.c | 5 ++-
drivers/xen/grant-dma-ops.c | 4 +-
include/linux/of.h | 14 ++++---
9 files changed, 89 insertions(+), 66 deletions(-)
diff --git a/drivers/cdx/cdx_msi.c b/drivers/cdx/cdx_msi.c
index 63b3544ec997..6924e07c7528 100644
--- a/drivers/cdx/cdx_msi.c
+++ b/drivers/cdx/cdx_msi.c
@@ -121,22 +121,23 @@ static int cdx_msi_prepare(struct irq_domain *msi_domain,
struct device *dev,
int nvec, msi_alloc_info_t *info)
{
+ struct of_phandle_args msi_spec = {};
struct cdx_device *cdx_dev = to_cdx_device(dev);
struct device *parent = cdx_dev->cdx->dev;
struct msi_domain_info *msi_info;
- u32 dev_id;
int ret;
/* Retrieve device ID from requestor ID using parent device */
- ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &dev_id);
+ ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &msi_spec);
if (ret) {
dev_err(dev, "of_map_id failed for MSI: %d\n", ret);
return ret;
}
+ of_node_put(msi_spec.np);
#ifdef GENERIC_MSI_DOMAIN_OPS
/* Set the device Id to be passed to the GIC-ITS */
- info->scratchpad[0].ul = dev_id;
+ info->scratchpad[0].ul = msi_spec.args[0];
#endif
msi_info = msi_get_domain_info(msi_domain->parent);
diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
index a511ecf21fcd..a18bb60f6f3d 100644
--- a/drivers/iommu/of_iommu.c
+++ b/drivers/iommu/of_iommu.c
@@ -45,10 +45,10 @@ static int of_iommu_configure_dev_id(struct device_node *master_np,
struct device *dev,
const u32 *id)
{
- struct of_phandle_args iommu_spec = { .args_count = 1 };
+ struct of_phandle_args iommu_spec = {};
int err;
- err = of_map_iommu_id(master_np, *id, &iommu_spec.np, iommu_spec.args);
+ err = of_map_iommu_id(master_np, *id, &iommu_spec);
if (err)
return err;
diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq-gic-its-msi-parent.c
index b63343a227a9..dd5f84b6470a 100644
--- a/drivers/irqchip/irq-gic-its-msi-parent.c
+++ b/drivers/irqchip/irq-gic-its-msi-parent.c
@@ -152,6 +152,8 @@ static int its_v5_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u32 *dev_id,
phys_addr_t *pa)
{
+ struct device_node *msi_ctrl __free(device_node) = NULL;
+ struct of_phandle_args msi_spec = {};
struct of_phandle_iterator it;
int ret;
@@ -178,9 +180,12 @@ static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u
}
}
- struct device_node *msi_ctrl __free(device_node) = NULL;
-
- return of_map_msi_id(dev->of_node, dev->id, &msi_ctrl, dev_id);
+ ret = of_map_msi_id(dev->of_node, dev->id, NULL, &msi_spec);
+ if (!ret) {
+ msi_ctrl = msi_spec.np;
+ *dev_id = msi_spec.args[0];
+ }
+ return ret;
}
static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev,
diff --git a/drivers/of/base.c b/drivers/of/base.c
index ae04487bd614..b3d002015192 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -2102,36 +2102,37 @@ int of_find_last_cache_level(unsigned int cpu)
* @id: device ID to map.
* @map_name: property name of the map to use.
* @map_mask_name: optional property name of the mask to use.
- * @target: optional pointer to a target device node.
- * @id_out: optional pointer to receive the translated ID.
+ * @filter_np: optional device node to filter matches by, or NULL to match any.
+ * If non-NULL, only map entries targeting this node will be matched.
+ * @arg: pointer to a &struct of_phandle_args for the result. On success,
+ * @arg->args[0] will contain the translated ID. If a map entry was
+ * matched, @arg->np will be set to the target node with a reference
+ * held that the caller must release with of_node_put().
*
* Given a device ID, look up the appropriate implementation-defined
* platform ID and/or the target device which receives transactions on that
- * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or
- * @id_out may be NULL if only the other is required. If @target points to
- * a non-NULL device node pointer, only entries targeting that node will be
- * matched; if it points to a NULL value, it will receive the device node of
- * the first matching target phandle, with a reference held.
+ * ID, as per the "iommu-map" and "msi-map" bindings.
*
* Return: 0 on success or a standard error code on failure.
*/
int of_map_id(const struct device_node *np, u32 id,
const char *map_name, const char *map_mask_name,
- struct device_node **target, u32 *id_out)
+ const struct device_node *filter_np, struct of_phandle_args *arg)
{
u32 map_mask, masked_id;
int map_len;
const __be32 *map = NULL;
- if (!np || !map_name || (!target && !id_out))
+ if (!np || !map_name || !arg)
return -EINVAL;
map = of_get_property(np, map_name, &map_len);
if (!map) {
- if (target)
+ if (filter_np)
return -ENODEV;
/* Otherwise, no map implies no translation */
- *id_out = id;
+ arg->args[0] = id;
+ arg->args_count = 1;
return 0;
}
@@ -2173,18 +2174,14 @@ int of_map_id(const struct device_node *np, u32 id,
if (!phandle_node)
return -ENODEV;
- if (target) {
- if (*target)
- of_node_put(phandle_node);
- else
- *target = phandle_node;
-
- if (*target != phandle_node)
- continue;
+ if (filter_np && filter_np != phandle_node) {
+ of_node_put(phandle_node);
+ continue;
}
- if (id_out)
- *id_out = masked_id - id_base + out_base;
+ arg->np = phandle_node;
+ arg->args[0] = masked_id - id_base + out_base;
+ arg->args_count = 1;
pr_debug("%pOF: %s, using mask %08x, id-base: %08x, out-base: %08x, length: %08x, id: %08x -> %08x\n",
np, map_name, map_mask, id_base, out_base,
@@ -2193,11 +2190,11 @@ int of_map_id(const struct device_node *np, u32 id,
}
pr_info("%pOF: no %s translation for id 0x%x on %pOF\n", np, map_name,
- id, target && *target ? *target : NULL);
+ id, filter_np);
/* Bypasses translation */
- if (id_out)
- *id_out = id;
+ arg->args[0] = id;
+ arg->args_count = 1;
return 0;
}
EXPORT_SYMBOL_GPL(of_map_id);
@@ -2207,17 +2204,19 @@ EXPORT_SYMBOL_GPL(of_map_id);
* @np: root complex device node.
* @id: Requester ID of the device (e.g. PCI RID/BDF or a platform
* stream/device ID) used as the lookup key in the iommu-map table.
- * @target: optional pointer to a target device node.
- * @id_out: optional pointer to receive the translated ID.
+ * @arg: pointer to a &struct of_phandle_args for the result. On success,
+ * @arg->args[0] contains the translated ID. If a map entry was matched,
+ * @arg->np holds a reference to the target node that the caller must
+ * release with of_node_put().
*
* Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask".
*
* Return: 0 on success or a standard error code on failure.
*/
int of_map_iommu_id(const struct device_node *np, u32 id,
- struct device_node **target, u32 *id_out)
+ struct of_phandle_args *arg)
{
- return of_map_id(np, id, "iommu-map", "iommu-map-mask", target, id_out);
+ return of_map_id(np, id, "iommu-map", "iommu-map-mask", NULL, arg);
}
EXPORT_SYMBOL_GPL(of_map_iommu_id);
@@ -2226,16 +2225,21 @@ EXPORT_SYMBOL_GPL(of_map_iommu_id);
* @np: root complex device node.
* @id: Requester ID of the device (e.g. PCI RID/BDF or a platform
* stream/device ID) used as the lookup key in the msi-map table.
- * @target: optional pointer to a target device node.
- * @id_out: optional pointer to receive the translated ID.
+ * @filter_np: optional MSI controller node to filter matches by, or NULL
+ * to match any. If non-NULL, only map entries targeting this node will
+ * be matched.
+ * @arg: pointer to a &struct of_phandle_args for the result. On success,
+ * @arg->args[0] contains the translated ID. If a map entry was matched,
+ * @arg->np holds a reference to the target node that the caller must
+ * release with of_node_put().
*
* Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask".
*
* Return: 0 on success or a standard error code on failure.
*/
int of_map_msi_id(const struct device_node *np, u32 id,
- struct device_node **target, u32 *id_out)
+ const struct device_node *filter_np, struct of_phandle_args *arg)
{
- return of_map_id(np, id, "msi-map", "msi-map-mask", target, id_out);
+ return of_map_id(np, id, "msi-map", "msi-map-mask", filter_np, arg);
}
EXPORT_SYMBOL_GPL(of_map_msi_id);
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index e37c1b3f8736..f86a56bd81fc 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -817,8 +817,16 @@ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in)
* "msi-map" or an "msi-parent" property.
*/
for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent) {
- if (!of_map_msi_id(parent_dev->of_node, id_in, msi_np, &id_out))
+ struct of_phandle_args msi_spec = {};
+
+ if (!of_map_msi_id(parent_dev->of_node, id_in, *msi_np, &msi_spec)) {
+ id_out = msi_spec.args[0];
+ if (!*msi_np)
+ *msi_np = msi_spec.np;
+ else
+ of_node_put(msi_spec.np);
break;
+ }
if (!of_check_msi_parent(parent_dev->of_node, msi_np))
break;
}
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index bff8289f804a..c0544d9c0921 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1137,30 +1137,32 @@ static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 rid)
static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid)
{
+ struct of_phandle_args iommu_spec = {};
+ struct of_phandle_args msi_spec = {};
struct device *dev = imx_pcie->pci->dev;
- struct device_node *target;
u32 sid_i, sid_m;
int err_i, err_m;
u32 sid = 0;
- target = NULL;
- err_i = of_map_iommu_id(dev->of_node, rid, &target, &sid_i);
- if (target) {
- of_node_put(target);
- } else {
+ err_i = of_map_iommu_id(dev->of_node, rid, &iommu_spec);
+ if (!err_i)
+ sid_i = iommu_spec.args[0];
+ of_node_put(iommu_spec.np);
+ if (!err_i && !iommu_spec.np) {
/*
- * "target == NULL && err_i == 0" means RID out of map range.
- * Use 1:1 map RID to streamID. Hardware can't support this
- * because the streamID is only 6 bits
+ * "iommu_spec.np == NULL && err_i == 0" means RID out of map
+ * range. Use 1:1 map RID to streamID. Hardware can't support
+ * this because the streamID is only 6 bits.
*/
err_i = -EINVAL;
}
- target = NULL;
- err_m = of_map_msi_id(dev->of_node, rid, &target, &sid_m);
-
+ err_m = of_map_msi_id(dev->of_node, rid, NULL, &msi_spec);
+ if (!err_m)
+ sid_m = msi_spec.args[0];
+ of_node_put(msi_spec.np);
/*
- * err_m target
+ * err_m msi_spec.np
* 0 NULL RID out of range. Use 1:1 map RID to
* streamID, Current hardware can't
* support it, so return -EINVAL.
@@ -1168,10 +1170,8 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid)
* 0 != NULL Get correct streamID from RID
* != 0 != NULL Invalid combination
*/
- if (!err_m && !target)
+ if (!err_m && !msi_spec.np)
return -EINVAL;
- else if (target)
- of_node_put(target); /* Find streamID map entry for RID in msi-map */
/*
* msi-map iommu-map
diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c
index a0937b7b3c4d..c2cffc0659f4 100644
--- a/drivers/pci/controller/pcie-apple.c
+++ b/drivers/pci/controller/pcie-apple.c
@@ -755,6 +755,7 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d
{
u32 sid, rid = pci_dev_id(pdev);
struct apple_pcie_port *port;
+ struct of_phandle_args iommu_spec = {};
int idx, err;
port = apple_pcie_get_port(pdev);
@@ -764,10 +765,12 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d
dev_dbg(&pdev->dev, "added to bus %s, index %d\n",
pci_name(pdev->bus->self), port->idx);
- err = of_map_iommu_id(port->pcie->dev->of_node, rid, NULL, &sid);
+ err = of_map_iommu_id(port->pcie->dev->of_node, rid, &iommu_spec);
if (err)
return err;
+ of_node_put(iommu_spec.np);
+ sid = iommu_spec.args[0];
mutex_lock(&port->pcie->lock);
idx = bitmap_find_free_region(port->sid_map, port->sid_map_sz, 0);
diff --git a/drivers/xen/grant-dma-ops.c b/drivers/xen/grant-dma-ops.c
index 1b7696b2d762..2aa1a772a0ff 100644
--- a/drivers/xen/grant-dma-ops.c
+++ b/drivers/xen/grant-dma-ops.c
@@ -319,13 +319,13 @@ static int xen_dt_grant_init_backend_domid(struct device *dev,
struct device_node *np,
domid_t *backend_domid)
{
- struct of_phandle_args iommu_spec = { .args_count = 1 };
+ struct of_phandle_args iommu_spec = {};
if (dev_is_pci(dev)) {
struct pci_dev *pdev = to_pci_dev(dev);
u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn);
- if (of_map_iommu_id(np, rid, &iommu_spec.np, iommu_spec.args)) {
+ if (of_map_iommu_id(np, rid, &iommu_spec)) {
dev_dbg(dev, "Cannot translate ID\n");
return -ESRCH;
}
diff --git a/include/linux/of.h b/include/linux/of.h
index fe841f3cc747..8548cd9eb4f1 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -463,13 +463,13 @@ bool of_console_check(const struct device_node *dn, char *name, int index);
int of_map_id(const struct device_node *np, u32 id,
const char *map_name, const char *map_mask_name,
- struct device_node **target, u32 *id_out);
+ const struct device_node *filter_np, struct of_phandle_args *arg);
int of_map_iommu_id(const struct device_node *np, u32 id,
- struct device_node **target, u32 *id_out);
+ struct of_phandle_args *arg);
int of_map_msi_id(const struct device_node *np, u32 id,
- struct device_node **target, u32 *id_out);
+ const struct device_node *filter_np, struct of_phandle_args *arg);
phys_addr_t of_dma_get_max_cpu_address(struct device_node *np);
@@ -935,19 +935,21 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag
static inline int of_map_id(const struct device_node *np, u32 id,
const char *map_name, const char *map_mask_name,
- struct device_node **target, u32 *id_out)
+ const struct device_node *filter_np,
+ struct of_phandle_args *arg)
{
return -EINVAL;
}
static inline int of_map_iommu_id(const struct device_node *np, u32 id,
- struct device_node **target, u32 *id_out)
+ struct of_phandle_args *arg)
{
return -EINVAL;
}
static inline int of_map_msi_id(const struct device_node *np, u32 id,
- struct device_node **target, u32 *id_out)
+ const struct device_node *filter_np,
+ struct of_phandle_args *arg)
{
return -EINVAL;
}
--
2.34.1
^ permalink raw reply related
* [PATCH v13 1/3] of: Add convenience wrappers for of_map_id()
From: Vijayanand Jitta @ 2026-04-08 10:03 UTC (permalink / raw)
To: Nipun Gupta, Nikhil Agarwal, Joerg Roedel, Will Deacon,
Robin Murphy, Marc Zyngier, Lorenzo Pieralisi, Thomas Gleixner,
Saravana Kannan, Richard Zhu, Lucas Stach,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Juergen Gross, Stefano Stabellini, Oleksandr Tyshchenko,
Dmitry Baryshkov, Konrad Dybcio, Bjorn Andersson, Rob Herring,
Conor Dooley, Krzysztof Kozlowski, Prakash Gupta, Vikash Garodia
Cc: linux-kernel, iommu, linux-arm-kernel, devicetree, linux-pci, imx,
xen-devel, linux-arm-msm, Vijayanand Jitta
In-Reply-To: <20260408-parse_iommu_cells-v13-0-fa921e92661b@oss.qualcomm.com>
From: Robin Murphy <robin.murphy@arm.com>
Since we now have quite a few users parsing "iommu-map" and "msi-map"
properties, give them some wrappers to conveniently encapsulate the
appropriate sets of property names. This will also make it easier to
then change of_map_id() to correctly account for specifier cells.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com>
---
drivers/cdx/cdx_msi.c | 3 +--
drivers/iommu/of_iommu.c | 4 +---
drivers/irqchip/irq-gic-its-msi-parent.c | 2 +-
drivers/of/base.c | 38 ++++++++++++++++++++++++++++++++
drivers/of/irq.c | 3 +--
drivers/pci/controller/dwc/pci-imx6.c | 6 ++---
drivers/pci/controller/pcie-apple.c | 3 +--
drivers/xen/grant-dma-ops.c | 3 +--
include/linux/of.h | 18 +++++++++++++++
9 files changed, 64 insertions(+), 16 deletions(-)
diff --git a/drivers/cdx/cdx_msi.c b/drivers/cdx/cdx_msi.c
index 91b95422b263..63b3544ec997 100644
--- a/drivers/cdx/cdx_msi.c
+++ b/drivers/cdx/cdx_msi.c
@@ -128,8 +128,7 @@ static int cdx_msi_prepare(struct irq_domain *msi_domain,
int ret;
/* Retrieve device ID from requestor ID using parent device */
- ret = of_map_id(parent->of_node, cdx_dev->msi_dev_id, "msi-map", "msi-map-mask",
- NULL, &dev_id);
+ ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &dev_id);
if (ret) {
dev_err(dev, "of_map_id failed for MSI: %d\n", ret);
return ret;
diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
index 6b989a62def2..a511ecf21fcd 100644
--- a/drivers/iommu/of_iommu.c
+++ b/drivers/iommu/of_iommu.c
@@ -48,9 +48,7 @@ static int of_iommu_configure_dev_id(struct device_node *master_np,
struct of_phandle_args iommu_spec = { .args_count = 1 };
int err;
- err = of_map_id(master_np, *id, "iommu-map",
- "iommu-map-mask", &iommu_spec.np,
- iommu_spec.args);
+ err = of_map_iommu_id(master_np, *id, &iommu_spec.np, iommu_spec.args);
if (err)
return err;
diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq-gic-its-msi-parent.c
index d36b278ae66c..b63343a227a9 100644
--- a/drivers/irqchip/irq-gic-its-msi-parent.c
+++ b/drivers/irqchip/irq-gic-its-msi-parent.c
@@ -180,7 +180,7 @@ static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u
struct device_node *msi_ctrl __free(device_node) = NULL;
- return of_map_id(dev->of_node, dev->id, "msi-map", "msi-map-mask", &msi_ctrl, dev_id);
+ return of_map_msi_id(dev->of_node, dev->id, &msi_ctrl, dev_id);
}
static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev,
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 57420806c1a2..ae04487bd614 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -2201,3 +2201,41 @@ int of_map_id(const struct device_node *np, u32 id,
return 0;
}
EXPORT_SYMBOL_GPL(of_map_id);
+
+/**
+ * of_map_iommu_id - Translate an ID using "iommu-map" bindings.
+ * @np: root complex device node.
+ * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform
+ * stream/device ID) used as the lookup key in the iommu-map table.
+ * @target: optional pointer to a target device node.
+ * @id_out: optional pointer to receive the translated ID.
+ *
+ * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask".
+ *
+ * Return: 0 on success or a standard error code on failure.
+ */
+int of_map_iommu_id(const struct device_node *np, u32 id,
+ struct device_node **target, u32 *id_out)
+{
+ return of_map_id(np, id, "iommu-map", "iommu-map-mask", target, id_out);
+}
+EXPORT_SYMBOL_GPL(of_map_iommu_id);
+
+/**
+ * of_map_msi_id - Translate an ID using "msi-map" bindings.
+ * @np: root complex device node.
+ * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform
+ * stream/device ID) used as the lookup key in the msi-map table.
+ * @target: optional pointer to a target device node.
+ * @id_out: optional pointer to receive the translated ID.
+ *
+ * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask".
+ *
+ * Return: 0 on success or a standard error code on failure.
+ */
+int of_map_msi_id(const struct device_node *np, u32 id,
+ struct device_node **target, u32 *id_out)
+{
+ return of_map_id(np, id, "msi-map", "msi-map-mask", target, id_out);
+}
+EXPORT_SYMBOL_GPL(of_map_msi_id);
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 6367c67732d2..e37c1b3f8736 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -817,8 +817,7 @@ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in)
* "msi-map" or an "msi-parent" property.
*/
for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent) {
- if (!of_map_id(parent_dev->of_node, id_in, "msi-map",
- "msi-map-mask", msi_np, &id_out))
+ if (!of_map_msi_id(parent_dev->of_node, id_in, msi_np, &id_out))
break;
if (!of_check_msi_parent(parent_dev->of_node, msi_np))
break;
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index a5b8d0b71677..bff8289f804a 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1144,8 +1144,7 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid)
u32 sid = 0;
target = NULL;
- err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask",
- &target, &sid_i);
+ err_i = of_map_iommu_id(dev->of_node, rid, &target, &sid_i);
if (target) {
of_node_put(target);
} else {
@@ -1158,8 +1157,7 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid)
}
target = NULL;
- err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask",
- &target, &sid_m);
+ err_m = of_map_msi_id(dev->of_node, rid, &target, &sid_m);
/*
* err_m target
diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c
index 2d92fc79f6dd..a0937b7b3c4d 100644
--- a/drivers/pci/controller/pcie-apple.c
+++ b/drivers/pci/controller/pcie-apple.c
@@ -764,8 +764,7 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d
dev_dbg(&pdev->dev, "added to bus %s, index %d\n",
pci_name(pdev->bus->self), port->idx);
- err = of_map_id(port->pcie->dev->of_node, rid, "iommu-map",
- "iommu-map-mask", NULL, &sid);
+ err = of_map_iommu_id(port->pcie->dev->of_node, rid, NULL, &sid);
if (err)
return err;
diff --git a/drivers/xen/grant-dma-ops.c b/drivers/xen/grant-dma-ops.c
index c2603e700178..1b7696b2d762 100644
--- a/drivers/xen/grant-dma-ops.c
+++ b/drivers/xen/grant-dma-ops.c
@@ -325,8 +325,7 @@ static int xen_dt_grant_init_backend_domid(struct device *dev,
struct pci_dev *pdev = to_pci_dev(dev);
u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn);
- if (of_map_id(np, rid, "iommu-map", "iommu-map-mask", &iommu_spec.np,
- iommu_spec.args)) {
+ if (of_map_iommu_id(np, rid, &iommu_spec.np, iommu_spec.args)) {
dev_dbg(dev, "Cannot translate ID\n");
return -ESRCH;
}
diff --git a/include/linux/of.h b/include/linux/of.h
index be6ec4916adf..fe841f3cc747 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -465,6 +465,12 @@ int of_map_id(const struct device_node *np, u32 id,
const char *map_name, const char *map_mask_name,
struct device_node **target, u32 *id_out);
+int of_map_iommu_id(const struct device_node *np, u32 id,
+ struct device_node **target, u32 *id_out);
+
+int of_map_msi_id(const struct device_node *np, u32 id,
+ struct device_node **target, u32 *id_out);
+
phys_addr_t of_dma_get_max_cpu_address(struct device_node *np);
struct kimage;
@@ -934,6 +940,18 @@ static inline int of_map_id(const struct device_node *np, u32 id,
return -EINVAL;
}
+static inline int of_map_iommu_id(const struct device_node *np, u32 id,
+ struct device_node **target, u32 *id_out)
+{
+ return -EINVAL;
+}
+
+static inline int of_map_msi_id(const struct device_node *np, u32 id,
+ struct device_node **target, u32 *id_out)
+{
+ return -EINVAL;
+}
+
static inline phys_addr_t of_dma_get_max_cpu_address(struct device_node *np)
{
return PHYS_ADDR_MAX;
--
2.34.1
^ permalink raw reply related
* [PATCH v13 0/3] of: parsing of multi #{iommu,msi}-cells in maps
From: Vijayanand Jitta @ 2026-04-08 10:03 UTC (permalink / raw)
To: Nipun Gupta, Nikhil Agarwal, Joerg Roedel, Will Deacon,
Robin Murphy, Marc Zyngier, Lorenzo Pieralisi, Thomas Gleixner,
Saravana Kannan, Richard Zhu, Lucas Stach,
Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Juergen Gross, Stefano Stabellini, Oleksandr Tyshchenko,
Dmitry Baryshkov, Konrad Dybcio, Bjorn Andersson, Rob Herring,
Conor Dooley, Krzysztof Kozlowski, Prakash Gupta, Vikash Garodia
Cc: linux-kernel, iommu, linux-arm-kernel, devicetree, linux-pci, imx,
xen-devel, linux-arm-msm, Vijayanand Jitta, Charan Teja Kalla
So far our parsing of {iommu,msi}-map properties has always blindly
assumed that the output specifiers will always have exactly 1 cell.
This typically does happen to be the case, but is not actually enforced
(and the PCI msi-map binding even explicitly states support for 0 or 1
cells) - as a result we've now ended up with dodgy DTs out in the field
which depend on this behaviour to map a 1-cell specifier for a 2-cell
provider, despite that being bogus per the bindings themselves.
Since there is some potential use[1] in being able to map at least
single input IDs to multi-cell output specifiers (and properly support
0-cell outputs as well), add support for properly parsing and using the
target nodes' #cells values, albeit with the unfortunate complication of
still having to work around expectations of the old behaviour too.
-- Robin.
Unlike single #{}-cell, it is complex to establish a linear relation
between input 'id' and output specifier for multi-cell properties, thus
it is always expected that len never going to be > 1.
These changes have been tested on QEMU for the arm64 architecture.
Since, this would also need update in dt-schema, raised PR[2] for the
same.
[1] https://lore.kernel.org/all/20250627-video_cb-v3-0-51e18c0ffbce@quicinc.com/
[2] PR for iommu-map dtschema: https://github.com/devicetree-org/dt-schema/pull/184
Robin,
Could this series be pulled into an immutable branch/tag, if it doesn't make
it into the v7.1 merge window? There are client changes dependent on it,
So it would help to get them moving forward rather than waiting another
cycle.
Thanks,
Vijay
V13:
- Fix bad_map handling in of_map_id(): 'cells' is re-initialized to 0
on each loop iteration, so the !bad_map guard was insufficient, cells
stayed 0 for all entries after the first. Fix by explicitly setting
cells=1 when bad_map is true on every iteration.
- Collected Acked-by from Frank Li.
Link to v12:
https://patch.msgid.link/20260331-parse_iommu_cells-v12-0-decfd305eea9@oss.qualcomm.com
V12:
- Call of_node_put() unconditionally in imx_pcie_add_lut_by_rid()
thereby addressing comments from Bjorn Helgaas.
Link to v11:
https://lore.kernel.org/r/20260325-parse_iommu_cells-v11-0-1fefa5c0e82c@oss.qualcomm.com
V11:
- Added explicit filter_np parameter to of_map_id() and of_map_msi_id()
per Dmitry Baryshkov's review feedback, making the filter explicit
instead of overloading arg->np as both input filter and output parameter.
- Removed of_node_put() from inside of_map_id(), making the caller responsible
for reference management. Updated of_msi_xlate() to properly handle reference counting.
- Collected ACKed by tags, and fixed minor typos.
Link to v10:
https://lore.kernel.org/r/20260309-parse_iommu_cells-v10-0-c62fcaa5a1d8@oss.qualcomm.com
V10:
- Move of_map_iommu_id()/of_map_msi_id() from include/linux/of.h to
drivers/of/base.c as out-of-line helpers per feedback from Marc Zyngier
and Rob Herring.
- Add kernel-doc to document both helpers for discoverability and
usage clarity.
- Fix of_map_msi_id() wrapper and all its callers (cdx_msi.c,
irq-gic-its-msi-parent.c, drivers/of/irq.c) to correctly use the new
struct of_phandle_args-based API with proper of_node_put() handling
as per feeback from Dmitry.
Link to v9:
https://lore.kernel.org/r/20260301-parse_iommu_cells-v9-0-4d1bceecc5e1@oss.qualcomm.com
V9:
- Updated TO/CC list based on feedback to include all relevant
maintainers.
- No functional changes to the patches themselves.
Link to V8:
https://lore.kernel.org/all/20260226074245.3098486-1-vijayanand.jitta@oss.qualcomm.com/
V8:
- Removed mentions of of_map_args from commit message to match code.
Link to V7:
https://lore.kernel.org/all/20260210101157.2145113-1-vijayanand.jitta@oss.qualcomm.com/
V7:
- Removed of_map_id_args structure and replaced it with
of_phandle_args as suggested by Dmitry.
Link to V6:
https://lore.kernel.org/all/20260121055400.937856-1-vijayanand.jitta@oss.qualcomm.com/
V6:
- Fixed build error reported by kernel test bot.
Link to V5:
https://lore.kernel.org/all/20260118181125.1436036-1-vijayanand.jitta@oss.qualcomm.com/
V5:
- Fixed Build Warnings.
- Raised PR for iommu-map dtschema: https://github.com/devicetree-org/dt-schema/pull/184
Link to V4:
https://lore.kernel.org/all/20251231114257.2382820-1-vijayanand.jitta@oss.qualcomm.com/
V4:
- Added Reviewed-by tag.
- Resolved warnings reported by kernel test bot, minor code
reorganization.
Link to V3:
https://lore.kernel.org/all/20251221213602.2413124-1-vijayanand.jitta@oss.qualcomm.com/
V3:
- Added Reviewed-by tag.
- Updated of_map_id_args struct as a wrapper to of_phandle_args and
added comment description as suggested by Rob Herring.
Link to V2:
https://lore.kernel.org/all/20251204095530.8627-1-vijayanand.jitta@oss.qualcomm.com/
V2:
- Incorporated the patches from Robin that does the clean implementation.
- Dropped the patches the were adding multi-map support from this series
as suggested.
V1:
https://lore.kernel.org/all/cover.1762235099.git.charan.kalla@oss.qualcomm.com/
RFC:
https://lore.kernel.org/all/20250928171718.436440-1-charan.kalla@oss.qualcomm.com/#r
Signed-off-by: Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com>
---
---
Charan Teja Kalla (1):
of: Factor arguments passed to of_map_id() into a struct
Robin Murphy (2):
of: Add convenience wrappers for of_map_id()
of: Respect #{iommu,msi}-cells in maps
drivers/cdx/cdx_msi.c | 8 +-
drivers/iommu/of_iommu.c | 6 +-
drivers/irqchip/irq-gic-its-msi-parent.c | 11 +-
drivers/of/base.c | 215 ++++++++++++++++++++++++-------
drivers/of/irq.c | 11 +-
drivers/pci/controller/dwc/pci-imx6.c | 34 +++--
drivers/pci/controller/pcie-apple.c | 6 +-
drivers/xen/grant-dma-ops.c | 5 +-
include/linux/of.h | 30 ++++-
9 files changed, 242 insertions(+), 84 deletions(-)
---
base-commit: 3fa5e5702a82d259897bd7e209469bc06368bf31
change-id: 20260301-parse_iommu_cells-1c33768aebba
Best regards,
--
Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v2 0/2] power: qcom,rpmpd: add RPMh power doamins support for Hawi SoC
From: Ulf Hansson @ 2026-04-08 10:02 UTC (permalink / raw)
To: Fenglin Wu
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio, Subbaraman Narayanamurthy, linux-arm-msm,
devicetree, linux-kernel, linux-pm, kernel, Taniya Das
In-Reply-To: <20260402-haw-rpmhpd-v2-0-2bce0767f2ca@oss.qualcomm.com>
On Fri, 3 Apr 2026 at 02:36, Fenglin Wu <fenglin.wu@oss.qualcomm.com> wrote:
>
> Add constant definitions for the new power domains and new voltage
> levels present in Hawi SoC. Also add RPMH power domain support for
> Hawi SoC.
>
> Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
The series applied for next, thanks!
Note, patch1 is also available on the immutable dt branch.
Kind regards
Uffe
> ---
> Changes in v2:
> - Squash patch 1 and 2 into a single binding change
> - Add trailers for the new patch 2
> - Link to v1: https://patch.msgid.link/20260401-haw-rpmhpd-v1-0-c830c79ed8f9@oss.qualcomm.com
>
> ---
> Fenglin Wu (2):
> dt-bindings: power: qcom,rpmhpd: Add RPMh power domain for Hawi SoC
> pmdomain: qcom: rpmhpd: Add power domains for Hawi SoC
>
> .../devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
> drivers/pmdomain/qcom/rpmhpd.c | 38 ++++++++++++++++++++++
> include/dt-bindings/power/qcom,rpmhpd.h | 12 +++++++
> 3 files changed, 51 insertions(+)
> ---
> base-commit: 33b1a2ee3a3df63e7a08e51e6de2b2d28ddf257f
> change-id: 20260401-haw-rpmhpd-b40a68a3ce79
>
> Best regards,
> --
> Fenglin Wu <fenglin.wu@oss.qualcomm.com>
>
^ permalink raw reply
* Re: [PATCH 2/2] pwm: clk-pwm: add GPIO and pinctrl support for constant output levels
From: Xilin Wu @ 2026-04-08 9:59 UTC (permalink / raw)
To: Nikita Travkin
Cc: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-pwm, devicetree, linux-kernel, linux-arm-msm
In-Reply-To: <41d54477e46354664360931ffcbeda11@trvn.ru>
On 4/7/2026 12:20 AM, Nikita Travkin wrote:
> Xilin Wu писал(а) 06.04.2026 20:50:
>> The clk-pwm driver cannot guarantee a defined output level when the
>> PWM is disabled or when 0%/100% duty cycle is requested, because the
>> pin state when the clock is stopped is hardware-dependent.
>>
>> Add optional GPIO and pinctrl support: when a GPIO descriptor and
>> pinctrl states ("default" for clock mux, "gpio" for GPIO mode) are
>> provided in the device tree, the driver switches the pin to GPIO mode
>> and drives the appropriate level for disabled/0%/100% states. For
>> normal PWM output, the pin is switched back to its clock function mux.
>>
>> If no GPIO is provided, the driver falls back to the original
>> clock-only behavior.
>>
>> Signed-off-by: Xilin Wu <sophon@radxa.com>
>> ---
>> drivers/pwm/pwm-clk.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++-----
>> 1 file changed, 66 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/pwm/pwm-clk.c b/drivers/pwm/pwm-clk.c
>> index f8f5af57acba..99821fae54e7 100644
>> --- a/drivers/pwm/pwm-clk.c
>> +++ b/drivers/pwm/pwm-clk.c
>> @@ -10,12 +10,15 @@
>> * Limitations:
>> * - Due to the fact that exact behavior depends on the underlying
>> * clock driver, various limitations are possible.
>> - * - Underlying clock may not be able to give 0% or 100% duty cycle
>> - * (constant off or on), exact behavior will depend on the clock.
>> - * - When the PWM is disabled, the clock will be disabled as well,
>> - * line state will depend on the clock.
>
> nit: I think those limitations would still stand for existing
> users, perhaps we could just add "... unless gpio pinctrl state
> is supplied" to these two?
Ack.
>
>> * - The clk API doesn't expose the necessary calls to implement
>> * .get_state().
>> + *
>> + * Optionally, a GPIO descriptor and pinctrl states ("default" and
>> + * "gpio") can be provided. When a constant output level is needed
>> + * (0% duty, 100% duty, or disabled), the driver switches the pin to
>> + * GPIO mode and drives the appropriate level. For normal PWM output
>> + * the pin is switched back to its clock function mux. If no GPIO is
>> + * provided, the driver falls back to the original clock-only behavior.
>> */
>>
>> #include <linux/kernel.h>
>> @@ -25,11 +28,17 @@
>> #include <linux/of.h>
>> #include <linux/platform_device.h>
>> #include <linux/clk.h>
>> +#include <linux/gpio/consumer.h>
>> +#include <linux/pinctrl/consumer.h>
>> #include <linux/pwm.h>
>>
>> struct pwm_clk_chip {
>> struct clk *clk;
>> bool clk_enabled;
>> + struct pinctrl *pinctrl;
>> + struct pinctrl_state *pins_default; /* clock function mux */
>> + struct pinctrl_state *pins_gpio; /* GPIO mode */
>> + struct gpio_desc *gpiod;
>> };
>>
>> static inline struct pwm_clk_chip *to_pwm_clk_chip(struct pwm_chip *chip)
>> @@ -45,14 +54,36 @@ static int pwm_clk_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>> u32 rate;
>> u64 period = state->period;
>> u64 duty_cycle = state->duty_cycle;
>> + bool constant_level = false;
>> + int gpio_value = 0;
>>
>> if (!state->enabled) {
>> - if (pwm->state.enabled) {
>> + constant_level = true;
>> + gpio_value = 0;
>> + } else if (state->duty_cycle == 0) {
>> + constant_level = true;
>> + gpio_value = (state->polarity == PWM_POLARITY_INVERSED) ? 1 : 0;
>> + } else if (state->duty_cycle >= state->period) {
>> + constant_level = true;
>> + gpio_value = (state->polarity == PWM_POLARITY_INVERSED) ? 0 : 1;
>> + }
>> +
>> + if (constant_level) {
>> + if (pcchip->gpiod) {
>> + pinctrl_select_state(pcchip->pinctrl, pcchip->pins_gpio);
>> + gpiod_direction_output(pcchip->gpiod, gpio_value);
>
> Is this the same case as below where gpio state has to be set
> before we can control it, or can we swap those so we first
> put gpio into a known state and only then mux it to the pad?
>
Yeah, I think it makes sense to set the gpio state first. Thanks for the
suggestion.
>
> Thanks for improving this driver,
> Nikita
>
>> + }
>> + if (pcchip->clk_enabled) {
>> clk_disable(pcchip->clk);
>> pcchip->clk_enabled = false;
>> }
>> return 0;
>> - } else if (!pwm->state.enabled) {
>> + }
>> +
>> + if (pcchip->gpiod)
>> + pinctrl_select_state(pcchip->pinctrl, pcchip->pins_default);
>> +
>> + if (!pcchip->clk_enabled) {
>> ret = clk_enable(pcchip->clk);
>> if (ret)
>> return ret;
>> @@ -97,6 +128,35 @@ static int pwm_clk_probe(struct platform_device *pdev)
>> return dev_err_probe(&pdev->dev, PTR_ERR(pcchip->clk),
>> "Failed to get clock\n");
>>
>> + pcchip->pinctrl = devm_pinctrl_get(&pdev->dev);
>> + if (IS_ERR(pcchip->pinctrl)) {
>> + ret = PTR_ERR(pcchip->pinctrl);
>> + pcchip->pinctrl = NULL;
>> + if (ret == -EPROBE_DEFER)
>> + return ret;
>> + } else {
>> + pcchip->pins_default = pinctrl_lookup_state(pcchip->pinctrl,
>> + PINCTRL_STATE_DEFAULT);
>> + pcchip->pins_gpio = pinctrl_lookup_state(pcchip->pinctrl,
>> + "gpio");
>> + if (IS_ERR(pcchip->pins_default) || IS_ERR(pcchip->pins_gpio))
>> + pcchip->pinctrl = NULL;
>> + }
>> +
>> + /*
>> + * Switch to GPIO pinctrl state before requesting the GPIO.
>> + * The driver core has already applied the "default" state, which
>> + * muxes the pin to the clock function and claims it. We must
>> + * release that claim first so that gpiolib can request the pin.
>> + */
>> + if (pcchip->pinctrl)
>> + pinctrl_select_state(pcchip->pinctrl, pcchip->pins_gpio);
>> +
>> + pcchip->gpiod = devm_gpiod_get_optional(&pdev->dev, NULL, GPIOD_ASIS);
>> + if (IS_ERR(pcchip->gpiod))
>> + return dev_err_probe(&pdev->dev, PTR_ERR(pcchip->gpiod),
>> + "Failed to get gpio\n");
>> +
>> chip->ops = &pwm_clk_ops;
>>
>> ret = pwmchip_add(chip);
>
--
Best regards,
Xilin Wu <sophon@radxa.com>
^ permalink raw reply
* Re: [PATCH 2/3] pinctrl: qcom: add the TLMM driver for the Nord platforms
From: Konrad Dybcio @ 2026-04-08 9:59 UTC (permalink / raw)
To: Bartosz Golaszewski, Bjorn Andersson, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Bartosz Golaszewski, Shawn Guo, Arnd Bergmann
Cc: linux-arm-msm, linux-gpio, devicetree, linux-kernel
In-Reply-To: <20260403-nord-tlmm-v1-2-4864f400c700@oss.qualcomm.com>
On 4/3/26 3:27 PM, Bartosz Golaszewski wrote:
> Add support for the TLMM controller on the Qualcomm Nord platform.
>
> Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> ---
[...]
> +static const struct msm_gpio_wakeirq_map nord_pdc_map[] = {
> + { 0, 67 }, { 1, 68 }, { 2, 82 }, { 3, 69 }, { 4, 70 },
> + { 5, 83 }, { 6, 71 }, { 7, 72 }, { 8, 84 }, { 9, 73 },
> + { 10, 119 }, { 11, 85 }, { 45, 107 }, { 46, 98 }, { 102, 77 },
> + { 108, 78 }, { 110, 120 }, { 114, 80 }, { 116, 81 }, { 120, 117 },
> + { 124, 108 }, { 126, 99 }, { 128, 100 }, { 132, 101 }, { 138, 87 },
> + { 142, 88 }, { 144, 89 }, { 153, 90 }, { 157, 91 }, { 159, 118 },
> + { 160, 110 }, { 161, 79 }, { 166, 109 }, { 168, 111 },
This list seems rather short.. are you sure it's complete?
And could you confirm that it's been synced for the prod verison of
the chip?
Konrad
^ permalink raw reply
* [PATCH 2/2] soc: qcom: socinfo: add SoC ID for IPQ9650 family
From: Kathiravan Thirumoorthy @ 2026-04-08 9:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Kathiravan Thirumoorthy
In-Reply-To: <20260408-ipq9650_soc_ids-v1-0-e76faac33f77@oss.qualcomm.com>
Add SoC IDs for Qualcomm's IPQ9650 family.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
drivers/soc/qcom/socinfo.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
index 8ffd903ebddb..77a605bfeb46 100644
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -533,6 +533,12 @@ static const struct soc_id soc_id[] = {
{ qcom_board_id(QCF2200) },
{ qcom_board_id(QCF3200) },
{ qcom_board_id(QCF3210) },
+ { qcom_board_id(IPQ9620) },
+ { qcom_board_id(IPQ9650) },
+ { qcom_board_id(IPQ9610) },
+ { qcom_board_id(IPQ9630) },
+ { qcom_board_id(IPQ9640) },
+ { qcom_board_id(IPQ9670) },
};
static const char *socinfo_machine(struct device *dev, unsigned int id)
--
2.34.1
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: arm: qcom,ids: add SOC IDs for IPQ9650 family
From: Kathiravan Thirumoorthy @ 2026-04-08 9:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Kathiravan Thirumoorthy
In-Reply-To: <20260408-ipq9650_soc_ids-v1-0-e76faac33f77@oss.qualcomm.com>
Add SoC IDs for Qualcomm's IPQ9650 family.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
include/dt-bindings/arm/qcom,ids.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index 336f7bb7188a..585017b98ee5 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -304,6 +304,12 @@
#define QCOM_ID_QCF2200 767
#define QCOM_ID_QCF3200 768
#define QCOM_ID_QCF3210 769
+#define QCOM_ID_IPQ9620 770
+#define QCOM_ID_IPQ9650 771
+#define QCOM_ID_IPQ9610 778
+#define QCOM_ID_IPQ9630 779
+#define QCOM_ID_IPQ9640 780
+#define QCOM_ID_IPQ9670 781
/*
* The board type and revision information, used by Qualcomm bootloaders and
--
2.34.1
^ permalink raw reply related
* [PATCH 0/2] Add the SoC ID for the Qualcomm's IPQ9650 family
From: Kathiravan Thirumoorthy @ 2026-04-08 9:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Kathiravan Thirumoorthy
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
Kathiravan Thirumoorthy (2):
dt-bindings: arm: qcom,ids: add SOC IDs for IPQ9650 family
soc: qcom: socinfo: add SoC ID for IPQ9650 family
drivers/soc/qcom/socinfo.c | 6 ++++++
include/dt-bindings/arm/qcom,ids.h | 6 ++++++
2 files changed, 12 insertions(+)
---
base-commit: f3e6330d7fe42b204af05a2dbc68b379e0ad179e
change-id: 20260408-ipq9650_soc_ids-597ecc1aef1f
Best regards,
--
Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v2 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
From: Konrad Dybcio @ 2026-04-08 9:57 UTC (permalink / raw)
To: jsandom, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260407-rb5gen2-dts-v2-5-d0c7f447ee73@axon.com>
On 4/7/26 5:46 PM, Joe Sandom via B4 Relay wrote:
> From: Joe Sandom <jsandom@axon.com>
>
> The RB5gen2 is an embedded development platform for the
> QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550).
[...]
> + /* Lontium LT9611UXC fails FW upgrade and has timeouts with geni-i2c */
> + /* Workaround is to use bit-banged I2C */
Interesting.. I was under the impression that it was only an issue on
RB1 and RB2 boards.. perhaps we're missing some magic register write..
[...]
> + pinctrl-names = "default";
> + pinctrl-0 = <&wlan_en>, <&bt_default>, <&sw_ctrl_default>,
> + <&pmk8550_sleep_clk>;
nit: let's keep the order of
property-n
property-names
file-wide
[...]
> +&sdhc_2 {
> + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
> + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
> + pinctrl-names = "default", "sleep";
> +
> + vmmc-supply = <&vreg_l9b_2p9>;
> + vqmmc-supply = <&vreg_l8b_1p8>;
> +
> + max-sd-hs-hz = <37000000>;
Are you sure you want to overwrite that? The value in the SoC DTSI is
set to half a MHz higher
> +
> + no-sdio;
> + no-mmc;
> +
> + status = "okay";
> +};
> +
> +&sleep_clk {
> + clock-frequency = <32764>;
> +};
> +
> +&spi11 {
> + status = "okay";
> +
> + can@0 {
> + compatible = "microchip,mcp2518fd";
> + reg = <0>;
> + interrupts-extended = <&tlmm 55 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk40m>;
> + spi-max-frequency = <10000000>;
> + vdd-supply = <&vreg_l14b_3p2>;
> + xceiver-supply = <&vreg_l14b_3p2>;
It may be that for this chip to actually be able to communiate with devices
on the bus, you need to set the new 'microchip,xstbyen' property
see:
https://lore.kernel.org/linux-arm-msm/20260321135031.3107408-1-viken.dadhaniya@oss.qualcomm.com/
[...]
> +&tlmm {
> + gpio-reserved-ranges = <32 8>;
Would you happen to know what these pins are connected to, and if
so, add a comment (like in arch/arm64/boot/dts/qcom/x1-crd.dtsi)?
> +
> + bt_default: bt-default-state {
> + pins = "gpio81";
It would be best to keep these entries ordered by pin idx
> + function = "gpio";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +
> + sw_ctrl_default: sw-ctrl-default-state {
> + pins = "gpio82";
> + function = "gpio";
> + bias-pull-down;
> + };
> +
> + lt9611_irq_pin: lt9611-irq-state {
> + pins = "gpio40";
> + function = "gpio";
> + bias-disable;
> + };
> +
> + lt9611_rst_pin: lt9611-rst-state {
> + pins = "gpio7";
> + function = "gpio";
> + output-high;
You shouldn't need to assert the GPIO state in the pin entry node
- the driver should take care of that
> + };
> +
> + ntn0_en: ntn0-en-state {
> + pins = "gpio67";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + ntn1_en: ntn1-en-state {
> + pins = "gpio42";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + upd_1p05_en: upd-1p05-en-state {
> + pins = "gpio179";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
I don't know if pulling up an active-high pin is what you want
(there's some more occurences)
Konrad
^ permalink raw reply
* Re: [PATCH v4 1/2] arm64: dts: qcom: talos: Add GPR node, audio services, and MI2S1 TLMM pins
From: Le Qi @ 2026-04-08 9:48 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel, kernel, Konrad Dybcio
In-Reply-To: <acqAf9fCi8GPxjkM@baldur>
On 3/30/2026 9:57 PM, Bjorn Andersson wrote:
> On Tue, Mar 24, 2026 at 02:04:04PM +0800, Le Qi wrote:
>> This patch adds the Generic Pack Router (GPR) node together with
>
> Please avoid phrases such as "This patch". Start your commit message
> with a description of the problem or purpose of the patch.
>
>> Audio Process Manager (APM) and Proxy Resource Manager (PRM)
>> audio service nodes to the Talos device tree description.
>>
>> It also introduces MI2S1 pinctrl states for data0, data1, sck,
>> and ws lines, grouped into a single entry at the SoC-level DTSI
>> for better reuse and clarity.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Signed-off-by: Le Qi <le.qi@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/talos.dtsi | 54 +++++++++++++++++++++++++++++
>> 1 file changed, 54 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
>> index f69a40fb8e28..cd451a112573 100644
>> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
>> @@ -19,6 +19,7 @@
>> #include <dt-bindings/power/qcom-rpmpd.h>
>> #include <dt-bindings/power/qcom,rpmhpd.h>
>> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> +#include <dt-bindings/soc/qcom,gpr.h>
>
> Keep includes sorted alphabetically.
>
Will modify in next patch, thanks.
> Regards,
> Bjorn
>
>>
>> / {
>> interrupt-parent = <&intc>;
>> @@ -1553,6 +1554,20 @@ tlmm: pinctrl@3100000 {
>> #interrupt-cells = <2>;
>> wakeup-parent = <&pdc>;
>>
>> + mi2s1_pins: mi2s1-state {
>> + pins = "gpio108", "gpio109", "gpio110", "gpio111";
>> + function = "mi2s_1";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +
>> + mi2s_mclk: mi2s-mclk-state {
>> + pins = "gpio122";
>> + function = "mclk2";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +
>> qup_i2c1_data_clk: qup-i2c1-data-clk-state {
>> pins = "gpio4", "gpio5";
>> function = "qup0";
>> @@ -4696,6 +4711,45 @@ compute-cb@6 {
>> dma-coherent;
>> };
>> };
>> +
>> + gpr: gpr {
>> + compatible = "qcom,gpr";
>> + qcom,glink-channels = "adsp_apps";
>> + qcom,domain = <GPR_DOMAIN_ID_ADSP>;
>> + qcom,intents = <512 20>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + q6apm: service@1 {
>> + compatible = "qcom,q6apm";
>> + reg = <GPR_APM_MODULE_IID>;
>> + #sound-dai-cells = <0>;
>> + qcom,protection-domain = "avs/audio",
>> + "msm/adsp/audio_pd";
>> +
>> + q6apmbedai: bedais {
>> + compatible = "qcom,q6apm-lpass-dais";
>> + #sound-dai-cells = <1>;
>> + };
>> +
>> + q6apmdai: dais {
>> + compatible = "qcom,q6apm-dais";
>> + iommus = <&apps_smmu 0x1721 0x0>;
>> + };
>> + };
>> +
>> + q6prm: service@2 {
>> + compatible = "qcom,q6prm";
>> + reg = <GPR_PRM_MODULE_IID>;
>> + qcom,protection-domain = "avs/audio",
>> + "msm/adsp/audio_pd";
>> +
>> + q6prmcc: clock-controller {
>> + compatible = "qcom,q6prm-lpass-clocks";
>> + #clock-cells = <2>;
>> + };
>> + };
>> + };
>> };
>> };
>>
>> --
>> 2.34.1
>>
--
Thx and BRs,
Le Qi
^ permalink raw reply
* Re: [PATCH v4 2/2] arm64: dts: qcom: talos-evk: Add sound card support with DA7212 codec
From: Le Qi @ 2026-04-08 9:48 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel, kernel, Dmitry Baryshkov,
Konrad Dybcio
In-Reply-To: <78ebca6b-d8e2-4db2-8a34-ebdb6f401a5c@oss.qualcomm.com>
On 4/8/2026 5:42 PM, Le Qi wrote:
> On 3/30/2026 9:53 PM, Bjorn Andersson wrote:
>> On Tue, Mar 24, 2026 at 02:04:05PM +0800, Le Qi wrote:
>>> Add the sound card node for QCS615 Talos EVK with DA7212 codec
>>> connected over the Primary MI2S interface. The configuration enables
>>> headphone playback and headset microphone capture, both of which have
>>> been tested to work.
>>>
>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>> Signed-off-by: Le Qi <le.qi@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/talos-evk.dts | 65 ++++++++++++++++++++++++++
>>
>> There's no such file in the upstream tree. Please test on upstream and
>> resubmit once this is ready to be merged.
>>
>
> Hi Bjorn, this is merged. I will post new patch, thank you.
>
>> Regards,
>> Bjorn
>>
>>> 1 file changed, 65 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/talos-evk.dts b/arch/arm64/
>>> boot/dts/qcom/talos-evk.dts
>>> index af100e22beee..6352d614e288 100644
>>> --- a/arch/arm64/boot/dts/qcom/talos-evk.dts
>>> +++ b/arch/arm64/boot/dts/qcom/talos-evk.dts
>>> @@ -5,6 +5,7 @@
>>> /dts-v1/;
>>> #include "talos-evk-som.dtsi"
>>> +#include <dt-bindings/sound/qcom,q6afe.h>
>>> / {
>>> model = "Qualcomm QCS615 IQ 615 EVK";
>>> @@ -40,6 +41,46 @@ hdmi_con_out: endpoint {
>>> };
>>> };
>>> + sound {
>>> + compatible = "qcom,qcs615-sndcard";
>>> + model = "TALOS-EVK";
>>> +
>>> + pinctrl-0 = <&mi2s1_pins>, <&mi2s_mclk>;
>>> + pinctrl-names = "default";
>>> +
>>> + pri-mi2s-capture-dai-link {
>>> + link-name = "Primary MI2S Capture";
>>> +
>>> + codec {
>>> + sound-dai = <&codec_da7212>;
>>> + };
>>> +
>>> + cpu {
>>> + sound-dai = <&q6apmbedai PRIMARY_MI2S_TX>;
>>> + };
>>> +
>>> + platform {
>>> + sound-dai = <&q6apm>;
>>> + };
>>> + };
>>> +
>>> + pri-mi2s-playback-dai-link {
>>> + link-name = "Primary MI2S Playback";
>>> +
>>> + codec {
>>> + sound-dai = <&codec_da7212>;
>>> + };
>>> +
>>> + cpu {
>>> + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>;
>>> + };
>>> +
>>> + platform {
>>> + sound-dai = <&q6apm>;
>>> + };
>>> + };
>>> + };
>>> +
>>> vreg_v1p8_out: regulator-v1p8-out {
>>> compatible = "regulator-fixed";
>>> regulator-name = "vreg-v1p8-out";
>>> @@ -109,6 +150,19 @@ adv7535_out: endpoint {
>>> };
>>> };
>>> +&i2c5 {
>>> + status = "okay";
>>> +
>>> + codec_da7212: codec@1a {
>>> + compatible = "dlg,da7212";
>>> + reg = <0x1a>;
>>> + #sound-dai-cells = <0>;
>>> + VDDA-supply = <&vreg_v1p8_out>;
>>> + VDDIO-supply = <&vreg_v1p8_out>;
>>> + VDDMIC-supply = <&vreg_v3p3_out>;
>>> + };
>>> +};
>>> +
>>> &mdss_dsi0_out {
>>> remote-endpoint = <&adv7535_in>;
>>> data-lanes = <0 1 2 3>;
>>> @@ -124,6 +178,17 @@ &pon_resin {
>>> status = "okay";
>>> };
>>> +&q6apmbedai {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + dai@17 {
>>> + reg = <PRIMARY_MI2S_TX>;
>>> + clocks = <&q6prmcc LPASS_CLK_ID_MCLK_2
>>> LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>>> + clock-names = "mclk";
>>> + };
>>> +};
>>> +
>>> &sdhc_2 {
>>> pinctrl-0 = <&sdc2_state_on>;
>>> pinctrl-1 = <&sdc2_state_off>;
>>> --
>>> 2.34.1
>>>
>
>
--
Thx and BRs,
Le Qi
^ permalink raw reply
* Re: [PATCH 12/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: add LPASS CPU audio variant
From: Xilin Wu @ 2026-04-08 9:47 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Dmitry Baryshkov,
Liam Girdwood, Mark Brown, Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, linux-sound
In-Reply-To: <29a7dd01-7513-4fe5-8546-d57757b3b2d0@oss.qualcomm.com>
On 4/8/2026 5:06 PM, Konrad Dybcio wrote:
> On 4/7/26 5:20 PM, Xilin Wu wrote:
>> Add a qcs6490-radxa-dragon-q6a-lpass-cpu.dts variant for debugging and
>> bring-up of the host-controlled LPASS audio path on the Radxa Dragon
>> Q6A.
>>
>> This variant enables the LPASS blocks and codec macros needed by the
>> lpass-cpu driver, wires WCD9380 playback/capture and DisplayPort audio
>> to the LPASS CDC DMA and DP interfaces, and disables remoteproc_adsp so
>> that the audio hardware is owned directly by Linux.
>>
>> This DTB is an optional configuration for systems booted with the kernel
>> running at EL2, where direct CPU access to the LPASS hardware is
>> available. It is useful for users who need low-latency and fully
>> controllable audio.
>
> I believe on Chrome platforms it was done this way because at some point
> it was determined that they would specifically like not to use the DSP.
>
> I think this is more of a hack than anything else.. but at the end of the
> commit message you mention low latency - is the impact actually measurable?
>
Some of our users also specifically prefer not to use the DSP [1] :)
Based on their testing, the AudioReach/ADSP path imposes a minimum
scheduling interval of 10 ms, which is much higher than the 0.67 ms they
can get on a Raspberry Pi 5 with direct I2S/DMA.
Since the lpass-cpu setup works properly, I would not consider this a hack.
[1]
https://forum.radxa.com/t/dragon-q6a-lpaif-mi2s-registers-locked-by-qualcomm-trustzone-no-direct-low-latency-audio-access-possible/30592
> Konrad
>
--
Best regards,
Xilin Wu <sophon@radxa.com>
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: qcom: eliza: Add QCE crypto
From: Konrad Dybcio @ 2026-04-08 9:45 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thara Gopinath, Herbert Xu, David S. Miller,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, linux-crypto, devicetree, linux-kernel
In-Reply-To: <20260407-crypto-qcom-eliza-v1-2-40f61a1454a2@oss.qualcomm.com>
On 4/7/26 3:51 PM, Krzysztof Kozlowski wrote:
> Add nodes for the BAM DAM and QCE crypto engine.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* RE: [PATCH v4 net-next 11/14] net: dsa: netc: add phylink MAC operations
From: Wei Fang @ 2026-04-08 9:44 UTC (permalink / raw)
To: Jakub Kicinski
Cc: Claudiu Manoil, Vladimir Oltean, Clark Wang,
andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,
pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, f.fainelli@gmail.com, Frank Li,
chleroy@kernel.org, horms@kernel.org, linux@armlinux.org.uk,
andrew@lunn.ch, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev
In-Reply-To: <20260403011740.1795694-1-kuba@kernel.org>
> > +static void netc_port_mac_rx_enable(struct netc_port *np)
> > +{
> > + netc_port_rmw(np, NETC_POR, PCR_RXDIS, 0);
> > + netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_RX_EN,
> > + PM_CMD_CFG_RX_EN);
> > +}
>
> Pseudo ports (like the CPU port) bypass PMAC register accesses during
> graceful stop via is_netc_pseudo_port(). Should there be a similar check
> here, and in netc_port_set_mac_mode(), to prevent accessing physical MAC
> registers on pseudo ports?
netc_mac_port_rmw() has checked whether the port is pseudo MAC. See
below.
static void netc_mac_port_rmw(struct netc_port *np, u32 reg,
u32 mask, u32 val)
{
u32 old, new;
if (is_netc_pseudo_port(np))
return;
[...]
}
>
> Additionally, when np->caps.pmac is true, netc_port_mac_rx_graceful_stop()
> disables the preemption MAC via NETC_PM_CMD_CFG(1). Should this function
> re-enable it when bringing the link back up?
netc_mac_port_rmw() also set preemption MAC if the port supports preemtion.
static void netc_mac_port_rmw(struct netc_port *np, u32 reg,
u32 mask, u32 val)
{
[...]
if (np->caps.pmac)
netc_port_wr(np, reg + NETC_PMAC_OFFSET, new);
}
>
> > +static void netc_port_wait_rx_empty(struct netc_port *np, int mac)
> > +{
> > + u32 val;
> > +
> > + if (read_poll_timeout(netc_port_rd, val, val & PM_IEVENT_RX_EMPTY,
> > + 100, 10000, false, np, NETC_PM_IEVENT(mac)))
> > + dev_warn(np->switch_priv->dev,
> > + "MAC %d of swp%d RX is not empty\n", mac,
> > + np->dp->index);
> > +}
>
> Is NETC_PM_IEVENT a sticky write-1-to-clear register? If the RX FIFO had
> previously emptied during normal operation, could this bit already be set,
> causing read_poll_timeout() to return immediately without waiting?
NETC_PM_IEVENT[RX_EMPTY] is a read only bit. It will be cleared
if Rx FIFO not empty or Rx packet receive in process. And it will be
set if Rx FIFO is empty and no Rx packet receive in process.
>
> > +static void netc_port_mac_rx_graceful_stop(struct netc_port *np)
> > +{
> > + u32 val;
> > +
> > + if (is_netc_pseudo_port(np))
> > + goto check_rx_busy;
> > +
> > + if (np->caps.pmac) {
> > + netc_port_rmw(np, NETC_PM_CMD_CFG(1), PM_CMD_CFG_RX_EN,
> 0);
> > + netc_port_wait_rx_empty(np, 1);
> > + }
> > +
> > + netc_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_RX_EN, 0);
> > + netc_port_wait_rx_empty(np, 0);
> > +
> > +check_rx_busy:
> > + if (read_poll_timeout(netc_port_rd, val, !(val & PSR_RX_BUSY),
> > + 100, 10000, false, np, NETC_PSR))
> > + dev_warn(np->switch_priv->dev, "swp%d RX is busy\n",
> > + np->dp->index);
> > +
> > + netc_port_rmw(np, NETC_POR, PCR_RXDIS, PCR_RXDIS);
> > +}
>
> For pseudo ports, the code jumps directly to check_rx_busy and polls for
> PSR_RX_BUSY to clear. Since PCR_RXDIS is only set after the polling
> completes, will the RX pipeline continue accepting traffic and cause this
> poll to always timeout on an active link?
For the pseudo ports, no need to check the PSR_RX_BUSY bit, only need
to set PCR_RXDIS bit to discard RX packets. I will improve it.
>
> > +static void netc_mac_link_up(struct phylink_config *config,
> > + struct phy_device *phy, unsigned int mode,
> > + phy_interface_t interface, int speed,
> > + int duplex, bool tx_pause, bool rx_pause)
> > +{
> > + struct dsa_port *dp = dsa_phylink_to_port(config);
> > + struct netc_port *np;
> > +
> > + np = NETC_PORT(dp->ds, dp->index);
> > + netc_port_set_speed(np, speed);
> > +
> > + if (phy_interface_mode_is_rgmii(interface))
> > + netc_port_set_rgmii_mac(np, speed, duplex);
> > +
> > + if (interface == PHY_INTERFACE_MODE_RMII ||
> > + interface == PHY_INTERFACE_MODE_REVMII ||
> > + interface == PHY_INTERFACE_MODE_MII)
> > + netc_port_set_rmii_mii_mac(np, speed, duplex);
> > +
> > + netc_port_mac_rx_enable(np);
> > +}
>
> The callback imx94_switch_phylink_get_caps() advertises MAC_ASYM_PAUSE
> and
> MAC_SYM_PAUSE capabilities. Is it expected that tx_pause and rx_pause are
> ignored here? If flow control is implemented in a subsequent patch, should
> the advertisement be deferred until then?
Okay, I will move the advertisement to the subsequent patch.
^ permalink raw reply
* Re: [PATCH v4 2/2] arch: arm64: boot: dts: qcom: add IMEM and PIL regions for glymur
From: Konrad Dybcio @ 2026-04-08 9:42 UTC (permalink / raw)
To: Ananthu C V, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: devicetree, linux-kernel, linux-arm-msm
In-Reply-To: <20260327-glymur-imem-v4-2-8fe0f20ad9fd@oss.qualcomm.com>
On 3/27/26 11:24 AM, Ananthu C V wrote:
> Add an IMEM on glymur which falls back to mmio-sram and define the
> PIL relocation info region as its child, for post mortem tools to
> locate the loaded remoteprocs.
>
> Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 4886e87ebd49..21ae05f0ee17 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -6457,6 +6457,22 @@ rx-pins {
> };
> };
>
> + sram@14680000 {
> + compatible = "qcom,glymur-imem", "mmio-sram";
> + reg = <0x0 0x14680000 0x0 0x1000>;
> + ranges = <0 0 0x14680000 0x1000>;
size=0x2c_000
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v2 24/24] arm64: dts: renesas: r9a09g047e57-smarc: add DA7212 audio codec support
From: Geert Uytterhoeven @ 2026-04-08 9:41 UTC (permalink / raw)
To: John Madieu
Cc: Kuninori Morimoto, Vinod Koul, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Michael Turquette, Stephen Boyd,
Conor Dooley, Frank Li, Liam Girdwood, Magnus Damm,
Thomas Gleixner, Jaroslav Kysela, Takashi Iwai, Philipp Zabel,
Claudiu Beznea, Biju Das, Fabrizio Castro, Lad Prabhakar,
John Madieu, linux-renesas-soc, linux-clk, devicetree,
linux-kernel, dmaengine, linux-sound
In-Reply-To: <20260402090524.9137-25-john.madieu.xa@bp.renesas.com>
Hi John,
On Thu, 2 Apr 2026 at 11:10, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> RZ/G3E SMARC board has a DA7212 audio codec connected via I2C1 for
> sound input/output using SSI3/SSI4 where:
>
> - The codec receives its master clock from the Versa3 clock
> generator present on the SoM
> - SSI4 shares clock pins with SSI3 to provide a separate data
> line for full-duplex audio capture.
>
> Enable audio support on RZ/G3E SMARC2 EVK boards with a DA7212 audio codec.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> @@ -280,6 +358,42 @@ &sdhi1 {
> vqmmc-supply = <&vqmmc_sd1_pvdd>;
> };
>
> +&snd_rzg3e {
Please preserve sort order (alphabetical, by label).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 02/24] clk: renesas: r9a09g047: Add audio clock and reset support
From: Geert Uytterhoeven @ 2026-04-08 9:38 UTC (permalink / raw)
To: John Madieu
Cc: Geert Uytterhoeven, Kuninori Morimoto, Vinod Koul, Mark Brown,
Rob Herring, Krzysztof Kozlowski, Michael Turquette, Stephen Boyd,
Conor Dooley, Frank Li, Liam Girdwood, Magnus Damm,
Thomas Gleixner, Jaroslav Kysela, Takashi Iwai, Philipp Zabel,
Claudiu Beznea, Biju Das, Fabrizio Castro, Lad Prabhakar,
John Madieu, linux-renesas-soc, linux-clk, devicetree,
linux-kernel, dmaengine, linux-sound
In-Reply-To: <20260402090524.9137-3-john.madieu.xa@bp.renesas.com>
Hi John,
On Thu, 2 Apr 2026 at 11:07, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> Add clock and reset entries for audio-related modules on the RZ/G3E SoC.
>
> Target modules are:
> - SSIU (Serial Sound Interface Unit) with SSI ch0-ch9
> - SCU (Sampling Rate Converter Unit) with SRC ch0-ch9, DVC ch0-ch1,
> CTU/MIX ch0-ch1
> - ADMAC (Audio DMA Controller)
> - ADG (Audio Clock Generator) with divider input clocks and audio
> master clock outputs
>
> While at it, reorder plldty_div16 to group it with other plldty fixed
> dividers.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -460,6 +483,96 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> BUS_MSTOP(3, BIT(4))),
> DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
> BUS_MSTOP(2, BIT(15))),
> + DEF_MOD("ssif_clk", CLK_PLLCLN_DIV8, 15, 5, 7, 21,
Please preserve sort order (by _onindex, _onbit);
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> + DEF_MOD("scu_clk", CLK_PLLCLN_DIV8, 15, 6, 7, 22,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("scu_clkx2", CLK_PLLCLN_DIV4, 15, 7, 7, 23,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("admac_clk", CLK_PLLCLN_DIV8, 15, 8, 7, 24,
> + BUS_MSTOP(2, BIT(5))),
> + DEF_MOD("adg_clks1", CLK_PLLCLN_DIV8, 15, 9, 7, 25,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_clk_200m", CLK_PLLCLN_DIV8, 15, 10, 7, 26,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_audio_clka", CLK_AUDIO_CLKA, 15, 11, 7, 27,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_audio_clkb", CLK_AUDIO_CLKB, 15, 12, 7, 28,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_audio_clkc", CLK_AUDIO_CLKC, 15, 13, 7, 29,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_ssi0_clk", CLK_PLLCLN_DIV8, 22, 0, -1, -1,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_ssi1_clk", CLK_PLLCLN_DIV8, 22, 1, -1, -1,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_ssi2_clk", CLK_PLLCLN_DIV8, 22, 2, -1, -1,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_ssi3_clk", CLK_PLLCLN_DIV8, 22, 3, -1, -1,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_ssi4_clk", CLK_PLLCLN_DIV8, 22, 4, -1, -1,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_ssi5_clk", CLK_PLLCLN_DIV8, 22, 5, -1, -1,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_ssi6_clk", CLK_PLLCLN_DIV8, 22, 6, -1, -1,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_ssi7_clk", CLK_PLLCLN_DIV8, 22, 7, -1, -1,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_ssi8_clk", CLK_PLLCLN_DIV8, 22, 8, -1, -1,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("adg_ssi9_clk", CLK_PLLCLN_DIV8, 22, 9, -1, -1,
> + BUS_MSTOP(2, BIT(2))),
> + DEF_MOD("dvc0_clk", CLK_PLLCLN_DIV8, 23, 0, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("dvc1_clk", CLK_PLLCLN_DIV8, 23, 1, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("ctu0_mix0_clk", CLK_PLLCLN_DIV8, 23, 2, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("ctu1_mix1_clk", CLK_PLLCLN_DIV8, 23, 3, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("src0_clk", CLK_PLLCLN_DIV8, 23, 4, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("src1_clk", CLK_PLLCLN_DIV8, 23, 5, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("src2_clk", CLK_PLLCLN_DIV8, 23, 6, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("src3_clk", CLK_PLLCLN_DIV8, 23, 7, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("src4_clk", CLK_PLLCLN_DIV8, 23, 8, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("src5_clk", CLK_PLLCLN_DIV8, 23, 9, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("src6_clk", CLK_PLLCLN_DIV8, 23, 10, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("src7_clk", CLK_PLLCLN_DIV8, 23, 11, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("src8_clk", CLK_PLLCLN_DIV8, 23, 12, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("src9_clk", CLK_PLLCLN_DIV8, 23, 13, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("scu_supply_clk", CLK_PLLCLN_DIV8, 23, 14, -1, -1,
> + BUS_MSTOP(2, BIT(0) | BIT(1))),
> + DEF_MOD("ssif_supply_clk", CLK_PLLCLN_DIV8, 24, 0, -1, -1,
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> + DEF_MOD("ssi0_clk", CLK_PLLCLN_DIV8, 24, 1, -1, -1,
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> + DEF_MOD("ssi1_clk", CLK_PLLCLN_DIV8, 24, 2, -1, -1,
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> + DEF_MOD("ssi2_clk", CLK_PLLCLN_DIV8, 24, 3, -1, -1,
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> + DEF_MOD("ssi3_clk", CLK_PLLCLN_DIV8, 24, 4, -1, -1,
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> + DEF_MOD("ssi4_clk", CLK_PLLCLN_DIV8, 24, 5, -1, -1,
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> + DEF_MOD("ssi5_clk", CLK_PLLCLN_DIV8, 24, 6, -1, -1,
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> + DEF_MOD("ssi6_clk", CLK_PLLCLN_DIV8, 24, 7, -1, -1,
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> + DEF_MOD("ssi7_clk", CLK_PLLCLN_DIV8, 24, 8, -1, -1,
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> + DEF_MOD("ssi8_clk", CLK_PLLCLN_DIV8, 24, 9, -1, -1,
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> + DEF_MOD("ssi9_clk", CLK_PLLCLN_DIV8, 24, 10, -1, -1,
> + BUS_MSTOP(2, BIT(3) | BIT(4))),
> };
>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
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